1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
82 * [l0] ll = 0 (.128, .lz)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
172 #include "compiler.h"
176 #include <inttypes.h>
180 #include "assemble.h"
186 * Matching errors. These should be sorted so that more specific
187 * errors come later in the sequence.
198 * Matching success; the conditional ones first
200 MOK_JUMP, /* Matching OK but needs jmp_match() */
201 MOK_GOOD /* Matching unconditionally OK */
205 enum ea_type type; /* what kind of EA is this? */
206 int sib_present; /* is a SIB byte necessary? */
207 int bytes; /* # of bytes of offset needed */
208 int size; /* lazy - this is sib+bytes+1 */
209 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
210 int8_t disp8; /* compressed displacement for EVEX */
213 #define GEN_SIB(scale, index, base) \
214 (((scale) << 6) | ((index) << 3) | ((base)))
216 #define GEN_MODRM(mod, reg, rm) \
217 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
219 static iflags_t cpu; /* cpu level received from nasm.c */
220 static efunc errfunc;
221 static struct ofmt *outfmt;
222 static ListGen *list;
224 static int64_t calcsize(int32_t, int64_t, int, insn *,
225 const struct itemplate *);
226 static void gencode(int32_t segment, int64_t offset, int bits,
227 insn * ins, const struct itemplate *temp,
229 static enum match_result find_match(const struct itemplate **tempp,
231 int32_t segment, int64_t offset, int bits);
232 static enum match_result matches(const struct itemplate *, insn *, int bits);
233 static opflags_t regflag(const operand *);
234 static int32_t regval(const operand *);
235 static int rexflags(int, opflags_t, int);
236 static int op_rexflags(const operand *, int);
237 static int op_evexflags(const operand *, int, uint8_t);
238 static void add_asp(insn *, int);
240 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
242 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
244 return ins->prefixes[pos] == prefix;
247 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
249 if (ins->prefixes[pos])
250 errfunc(ERR_NONFATAL, "invalid %s prefix",
251 prefix_name(ins->prefixes[pos]));
254 static const char *size_name(int size)
278 static void warn_overflow(int pass, int size)
280 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
281 "%s data exceeds bounds", size_name(size));
284 static void warn_overflow_const(int64_t data, int size)
286 if (overflow_general(data, size))
287 warn_overflow(ERR_PASS1, size);
290 static void warn_overflow_opd(const struct operand *o, int size)
292 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
293 if (overflow_general(o->offset, size))
294 warn_overflow(ERR_PASS2, size);
299 * This routine wrappers the real output format's output routine,
300 * in order to pass a copy of the data off to the listing file
301 * generator at the same time.
303 static void out(int64_t offset, int32_t segto, const void *data,
304 enum out_type type, uint64_t size,
305 int32_t segment, int32_t wrt)
307 static int32_t lineno = 0; /* static!!! */
308 static char *lnfname = NULL;
311 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
313 * This is a non-relocated address, and we're going to
314 * convert it into RAWDATA format.
319 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
323 WRITEADDR(q, *(int64_t *)data, size);
328 list->output(offset, data, type, size);
331 * this call to src_get determines when we call the
332 * debug-format-specific "linenum" function
333 * it updates lineno and lnfname to the current values
334 * returning 0 if "same as last time", -2 if lnfname
335 * changed, and the amount by which lineno changed,
336 * if it did. thus, these variables must be static
339 if (src_get(&lineno, &lnfname))
340 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
342 outfmt->output(segto, data, type, size, segment, wrt);
345 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
347 if (opx->segment != NO_SEG) {
348 uint64_t data = opx->offset;
349 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
351 uint8_t byte = opx->offset;
352 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
356 static bool jmp_match(int32_t segment, int64_t offset, int bits,
357 insn * ins, const struct itemplate *temp)
360 const uint8_t *code = temp->code;
363 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
367 if (optimizing < 0 && c == 0371)
370 isize = calcsize(segment, offset, bits, ins, temp);
372 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
373 /* Be optimistic in pass 1 */
376 if (ins->oprs[0].segment != segment)
379 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
380 return (isize >= -128 && isize <= 127); /* is it byte size? */
383 int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp,
384 insn * instruction, struct ofmt *output, efunc error,
387 const struct itemplate *temp;
392 int64_t start = offset;
393 int64_t wsize; /* size for DB etc. */
395 errfunc = error; /* to pass to other functions */
397 outfmt = output; /* likewise */
398 list = listgen; /* and again */
400 wsize = idata_bytes(instruction->opcode);
406 int32_t t = instruction->times;
409 "instruction->times < 0 (%ld) in assemble()", t);
411 while (t--) { /* repeat TIMES times */
412 list_for_each(e, instruction->eops) {
413 if (e->type == EOT_DB_NUMBER) {
415 errfunc(ERR_NONFATAL,
416 "integer supplied to a DT, DO or DY"
419 out(offset, segment, &e->offset,
420 OUT_ADDRESS, wsize, e->segment, e->wrt);
423 } else if (e->type == EOT_DB_STRING ||
424 e->type == EOT_DB_STRING_FREE) {
427 out(offset, segment, e->stringval,
428 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
429 align = e->stringlen % wsize;
432 align = wsize - align;
433 out(offset, segment, zero_buffer,
434 OUT_RAWDATA, align, NO_SEG, NO_SEG);
436 offset += e->stringlen + align;
439 if (t > 0 && t == instruction->times - 1) {
441 * Dummy call to list->output to give the offset to the
444 list->output(offset, NULL, OUT_RAWDATA, 0);
445 list->uplevel(LIST_TIMES);
448 if (instruction->times > 1)
449 list->downlevel(LIST_TIMES);
450 return offset - start;
453 if (instruction->opcode == I_INCBIN) {
454 const char *fname = instruction->eops->stringval;
457 fp = fopen(fname, "rb");
459 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
461 } else if (fseek(fp, 0L, SEEK_END) < 0) {
462 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
466 static char buf[4096];
467 size_t t = instruction->times;
472 if (instruction->eops->next) {
473 base = instruction->eops->next->offset;
475 if (instruction->eops->next->next &&
476 len > (size_t)instruction->eops->next->next->offset)
477 len = (size_t)instruction->eops->next->next->offset;
480 * Dummy call to list->output to give the offset to the
483 list->output(offset, NULL, OUT_RAWDATA, 0);
484 list->uplevel(LIST_INCBIN);
488 fseek(fp, base, SEEK_SET);
492 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
495 * This shouldn't happen unless the file
496 * actually changes while we are reading
500 "`incbin': unexpected EOF while"
501 " reading file `%s'", fname);
502 t = 0; /* Try to exit cleanly */
505 out(offset, segment, buf, OUT_RAWDATA, m,
510 list->downlevel(LIST_INCBIN);
511 if (instruction->times > 1) {
513 * Dummy call to list->output to give the offset to the
516 list->output(offset, NULL, OUT_RAWDATA, 0);
517 list->uplevel(LIST_TIMES);
518 list->downlevel(LIST_TIMES);
521 return instruction->times * len;
523 return 0; /* if we're here, there's an error */
526 /* Check to see if we need an address-size prefix */
527 add_asp(instruction, bits);
529 m = find_match(&temp, instruction, segment, offset, bits);
533 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
534 itimes = instruction->times;
535 if (insn_size < 0) /* shouldn't be, on pass two */
536 error(ERR_PANIC, "errors made it through from pass one");
539 for (j = 0; j < MAXPREFIX; j++) {
541 switch (instruction->prefixes[j]) {
562 error(ERR_WARNING | ERR_PASS2,
563 "cs segment base generated, but will be ignored in 64-bit mode");
569 error(ERR_WARNING | ERR_PASS2,
570 "ds segment base generated, but will be ignored in 64-bit mode");
576 error(ERR_WARNING | ERR_PASS2,
577 "es segment base generated, but will be ignored in 64-bit mode");
589 error(ERR_WARNING | ERR_PASS2,
590 "ss segment base generated, but will be ignored in 64-bit mode");
597 "segr6 and segr7 cannot be used as prefixes");
602 "16-bit addressing is not supported "
604 } else if (bits != 16)
614 "64-bit addressing is only supported "
638 error(ERR_PANIC, "invalid instruction prefix");
641 out(offset, segment, &c, OUT_RAWDATA, 1,
646 insn_end = offset + insn_size;
647 gencode(segment, offset, bits, instruction,
650 if (itimes > 0 && itimes == instruction->times - 1) {
652 * Dummy call to list->output to give the offset to the
655 list->output(offset, NULL, OUT_RAWDATA, 0);
656 list->uplevel(LIST_TIMES);
659 if (instruction->times > 1)
660 list->downlevel(LIST_TIMES);
661 return offset - start;
665 case MERR_OPSIZEMISSING:
666 error(ERR_NONFATAL, "operation size not specified");
668 case MERR_OPSIZEMISMATCH:
669 error(ERR_NONFATAL, "mismatch in operand sizes");
672 error(ERR_NONFATAL, "no instruction for this cpu level");
675 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
680 "invalid combination of opcode and operands");
687 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp,
688 insn * instruction, efunc error)
690 const struct itemplate *temp;
693 errfunc = error; /* to pass to other functions */
696 if (instruction->opcode == I_none)
699 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
700 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
701 instruction->opcode == I_DT || instruction->opcode == I_DO ||
702 instruction->opcode == I_DY) {
704 int32_t isize, osize, wsize;
707 wsize = idata_bytes(instruction->opcode);
709 list_for_each(e, instruction->eops) {
713 if (e->type == EOT_DB_NUMBER) {
715 warn_overflow_const(e->offset, wsize);
716 } else if (e->type == EOT_DB_STRING ||
717 e->type == EOT_DB_STRING_FREE)
718 osize = e->stringlen;
720 align = (-osize) % wsize;
723 isize += osize + align;
725 return isize * instruction->times;
728 if (instruction->opcode == I_INCBIN) {
729 const char *fname = instruction->eops->stringval;
734 fp = fopen(fname, "rb");
736 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
738 else if (fseek(fp, 0L, SEEK_END) < 0)
739 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
743 if (instruction->eops->next) {
744 len -= instruction->eops->next->offset;
745 if (instruction->eops->next->next &&
746 len > (size_t)instruction->eops->next->next->offset) {
747 len = (size_t)instruction->eops->next->next->offset;
750 val = instruction->times * len;
757 /* Check to see if we need an address-size prefix */
758 add_asp(instruction, bits);
760 m = find_match(&temp, instruction, segment, offset, bits);
762 /* we've matched an instruction. */
766 isize = calcsize(segment, offset, bits, instruction, temp);
769 for (j = 0; j < MAXPREFIX; j++) {
770 switch (instruction->prefixes[j]) {
796 return isize * instruction->times;
798 return -1; /* didn't match any instruction */
802 static void bad_hle_warn(const insn * ins, uint8_t hleok)
804 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
805 enum whatwarn { w_none, w_lock, w_inval } ww;
806 static const enum whatwarn warn[2][4] =
808 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
809 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
813 n = (unsigned int)rep_pfx - P_XACQUIRE;
815 return; /* Not XACQUIRE/XRELEASE */
818 if (!is_class(MEMORY, ins->oprs[0].type))
819 ww = w_inval; /* HLE requires operand 0 to be memory */
826 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
827 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
828 "%s with this instruction requires lock",
829 prefix_name(rep_pfx));
834 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
835 "%s invalid with this instruction",
836 prefix_name(rep_pfx));
841 /* Common construct */
842 #define case3(x) case (x): case (x)+1: case (x)+2
843 #define case4(x) case3(x): case (x)+3
845 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
846 insn * ins, const struct itemplate *temp)
848 const uint8_t *codes = temp->code;
857 bool lockcheck = true;
858 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
860 ins->rex = 0; /* Ensure REX is reset */
861 eat = EA_SCALAR; /* Expect a scalar EA */
862 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
864 if (ins->prefixes[PPS_OSIZE] == P_O64)
867 (void)segment; /* Don't warn that this parameter is unused */
868 (void)offset; /* Don't warn that this parameter is unused */
872 op1 = (c & 3) + ((opex & 1) << 2);
873 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
874 opx = &ins->oprs[op1];
875 opex = 0; /* For the next iteration */
879 codes += c, length += c;
888 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
893 /* this is an index reg of MIB operand */
894 mib_index = opx->basereg;
907 if (opx->type & (BITS16 | BITS32 | BITS64))
908 length += (opx->type & BITS16) ? 2 : 4;
910 length += (bits == 16) ? 2 : 4;
918 length += ins->addr_size >> 3;
926 length += 8; /* MOV reg64/imm */
934 if (opx->type & (BITS16 | BITS32 | BITS64))
935 length += (opx->type & BITS16) ? 2 : 4;
937 length += (bits == 16) ? 2 : 4;
960 ins->vexreg = regval(opx);
961 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
962 ins->vex_cm = *codes++;
963 ins->vex_wlp = *codes++;
964 ins->evex_tuple = (*codes++ - 0300);
970 ins->vex_cm = *codes++;
971 ins->vex_wlp = *codes++;
972 ins->evex_tuple = (*codes++ - 0300);
981 ins->vexreg = regval(opx);
982 ins->vex_cm = *codes++;
983 ins->vex_wlp = *codes++;
989 ins->vex_cm = *codes++;
990 ins->vex_wlp = *codes++;
1007 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1011 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1018 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1019 has_prefix(ins, PPS_ASIZE, P_A32))
1028 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1032 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1034 ins->prefixes[PPS_OSIZE] = P_O16;
1040 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1044 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1046 ins->prefixes[PPS_OSIZE] = P_O32;
1088 if (!ins->prefixes[PPS_REP])
1089 ins->prefixes[PPS_REP] = P_REP;
1093 if (!ins->prefixes[PPS_REP])
1094 ins->prefixes[PPS_REP] = P_REPNE;
1098 if (ins->oprs[0].segment != NO_SEG)
1099 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1100 " quantity of BSS space");
1102 length += ins->oprs[0].offset;
1106 if (!ins->prefixes[PPS_WAIT])
1107 ins->prefixes[PPS_WAIT] = P_WAIT;
1162 struct operand *opy = &ins->oprs[op2];
1163 struct operand *op_er_sae;
1165 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1168 /* pick rfield from operand b (opx) */
1169 rflags = regflag(opx);
1170 rfield = nasm_regvals[opx->basereg];
1176 /* EVEX.b1 : evex_brerop contains the operand position */
1177 op_er_sae = (ins->evex_brerop >= 0 ?
1178 &ins->oprs[ins->evex_brerop] : NULL);
1180 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1182 ins->evex_p[2] |= EVEX_P2B;
1183 if (op_er_sae->decoflags & ER) {
1184 /* set EVEX.RC (rounding control) */
1185 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1189 /* set EVEX.L'L (vector length) */
1190 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1191 if (opy->decoflags & BRDCAST_MASK) {
1193 ins->evex_p[2] |= EVEX_P2B;
1198 * if a separate form of MIB (ICC style) is used,
1199 * the index reg info is merged into mem operand
1201 if (mib_index != R_none) {
1202 opy->indexreg = mib_index;
1204 opy->hintbase = mib_index;
1205 opy->hinttype = EAH_NOTBASE;
1209 * only for mib operands, make a single reg index [reg*1].
1210 * gas uses this form to explicitly denote index register.
1212 if ((temp->flags & IF_MIB) &&
1213 (opy->indexreg == -1 && opy->hintbase == opy->basereg &&
1214 opy->hinttype == EAH_NOTBASE)) {
1215 opy->indexreg = opy->basereg;
1220 if (process_ea(opy, &ea_data, bits,
1221 rfield, rflags, ins) != eat) {
1222 errfunc(ERR_NONFATAL, "invalid effective address");
1225 ins->rex |= ea_data.rex;
1226 length += ea_data.size;
1232 errfunc(ERR_PANIC, "internal instruction table corrupt"
1233 ": instruction code \\%o (0x%02X) given", c, c);
1238 ins->rex &= rex_mask;
1240 if (ins->rex & REX_NH) {
1241 if (ins->rex & REX_H) {
1242 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1245 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1248 if (ins->rex & (REX_V | REX_EV)) {
1249 int bad32 = REX_R|REX_W|REX_X|REX_B;
1251 if (ins->rex & REX_H) {
1252 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1255 switch (ins->vex_wlp & 060) {
1269 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1270 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1272 } else if (!(ins->rex & REX_EV) &&
1273 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1274 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1277 if (ins->rex & REX_EV)
1279 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1283 } else if (ins->rex & REX_REAL) {
1284 if (ins->rex & REX_H) {
1285 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1287 } else if (bits == 64) {
1289 } else if ((ins->rex & REX_L) &&
1290 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1293 assert_no_prefix(ins, PPS_LOCK);
1294 lockcheck = false; /* Already errored, no need for warning */
1297 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1302 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1303 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1304 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1305 "instruction is not lockable");
1308 bad_hle_warn(ins, hleok);
1313 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1316 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1317 ins->rex = (ins->rex & REX_REAL) | REX_P;
1318 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1327 static void gencode(int32_t segment, int64_t offset, int bits,
1328 insn * ins, const struct itemplate *temp,
1336 struct operand *opx;
1337 const uint8_t *codes = temp->code;
1339 enum ea_type eat = EA_SCALAR;
1343 op1 = (c & 3) + ((opex & 1) << 2);
1344 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1345 opx = &ins->oprs[op1];
1346 opex = 0; /* For the next iteration */
1353 offset += emit_rex(ins, segment, offset, bits);
1354 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1366 offset += emit_rex(ins, segment, offset, bits);
1367 bytes[0] = *codes++ + (regval(opx) & 7);
1368 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1376 if (opx->offset < -256 || opx->offset > 255) {
1377 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1378 "byte value exceeds bounds");
1380 out_imm8(offset, segment, opx);
1385 if (opx->offset < 0 || opx->offset > 255)
1386 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1387 "unsigned byte value exceeds bounds");
1388 out_imm8(offset, segment, opx);
1393 warn_overflow_opd(opx, 2);
1395 out(offset, segment, &data, OUT_ADDRESS, 2,
1396 opx->segment, opx->wrt);
1401 if (opx->type & (BITS16 | BITS32))
1402 size = (opx->type & BITS16) ? 2 : 4;
1404 size = (bits == 16) ? 2 : 4;
1405 warn_overflow_opd(opx, size);
1407 out(offset, segment, &data, OUT_ADDRESS, size,
1408 opx->segment, opx->wrt);
1413 warn_overflow_opd(opx, 4);
1415 out(offset, segment, &data, OUT_ADDRESS, 4,
1416 opx->segment, opx->wrt);
1422 size = ins->addr_size >> 3;
1423 warn_overflow_opd(opx, size);
1424 out(offset, segment, &data, OUT_ADDRESS, size,
1425 opx->segment, opx->wrt);
1430 if (opx->segment != segment) {
1432 out(offset, segment, &data,
1433 OUT_REL1ADR, insn_end - offset,
1434 opx->segment, opx->wrt);
1436 data = opx->offset - insn_end;
1437 if (data > 127 || data < -128)
1438 errfunc(ERR_NONFATAL, "short jump is out of range");
1439 out(offset, segment, &data,
1440 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1446 data = (int64_t)opx->offset;
1447 out(offset, segment, &data, OUT_ADDRESS, 8,
1448 opx->segment, opx->wrt);
1453 if (opx->segment != segment) {
1455 out(offset, segment, &data,
1456 OUT_REL2ADR, insn_end - offset,
1457 opx->segment, opx->wrt);
1459 data = opx->offset - insn_end;
1460 out(offset, segment, &data,
1461 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1467 if (opx->type & (BITS16 | BITS32 | BITS64))
1468 size = (opx->type & BITS16) ? 2 : 4;
1470 size = (bits == 16) ? 2 : 4;
1471 if (opx->segment != segment) {
1473 out(offset, segment, &data,
1474 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1475 insn_end - offset, opx->segment, opx->wrt);
1477 data = opx->offset - insn_end;
1478 out(offset, segment, &data,
1479 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1485 if (opx->segment != segment) {
1487 out(offset, segment, &data,
1488 OUT_REL4ADR, insn_end - offset,
1489 opx->segment, opx->wrt);
1491 data = opx->offset - insn_end;
1492 out(offset, segment, &data,
1493 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1499 if (opx->segment == NO_SEG)
1500 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1503 out(offset, segment, &data, OUT_ADDRESS, 2,
1504 outfmt->segbase(1 + opx->segment),
1511 opx = &ins->oprs[c >> 3];
1512 bytes[0] = nasm_regvals[opx->basereg] << 4;
1513 opx = &ins->oprs[c & 7];
1514 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1515 errfunc(ERR_NONFATAL,
1516 "non-absolute expression not permitted as argument %d",
1519 if (opx->offset & ~15) {
1520 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1521 "four-bit argument exceeds bounds");
1523 bytes[0] |= opx->offset & 15;
1525 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1531 opx = &ins->oprs[c >> 4];
1532 bytes[0] = nasm_regvals[opx->basereg] << 4;
1534 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1539 bytes[0] = nasm_regvals[opx->basereg] << 4;
1540 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1546 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1547 (int32_t)data != (int64_t)data) {
1548 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1549 "signed dword immediate exceeds bounds");
1551 out(offset, segment, &data, OUT_ADDRESS, 4,
1552 opx->segment, opx->wrt);
1559 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1560 EVEX_P2Z | EVEX_P2AAA, 2);
1561 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1563 /* EVEX.X can be set by either REX or EVEX for different reasons */
1564 bytes[1] = ((((ins->rex & 7) << 5) |
1565 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1567 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1568 ((~ins->vexreg & 15) << 3) |
1569 (1 << 2) | (ins->vex_wlp & 3);
1570 bytes[3] = ins->evex_p[2];
1571 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1578 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1579 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1580 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1581 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1582 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1583 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1587 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1588 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1589 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1604 if (ins->rex & REX_W)
1606 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1608 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1613 um = (uint64_t)2 << (s-1);
1616 if (uv > 127 && uv < (uint64_t)-128 &&
1617 (uv < um-128 || uv > um-1)) {
1618 /* If this wasn't explicitly byte-sized, warn as though we
1619 * had fallen through to the imm16/32/64 case.
1621 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1622 "%s value exceeds bounds",
1623 (opx->type & BITS8) ? "signed byte" :
1628 if (opx->segment != NO_SEG) {
1630 out(offset, segment, &data, OUT_ADDRESS, 1,
1631 opx->segment, opx->wrt);
1634 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1645 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1647 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1654 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1656 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1691 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1692 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1701 *bytes = c - 0332 + 0xF2;
1702 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1707 if (ins->rex & REX_R) {
1709 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1712 ins->rex &= ~(REX_L|REX_R);
1723 if (ins->oprs[0].segment != NO_SEG)
1724 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1726 int64_t size = ins->oprs[0].offset;
1728 out(offset, segment, NULL,
1729 OUT_RESERVE, size, NO_SEG, NO_SEG);
1742 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1752 *bytes = c - 0366 + 0x66;
1753 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1761 *bytes = bits == 16 ? 3 : 5;
1762 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1796 struct operand *opy = &ins->oprs[op2];
1799 /* pick rfield from operand b (opx) */
1800 rflags = regflag(opx);
1801 rfield = nasm_regvals[opx->basereg];
1803 /* rfield is constant */
1808 if (process_ea(opy, &ea_data, bits,
1809 rfield, rflags, ins) != eat)
1810 errfunc(ERR_NONFATAL, "invalid effective address");
1813 *p++ = ea_data.modrm;
1814 if (ea_data.sib_present)
1818 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1821 * Make sure the address gets the right offset in case
1822 * the line breaks in the .lst file (BR 1197827)
1827 switch (ea_data.bytes) {
1834 /* use compressed displacement, if available */
1835 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1838 if (opy->segment == segment) {
1840 if (overflow_signed(data, ea_data.bytes))
1841 warn_overflow(ERR_PASS2, ea_data.bytes);
1842 out(offset, segment, &data, OUT_ADDRESS,
1843 ea_data.bytes, NO_SEG, NO_SEG);
1845 /* overflow check in output/linker? */
1846 out(offset, segment, &data, OUT_REL4ADR,
1847 insn_end - offset, opy->segment, opy->wrt);
1850 if (overflow_general(data, ins->addr_size >> 3) ||
1851 signed_bits(data, ins->addr_size) !=
1852 signed_bits(data, ea_data.bytes * 8))
1853 warn_overflow(ERR_PASS2, ea_data.bytes);
1855 out(offset, segment, &data, OUT_ADDRESS,
1856 ea_data.bytes, opy->segment, opy->wrt);
1862 "Invalid amount of bytes (%d) for offset?!",
1871 errfunc(ERR_PANIC, "internal instruction table corrupt"
1872 ": instruction code \\%o (0x%02X) given", c, c);
1878 static opflags_t regflag(const operand * o)
1880 if (!is_register(o->basereg))
1881 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1882 return nasm_reg_flags[o->basereg];
1885 static int32_t regval(const operand * o)
1887 if (!is_register(o->basereg))
1888 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1889 return nasm_regvals[o->basereg];
1892 static int op_rexflags(const operand * o, int mask)
1897 if (!is_register(o->basereg))
1898 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1900 flags = nasm_reg_flags[o->basereg];
1901 val = nasm_regvals[o->basereg];
1903 return rexflags(val, flags, mask);
1906 static int rexflags(int val, opflags_t flags, int mask)
1910 if (val >= 0 && (val & 8))
1911 rex |= REX_B|REX_X|REX_R;
1914 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1916 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1922 static int evexflags(int val, decoflags_t deco,
1923 int mask, uint8_t byte)
1929 if (val >= 0 && (val & 16))
1930 evex |= (EVEX_P0RP | EVEX_P0X);
1933 if (val >= 0 && (val & 16))
1937 if (deco & OPMASK_MASK)
1938 evex |= deco & EVEX_P2AAA;
1944 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1948 if (!is_register(o->basereg))
1949 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1951 val = nasm_regvals[o->basereg];
1953 return evexflags(val, o->decoflags, mask, byte);
1956 static enum match_result find_match(const struct itemplate **tempp,
1958 int32_t segment, int64_t offset, int bits)
1960 const struct itemplate *temp;
1961 enum match_result m, merr;
1962 opflags_t xsizeflags[MAX_OPERANDS];
1963 bool opsizemissing = false;
1964 int8_t broadcast = instruction->evex_brerop;
1967 /* broadcasting uses a different data element size */
1968 for (i = 0; i < instruction->operands; i++)
1970 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
1972 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1974 merr = MERR_INVALOP;
1976 for (temp = nasm_instructions[instruction->opcode];
1977 temp->opcode != I_none; temp++) {
1978 m = matches(temp, instruction, bits);
1979 if (m == MOK_JUMP) {
1980 if (jmp_match(segment, offset, bits, instruction, temp))
1984 } else if (m == MERR_OPSIZEMISSING &&
1985 (temp->flags & IF_SMASK) != IF_SX) {
1987 * Missing operand size and a candidate for fuzzy matching...
1989 for (i = 0; i < temp->operands; i++)
1991 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
1993 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1994 opsizemissing = true;
1998 if (merr == MOK_GOOD)
2002 /* No match, but see if we can get a fuzzy operand size match... */
2006 for (i = 0; i < instruction->operands; i++) {
2008 * We ignore extrinsic operand sizes on registers, so we should
2009 * never try to fuzzy-match on them. This also resolves the case
2010 * when we have e.g. "xmmrm128" in two different positions.
2012 if (is_class(REGISTER, instruction->oprs[i].type))
2015 /* This tests if xsizeflags[i] has more than one bit set */
2016 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2017 goto done; /* No luck */
2020 instruction->oprs[i].decoflags |= xsizeflags[i];
2022 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2025 /* Try matching again... */
2026 for (temp = nasm_instructions[instruction->opcode];
2027 temp->opcode != I_none; temp++) {
2028 m = matches(temp, instruction, bits);
2029 if (m == MOK_JUMP) {
2030 if (jmp_match(segment, offset, bits, instruction, temp))
2037 if (merr == MOK_GOOD)
2046 static enum match_result matches(const struct itemplate *itemp,
2047 insn *instruction, int bits)
2049 opflags_t size[MAX_OPERANDS], asize;
2050 bool opsizemissing = false;
2056 if (itemp->opcode != instruction->opcode)
2057 return MERR_INVALOP;
2060 * Count the operands
2062 if (itemp->operands != instruction->operands)
2063 return MERR_INVALOP;
2068 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2069 return MERR_INVALOP;
2072 * Check that no spurious colons or TOs are present
2074 for (i = 0; i < itemp->operands; i++)
2075 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2076 return MERR_INVALOP;
2079 * Process size flags
2081 switch (itemp->flags & IF_SMASK) {
2124 if (itemp->flags & IF_ARMASK) {
2125 /* S- flags only apply to a specific operand */
2126 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2127 memset(size, 0, sizeof size);
2130 /* S- flags apply to all operands */
2131 for (i = 0; i < MAX_OPERANDS; i++)
2136 * Check that the operand flags all match up,
2137 * it's a bit tricky so lets be verbose:
2139 * 1) Find out the size of operand. If instruction
2140 * doesn't have one specified -- we're trying to
2141 * guess it either from template (IF_S* flag) or
2144 * 2) If template operand do not match the instruction OR
2145 * template has an operand size specified AND this size differ
2146 * from which instruction has (perhaps we got it from code bits)
2148 * a) Check that only size of instruction and operand is differ
2149 * other characteristics do match
2150 * b) Perhaps it's a register specified in instruction so
2151 * for such a case we just mark that operand as "size
2152 * missing" and this will turn on fuzzy operand size
2153 * logic facility (handled by a caller)
2155 for (i = 0; i < itemp->operands; i++) {
2156 opflags_t type = instruction->oprs[i].type;
2157 decoflags_t deco = instruction->oprs[i].decoflags;
2158 if (!(type & SIZE_MASK))
2161 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2162 (itemp->deco[i] & deco) != deco) {
2163 return MERR_INVALOP;
2164 } else if ((itemp->opd[i] & SIZE_MASK) &&
2165 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2166 if (type & SIZE_MASK) {
2168 * when broadcasting, the element size depends on
2169 * the instruction type. decorator flag should match.
2171 #define MATCH_BRSZ(bits) (((type & SIZE_MASK) == BITS##bits) && \
2172 ((itemp->deco[i] & BRSIZE_MASK) == BR_BITS##bits))
2173 if (!((deco & BRDCAST_MASK) &&
2174 (MATCH_BRSZ(32) || MATCH_BRSZ(64)))) {
2175 return MERR_INVALOP;
2177 } else if (!is_class(REGISTER, type)) {
2179 * Note: we don't honor extrinsic operand sizes for registers,
2180 * so "missing operand size" for a register should be
2181 * considered a wildcard match rather than an error.
2183 opsizemissing = true;
2185 } else if (is_register(instruction->oprs[i].basereg) &&
2186 nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
2187 !(itemp->flags & IF_AVX512)) {
2188 return MERR_ENCMISMATCH;
2193 return MERR_OPSIZEMISSING;
2196 * Check operand sizes
2198 if (itemp->flags & (IF_SM | IF_SM2)) {
2199 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2200 for (i = 0; i < oprs; i++) {
2201 asize = itemp->opd[i] & SIZE_MASK;
2203 for (i = 0; i < oprs; i++)
2209 oprs = itemp->operands;
2212 for (i = 0; i < itemp->operands; i++) {
2213 if (!(itemp->opd[i] & SIZE_MASK) &&
2214 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2215 return MERR_OPSIZEMISMATCH;
2219 * Check template is okay at the set cpu level
2221 if (((itemp->flags & IF_PLEVEL) > cpu))
2225 * Verify the appropriate long mode flag.
2227 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2228 return MERR_BADMODE;
2231 * If we have a HLE prefix, look for the NOHLE flag
2233 if ((itemp->flags & IF_NOHLE) &&
2234 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2235 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2239 * Check if special handling needed for Jumps
2241 if ((itemp->code[0] & ~1) == 0370)
2245 * Check if BND prefix is allowed
2247 if ((IF_BND & ~itemp->flags) &&
2248 has_prefix(instruction, PPS_REP, P_BND))
2255 * Check if offset is a multiple of N with corresponding tuple type
2256 * if Disp8*N is available, compressed displacement is stored in compdisp
2258 static bool is_disp8n(operand *input, insn *ins, int8_t *compdisp)
2260 const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}},
2261 {{16, 32, 64}, {8, 8, 8}}};
2262 const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}};
2263 const uint8_t dup_n[VLMAX] = {8, 32, 64};
2265 bool evex_b = input->decoflags & BRDCAST_MASK;
2266 enum ttypes tuple = ins->evex_tuple;
2267 /* vex_wlp composed as [wwllpp] */
2268 enum vectlens vectlen = (ins->vex_wlp & 0x0c) >> 2;
2269 /* wig(=2) is treated as w0(=0) */
2270 bool evex_w = (ins->vex_wlp & 0x10) >> 4;
2271 int32_t off = input->offset;
2277 n = fv_n[evex_w][evex_b][vectlen];
2280 n = hv_n[evex_b][vectlen];
2284 /* 16, 32, 64 for VL 128, 256, 512 respectively*/
2285 n = 1 << (vectlen + 4);
2287 case T1S8: /* N = 1 */
2288 case T1S16: /* N = 2 */
2289 n = tuple - T1S8 + 1;
2292 /* N = 4 for 32bit, 8 for 64bit */
2297 /* N = 4 for 32bit, 8 for 64bit */
2298 n = (tuple == T1F32 ? 4 : 8);
2303 if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1))
2306 n = 1 << (tuple - T2 + evex_w + 3);
2311 n = 1 << (OVM - tuple + vectlen + 1);
2324 if (n && !(off & (n - 1))) {
2326 /* if it fits in Disp8 */
2327 if (disp8 >= -128 && disp8 <= 127) {
2338 * Check if ModR/M.mod should/can be 01.
2339 * - EAF_BYTEOFFS is set
2340 * - offset can fit in a byte when EVEX is not used
2341 * - offset can be compressed when EVEX is used
2343 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2344 (o >= -128 && o <= 127 && \
2345 seg == NO_SEG && !forw_ref && \
2346 !(input->eaflags & EAF_WORDOFFS) && \
2347 !(ins->rex & REX_EV)) || \
2348 (ins->rex & REX_EV && \
2349 is_disp8n(input, ins, &output->disp8)))
2351 static enum ea_type process_ea(operand *input, ea *output, int bits,
2352 int rfield, opflags_t rflags, insn *ins)
2354 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2355 int addrbits = ins->addr_size;
2357 output->type = EA_SCALAR;
2358 output->rip = false;
2361 /* REX flags for the rfield operand */
2362 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2363 /* EVEX.R' flag for the REG operand */
2364 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2366 if (is_class(REGISTER, input->type)) {
2368 * It's a direct register.
2370 if (!is_register(input->basereg))
2373 if (!is_reg_class(REG_EA, input->basereg))
2376 /* broadcasting is not available with a direct register operand. */
2377 if (input->decoflags & BRDCAST_MASK) {
2378 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2382 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2383 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2384 output->sib_present = false; /* no SIB necessary */
2385 output->bytes = 0; /* no offset necessary either */
2386 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2389 * It's a memory reference.
2392 /* Embedded rounding or SAE is not available with a mem ref operand. */
2393 if (input->decoflags & (ER | SAE)) {
2394 nasm_error(ERR_NONFATAL,
2395 "Embedded rounding is available only with reg-reg op.");
2399 if (input->basereg == -1 &&
2400 (input->indexreg == -1 || input->scale == 0)) {
2402 * It's a pure offset.
2404 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2405 input->segment == NO_SEG) {
2406 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2407 input->type &= ~IP_REL;
2408 input->type |= MEMORY;
2411 if (input->eaflags & EAF_BYTEOFFS ||
2412 (input->eaflags & EAF_WORDOFFS &&
2413 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2414 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2417 if (bits == 64 && (~input->type & IP_REL)) {
2418 output->sib_present = true;
2419 output->sib = GEN_SIB(0, 4, 5);
2421 output->modrm = GEN_MODRM(0, rfield, 4);
2422 output->rip = false;
2424 output->sib_present = false;
2425 output->bytes = (addrbits != 16 ? 4 : 2);
2426 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2427 output->rip = bits == 64;
2431 * It's an indirection.
2433 int i = input->indexreg, b = input->basereg, s = input->scale;
2434 int32_t seg = input->segment;
2435 int hb = input->hintbase, ht = input->hinttype;
2436 int t, it, bt; /* register numbers */
2437 opflags_t x, ix, bx; /* register flags */
2440 i = -1; /* make this easy, at least */
2442 if (is_register(i)) {
2443 it = nasm_regvals[i];
2444 ix = nasm_reg_flags[i];
2450 if (is_register(b)) {
2451 bt = nasm_regvals[b];
2452 bx = nasm_reg_flags[b];
2458 /* if either one are a vector register... */
2459 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2460 opflags_t sok = BITS32 | BITS64;
2461 int32_t o = input->offset;
2462 int mod, scale, index, base;
2465 * For a vector SIB, one has to be a vector and the other,
2466 * if present, a GPR. The vector must be the index operand.
2468 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2474 t = bt, bt = it, it = t;
2475 x = bx, bx = ix, ix = x;
2481 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2488 * While we're here, ensure the user didn't specify
2491 if (input->disp_size == 16 || input->disp_size == 64)
2494 if (addrbits == 16 ||
2495 (addrbits == 32 && !(sok & BITS32)) ||
2496 (addrbits == 64 && !(sok & BITS64)))
2499 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2500 : ((ix & YMMREG & ~REG_EA)
2501 ? EA_YMMVSIB : EA_XMMVSIB));
2503 output->rex |= rexflags(it, ix, REX_X);
2504 output->rex |= rexflags(bt, bx, REX_B);
2505 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2507 index = it & 7; /* it is known to be != -1 */
2522 default: /* then what the smeg is it? */
2523 goto err; /* panic */
2531 if (base != REG_NUM_EBP && o == 0 &&
2532 seg == NO_SEG && !forw_ref &&
2533 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2535 else if (IS_MOD_01())
2541 output->sib_present = true;
2542 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2543 output->modrm = GEN_MODRM(mod, rfield, 4);
2544 output->sib = GEN_SIB(scale, index, base);
2545 } else if ((ix|bx) & (BITS32|BITS64)) {
2547 * it must be a 32/64-bit memory reference. Firstly we have
2548 * to check that all registers involved are type E/Rxx.
2550 opflags_t sok = BITS32 | BITS64;
2551 int32_t o = input->offset;
2554 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2562 goto err; /* Invalid register */
2563 if (~sok & bx & SIZE_MASK)
2564 goto err; /* Invalid size */
2569 * While we're here, ensure the user didn't specify
2572 if (input->disp_size == 16 || input->disp_size == 64)
2575 if (addrbits == 16 ||
2576 (addrbits == 32 && !(sok & BITS32)) ||
2577 (addrbits == 64 && !(sok & BITS64)))
2580 /* now reorganize base/index */
2581 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2582 ((hb == b && ht == EAH_NOTBASE) ||
2583 (hb == i && ht == EAH_MAKEBASE))) {
2584 /* swap if hints say so */
2585 t = bt, bt = it, it = t;
2586 x = bx, bx = ix, ix = x;
2588 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2589 bt = -1, bx = 0, s++;
2590 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2591 /* make single reg base, unless hint */
2592 bt = it, bx = ix, it = -1, ix = 0;
2594 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2595 s == 3 || s == 5 || s == 9) && bt == -1)
2596 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2597 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2598 (input->eaflags & EAF_TIMESTWO))
2599 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2600 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2601 if (s == 1 && it == REG_NUM_ESP) {
2602 /* swap ESP into base if scale is 1 */
2603 t = it, it = bt, bt = t;
2604 x = ix, ix = bx, bx = x;
2606 if (it == REG_NUM_ESP ||
2607 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2608 goto err; /* wrong, for various reasons */
2610 output->rex |= rexflags(it, ix, REX_X);
2611 output->rex |= rexflags(bt, bx, REX_B);
2613 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2622 if (rm != REG_NUM_EBP && o == 0 &&
2623 seg == NO_SEG && !forw_ref &&
2624 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2626 else if (IS_MOD_01())
2632 output->sib_present = false;
2633 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2634 output->modrm = GEN_MODRM(mod, rfield, rm);
2637 int mod, scale, index, base;
2657 default: /* then what the smeg is it? */
2658 goto err; /* panic */
2666 if (base != REG_NUM_EBP && o == 0 &&
2667 seg == NO_SEG && !forw_ref &&
2668 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2670 else if (IS_MOD_01())
2676 output->sib_present = true;
2677 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2678 output->modrm = GEN_MODRM(mod, rfield, 4);
2679 output->sib = GEN_SIB(scale, index, base);
2681 } else { /* it's 16-bit */
2683 int16_t o = input->offset;
2685 /* check for 64-bit long mode */
2689 /* check all registers are BX, BP, SI or DI */
2690 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2691 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2694 /* ensure the user didn't specify DWORD/QWORD */
2695 if (input->disp_size == 32 || input->disp_size == 64)
2698 if (s != 1 && i != -1)
2699 goto err; /* no can do, in 16-bit EA */
2700 if (b == -1 && i != -1) {
2705 if ((b == R_SI || b == R_DI) && i != -1) {
2710 /* have BX/BP as base, SI/DI index */
2712 goto err; /* shouldn't ever happen, in theory */
2713 if (i != -1 && b != -1 &&
2714 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2715 goto err; /* invalid combinations */
2716 if (b == -1) /* pure offset: handled above */
2717 goto err; /* so if it gets to here, panic! */
2721 switch (i * 256 + b) {
2722 case R_SI * 256 + R_BX:
2725 case R_DI * 256 + R_BX:
2728 case R_SI * 256 + R_BP:
2731 case R_DI * 256 + R_BP:
2749 if (rm == -1) /* can't happen, in theory */
2750 goto err; /* so panic if it does */
2752 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2753 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2755 else if (IS_MOD_01())
2760 output->sib_present = false; /* no SIB - it's 16-bit */
2761 output->bytes = mod; /* bytes of offset needed */
2762 output->modrm = GEN_MODRM(mod, rfield, rm);
2767 output->size = 1 + output->sib_present + output->bytes;
2768 return output->type;
2771 return output->type = EA_INVALID;
2774 static void add_asp(insn *ins, int addrbits)
2779 valid = (addrbits == 64) ? 64|32 : 32|16;
2781 switch (ins->prefixes[PPS_ASIZE]) {
2792 valid &= (addrbits == 32) ? 16 : 32;
2798 for (j = 0; j < ins->operands; j++) {
2799 if (is_class(MEMORY, ins->oprs[j].type)) {
2802 /* Verify as Register */
2803 if (!is_register(ins->oprs[j].indexreg))
2806 i = nasm_reg_flags[ins->oprs[j].indexreg];
2808 /* Verify as Register */
2809 if (!is_register(ins->oprs[j].basereg))
2812 b = nasm_reg_flags[ins->oprs[j].basereg];
2814 if (ins->oprs[j].scale == 0)
2818 int ds = ins->oprs[j].disp_size;
2819 if ((addrbits != 64 && ds > 8) ||
2820 (addrbits == 64 && ds == 16))
2840 if (valid & addrbits) {
2841 ins->addr_size = addrbits;
2842 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2843 /* Add an address size prefix */
2844 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2845 ins->addr_size = (addrbits == 32) ? 16 : 32;
2848 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2849 ins->addr_size = addrbits; /* Error recovery */
2852 defdisp = ins->addr_size == 16 ? 16 : 32;
2854 for (j = 0; j < ins->operands; j++) {
2855 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2856 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2858 * mem_offs sizes must match the address size; if not,
2859 * strip the MEM_OFFS bit and match only EA instructions
2861 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);