1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
82 * [l0] ll = 0 (.128, .lz)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
172 #include "compiler.h"
176 #include <inttypes.h>
180 #include "assemble.h"
187 * Matching errors. These should be sorted so that more specific
188 * errors come later in the sequence.
201 * Matching success; the conditional ones first
203 MOK_JUMP, /* Matching OK but needs jmp_match() */
204 MOK_GOOD /* Matching unconditionally OK */
208 enum ea_type type; /* what kind of EA is this? */
209 int sib_present; /* is a SIB byte necessary? */
210 int bytes; /* # of bytes of offset needed */
211 int size; /* lazy - this is sib+bytes+1 */
212 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
213 int8_t disp8; /* compressed displacement for EVEX */
216 #define GEN_SIB(scale, index, base) \
217 (((scale) << 6) | ((index) << 3) | ((base)))
219 #define GEN_MODRM(mod, reg, rm) \
220 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
222 static iflag_t cpu; /* cpu level received from nasm.c */
223 static efunc errfunc;
224 static struct ofmt *outfmt;
225 static ListGen *list;
227 static int64_t calcsize(int32_t, int64_t, int, insn *,
228 const struct itemplate *);
229 static void gencode(int32_t segment, int64_t offset, int bits,
230 insn * ins, const struct itemplate *temp,
232 static enum match_result find_match(const struct itemplate **tempp,
234 int32_t segment, int64_t offset, int bits);
235 static enum match_result matches(const struct itemplate *, insn *, int bits);
236 static opflags_t regflag(const operand *);
237 static int32_t regval(const operand *);
238 static int rexflags(int, opflags_t, int);
239 static int op_rexflags(const operand *, int);
240 static int op_evexflags(const operand *, int, uint8_t);
241 static void add_asp(insn *, int);
243 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
245 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
247 return ins->prefixes[pos] == prefix;
250 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
252 if (ins->prefixes[pos])
253 errfunc(ERR_NONFATAL, "invalid %s prefix",
254 prefix_name(ins->prefixes[pos]));
257 static const char *size_name(int size)
281 static void warn_overflow(int pass, int size)
283 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
284 "%s data exceeds bounds", size_name(size));
287 static void warn_overflow_const(int64_t data, int size)
289 if (overflow_general(data, size))
290 warn_overflow(ERR_PASS1, size);
293 static void warn_overflow_opd(const struct operand *o, int size)
295 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
296 if (overflow_general(o->offset, size))
297 warn_overflow(ERR_PASS2, size);
302 * This routine wrappers the real output format's output routine,
303 * in order to pass a copy of the data off to the listing file
304 * generator at the same time.
306 static void out(int64_t offset, int32_t segto, const void *data,
307 enum out_type type, uint64_t size,
308 int32_t segment, int32_t wrt)
310 static int32_t lineno = 0; /* static!!! */
311 static char *lnfname = NULL;
314 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
316 * This is a non-relocated address, and we're going to
317 * convert it into RAWDATA format.
322 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
326 WRITEADDR(q, *(int64_t *)data, size);
331 list->output(offset, data, type, size);
334 * this call to src_get determines when we call the
335 * debug-format-specific "linenum" function
336 * it updates lineno and lnfname to the current values
337 * returning 0 if "same as last time", -2 if lnfname
338 * changed, and the amount by which lineno changed,
339 * if it did. thus, these variables must be static
342 if (src_get(&lineno, &lnfname))
343 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
345 outfmt->output(segto, data, type, size, segment, wrt);
348 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
350 if (opx->segment != NO_SEG) {
351 uint64_t data = opx->offset;
352 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
354 uint8_t byte = opx->offset;
355 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
359 static bool jmp_match(int32_t segment, int64_t offset, int bits,
360 insn * ins, const struct itemplate *temp)
363 const uint8_t *code = temp->code;
367 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
371 if (optimizing < 0 && c == 0371)
374 isize = calcsize(segment, offset, bits, ins, temp);
376 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
377 /* Be optimistic in pass 1 */
380 if (ins->oprs[0].segment != segment)
383 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
384 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
386 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
387 /* jmp short (opcode eb) cannot be used with bnd prefix. */
388 ins->prefixes[PPS_REP] = P_none;
389 errfunc(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
390 "jmp short does not init bnd regs - bnd prefix dropped.");
396 int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
397 insn * instruction, struct ofmt *output, efunc error,
400 const struct itemplate *temp;
405 int64_t start = offset;
406 int64_t wsize; /* size for DB etc. */
408 errfunc = error; /* to pass to other functions */
410 outfmt = output; /* likewise */
411 list = listgen; /* and again */
413 wsize = idata_bytes(instruction->opcode);
419 int32_t t = instruction->times;
422 "instruction->times < 0 (%ld) in assemble()", t);
424 while (t--) { /* repeat TIMES times */
425 list_for_each(e, instruction->eops) {
426 if (e->type == EOT_DB_NUMBER) {
428 errfunc(ERR_NONFATAL,
429 "integer supplied to a DT, DO or DY"
432 out(offset, segment, &e->offset,
433 OUT_ADDRESS, wsize, e->segment, e->wrt);
436 } else if (e->type == EOT_DB_STRING ||
437 e->type == EOT_DB_STRING_FREE) {
440 out(offset, segment, e->stringval,
441 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
442 align = e->stringlen % wsize;
445 align = wsize - align;
446 out(offset, segment, zero_buffer,
447 OUT_RAWDATA, align, NO_SEG, NO_SEG);
449 offset += e->stringlen + align;
452 if (t > 0 && t == instruction->times - 1) {
454 * Dummy call to list->output to give the offset to the
457 list->output(offset, NULL, OUT_RAWDATA, 0);
458 list->uplevel(LIST_TIMES);
461 if (instruction->times > 1)
462 list->downlevel(LIST_TIMES);
463 return offset - start;
466 if (instruction->opcode == I_INCBIN) {
467 const char *fname = instruction->eops->stringval;
470 fp = fopen(fname, "rb");
472 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
474 } else if (fseek(fp, 0L, SEEK_END) < 0) {
475 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
479 static char buf[4096];
480 size_t t = instruction->times;
485 if (instruction->eops->next) {
486 base = instruction->eops->next->offset;
488 if (instruction->eops->next->next &&
489 len > (size_t)instruction->eops->next->next->offset)
490 len = (size_t)instruction->eops->next->next->offset;
493 * Dummy call to list->output to give the offset to the
496 list->output(offset, NULL, OUT_RAWDATA, 0);
497 list->uplevel(LIST_INCBIN);
501 fseek(fp, base, SEEK_SET);
505 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
508 * This shouldn't happen unless the file
509 * actually changes while we are reading
513 "`incbin': unexpected EOF while"
514 " reading file `%s'", fname);
515 t = 0; /* Try to exit cleanly */
518 out(offset, segment, buf, OUT_RAWDATA, m,
523 list->downlevel(LIST_INCBIN);
524 if (instruction->times > 1) {
526 * Dummy call to list->output to give the offset to the
529 list->output(offset, NULL, OUT_RAWDATA, 0);
530 list->uplevel(LIST_TIMES);
531 list->downlevel(LIST_TIMES);
534 return instruction->times * len;
536 return 0; /* if we're here, there's an error */
539 /* Check to see if we need an address-size prefix */
540 add_asp(instruction, bits);
542 m = find_match(&temp, instruction, segment, offset, bits);
546 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
547 itimes = instruction->times;
548 if (insn_size < 0) /* shouldn't be, on pass two */
549 error(ERR_PANIC, "errors made it through from pass one");
552 for (j = 0; j < MAXPREFIX; j++) {
554 switch (instruction->prefixes[j]) {
575 error(ERR_WARNING | ERR_PASS2,
576 "cs segment base generated, but will be ignored in 64-bit mode");
582 error(ERR_WARNING | ERR_PASS2,
583 "ds segment base generated, but will be ignored in 64-bit mode");
589 error(ERR_WARNING | ERR_PASS2,
590 "es segment base generated, but will be ignored in 64-bit mode");
602 error(ERR_WARNING | ERR_PASS2,
603 "ss segment base generated, but will be ignored in 64-bit mode");
610 "segr6 and segr7 cannot be used as prefixes");
615 "16-bit addressing is not supported "
617 } else if (bits != 16)
627 "64-bit addressing is only supported "
655 error(ERR_PANIC, "invalid instruction prefix");
658 out(offset, segment, &c, OUT_RAWDATA, 1,
663 insn_end = offset + insn_size;
664 gencode(segment, offset, bits, instruction,
667 if (itimes > 0 && itimes == instruction->times - 1) {
669 * Dummy call to list->output to give the offset to the
672 list->output(offset, NULL, OUT_RAWDATA, 0);
673 list->uplevel(LIST_TIMES);
676 if (instruction->times > 1)
677 list->downlevel(LIST_TIMES);
678 return offset - start;
682 case MERR_OPSIZEMISSING:
683 error(ERR_NONFATAL, "operation size not specified");
685 case MERR_OPSIZEMISMATCH:
686 error(ERR_NONFATAL, "mismatch in operand sizes");
688 case MERR_BRNUMMISMATCH:
690 "mismatch in the number of broadcasting elements");
693 error(ERR_NONFATAL, "no instruction for this cpu level");
696 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
699 case MERR_ENCMISMATCH:
700 error(ERR_NONFATAL, "specific encoding scheme not available");
703 error(ERR_NONFATAL, "bnd prefix is not allowed");
706 error(ERR_NONFATAL, "%s prefix is not allowed",
707 (has_prefix(instruction, PPS_REP, P_REPNE) ?
712 "invalid combination of opcode and operands");
719 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
720 insn * instruction, efunc error)
722 const struct itemplate *temp;
725 errfunc = error; /* to pass to other functions */
728 if (instruction->opcode == I_none)
731 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
732 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
733 instruction->opcode == I_DT || instruction->opcode == I_DO ||
734 instruction->opcode == I_DY) {
736 int32_t isize, osize, wsize;
739 wsize = idata_bytes(instruction->opcode);
741 list_for_each(e, instruction->eops) {
745 if (e->type == EOT_DB_NUMBER) {
747 warn_overflow_const(e->offset, wsize);
748 } else if (e->type == EOT_DB_STRING ||
749 e->type == EOT_DB_STRING_FREE)
750 osize = e->stringlen;
752 align = (-osize) % wsize;
755 isize += osize + align;
757 return isize * instruction->times;
760 if (instruction->opcode == I_INCBIN) {
761 const char *fname = instruction->eops->stringval;
766 fp = fopen(fname, "rb");
768 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
770 else if (fseek(fp, 0L, SEEK_END) < 0)
771 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
775 if (instruction->eops->next) {
776 len -= instruction->eops->next->offset;
777 if (instruction->eops->next->next &&
778 len > (size_t)instruction->eops->next->next->offset) {
779 len = (size_t)instruction->eops->next->next->offset;
782 val = instruction->times * len;
789 /* Check to see if we need an address-size prefix */
790 add_asp(instruction, bits);
792 m = find_match(&temp, instruction, segment, offset, bits);
794 /* we've matched an instruction. */
798 isize = calcsize(segment, offset, bits, instruction, temp);
801 for (j = 0; j < MAXPREFIX; j++) {
802 switch (instruction->prefixes[j]) {
832 return isize * instruction->times;
834 return -1; /* didn't match any instruction */
838 static void bad_hle_warn(const insn * ins, uint8_t hleok)
840 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
841 enum whatwarn { w_none, w_lock, w_inval } ww;
842 static const enum whatwarn warn[2][4] =
844 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
845 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
849 n = (unsigned int)rep_pfx - P_XACQUIRE;
851 return; /* Not XACQUIRE/XRELEASE */
854 if (!is_class(MEMORY, ins->oprs[0].type))
855 ww = w_inval; /* HLE requires operand 0 to be memory */
862 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
863 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
864 "%s with this instruction requires lock",
865 prefix_name(rep_pfx));
870 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
871 "%s invalid with this instruction",
872 prefix_name(rep_pfx));
877 /* Common construct */
878 #define case3(x) case (x): case (x)+1: case (x)+2
879 #define case4(x) case3(x): case (x)+3
881 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
882 insn * ins, const struct itemplate *temp)
884 const uint8_t *codes = temp->code;
893 bool lockcheck = true;
894 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
896 ins->rex = 0; /* Ensure REX is reset */
897 eat = EA_SCALAR; /* Expect a scalar EA */
898 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
900 if (ins->prefixes[PPS_OSIZE] == P_O64)
903 (void)segment; /* Don't warn that this parameter is unused */
904 (void)offset; /* Don't warn that this parameter is unused */
908 op1 = (c & 3) + ((opex & 1) << 2);
909 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
910 opx = &ins->oprs[op1];
911 opex = 0; /* For the next iteration */
915 codes += c, length += c;
924 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
929 /* this is an index reg of MIB operand */
930 mib_index = opx->basereg;
943 if (opx->type & (BITS16 | BITS32 | BITS64))
944 length += (opx->type & BITS16) ? 2 : 4;
946 length += (bits == 16) ? 2 : 4;
954 length += ins->addr_size >> 3;
962 length += 8; /* MOV reg64/imm */
970 if (opx->type & (BITS16 | BITS32 | BITS64))
971 length += (opx->type & BITS16) ? 2 : 4;
973 length += (bits == 16) ? 2 : 4;
996 ins->vexreg = regval(opx);
997 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
998 ins->vex_cm = *codes++;
999 ins->vex_wlp = *codes++;
1000 ins->evex_tuple = (*codes++ - 0300);
1006 ins->vex_cm = *codes++;
1007 ins->vex_wlp = *codes++;
1008 ins->evex_tuple = (*codes++ - 0300);
1017 ins->vexreg = regval(opx);
1018 ins->vex_cm = *codes++;
1019 ins->vex_wlp = *codes++;
1025 ins->vex_cm = *codes++;
1026 ins->vex_wlp = *codes++;
1043 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1047 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1054 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1055 has_prefix(ins, PPS_ASIZE, P_A32))
1064 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1068 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1070 ins->prefixes[PPS_OSIZE] = P_O16;
1076 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1080 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1082 ins->prefixes[PPS_OSIZE] = P_O32;
1124 if (!ins->prefixes[PPS_REP])
1125 ins->prefixes[PPS_REP] = P_REP;
1129 if (!ins->prefixes[PPS_REP])
1130 ins->prefixes[PPS_REP] = P_REPNE;
1134 if (ins->oprs[0].segment != NO_SEG)
1135 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1136 " quantity of BSS space");
1138 length += ins->oprs[0].offset;
1142 if (!ins->prefixes[PPS_WAIT])
1143 ins->prefixes[PPS_WAIT] = P_WAIT;
1198 struct operand *opy = &ins->oprs[op2];
1199 struct operand *op_er_sae;
1201 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1204 /* pick rfield from operand b (opx) */
1205 rflags = regflag(opx);
1206 rfield = nasm_regvals[opx->basereg];
1212 /* EVEX.b1 : evex_brerop contains the operand position */
1213 op_er_sae = (ins->evex_brerop >= 0 ?
1214 &ins->oprs[ins->evex_brerop] : NULL);
1216 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1218 ins->evex_p[2] |= EVEX_P2B;
1219 if (op_er_sae->decoflags & ER) {
1220 /* set EVEX.RC (rounding control) */
1221 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1225 /* set EVEX.L'L (vector length) */
1226 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1227 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1228 if (opy->decoflags & BRDCAST_MASK) {
1230 ins->evex_p[2] |= EVEX_P2B;
1234 if (itemp_has(temp, IF_MIB)) {
1235 opy->eaflags |= EAF_MIB;
1237 * if a separate form of MIB (ICC style) is used,
1238 * the index reg info is merged into mem operand
1240 if (mib_index != R_none) {
1241 opy->indexreg = mib_index;
1243 opy->hintbase = mib_index;
1244 opy->hinttype = EAH_NOTBASE;
1248 if (process_ea(opy, &ea_data, bits,
1249 rfield, rflags, ins) != eat) {
1250 errfunc(ERR_NONFATAL, "invalid effective address");
1253 ins->rex |= ea_data.rex;
1254 length += ea_data.size;
1260 errfunc(ERR_PANIC, "internal instruction table corrupt"
1261 ": instruction code \\%o (0x%02X) given", c, c);
1266 ins->rex &= rex_mask;
1268 if (ins->rex & REX_NH) {
1269 if (ins->rex & REX_H) {
1270 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1273 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1276 switch (ins->prefixes[PPS_VEX]) {
1278 if (!(ins->rex & REX_EV))
1283 if (!(ins->rex & REX_V))
1290 if (ins->rex & (REX_V | REX_EV)) {
1291 int bad32 = REX_R|REX_W|REX_X|REX_B;
1293 if (ins->rex & REX_H) {
1294 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1297 switch (ins->vex_wlp & 060) {
1311 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1312 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1314 } else if (!(ins->rex & REX_EV) &&
1315 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1316 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1319 if (ins->rex & REX_EV)
1321 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1322 ins->prefixes[PPS_VEX] == P_VEX3)
1326 } else if (ins->rex & REX_REAL) {
1327 if (ins->rex & REX_H) {
1328 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1330 } else if (bits == 64) {
1332 } else if ((ins->rex & REX_L) &&
1333 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1334 iflag_ffs(&cpu) >= IF_X86_64) {
1336 assert_no_prefix(ins, PPS_LOCK);
1337 lockcheck = false; /* Already errored, no need for warning */
1340 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1345 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1346 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1347 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1348 "instruction is not lockable");
1351 bad_hle_warn(ins, hleok);
1354 * when BND prefix is set by DEFAULT directive,
1355 * BND prefix is added to every appropriate instruction line
1356 * unless it is overridden by NOBND prefix.
1359 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1360 ins->prefixes[PPS_REP] = P_BND;
1365 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1368 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1369 int rex = (ins->rex & REX_REAL) | REX_P;
1370 out(offset, segment, &rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1378 static void gencode(int32_t segment, int64_t offset, int bits,
1379 insn * ins, const struct itemplate *temp,
1387 struct operand *opx;
1388 const uint8_t *codes = temp->code;
1390 enum ea_type eat = EA_SCALAR;
1394 op1 = (c & 3) + ((opex & 1) << 2);
1395 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1396 opx = &ins->oprs[op1];
1397 opex = 0; /* For the next iteration */
1404 offset += emit_rex(ins, segment, offset, bits);
1405 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1417 offset += emit_rex(ins, segment, offset, bits);
1418 bytes[0] = *codes++ + (regval(opx) & 7);
1419 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1427 if (opx->offset < -256 || opx->offset > 255) {
1428 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1429 "byte value exceeds bounds");
1431 out_imm8(offset, segment, opx);
1436 if (opx->offset < 0 || opx->offset > 255)
1437 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1438 "unsigned byte value exceeds bounds");
1439 out_imm8(offset, segment, opx);
1444 warn_overflow_opd(opx, 2);
1446 out(offset, segment, &data, OUT_ADDRESS, 2,
1447 opx->segment, opx->wrt);
1452 if (opx->type & (BITS16 | BITS32))
1453 size = (opx->type & BITS16) ? 2 : 4;
1455 size = (bits == 16) ? 2 : 4;
1456 warn_overflow_opd(opx, size);
1458 out(offset, segment, &data, OUT_ADDRESS, size,
1459 opx->segment, opx->wrt);
1464 warn_overflow_opd(opx, 4);
1466 out(offset, segment, &data, OUT_ADDRESS, 4,
1467 opx->segment, opx->wrt);
1473 size = ins->addr_size >> 3;
1474 warn_overflow_opd(opx, size);
1475 out(offset, segment, &data, OUT_ADDRESS, size,
1476 opx->segment, opx->wrt);
1481 if (opx->segment != segment) {
1483 out(offset, segment, &data,
1484 OUT_REL1ADR, insn_end - offset,
1485 opx->segment, opx->wrt);
1487 data = opx->offset - insn_end;
1488 if (data > 127 || data < -128)
1489 errfunc(ERR_NONFATAL, "short jump is out of range");
1490 out(offset, segment, &data,
1491 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1497 data = (int64_t)opx->offset;
1498 out(offset, segment, &data, OUT_ADDRESS, 8,
1499 opx->segment, opx->wrt);
1504 if (opx->segment != segment) {
1506 out(offset, segment, &data,
1507 OUT_REL2ADR, insn_end - offset,
1508 opx->segment, opx->wrt);
1510 data = opx->offset - insn_end;
1511 out(offset, segment, &data,
1512 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1518 if (opx->type & (BITS16 | BITS32 | BITS64))
1519 size = (opx->type & BITS16) ? 2 : 4;
1521 size = (bits == 16) ? 2 : 4;
1522 if (opx->segment != segment) {
1524 out(offset, segment, &data,
1525 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1526 insn_end - offset, opx->segment, opx->wrt);
1528 data = opx->offset - insn_end;
1529 out(offset, segment, &data,
1530 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1536 if (opx->segment != segment) {
1538 out(offset, segment, &data,
1539 OUT_REL4ADR, insn_end - offset,
1540 opx->segment, opx->wrt);
1542 data = opx->offset - insn_end;
1543 out(offset, segment, &data,
1544 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1550 if (opx->segment == NO_SEG)
1551 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1554 out(offset, segment, &data, OUT_ADDRESS, 2,
1555 outfmt->segbase(1 + opx->segment),
1562 opx = &ins->oprs[c >> 3];
1563 bytes[0] = nasm_regvals[opx->basereg] << 4;
1564 opx = &ins->oprs[c & 7];
1565 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1566 errfunc(ERR_NONFATAL,
1567 "non-absolute expression not permitted as argument %d",
1570 if (opx->offset & ~15) {
1571 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1572 "four-bit argument exceeds bounds");
1574 bytes[0] |= opx->offset & 15;
1576 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1582 opx = &ins->oprs[c >> 4];
1583 bytes[0] = nasm_regvals[opx->basereg] << 4;
1585 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1590 bytes[0] = nasm_regvals[opx->basereg] << 4;
1591 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1597 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1598 (int32_t)data != (int64_t)data) {
1599 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1600 "signed dword immediate exceeds bounds");
1602 out(offset, segment, &data, OUT_ADDRESS, 4,
1603 opx->segment, opx->wrt);
1610 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1611 EVEX_P2Z | EVEX_P2AAA, 2);
1612 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1614 /* EVEX.X can be set by either REX or EVEX for different reasons */
1615 bytes[1] = ((((ins->rex & 7) << 5) |
1616 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1618 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1619 ((~ins->vexreg & 15) << 3) |
1620 (1 << 2) | (ins->vex_wlp & 3);
1621 bytes[3] = ins->evex_p[2];
1622 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1629 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1630 ins->prefixes[PPS_VEX] == P_VEX3) {
1631 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1632 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1633 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1634 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1635 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1639 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1640 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1641 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1656 if (ins->rex & REX_W)
1658 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1660 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1665 um = (uint64_t)2 << (s-1);
1668 if (uv > 127 && uv < (uint64_t)-128 &&
1669 (uv < um-128 || uv > um-1)) {
1670 /* If this wasn't explicitly byte-sized, warn as though we
1671 * had fallen through to the imm16/32/64 case.
1673 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1674 "%s value exceeds bounds",
1675 (opx->type & BITS8) ? "signed byte" :
1680 if (opx->segment != NO_SEG) {
1682 out(offset, segment, &data, OUT_ADDRESS, 1,
1683 opx->segment, opx->wrt);
1686 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1697 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1699 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1706 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1708 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1743 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1744 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1753 *bytes = c - 0332 + 0xF2;
1754 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1759 if (ins->rex & REX_R) {
1761 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1764 ins->rex &= ~(REX_L|REX_R);
1775 if (ins->oprs[0].segment != NO_SEG)
1776 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1778 int64_t size = ins->oprs[0].offset;
1780 out(offset, segment, NULL,
1781 OUT_RESERVE, size, NO_SEG, NO_SEG);
1794 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1804 *bytes = c - 0366 + 0x66;
1805 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1813 *bytes = bits == 16 ? 3 : 5;
1814 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1848 struct operand *opy = &ins->oprs[op2];
1851 /* pick rfield from operand b (opx) */
1852 rflags = regflag(opx);
1853 rfield = nasm_regvals[opx->basereg];
1855 /* rfield is constant */
1860 if (process_ea(opy, &ea_data, bits,
1861 rfield, rflags, ins) != eat)
1862 errfunc(ERR_NONFATAL, "invalid effective address");
1865 *p++ = ea_data.modrm;
1866 if (ea_data.sib_present)
1870 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1873 * Make sure the address gets the right offset in case
1874 * the line breaks in the .lst file (BR 1197827)
1879 switch (ea_data.bytes) {
1886 /* use compressed displacement, if available */
1887 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1890 if (opy->segment == segment) {
1892 if (overflow_signed(data, ea_data.bytes))
1893 warn_overflow(ERR_PASS2, ea_data.bytes);
1894 out(offset, segment, &data, OUT_ADDRESS,
1895 ea_data.bytes, NO_SEG, NO_SEG);
1897 /* overflow check in output/linker? */
1898 out(offset, segment, &data, OUT_REL4ADR,
1899 insn_end - offset, opy->segment, opy->wrt);
1902 if (overflow_general(data, ins->addr_size >> 3) ||
1903 signed_bits(data, ins->addr_size) !=
1904 signed_bits(data, ea_data.bytes * 8))
1905 warn_overflow(ERR_PASS2, ea_data.bytes);
1907 out(offset, segment, &data, OUT_ADDRESS,
1908 ea_data.bytes, opy->segment, opy->wrt);
1914 "Invalid amount of bytes (%d) for offset?!",
1923 errfunc(ERR_PANIC, "internal instruction table corrupt"
1924 ": instruction code \\%o (0x%02X) given", c, c);
1930 static opflags_t regflag(const operand * o)
1932 if (!is_register(o->basereg))
1933 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1934 return nasm_reg_flags[o->basereg];
1937 static int32_t regval(const operand * o)
1939 if (!is_register(o->basereg))
1940 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1941 return nasm_regvals[o->basereg];
1944 static int op_rexflags(const operand * o, int mask)
1949 if (!is_register(o->basereg))
1950 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1952 flags = nasm_reg_flags[o->basereg];
1953 val = nasm_regvals[o->basereg];
1955 return rexflags(val, flags, mask);
1958 static int rexflags(int val, opflags_t flags, int mask)
1962 if (val >= 0 && (val & 8))
1963 rex |= REX_B|REX_X|REX_R;
1966 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1968 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1974 static int evexflags(int val, decoflags_t deco,
1975 int mask, uint8_t byte)
1981 if (val >= 0 && (val & 16))
1982 evex |= (EVEX_P0RP | EVEX_P0X);
1985 if (val >= 0 && (val & 16))
1989 if (deco & OPMASK_MASK)
1990 evex |= deco & EVEX_P2AAA;
1996 static int op_evexflags(const operand * o, int mask, uint8_t byte)
2000 if (!is_register(o->basereg))
2001 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
2003 val = nasm_regvals[o->basereg];
2005 return evexflags(val, o->decoflags, mask, byte);
2008 static enum match_result find_match(const struct itemplate **tempp,
2010 int32_t segment, int64_t offset, int bits)
2012 const struct itemplate *temp;
2013 enum match_result m, merr;
2014 opflags_t xsizeflags[MAX_OPERANDS];
2015 bool opsizemissing = false;
2016 int8_t broadcast = instruction->evex_brerop;
2019 /* broadcasting uses a different data element size */
2020 for (i = 0; i < instruction->operands; i++)
2022 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2024 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2026 merr = MERR_INVALOP;
2028 for (temp = nasm_instructions[instruction->opcode];
2029 temp->opcode != I_none; temp++) {
2030 m = matches(temp, instruction, bits);
2031 if (m == MOK_JUMP) {
2032 if (jmp_match(segment, offset, bits, instruction, temp))
2036 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2038 * Missing operand size and a candidate for fuzzy matching...
2040 for (i = 0; i < temp->operands; i++)
2042 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2044 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2045 opsizemissing = true;
2049 if (merr == MOK_GOOD)
2053 /* No match, but see if we can get a fuzzy operand size match... */
2057 for (i = 0; i < instruction->operands; i++) {
2059 * We ignore extrinsic operand sizes on registers, so we should
2060 * never try to fuzzy-match on them. This also resolves the case
2061 * when we have e.g. "xmmrm128" in two different positions.
2063 if (is_class(REGISTER, instruction->oprs[i].type))
2066 /* This tests if xsizeflags[i] has more than one bit set */
2067 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2068 goto done; /* No luck */
2070 if (i == broadcast) {
2071 instruction->oprs[i].decoflags |= xsizeflags[i];
2072 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2075 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2079 /* Try matching again... */
2080 for (temp = nasm_instructions[instruction->opcode];
2081 temp->opcode != I_none; temp++) {
2082 m = matches(temp, instruction, bits);
2083 if (m == MOK_JUMP) {
2084 if (jmp_match(segment, offset, bits, instruction, temp))
2091 if (merr == MOK_GOOD)
2100 static enum match_result matches(const struct itemplate *itemp,
2101 insn *instruction, int bits)
2103 opflags_t size[MAX_OPERANDS], asize;
2104 bool opsizemissing = false;
2110 if (itemp->opcode != instruction->opcode)
2111 return MERR_INVALOP;
2114 * Count the operands
2116 if (itemp->operands != instruction->operands)
2117 return MERR_INVALOP;
2122 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2123 return MERR_INVALOP;
2128 switch (instruction->prefixes[PPS_VEX]) {
2130 if (!itemp_has(itemp, IF_EVEX))
2131 return MERR_ENCMISMATCH;
2135 if (!itemp_has(itemp, IF_VEX))
2136 return MERR_ENCMISMATCH;
2143 * Check that no spurious colons or TOs are present
2145 for (i = 0; i < itemp->operands; i++)
2146 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2147 return MERR_INVALOP;
2150 * Process size flags
2152 switch (itemp_smask(itemp)) {
2153 case IF_GENBIT(IF_SB):
2156 case IF_GENBIT(IF_SW):
2159 case IF_GENBIT(IF_SD):
2162 case IF_GENBIT(IF_SQ):
2165 case IF_GENBIT(IF_SO):
2168 case IF_GENBIT(IF_SY):
2171 case IF_GENBIT(IF_SZ):
2174 case IF_GENBIT(IF_SIZE):
2195 if (itemp_armask(itemp)) {
2196 /* S- flags only apply to a specific operand */
2197 i = itemp_arg(itemp);
2198 memset(size, 0, sizeof size);
2201 /* S- flags apply to all operands */
2202 for (i = 0; i < MAX_OPERANDS; i++)
2207 * Check that the operand flags all match up,
2208 * it's a bit tricky so lets be verbose:
2210 * 1) Find out the size of operand. If instruction
2211 * doesn't have one specified -- we're trying to
2212 * guess it either from template (IF_S* flag) or
2215 * 2) If template operand do not match the instruction OR
2216 * template has an operand size specified AND this size differ
2217 * from which instruction has (perhaps we got it from code bits)
2219 * a) Check that only size of instruction and operand is differ
2220 * other characteristics do match
2221 * b) Perhaps it's a register specified in instruction so
2222 * for such a case we just mark that operand as "size
2223 * missing" and this will turn on fuzzy operand size
2224 * logic facility (handled by a caller)
2226 for (i = 0; i < itemp->operands; i++) {
2227 opflags_t type = instruction->oprs[i].type;
2228 decoflags_t deco = instruction->oprs[i].decoflags;
2229 bool is_broadcast = deco & BRDCAST_MASK;
2230 uint8_t brcast_num = 0;
2231 opflags_t template_opsize, insn_opsize;
2233 if (!(type & SIZE_MASK))
2236 insn_opsize = type & SIZE_MASK;
2237 if (!is_broadcast) {
2238 template_opsize = itemp->opd[i] & SIZE_MASK;
2240 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2242 * when broadcasting, the element size depends on
2243 * the instruction type. decorator flag should match.
2247 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2248 /* calculate the proper number : {1to<brcast_num>} */
2249 brcast_num = (itemp->opd[i] & SIZE_MASK) / BITS128 *
2250 BITS64 / template_opsize * 2;
2252 template_opsize = 0;
2256 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2257 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2258 return MERR_INVALOP;
2259 } else if (template_opsize) {
2260 if (template_opsize != insn_opsize) {
2262 return MERR_INVALOP;
2263 } else if (!is_class(REGISTER, type)) {
2265 * Note: we don't honor extrinsic operand sizes for registers,
2266 * so "missing operand size" for a register should be
2267 * considered a wildcard match rather than an error.
2269 opsizemissing = true;
2271 } else if (is_broadcast &&
2273 (8U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2275 * broadcasting opsize matches but the number of repeated memory
2276 * element does not match.
2277 * if 64b double precision float is broadcasted to zmm (512b),
2278 * broadcasting decorator must be {1to8}.
2280 return MERR_BRNUMMISMATCH;
2286 return MERR_OPSIZEMISSING;
2289 * Check operand sizes
2291 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2292 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2293 for (i = 0; i < oprs; i++) {
2294 asize = itemp->opd[i] & SIZE_MASK;
2296 for (i = 0; i < oprs; i++)
2302 oprs = itemp->operands;
2305 for (i = 0; i < itemp->operands; i++) {
2306 if (!(itemp->opd[i] & SIZE_MASK) &&
2307 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2308 return MERR_OPSIZEMISMATCH;
2312 * Check template is okay at the set cpu level
2314 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2318 * Verify the appropriate long mode flag.
2320 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2321 return MERR_BADMODE;
2324 * If we have a HLE prefix, look for the NOHLE flag
2326 if (itemp_has(itemp, IF_NOHLE) &&
2327 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2328 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2332 * Check if special handling needed for Jumps
2334 if ((itemp->code[0] & ~1) == 0370)
2338 * Check if BND prefix is allowed.
2339 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2341 if (!itemp_has(itemp, IF_BND) &&
2342 (has_prefix(instruction, PPS_REP, P_BND) ||
2343 has_prefix(instruction, PPS_REP, P_NOBND)))
2345 else if (itemp_has(itemp, IF_BND) &&
2346 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2347 has_prefix(instruction, PPS_REP, P_REPNZ)))
2348 return MERR_BADREPNE;
2354 * Check if ModR/M.mod should/can be 01.
2355 * - EAF_BYTEOFFS is set
2356 * - offset can fit in a byte when EVEX is not used
2357 * - offset can be compressed when EVEX is used
2359 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2360 (o >= -128 && o <= 127 && \
2361 seg == NO_SEG && !forw_ref && \
2362 !(input->eaflags & EAF_WORDOFFS) && \
2363 !(ins->rex & REX_EV)) || \
2364 (ins->rex & REX_EV && \
2365 is_disp8n(input, ins, &output->disp8)))
2367 static enum ea_type process_ea(operand *input, ea *output, int bits,
2368 int rfield, opflags_t rflags, insn *ins)
2370 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2371 int addrbits = ins->addr_size;
2372 int eaflags = input->eaflags;
2374 output->type = EA_SCALAR;
2375 output->rip = false;
2378 /* REX flags for the rfield operand */
2379 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2380 /* EVEX.R' flag for the REG operand */
2381 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2383 if (is_class(REGISTER, input->type)) {
2385 * It's a direct register.
2387 if (!is_register(input->basereg))
2390 if (!is_reg_class(REG_EA, input->basereg))
2393 /* broadcasting is not available with a direct register operand. */
2394 if (input->decoflags & BRDCAST_MASK) {
2395 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2399 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2400 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2401 output->sib_present = false; /* no SIB necessary */
2402 output->bytes = 0; /* no offset necessary either */
2403 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2406 * It's a memory reference.
2409 /* Embedded rounding or SAE is not available with a mem ref operand. */
2410 if (input->decoflags & (ER | SAE)) {
2411 nasm_error(ERR_NONFATAL,
2412 "Embedded rounding is available only with reg-reg op.");
2416 if (input->basereg == -1 &&
2417 (input->indexreg == -1 || input->scale == 0)) {
2419 * It's a pure offset.
2421 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2422 input->segment == NO_SEG) {
2423 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2424 input->type &= ~IP_REL;
2425 input->type |= MEMORY;
2429 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2430 nasm_error(ERR_NONFATAL, "RIP-relative addressing is prohibited for mib.");
2434 if (eaflags & EAF_BYTEOFFS ||
2435 (eaflags & EAF_WORDOFFS &&
2436 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2437 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2440 if (bits == 64 && (~input->type & IP_REL)) {
2441 output->sib_present = true;
2442 output->sib = GEN_SIB(0, 4, 5);
2444 output->modrm = GEN_MODRM(0, rfield, 4);
2445 output->rip = false;
2447 output->sib_present = false;
2448 output->bytes = (addrbits != 16 ? 4 : 2);
2449 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2450 output->rip = bits == 64;
2454 * It's an indirection.
2456 int i = input->indexreg, b = input->basereg, s = input->scale;
2457 int32_t seg = input->segment;
2458 int hb = input->hintbase, ht = input->hinttype;
2459 int t, it, bt; /* register numbers */
2460 opflags_t x, ix, bx; /* register flags */
2463 i = -1; /* make this easy, at least */
2465 if (is_register(i)) {
2466 it = nasm_regvals[i];
2467 ix = nasm_reg_flags[i];
2473 if (is_register(b)) {
2474 bt = nasm_regvals[b];
2475 bx = nasm_reg_flags[b];
2481 /* if either one are a vector register... */
2482 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2483 opflags_t sok = BITS32 | BITS64;
2484 int32_t o = input->offset;
2485 int mod, scale, index, base;
2488 * For a vector SIB, one has to be a vector and the other,
2489 * if present, a GPR. The vector must be the index operand.
2491 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2497 t = bt, bt = it, it = t;
2498 x = bx, bx = ix, ix = x;
2504 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2511 * While we're here, ensure the user didn't specify
2514 if (input->disp_size == 16 || input->disp_size == 64)
2517 if (addrbits == 16 ||
2518 (addrbits == 32 && !(sok & BITS32)) ||
2519 (addrbits == 64 && !(sok & BITS64)))
2522 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2523 : ((ix & YMMREG & ~REG_EA)
2524 ? EA_YMMVSIB : EA_XMMVSIB));
2526 output->rex |= rexflags(it, ix, REX_X);
2527 output->rex |= rexflags(bt, bx, REX_B);
2528 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2530 index = it & 7; /* it is known to be != -1 */
2545 default: /* then what the smeg is it? */
2546 goto err; /* panic */
2554 if (base != REG_NUM_EBP && o == 0 &&
2555 seg == NO_SEG && !forw_ref &&
2556 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2558 else if (IS_MOD_01())
2564 output->sib_present = true;
2565 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2566 output->modrm = GEN_MODRM(mod, rfield, 4);
2567 output->sib = GEN_SIB(scale, index, base);
2568 } else if ((ix|bx) & (BITS32|BITS64)) {
2570 * it must be a 32/64-bit memory reference. Firstly we have
2571 * to check that all registers involved are type E/Rxx.
2573 opflags_t sok = BITS32 | BITS64;
2574 int32_t o = input->offset;
2577 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2585 goto err; /* Invalid register */
2586 if (~sok & bx & SIZE_MASK)
2587 goto err; /* Invalid size */
2592 * While we're here, ensure the user didn't specify
2595 if (input->disp_size == 16 || input->disp_size == 64)
2598 if (addrbits == 16 ||
2599 (addrbits == 32 && !(sok & BITS32)) ||
2600 (addrbits == 64 && !(sok & BITS64)))
2603 /* now reorganize base/index */
2604 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2605 ((hb == b && ht == EAH_NOTBASE) ||
2606 (hb == i && ht == EAH_MAKEBASE))) {
2607 /* swap if hints say so */
2608 t = bt, bt = it, it = t;
2609 x = bx, bx = ix, ix = x;
2612 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2613 /* make single reg base, unless hint */
2614 bt = it, bx = ix, it = -1, ix = 0;
2616 if (eaflags & EAF_MIB) {
2617 /* only for mib operands */
2618 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2620 * make a single reg index [reg*1].
2621 * gas uses this form for an explicit index register.
2623 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2625 if ((ht == EAH_SUMMED) && bt == -1) {
2626 /* separate once summed index into [base, index] */
2627 bt = it, bx = ix, s--;
2630 if (((s == 2 && it != REG_NUM_ESP &&
2631 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2632 s == 3 || s == 5 || s == 9) && bt == -1) {
2633 /* convert 3*EAX to EAX+2*EAX */
2634 bt = it, bx = ix, s--;
2636 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2637 (eaflags & EAF_TIMESTWO) &&
2638 (hb == b && ht == EAH_NOTBASE)) {
2640 * convert [NOSPLIT EAX*1]
2641 * to sib format with 0x0 displacement - [EAX*1+0].
2643 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2646 if (s == 1 && it == REG_NUM_ESP) {
2647 /* swap ESP into base if scale is 1 */
2648 t = it, it = bt, bt = t;
2649 x = ix, ix = bx, bx = x;
2651 if (it == REG_NUM_ESP ||
2652 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2653 goto err; /* wrong, for various reasons */
2655 output->rex |= rexflags(it, ix, REX_X);
2656 output->rex |= rexflags(bt, bx, REX_B);
2658 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2667 if (rm != REG_NUM_EBP && o == 0 &&
2668 seg == NO_SEG && !forw_ref &&
2669 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2671 else if (IS_MOD_01())
2677 output->sib_present = false;
2678 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2679 output->modrm = GEN_MODRM(mod, rfield, rm);
2682 int mod, scale, index, base;
2702 default: /* then what the smeg is it? */
2703 goto err; /* panic */
2711 if (base != REG_NUM_EBP && o == 0 &&
2712 seg == NO_SEG && !forw_ref &&
2713 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2715 else if (IS_MOD_01())
2721 output->sib_present = true;
2722 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2723 output->modrm = GEN_MODRM(mod, rfield, 4);
2724 output->sib = GEN_SIB(scale, index, base);
2726 } else { /* it's 16-bit */
2728 int16_t o = input->offset;
2730 /* check for 64-bit long mode */
2734 /* check all registers are BX, BP, SI or DI */
2735 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2736 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2739 /* ensure the user didn't specify DWORD/QWORD */
2740 if (input->disp_size == 32 || input->disp_size == 64)
2743 if (s != 1 && i != -1)
2744 goto err; /* no can do, in 16-bit EA */
2745 if (b == -1 && i != -1) {
2750 if ((b == R_SI || b == R_DI) && i != -1) {
2755 /* have BX/BP as base, SI/DI index */
2757 goto err; /* shouldn't ever happen, in theory */
2758 if (i != -1 && b != -1 &&
2759 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2760 goto err; /* invalid combinations */
2761 if (b == -1) /* pure offset: handled above */
2762 goto err; /* so if it gets to here, panic! */
2766 switch (i * 256 + b) {
2767 case R_SI * 256 + R_BX:
2770 case R_DI * 256 + R_BX:
2773 case R_SI * 256 + R_BP:
2776 case R_DI * 256 + R_BP:
2794 if (rm == -1) /* can't happen, in theory */
2795 goto err; /* so panic if it does */
2797 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2798 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2800 else if (IS_MOD_01())
2805 output->sib_present = false; /* no SIB - it's 16-bit */
2806 output->bytes = mod; /* bytes of offset needed */
2807 output->modrm = GEN_MODRM(mod, rfield, rm);
2812 output->size = 1 + output->sib_present + output->bytes;
2813 return output->type;
2816 return output->type = EA_INVALID;
2819 static void add_asp(insn *ins, int addrbits)
2824 valid = (addrbits == 64) ? 64|32 : 32|16;
2826 switch (ins->prefixes[PPS_ASIZE]) {
2837 valid &= (addrbits == 32) ? 16 : 32;
2843 for (j = 0; j < ins->operands; j++) {
2844 if (is_class(MEMORY, ins->oprs[j].type)) {
2847 /* Verify as Register */
2848 if (!is_register(ins->oprs[j].indexreg))
2851 i = nasm_reg_flags[ins->oprs[j].indexreg];
2853 /* Verify as Register */
2854 if (!is_register(ins->oprs[j].basereg))
2857 b = nasm_reg_flags[ins->oprs[j].basereg];
2859 if (ins->oprs[j].scale == 0)
2863 int ds = ins->oprs[j].disp_size;
2864 if ((addrbits != 64 && ds > 8) ||
2865 (addrbits == 64 && ds == 16))
2885 if (valid & addrbits) {
2886 ins->addr_size = addrbits;
2887 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2888 /* Add an address size prefix */
2889 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2890 ins->addr_size = (addrbits == 32) ? 16 : 32;
2893 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2894 ins->addr_size = addrbits; /* Error recovery */
2897 defdisp = ins->addr_size == 16 ? 16 : 32;
2899 for (j = 0; j < ins->operands; j++) {
2900 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2901 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2903 * mem_offs sizes must match the address size; if not,
2904 * strip the MEM_OFFS bit and match only EA instructions
2906 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);