1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \20..\23 - a byte immediate operand, from operand 0..3
46 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
47 * \30..\33 - a word immediate operand, from operand 0..3
48 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
49 * assembly mode or the operand-size override on the operand
50 * \40..\43 - a long immediate operand, from operand 0..3
51 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
52 * depending on the address size of the instruction.
53 * \50..\53 - a byte relative operand, from operand 0..3
54 * \54..\57 - a qword immediate operand, from operand 0..3
55 * \60..\63 - a word relative operand, from operand 0..3
56 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
57 * assembly mode or the operand-size override on the operand
58 * \70..\73 - a long relative operand, from operand 0..3
59 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
60 * \1ab - a ModRM, calculated on EA in operand a, with the spare
61 * field the register value of operand b.
62 * \172\ab - the register number from operand a in bits 7..4, with
63 * the 4-bit immediate from operand b in bits 3..0.
64 * \173\xab - the register number from operand a in bits 7..4, with
65 * the value b in bits 3..0.
66 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
67 * an arbitrary value in bits 3..0 (assembled as zero.)
68 * \2ab - a ModRM, calculated on EA in operand a, with the spare
69 * field equal to digit b.
70 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
71 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
72 * V field taken from operand 0..3.
73 * \270 - this instruction uses VEX/XOP rather than REX, with the
74 * V field set to 1111b.
76 * VEX/XOP prefixes are followed by the sequence:
77 * \tmm\wlp where mm is the M field; and wlp is:
79 * [l0] ll = 0 for L = 0 (.128, .lz)
80 * [l1] ll = 1 for L = 1 (.256)
81 * [lig] ll = 2 for L don't care (always assembled as 0)
83 * [w0] ww = 0 for W = 0
84 * [w1 ] ww = 1 for W = 1
85 * [wig] ww = 2 for W don't care (always assembled as 0)
86 * [ww] ww = 3 for W used as REX.W
88 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
90 * \271 - instruction takes XRELEASE (F3) with or without lock
91 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
92 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
93 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
94 * to the operand size (if o16/o32/o64 present) or the bit size
95 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
96 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
97 * \312 - (disassembler only) invalid with non-default address size.
98 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
99 * \314 - (disassembler only) invalid with REX.B
100 * \315 - (disassembler only) invalid with REX.X
101 * \316 - (disassembler only) invalid with REX.R
102 * \317 - (disassembler only) invalid with REX.W
103 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
104 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
105 * \322 - indicates that this instruction is only valid when the
106 * operand size is the default (instruction to disassembler,
107 * generates no code in the assembler)
108 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
109 * \324 - indicates 64-bit operand size requiring REX prefix.
110 * \325 - instruction which always uses spl/bpl/sil/dil
111 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
112 disassembler only; for SSE instructions.
113 * \330 - a literal byte follows in the code stream, to be added
114 * to the condition code value of the instruction.
115 * \331 - instruction not valid with REP prefix. Hint for
116 * disassembler only; for SSE instructions.
117 * \332 - REP prefix (0xF2 byte) used as opcode extension.
118 * \333 - REP prefix (0xF3 byte) used as opcode extension.
119 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
120 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
121 * \336 - force a REP(E) prefix (0xF3) even if not specified.
122 * \337 - force a REPNE prefix (0xF2) even if not specified.
123 * \336-\337 are still listed as prefixes in the disassembler.
124 * \340 - reserve <operand 0> bytes of uninitialized storage.
125 * Operand 0 had better be a segmentless constant.
126 * \341 - this instruction needs a WAIT "prefix"
127 * \360 - no SSE prefix (== \364\331)
128 * \361 - 66 SSE prefix (== \366\331)
129 * \364 - operand-size prefix (0x66) not permitted
130 * \365 - address-size prefix (0x67) not permitted
131 * \366 - operand-size prefix (0x66) used as opcode extension
132 * \367 - address-size prefix (0x67) used as opcode extension
133 * \370,\371 - match only if operand 0 meets byte jump criteria.
134 * 370 is used for Jcc, 371 is used for JMP.
135 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
136 * used for conditional jump over longer jump
137 * \374 - this instruction takes an XMM VSIB memory EA
138 * \375 - this instruction takes an YMM VSIB memory EA
141 #include "compiler.h"
145 #include <inttypes.h>
149 #include "assemble.h"
155 * Matching errors. These should be sorted so that more specific
156 * errors come later in the sequence.
165 * Matching success; the conditional ones first
167 MOK_JUMP, /* Matching OK but needs jmp_match() */
168 MOK_GOOD /* Matching unconditionally OK */
172 enum ea_type type; /* what kind of EA is this? */
173 int sib_present; /* is a SIB byte necessary? */
174 int bytes; /* # of bytes of offset needed */
175 int size; /* lazy - this is sib+bytes+1 */
176 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
179 #define GEN_SIB(scale, index, base) \
180 (((scale) << 6) | ((index) << 3) | ((base)))
182 #define GEN_MODRM(mod, reg, rm) \
183 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
185 static uint32_t cpu; /* cpu level received from nasm.c */
186 static efunc errfunc;
187 static struct ofmt *outfmt;
188 static ListGen *list;
190 static int64_t calcsize(int32_t, int64_t, int, insn *,
191 const struct itemplate *);
192 static void gencode(int32_t segment, int64_t offset, int bits,
193 insn * ins, const struct itemplate *temp,
195 static enum match_result find_match(const struct itemplate **tempp,
197 int32_t segment, int64_t offset, int bits);
198 static enum match_result matches(const struct itemplate *, insn *, int bits);
199 static opflags_t regflag(const operand *);
200 static int32_t regval(const operand *);
201 static int rexflags(int, opflags_t, int);
202 static int op_rexflags(const operand *, int);
203 static void add_asp(insn *, int);
205 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
207 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
209 return ins->prefixes[pos] == prefix;
212 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
214 if (ins->prefixes[pos])
215 errfunc(ERR_NONFATAL, "invalid %s prefix",
216 prefix_name(ins->prefixes[pos]));
219 static const char *size_name(int size)
241 static void warn_overflow(int pass, int size)
243 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
244 "%s data exceeds bounds", size_name(size));
247 static void warn_overflow_const(int64_t data, int size)
249 if (overflow_general(data, size))
250 warn_overflow(ERR_PASS1, size);
253 static void warn_overflow_opd(const struct operand *o, int size)
255 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
256 if (overflow_general(o->offset, size))
257 warn_overflow(ERR_PASS2, size);
262 * This routine wrappers the real output format's output routine,
263 * in order to pass a copy of the data off to the listing file
264 * generator at the same time.
266 static void out(int64_t offset, int32_t segto, const void *data,
267 enum out_type type, uint64_t size,
268 int32_t segment, int32_t wrt)
270 static int32_t lineno = 0; /* static!!! */
271 static char *lnfname = NULL;
274 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
276 * This is a non-relocated address, and we're going to
277 * convert it into RAWDATA format.
282 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
286 WRITEADDR(q, *(int64_t *)data, size);
291 list->output(offset, data, type, size);
294 * this call to src_get determines when we call the
295 * debug-format-specific "linenum" function
296 * it updates lineno and lnfname to the current values
297 * returning 0 if "same as last time", -2 if lnfname
298 * changed, and the amount by which lineno changed,
299 * if it did. thus, these variables must be static
302 if (src_get(&lineno, &lnfname))
303 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
305 outfmt->output(segto, data, type, size, segment, wrt);
308 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
310 if (opx->segment != NO_SEG) {
311 uint64_t data = opx->offset;
312 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
314 uint8_t byte = opx->offset;
315 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
319 static bool jmp_match(int32_t segment, int64_t offset, int bits,
320 insn * ins, const struct itemplate *temp)
323 const uint8_t *code = temp->code;
326 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
330 if (optimizing < 0 && c == 0371)
333 isize = calcsize(segment, offset, bits, ins, temp);
335 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
336 /* Be optimistic in pass 1 */
339 if (ins->oprs[0].segment != segment)
342 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
343 return (isize >= -128 && isize <= 127); /* is it byte size? */
346 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
347 insn * instruction, struct ofmt *output, efunc error,
350 const struct itemplate *temp;
355 int64_t start = offset;
356 int64_t wsize; /* size for DB etc. */
358 errfunc = error; /* to pass to other functions */
360 outfmt = output; /* likewise */
361 list = listgen; /* and again */
363 wsize = idata_bytes(instruction->opcode);
369 int32_t t = instruction->times;
372 "instruction->times < 0 (%ld) in assemble()", t);
374 while (t--) { /* repeat TIMES times */
375 list_for_each(e, instruction->eops) {
376 if (e->type == EOT_DB_NUMBER) {
378 errfunc(ERR_NONFATAL,
379 "integer supplied to a DT, DO or DY"
382 out(offset, segment, &e->offset,
383 OUT_ADDRESS, wsize, e->segment, e->wrt);
386 } else if (e->type == EOT_DB_STRING ||
387 e->type == EOT_DB_STRING_FREE) {
390 out(offset, segment, e->stringval,
391 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
392 align = e->stringlen % wsize;
395 align = wsize - align;
396 out(offset, segment, zero_buffer,
397 OUT_RAWDATA, align, NO_SEG, NO_SEG);
399 offset += e->stringlen + align;
402 if (t > 0 && t == instruction->times - 1) {
404 * Dummy call to list->output to give the offset to the
407 list->output(offset, NULL, OUT_RAWDATA, 0);
408 list->uplevel(LIST_TIMES);
411 if (instruction->times > 1)
412 list->downlevel(LIST_TIMES);
413 return offset - start;
416 if (instruction->opcode == I_INCBIN) {
417 const char *fname = instruction->eops->stringval;
420 fp = fopen(fname, "rb");
422 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
424 } else if (fseek(fp, 0L, SEEK_END) < 0) {
425 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
428 static char buf[4096];
429 size_t t = instruction->times;
434 if (instruction->eops->next) {
435 base = instruction->eops->next->offset;
437 if (instruction->eops->next->next &&
438 len > (size_t)instruction->eops->next->next->offset)
439 len = (size_t)instruction->eops->next->next->offset;
442 * Dummy call to list->output to give the offset to the
445 list->output(offset, NULL, OUT_RAWDATA, 0);
446 list->uplevel(LIST_INCBIN);
450 fseek(fp, base, SEEK_SET);
454 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
457 * This shouldn't happen unless the file
458 * actually changes while we are reading
462 "`incbin': unexpected EOF while"
463 " reading file `%s'", fname);
464 t = 0; /* Try to exit cleanly */
467 out(offset, segment, buf, OUT_RAWDATA, m,
472 list->downlevel(LIST_INCBIN);
473 if (instruction->times > 1) {
475 * Dummy call to list->output to give the offset to the
478 list->output(offset, NULL, OUT_RAWDATA, 0);
479 list->uplevel(LIST_TIMES);
480 list->downlevel(LIST_TIMES);
483 return instruction->times * len;
485 return 0; /* if we're here, there's an error */
488 /* Check to see if we need an address-size prefix */
489 add_asp(instruction, bits);
491 m = find_match(&temp, instruction, segment, offset, bits);
495 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
496 itimes = instruction->times;
497 if (insn_size < 0) /* shouldn't be, on pass two */
498 error(ERR_PANIC, "errors made it through from pass one");
501 for (j = 0; j < MAXPREFIX; j++) {
503 switch (instruction->prefixes[j]) {
523 error(ERR_WARNING | ERR_PASS2,
524 "cs segment base generated, but will be ignored in 64-bit mode");
530 error(ERR_WARNING | ERR_PASS2,
531 "ds segment base generated, but will be ignored in 64-bit mode");
537 error(ERR_WARNING | ERR_PASS2,
538 "es segment base generated, but will be ignored in 64-bit mode");
550 error(ERR_WARNING | ERR_PASS2,
551 "ss segment base generated, but will be ignored in 64-bit mode");
558 "segr6 and segr7 cannot be used as prefixes");
563 "16-bit addressing is not supported "
565 } else if (bits != 16)
575 "64-bit addressing is only supported "
599 error(ERR_PANIC, "invalid instruction prefix");
602 out(offset, segment, &c, OUT_RAWDATA, 1,
607 insn_end = offset + insn_size;
608 gencode(segment, offset, bits, instruction,
611 if (itimes > 0 && itimes == instruction->times - 1) {
613 * Dummy call to list->output to give the offset to the
616 list->output(offset, NULL, OUT_RAWDATA, 0);
617 list->uplevel(LIST_TIMES);
620 if (instruction->times > 1)
621 list->downlevel(LIST_TIMES);
622 return offset - start;
626 case MERR_OPSIZEMISSING:
627 error(ERR_NONFATAL, "operation size not specified");
629 case MERR_OPSIZEMISMATCH:
630 error(ERR_NONFATAL, "mismatch in operand sizes");
633 error(ERR_NONFATAL, "no instruction for this cpu level");
636 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
641 "invalid combination of opcode and operands");
648 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
649 insn * instruction, efunc error)
651 const struct itemplate *temp;
654 errfunc = error; /* to pass to other functions */
657 if (instruction->opcode == I_none)
660 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
661 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
662 instruction->opcode == I_DT || instruction->opcode == I_DO ||
663 instruction->opcode == I_DY) {
665 int32_t isize, osize, wsize;
668 wsize = idata_bytes(instruction->opcode);
670 list_for_each(e, instruction->eops) {
674 if (e->type == EOT_DB_NUMBER) {
676 warn_overflow_const(e->offset, wsize);
677 } else if (e->type == EOT_DB_STRING ||
678 e->type == EOT_DB_STRING_FREE)
679 osize = e->stringlen;
681 align = (-osize) % wsize;
684 isize += osize + align;
686 return isize * instruction->times;
689 if (instruction->opcode == I_INCBIN) {
690 const char *fname = instruction->eops->stringval;
695 fp = fopen(fname, "rb");
697 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
699 else if (fseek(fp, 0L, SEEK_END) < 0)
700 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
704 if (instruction->eops->next) {
705 len -= instruction->eops->next->offset;
706 if (instruction->eops->next->next &&
707 len > (size_t)instruction->eops->next->next->offset) {
708 len = (size_t)instruction->eops->next->next->offset;
711 val = instruction->times * len;
718 /* Check to see if we need an address-size prefix */
719 add_asp(instruction, bits);
721 m = find_match(&temp, instruction, segment, offset, bits);
723 /* we've matched an instruction. */
727 isize = calcsize(segment, offset, bits, instruction, temp);
730 for (j = 0; j < MAXPREFIX; j++) {
731 switch (instruction->prefixes[j]) {
757 return isize * instruction->times;
759 return -1; /* didn't match any instruction */
763 static void bad_hle_warn(const insn * ins, uint8_t hleok)
765 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
766 enum whatwarn { w_none, w_lock, w_inval } ww;
767 static const enum whatwarn warn[2][4] =
769 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
770 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
774 n = (unsigned int)rep_pfx - P_XACQUIRE;
776 return; /* Not XACQUIRE/XRELEASE */
779 if (!is_class(MEMORY, ins->oprs[0].type))
780 ww = w_inval; /* HLE requires operand 0 to be memory */
787 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
788 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
789 "%s with this instruction requires lock",
790 prefix_name(rep_pfx));
795 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
796 "%s invalid with this instruction",
797 prefix_name(rep_pfx));
802 /* Common construct */
803 #define case3(x) case (x): case (x)+1: case (x)+2
804 #define case4(x) case3(x): case (x)+3
806 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
807 insn * ins, const struct itemplate *temp)
809 const uint8_t *codes = temp->code;
818 bool lockcheck = true;
820 ins->rex = 0; /* Ensure REX is reset */
821 eat = EA_SCALAR; /* Expect a scalar EA */
823 if (ins->prefixes[PPS_OSIZE] == P_O64)
826 (void)segment; /* Don't warn that this parameter is unused */
827 (void)offset; /* Don't warn that this parameter is unused */
831 op1 = (c & 3) + ((opex & 1) << 2);
832 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
833 opx = &ins->oprs[op1];
834 opex = 0; /* For the next iteration */
838 codes += c, length += c;
847 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
861 if (opx->type & (BITS16 | BITS32 | BITS64))
862 length += (opx->type & BITS16) ? 2 : 4;
864 length += (bits == 16) ? 2 : 4;
872 length += ins->addr_size >> 3;
880 length += 8; /* MOV reg64/imm */
888 if (opx->type & (BITS16 | BITS32 | BITS64))
889 length += (opx->type & BITS16) ? 2 : 4;
891 length += (bits == 16) ? 2 : 4;
918 ins->vexreg = regval(opx);
919 ins->vex_cm = *codes++;
920 ins->vex_wlp = *codes++;
926 ins->vex_cm = *codes++;
927 ins->vex_wlp = *codes++;
944 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
948 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
955 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
956 has_prefix(ins, PPS_ASIZE, P_A32))
965 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
969 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
971 ins->prefixes[PPS_OSIZE] = P_O16;
977 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
981 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
983 ins->prefixes[PPS_OSIZE] = P_O32;
1025 if (!ins->prefixes[PPS_REP])
1026 ins->prefixes[PPS_REP] = P_REP;
1030 if (!ins->prefixes[PPS_REP])
1031 ins->prefixes[PPS_REP] = P_REPNE;
1035 if (ins->oprs[0].segment != NO_SEG)
1036 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1037 " quantity of BSS space");
1039 length += ins->oprs[0].offset;
1043 if (!ins->prefixes[PPS_WAIT])
1044 ins->prefixes[PPS_WAIT] = P_WAIT;
1094 struct operand *opy = &ins->oprs[op2];
1096 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1099 /* pick rfield from operand b (opx) */
1100 rflags = regflag(opx);
1101 rfield = nasm_regvals[opx->basereg];
1106 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1107 rfield, rflags) != eat) {
1108 errfunc(ERR_NONFATAL, "invalid effective address");
1111 ins->rex |= ea_data.rex;
1112 length += ea_data.size;
1118 errfunc(ERR_PANIC, "internal instruction table corrupt"
1119 ": instruction code \\%o (0x%02X) given", c, c);
1124 ins->rex &= rex_mask;
1126 if (ins->rex & REX_NH) {
1127 if (ins->rex & REX_H) {
1128 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1131 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1134 if (ins->rex & REX_V) {
1135 int bad32 = REX_R|REX_W|REX_X|REX_B;
1137 if (ins->rex & REX_H) {
1138 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1141 switch (ins->vex_wlp & 060) {
1155 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1156 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1159 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1163 } else if (ins->rex & REX_REAL) {
1164 if (ins->rex & REX_H) {
1165 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1167 } else if (bits == 64) {
1169 } else if ((ins->rex & REX_L) &&
1170 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1173 assert_no_prefix(ins, PPS_LOCK);
1174 lockcheck = false; /* Already errored, no need for warning */
1177 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1182 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1183 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1184 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1185 "instruction is not lockable");
1188 bad_hle_warn(ins, hleok);
1193 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1196 if ((ins->rex & REX_REAL) && !(ins->rex & REX_V)) {
1197 ins->rex = (ins->rex & REX_REAL) | REX_P;
1198 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1207 static void gencode(int32_t segment, int64_t offset, int bits,
1208 insn * ins, const struct itemplate *temp,
1216 struct operand *opx;
1217 const uint8_t *codes = temp->code;
1219 enum ea_type eat = EA_SCALAR;
1223 op1 = (c & 3) + ((opex & 1) << 2);
1224 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1225 opx = &ins->oprs[op1];
1226 opex = 0; /* For the next iteration */
1233 offset += emit_rex(ins, segment, offset, bits);
1234 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1246 offset += emit_rex(ins, segment, offset, bits);
1247 bytes[0] = *codes++ + (regval(opx) & 7);
1248 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1253 if (opx->offset < -256 || opx->offset > 255) {
1254 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1255 "byte value exceeds bounds");
1257 out_imm8(offset, segment, opx);
1262 if (opx->offset < 0 || opx->offset > 255)
1263 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1264 "unsigned byte value exceeds bounds");
1265 out_imm8(offset, segment, opx);
1270 warn_overflow_opd(opx, 2);
1272 out(offset, segment, &data, OUT_ADDRESS, 2,
1273 opx->segment, opx->wrt);
1278 if (opx->type & (BITS16 | BITS32))
1279 size = (opx->type & BITS16) ? 2 : 4;
1281 size = (bits == 16) ? 2 : 4;
1282 warn_overflow_opd(opx, size);
1284 out(offset, segment, &data, OUT_ADDRESS, size,
1285 opx->segment, opx->wrt);
1290 warn_overflow_opd(opx, 4);
1292 out(offset, segment, &data, OUT_ADDRESS, 4,
1293 opx->segment, opx->wrt);
1299 size = ins->addr_size >> 3;
1300 warn_overflow_opd(opx, size);
1301 out(offset, segment, &data, OUT_ADDRESS, size,
1302 opx->segment, opx->wrt);
1307 if (opx->segment != segment) {
1309 out(offset, segment, &data,
1310 OUT_REL1ADR, insn_end - offset,
1311 opx->segment, opx->wrt);
1313 data = opx->offset - insn_end;
1314 if (data > 127 || data < -128)
1315 errfunc(ERR_NONFATAL, "short jump is out of range");
1316 out(offset, segment, &data,
1317 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1323 data = (int64_t)opx->offset;
1324 out(offset, segment, &data, OUT_ADDRESS, 8,
1325 opx->segment, opx->wrt);
1330 if (opx->segment != segment) {
1332 out(offset, segment, &data,
1333 OUT_REL2ADR, insn_end - offset,
1334 opx->segment, opx->wrt);
1336 data = opx->offset - insn_end;
1337 out(offset, segment, &data,
1338 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1344 if (opx->type & (BITS16 | BITS32 | BITS64))
1345 size = (opx->type & BITS16) ? 2 : 4;
1347 size = (bits == 16) ? 2 : 4;
1348 if (opx->segment != segment) {
1350 out(offset, segment, &data,
1351 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1352 insn_end - offset, opx->segment, opx->wrt);
1354 data = opx->offset - insn_end;
1355 out(offset, segment, &data,
1356 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1362 if (opx->segment != segment) {
1364 out(offset, segment, &data,
1365 OUT_REL4ADR, insn_end - offset,
1366 opx->segment, opx->wrt);
1368 data = opx->offset - insn_end;
1369 out(offset, segment, &data,
1370 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1376 if (opx->segment == NO_SEG)
1377 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1380 out(offset, segment, &data, OUT_ADDRESS, 2,
1381 outfmt->segbase(1 + opx->segment),
1388 opx = &ins->oprs[c >> 3];
1389 bytes[0] = nasm_regvals[opx->basereg] << 4;
1390 opx = &ins->oprs[c & 7];
1391 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1392 errfunc(ERR_NONFATAL,
1393 "non-absolute expression not permitted as argument %d",
1396 if (opx->offset & ~15) {
1397 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1398 "four-bit argument exceeds bounds");
1400 bytes[0] |= opx->offset & 15;
1402 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1408 opx = &ins->oprs[c >> 4];
1409 bytes[0] = nasm_regvals[opx->basereg] << 4;
1411 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1416 bytes[0] = nasm_regvals[opx->basereg] << 4;
1417 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1423 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1424 (int32_t)data != (int64_t)data) {
1425 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1426 "signed dword immediate exceeds bounds");
1428 out(offset, segment, &data, OUT_ADDRESS, 4,
1429 opx->segment, opx->wrt);
1436 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1437 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1438 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1439 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1440 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1441 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1445 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1446 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1447 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1462 if (ins->rex & REX_W)
1464 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1466 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1471 um = (uint64_t)2 << (s-1);
1474 if (uv > 127 && uv < (uint64_t)-128 &&
1475 (uv < um-128 || uv > um-1)) {
1476 /* If this wasn't explicitly byte-sized, warn as though we
1477 * had fallen through to the imm16/32/64 case.
1479 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1480 "%s value exceeds bounds",
1481 (opx->type & BITS8) ? "signed byte" :
1486 if (opx->segment != NO_SEG) {
1488 out(offset, segment, &data, OUT_ADDRESS, 1,
1489 opx->segment, opx->wrt);
1492 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1503 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1505 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1512 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1514 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1549 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1550 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1559 *bytes = c - 0332 + 0xF2;
1560 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1565 if (ins->rex & REX_R) {
1567 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1570 ins->rex &= ~(REX_L|REX_R);
1581 if (ins->oprs[0].segment != NO_SEG)
1582 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1584 int64_t size = ins->oprs[0].offset;
1586 out(offset, segment, NULL,
1587 OUT_RESERVE, size, NO_SEG, NO_SEG);
1600 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1610 *bytes = c - 0366 + 0x66;
1611 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1620 *bytes = bits == 16 ? 3 : 5;
1621 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1651 struct operand *opy = &ins->oprs[op2];
1654 /* pick rfield from operand b (opx) */
1655 rflags = regflag(opx);
1656 rfield = nasm_regvals[opx->basereg];
1658 /* rfield is constant */
1663 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1664 rfield, rflags) != eat)
1665 errfunc(ERR_NONFATAL, "invalid effective address");
1668 *p++ = ea_data.modrm;
1669 if (ea_data.sib_present)
1673 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1676 * Make sure the address gets the right offset in case
1677 * the line breaks in the .lst file (BR 1197827)
1682 switch (ea_data.bytes) {
1692 if (opy->segment == segment) {
1694 if (overflow_signed(data, ea_data.bytes))
1695 warn_overflow(ERR_PASS2, ea_data.bytes);
1696 out(offset, segment, &data, OUT_ADDRESS,
1697 ea_data.bytes, NO_SEG, NO_SEG);
1699 /* overflow check in output/linker? */
1700 out(offset, segment, &data, OUT_REL4ADR,
1701 insn_end - offset, opy->segment, opy->wrt);
1704 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1705 signed_bits(opy->offset, ins->addr_size) !=
1706 signed_bits(opy->offset, ea_data.bytes * 8))
1707 warn_overflow(ERR_PASS2, ea_data.bytes);
1709 out(offset, segment, &data, OUT_ADDRESS,
1710 ea_data.bytes, opy->segment, opy->wrt);
1716 "Invalid amount of bytes (%d) for offset?!",
1725 errfunc(ERR_PANIC, "internal instruction table corrupt"
1726 ": instruction code \\%o (0x%02X) given", c, c);
1732 static opflags_t regflag(const operand * o)
1734 if (!is_register(o->basereg))
1735 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1736 return nasm_reg_flags[o->basereg];
1739 static int32_t regval(const operand * o)
1741 if (!is_register(o->basereg))
1742 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1743 return nasm_regvals[o->basereg];
1746 static int op_rexflags(const operand * o, int mask)
1751 if (!is_register(o->basereg))
1752 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1754 flags = nasm_reg_flags[o->basereg];
1755 val = nasm_regvals[o->basereg];
1757 return rexflags(val, flags, mask);
1760 static int rexflags(int val, opflags_t flags, int mask)
1765 rex |= REX_B|REX_X|REX_R;
1768 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1770 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1776 static enum match_result find_match(const struct itemplate **tempp,
1778 int32_t segment, int64_t offset, int bits)
1780 const struct itemplate *temp;
1781 enum match_result m, merr;
1782 opflags_t xsizeflags[MAX_OPERANDS];
1783 bool opsizemissing = false;
1786 for (i = 0; i < instruction->operands; i++)
1787 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1789 merr = MERR_INVALOP;
1791 for (temp = nasm_instructions[instruction->opcode];
1792 temp->opcode != I_none; temp++) {
1793 m = matches(temp, instruction, bits);
1794 if (m == MOK_JUMP) {
1795 if (jmp_match(segment, offset, bits, instruction, temp))
1799 } else if (m == MERR_OPSIZEMISSING &&
1800 (temp->flags & IF_SMASK) != IF_SX) {
1802 * Missing operand size and a candidate for fuzzy matching...
1804 for (i = 0; i < temp->operands; i++)
1805 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1806 opsizemissing = true;
1810 if (merr == MOK_GOOD)
1814 /* No match, but see if we can get a fuzzy operand size match... */
1818 for (i = 0; i < instruction->operands; i++) {
1820 * We ignore extrinsic operand sizes on registers, so we should
1821 * never try to fuzzy-match on them. This also resolves the case
1822 * when we have e.g. "xmmrm128" in two different positions.
1824 if (is_class(REGISTER, instruction->oprs[i].type))
1827 /* This tests if xsizeflags[i] has more than one bit set */
1828 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1829 goto done; /* No luck */
1831 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1834 /* Try matching again... */
1835 for (temp = nasm_instructions[instruction->opcode];
1836 temp->opcode != I_none; temp++) {
1837 m = matches(temp, instruction, bits);
1838 if (m == MOK_JUMP) {
1839 if (jmp_match(segment, offset, bits, instruction, temp))
1846 if (merr == MOK_GOOD)
1855 static enum match_result matches(const struct itemplate *itemp,
1856 insn *instruction, int bits)
1858 opflags_t size[MAX_OPERANDS], asize;
1859 bool opsizemissing = false;
1865 if (itemp->opcode != instruction->opcode)
1866 return MERR_INVALOP;
1869 * Count the operands
1871 if (itemp->operands != instruction->operands)
1872 return MERR_INVALOP;
1877 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
1878 return MERR_INVALOP;
1881 * Check that no spurious colons or TOs are present
1883 for (i = 0; i < itemp->operands; i++)
1884 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1885 return MERR_INVALOP;
1888 * Process size flags
1890 switch (itemp->flags & IF_SMASK) {
1930 if (itemp->flags & IF_ARMASK) {
1931 /* S- flags only apply to a specific operand */
1932 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1933 memset(size, 0, sizeof size);
1936 /* S- flags apply to all operands */
1937 for (i = 0; i < MAX_OPERANDS; i++)
1942 * Check that the operand flags all match up,
1943 * it's a bit tricky so lets be verbose:
1945 * 1) Find out the size of operand. If instruction
1946 * doesn't have one specified -- we're trying to
1947 * guess it either from template (IF_S* flag) or
1950 * 2) If template operand do not match the instruction OR
1951 * template has an operand size specified AND this size differ
1952 * from which instruction has (perhaps we got it from code bits)
1954 * a) Check that only size of instruction and operand is differ
1955 * other characteristics do match
1956 * b) Perhaps it's a register specified in instruction so
1957 * for such a case we just mark that operand as "size
1958 * missing" and this will turn on fuzzy operand size
1959 * logic facility (handled by a caller)
1961 for (i = 0; i < itemp->operands; i++) {
1962 opflags_t type = instruction->oprs[i].type;
1963 if (!(type & SIZE_MASK))
1966 if (itemp->opd[i] & ~type & ~SIZE_MASK) {
1967 return MERR_INVALOP;
1968 } else if ((itemp->opd[i] & SIZE_MASK) &&
1969 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
1970 if (type & SIZE_MASK) {
1971 return MERR_INVALOP;
1972 } else if (!is_class(REGISTER, type)) {
1974 * Note: we don't honor extrinsic operand sizes for registers,
1975 * so "missing operand size" for a register should be
1976 * considered a wildcard match rather than an error.
1978 opsizemissing = true;
1984 return MERR_OPSIZEMISSING;
1987 * Check operand sizes
1989 if (itemp->flags & (IF_SM | IF_SM2)) {
1990 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
1991 for (i = 0; i < oprs; i++) {
1992 asize = itemp->opd[i] & SIZE_MASK;
1994 for (i = 0; i < oprs; i++)
2000 oprs = itemp->operands;
2003 for (i = 0; i < itemp->operands; i++) {
2004 if (!(itemp->opd[i] & SIZE_MASK) &&
2005 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2006 return MERR_OPSIZEMISMATCH;
2010 * Check template is okay at the set cpu level
2012 if (((itemp->flags & IF_PLEVEL) > cpu))
2016 * Verify the appropriate long mode flag.
2018 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2019 return MERR_BADMODE;
2022 * If we have a HLE prefix, look for the NOHLE flag
2024 if ((itemp->flags & IF_NOHLE) &&
2025 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2026 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2030 * Check if special handling needed for Jumps
2032 if ((itemp->code[0] & ~1) == 0370)
2038 static enum ea_type process_ea(operand *input, ea *output, int bits,
2039 int addrbits, int rfield, opflags_t rflags)
2041 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2043 output->type = EA_SCALAR;
2044 output->rip = false;
2046 /* REX flags for the rfield operand */
2047 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2049 if (is_class(REGISTER, input->type)) {
2051 * It's a direct register.
2053 if (!is_register(input->basereg))
2056 if (!is_class(REG_EA, regflag(input)))
2059 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2060 output->sib_present = false; /* no SIB necessary */
2061 output->bytes = 0; /* no offset necessary either */
2062 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2065 * It's a memory reference.
2067 if (input->basereg == -1 &&
2068 (input->indexreg == -1 || input->scale == 0)) {
2070 * It's a pure offset.
2072 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2073 input->segment == NO_SEG) {
2074 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2075 input->type &= ~IP_REL;
2076 input->type |= MEMORY;
2079 if (input->eaflags & EAF_BYTEOFFS ||
2080 (input->eaflags & EAF_WORDOFFS &&
2081 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2082 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2085 if (bits == 64 && (~input->type & IP_REL)) {
2086 output->sib_present = true;
2087 output->sib = GEN_SIB(0, 4, 5);
2089 output->modrm = GEN_MODRM(0, rfield, 4);
2090 output->rip = false;
2092 output->sib_present = false;
2093 output->bytes = (addrbits != 16 ? 4 : 2);
2094 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2095 output->rip = bits == 64;
2099 * It's an indirection.
2101 int i = input->indexreg, b = input->basereg, s = input->scale;
2102 int32_t seg = input->segment;
2103 int hb = input->hintbase, ht = input->hinttype;
2104 int t, it, bt; /* register numbers */
2105 opflags_t x, ix, bx; /* register flags */
2108 i = -1; /* make this easy, at least */
2110 if (is_register(i)) {
2111 it = nasm_regvals[i];
2112 ix = nasm_reg_flags[i];
2118 if (is_register(b)) {
2119 bt = nasm_regvals[b];
2120 bx = nasm_reg_flags[b];
2126 /* if either one are a vector register... */
2127 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2128 opflags_t sok = BITS32 | BITS64;
2129 int32_t o = input->offset;
2130 int mod, scale, index, base;
2133 * For a vector SIB, one has to be a vector and the other,
2134 * if present, a GPR. The vector must be the index operand.
2136 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2142 t = bt, bt = it, it = t;
2143 x = bx, bx = ix, ix = x;
2149 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2156 * While we're here, ensure the user didn't specify
2159 if (input->disp_size == 16 || input->disp_size == 64)
2162 if (addrbits == 16 ||
2163 (addrbits == 32 && !(sok & BITS32)) ||
2164 (addrbits == 64 && !(sok & BITS64)))
2167 output->type = (ix & YMMREG & ~REG_EA)
2168 ? EA_YMMVSIB : EA_XMMVSIB;
2170 output->rex |= rexflags(it, ix, REX_X);
2171 output->rex |= rexflags(bt, bx, REX_B);
2173 index = it & 7; /* it is known to be != -1 */
2188 default: /* then what the smeg is it? */
2189 goto err; /* panic */
2197 if (base != REG_NUM_EBP && o == 0 &&
2198 seg == NO_SEG && !forw_ref &&
2199 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2201 else if (input->eaflags & EAF_BYTEOFFS ||
2202 (o >= -128 && o <= 127 &&
2203 seg == NO_SEG && !forw_ref &&
2204 !(input->eaflags & EAF_WORDOFFS)))
2210 output->sib_present = true;
2211 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2212 output->modrm = GEN_MODRM(mod, rfield, 4);
2213 output->sib = GEN_SIB(scale, index, base);
2214 } else if ((ix|bx) & (BITS32|BITS64)) {
2216 * it must be a 32/64-bit memory reference. Firstly we have
2217 * to check that all registers involved are type E/Rxx.
2219 opflags_t sok = BITS32 | BITS64;
2220 int32_t o = input->offset;
2223 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2231 goto err; /* Invalid register */
2232 if (~sok & bx & SIZE_MASK)
2233 goto err; /* Invalid size */
2238 * While we're here, ensure the user didn't specify
2241 if (input->disp_size == 16 || input->disp_size == 64)
2244 if (addrbits == 16 ||
2245 (addrbits == 32 && !(sok & BITS32)) ||
2246 (addrbits == 64 && !(sok & BITS64)))
2249 /* now reorganize base/index */
2250 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2251 ((hb == b && ht == EAH_NOTBASE) ||
2252 (hb == i && ht == EAH_MAKEBASE))) {
2253 /* swap if hints say so */
2254 t = bt, bt = it, it = t;
2255 x = bx, bx = ix, ix = x;
2257 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2258 bt = -1, bx = 0, s++;
2259 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2260 /* make single reg base, unless hint */
2261 bt = it, bx = ix, it = -1, ix = 0;
2263 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2264 s == 3 || s == 5 || s == 9) && bt == -1)
2265 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2266 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2267 (input->eaflags & EAF_TIMESTWO))
2268 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2269 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2270 if (s == 1 && it == REG_NUM_ESP) {
2271 /* swap ESP into base if scale is 1 */
2272 t = it, it = bt, bt = t;
2273 x = ix, ix = bx, bx = x;
2275 if (it == REG_NUM_ESP ||
2276 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2277 goto err; /* wrong, for various reasons */
2279 output->rex |= rexflags(it, ix, REX_X);
2280 output->rex |= rexflags(bt, bx, REX_B);
2282 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2291 if (rm != REG_NUM_EBP && o == 0 &&
2292 seg == NO_SEG && !forw_ref &&
2293 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2295 else if (input->eaflags & EAF_BYTEOFFS ||
2296 (o >= -128 && o <= 127 &&
2297 seg == NO_SEG && !forw_ref &&
2298 !(input->eaflags & EAF_WORDOFFS)))
2304 output->sib_present = false;
2305 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2306 output->modrm = GEN_MODRM(mod, rfield, rm);
2309 int mod, scale, index, base;
2329 default: /* then what the smeg is it? */
2330 goto err; /* panic */
2338 if (base != REG_NUM_EBP && o == 0 &&
2339 seg == NO_SEG && !forw_ref &&
2340 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2342 else if (input->eaflags & EAF_BYTEOFFS ||
2343 (o >= -128 && o <= 127 &&
2344 seg == NO_SEG && !forw_ref &&
2345 !(input->eaflags & EAF_WORDOFFS)))
2351 output->sib_present = true;
2352 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2353 output->modrm = GEN_MODRM(mod, rfield, 4);
2354 output->sib = GEN_SIB(scale, index, base);
2356 } else { /* it's 16-bit */
2358 int16_t o = input->offset;
2360 /* check for 64-bit long mode */
2364 /* check all registers are BX, BP, SI or DI */
2365 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2366 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2369 /* ensure the user didn't specify DWORD/QWORD */
2370 if (input->disp_size == 32 || input->disp_size == 64)
2373 if (s != 1 && i != -1)
2374 goto err; /* no can do, in 16-bit EA */
2375 if (b == -1 && i != -1) {
2380 if ((b == R_SI || b == R_DI) && i != -1) {
2385 /* have BX/BP as base, SI/DI index */
2387 goto err; /* shouldn't ever happen, in theory */
2388 if (i != -1 && b != -1 &&
2389 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2390 goto err; /* invalid combinations */
2391 if (b == -1) /* pure offset: handled above */
2392 goto err; /* so if it gets to here, panic! */
2396 switch (i * 256 + b) {
2397 case R_SI * 256 + R_BX:
2400 case R_DI * 256 + R_BX:
2403 case R_SI * 256 + R_BP:
2406 case R_DI * 256 + R_BP:
2424 if (rm == -1) /* can't happen, in theory */
2425 goto err; /* so panic if it does */
2427 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2428 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2430 else if (input->eaflags & EAF_BYTEOFFS ||
2431 (o >= -128 && o <= 127 && seg == NO_SEG &&
2432 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2437 output->sib_present = false; /* no SIB - it's 16-bit */
2438 output->bytes = mod; /* bytes of offset needed */
2439 output->modrm = GEN_MODRM(mod, rfield, rm);
2444 output->size = 1 + output->sib_present + output->bytes;
2445 return output->type;
2448 return output->type = EA_INVALID;
2451 static void add_asp(insn *ins, int addrbits)
2456 valid = (addrbits == 64) ? 64|32 : 32|16;
2458 switch (ins->prefixes[PPS_ASIZE]) {
2469 valid &= (addrbits == 32) ? 16 : 32;
2475 for (j = 0; j < ins->operands; j++) {
2476 if (is_class(MEMORY, ins->oprs[j].type)) {
2479 /* Verify as Register */
2480 if (!is_register(ins->oprs[j].indexreg))
2483 i = nasm_reg_flags[ins->oprs[j].indexreg];
2485 /* Verify as Register */
2486 if (!is_register(ins->oprs[j].basereg))
2489 b = nasm_reg_flags[ins->oprs[j].basereg];
2491 if (ins->oprs[j].scale == 0)
2495 int ds = ins->oprs[j].disp_size;
2496 if ((addrbits != 64 && ds > 8) ||
2497 (addrbits == 64 && ds == 16))
2517 if (valid & addrbits) {
2518 ins->addr_size = addrbits;
2519 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2520 /* Add an address size prefix */
2521 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2522 ins->addr_size = (addrbits == 32) ? 16 : 32;
2525 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2526 ins->addr_size = addrbits; /* Error recovery */
2529 defdisp = ins->addr_size == 16 ? 16 : 32;
2531 for (j = 0; j < ins->operands; j++) {
2532 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2533 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2535 * mem_offs sizes must match the address size; if not,
2536 * strip the MEM_OFFS bit and match only EA instructions
2538 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);