1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - a signed byte immediate operand, from operand 0..3
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \140..\143 - an immediate word or signed byte for operand 0..3
64 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
65 * is a signed byte rather than a word. Opcode byte follows.
66 * \150..\153 - an immediate dword or signed byte for operand 0..3
67 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
68 * is a signed byte rather than a dword. Opcode byte follows.
69 * \172\ab - the register number from operand a in bits 7..4, with
70 * the 4-bit immediate from operand b in bits 3..0.
71 * \173\xab - the register number from operand a in bits 7..4, with
72 * the value b in bits 3..0.
73 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
74 * an arbitrary value in bits 3..0 (assembled as zero.)
75 * \2ab - a ModRM, calculated on EA in operand a, with the spare
76 * field equal to digit b.
77 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
78 * is not equal to the truncated and sign-extended 32-bit
79 * operand; used for 32-bit immediates in 64-bit mode.
80 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
81 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
82 * V field taken from operand 0..3.
83 * \264 - skip this instruction pattern if HLE prefixes present
84 * \265 - instruction takes XRELEASE (F3) with or without lock
85 * \266 - instruction takes XACQUIRE/XRELEASE with or without lock
86 * \267 - instruction takes XACQUIRE/XRELEASE with lock only
87 * \270 - this instruction uses VEX/XOP rather than REX, with the
88 * V field set to 1111b.
90 * VEX/XOP prefixes are followed by the sequence:
91 * \tmm\wlp where mm is the M field; and wlp is:
93 * [l0] ll = 0 for L = 0 (.128, .lz)
94 * [l1] ll = 1 for L = 1 (.256)
95 * [lig] ll = 2 for L don't care (always assembled as 0)
97 * [w0] ww = 0 for W = 0
98 * [w1 ] ww = 1 for W = 1
99 * [wig] ww = 2 for W don't care (always assembled as 0)
100 * [ww] ww = 3 for W used as REX.W
102 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
104 * \274..\277 - a signed byte immediate operand, from operand 0..3,
105 * which is to be extended to the operand size.
106 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
107 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
108 * \312 - (disassembler only) invalid with non-default address size.
109 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
110 * \314 - (disassembler only) invalid with REX.B
111 * \315 - (disassembler only) invalid with REX.X
112 * \316 - (disassembler only) invalid with REX.R
113 * \317 - (disassembler only) invalid with REX.W
114 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
115 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
116 * \322 - indicates that this instruction is only valid when the
117 * operand size is the default (instruction to disassembler,
118 * generates no code in the assembler)
119 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
120 * \324 - indicates 64-bit operand size requiring REX prefix.
121 * \325 - instruction which always uses spl/bpl/sil/dil
122 * \330 - a literal byte follows in the code stream, to be added
123 * to the condition code value of the instruction.
124 * \331 - instruction not valid with REP prefix. Hint for
125 * disassembler only; for SSE instructions.
126 * \332 - REP prefix (0xF2 byte) used as opcode extension.
127 * \333 - REP prefix (0xF3 byte) used as opcode extension.
128 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
129 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
130 * \336 - force a REP(E) prefix (0xF2) even if not specified.
131 * \337 - force a REPNE prefix (0xF3) even if not specified.
132 * \336-\337 are still listed as prefixes in the disassembler.
133 * \340 - reserve <operand 0> bytes of uninitialized storage.
134 * Operand 0 had better be a segmentless constant.
135 * \341 - this instruction needs a WAIT "prefix"
136 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
137 * (POP is never used for CS) depending on operand 0
138 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
140 * \360 - no SSE prefix (== \364\331)
141 * \361 - 66 SSE prefix (== \366\331)
142 * \362 - F2 SSE prefix (== \364\332)
143 * \363 - F3 SSE prefix (== \364\333)
144 * \364 - operand-size prefix (0x66) not permitted
145 * \365 - address-size prefix (0x67) not permitted
146 * \366 - operand-size prefix (0x66) used as opcode extension
147 * \367 - address-size prefix (0x67) used as opcode extension
148 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
149 * 370 is used for Jcc, 371 is used for JMP.
150 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
151 * used for conditional jump over longer jump
152 * \374 - this instruction takes an XMM VSIB memory EA
153 * \375 - this instruction takes an YMM VSIB memory EA
156 #include "compiler.h"
160 #include <inttypes.h>
164 #include "assemble.h"
170 * Matching errors. These should be sorted so that more specific
171 * errors come later in the sequence.
179 * Matching success; the conditional ones first
181 MOK_JUMP, /* Matching OK but needs jmp_match() */
182 MOK_GOOD /* Matching unconditionally OK */
186 enum ea_type type; /* what kind of EA is this? */
187 int sib_present; /* is a SIB byte necessary? */
188 int bytes; /* # of bytes of offset needed */
189 int size; /* lazy - this is sib+bytes+1 */
190 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
193 #define GEN_SIB(scale, index, base) \
194 (((scale) << 6) | ((index) << 3) | ((base)))
196 #define GEN_MODRM(mod, reg, rm) \
197 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
199 static uint32_t cpu; /* cpu level received from nasm.c */
200 static efunc errfunc;
201 static struct ofmt *outfmt;
202 static ListGen *list;
204 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
205 static void gencode(int32_t segment, int64_t offset, int bits,
206 insn * ins, const struct itemplate *temp,
208 static enum match_result find_match(const struct itemplate **tempp,
210 int32_t segment, int64_t offset, int bits);
211 static enum match_result matches(const struct itemplate *, insn *, int bits);
212 static opflags_t regflag(const operand *);
213 static int32_t regval(const operand *);
214 static int rexflags(int, opflags_t, int);
215 static int op_rexflags(const operand *, int);
216 static void add_asp(insn *, int);
218 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
220 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
222 return ins->prefixes[pos] == prefix;
225 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
227 if (ins->prefixes[pos])
228 errfunc(ERR_NONFATAL, "invalid %s prefix",
229 prefix_name(ins->prefixes[pos]));
232 static const char *size_name(int size)
254 static void warn_overflow(int pass, int size)
256 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
257 "%s data exceeds bounds", size_name(size));
260 static void warn_overflow_const(int64_t data, int size)
262 if (overflow_general(data, size))
263 warn_overflow(ERR_PASS1, size);
266 static void warn_overflow_opd(const struct operand *o, int size)
268 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
269 if (overflow_general(o->offset, size))
270 warn_overflow(ERR_PASS2, size);
275 * This routine wrappers the real output format's output routine,
276 * in order to pass a copy of the data off to the listing file
277 * generator at the same time.
279 static void out(int64_t offset, int32_t segto, const void *data,
280 enum out_type type, uint64_t size,
281 int32_t segment, int32_t wrt)
283 static int32_t lineno = 0; /* static!!! */
284 static char *lnfname = NULL;
287 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
289 * This is a non-relocated address, and we're going to
290 * convert it into RAWDATA format.
295 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
299 WRITEADDR(q, *(int64_t *)data, size);
304 list->output(offset, data, type, size);
307 * this call to src_get determines when we call the
308 * debug-format-specific "linenum" function
309 * it updates lineno and lnfname to the current values
310 * returning 0 if "same as last time", -2 if lnfname
311 * changed, and the amount by which lineno changed,
312 * if it did. thus, these variables must be static
315 if (src_get(&lineno, &lnfname))
316 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
318 outfmt->output(segto, data, type, size, segment, wrt);
321 static bool jmp_match(int32_t segment, int64_t offset, int bits,
322 insn * ins, const uint8_t *code)
327 if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT))
331 if (optimizing < 0 && c == 0371)
334 isize = calcsize(segment, offset, bits, ins, code);
336 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
337 /* Be optimistic in pass 1 */
340 if (ins->oprs[0].segment != segment)
343 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
344 return (isize >= -128 && isize <= 127); /* is it byte size? */
347 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
348 insn * instruction, struct ofmt *output, efunc error,
351 const struct itemplate *temp;
356 int64_t start = offset;
357 int64_t wsize; /* size for DB etc. */
359 errfunc = error; /* to pass to other functions */
361 outfmt = output; /* likewise */
362 list = listgen; /* and again */
364 wsize = idata_bytes(instruction->opcode);
370 int32_t t = instruction->times;
373 "instruction->times < 0 (%ld) in assemble()", t);
375 while (t--) { /* repeat TIMES times */
376 list_for_each(e, instruction->eops) {
377 if (e->type == EOT_DB_NUMBER) {
379 errfunc(ERR_NONFATAL,
380 "integer supplied to a DT, DO or DY"
383 out(offset, segment, &e->offset,
384 OUT_ADDRESS, wsize, e->segment, e->wrt);
387 } else if (e->type == EOT_DB_STRING ||
388 e->type == EOT_DB_STRING_FREE) {
391 out(offset, segment, e->stringval,
392 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
393 align = e->stringlen % wsize;
396 align = wsize - align;
397 out(offset, segment, zero_buffer,
398 OUT_RAWDATA, align, NO_SEG, NO_SEG);
400 offset += e->stringlen + align;
403 if (t > 0 && t == instruction->times - 1) {
405 * Dummy call to list->output to give the offset to the
408 list->output(offset, NULL, OUT_RAWDATA, 0);
409 list->uplevel(LIST_TIMES);
412 if (instruction->times > 1)
413 list->downlevel(LIST_TIMES);
414 return offset - start;
417 if (instruction->opcode == I_INCBIN) {
418 const char *fname = instruction->eops->stringval;
421 fp = fopen(fname, "rb");
423 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
425 } else if (fseek(fp, 0L, SEEK_END) < 0) {
426 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
429 static char buf[4096];
430 size_t t = instruction->times;
435 if (instruction->eops->next) {
436 base = instruction->eops->next->offset;
438 if (instruction->eops->next->next &&
439 len > (size_t)instruction->eops->next->next->offset)
440 len = (size_t)instruction->eops->next->next->offset;
443 * Dummy call to list->output to give the offset to the
446 list->output(offset, NULL, OUT_RAWDATA, 0);
447 list->uplevel(LIST_INCBIN);
451 fseek(fp, base, SEEK_SET);
455 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
458 * This shouldn't happen unless the file
459 * actually changes while we are reading
463 "`incbin': unexpected EOF while"
464 " reading file `%s'", fname);
465 t = 0; /* Try to exit cleanly */
468 out(offset, segment, buf, OUT_RAWDATA, m,
473 list->downlevel(LIST_INCBIN);
474 if (instruction->times > 1) {
476 * Dummy call to list->output to give the offset to the
479 list->output(offset, NULL, OUT_RAWDATA, 0);
480 list->uplevel(LIST_TIMES);
481 list->downlevel(LIST_TIMES);
484 return instruction->times * len;
486 return 0; /* if we're here, there's an error */
489 /* Check to see if we need an address-size prefix */
490 add_asp(instruction, bits);
492 m = find_match(&temp, instruction, segment, offset, bits);
496 int64_t insn_size = calcsize(segment, offset, bits,
497 instruction, temp->code);
498 itimes = instruction->times;
499 if (insn_size < 0) /* shouldn't be, on pass two */
500 error(ERR_PANIC, "errors made it through from pass one");
503 for (j = 0; j < MAXPREFIX; j++) {
505 switch (instruction->prefixes[j]) {
525 error(ERR_WARNING | ERR_PASS2,
526 "cs segment base generated, but will be ignored in 64-bit mode");
532 error(ERR_WARNING | ERR_PASS2,
533 "ds segment base generated, but will be ignored in 64-bit mode");
539 error(ERR_WARNING | ERR_PASS2,
540 "es segment base generated, but will be ignored in 64-bit mode");
552 error(ERR_WARNING | ERR_PASS2,
553 "ss segment base generated, but will be ignored in 64-bit mode");
560 "segr6 and segr7 cannot be used as prefixes");
565 "16-bit addressing is not supported "
567 } else if (bits != 16)
577 "64-bit addressing is only supported "
601 error(ERR_PANIC, "invalid instruction prefix");
604 out(offset, segment, &c, OUT_RAWDATA, 1,
609 insn_end = offset + insn_size;
610 gencode(segment, offset, bits, instruction,
613 if (itimes > 0 && itimes == instruction->times - 1) {
615 * Dummy call to list->output to give the offset to the
618 list->output(offset, NULL, OUT_RAWDATA, 0);
619 list->uplevel(LIST_TIMES);
622 if (instruction->times > 1)
623 list->downlevel(LIST_TIMES);
624 return offset - start;
628 case MERR_OPSIZEMISSING:
629 error(ERR_NONFATAL, "operation size not specified");
631 case MERR_OPSIZEMISMATCH:
632 error(ERR_NONFATAL, "mismatch in operand sizes");
635 error(ERR_NONFATAL, "no instruction for this cpu level");
638 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
643 "invalid combination of opcode and operands");
650 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
651 insn * instruction, efunc error)
653 const struct itemplate *temp;
656 errfunc = error; /* to pass to other functions */
659 if (instruction->opcode == I_none)
662 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
663 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
664 instruction->opcode == I_DT || instruction->opcode == I_DO ||
665 instruction->opcode == I_DY) {
667 int32_t isize, osize, wsize;
670 wsize = idata_bytes(instruction->opcode);
672 list_for_each(e, instruction->eops) {
676 if (e->type == EOT_DB_NUMBER) {
678 warn_overflow_const(e->offset, wsize);
679 } else if (e->type == EOT_DB_STRING ||
680 e->type == EOT_DB_STRING_FREE)
681 osize = e->stringlen;
683 align = (-osize) % wsize;
686 isize += osize + align;
688 return isize * instruction->times;
691 if (instruction->opcode == I_INCBIN) {
692 const char *fname = instruction->eops->stringval;
697 fp = fopen(fname, "rb");
699 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
701 else if (fseek(fp, 0L, SEEK_END) < 0)
702 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
706 if (instruction->eops->next) {
707 len -= instruction->eops->next->offset;
708 if (instruction->eops->next->next &&
709 len > (size_t)instruction->eops->next->next->offset) {
710 len = (size_t)instruction->eops->next->next->offset;
713 val = instruction->times * len;
720 /* Check to see if we need an address-size prefix */
721 add_asp(instruction, bits);
723 m = find_match(&temp, instruction, segment, offset, bits);
725 /* we've matched an instruction. */
727 const uint8_t *codes = temp->code;
730 isize = calcsize(segment, offset, bits, instruction, codes);
733 for (j = 0; j < MAXPREFIX; j++) {
734 switch (instruction->prefixes[j]) {
760 return isize * instruction->times;
762 return -1; /* didn't match any instruction */
766 static bool possible_sbyte(operand *o)
768 return o->wrt == NO_SEG && o->segment == NO_SEG &&
769 !(o->opflags & OPFLAG_UNKNOWN) &&
770 optimizing >= 0 && !(o->type & STRICT);
773 /* check that opn[op] is a signed byte of size 16 or 32 */
774 static bool is_sbyte16(operand *o)
778 if (!possible_sbyte(o))
782 return v >= -128 && v <= 127;
785 static bool is_sbyte32(operand *o)
789 if (!possible_sbyte(o))
793 return v >= -128 && v <= 127;
796 static void bad_hle_warn(const insn * ins, uint8_t hleok)
798 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
799 enum whatwarn { w_none, w_lock, w_inval };
800 static const enum whatwarn warn[2][4] =
802 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
803 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
807 n = (unsigned int)rep_pfx - P_XACQUIRE;
809 return; /* Not XACQUIRE/XRELEASE */
811 switch (warn[n][hleok]) {
816 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
817 errfunc(ERR_WARNING | ERR_PASS2,
818 "%s with this instruction requires lock",
819 prefix_name(rep_pfx));
824 errfunc(ERR_WARNING | ERR_PASS2,
825 "%s invalid with this instruction",
826 prefix_name(rep_pfx));
831 /* Common construct */
832 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
834 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
835 insn * ins, const uint8_t *codes)
846 ins->rex = 0; /* Ensure REX is reset */
847 eat = EA_SCALAR; /* Expect a scalar EA */
849 if (ins->prefixes[PPS_OSIZE] == P_O64)
852 (void)segment; /* Don't warn that this parameter is unused */
853 (void)offset; /* Don't warn that this parameter is unused */
857 op1 = (c & 3) + ((opex & 1) << 2);
858 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
859 opx = &ins->oprs[op1];
860 opex = 0; /* For the next iteration */
867 codes += c, length += c;
878 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
893 if (opx->type & (BITS16 | BITS32 | BITS64))
894 length += (opx->type & BITS16) ? 2 : 4;
896 length += (bits == 16) ? 2 : 4;
904 length += ins->addr_size >> 3;
912 length += 8; /* MOV reg64/imm */
920 if (opx->type & (BITS16 | BITS32 | BITS64))
921 length += (opx->type & BITS16) ? 2 : 4;
923 length += (bits == 16) ? 2 : 4;
935 length += is_sbyte16(opx) ? 1 : 2;
944 length += is_sbyte32(opx) ? 1 : 4;
963 length += is_sbyte32(opx) ? 1 : 4;
972 ins->vexreg = regval(opx);
973 ins->vex_cm = *codes++;
974 ins->vex_wlp = *codes++;
978 if (has_prefix(ins, PPS_REP, P_XACQUIRE) ||
979 has_prefix(ins, PPS_REP, P_XRELEASE))
992 ins->vex_cm = *codes++;
993 ins->vex_wlp = *codes++;
1006 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1010 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1017 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1018 has_prefix(ins, PPS_ASIZE, P_A32))
1027 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1031 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1033 ins->prefixes[PPS_OSIZE] = P_O16;
1039 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1043 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1045 ins->prefixes[PPS_OSIZE] = P_O32;
1084 if (!ins->prefixes[PPS_REP])
1085 ins->prefixes[PPS_REP] = P_REP;
1089 if (!ins->prefixes[PPS_REP])
1090 ins->prefixes[PPS_REP] = P_REPNE;
1094 if (ins->oprs[0].segment != NO_SEG)
1095 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1096 " quantity of BSS space");
1098 length += ins->oprs[0].offset;
1102 if (!ins->prefixes[PPS_WAIT])
1103 ins->prefixes[PPS_WAIT] = P_WAIT;
1161 struct operand *opy = &ins->oprs[op2];
1163 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1166 /* pick rfield from operand b (opx) */
1167 rflags = regflag(opx);
1168 rfield = nasm_regvals[opx->basereg];
1173 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1174 rfield, rflags) != eat) {
1175 errfunc(ERR_NONFATAL, "invalid effective address");
1178 ins->rex |= ea_data.rex;
1179 length += ea_data.size;
1185 errfunc(ERR_PANIC, "internal instruction table corrupt"
1186 ": instruction code \\%o (0x%02X) given", c, c);
1191 ins->rex &= rex_mask;
1193 if (ins->rex & REX_NH) {
1194 if (ins->rex & REX_H) {
1195 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1198 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1201 if (ins->rex & REX_V) {
1202 int bad32 = REX_R|REX_W|REX_X|REX_B;
1204 if (ins->rex & REX_H) {
1205 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1208 switch (ins->vex_wlp & 060) {
1222 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1223 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1226 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1230 } else if (ins->rex & REX_REAL) {
1231 if (ins->rex & REX_H) {
1232 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1234 } else if (bits == 64) {
1236 } else if ((ins->rex & REX_L) &&
1237 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1240 assert_no_prefix(ins, PPS_LOCK);
1243 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1248 bad_hle_warn(ins, hleok);
1253 #define EMIT_REX() \
1254 if (!(ins->rex & REX_V) && (ins->rex & REX_REAL) && (bits == 64)) { \
1255 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1256 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1261 static void gencode(int32_t segment, int64_t offset, int bits,
1262 insn * ins, const struct itemplate *temp,
1265 static const char condval[] = { /* conditional opcodes */
1266 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1267 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1268 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1275 struct operand *opx;
1276 const uint8_t *codes = temp->code;
1278 enum ea_type eat = EA_SCALAR;
1282 op1 = (c & 3) + ((opex & 1) << 2);
1283 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1284 opx = &ins->oprs[op1];
1285 opex = 0; /* For the next iteration */
1293 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1306 bytes[0] = *codes++ + (regval(opx) & 7);
1307 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1313 * The test for BITS8 and SBYTE here is intended to avoid
1314 * warning on optimizer actions due to SBYTE, while still
1315 * warn on explicit BYTE directives. Also warn, obviously,
1316 * if the optimizer isn't enabled.
1318 if (((opx->type & BITS8) ||
1319 !(opx->type & temp->opd[op1] & BYTENESS)) &&
1320 (opx->offset < -128 || opx->offset > 127)) {
1321 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1322 "signed byte value exceeds bounds");
1324 if (opx->segment != NO_SEG) {
1326 out(offset, segment, &data, OUT_ADDRESS, 1,
1327 opx->segment, opx->wrt);
1329 bytes[0] = opx->offset;
1330 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1337 if (opx->offset < -256 || opx->offset > 255) {
1338 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1339 "byte value exceeds bounds");
1341 if (opx->segment != NO_SEG) {
1343 out(offset, segment, &data, OUT_ADDRESS, 1,
1344 opx->segment, opx->wrt);
1346 bytes[0] = opx->offset;
1347 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1354 if (opx->offset < 0 || opx->offset > 255)
1355 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1356 "unsigned byte value exceeds bounds");
1357 if (opx->segment != NO_SEG) {
1359 out(offset, segment, &data, OUT_ADDRESS, 1,
1360 opx->segment, opx->wrt);
1362 bytes[0] = opx->offset;
1363 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1370 warn_overflow_opd(opx, 2);
1372 out(offset, segment, &data, OUT_ADDRESS, 2,
1373 opx->segment, opx->wrt);
1378 if (opx->type & (BITS16 | BITS32))
1379 size = (opx->type & BITS16) ? 2 : 4;
1381 size = (bits == 16) ? 2 : 4;
1382 warn_overflow_opd(opx, size);
1384 out(offset, segment, &data, OUT_ADDRESS, size,
1385 opx->segment, opx->wrt);
1390 warn_overflow_opd(opx, 4);
1392 out(offset, segment, &data, OUT_ADDRESS, 4,
1393 opx->segment, opx->wrt);
1399 size = ins->addr_size >> 3;
1400 warn_overflow_opd(opx, size);
1401 out(offset, segment, &data, OUT_ADDRESS, size,
1402 opx->segment, opx->wrt);
1407 if (opx->segment != segment) {
1409 out(offset, segment, &data,
1410 OUT_REL1ADR, insn_end - offset,
1411 opx->segment, opx->wrt);
1413 data = opx->offset - insn_end;
1414 if (data > 127 || data < -128)
1415 errfunc(ERR_NONFATAL, "short jump is out of range");
1416 out(offset, segment, &data,
1417 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1423 data = (int64_t)opx->offset;
1424 out(offset, segment, &data, OUT_ADDRESS, 8,
1425 opx->segment, opx->wrt);
1430 if (opx->segment != segment) {
1432 out(offset, segment, &data,
1433 OUT_REL2ADR, insn_end - offset,
1434 opx->segment, opx->wrt);
1436 data = opx->offset - insn_end;
1437 out(offset, segment, &data,
1438 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1444 if (opx->type & (BITS16 | BITS32 | BITS64))
1445 size = (opx->type & BITS16) ? 2 : 4;
1447 size = (bits == 16) ? 2 : 4;
1448 if (opx->segment != segment) {
1450 out(offset, segment, &data,
1451 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1452 insn_end - offset, opx->segment, opx->wrt);
1454 data = opx->offset - insn_end;
1455 out(offset, segment, &data,
1456 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1462 if (opx->segment != segment) {
1464 out(offset, segment, &data,
1465 OUT_REL4ADR, insn_end - offset,
1466 opx->segment, opx->wrt);
1468 data = opx->offset - insn_end;
1469 out(offset, segment, &data,
1470 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1476 if (opx->segment == NO_SEG)
1477 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1480 out(offset, segment, &data, OUT_ADDRESS, 2,
1481 outfmt->segbase(1 + opx->segment),
1488 warn_overflow_opd(opx, 2);
1489 if (is_sbyte16(opx)) {
1491 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1495 out(offset, segment, &data, OUT_ADDRESS, 2,
1496 opx->segment, opx->wrt);
1503 bytes[0] = *codes++;
1504 if (is_sbyte16(opx))
1505 bytes[0] |= 2; /* s-bit */
1506 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1512 warn_overflow_opd(opx, 4);
1513 if (is_sbyte32(opx)) {
1515 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1519 out(offset, segment, &data, OUT_ADDRESS, 4,
1520 opx->segment, opx->wrt);
1527 bytes[0] = *codes++;
1528 if (is_sbyte32(opx))
1529 bytes[0] |= 2; /* s-bit */
1530 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1536 opx = &ins->oprs[c >> 3];
1537 bytes[0] = nasm_regvals[opx->basereg] << 4;
1538 opx = &ins->oprs[c & 7];
1539 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1540 errfunc(ERR_NONFATAL,
1541 "non-absolute expression not permitted as argument %d",
1544 if (opx->offset & ~15) {
1545 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1546 "four-bit argument exceeds bounds");
1548 bytes[0] |= opx->offset & 15;
1550 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1556 opx = &ins->oprs[c >> 4];
1557 bytes[0] = nasm_regvals[opx->basereg] << 4;
1559 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1564 bytes[0] = nasm_regvals[opx->basereg] << 4;
1565 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1571 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1572 (int32_t)data != (int64_t)data) {
1573 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1574 "signed dword immediate exceeds bounds");
1576 if (is_sbyte32(opx)) {
1578 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1582 out(offset, segment, &data, OUT_ADDRESS, 4,
1583 opx->segment, opx->wrt);
1590 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1591 (int32_t)data != (int64_t)data) {
1592 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1593 "signed dword immediate exceeds bounds");
1595 out(offset, segment, &data, OUT_ADDRESS, 4,
1596 opx->segment, opx->wrt);
1603 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1604 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1605 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1606 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1607 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1608 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1612 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1613 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1614 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1627 if (ins->rex & REX_W)
1629 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1631 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1636 um = (uint64_t)2 << (s-1);
1639 if (uv > 127 && uv < (uint64_t)-128 &&
1640 (uv < um-128 || uv > um-1)) {
1641 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1642 "signed byte value exceeds bounds");
1644 if (opx->segment != NO_SEG) {
1646 out(offset, segment, &data, OUT_ADDRESS, 1,
1647 opx->segment, opx->wrt);
1650 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1661 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1663 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1670 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1672 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1704 *bytes = *codes++ ^ condval[ins->condition];
1705 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1714 *bytes = c - 0332 + 0xF2;
1715 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1720 if (ins->rex & REX_R) {
1722 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1725 ins->rex &= ~(REX_L|REX_R);
1736 if (ins->oprs[0].segment != NO_SEG)
1737 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1739 int64_t size = ins->oprs[0].offset;
1741 out(offset, segment, NULL,
1742 OUT_RESERVE, size, NO_SEG, NO_SEG);
1753 switch (ins->oprs[0].basereg) {
1768 "bizarre 8086 segment register received");
1770 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1777 switch (ins->oprs[0].basereg) {
1786 "bizarre 386 segment register received");
1788 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1797 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1803 bytes[0] = c - 0362 + 0xf2;
1804 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1814 *bytes = c - 0366 + 0x66;
1815 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1825 *bytes = bits == 16 ? 3 : 5;
1826 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1856 struct operand *opy = &ins->oprs[op2];
1859 /* pick rfield from operand b (opx) */
1860 rflags = regflag(opx);
1861 rfield = nasm_regvals[opx->basereg];
1863 /* rfield is constant */
1868 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1869 rfield, rflags) != eat)
1870 errfunc(ERR_NONFATAL, "invalid effective address");
1873 *p++ = ea_data.modrm;
1874 if (ea_data.sib_present)
1878 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1881 * Make sure the address gets the right offset in case
1882 * the line breaks in the .lst file (BR 1197827)
1887 switch (ea_data.bytes) {
1897 if (opy->segment == segment) {
1899 if (overflow_signed(data, ea_data.bytes))
1900 warn_overflow(ERR_PASS2, ea_data.bytes);
1901 out(offset, segment, &data, OUT_ADDRESS,
1902 ea_data.bytes, NO_SEG, NO_SEG);
1904 /* overflow check in output/linker? */
1905 out(offset, segment, &data, OUT_REL4ADR,
1906 insn_end - offset, opy->segment, opy->wrt);
1909 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1910 signed_bits(opy->offset, ins->addr_size) !=
1911 signed_bits(opy->offset, ea_data.bytes * 8))
1912 warn_overflow(ERR_PASS2, ea_data.bytes);
1914 out(offset, segment, &data, OUT_ADDRESS,
1915 ea_data.bytes, opy->segment, opy->wrt);
1921 "Invalid amount of bytes (%d) for offset?!",
1930 errfunc(ERR_PANIC, "internal instruction table corrupt"
1931 ": instruction code \\%o (0x%02X) given", c, c);
1937 static opflags_t regflag(const operand * o)
1939 if (!is_register(o->basereg))
1940 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1941 return nasm_reg_flags[o->basereg];
1944 static int32_t regval(const operand * o)
1946 if (!is_register(o->basereg))
1947 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1948 return nasm_regvals[o->basereg];
1951 static int op_rexflags(const operand * o, int mask)
1956 if (!is_register(o->basereg))
1957 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1959 flags = nasm_reg_flags[o->basereg];
1960 val = nasm_regvals[o->basereg];
1962 return rexflags(val, flags, mask);
1965 static int rexflags(int val, opflags_t flags, int mask)
1970 rex |= REX_B|REX_X|REX_R;
1973 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1975 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1981 static enum match_result find_match(const struct itemplate **tempp,
1983 int32_t segment, int64_t offset, int bits)
1985 const struct itemplate *temp;
1986 enum match_result m, merr;
1987 opflags_t xsizeflags[MAX_OPERANDS];
1988 bool opsizemissing = false;
1991 for (i = 0; i < instruction->operands; i++)
1992 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1994 merr = MERR_INVALOP;
1996 for (temp = nasm_instructions[instruction->opcode];
1997 temp->opcode != I_none; temp++) {
1998 m = matches(temp, instruction, bits);
1999 if (m == MOK_JUMP) {
2000 if (jmp_match(segment, offset, bits, instruction, temp->code))
2004 } else if (m == MERR_OPSIZEMISSING &&
2005 (temp->flags & IF_SMASK) != IF_SX) {
2007 * Missing operand size and a candidate for fuzzy matching...
2009 for (i = 0; i < temp->operands; i++) {
2010 if ((temp->opd[i] & SAME_AS) == 0)
2011 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2013 opsizemissing = true;
2017 if (merr == MOK_GOOD)
2021 /* No match, but see if we can get a fuzzy operand size match... */
2025 for (i = 0; i < instruction->operands; i++) {
2027 * We ignore extrinsic operand sizes on registers, so we should
2028 * never try to fuzzy-match on them. This also resolves the case
2029 * when we have e.g. "xmmrm128" in two different positions.
2031 if (is_class(REGISTER, instruction->oprs[i].type))
2034 /* This tests if xsizeflags[i] has more than one bit set */
2035 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2036 goto done; /* No luck */
2038 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2041 /* Try matching again... */
2042 for (temp = nasm_instructions[instruction->opcode];
2043 temp->opcode != I_none; temp++) {
2044 m = matches(temp, instruction, bits);
2045 if (m == MOK_JUMP) {
2046 if (jmp_match(segment, offset, bits, instruction, temp->code))
2053 if (merr == MOK_GOOD)
2062 static enum match_result matches(const struct itemplate *itemp,
2063 insn *instruction, int bits)
2065 int i, size[MAX_OPERANDS], asize, oprs;
2066 bool opsizemissing = false;
2071 if (itemp->opcode != instruction->opcode)
2072 return MERR_INVALOP;
2075 * Count the operands
2077 if (itemp->operands != instruction->operands)
2078 return MERR_INVALOP;
2083 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2084 return MERR_INVALOP;
2087 * Check that no spurious colons or TOs are present
2089 for (i = 0; i < itemp->operands; i++)
2090 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2091 return MERR_INVALOP;
2094 * Process size flags
2096 switch (itemp->flags & IF_SMASK) {
2136 if (itemp->flags & IF_ARMASK) {
2137 /* S- flags only apply to a specific operand */
2138 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2139 memset(size, 0, sizeof size);
2142 /* S- flags apply to all operands */
2143 for (i = 0; i < MAX_OPERANDS; i++)
2148 * Check that the operand flags all match up,
2149 * it's a bit tricky so lets be verbose:
2151 * 1) Find out the size of operand. If instruction
2152 * doesn't have one specified -- we're trying to
2153 * guess it either from template (IF_S* flag) or
2156 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2157 * (ie the same operand as was specified somewhere in template, and
2158 * this referred operand index is being achieved via ~SAME_AS)
2159 * we are to be sure that both registers (in template and instruction)
2162 * 3) If template operand do not match the instruction OR
2163 * template has an operand size specified AND this size differ
2164 * from which instruction has (perhaps we got it from code bits)
2166 * a) Check that only size of instruction and operand is differ
2167 * other characteristics do match
2168 * b) Perhaps it's a register specified in instruction so
2169 * for such a case we just mark that operand as "size
2170 * missing" and this will turn on fuzzy operand size
2171 * logic facility (handled by a caller)
2173 for (i = 0; i < itemp->operands; i++) {
2174 opflags_t type = instruction->oprs[i].type;
2175 if (!(type & SIZE_MASK))
2178 if (itemp->opd[i] & SAME_AS) {
2179 int j = itemp->opd[i] & ~SAME_AS;
2180 if (type != instruction->oprs[j].type ||
2181 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2182 return MERR_INVALOP;
2183 } else if (itemp->opd[i] & ~type ||
2184 ((itemp->opd[i] & SIZE_MASK) &&
2185 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2186 if ((itemp->opd[i] & ~type & ~SIZE_MASK) || (type & SIZE_MASK)) {
2187 return MERR_INVALOP;
2188 } else if (!is_class(REGISTER, type)) {
2190 * Note: we don't honor extrinsic operand sizes for registers,
2191 * so "missing operand size" for a register should be
2192 * considered a wildcard match rather than an error.
2194 opsizemissing = true;
2200 return MERR_OPSIZEMISSING;
2203 * Check operand sizes
2205 if (itemp->flags & (IF_SM | IF_SM2)) {
2206 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2207 for (i = 0; i < oprs; i++) {
2208 asize = itemp->opd[i] & SIZE_MASK;
2210 for (i = 0; i < oprs; i++)
2216 oprs = itemp->operands;
2219 for (i = 0; i < itemp->operands; i++) {
2220 if (!(itemp->opd[i] & SIZE_MASK) &&
2221 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2222 return MERR_OPSIZEMISMATCH;
2226 * Check template is okay at the set cpu level
2228 if (((itemp->flags & IF_PLEVEL) > cpu))
2232 * Verify the appropriate long mode flag.
2234 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2235 return MERR_BADMODE;
2238 * Check if special handling needed for Jumps
2240 if ((itemp->code[0] & 0374) == 0370)
2246 static enum ea_type process_ea(operand *input, ea *output, int bits,
2247 int addrbits, int rfield, opflags_t rflags)
2249 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2251 output->type = EA_SCALAR;
2252 output->rip = false;
2254 /* REX flags for the rfield operand */
2255 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2257 if (is_class(REGISTER, input->type)) {
2259 * It's a direct register.
2263 if (!is_register(input->basereg))
2268 if (!is_class(REG_EA, f))
2271 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2272 output->sib_present = false; /* no SIB necessary */
2273 output->bytes = 0; /* no offset necessary either */
2274 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2277 * It's a memory reference.
2279 if (input->basereg == -1 &&
2280 (input->indexreg == -1 || input->scale == 0)) {
2282 * It's a pure offset.
2284 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2285 input->segment == NO_SEG) {
2286 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2287 input->type &= ~IP_REL;
2288 input->type |= MEMORY;
2291 if (input->eaflags & EAF_BYTEOFFS ||
2292 (input->eaflags & EAF_WORDOFFS &&
2293 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2294 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2297 if (bits == 64 && (~input->type & IP_REL)) {
2298 output->sib_present = true;
2299 output->sib = GEN_SIB(0, 4, 5);
2301 output->modrm = GEN_MODRM(0, rfield, 4);
2302 output->rip = false;
2304 output->sib_present = false;
2305 output->bytes = (addrbits != 16 ? 4 : 2);
2306 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2307 output->rip = bits == 64;
2311 * It's an indirection.
2313 int i = input->indexreg, b = input->basereg, s = input->scale;
2314 int32_t seg = input->segment;
2315 int hb = input->hintbase, ht = input->hinttype;
2316 int t, it, bt; /* register numbers */
2317 opflags_t x, ix, bx; /* register flags */
2320 i = -1; /* make this easy, at least */
2322 if (is_register(i)) {
2323 it = nasm_regvals[i];
2324 ix = nasm_reg_flags[i];
2330 if (is_register(b)) {
2331 bt = nasm_regvals[b];
2332 bx = nasm_reg_flags[b];
2338 /* if either one are a vector register... */
2339 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2340 int32_t sok = BITS32 | BITS64;
2341 int32_t o = input->offset;
2342 int mod, scale, index, base;
2345 * For a vector SIB, one has to be a vector and the other,
2346 * if present, a GPR. The vector must be the index operand.
2348 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2354 t = bt, bt = it, it = t;
2355 x = bx, bx = ix, ix = x;
2361 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2368 * While we're here, ensure the user didn't specify
2371 if (input->disp_size == 16 || input->disp_size == 64)
2374 if (addrbits == 16 ||
2375 (addrbits == 32 && !(sok & BITS32)) ||
2376 (addrbits == 64 && !(sok & BITS64)))
2379 output->type = (ix & YMMREG & ~REG_EA)
2380 ? EA_YMMVSIB : EA_XMMVSIB;
2382 output->rex |= rexflags(it, ix, REX_X);
2383 output->rex |= rexflags(bt, bx, REX_B);
2385 index = it & 7; /* it is known to be != -1 */
2400 default: /* then what the smeg is it? */
2401 goto err; /* panic */
2409 if (base != REG_NUM_EBP && o == 0 &&
2410 seg == NO_SEG && !forw_ref &&
2411 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2413 else if (input->eaflags & EAF_BYTEOFFS ||
2414 (o >= -128 && o <= 127 &&
2415 seg == NO_SEG && !forw_ref &&
2416 !(input->eaflags & EAF_WORDOFFS)))
2422 output->sib_present = true;
2423 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2424 output->modrm = GEN_MODRM(mod, rfield, 4);
2425 output->sib = GEN_SIB(scale, index, base);
2426 } else if ((ix|bx) & (BITS32|BITS64)) {
2428 * it must be a 32/64-bit memory reference. Firstly we have
2429 * to check that all registers involved are type E/Rxx.
2431 int32_t sok = BITS32 | BITS64;
2432 int32_t o = input->offset;
2435 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2443 goto err; /* Invalid register */
2444 if (~sok & bx & SIZE_MASK)
2445 goto err; /* Invalid size */
2450 * While we're here, ensure the user didn't specify
2453 if (input->disp_size == 16 || input->disp_size == 64)
2456 if (addrbits == 16 ||
2457 (addrbits == 32 && !(sok & BITS32)) ||
2458 (addrbits == 64 && !(sok & BITS64)))
2461 /* now reorganize base/index */
2462 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2463 ((hb == b && ht == EAH_NOTBASE) ||
2464 (hb == i && ht == EAH_MAKEBASE))) {
2465 /* swap if hints say so */
2466 t = bt, bt = it, it = t;
2467 x = bx, bx = ix, ix = x;
2469 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2470 bt = -1, bx = 0, s++;
2471 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2472 /* make single reg base, unless hint */
2473 bt = it, bx = ix, it = -1, ix = 0;
2475 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2476 s == 3 || s == 5 || s == 9) && bt == -1)
2477 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2478 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2479 (input->eaflags & EAF_TIMESTWO))
2480 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2481 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2482 if (s == 1 && it == REG_NUM_ESP) {
2483 /* swap ESP into base if scale is 1 */
2484 t = it, it = bt, bt = t;
2485 x = ix, ix = bx, bx = x;
2487 if (it == REG_NUM_ESP ||
2488 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2489 goto err; /* wrong, for various reasons */
2491 output->rex |= rexflags(it, ix, REX_X);
2492 output->rex |= rexflags(bt, bx, REX_B);
2494 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2503 if (rm != REG_NUM_EBP && o == 0 &&
2504 seg == NO_SEG && !forw_ref &&
2505 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2507 else if (input->eaflags & EAF_BYTEOFFS ||
2508 (o >= -128 && o <= 127 &&
2509 seg == NO_SEG && !forw_ref &&
2510 !(input->eaflags & EAF_WORDOFFS)))
2516 output->sib_present = false;
2517 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2518 output->modrm = GEN_MODRM(mod, rfield, rm);
2521 int mod, scale, index, base;
2541 default: /* then what the smeg is it? */
2542 goto err; /* panic */
2550 if (base != REG_NUM_EBP && o == 0 &&
2551 seg == NO_SEG && !forw_ref &&
2552 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2554 else if (input->eaflags & EAF_BYTEOFFS ||
2555 (o >= -128 && o <= 127 &&
2556 seg == NO_SEG && !forw_ref &&
2557 !(input->eaflags & EAF_WORDOFFS)))
2563 output->sib_present = true;
2564 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2565 output->modrm = GEN_MODRM(mod, rfield, 4);
2566 output->sib = GEN_SIB(scale, index, base);
2568 } else { /* it's 16-bit */
2570 int16_t o = input->offset;
2572 /* check for 64-bit long mode */
2576 /* check all registers are BX, BP, SI or DI */
2577 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2578 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2581 /* ensure the user didn't specify DWORD/QWORD */
2582 if (input->disp_size == 32 || input->disp_size == 64)
2585 if (s != 1 && i != -1)
2586 goto err; /* no can do, in 16-bit EA */
2587 if (b == -1 && i != -1) {
2592 if ((b == R_SI || b == R_DI) && i != -1) {
2597 /* have BX/BP as base, SI/DI index */
2599 goto err; /* shouldn't ever happen, in theory */
2600 if (i != -1 && b != -1 &&
2601 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2602 goto err; /* invalid combinations */
2603 if (b == -1) /* pure offset: handled above */
2604 goto err; /* so if it gets to here, panic! */
2608 switch (i * 256 + b) {
2609 case R_SI * 256 + R_BX:
2612 case R_DI * 256 + R_BX:
2615 case R_SI * 256 + R_BP:
2618 case R_DI * 256 + R_BP:
2636 if (rm == -1) /* can't happen, in theory */
2637 goto err; /* so panic if it does */
2639 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2640 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2642 else if (input->eaflags & EAF_BYTEOFFS ||
2643 (o >= -128 && o <= 127 && seg == NO_SEG &&
2644 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2649 output->sib_present = false; /* no SIB - it's 16-bit */
2650 output->bytes = mod; /* bytes of offset needed */
2651 output->modrm = GEN_MODRM(mod, rfield, rm);
2656 output->size = 1 + output->sib_present + output->bytes;
2657 return output->type;
2660 return output->type = EA_INVALID;
2663 static void add_asp(insn *ins, int addrbits)
2668 valid = (addrbits == 64) ? 64|32 : 32|16;
2670 switch (ins->prefixes[PPS_ASIZE]) {
2681 valid &= (addrbits == 32) ? 16 : 32;
2687 for (j = 0; j < ins->operands; j++) {
2688 if (is_class(MEMORY, ins->oprs[j].type)) {
2691 /* Verify as Register */
2692 if (!is_register(ins->oprs[j].indexreg))
2695 i = nasm_reg_flags[ins->oprs[j].indexreg];
2697 /* Verify as Register */
2698 if (!is_register(ins->oprs[j].basereg))
2701 b = nasm_reg_flags[ins->oprs[j].basereg];
2703 if (ins->oprs[j].scale == 0)
2707 int ds = ins->oprs[j].disp_size;
2708 if ((addrbits != 64 && ds > 8) ||
2709 (addrbits == 64 && ds == 16))
2729 if (valid & addrbits) {
2730 ins->addr_size = addrbits;
2731 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2732 /* Add an address size prefix */
2733 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2734 ins->addr_size = (addrbits == 32) ? 16 : 32;
2737 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2738 ins->addr_size = addrbits; /* Error recovery */
2741 defdisp = ins->addr_size == 16 ? 16 : 32;
2743 for (j = 0; j < ins->operands; j++) {
2744 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2745 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2747 * mem_offs sizes must match the address size; if not,
2748 * strip the MEM_OFFS bit and match only EA instructions
2750 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);