1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - a signed byte immediate operand, from operand 0..3
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \140..\143 - an immediate word or signed byte for operand 0..3
64 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
65 * is a signed byte rather than a word. Opcode byte follows.
66 * \150..\153 - an immediate dword or signed byte for operand 0..3
67 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
68 * is a signed byte rather than a dword. Opcode byte follows.
69 * \172\ab - the register number from operand a in bits 7..4, with
70 * the 4-bit immediate from operand b in bits 3..0.
71 * \173\xab - the register number from operand a in bits 7..4, with
72 * the value b in bits 3..0.
73 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
74 * an arbitrary value in bits 3..0 (assembled as zero.)
75 * \2ab - a ModRM, calculated on EA in operand a, with the spare
76 * field equal to digit b.
77 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
78 * is not equal to the truncated and sign-extended 32-bit
79 * operand; used for 32-bit immediates in 64-bit mode.
80 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
81 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
82 * V field taken from operand 0..3.
83 * \264 - skip this instruction pattern if HLE prefixes present
84 * \265 - instruction takes XRELEASE (F3) with or without lock
85 * \266 - instruction takes XACQUIRE/XRELEASE with or without lock
86 * \267 - instruction takes XACQUIRE/XRELEASE with lock only
87 * \270 - this instruction uses VEX/XOP rather than REX, with the
88 * V field set to 1111b.
90 * VEX/XOP prefixes are followed by the sequence:
91 * \tmm\wlp where mm is the M field; and wlp is:
93 * [l0] ll = 0 for L = 0 (.128, .lz)
94 * [l1] ll = 1 for L = 1 (.256)
95 * [lig] ll = 2 for L don't care (always assembled as 0)
97 * [w0] ww = 0 for W = 0
98 * [w1 ] ww = 1 for W = 1
99 * [wig] ww = 2 for W don't care (always assembled as 0)
100 * [ww] ww = 3 for W used as REX.W
102 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
104 * \274..\277 - a signed byte immediate operand, from operand 0..3,
105 * which is to be extended to the operand size.
106 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
107 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
108 * \312 - (disassembler only) invalid with non-default address size.
109 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
110 * \314 - (disassembler only) invalid with REX.B
111 * \315 - (disassembler only) invalid with REX.X
112 * \316 - (disassembler only) invalid with REX.R
113 * \317 - (disassembler only) invalid with REX.W
114 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
115 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
116 * \322 - indicates that this instruction is only valid when the
117 * operand size is the default (instruction to disassembler,
118 * generates no code in the assembler)
119 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
120 * \324 - indicates 64-bit operand size requiring REX prefix.
121 * \325 - instruction which always uses spl/bpl/sil/dil
122 * \330 - a literal byte follows in the code stream, to be added
123 * to the condition code value of the instruction.
124 * \331 - instruction not valid with REP prefix. Hint for
125 * disassembler only; for SSE instructions.
126 * \332 - REP prefix (0xF2 byte) used as opcode extension.
127 * \333 - REP prefix (0xF3 byte) used as opcode extension.
128 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
129 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
130 * \336 - force a REP(E) prefix (0xF2) even if not specified.
131 * \337 - force a REPNE prefix (0xF3) even if not specified.
132 * \336-\337 are still listed as prefixes in the disassembler.
133 * \340 - reserve <operand 0> bytes of uninitialized storage.
134 * Operand 0 had better be a segmentless constant.
135 * \341 - this instruction needs a WAIT "prefix"
136 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
137 * (POP is never used for CS) depending on operand 0
138 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
140 * \360 - no SSE prefix (== \364\331)
141 * \361 - 66 SSE prefix (== \366\331)
142 * \362 - F2 SSE prefix (== \364\332)
143 * \363 - F3 SSE prefix (== \364\333)
144 * \364 - operand-size prefix (0x66) not permitted
145 * \365 - address-size prefix (0x67) not permitted
146 * \366 - operand-size prefix (0x66) used as opcode extension
147 * \367 - address-size prefix (0x67) used as opcode extension
148 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
149 * 370 is used for Jcc, 371 is used for JMP.
150 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
151 * used for conditional jump over longer jump
152 * \374 - this instruction takes an XMM VSIB memory EA
153 * \375 - this instruction takes an YMM VSIB memory EA
156 #include "compiler.h"
160 #include <inttypes.h>
164 #include "assemble.h"
170 * Matching errors. These should be sorted so that more specific
171 * errors come later in the sequence.
179 * Matching success; the conditional ones first
181 MOK_JUMP, /* Matching OK but needs jmp_match() */
182 MOK_GOOD /* Matching unconditionally OK */
186 enum ea_type type; /* what kind of EA is this? */
187 int sib_present; /* is a SIB byte necessary? */
188 int bytes; /* # of bytes of offset needed */
189 int size; /* lazy - this is sib+bytes+1 */
190 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
193 #define GEN_SIB(scale, index, base) \
194 (((scale) << 6) | ((index) << 3) | ((base)))
196 #define GEN_MODRM(mod, reg, rm) \
197 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
199 static uint32_t cpu; /* cpu level received from nasm.c */
200 static efunc errfunc;
201 static struct ofmt *outfmt;
202 static ListGen *list;
204 static int64_t calcsize(int32_t, int64_t, int, insn *,
205 const struct itemplate *);
206 static void gencode(int32_t segment, int64_t offset, int bits,
207 insn * ins, const struct itemplate *temp,
209 static enum match_result find_match(const struct itemplate **tempp,
211 int32_t segment, int64_t offset, int bits);
212 static enum match_result matches(const struct itemplate *, insn *, int bits);
213 static opflags_t regflag(const operand *);
214 static int32_t regval(const operand *);
215 static int rexflags(int, opflags_t, int);
216 static int op_rexflags(const operand *, int);
217 static void add_asp(insn *, int);
219 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
221 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
223 return ins->prefixes[pos] == prefix;
226 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
228 if (ins->prefixes[pos])
229 errfunc(ERR_NONFATAL, "invalid %s prefix",
230 prefix_name(ins->prefixes[pos]));
233 static const char *size_name(int size)
255 static void warn_overflow(int pass, int size)
257 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
258 "%s data exceeds bounds", size_name(size));
261 static void warn_overflow_const(int64_t data, int size)
263 if (overflow_general(data, size))
264 warn_overflow(ERR_PASS1, size);
267 static void warn_overflow_opd(const struct operand *o, int size)
269 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
270 if (overflow_general(o->offset, size))
271 warn_overflow(ERR_PASS2, size);
276 * This routine wrappers the real output format's output routine,
277 * in order to pass a copy of the data off to the listing file
278 * generator at the same time.
280 static void out(int64_t offset, int32_t segto, const void *data,
281 enum out_type type, uint64_t size,
282 int32_t segment, int32_t wrt)
284 static int32_t lineno = 0; /* static!!! */
285 static char *lnfname = NULL;
288 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
290 * This is a non-relocated address, and we're going to
291 * convert it into RAWDATA format.
296 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
300 WRITEADDR(q, *(int64_t *)data, size);
305 list->output(offset, data, type, size);
308 * this call to src_get determines when we call the
309 * debug-format-specific "linenum" function
310 * it updates lineno and lnfname to the current values
311 * returning 0 if "same as last time", -2 if lnfname
312 * changed, and the amount by which lineno changed,
313 * if it did. thus, these variables must be static
316 if (src_get(&lineno, &lnfname))
317 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
319 outfmt->output(segto, data, type, size, segment, wrt);
322 static bool jmp_match(int32_t segment, int64_t offset, int bits,
323 insn * ins, const struct itemplate *temp)
326 const uint8_t *code = temp->code;
329 if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT))
333 if (optimizing < 0 && c == 0371)
336 isize = calcsize(segment, offset, bits, ins, temp);
338 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
339 /* Be optimistic in pass 1 */
342 if (ins->oprs[0].segment != segment)
345 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
346 return (isize >= -128 && isize <= 127); /* is it byte size? */
349 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
350 insn * instruction, struct ofmt *output, efunc error,
353 const struct itemplate *temp;
358 int64_t start = offset;
359 int64_t wsize; /* size for DB etc. */
361 errfunc = error; /* to pass to other functions */
363 outfmt = output; /* likewise */
364 list = listgen; /* and again */
366 wsize = idata_bytes(instruction->opcode);
372 int32_t t = instruction->times;
375 "instruction->times < 0 (%ld) in assemble()", t);
377 while (t--) { /* repeat TIMES times */
378 list_for_each(e, instruction->eops) {
379 if (e->type == EOT_DB_NUMBER) {
381 errfunc(ERR_NONFATAL,
382 "integer supplied to a DT, DO or DY"
385 out(offset, segment, &e->offset,
386 OUT_ADDRESS, wsize, e->segment, e->wrt);
389 } else if (e->type == EOT_DB_STRING ||
390 e->type == EOT_DB_STRING_FREE) {
393 out(offset, segment, e->stringval,
394 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
395 align = e->stringlen % wsize;
398 align = wsize - align;
399 out(offset, segment, zero_buffer,
400 OUT_RAWDATA, align, NO_SEG, NO_SEG);
402 offset += e->stringlen + align;
405 if (t > 0 && t == instruction->times - 1) {
407 * Dummy call to list->output to give the offset to the
410 list->output(offset, NULL, OUT_RAWDATA, 0);
411 list->uplevel(LIST_TIMES);
414 if (instruction->times > 1)
415 list->downlevel(LIST_TIMES);
416 return offset - start;
419 if (instruction->opcode == I_INCBIN) {
420 const char *fname = instruction->eops->stringval;
423 fp = fopen(fname, "rb");
425 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
427 } else if (fseek(fp, 0L, SEEK_END) < 0) {
428 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
431 static char buf[4096];
432 size_t t = instruction->times;
437 if (instruction->eops->next) {
438 base = instruction->eops->next->offset;
440 if (instruction->eops->next->next &&
441 len > (size_t)instruction->eops->next->next->offset)
442 len = (size_t)instruction->eops->next->next->offset;
445 * Dummy call to list->output to give the offset to the
448 list->output(offset, NULL, OUT_RAWDATA, 0);
449 list->uplevel(LIST_INCBIN);
453 fseek(fp, base, SEEK_SET);
457 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
460 * This shouldn't happen unless the file
461 * actually changes while we are reading
465 "`incbin': unexpected EOF while"
466 " reading file `%s'", fname);
467 t = 0; /* Try to exit cleanly */
470 out(offset, segment, buf, OUT_RAWDATA, m,
475 list->downlevel(LIST_INCBIN);
476 if (instruction->times > 1) {
478 * Dummy call to list->output to give the offset to the
481 list->output(offset, NULL, OUT_RAWDATA, 0);
482 list->uplevel(LIST_TIMES);
483 list->downlevel(LIST_TIMES);
486 return instruction->times * len;
488 return 0; /* if we're here, there's an error */
491 /* Check to see if we need an address-size prefix */
492 add_asp(instruction, bits);
494 m = find_match(&temp, instruction, segment, offset, bits);
498 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
499 itimes = instruction->times;
500 if (insn_size < 0) /* shouldn't be, on pass two */
501 error(ERR_PANIC, "errors made it through from pass one");
504 for (j = 0; j < MAXPREFIX; j++) {
506 switch (instruction->prefixes[j]) {
526 error(ERR_WARNING | ERR_PASS2,
527 "cs segment base generated, but will be ignored in 64-bit mode");
533 error(ERR_WARNING | ERR_PASS2,
534 "ds segment base generated, but will be ignored in 64-bit mode");
540 error(ERR_WARNING | ERR_PASS2,
541 "es segment base generated, but will be ignored in 64-bit mode");
553 error(ERR_WARNING | ERR_PASS2,
554 "ss segment base generated, but will be ignored in 64-bit mode");
561 "segr6 and segr7 cannot be used as prefixes");
566 "16-bit addressing is not supported "
568 } else if (bits != 16)
578 "64-bit addressing is only supported "
602 error(ERR_PANIC, "invalid instruction prefix");
605 out(offset, segment, &c, OUT_RAWDATA, 1,
610 insn_end = offset + insn_size;
611 gencode(segment, offset, bits, instruction,
614 if (itimes > 0 && itimes == instruction->times - 1) {
616 * Dummy call to list->output to give the offset to the
619 list->output(offset, NULL, OUT_RAWDATA, 0);
620 list->uplevel(LIST_TIMES);
623 if (instruction->times > 1)
624 list->downlevel(LIST_TIMES);
625 return offset - start;
629 case MERR_OPSIZEMISSING:
630 error(ERR_NONFATAL, "operation size not specified");
632 case MERR_OPSIZEMISMATCH:
633 error(ERR_NONFATAL, "mismatch in operand sizes");
636 error(ERR_NONFATAL, "no instruction for this cpu level");
639 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
644 "invalid combination of opcode and operands");
651 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
652 insn * instruction, efunc error)
654 const struct itemplate *temp;
657 errfunc = error; /* to pass to other functions */
660 if (instruction->opcode == I_none)
663 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
664 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
665 instruction->opcode == I_DT || instruction->opcode == I_DO ||
666 instruction->opcode == I_DY) {
668 int32_t isize, osize, wsize;
671 wsize = idata_bytes(instruction->opcode);
673 list_for_each(e, instruction->eops) {
677 if (e->type == EOT_DB_NUMBER) {
679 warn_overflow_const(e->offset, wsize);
680 } else if (e->type == EOT_DB_STRING ||
681 e->type == EOT_DB_STRING_FREE)
682 osize = e->stringlen;
684 align = (-osize) % wsize;
687 isize += osize + align;
689 return isize * instruction->times;
692 if (instruction->opcode == I_INCBIN) {
693 const char *fname = instruction->eops->stringval;
698 fp = fopen(fname, "rb");
700 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
702 else if (fseek(fp, 0L, SEEK_END) < 0)
703 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
707 if (instruction->eops->next) {
708 len -= instruction->eops->next->offset;
709 if (instruction->eops->next->next &&
710 len > (size_t)instruction->eops->next->next->offset) {
711 len = (size_t)instruction->eops->next->next->offset;
714 val = instruction->times * len;
721 /* Check to see if we need an address-size prefix */
722 add_asp(instruction, bits);
724 m = find_match(&temp, instruction, segment, offset, bits);
726 /* we've matched an instruction. */
730 isize = calcsize(segment, offset, bits, instruction, temp);
733 for (j = 0; j < MAXPREFIX; j++) {
734 switch (instruction->prefixes[j]) {
760 return isize * instruction->times;
762 return -1; /* didn't match any instruction */
766 static bool possible_sbyte(operand *o)
768 return o->wrt == NO_SEG && o->segment == NO_SEG &&
769 !(o->opflags & OPFLAG_UNKNOWN) &&
770 optimizing >= 0 && !(o->type & STRICT);
773 /* check that opn[op] is a signed byte of size 16 or 32 */
774 static bool is_sbyte16(operand *o)
778 if (!possible_sbyte(o))
782 return v >= -128 && v <= 127;
785 static bool is_sbyte32(operand *o)
789 if (!possible_sbyte(o))
793 return v >= -128 && v <= 127;
796 static void bad_hle_warn(const insn * ins, uint8_t hleok)
798 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
799 enum whatwarn { w_none, w_lock, w_inval } ww;
800 static const enum whatwarn warn[2][4] =
802 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
803 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
807 n = (unsigned int)rep_pfx - P_XACQUIRE;
809 return; /* Not XACQUIRE/XRELEASE */
812 if (!is_class(MEMORY, ins->oprs[0].type))
813 ww = w_inval; /* HLE requires operand 0 to be memory */
820 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
821 errfunc(ERR_WARNING | ERR_PASS2,
822 "%s with this instruction requires lock",
823 prefix_name(rep_pfx));
828 errfunc(ERR_WARNING | ERR_PASS2,
829 "%s invalid with this instruction",
830 prefix_name(rep_pfx));
835 /* Common construct */
836 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
838 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
839 insn * ins, const struct itemplate *temp)
841 const uint8_t *codes = temp->code;
850 bool lockcheck = true;
852 ins->rex = 0; /* Ensure REX is reset */
853 eat = EA_SCALAR; /* Expect a scalar EA */
855 if (ins->prefixes[PPS_OSIZE] == P_O64)
858 (void)segment; /* Don't warn that this parameter is unused */
859 (void)offset; /* Don't warn that this parameter is unused */
863 op1 = (c & 3) + ((opex & 1) << 2);
864 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
865 opx = &ins->oprs[op1];
866 opex = 0; /* For the next iteration */
873 codes += c, length += c;
884 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
899 if (opx->type & (BITS16 | BITS32 | BITS64))
900 length += (opx->type & BITS16) ? 2 : 4;
902 length += (bits == 16) ? 2 : 4;
910 length += ins->addr_size >> 3;
918 length += 8; /* MOV reg64/imm */
926 if (opx->type & (BITS16 | BITS32 | BITS64))
927 length += (opx->type & BITS16) ? 2 : 4;
929 length += (bits == 16) ? 2 : 4;
941 length += is_sbyte16(opx) ? 1 : 2;
950 length += is_sbyte32(opx) ? 1 : 4;
969 length += is_sbyte32(opx) ? 1 : 4;
978 ins->vexreg = regval(opx);
979 ins->vex_cm = *codes++;
980 ins->vex_wlp = *codes++;
984 if (has_prefix(ins, PPS_REP, P_XACQUIRE) ||
985 has_prefix(ins, PPS_REP, P_XRELEASE))
998 ins->vex_cm = *codes++;
999 ins->vex_wlp = *codes++;
1012 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1016 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1023 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1024 has_prefix(ins, PPS_ASIZE, P_A32))
1033 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1037 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1039 ins->prefixes[PPS_OSIZE] = P_O16;
1045 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1049 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1051 ins->prefixes[PPS_OSIZE] = P_O32;
1090 if (!ins->prefixes[PPS_REP])
1091 ins->prefixes[PPS_REP] = P_REP;
1095 if (!ins->prefixes[PPS_REP])
1096 ins->prefixes[PPS_REP] = P_REPNE;
1100 if (ins->oprs[0].segment != NO_SEG)
1101 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1102 " quantity of BSS space");
1104 length += ins->oprs[0].offset;
1108 if (!ins->prefixes[PPS_WAIT])
1109 ins->prefixes[PPS_WAIT] = P_WAIT;
1167 struct operand *opy = &ins->oprs[op2];
1169 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1172 /* pick rfield from operand b (opx) */
1173 rflags = regflag(opx);
1174 rfield = nasm_regvals[opx->basereg];
1179 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1180 rfield, rflags) != eat) {
1181 errfunc(ERR_NONFATAL, "invalid effective address");
1184 ins->rex |= ea_data.rex;
1185 length += ea_data.size;
1191 errfunc(ERR_PANIC, "internal instruction table corrupt"
1192 ": instruction code \\%o (0x%02X) given", c, c);
1197 ins->rex &= rex_mask;
1199 if (ins->rex & REX_NH) {
1200 if (ins->rex & REX_H) {
1201 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1204 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1207 if (ins->rex & REX_V) {
1208 int bad32 = REX_R|REX_W|REX_X|REX_B;
1210 if (ins->rex & REX_H) {
1211 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1214 switch (ins->vex_wlp & 060) {
1228 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1229 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1232 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1236 } else if (ins->rex & REX_REAL) {
1237 if (ins->rex & REX_H) {
1238 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1240 } else if (bits == 64) {
1242 } else if ((ins->rex & REX_L) &&
1243 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1246 assert_no_prefix(ins, PPS_LOCK);
1247 lockcheck = false; /* Already errored, no need for warning */
1250 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1255 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1256 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1257 errfunc(ERR_WARNING | ERR_PASS2,
1258 "instruction is not lockable");
1261 bad_hle_warn(ins, hleok);
1266 #define EMIT_REX() \
1267 if (!(ins->rex & REX_V) && (ins->rex & REX_REAL) && (bits == 64)) { \
1268 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1269 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1274 static void gencode(int32_t segment, int64_t offset, int bits,
1275 insn * ins, const struct itemplate *temp,
1278 static const char condval[] = { /* conditional opcodes */
1279 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1280 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1281 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1288 struct operand *opx;
1289 const uint8_t *codes = temp->code;
1291 enum ea_type eat = EA_SCALAR;
1295 op1 = (c & 3) + ((opex & 1) << 2);
1296 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1297 opx = &ins->oprs[op1];
1298 opex = 0; /* For the next iteration */
1306 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1319 bytes[0] = *codes++ + (regval(opx) & 7);
1320 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1326 * The test for BITS8 and SBYTE here is intended to avoid
1327 * warning on optimizer actions due to SBYTE, while still
1328 * warn on explicit BYTE directives. Also warn, obviously,
1329 * if the optimizer isn't enabled.
1331 if (((opx->type & BITS8) ||
1332 !(opx->type & temp->opd[op1] & BYTENESS)) &&
1333 (opx->offset < -128 || opx->offset > 127)) {
1334 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1335 "signed byte value exceeds bounds");
1337 if (opx->segment != NO_SEG) {
1339 out(offset, segment, &data, OUT_ADDRESS, 1,
1340 opx->segment, opx->wrt);
1342 bytes[0] = opx->offset;
1343 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1350 if (opx->offset < -256 || opx->offset > 255) {
1351 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1352 "byte value exceeds bounds");
1354 if (opx->segment != NO_SEG) {
1356 out(offset, segment, &data, OUT_ADDRESS, 1,
1357 opx->segment, opx->wrt);
1359 bytes[0] = opx->offset;
1360 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1367 if (opx->offset < 0 || opx->offset > 255)
1368 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1369 "unsigned byte value exceeds bounds");
1370 if (opx->segment != NO_SEG) {
1372 out(offset, segment, &data, OUT_ADDRESS, 1,
1373 opx->segment, opx->wrt);
1375 bytes[0] = opx->offset;
1376 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1383 warn_overflow_opd(opx, 2);
1385 out(offset, segment, &data, OUT_ADDRESS, 2,
1386 opx->segment, opx->wrt);
1391 if (opx->type & (BITS16 | BITS32))
1392 size = (opx->type & BITS16) ? 2 : 4;
1394 size = (bits == 16) ? 2 : 4;
1395 warn_overflow_opd(opx, size);
1397 out(offset, segment, &data, OUT_ADDRESS, size,
1398 opx->segment, opx->wrt);
1403 warn_overflow_opd(opx, 4);
1405 out(offset, segment, &data, OUT_ADDRESS, 4,
1406 opx->segment, opx->wrt);
1412 size = ins->addr_size >> 3;
1413 warn_overflow_opd(opx, size);
1414 out(offset, segment, &data, OUT_ADDRESS, size,
1415 opx->segment, opx->wrt);
1420 if (opx->segment != segment) {
1422 out(offset, segment, &data,
1423 OUT_REL1ADR, insn_end - offset,
1424 opx->segment, opx->wrt);
1426 data = opx->offset - insn_end;
1427 if (data > 127 || data < -128)
1428 errfunc(ERR_NONFATAL, "short jump is out of range");
1429 out(offset, segment, &data,
1430 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1436 data = (int64_t)opx->offset;
1437 out(offset, segment, &data, OUT_ADDRESS, 8,
1438 opx->segment, opx->wrt);
1443 if (opx->segment != segment) {
1445 out(offset, segment, &data,
1446 OUT_REL2ADR, insn_end - offset,
1447 opx->segment, opx->wrt);
1449 data = opx->offset - insn_end;
1450 out(offset, segment, &data,
1451 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1457 if (opx->type & (BITS16 | BITS32 | BITS64))
1458 size = (opx->type & BITS16) ? 2 : 4;
1460 size = (bits == 16) ? 2 : 4;
1461 if (opx->segment != segment) {
1463 out(offset, segment, &data,
1464 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1465 insn_end - offset, opx->segment, opx->wrt);
1467 data = opx->offset - insn_end;
1468 out(offset, segment, &data,
1469 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1475 if (opx->segment != segment) {
1477 out(offset, segment, &data,
1478 OUT_REL4ADR, insn_end - offset,
1479 opx->segment, opx->wrt);
1481 data = opx->offset - insn_end;
1482 out(offset, segment, &data,
1483 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1489 if (opx->segment == NO_SEG)
1490 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1493 out(offset, segment, &data, OUT_ADDRESS, 2,
1494 outfmt->segbase(1 + opx->segment),
1501 warn_overflow_opd(opx, 2);
1502 if (is_sbyte16(opx)) {
1504 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1508 out(offset, segment, &data, OUT_ADDRESS, 2,
1509 opx->segment, opx->wrt);
1516 bytes[0] = *codes++;
1517 if (is_sbyte16(opx))
1518 bytes[0] |= 2; /* s-bit */
1519 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1525 warn_overflow_opd(opx, 4);
1526 if (is_sbyte32(opx)) {
1528 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1532 out(offset, segment, &data, OUT_ADDRESS, 4,
1533 opx->segment, opx->wrt);
1540 bytes[0] = *codes++;
1541 if (is_sbyte32(opx))
1542 bytes[0] |= 2; /* s-bit */
1543 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1549 opx = &ins->oprs[c >> 3];
1550 bytes[0] = nasm_regvals[opx->basereg] << 4;
1551 opx = &ins->oprs[c & 7];
1552 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1553 errfunc(ERR_NONFATAL,
1554 "non-absolute expression not permitted as argument %d",
1557 if (opx->offset & ~15) {
1558 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1559 "four-bit argument exceeds bounds");
1561 bytes[0] |= opx->offset & 15;
1563 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1569 opx = &ins->oprs[c >> 4];
1570 bytes[0] = nasm_regvals[opx->basereg] << 4;
1572 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1577 bytes[0] = nasm_regvals[opx->basereg] << 4;
1578 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1584 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1585 (int32_t)data != (int64_t)data) {
1586 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1587 "signed dword immediate exceeds bounds");
1589 if (is_sbyte32(opx)) {
1591 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1595 out(offset, segment, &data, OUT_ADDRESS, 4,
1596 opx->segment, opx->wrt);
1603 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1604 (int32_t)data != (int64_t)data) {
1605 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1606 "signed dword immediate exceeds bounds");
1608 out(offset, segment, &data, OUT_ADDRESS, 4,
1609 opx->segment, opx->wrt);
1616 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1617 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1618 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1619 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1620 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1621 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1625 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1626 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1627 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1640 if (ins->rex & REX_W)
1642 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1644 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1649 um = (uint64_t)2 << (s-1);
1652 if (uv > 127 && uv < (uint64_t)-128 &&
1653 (uv < um-128 || uv > um-1)) {
1654 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1655 "signed byte value exceeds bounds");
1657 if (opx->segment != NO_SEG) {
1659 out(offset, segment, &data, OUT_ADDRESS, 1,
1660 opx->segment, opx->wrt);
1663 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1674 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1676 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1683 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1685 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1717 *bytes = *codes++ ^ condval[ins->condition];
1718 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1727 *bytes = c - 0332 + 0xF2;
1728 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1733 if (ins->rex & REX_R) {
1735 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1738 ins->rex &= ~(REX_L|REX_R);
1749 if (ins->oprs[0].segment != NO_SEG)
1750 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1752 int64_t size = ins->oprs[0].offset;
1754 out(offset, segment, NULL,
1755 OUT_RESERVE, size, NO_SEG, NO_SEG);
1766 switch (ins->oprs[0].basereg) {
1781 "bizarre 8086 segment register received");
1783 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1790 switch (ins->oprs[0].basereg) {
1799 "bizarre 386 segment register received");
1801 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1810 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1816 bytes[0] = c - 0362 + 0xf2;
1817 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1827 *bytes = c - 0366 + 0x66;
1828 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1838 *bytes = bits == 16 ? 3 : 5;
1839 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1869 struct operand *opy = &ins->oprs[op2];
1872 /* pick rfield from operand b (opx) */
1873 rflags = regflag(opx);
1874 rfield = nasm_regvals[opx->basereg];
1876 /* rfield is constant */
1881 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1882 rfield, rflags) != eat)
1883 errfunc(ERR_NONFATAL, "invalid effective address");
1886 *p++ = ea_data.modrm;
1887 if (ea_data.sib_present)
1891 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1894 * Make sure the address gets the right offset in case
1895 * the line breaks in the .lst file (BR 1197827)
1900 switch (ea_data.bytes) {
1910 if (opy->segment == segment) {
1912 if (overflow_signed(data, ea_data.bytes))
1913 warn_overflow(ERR_PASS2, ea_data.bytes);
1914 out(offset, segment, &data, OUT_ADDRESS,
1915 ea_data.bytes, NO_SEG, NO_SEG);
1917 /* overflow check in output/linker? */
1918 out(offset, segment, &data, OUT_REL4ADR,
1919 insn_end - offset, opy->segment, opy->wrt);
1922 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1923 signed_bits(opy->offset, ins->addr_size) !=
1924 signed_bits(opy->offset, ea_data.bytes * 8))
1925 warn_overflow(ERR_PASS2, ea_data.bytes);
1927 out(offset, segment, &data, OUT_ADDRESS,
1928 ea_data.bytes, opy->segment, opy->wrt);
1934 "Invalid amount of bytes (%d) for offset?!",
1943 errfunc(ERR_PANIC, "internal instruction table corrupt"
1944 ": instruction code \\%o (0x%02X) given", c, c);
1950 static opflags_t regflag(const operand * o)
1952 if (!is_register(o->basereg))
1953 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1954 return nasm_reg_flags[o->basereg];
1957 static int32_t regval(const operand * o)
1959 if (!is_register(o->basereg))
1960 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1961 return nasm_regvals[o->basereg];
1964 static int op_rexflags(const operand * o, int mask)
1969 if (!is_register(o->basereg))
1970 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1972 flags = nasm_reg_flags[o->basereg];
1973 val = nasm_regvals[o->basereg];
1975 return rexflags(val, flags, mask);
1978 static int rexflags(int val, opflags_t flags, int mask)
1983 rex |= REX_B|REX_X|REX_R;
1986 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1988 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1994 static enum match_result find_match(const struct itemplate **tempp,
1996 int32_t segment, int64_t offset, int bits)
1998 const struct itemplate *temp;
1999 enum match_result m, merr;
2000 opflags_t xsizeflags[MAX_OPERANDS];
2001 bool opsizemissing = false;
2004 for (i = 0; i < instruction->operands; i++)
2005 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2007 merr = MERR_INVALOP;
2009 for (temp = nasm_instructions[instruction->opcode];
2010 temp->opcode != I_none; temp++) {
2011 m = matches(temp, instruction, bits);
2012 if (m == MOK_JUMP) {
2013 if (jmp_match(segment, offset, bits, instruction, temp))
2017 } else if (m == MERR_OPSIZEMISSING &&
2018 (temp->flags & IF_SMASK) != IF_SX) {
2020 * Missing operand size and a candidate for fuzzy matching...
2022 for (i = 0; i < temp->operands; i++) {
2023 if ((temp->opd[i] & SAME_AS) == 0)
2024 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2026 opsizemissing = true;
2030 if (merr == MOK_GOOD)
2034 /* No match, but see if we can get a fuzzy operand size match... */
2038 for (i = 0; i < instruction->operands; i++) {
2040 * We ignore extrinsic operand sizes on registers, so we should
2041 * never try to fuzzy-match on them. This also resolves the case
2042 * when we have e.g. "xmmrm128" in two different positions.
2044 if (is_class(REGISTER, instruction->oprs[i].type))
2047 /* This tests if xsizeflags[i] has more than one bit set */
2048 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2049 goto done; /* No luck */
2051 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2054 /* Try matching again... */
2055 for (temp = nasm_instructions[instruction->opcode];
2056 temp->opcode != I_none; temp++) {
2057 m = matches(temp, instruction, bits);
2058 if (m == MOK_JUMP) {
2059 if (jmp_match(segment, offset, bits, instruction, temp))
2066 if (merr == MOK_GOOD)
2075 static enum match_result matches(const struct itemplate *itemp,
2076 insn *instruction, int bits)
2078 int i, size[MAX_OPERANDS], asize, oprs;
2079 bool opsizemissing = false;
2084 if (itemp->opcode != instruction->opcode)
2085 return MERR_INVALOP;
2088 * Count the operands
2090 if (itemp->operands != instruction->operands)
2091 return MERR_INVALOP;
2096 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2097 return MERR_INVALOP;
2100 * Check that no spurious colons or TOs are present
2102 for (i = 0; i < itemp->operands; i++)
2103 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2104 return MERR_INVALOP;
2107 * Process size flags
2109 switch (itemp->flags & IF_SMASK) {
2149 if (itemp->flags & IF_ARMASK) {
2150 /* S- flags only apply to a specific operand */
2151 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2152 memset(size, 0, sizeof size);
2155 /* S- flags apply to all operands */
2156 for (i = 0; i < MAX_OPERANDS; i++)
2161 * Check that the operand flags all match up,
2162 * it's a bit tricky so lets be verbose:
2164 * 1) Find out the size of operand. If instruction
2165 * doesn't have one specified -- we're trying to
2166 * guess it either from template (IF_S* flag) or
2169 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2170 * (ie the same operand as was specified somewhere in template, and
2171 * this referred operand index is being achieved via ~SAME_AS)
2172 * we are to be sure that both registers (in template and instruction)
2175 * 3) If template operand do not match the instruction OR
2176 * template has an operand size specified AND this size differ
2177 * from which instruction has (perhaps we got it from code bits)
2179 * a) Check that only size of instruction and operand is differ
2180 * other characteristics do match
2181 * b) Perhaps it's a register specified in instruction so
2182 * for such a case we just mark that operand as "size
2183 * missing" and this will turn on fuzzy operand size
2184 * logic facility (handled by a caller)
2186 for (i = 0; i < itemp->operands; i++) {
2187 opflags_t type = instruction->oprs[i].type;
2188 if (!(type & SIZE_MASK))
2191 if (itemp->opd[i] & SAME_AS) {
2192 int j = itemp->opd[i] & ~SAME_AS;
2193 if (type != instruction->oprs[j].type ||
2194 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2195 return MERR_INVALOP;
2196 } else if (itemp->opd[i] & ~type ||
2197 ((itemp->opd[i] & SIZE_MASK) &&
2198 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2199 if ((itemp->opd[i] & ~type & ~SIZE_MASK) || (type & SIZE_MASK)) {
2200 return MERR_INVALOP;
2201 } else if (!is_class(REGISTER, type)) {
2203 * Note: we don't honor extrinsic operand sizes for registers,
2204 * so "missing operand size" for a register should be
2205 * considered a wildcard match rather than an error.
2207 opsizemissing = true;
2213 return MERR_OPSIZEMISSING;
2216 * Check operand sizes
2218 if (itemp->flags & (IF_SM | IF_SM2)) {
2219 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2220 for (i = 0; i < oprs; i++) {
2221 asize = itemp->opd[i] & SIZE_MASK;
2223 for (i = 0; i < oprs; i++)
2229 oprs = itemp->operands;
2232 for (i = 0; i < itemp->operands; i++) {
2233 if (!(itemp->opd[i] & SIZE_MASK) &&
2234 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2235 return MERR_OPSIZEMISMATCH;
2239 * Check template is okay at the set cpu level
2241 if (((itemp->flags & IF_PLEVEL) > cpu))
2245 * Verify the appropriate long mode flag.
2247 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2248 return MERR_BADMODE;
2251 * Check if special handling needed for Jumps
2253 if ((itemp->code[0] & 0374) == 0370)
2259 static enum ea_type process_ea(operand *input, ea *output, int bits,
2260 int addrbits, int rfield, opflags_t rflags)
2262 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2264 output->type = EA_SCALAR;
2265 output->rip = false;
2267 /* REX flags for the rfield operand */
2268 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2270 if (is_class(REGISTER, input->type)) {
2272 * It's a direct register.
2276 if (!is_register(input->basereg))
2281 if (!is_class(REG_EA, f))
2284 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2285 output->sib_present = false; /* no SIB necessary */
2286 output->bytes = 0; /* no offset necessary either */
2287 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2290 * It's a memory reference.
2292 if (input->basereg == -1 &&
2293 (input->indexreg == -1 || input->scale == 0)) {
2295 * It's a pure offset.
2297 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2298 input->segment == NO_SEG) {
2299 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2300 input->type &= ~IP_REL;
2301 input->type |= MEMORY;
2304 if (input->eaflags & EAF_BYTEOFFS ||
2305 (input->eaflags & EAF_WORDOFFS &&
2306 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2307 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2310 if (bits == 64 && (~input->type & IP_REL)) {
2311 output->sib_present = true;
2312 output->sib = GEN_SIB(0, 4, 5);
2314 output->modrm = GEN_MODRM(0, rfield, 4);
2315 output->rip = false;
2317 output->sib_present = false;
2318 output->bytes = (addrbits != 16 ? 4 : 2);
2319 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2320 output->rip = bits == 64;
2324 * It's an indirection.
2326 int i = input->indexreg, b = input->basereg, s = input->scale;
2327 int32_t seg = input->segment;
2328 int hb = input->hintbase, ht = input->hinttype;
2329 int t, it, bt; /* register numbers */
2330 opflags_t x, ix, bx; /* register flags */
2333 i = -1; /* make this easy, at least */
2335 if (is_register(i)) {
2336 it = nasm_regvals[i];
2337 ix = nasm_reg_flags[i];
2343 if (is_register(b)) {
2344 bt = nasm_regvals[b];
2345 bx = nasm_reg_flags[b];
2351 /* if either one are a vector register... */
2352 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2353 int32_t sok = BITS32 | BITS64;
2354 int32_t o = input->offset;
2355 int mod, scale, index, base;
2358 * For a vector SIB, one has to be a vector and the other,
2359 * if present, a GPR. The vector must be the index operand.
2361 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2367 t = bt, bt = it, it = t;
2368 x = bx, bx = ix, ix = x;
2374 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2381 * While we're here, ensure the user didn't specify
2384 if (input->disp_size == 16 || input->disp_size == 64)
2387 if (addrbits == 16 ||
2388 (addrbits == 32 && !(sok & BITS32)) ||
2389 (addrbits == 64 && !(sok & BITS64)))
2392 output->type = (ix & YMMREG & ~REG_EA)
2393 ? EA_YMMVSIB : EA_XMMVSIB;
2395 output->rex |= rexflags(it, ix, REX_X);
2396 output->rex |= rexflags(bt, bx, REX_B);
2398 index = it & 7; /* it is known to be != -1 */
2413 default: /* then what the smeg is it? */
2414 goto err; /* panic */
2422 if (base != REG_NUM_EBP && o == 0 &&
2423 seg == NO_SEG && !forw_ref &&
2424 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2426 else if (input->eaflags & EAF_BYTEOFFS ||
2427 (o >= -128 && o <= 127 &&
2428 seg == NO_SEG && !forw_ref &&
2429 !(input->eaflags & EAF_WORDOFFS)))
2435 output->sib_present = true;
2436 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2437 output->modrm = GEN_MODRM(mod, rfield, 4);
2438 output->sib = GEN_SIB(scale, index, base);
2439 } else if ((ix|bx) & (BITS32|BITS64)) {
2441 * it must be a 32/64-bit memory reference. Firstly we have
2442 * to check that all registers involved are type E/Rxx.
2444 int32_t sok = BITS32 | BITS64;
2445 int32_t o = input->offset;
2448 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2456 goto err; /* Invalid register */
2457 if (~sok & bx & SIZE_MASK)
2458 goto err; /* Invalid size */
2463 * While we're here, ensure the user didn't specify
2466 if (input->disp_size == 16 || input->disp_size == 64)
2469 if (addrbits == 16 ||
2470 (addrbits == 32 && !(sok & BITS32)) ||
2471 (addrbits == 64 && !(sok & BITS64)))
2474 /* now reorganize base/index */
2475 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2476 ((hb == b && ht == EAH_NOTBASE) ||
2477 (hb == i && ht == EAH_MAKEBASE))) {
2478 /* swap if hints say so */
2479 t = bt, bt = it, it = t;
2480 x = bx, bx = ix, ix = x;
2482 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2483 bt = -1, bx = 0, s++;
2484 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2485 /* make single reg base, unless hint */
2486 bt = it, bx = ix, it = -1, ix = 0;
2488 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2489 s == 3 || s == 5 || s == 9) && bt == -1)
2490 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2491 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2492 (input->eaflags & EAF_TIMESTWO))
2493 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2494 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2495 if (s == 1 && it == REG_NUM_ESP) {
2496 /* swap ESP into base if scale is 1 */
2497 t = it, it = bt, bt = t;
2498 x = ix, ix = bx, bx = x;
2500 if (it == REG_NUM_ESP ||
2501 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2502 goto err; /* wrong, for various reasons */
2504 output->rex |= rexflags(it, ix, REX_X);
2505 output->rex |= rexflags(bt, bx, REX_B);
2507 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2516 if (rm != REG_NUM_EBP && o == 0 &&
2517 seg == NO_SEG && !forw_ref &&
2518 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2520 else if (input->eaflags & EAF_BYTEOFFS ||
2521 (o >= -128 && o <= 127 &&
2522 seg == NO_SEG && !forw_ref &&
2523 !(input->eaflags & EAF_WORDOFFS)))
2529 output->sib_present = false;
2530 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2531 output->modrm = GEN_MODRM(mod, rfield, rm);
2534 int mod, scale, index, base;
2554 default: /* then what the smeg is it? */
2555 goto err; /* panic */
2563 if (base != REG_NUM_EBP && o == 0 &&
2564 seg == NO_SEG && !forw_ref &&
2565 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2567 else if (input->eaflags & EAF_BYTEOFFS ||
2568 (o >= -128 && o <= 127 &&
2569 seg == NO_SEG && !forw_ref &&
2570 !(input->eaflags & EAF_WORDOFFS)))
2576 output->sib_present = true;
2577 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2578 output->modrm = GEN_MODRM(mod, rfield, 4);
2579 output->sib = GEN_SIB(scale, index, base);
2581 } else { /* it's 16-bit */
2583 int16_t o = input->offset;
2585 /* check for 64-bit long mode */
2589 /* check all registers are BX, BP, SI or DI */
2590 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2591 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2594 /* ensure the user didn't specify DWORD/QWORD */
2595 if (input->disp_size == 32 || input->disp_size == 64)
2598 if (s != 1 && i != -1)
2599 goto err; /* no can do, in 16-bit EA */
2600 if (b == -1 && i != -1) {
2605 if ((b == R_SI || b == R_DI) && i != -1) {
2610 /* have BX/BP as base, SI/DI index */
2612 goto err; /* shouldn't ever happen, in theory */
2613 if (i != -1 && b != -1 &&
2614 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2615 goto err; /* invalid combinations */
2616 if (b == -1) /* pure offset: handled above */
2617 goto err; /* so if it gets to here, panic! */
2621 switch (i * 256 + b) {
2622 case R_SI * 256 + R_BX:
2625 case R_DI * 256 + R_BX:
2628 case R_SI * 256 + R_BP:
2631 case R_DI * 256 + R_BP:
2649 if (rm == -1) /* can't happen, in theory */
2650 goto err; /* so panic if it does */
2652 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2653 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2655 else if (input->eaflags & EAF_BYTEOFFS ||
2656 (o >= -128 && o <= 127 && seg == NO_SEG &&
2657 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2662 output->sib_present = false; /* no SIB - it's 16-bit */
2663 output->bytes = mod; /* bytes of offset needed */
2664 output->modrm = GEN_MODRM(mod, rfield, rm);
2669 output->size = 1 + output->sib_present + output->bytes;
2670 return output->type;
2673 return output->type = EA_INVALID;
2676 static void add_asp(insn *ins, int addrbits)
2681 valid = (addrbits == 64) ? 64|32 : 32|16;
2683 switch (ins->prefixes[PPS_ASIZE]) {
2694 valid &= (addrbits == 32) ? 16 : 32;
2700 for (j = 0; j < ins->operands; j++) {
2701 if (is_class(MEMORY, ins->oprs[j].type)) {
2704 /* Verify as Register */
2705 if (!is_register(ins->oprs[j].indexreg))
2708 i = nasm_reg_flags[ins->oprs[j].indexreg];
2710 /* Verify as Register */
2711 if (!is_register(ins->oprs[j].basereg))
2714 b = nasm_reg_flags[ins->oprs[j].basereg];
2716 if (ins->oprs[j].scale == 0)
2720 int ds = ins->oprs[j].disp_size;
2721 if ((addrbits != 64 && ds > 8) ||
2722 (addrbits == 64 && ds == 16))
2742 if (valid & addrbits) {
2743 ins->addr_size = addrbits;
2744 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2745 /* Add an address size prefix */
2746 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2747 ins->addr_size = (addrbits == 32) ? 16 : 32;
2750 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2751 ins->addr_size = addrbits; /* Error recovery */
2754 defdisp = ins->addr_size == 16 ? 16 : 32;
2756 for (j = 0; j < ins->operands; j++) {
2757 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2758 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2760 * mem_offs sizes must match the address size; if not,
2761 * strip the MEM_OFFS bit and match only EA instructions
2763 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);