1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \20..\23 - a byte immediate operand, from operand 0..3
46 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
47 * \30..\33 - a word immediate operand, from operand 0..3
48 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
49 * assembly mode or the operand-size override on the operand
50 * \40..\43 - a long immediate operand, from operand 0..3
51 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
52 * depending on the address size of the instruction.
53 * \50..\53 - a byte relative operand, from operand 0..3
54 * \54..\57 - a qword immediate operand, from operand 0..3
55 * \60..\63 - a word relative operand, from operand 0..3
56 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
57 * assembly mode or the operand-size override on the operand
58 * \70..\73 - a long relative operand, from operand 0..3
59 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
60 * \1ab - a ModRM, calculated on EA in operand a, with the spare
61 * field the register value of operand b.
62 * \172\ab - the register number from operand a in bits 7..4, with
63 * the 4-bit immediate from operand b in bits 3..0.
64 * \173\xab - the register number from operand a in bits 7..4, with
65 * the value b in bits 3..0.
66 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
67 * an arbitrary value in bits 3..0 (assembled as zero.)
68 * \2ab - a ModRM, calculated on EA in operand a, with the spare
69 * field equal to digit b.
70 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
71 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
72 * V field taken from operand 0..3.
73 * \270 - this instruction uses VEX/XOP rather than REX, with the
74 * V field set to 1111b.
76 * VEX/XOP prefixes are followed by the sequence:
77 * \tmm\wlp where mm is the M field; and wlp is:
79 * [l0] ll = 0 for L = 0 (.128, .lz)
80 * [l1] ll = 1 for L = 1 (.256)
81 * [lig] ll = 2 for L don't care (always assembled as 0)
83 * [w0] ww = 0 for W = 0
84 * [w1 ] ww = 1 for W = 1
85 * [wig] ww = 2 for W don't care (always assembled as 0)
86 * [ww] ww = 3 for W used as REX.W
88 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
90 * \271 - instruction takes XRELEASE (F3) with or without lock
91 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
92 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
93 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
94 * to the operand size (if o16/o32/o64 present) or the bit size
95 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
96 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
97 * \312 - (disassembler only) invalid with non-default address size.
98 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
99 * \314 - (disassembler only) invalid with REX.B
100 * \315 - (disassembler only) invalid with REX.X
101 * \316 - (disassembler only) invalid with REX.R
102 * \317 - (disassembler only) invalid with REX.W
103 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
104 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
105 * \322 - indicates that this instruction is only valid when the
106 * operand size is the default (instruction to disassembler,
107 * generates no code in the assembler)
108 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
109 * \324 - indicates 64-bit operand size requiring REX prefix.
110 * \325 - instruction which always uses spl/bpl/sil/dil
111 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
112 disassembler only; for SSE instructions.
113 * \330 - a literal byte follows in the code stream, to be added
114 * to the condition code value of the instruction.
115 * \331 - instruction not valid with REP prefix. Hint for
116 * disassembler only; for SSE instructions.
117 * \332 - REP prefix (0xF2 byte) used as opcode extension.
118 * \333 - REP prefix (0xF3 byte) used as opcode extension.
119 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
120 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
121 * \336 - force a REP(E) prefix (0xF3) even if not specified.
122 * \337 - force a REPNE prefix (0xF2) even if not specified.
123 * \336-\337 are still listed as prefixes in the disassembler.
124 * \340 - reserve <operand 0> bytes of uninitialized storage.
125 * Operand 0 had better be a segmentless constant.
126 * \341 - this instruction needs a WAIT "prefix"
127 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
128 * (POP is never used for CS) depending on operand 0
129 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
131 * \360 - no SSE prefix (== \364\331)
132 * \361 - 66 SSE prefix (== \366\331)
133 * \362 - F2 SSE prefix (== \364\332)
134 * \363 - F3 SSE prefix (== \364\333)
135 * \364 - operand-size prefix (0x66) not permitted
136 * \365 - address-size prefix (0x67) not permitted
137 * \366 - operand-size prefix (0x66) used as opcode extension
138 * \367 - address-size prefix (0x67) used as opcode extension
139 * \370,\371 - match only if operand 0 meets byte jump criteria.
140 * 370 is used for Jcc, 371 is used for JMP.
141 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
142 * used for conditional jump over longer jump
143 * \374 - this instruction takes an XMM VSIB memory EA
144 * \375 - this instruction takes an YMM VSIB memory EA
147 #include "compiler.h"
151 #include <inttypes.h>
155 #include "assemble.h"
161 * Matching errors. These should be sorted so that more specific
162 * errors come later in the sequence.
171 * Matching success; the conditional ones first
173 MOK_JUMP, /* Matching OK but needs jmp_match() */
174 MOK_GOOD /* Matching unconditionally OK */
178 enum ea_type type; /* what kind of EA is this? */
179 int sib_present; /* is a SIB byte necessary? */
180 int bytes; /* # of bytes of offset needed */
181 int size; /* lazy - this is sib+bytes+1 */
182 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
185 #define GEN_SIB(scale, index, base) \
186 (((scale) << 6) | ((index) << 3) | ((base)))
188 #define GEN_MODRM(mod, reg, rm) \
189 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
191 static uint32_t cpu; /* cpu level received from nasm.c */
192 static efunc errfunc;
193 static struct ofmt *outfmt;
194 static ListGen *list;
196 static int64_t calcsize(int32_t, int64_t, int, insn *,
197 const struct itemplate *);
198 static void gencode(int32_t segment, int64_t offset, int bits,
199 insn * ins, const struct itemplate *temp,
201 static enum match_result find_match(const struct itemplate **tempp,
203 int32_t segment, int64_t offset, int bits);
204 static enum match_result matches(const struct itemplate *, insn *, int bits);
205 static opflags_t regflag(const operand *);
206 static int32_t regval(const operand *);
207 static int rexflags(int, opflags_t, int);
208 static int op_rexflags(const operand *, int);
209 static void add_asp(insn *, int);
211 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
213 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
215 return ins->prefixes[pos] == prefix;
218 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
220 if (ins->prefixes[pos])
221 errfunc(ERR_NONFATAL, "invalid %s prefix",
222 prefix_name(ins->prefixes[pos]));
225 static const char *size_name(int size)
247 static void warn_overflow(int pass, int size)
249 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
250 "%s data exceeds bounds", size_name(size));
253 static void warn_overflow_const(int64_t data, int size)
255 if (overflow_general(data, size))
256 warn_overflow(ERR_PASS1, size);
259 static void warn_overflow_opd(const struct operand *o, int size)
261 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
262 if (overflow_general(o->offset, size))
263 warn_overflow(ERR_PASS2, size);
268 * This routine wrappers the real output format's output routine,
269 * in order to pass a copy of the data off to the listing file
270 * generator at the same time.
272 static void out(int64_t offset, int32_t segto, const void *data,
273 enum out_type type, uint64_t size,
274 int32_t segment, int32_t wrt)
276 static int32_t lineno = 0; /* static!!! */
277 static char *lnfname = NULL;
280 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
282 * This is a non-relocated address, and we're going to
283 * convert it into RAWDATA format.
288 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
292 WRITEADDR(q, *(int64_t *)data, size);
297 list->output(offset, data, type, size);
300 * this call to src_get determines when we call the
301 * debug-format-specific "linenum" function
302 * it updates lineno and lnfname to the current values
303 * returning 0 if "same as last time", -2 if lnfname
304 * changed, and the amount by which lineno changed,
305 * if it did. thus, these variables must be static
308 if (src_get(&lineno, &lnfname))
309 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
311 outfmt->output(segto, data, type, size, segment, wrt);
314 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
316 if (opx->segment != NO_SEG) {
317 uint64_t data = opx->offset;
318 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
320 uint8_t byte = opx->offset;
321 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
325 static bool jmp_match(int32_t segment, int64_t offset, int bits,
326 insn * ins, const struct itemplate *temp)
329 const uint8_t *code = temp->code;
332 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
336 if (optimizing < 0 && c == 0371)
339 isize = calcsize(segment, offset, bits, ins, temp);
341 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
342 /* Be optimistic in pass 1 */
345 if (ins->oprs[0].segment != segment)
348 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
349 return (isize >= -128 && isize <= 127); /* is it byte size? */
352 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
353 insn * instruction, struct ofmt *output, efunc error,
356 const struct itemplate *temp;
361 int64_t start = offset;
362 int64_t wsize; /* size for DB etc. */
364 errfunc = error; /* to pass to other functions */
366 outfmt = output; /* likewise */
367 list = listgen; /* and again */
369 wsize = idata_bytes(instruction->opcode);
375 int32_t t = instruction->times;
378 "instruction->times < 0 (%ld) in assemble()", t);
380 while (t--) { /* repeat TIMES times */
381 list_for_each(e, instruction->eops) {
382 if (e->type == EOT_DB_NUMBER) {
384 errfunc(ERR_NONFATAL,
385 "integer supplied to a DT, DO or DY"
388 out(offset, segment, &e->offset,
389 OUT_ADDRESS, wsize, e->segment, e->wrt);
392 } else if (e->type == EOT_DB_STRING ||
393 e->type == EOT_DB_STRING_FREE) {
396 out(offset, segment, e->stringval,
397 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
398 align = e->stringlen % wsize;
401 align = wsize - align;
402 out(offset, segment, zero_buffer,
403 OUT_RAWDATA, align, NO_SEG, NO_SEG);
405 offset += e->stringlen + align;
408 if (t > 0 && t == instruction->times - 1) {
410 * Dummy call to list->output to give the offset to the
413 list->output(offset, NULL, OUT_RAWDATA, 0);
414 list->uplevel(LIST_TIMES);
417 if (instruction->times > 1)
418 list->downlevel(LIST_TIMES);
419 return offset - start;
422 if (instruction->opcode == I_INCBIN) {
423 const char *fname = instruction->eops->stringval;
426 fp = fopen(fname, "rb");
428 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
430 } else if (fseek(fp, 0L, SEEK_END) < 0) {
431 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
434 static char buf[4096];
435 size_t t = instruction->times;
440 if (instruction->eops->next) {
441 base = instruction->eops->next->offset;
443 if (instruction->eops->next->next &&
444 len > (size_t)instruction->eops->next->next->offset)
445 len = (size_t)instruction->eops->next->next->offset;
448 * Dummy call to list->output to give the offset to the
451 list->output(offset, NULL, OUT_RAWDATA, 0);
452 list->uplevel(LIST_INCBIN);
456 fseek(fp, base, SEEK_SET);
460 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
463 * This shouldn't happen unless the file
464 * actually changes while we are reading
468 "`incbin': unexpected EOF while"
469 " reading file `%s'", fname);
470 t = 0; /* Try to exit cleanly */
473 out(offset, segment, buf, OUT_RAWDATA, m,
478 list->downlevel(LIST_INCBIN);
479 if (instruction->times > 1) {
481 * Dummy call to list->output to give the offset to the
484 list->output(offset, NULL, OUT_RAWDATA, 0);
485 list->uplevel(LIST_TIMES);
486 list->downlevel(LIST_TIMES);
489 return instruction->times * len;
491 return 0; /* if we're here, there's an error */
494 /* Check to see if we need an address-size prefix */
495 add_asp(instruction, bits);
497 m = find_match(&temp, instruction, segment, offset, bits);
501 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
502 itimes = instruction->times;
503 if (insn_size < 0) /* shouldn't be, on pass two */
504 error(ERR_PANIC, "errors made it through from pass one");
507 for (j = 0; j < MAXPREFIX; j++) {
509 switch (instruction->prefixes[j]) {
529 error(ERR_WARNING | ERR_PASS2,
530 "cs segment base generated, but will be ignored in 64-bit mode");
536 error(ERR_WARNING | ERR_PASS2,
537 "ds segment base generated, but will be ignored in 64-bit mode");
543 error(ERR_WARNING | ERR_PASS2,
544 "es segment base generated, but will be ignored in 64-bit mode");
556 error(ERR_WARNING | ERR_PASS2,
557 "ss segment base generated, but will be ignored in 64-bit mode");
564 "segr6 and segr7 cannot be used as prefixes");
569 "16-bit addressing is not supported "
571 } else if (bits != 16)
581 "64-bit addressing is only supported "
605 error(ERR_PANIC, "invalid instruction prefix");
608 out(offset, segment, &c, OUT_RAWDATA, 1,
613 insn_end = offset + insn_size;
614 gencode(segment, offset, bits, instruction,
617 if (itimes > 0 && itimes == instruction->times - 1) {
619 * Dummy call to list->output to give the offset to the
622 list->output(offset, NULL, OUT_RAWDATA, 0);
623 list->uplevel(LIST_TIMES);
626 if (instruction->times > 1)
627 list->downlevel(LIST_TIMES);
628 return offset - start;
632 case MERR_OPSIZEMISSING:
633 error(ERR_NONFATAL, "operation size not specified");
635 case MERR_OPSIZEMISMATCH:
636 error(ERR_NONFATAL, "mismatch in operand sizes");
639 error(ERR_NONFATAL, "no instruction for this cpu level");
642 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
647 "invalid combination of opcode and operands");
654 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
655 insn * instruction, efunc error)
657 const struct itemplate *temp;
660 errfunc = error; /* to pass to other functions */
663 if (instruction->opcode == I_none)
666 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
667 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
668 instruction->opcode == I_DT || instruction->opcode == I_DO ||
669 instruction->opcode == I_DY) {
671 int32_t isize, osize, wsize;
674 wsize = idata_bytes(instruction->opcode);
676 list_for_each(e, instruction->eops) {
680 if (e->type == EOT_DB_NUMBER) {
682 warn_overflow_const(e->offset, wsize);
683 } else if (e->type == EOT_DB_STRING ||
684 e->type == EOT_DB_STRING_FREE)
685 osize = e->stringlen;
687 align = (-osize) % wsize;
690 isize += osize + align;
692 return isize * instruction->times;
695 if (instruction->opcode == I_INCBIN) {
696 const char *fname = instruction->eops->stringval;
701 fp = fopen(fname, "rb");
703 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
705 else if (fseek(fp, 0L, SEEK_END) < 0)
706 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
710 if (instruction->eops->next) {
711 len -= instruction->eops->next->offset;
712 if (instruction->eops->next->next &&
713 len > (size_t)instruction->eops->next->next->offset) {
714 len = (size_t)instruction->eops->next->next->offset;
717 val = instruction->times * len;
724 /* Check to see if we need an address-size prefix */
725 add_asp(instruction, bits);
727 m = find_match(&temp, instruction, segment, offset, bits);
729 /* we've matched an instruction. */
733 isize = calcsize(segment, offset, bits, instruction, temp);
736 for (j = 0; j < MAXPREFIX; j++) {
737 switch (instruction->prefixes[j]) {
763 return isize * instruction->times;
765 return -1; /* didn't match any instruction */
769 static void bad_hle_warn(const insn * ins, uint8_t hleok)
771 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
772 enum whatwarn { w_none, w_lock, w_inval } ww;
773 static const enum whatwarn warn[2][4] =
775 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
776 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
780 n = (unsigned int)rep_pfx - P_XACQUIRE;
782 return; /* Not XACQUIRE/XRELEASE */
785 if (!is_class(MEMORY, ins->oprs[0].type))
786 ww = w_inval; /* HLE requires operand 0 to be memory */
793 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
794 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
795 "%s with this instruction requires lock",
796 prefix_name(rep_pfx));
801 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
802 "%s invalid with this instruction",
803 prefix_name(rep_pfx));
808 /* Common construct */
809 #define case3(x) case (x): case (x)+1: case (x)+2
810 #define case4(x) case3(x): case (x)+3
812 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
813 insn * ins, const struct itemplate *temp)
815 const uint8_t *codes = temp->code;
824 bool lockcheck = true;
826 ins->rex = 0; /* Ensure REX is reset */
827 eat = EA_SCALAR; /* Expect a scalar EA */
829 if (ins->prefixes[PPS_OSIZE] == P_O64)
832 (void)segment; /* Don't warn that this parameter is unused */
833 (void)offset; /* Don't warn that this parameter is unused */
837 op1 = (c & 3) + ((opex & 1) << 2);
838 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
839 opx = &ins->oprs[op1];
840 opex = 0; /* For the next iteration */
844 codes += c, length += c;
853 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
867 if (opx->type & (BITS16 | BITS32 | BITS64))
868 length += (opx->type & BITS16) ? 2 : 4;
870 length += (bits == 16) ? 2 : 4;
878 length += ins->addr_size >> 3;
886 length += 8; /* MOV reg64/imm */
894 if (opx->type & (BITS16 | BITS32 | BITS64))
895 length += (opx->type & BITS16) ? 2 : 4;
897 length += (bits == 16) ? 2 : 4;
924 ins->vexreg = regval(opx);
925 ins->vex_cm = *codes++;
926 ins->vex_wlp = *codes++;
932 ins->vex_cm = *codes++;
933 ins->vex_wlp = *codes++;
950 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
954 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
961 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
962 has_prefix(ins, PPS_ASIZE, P_A32))
971 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
975 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
977 ins->prefixes[PPS_OSIZE] = P_O16;
983 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
987 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
989 ins->prefixes[PPS_OSIZE] = P_O32;
1031 if (!ins->prefixes[PPS_REP])
1032 ins->prefixes[PPS_REP] = P_REP;
1036 if (!ins->prefixes[PPS_REP])
1037 ins->prefixes[PPS_REP] = P_REPNE;
1041 if (ins->oprs[0].segment != NO_SEG)
1042 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1043 " quantity of BSS space");
1045 length += ins->oprs[0].offset;
1049 if (!ins->prefixes[PPS_WAIT])
1050 ins->prefixes[PPS_WAIT] = P_WAIT;
1104 struct operand *opy = &ins->oprs[op2];
1106 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1109 /* pick rfield from operand b (opx) */
1110 rflags = regflag(opx);
1111 rfield = nasm_regvals[opx->basereg];
1116 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1117 rfield, rflags) != eat) {
1118 errfunc(ERR_NONFATAL, "invalid effective address");
1121 ins->rex |= ea_data.rex;
1122 length += ea_data.size;
1128 errfunc(ERR_PANIC, "internal instruction table corrupt"
1129 ": instruction code \\%o (0x%02X) given", c, c);
1134 ins->rex &= rex_mask;
1136 if (ins->rex & REX_NH) {
1137 if (ins->rex & REX_H) {
1138 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1141 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1144 if (ins->rex & REX_V) {
1145 int bad32 = REX_R|REX_W|REX_X|REX_B;
1147 if (ins->rex & REX_H) {
1148 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1151 switch (ins->vex_wlp & 060) {
1165 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1166 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1169 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1173 } else if (ins->rex & REX_REAL) {
1174 if (ins->rex & REX_H) {
1175 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1177 } else if (bits == 64) {
1179 } else if ((ins->rex & REX_L) &&
1180 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1183 assert_no_prefix(ins, PPS_LOCK);
1184 lockcheck = false; /* Already errored, no need for warning */
1187 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1192 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1193 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1194 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1195 "instruction is not lockable");
1198 bad_hle_warn(ins, hleok);
1203 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1206 if ((ins->rex & REX_REAL) && !(ins->rex & REX_V)) {
1207 ins->rex = (ins->rex & REX_REAL) | REX_P;
1208 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1217 static void gencode(int32_t segment, int64_t offset, int bits,
1218 insn * ins, const struct itemplate *temp,
1226 struct operand *opx;
1227 const uint8_t *codes = temp->code;
1229 enum ea_type eat = EA_SCALAR;
1233 op1 = (c & 3) + ((opex & 1) << 2);
1234 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1235 opx = &ins->oprs[op1];
1236 opex = 0; /* For the next iteration */
1243 offset += emit_rex(ins, segment, offset, bits);
1244 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1256 offset += emit_rex(ins, segment, offset, bits);
1257 bytes[0] = *codes++ + (regval(opx) & 7);
1258 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1263 if (opx->offset < -256 || opx->offset > 255) {
1264 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1265 "byte value exceeds bounds");
1267 out_imm8(offset, segment, opx);
1272 if (opx->offset < 0 || opx->offset > 255)
1273 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1274 "unsigned byte value exceeds bounds");
1275 out_imm8(offset, segment, opx);
1280 warn_overflow_opd(opx, 2);
1282 out(offset, segment, &data, OUT_ADDRESS, 2,
1283 opx->segment, opx->wrt);
1288 if (opx->type & (BITS16 | BITS32))
1289 size = (opx->type & BITS16) ? 2 : 4;
1291 size = (bits == 16) ? 2 : 4;
1292 warn_overflow_opd(opx, size);
1294 out(offset, segment, &data, OUT_ADDRESS, size,
1295 opx->segment, opx->wrt);
1300 warn_overflow_opd(opx, 4);
1302 out(offset, segment, &data, OUT_ADDRESS, 4,
1303 opx->segment, opx->wrt);
1309 size = ins->addr_size >> 3;
1310 warn_overflow_opd(opx, size);
1311 out(offset, segment, &data, OUT_ADDRESS, size,
1312 opx->segment, opx->wrt);
1317 if (opx->segment != segment) {
1319 out(offset, segment, &data,
1320 OUT_REL1ADR, insn_end - offset,
1321 opx->segment, opx->wrt);
1323 data = opx->offset - insn_end;
1324 if (data > 127 || data < -128)
1325 errfunc(ERR_NONFATAL, "short jump is out of range");
1326 out(offset, segment, &data,
1327 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1333 data = (int64_t)opx->offset;
1334 out(offset, segment, &data, OUT_ADDRESS, 8,
1335 opx->segment, opx->wrt);
1340 if (opx->segment != segment) {
1342 out(offset, segment, &data,
1343 OUT_REL2ADR, insn_end - offset,
1344 opx->segment, opx->wrt);
1346 data = opx->offset - insn_end;
1347 out(offset, segment, &data,
1348 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1354 if (opx->type & (BITS16 | BITS32 | BITS64))
1355 size = (opx->type & BITS16) ? 2 : 4;
1357 size = (bits == 16) ? 2 : 4;
1358 if (opx->segment != segment) {
1360 out(offset, segment, &data,
1361 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1362 insn_end - offset, opx->segment, opx->wrt);
1364 data = opx->offset - insn_end;
1365 out(offset, segment, &data,
1366 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1372 if (opx->segment != segment) {
1374 out(offset, segment, &data,
1375 OUT_REL4ADR, insn_end - offset,
1376 opx->segment, opx->wrt);
1378 data = opx->offset - insn_end;
1379 out(offset, segment, &data,
1380 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1386 if (opx->segment == NO_SEG)
1387 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1390 out(offset, segment, &data, OUT_ADDRESS, 2,
1391 outfmt->segbase(1 + opx->segment),
1398 opx = &ins->oprs[c >> 3];
1399 bytes[0] = nasm_regvals[opx->basereg] << 4;
1400 opx = &ins->oprs[c & 7];
1401 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1402 errfunc(ERR_NONFATAL,
1403 "non-absolute expression not permitted as argument %d",
1406 if (opx->offset & ~15) {
1407 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1408 "four-bit argument exceeds bounds");
1410 bytes[0] |= opx->offset & 15;
1412 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1418 opx = &ins->oprs[c >> 4];
1419 bytes[0] = nasm_regvals[opx->basereg] << 4;
1421 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1426 bytes[0] = nasm_regvals[opx->basereg] << 4;
1427 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1433 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1434 (int32_t)data != (int64_t)data) {
1435 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1436 "signed dword immediate exceeds bounds");
1438 out(offset, segment, &data, OUT_ADDRESS, 4,
1439 opx->segment, opx->wrt);
1446 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1447 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1448 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1449 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1450 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1451 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1455 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1456 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1457 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1472 if (ins->rex & REX_W)
1474 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1476 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1481 um = (uint64_t)2 << (s-1);
1484 if (uv > 127 && uv < (uint64_t)-128 &&
1485 (uv < um-128 || uv > um-1)) {
1486 /* If this wasn't explicitly byte-sized, warn as though we
1487 * had fallen through to the imm16/32/64 case.
1489 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1490 "%s value exceeds bounds",
1491 (opx->type & BITS8) ? "signed byte" :
1496 if (opx->segment != NO_SEG) {
1498 out(offset, segment, &data, OUT_ADDRESS, 1,
1499 opx->segment, opx->wrt);
1502 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1513 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1515 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1522 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1524 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1559 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1560 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1569 *bytes = c - 0332 + 0xF2;
1570 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1575 if (ins->rex & REX_R) {
1577 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1580 ins->rex &= ~(REX_L|REX_R);
1591 if (ins->oprs[0].segment != NO_SEG)
1592 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1594 int64_t size = ins->oprs[0].offset;
1596 out(offset, segment, NULL,
1597 OUT_RESERVE, size, NO_SEG, NO_SEG);
1608 switch (ins->oprs[0].basereg) {
1623 "bizarre 8086 segment register received");
1625 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1632 switch (ins->oprs[0].basereg) {
1641 "bizarre 386 segment register received");
1643 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1652 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1658 bytes[0] = c - 0362 + 0xf2;
1659 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1669 *bytes = c - 0366 + 0x66;
1670 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1679 *bytes = bits == 16 ? 3 : 5;
1680 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1710 struct operand *opy = &ins->oprs[op2];
1713 /* pick rfield from operand b (opx) */
1714 rflags = regflag(opx);
1715 rfield = nasm_regvals[opx->basereg];
1717 /* rfield is constant */
1722 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1723 rfield, rflags) != eat)
1724 errfunc(ERR_NONFATAL, "invalid effective address");
1727 *p++ = ea_data.modrm;
1728 if (ea_data.sib_present)
1732 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1735 * Make sure the address gets the right offset in case
1736 * the line breaks in the .lst file (BR 1197827)
1741 switch (ea_data.bytes) {
1751 if (opy->segment == segment) {
1753 if (overflow_signed(data, ea_data.bytes))
1754 warn_overflow(ERR_PASS2, ea_data.bytes);
1755 out(offset, segment, &data, OUT_ADDRESS,
1756 ea_data.bytes, NO_SEG, NO_SEG);
1758 /* overflow check in output/linker? */
1759 out(offset, segment, &data, OUT_REL4ADR,
1760 insn_end - offset, opy->segment, opy->wrt);
1763 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1764 signed_bits(opy->offset, ins->addr_size) !=
1765 signed_bits(opy->offset, ea_data.bytes * 8))
1766 warn_overflow(ERR_PASS2, ea_data.bytes);
1768 out(offset, segment, &data, OUT_ADDRESS,
1769 ea_data.bytes, opy->segment, opy->wrt);
1775 "Invalid amount of bytes (%d) for offset?!",
1784 errfunc(ERR_PANIC, "internal instruction table corrupt"
1785 ": instruction code \\%o (0x%02X) given", c, c);
1791 static opflags_t regflag(const operand * o)
1793 if (!is_register(o->basereg))
1794 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1795 return nasm_reg_flags[o->basereg];
1798 static int32_t regval(const operand * o)
1800 if (!is_register(o->basereg))
1801 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1802 return nasm_regvals[o->basereg];
1805 static int op_rexflags(const operand * o, int mask)
1810 if (!is_register(o->basereg))
1811 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1813 flags = nasm_reg_flags[o->basereg];
1814 val = nasm_regvals[o->basereg];
1816 return rexflags(val, flags, mask);
1819 static int rexflags(int val, opflags_t flags, int mask)
1824 rex |= REX_B|REX_X|REX_R;
1827 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1829 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1835 static enum match_result find_match(const struct itemplate **tempp,
1837 int32_t segment, int64_t offset, int bits)
1839 const struct itemplate *temp;
1840 enum match_result m, merr;
1841 opflags_t xsizeflags[MAX_OPERANDS];
1842 bool opsizemissing = false;
1845 for (i = 0; i < instruction->operands; i++)
1846 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1848 merr = MERR_INVALOP;
1850 for (temp = nasm_instructions[instruction->opcode];
1851 temp->opcode != I_none; temp++) {
1852 m = matches(temp, instruction, bits);
1853 if (m == MOK_JUMP) {
1854 if (jmp_match(segment, offset, bits, instruction, temp))
1858 } else if (m == MERR_OPSIZEMISSING &&
1859 (temp->flags & IF_SMASK) != IF_SX) {
1861 * Missing operand size and a candidate for fuzzy matching...
1863 for (i = 0; i < temp->operands; i++) {
1864 if ((temp->opd[i] & SAME_AS) == 0)
1865 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1867 opsizemissing = true;
1871 if (merr == MOK_GOOD)
1875 /* No match, but see if we can get a fuzzy operand size match... */
1879 for (i = 0; i < instruction->operands; i++) {
1881 * We ignore extrinsic operand sizes on registers, so we should
1882 * never try to fuzzy-match on them. This also resolves the case
1883 * when we have e.g. "xmmrm128" in two different positions.
1885 if (is_class(REGISTER, instruction->oprs[i].type))
1888 /* This tests if xsizeflags[i] has more than one bit set */
1889 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1890 goto done; /* No luck */
1892 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1895 /* Try matching again... */
1896 for (temp = nasm_instructions[instruction->opcode];
1897 temp->opcode != I_none; temp++) {
1898 m = matches(temp, instruction, bits);
1899 if (m == MOK_JUMP) {
1900 if (jmp_match(segment, offset, bits, instruction, temp))
1907 if (merr == MOK_GOOD)
1916 static enum match_result matches(const struct itemplate *itemp,
1917 insn *instruction, int bits)
1919 opflags_t size[MAX_OPERANDS], asize;
1920 bool opsizemissing = false;
1926 if (itemp->opcode != instruction->opcode)
1927 return MERR_INVALOP;
1930 * Count the operands
1932 if (itemp->operands != instruction->operands)
1933 return MERR_INVALOP;
1938 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
1939 return MERR_INVALOP;
1942 * Check that no spurious colons or TOs are present
1944 for (i = 0; i < itemp->operands; i++)
1945 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1946 return MERR_INVALOP;
1949 * Process size flags
1951 switch (itemp->flags & IF_SMASK) {
1991 if (itemp->flags & IF_ARMASK) {
1992 /* S- flags only apply to a specific operand */
1993 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1994 memset(size, 0, sizeof size);
1997 /* S- flags apply to all operands */
1998 for (i = 0; i < MAX_OPERANDS; i++)
2003 * Check that the operand flags all match up,
2004 * it's a bit tricky so lets be verbose:
2006 * 1) Find out the size of operand. If instruction
2007 * doesn't have one specified -- we're trying to
2008 * guess it either from template (IF_S* flag) or
2011 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2012 * (ie the same operand as was specified somewhere in template, and
2013 * this referred operand index is being achieved via ~SAME_AS)
2014 * we are to be sure that both registers (in template and instruction)
2017 * 3) If template operand do not match the instruction OR
2018 * template has an operand size specified AND this size differ
2019 * from which instruction has (perhaps we got it from code bits)
2021 * a) Check that only size of instruction and operand is differ
2022 * other characteristics do match
2023 * b) Perhaps it's a register specified in instruction so
2024 * for such a case we just mark that operand as "size
2025 * missing" and this will turn on fuzzy operand size
2026 * logic facility (handled by a caller)
2028 for (i = 0; i < itemp->operands; i++) {
2029 opflags_t type = instruction->oprs[i].type;
2030 if (!(type & SIZE_MASK))
2033 if (itemp->opd[i] & SAME_AS) {
2034 int j = itemp->opd[i] & ~SAME_AS;
2035 if (type != instruction->oprs[j].type ||
2036 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2037 return MERR_INVALOP;
2038 } else if (itemp->opd[i] & ~type & ~SIZE_MASK) {
2039 return MERR_INVALOP;
2040 } else if ((itemp->opd[i] & SIZE_MASK) &&
2041 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2042 if (type & SIZE_MASK) {
2043 return MERR_INVALOP;
2044 } else if (!is_class(REGISTER, type)) {
2046 * Note: we don't honor extrinsic operand sizes for registers,
2047 * so "missing operand size" for a register should be
2048 * considered a wildcard match rather than an error.
2050 opsizemissing = true;
2056 return MERR_OPSIZEMISSING;
2059 * Check operand sizes
2061 if (itemp->flags & (IF_SM | IF_SM2)) {
2062 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2063 for (i = 0; i < oprs; i++) {
2064 asize = itemp->opd[i] & SIZE_MASK;
2066 for (i = 0; i < oprs; i++)
2072 oprs = itemp->operands;
2075 for (i = 0; i < itemp->operands; i++) {
2076 if (!(itemp->opd[i] & SIZE_MASK) &&
2077 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2078 return MERR_OPSIZEMISMATCH;
2082 * Check template is okay at the set cpu level
2084 if (((itemp->flags & IF_PLEVEL) > cpu))
2088 * Verify the appropriate long mode flag.
2090 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2091 return MERR_BADMODE;
2094 * If we have a HLE prefix, look for the NOHLE flag
2096 if ((itemp->flags & IF_NOHLE) &&
2097 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2098 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2102 * Check if special handling needed for Jumps
2104 if ((itemp->code[0] & ~1) == 0370)
2110 static enum ea_type process_ea(operand *input, ea *output, int bits,
2111 int addrbits, int rfield, opflags_t rflags)
2113 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2115 output->type = EA_SCALAR;
2116 output->rip = false;
2118 /* REX flags for the rfield operand */
2119 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2121 if (is_class(REGISTER, input->type)) {
2123 * It's a direct register.
2125 if (!is_register(input->basereg))
2128 if (!is_class(REG_EA, regflag(input)))
2131 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2132 output->sib_present = false; /* no SIB necessary */
2133 output->bytes = 0; /* no offset necessary either */
2134 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2137 * It's a memory reference.
2139 if (input->basereg == -1 &&
2140 (input->indexreg == -1 || input->scale == 0)) {
2142 * It's a pure offset.
2144 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2145 input->segment == NO_SEG) {
2146 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2147 input->type &= ~IP_REL;
2148 input->type |= MEMORY;
2151 if (input->eaflags & EAF_BYTEOFFS ||
2152 (input->eaflags & EAF_WORDOFFS &&
2153 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2154 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2157 if (bits == 64 && (~input->type & IP_REL)) {
2158 output->sib_present = true;
2159 output->sib = GEN_SIB(0, 4, 5);
2161 output->modrm = GEN_MODRM(0, rfield, 4);
2162 output->rip = false;
2164 output->sib_present = false;
2165 output->bytes = (addrbits != 16 ? 4 : 2);
2166 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2167 output->rip = bits == 64;
2171 * It's an indirection.
2173 int i = input->indexreg, b = input->basereg, s = input->scale;
2174 int32_t seg = input->segment;
2175 int hb = input->hintbase, ht = input->hinttype;
2176 int t, it, bt; /* register numbers */
2177 opflags_t x, ix, bx; /* register flags */
2180 i = -1; /* make this easy, at least */
2182 if (is_register(i)) {
2183 it = nasm_regvals[i];
2184 ix = nasm_reg_flags[i];
2190 if (is_register(b)) {
2191 bt = nasm_regvals[b];
2192 bx = nasm_reg_flags[b];
2198 /* if either one are a vector register... */
2199 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2200 opflags_t sok = BITS32 | BITS64;
2201 int32_t o = input->offset;
2202 int mod, scale, index, base;
2205 * For a vector SIB, one has to be a vector and the other,
2206 * if present, a GPR. The vector must be the index operand.
2208 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2214 t = bt, bt = it, it = t;
2215 x = bx, bx = ix, ix = x;
2221 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2228 * While we're here, ensure the user didn't specify
2231 if (input->disp_size == 16 || input->disp_size == 64)
2234 if (addrbits == 16 ||
2235 (addrbits == 32 && !(sok & BITS32)) ||
2236 (addrbits == 64 && !(sok & BITS64)))
2239 output->type = (ix & YMMREG & ~REG_EA)
2240 ? EA_YMMVSIB : EA_XMMVSIB;
2242 output->rex |= rexflags(it, ix, REX_X);
2243 output->rex |= rexflags(bt, bx, REX_B);
2245 index = it & 7; /* it is known to be != -1 */
2260 default: /* then what the smeg is it? */
2261 goto err; /* panic */
2269 if (base != REG_NUM_EBP && o == 0 &&
2270 seg == NO_SEG && !forw_ref &&
2271 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2273 else if (input->eaflags & EAF_BYTEOFFS ||
2274 (o >= -128 && o <= 127 &&
2275 seg == NO_SEG && !forw_ref &&
2276 !(input->eaflags & EAF_WORDOFFS)))
2282 output->sib_present = true;
2283 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2284 output->modrm = GEN_MODRM(mod, rfield, 4);
2285 output->sib = GEN_SIB(scale, index, base);
2286 } else if ((ix|bx) & (BITS32|BITS64)) {
2288 * it must be a 32/64-bit memory reference. Firstly we have
2289 * to check that all registers involved are type E/Rxx.
2291 opflags_t sok = BITS32 | BITS64;
2292 int32_t o = input->offset;
2295 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2303 goto err; /* Invalid register */
2304 if (~sok & bx & SIZE_MASK)
2305 goto err; /* Invalid size */
2310 * While we're here, ensure the user didn't specify
2313 if (input->disp_size == 16 || input->disp_size == 64)
2316 if (addrbits == 16 ||
2317 (addrbits == 32 && !(sok & BITS32)) ||
2318 (addrbits == 64 && !(sok & BITS64)))
2321 /* now reorganize base/index */
2322 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2323 ((hb == b && ht == EAH_NOTBASE) ||
2324 (hb == i && ht == EAH_MAKEBASE))) {
2325 /* swap if hints say so */
2326 t = bt, bt = it, it = t;
2327 x = bx, bx = ix, ix = x;
2329 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2330 bt = -1, bx = 0, s++;
2331 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2332 /* make single reg base, unless hint */
2333 bt = it, bx = ix, it = -1, ix = 0;
2335 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2336 s == 3 || s == 5 || s == 9) && bt == -1)
2337 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2338 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2339 (input->eaflags & EAF_TIMESTWO))
2340 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2341 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2342 if (s == 1 && it == REG_NUM_ESP) {
2343 /* swap ESP into base if scale is 1 */
2344 t = it, it = bt, bt = t;
2345 x = ix, ix = bx, bx = x;
2347 if (it == REG_NUM_ESP ||
2348 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2349 goto err; /* wrong, for various reasons */
2351 output->rex |= rexflags(it, ix, REX_X);
2352 output->rex |= rexflags(bt, bx, REX_B);
2354 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2363 if (rm != REG_NUM_EBP && o == 0 &&
2364 seg == NO_SEG && !forw_ref &&
2365 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2367 else if (input->eaflags & EAF_BYTEOFFS ||
2368 (o >= -128 && o <= 127 &&
2369 seg == NO_SEG && !forw_ref &&
2370 !(input->eaflags & EAF_WORDOFFS)))
2376 output->sib_present = false;
2377 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2378 output->modrm = GEN_MODRM(mod, rfield, rm);
2381 int mod, scale, index, base;
2401 default: /* then what the smeg is it? */
2402 goto err; /* panic */
2410 if (base != REG_NUM_EBP && o == 0 &&
2411 seg == NO_SEG && !forw_ref &&
2412 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2414 else if (input->eaflags & EAF_BYTEOFFS ||
2415 (o >= -128 && o <= 127 &&
2416 seg == NO_SEG && !forw_ref &&
2417 !(input->eaflags & EAF_WORDOFFS)))
2423 output->sib_present = true;
2424 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2425 output->modrm = GEN_MODRM(mod, rfield, 4);
2426 output->sib = GEN_SIB(scale, index, base);
2428 } else { /* it's 16-bit */
2430 int16_t o = input->offset;
2432 /* check for 64-bit long mode */
2436 /* check all registers are BX, BP, SI or DI */
2437 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2438 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2441 /* ensure the user didn't specify DWORD/QWORD */
2442 if (input->disp_size == 32 || input->disp_size == 64)
2445 if (s != 1 && i != -1)
2446 goto err; /* no can do, in 16-bit EA */
2447 if (b == -1 && i != -1) {
2452 if ((b == R_SI || b == R_DI) && i != -1) {
2457 /* have BX/BP as base, SI/DI index */
2459 goto err; /* shouldn't ever happen, in theory */
2460 if (i != -1 && b != -1 &&
2461 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2462 goto err; /* invalid combinations */
2463 if (b == -1) /* pure offset: handled above */
2464 goto err; /* so if it gets to here, panic! */
2468 switch (i * 256 + b) {
2469 case R_SI * 256 + R_BX:
2472 case R_DI * 256 + R_BX:
2475 case R_SI * 256 + R_BP:
2478 case R_DI * 256 + R_BP:
2496 if (rm == -1) /* can't happen, in theory */
2497 goto err; /* so panic if it does */
2499 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2500 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2502 else if (input->eaflags & EAF_BYTEOFFS ||
2503 (o >= -128 && o <= 127 && seg == NO_SEG &&
2504 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2509 output->sib_present = false; /* no SIB - it's 16-bit */
2510 output->bytes = mod; /* bytes of offset needed */
2511 output->modrm = GEN_MODRM(mod, rfield, rm);
2516 output->size = 1 + output->sib_present + output->bytes;
2517 return output->type;
2520 return output->type = EA_INVALID;
2523 static void add_asp(insn *ins, int addrbits)
2528 valid = (addrbits == 64) ? 64|32 : 32|16;
2530 switch (ins->prefixes[PPS_ASIZE]) {
2541 valid &= (addrbits == 32) ? 16 : 32;
2547 for (j = 0; j < ins->operands; j++) {
2548 if (is_class(MEMORY, ins->oprs[j].type)) {
2551 /* Verify as Register */
2552 if (!is_register(ins->oprs[j].indexreg))
2555 i = nasm_reg_flags[ins->oprs[j].indexreg];
2557 /* Verify as Register */
2558 if (!is_register(ins->oprs[j].basereg))
2561 b = nasm_reg_flags[ins->oprs[j].basereg];
2563 if (ins->oprs[j].scale == 0)
2567 int ds = ins->oprs[j].disp_size;
2568 if ((addrbits != 64 && ds > 8) ||
2569 (addrbits == 64 && ds == 16))
2589 if (valid & addrbits) {
2590 ins->addr_size = addrbits;
2591 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2592 /* Add an address size prefix */
2593 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2594 ins->addr_size = (addrbits == 32) ? 16 : 32;
2597 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2598 ins->addr_size = addrbits; /* Error recovery */
2601 defdisp = ins->addr_size == 16 ? 16 : 32;
2603 for (j = 0; j < ins->operands; j++) {
2604 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2605 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2607 * mem_offs sizes must match the address size; if not,
2608 * strip the MEM_OFFS bit and match only EA instructions
2610 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);