1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \20..\23 - a byte immediate operand, from operand 0..3
46 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
47 * \30..\33 - a word immediate operand, from operand 0..3
48 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
49 * assembly mode or the operand-size override on the operand
50 * \40..\43 - a long immediate operand, from operand 0..3
51 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
52 * depending on the address size of the instruction.
53 * \50..\53 - a byte relative operand, from operand 0..3
54 * \54..\57 - a qword immediate operand, from operand 0..3
55 * \60..\63 - a word relative operand, from operand 0..3
56 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
57 * assembly mode or the operand-size override on the operand
58 * \70..\73 - a long relative operand, from operand 0..3
59 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
60 * \1ab - a ModRM, calculated on EA in operand a, with the spare
61 * field the register value of operand b.
62 * \172\ab - the register number from operand a in bits 7..4, with
63 * the 4-bit immediate from operand b in bits 3..0.
64 * \173\xab - the register number from operand a in bits 7..4, with
65 * the value b in bits 3..0.
66 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
67 * an arbitrary value in bits 3..0 (assembled as zero.)
68 * \2ab - a ModRM, calculated on EA in operand a, with the spare
69 * field equal to digit b.
70 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
71 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
72 * V field taken from operand 0..3.
73 * \270 - this instruction uses VEX/XOP rather than REX, with the
74 * V field set to 1111b.
76 * VEX/XOP prefixes are followed by the sequence:
77 * \tmm\wlp where mm is the M field; and wlp is:
79 * [l0] ll = 0 for L = 0 (.128, .lz)
80 * [l1] ll = 1 for L = 1 (.256)
81 * [lig] ll = 2 for L don't care (always assembled as 0)
83 * [w0] ww = 0 for W = 0
84 * [w1 ] ww = 1 for W = 1
85 * [wig] ww = 2 for W don't care (always assembled as 0)
86 * [ww] ww = 3 for W used as REX.W
88 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
90 * \271 - instruction takes XRELEASE (F3) with or without lock
91 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
92 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
93 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
94 * to the operand size (if o16/o32/o64 present) or the bit size
95 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
96 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
97 * \312 - (disassembler only) invalid with non-default address size.
98 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
99 * \314 - (disassembler only) invalid with REX.B
100 * \315 - (disassembler only) invalid with REX.X
101 * \316 - (disassembler only) invalid with REX.R
102 * \317 - (disassembler only) invalid with REX.W
103 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
104 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
105 * \322 - indicates that this instruction is only valid when the
106 * operand size is the default (instruction to disassembler,
107 * generates no code in the assembler)
108 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
109 * \324 - indicates 64-bit operand size requiring REX prefix.
110 * \325 - instruction which always uses spl/bpl/sil/dil
111 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
112 disassembler only; for SSE instructions.
113 * \330 - a literal byte follows in the code stream, to be added
114 * to the condition code value of the instruction.
115 * \331 - instruction not valid with REP prefix. Hint for
116 * disassembler only; for SSE instructions.
117 * \332 - REP prefix (0xF2 byte) used as opcode extension.
118 * \333 - REP prefix (0xF3 byte) used as opcode extension.
119 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
120 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
121 * \336 - force a REP(E) prefix (0xF3) even if not specified.
122 * \337 - force a REPNE prefix (0xF2) even if not specified.
123 * \336-\337 are still listed as prefixes in the disassembler.
124 * \340 - reserve <operand 0> bytes of uninitialized storage.
125 * Operand 0 had better be a segmentless constant.
126 * \341 - this instruction needs a WAIT "prefix"
127 * \360 - no SSE prefix (== \364\331)
128 * \361 - 66 SSE prefix (== \366\331)
129 * \362 - F2 SSE prefix (== \364\332)
130 * \363 - F3 SSE prefix (== \364\333)
131 * \364 - operand-size prefix (0x66) not permitted
132 * \365 - address-size prefix (0x67) not permitted
133 * \366 - operand-size prefix (0x66) used as opcode extension
134 * \367 - address-size prefix (0x67) used as opcode extension
135 * \370,\371 - match only if operand 0 meets byte jump criteria.
136 * 370 is used for Jcc, 371 is used for JMP.
137 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
138 * used for conditional jump over longer jump
139 * \374 - this instruction takes an XMM VSIB memory EA
140 * \375 - this instruction takes an YMM VSIB memory EA
143 #include "compiler.h"
147 #include <inttypes.h>
151 #include "assemble.h"
157 * Matching errors. These should be sorted so that more specific
158 * errors come later in the sequence.
167 * Matching success; the conditional ones first
169 MOK_JUMP, /* Matching OK but needs jmp_match() */
170 MOK_GOOD /* Matching unconditionally OK */
174 enum ea_type type; /* what kind of EA is this? */
175 int sib_present; /* is a SIB byte necessary? */
176 int bytes; /* # of bytes of offset needed */
177 int size; /* lazy - this is sib+bytes+1 */
178 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
181 #define GEN_SIB(scale, index, base) \
182 (((scale) << 6) | ((index) << 3) | ((base)))
184 #define GEN_MODRM(mod, reg, rm) \
185 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
187 static uint32_t cpu; /* cpu level received from nasm.c */
188 static efunc errfunc;
189 static struct ofmt *outfmt;
190 static ListGen *list;
192 static int64_t calcsize(int32_t, int64_t, int, insn *,
193 const struct itemplate *);
194 static void gencode(int32_t segment, int64_t offset, int bits,
195 insn * ins, const struct itemplate *temp,
197 static enum match_result find_match(const struct itemplate **tempp,
199 int32_t segment, int64_t offset, int bits);
200 static enum match_result matches(const struct itemplate *, insn *, int bits);
201 static opflags_t regflag(const operand *);
202 static int32_t regval(const operand *);
203 static int rexflags(int, opflags_t, int);
204 static int op_rexflags(const operand *, int);
205 static void add_asp(insn *, int);
207 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
209 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
211 return ins->prefixes[pos] == prefix;
214 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
216 if (ins->prefixes[pos])
217 errfunc(ERR_NONFATAL, "invalid %s prefix",
218 prefix_name(ins->prefixes[pos]));
221 static const char *size_name(int size)
243 static void warn_overflow(int pass, int size)
245 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
246 "%s data exceeds bounds", size_name(size));
249 static void warn_overflow_const(int64_t data, int size)
251 if (overflow_general(data, size))
252 warn_overflow(ERR_PASS1, size);
255 static void warn_overflow_opd(const struct operand *o, int size)
257 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
258 if (overflow_general(o->offset, size))
259 warn_overflow(ERR_PASS2, size);
264 * This routine wrappers the real output format's output routine,
265 * in order to pass a copy of the data off to the listing file
266 * generator at the same time.
268 static void out(int64_t offset, int32_t segto, const void *data,
269 enum out_type type, uint64_t size,
270 int32_t segment, int32_t wrt)
272 static int32_t lineno = 0; /* static!!! */
273 static char *lnfname = NULL;
276 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
278 * This is a non-relocated address, and we're going to
279 * convert it into RAWDATA format.
284 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
288 WRITEADDR(q, *(int64_t *)data, size);
293 list->output(offset, data, type, size);
296 * this call to src_get determines when we call the
297 * debug-format-specific "linenum" function
298 * it updates lineno and lnfname to the current values
299 * returning 0 if "same as last time", -2 if lnfname
300 * changed, and the amount by which lineno changed,
301 * if it did. thus, these variables must be static
304 if (src_get(&lineno, &lnfname))
305 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
307 outfmt->output(segto, data, type, size, segment, wrt);
310 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
312 if (opx->segment != NO_SEG) {
313 uint64_t data = opx->offset;
314 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
316 uint8_t byte = opx->offset;
317 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
321 static bool jmp_match(int32_t segment, int64_t offset, int bits,
322 insn * ins, const struct itemplate *temp)
325 const uint8_t *code = temp->code;
328 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
332 if (optimizing < 0 && c == 0371)
335 isize = calcsize(segment, offset, bits, ins, temp);
337 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
338 /* Be optimistic in pass 1 */
341 if (ins->oprs[0].segment != segment)
344 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
345 return (isize >= -128 && isize <= 127); /* is it byte size? */
348 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
349 insn * instruction, struct ofmt *output, efunc error,
352 const struct itemplate *temp;
357 int64_t start = offset;
358 int64_t wsize; /* size for DB etc. */
360 errfunc = error; /* to pass to other functions */
362 outfmt = output; /* likewise */
363 list = listgen; /* and again */
365 wsize = idata_bytes(instruction->opcode);
371 int32_t t = instruction->times;
374 "instruction->times < 0 (%ld) in assemble()", t);
376 while (t--) { /* repeat TIMES times */
377 list_for_each(e, instruction->eops) {
378 if (e->type == EOT_DB_NUMBER) {
380 errfunc(ERR_NONFATAL,
381 "integer supplied to a DT, DO or DY"
384 out(offset, segment, &e->offset,
385 OUT_ADDRESS, wsize, e->segment, e->wrt);
388 } else if (e->type == EOT_DB_STRING ||
389 e->type == EOT_DB_STRING_FREE) {
392 out(offset, segment, e->stringval,
393 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
394 align = e->stringlen % wsize;
397 align = wsize - align;
398 out(offset, segment, zero_buffer,
399 OUT_RAWDATA, align, NO_SEG, NO_SEG);
401 offset += e->stringlen + align;
404 if (t > 0 && t == instruction->times - 1) {
406 * Dummy call to list->output to give the offset to the
409 list->output(offset, NULL, OUT_RAWDATA, 0);
410 list->uplevel(LIST_TIMES);
413 if (instruction->times > 1)
414 list->downlevel(LIST_TIMES);
415 return offset - start;
418 if (instruction->opcode == I_INCBIN) {
419 const char *fname = instruction->eops->stringval;
422 fp = fopen(fname, "rb");
424 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
426 } else if (fseek(fp, 0L, SEEK_END) < 0) {
427 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
430 static char buf[4096];
431 size_t t = instruction->times;
436 if (instruction->eops->next) {
437 base = instruction->eops->next->offset;
439 if (instruction->eops->next->next &&
440 len > (size_t)instruction->eops->next->next->offset)
441 len = (size_t)instruction->eops->next->next->offset;
444 * Dummy call to list->output to give the offset to the
447 list->output(offset, NULL, OUT_RAWDATA, 0);
448 list->uplevel(LIST_INCBIN);
452 fseek(fp, base, SEEK_SET);
456 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
459 * This shouldn't happen unless the file
460 * actually changes while we are reading
464 "`incbin': unexpected EOF while"
465 " reading file `%s'", fname);
466 t = 0; /* Try to exit cleanly */
469 out(offset, segment, buf, OUT_RAWDATA, m,
474 list->downlevel(LIST_INCBIN);
475 if (instruction->times > 1) {
477 * Dummy call to list->output to give the offset to the
480 list->output(offset, NULL, OUT_RAWDATA, 0);
481 list->uplevel(LIST_TIMES);
482 list->downlevel(LIST_TIMES);
485 return instruction->times * len;
487 return 0; /* if we're here, there's an error */
490 /* Check to see if we need an address-size prefix */
491 add_asp(instruction, bits);
493 m = find_match(&temp, instruction, segment, offset, bits);
497 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
498 itimes = instruction->times;
499 if (insn_size < 0) /* shouldn't be, on pass two */
500 error(ERR_PANIC, "errors made it through from pass one");
503 for (j = 0; j < MAXPREFIX; j++) {
505 switch (instruction->prefixes[j]) {
525 error(ERR_WARNING | ERR_PASS2,
526 "cs segment base generated, but will be ignored in 64-bit mode");
532 error(ERR_WARNING | ERR_PASS2,
533 "ds segment base generated, but will be ignored in 64-bit mode");
539 error(ERR_WARNING | ERR_PASS2,
540 "es segment base generated, but will be ignored in 64-bit mode");
552 error(ERR_WARNING | ERR_PASS2,
553 "ss segment base generated, but will be ignored in 64-bit mode");
560 "segr6 and segr7 cannot be used as prefixes");
565 "16-bit addressing is not supported "
567 } else if (bits != 16)
577 "64-bit addressing is only supported "
601 error(ERR_PANIC, "invalid instruction prefix");
604 out(offset, segment, &c, OUT_RAWDATA, 1,
609 insn_end = offset + insn_size;
610 gencode(segment, offset, bits, instruction,
613 if (itimes > 0 && itimes == instruction->times - 1) {
615 * Dummy call to list->output to give the offset to the
618 list->output(offset, NULL, OUT_RAWDATA, 0);
619 list->uplevel(LIST_TIMES);
622 if (instruction->times > 1)
623 list->downlevel(LIST_TIMES);
624 return offset - start;
628 case MERR_OPSIZEMISSING:
629 error(ERR_NONFATAL, "operation size not specified");
631 case MERR_OPSIZEMISMATCH:
632 error(ERR_NONFATAL, "mismatch in operand sizes");
635 error(ERR_NONFATAL, "no instruction for this cpu level");
638 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
643 "invalid combination of opcode and operands");
650 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
651 insn * instruction, efunc error)
653 const struct itemplate *temp;
656 errfunc = error; /* to pass to other functions */
659 if (instruction->opcode == I_none)
662 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
663 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
664 instruction->opcode == I_DT || instruction->opcode == I_DO ||
665 instruction->opcode == I_DY) {
667 int32_t isize, osize, wsize;
670 wsize = idata_bytes(instruction->opcode);
672 list_for_each(e, instruction->eops) {
676 if (e->type == EOT_DB_NUMBER) {
678 warn_overflow_const(e->offset, wsize);
679 } else if (e->type == EOT_DB_STRING ||
680 e->type == EOT_DB_STRING_FREE)
681 osize = e->stringlen;
683 align = (-osize) % wsize;
686 isize += osize + align;
688 return isize * instruction->times;
691 if (instruction->opcode == I_INCBIN) {
692 const char *fname = instruction->eops->stringval;
697 fp = fopen(fname, "rb");
699 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
701 else if (fseek(fp, 0L, SEEK_END) < 0)
702 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
706 if (instruction->eops->next) {
707 len -= instruction->eops->next->offset;
708 if (instruction->eops->next->next &&
709 len > (size_t)instruction->eops->next->next->offset) {
710 len = (size_t)instruction->eops->next->next->offset;
713 val = instruction->times * len;
720 /* Check to see if we need an address-size prefix */
721 add_asp(instruction, bits);
723 m = find_match(&temp, instruction, segment, offset, bits);
725 /* we've matched an instruction. */
729 isize = calcsize(segment, offset, bits, instruction, temp);
732 for (j = 0; j < MAXPREFIX; j++) {
733 switch (instruction->prefixes[j]) {
759 return isize * instruction->times;
761 return -1; /* didn't match any instruction */
765 static void bad_hle_warn(const insn * ins, uint8_t hleok)
767 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
768 enum whatwarn { w_none, w_lock, w_inval } ww;
769 static const enum whatwarn warn[2][4] =
771 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
772 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
776 n = (unsigned int)rep_pfx - P_XACQUIRE;
778 return; /* Not XACQUIRE/XRELEASE */
781 if (!is_class(MEMORY, ins->oprs[0].type))
782 ww = w_inval; /* HLE requires operand 0 to be memory */
789 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
790 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
791 "%s with this instruction requires lock",
792 prefix_name(rep_pfx));
797 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
798 "%s invalid with this instruction",
799 prefix_name(rep_pfx));
804 /* Common construct */
805 #define case3(x) case (x): case (x)+1: case (x)+2
806 #define case4(x) case3(x): case (x)+3
808 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
809 insn * ins, const struct itemplate *temp)
811 const uint8_t *codes = temp->code;
820 bool lockcheck = true;
822 ins->rex = 0; /* Ensure REX is reset */
823 eat = EA_SCALAR; /* Expect a scalar EA */
825 if (ins->prefixes[PPS_OSIZE] == P_O64)
828 (void)segment; /* Don't warn that this parameter is unused */
829 (void)offset; /* Don't warn that this parameter is unused */
833 op1 = (c & 3) + ((opex & 1) << 2);
834 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
835 opx = &ins->oprs[op1];
836 opex = 0; /* For the next iteration */
840 codes += c, length += c;
849 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
863 if (opx->type & (BITS16 | BITS32 | BITS64))
864 length += (opx->type & BITS16) ? 2 : 4;
866 length += (bits == 16) ? 2 : 4;
874 length += ins->addr_size >> 3;
882 length += 8; /* MOV reg64/imm */
890 if (opx->type & (BITS16 | BITS32 | BITS64))
891 length += (opx->type & BITS16) ? 2 : 4;
893 length += (bits == 16) ? 2 : 4;
920 ins->vexreg = regval(opx);
921 ins->vex_cm = *codes++;
922 ins->vex_wlp = *codes++;
928 ins->vex_cm = *codes++;
929 ins->vex_wlp = *codes++;
946 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
950 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
957 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
958 has_prefix(ins, PPS_ASIZE, P_A32))
967 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
971 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
973 ins->prefixes[PPS_OSIZE] = P_O16;
979 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
983 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
985 ins->prefixes[PPS_OSIZE] = P_O32;
1027 if (!ins->prefixes[PPS_REP])
1028 ins->prefixes[PPS_REP] = P_REP;
1032 if (!ins->prefixes[PPS_REP])
1033 ins->prefixes[PPS_REP] = P_REPNE;
1037 if (ins->oprs[0].segment != NO_SEG)
1038 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1039 " quantity of BSS space");
1041 length += ins->oprs[0].offset;
1045 if (!ins->prefixes[PPS_WAIT])
1046 ins->prefixes[PPS_WAIT] = P_WAIT;
1096 struct operand *opy = &ins->oprs[op2];
1098 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1101 /* pick rfield from operand b (opx) */
1102 rflags = regflag(opx);
1103 rfield = nasm_regvals[opx->basereg];
1108 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1109 rfield, rflags) != eat) {
1110 errfunc(ERR_NONFATAL, "invalid effective address");
1113 ins->rex |= ea_data.rex;
1114 length += ea_data.size;
1120 errfunc(ERR_PANIC, "internal instruction table corrupt"
1121 ": instruction code \\%o (0x%02X) given", c, c);
1126 ins->rex &= rex_mask;
1128 if (ins->rex & REX_NH) {
1129 if (ins->rex & REX_H) {
1130 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1133 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1136 if (ins->rex & REX_V) {
1137 int bad32 = REX_R|REX_W|REX_X|REX_B;
1139 if (ins->rex & REX_H) {
1140 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1143 switch (ins->vex_wlp & 060) {
1157 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1158 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1161 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1165 } else if (ins->rex & REX_REAL) {
1166 if (ins->rex & REX_H) {
1167 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1169 } else if (bits == 64) {
1171 } else if ((ins->rex & REX_L) &&
1172 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1175 assert_no_prefix(ins, PPS_LOCK);
1176 lockcheck = false; /* Already errored, no need for warning */
1179 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1184 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1185 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1186 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1187 "instruction is not lockable");
1190 bad_hle_warn(ins, hleok);
1195 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1198 if ((ins->rex & REX_REAL) && !(ins->rex & REX_V)) {
1199 ins->rex = (ins->rex & REX_REAL) | REX_P;
1200 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1209 static void gencode(int32_t segment, int64_t offset, int bits,
1210 insn * ins, const struct itemplate *temp,
1218 struct operand *opx;
1219 const uint8_t *codes = temp->code;
1221 enum ea_type eat = EA_SCALAR;
1225 op1 = (c & 3) + ((opex & 1) << 2);
1226 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1227 opx = &ins->oprs[op1];
1228 opex = 0; /* For the next iteration */
1235 offset += emit_rex(ins, segment, offset, bits);
1236 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1248 offset += emit_rex(ins, segment, offset, bits);
1249 bytes[0] = *codes++ + (regval(opx) & 7);
1250 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1255 if (opx->offset < -256 || opx->offset > 255) {
1256 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1257 "byte value exceeds bounds");
1259 out_imm8(offset, segment, opx);
1264 if (opx->offset < 0 || opx->offset > 255)
1265 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1266 "unsigned byte value exceeds bounds");
1267 out_imm8(offset, segment, opx);
1272 warn_overflow_opd(opx, 2);
1274 out(offset, segment, &data, OUT_ADDRESS, 2,
1275 opx->segment, opx->wrt);
1280 if (opx->type & (BITS16 | BITS32))
1281 size = (opx->type & BITS16) ? 2 : 4;
1283 size = (bits == 16) ? 2 : 4;
1284 warn_overflow_opd(opx, size);
1286 out(offset, segment, &data, OUT_ADDRESS, size,
1287 opx->segment, opx->wrt);
1292 warn_overflow_opd(opx, 4);
1294 out(offset, segment, &data, OUT_ADDRESS, 4,
1295 opx->segment, opx->wrt);
1301 size = ins->addr_size >> 3;
1302 warn_overflow_opd(opx, size);
1303 out(offset, segment, &data, OUT_ADDRESS, size,
1304 opx->segment, opx->wrt);
1309 if (opx->segment != segment) {
1311 out(offset, segment, &data,
1312 OUT_REL1ADR, insn_end - offset,
1313 opx->segment, opx->wrt);
1315 data = opx->offset - insn_end;
1316 if (data > 127 || data < -128)
1317 errfunc(ERR_NONFATAL, "short jump is out of range");
1318 out(offset, segment, &data,
1319 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1325 data = (int64_t)opx->offset;
1326 out(offset, segment, &data, OUT_ADDRESS, 8,
1327 opx->segment, opx->wrt);
1332 if (opx->segment != segment) {
1334 out(offset, segment, &data,
1335 OUT_REL2ADR, insn_end - offset,
1336 opx->segment, opx->wrt);
1338 data = opx->offset - insn_end;
1339 out(offset, segment, &data,
1340 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1346 if (opx->type & (BITS16 | BITS32 | BITS64))
1347 size = (opx->type & BITS16) ? 2 : 4;
1349 size = (bits == 16) ? 2 : 4;
1350 if (opx->segment != segment) {
1352 out(offset, segment, &data,
1353 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1354 insn_end - offset, opx->segment, opx->wrt);
1356 data = opx->offset - insn_end;
1357 out(offset, segment, &data,
1358 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1364 if (opx->segment != segment) {
1366 out(offset, segment, &data,
1367 OUT_REL4ADR, insn_end - offset,
1368 opx->segment, opx->wrt);
1370 data = opx->offset - insn_end;
1371 out(offset, segment, &data,
1372 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1378 if (opx->segment == NO_SEG)
1379 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1382 out(offset, segment, &data, OUT_ADDRESS, 2,
1383 outfmt->segbase(1 + opx->segment),
1390 opx = &ins->oprs[c >> 3];
1391 bytes[0] = nasm_regvals[opx->basereg] << 4;
1392 opx = &ins->oprs[c & 7];
1393 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1394 errfunc(ERR_NONFATAL,
1395 "non-absolute expression not permitted as argument %d",
1398 if (opx->offset & ~15) {
1399 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1400 "four-bit argument exceeds bounds");
1402 bytes[0] |= opx->offset & 15;
1404 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1410 opx = &ins->oprs[c >> 4];
1411 bytes[0] = nasm_regvals[opx->basereg] << 4;
1413 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1418 bytes[0] = nasm_regvals[opx->basereg] << 4;
1419 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1425 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1426 (int32_t)data != (int64_t)data) {
1427 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1428 "signed dword immediate exceeds bounds");
1430 out(offset, segment, &data, OUT_ADDRESS, 4,
1431 opx->segment, opx->wrt);
1438 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1439 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1440 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1441 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1442 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1443 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1447 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1448 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1449 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1464 if (ins->rex & REX_W)
1466 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1468 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1473 um = (uint64_t)2 << (s-1);
1476 if (uv > 127 && uv < (uint64_t)-128 &&
1477 (uv < um-128 || uv > um-1)) {
1478 /* If this wasn't explicitly byte-sized, warn as though we
1479 * had fallen through to the imm16/32/64 case.
1481 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1482 "%s value exceeds bounds",
1483 (opx->type & BITS8) ? "signed byte" :
1488 if (opx->segment != NO_SEG) {
1490 out(offset, segment, &data, OUT_ADDRESS, 1,
1491 opx->segment, opx->wrt);
1494 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1505 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1507 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1514 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1516 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1551 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1552 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1561 *bytes = c - 0332 + 0xF2;
1562 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1567 if (ins->rex & REX_R) {
1569 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1572 ins->rex &= ~(REX_L|REX_R);
1583 if (ins->oprs[0].segment != NO_SEG)
1584 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1586 int64_t size = ins->oprs[0].offset;
1588 out(offset, segment, NULL,
1589 OUT_RESERVE, size, NO_SEG, NO_SEG);
1602 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1608 bytes[0] = c - 0362 + 0xf2;
1609 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1619 *bytes = c - 0366 + 0x66;
1620 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1629 *bytes = bits == 16 ? 3 : 5;
1630 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1660 struct operand *opy = &ins->oprs[op2];
1663 /* pick rfield from operand b (opx) */
1664 rflags = regflag(opx);
1665 rfield = nasm_regvals[opx->basereg];
1667 /* rfield is constant */
1672 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1673 rfield, rflags) != eat)
1674 errfunc(ERR_NONFATAL, "invalid effective address");
1677 *p++ = ea_data.modrm;
1678 if (ea_data.sib_present)
1682 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1685 * Make sure the address gets the right offset in case
1686 * the line breaks in the .lst file (BR 1197827)
1691 switch (ea_data.bytes) {
1701 if (opy->segment == segment) {
1703 if (overflow_signed(data, ea_data.bytes))
1704 warn_overflow(ERR_PASS2, ea_data.bytes);
1705 out(offset, segment, &data, OUT_ADDRESS,
1706 ea_data.bytes, NO_SEG, NO_SEG);
1708 /* overflow check in output/linker? */
1709 out(offset, segment, &data, OUT_REL4ADR,
1710 insn_end - offset, opy->segment, opy->wrt);
1713 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1714 signed_bits(opy->offset, ins->addr_size) !=
1715 signed_bits(opy->offset, ea_data.bytes * 8))
1716 warn_overflow(ERR_PASS2, ea_data.bytes);
1718 out(offset, segment, &data, OUT_ADDRESS,
1719 ea_data.bytes, opy->segment, opy->wrt);
1725 "Invalid amount of bytes (%d) for offset?!",
1734 errfunc(ERR_PANIC, "internal instruction table corrupt"
1735 ": instruction code \\%o (0x%02X) given", c, c);
1741 static opflags_t regflag(const operand * o)
1743 if (!is_register(o->basereg))
1744 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1745 return nasm_reg_flags[o->basereg];
1748 static int32_t regval(const operand * o)
1750 if (!is_register(o->basereg))
1751 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1752 return nasm_regvals[o->basereg];
1755 static int op_rexflags(const operand * o, int mask)
1760 if (!is_register(o->basereg))
1761 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1763 flags = nasm_reg_flags[o->basereg];
1764 val = nasm_regvals[o->basereg];
1766 return rexflags(val, flags, mask);
1769 static int rexflags(int val, opflags_t flags, int mask)
1774 rex |= REX_B|REX_X|REX_R;
1777 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1779 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1785 static enum match_result find_match(const struct itemplate **tempp,
1787 int32_t segment, int64_t offset, int bits)
1789 const struct itemplate *temp;
1790 enum match_result m, merr;
1791 opflags_t xsizeflags[MAX_OPERANDS];
1792 bool opsizemissing = false;
1795 for (i = 0; i < instruction->operands; i++)
1796 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1798 merr = MERR_INVALOP;
1800 for (temp = nasm_instructions[instruction->opcode];
1801 temp->opcode != I_none; temp++) {
1802 m = matches(temp, instruction, bits);
1803 if (m == MOK_JUMP) {
1804 if (jmp_match(segment, offset, bits, instruction, temp))
1808 } else if (m == MERR_OPSIZEMISSING &&
1809 (temp->flags & IF_SMASK) != IF_SX) {
1811 * Missing operand size and a candidate for fuzzy matching...
1813 for (i = 0; i < temp->operands; i++)
1814 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1815 opsizemissing = true;
1819 if (merr == MOK_GOOD)
1823 /* No match, but see if we can get a fuzzy operand size match... */
1827 for (i = 0; i < instruction->operands; i++) {
1829 * We ignore extrinsic operand sizes on registers, so we should
1830 * never try to fuzzy-match on them. This also resolves the case
1831 * when we have e.g. "xmmrm128" in two different positions.
1833 if (is_class(REGISTER, instruction->oprs[i].type))
1836 /* This tests if xsizeflags[i] has more than one bit set */
1837 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1838 goto done; /* No luck */
1840 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1843 /* Try matching again... */
1844 for (temp = nasm_instructions[instruction->opcode];
1845 temp->opcode != I_none; temp++) {
1846 m = matches(temp, instruction, bits);
1847 if (m == MOK_JUMP) {
1848 if (jmp_match(segment, offset, bits, instruction, temp))
1855 if (merr == MOK_GOOD)
1864 static enum match_result matches(const struct itemplate *itemp,
1865 insn *instruction, int bits)
1867 opflags_t size[MAX_OPERANDS], asize;
1868 bool opsizemissing = false;
1874 if (itemp->opcode != instruction->opcode)
1875 return MERR_INVALOP;
1878 * Count the operands
1880 if (itemp->operands != instruction->operands)
1881 return MERR_INVALOP;
1886 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
1887 return MERR_INVALOP;
1890 * Check that no spurious colons or TOs are present
1892 for (i = 0; i < itemp->operands; i++)
1893 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1894 return MERR_INVALOP;
1897 * Process size flags
1899 switch (itemp->flags & IF_SMASK) {
1939 if (itemp->flags & IF_ARMASK) {
1940 /* S- flags only apply to a specific operand */
1941 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1942 memset(size, 0, sizeof size);
1945 /* S- flags apply to all operands */
1946 for (i = 0; i < MAX_OPERANDS; i++)
1951 * Check that the operand flags all match up,
1952 * it's a bit tricky so lets be verbose:
1954 * 1) Find out the size of operand. If instruction
1955 * doesn't have one specified -- we're trying to
1956 * guess it either from template (IF_S* flag) or
1959 * 2) If template operand do not match the instruction OR
1960 * template has an operand size specified AND this size differ
1961 * from which instruction has (perhaps we got it from code bits)
1963 * a) Check that only size of instruction and operand is differ
1964 * other characteristics do match
1965 * b) Perhaps it's a register specified in instruction so
1966 * for such a case we just mark that operand as "size
1967 * missing" and this will turn on fuzzy operand size
1968 * logic facility (handled by a caller)
1970 for (i = 0; i < itemp->operands; i++) {
1971 opflags_t type = instruction->oprs[i].type;
1972 if (!(type & SIZE_MASK))
1975 if (itemp->opd[i] & ~type & ~SIZE_MASK) {
1976 return MERR_INVALOP;
1977 } else if ((itemp->opd[i] & SIZE_MASK) &&
1978 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
1979 if (type & SIZE_MASK) {
1980 return MERR_INVALOP;
1981 } else if (!is_class(REGISTER, type)) {
1983 * Note: we don't honor extrinsic operand sizes for registers,
1984 * so "missing operand size" for a register should be
1985 * considered a wildcard match rather than an error.
1987 opsizemissing = true;
1993 return MERR_OPSIZEMISSING;
1996 * Check operand sizes
1998 if (itemp->flags & (IF_SM | IF_SM2)) {
1999 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2000 for (i = 0; i < oprs; i++) {
2001 asize = itemp->opd[i] & SIZE_MASK;
2003 for (i = 0; i < oprs; i++)
2009 oprs = itemp->operands;
2012 for (i = 0; i < itemp->operands; i++) {
2013 if (!(itemp->opd[i] & SIZE_MASK) &&
2014 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2015 return MERR_OPSIZEMISMATCH;
2019 * Check template is okay at the set cpu level
2021 if (((itemp->flags & IF_PLEVEL) > cpu))
2025 * Verify the appropriate long mode flag.
2027 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2028 return MERR_BADMODE;
2031 * If we have a HLE prefix, look for the NOHLE flag
2033 if ((itemp->flags & IF_NOHLE) &&
2034 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2035 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2039 * Check if special handling needed for Jumps
2041 if ((itemp->code[0] & ~1) == 0370)
2047 static enum ea_type process_ea(operand *input, ea *output, int bits,
2048 int addrbits, int rfield, opflags_t rflags)
2050 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2052 output->type = EA_SCALAR;
2053 output->rip = false;
2055 /* REX flags for the rfield operand */
2056 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2058 if (is_class(REGISTER, input->type)) {
2060 * It's a direct register.
2062 if (!is_register(input->basereg))
2065 if (!is_class(REG_EA, regflag(input)))
2068 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2069 output->sib_present = false; /* no SIB necessary */
2070 output->bytes = 0; /* no offset necessary either */
2071 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2074 * It's a memory reference.
2076 if (input->basereg == -1 &&
2077 (input->indexreg == -1 || input->scale == 0)) {
2079 * It's a pure offset.
2081 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2082 input->segment == NO_SEG) {
2083 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2084 input->type &= ~IP_REL;
2085 input->type |= MEMORY;
2088 if (input->eaflags & EAF_BYTEOFFS ||
2089 (input->eaflags & EAF_WORDOFFS &&
2090 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2091 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2094 if (bits == 64 && (~input->type & IP_REL)) {
2095 output->sib_present = true;
2096 output->sib = GEN_SIB(0, 4, 5);
2098 output->modrm = GEN_MODRM(0, rfield, 4);
2099 output->rip = false;
2101 output->sib_present = false;
2102 output->bytes = (addrbits != 16 ? 4 : 2);
2103 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2104 output->rip = bits == 64;
2108 * It's an indirection.
2110 int i = input->indexreg, b = input->basereg, s = input->scale;
2111 int32_t seg = input->segment;
2112 int hb = input->hintbase, ht = input->hinttype;
2113 int t, it, bt; /* register numbers */
2114 opflags_t x, ix, bx; /* register flags */
2117 i = -1; /* make this easy, at least */
2119 if (is_register(i)) {
2120 it = nasm_regvals[i];
2121 ix = nasm_reg_flags[i];
2127 if (is_register(b)) {
2128 bt = nasm_regvals[b];
2129 bx = nasm_reg_flags[b];
2135 /* if either one are a vector register... */
2136 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2137 opflags_t sok = BITS32 | BITS64;
2138 int32_t o = input->offset;
2139 int mod, scale, index, base;
2142 * For a vector SIB, one has to be a vector and the other,
2143 * if present, a GPR. The vector must be the index operand.
2145 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2151 t = bt, bt = it, it = t;
2152 x = bx, bx = ix, ix = x;
2158 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2165 * While we're here, ensure the user didn't specify
2168 if (input->disp_size == 16 || input->disp_size == 64)
2171 if (addrbits == 16 ||
2172 (addrbits == 32 && !(sok & BITS32)) ||
2173 (addrbits == 64 && !(sok & BITS64)))
2176 output->type = (ix & YMMREG & ~REG_EA)
2177 ? EA_YMMVSIB : EA_XMMVSIB;
2179 output->rex |= rexflags(it, ix, REX_X);
2180 output->rex |= rexflags(bt, bx, REX_B);
2182 index = it & 7; /* it is known to be != -1 */
2197 default: /* then what the smeg is it? */
2198 goto err; /* panic */
2206 if (base != REG_NUM_EBP && o == 0 &&
2207 seg == NO_SEG && !forw_ref &&
2208 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2210 else if (input->eaflags & EAF_BYTEOFFS ||
2211 (o >= -128 && o <= 127 &&
2212 seg == NO_SEG && !forw_ref &&
2213 !(input->eaflags & EAF_WORDOFFS)))
2219 output->sib_present = true;
2220 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2221 output->modrm = GEN_MODRM(mod, rfield, 4);
2222 output->sib = GEN_SIB(scale, index, base);
2223 } else if ((ix|bx) & (BITS32|BITS64)) {
2225 * it must be a 32/64-bit memory reference. Firstly we have
2226 * to check that all registers involved are type E/Rxx.
2228 opflags_t sok = BITS32 | BITS64;
2229 int32_t o = input->offset;
2232 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2240 goto err; /* Invalid register */
2241 if (~sok & bx & SIZE_MASK)
2242 goto err; /* Invalid size */
2247 * While we're here, ensure the user didn't specify
2250 if (input->disp_size == 16 || input->disp_size == 64)
2253 if (addrbits == 16 ||
2254 (addrbits == 32 && !(sok & BITS32)) ||
2255 (addrbits == 64 && !(sok & BITS64)))
2258 /* now reorganize base/index */
2259 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2260 ((hb == b && ht == EAH_NOTBASE) ||
2261 (hb == i && ht == EAH_MAKEBASE))) {
2262 /* swap if hints say so */
2263 t = bt, bt = it, it = t;
2264 x = bx, bx = ix, ix = x;
2266 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2267 bt = -1, bx = 0, s++;
2268 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2269 /* make single reg base, unless hint */
2270 bt = it, bx = ix, it = -1, ix = 0;
2272 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2273 s == 3 || s == 5 || s == 9) && bt == -1)
2274 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2275 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2276 (input->eaflags & EAF_TIMESTWO))
2277 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2278 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2279 if (s == 1 && it == REG_NUM_ESP) {
2280 /* swap ESP into base if scale is 1 */
2281 t = it, it = bt, bt = t;
2282 x = ix, ix = bx, bx = x;
2284 if (it == REG_NUM_ESP ||
2285 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2286 goto err; /* wrong, for various reasons */
2288 output->rex |= rexflags(it, ix, REX_X);
2289 output->rex |= rexflags(bt, bx, REX_B);
2291 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2300 if (rm != REG_NUM_EBP && o == 0 &&
2301 seg == NO_SEG && !forw_ref &&
2302 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2304 else if (input->eaflags & EAF_BYTEOFFS ||
2305 (o >= -128 && o <= 127 &&
2306 seg == NO_SEG && !forw_ref &&
2307 !(input->eaflags & EAF_WORDOFFS)))
2313 output->sib_present = false;
2314 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2315 output->modrm = GEN_MODRM(mod, rfield, rm);
2318 int mod, scale, index, base;
2338 default: /* then what the smeg is it? */
2339 goto err; /* panic */
2347 if (base != REG_NUM_EBP && o == 0 &&
2348 seg == NO_SEG && !forw_ref &&
2349 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2351 else if (input->eaflags & EAF_BYTEOFFS ||
2352 (o >= -128 && o <= 127 &&
2353 seg == NO_SEG && !forw_ref &&
2354 !(input->eaflags & EAF_WORDOFFS)))
2360 output->sib_present = true;
2361 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2362 output->modrm = GEN_MODRM(mod, rfield, 4);
2363 output->sib = GEN_SIB(scale, index, base);
2365 } else { /* it's 16-bit */
2367 int16_t o = input->offset;
2369 /* check for 64-bit long mode */
2373 /* check all registers are BX, BP, SI or DI */
2374 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2375 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2378 /* ensure the user didn't specify DWORD/QWORD */
2379 if (input->disp_size == 32 || input->disp_size == 64)
2382 if (s != 1 && i != -1)
2383 goto err; /* no can do, in 16-bit EA */
2384 if (b == -1 && i != -1) {
2389 if ((b == R_SI || b == R_DI) && i != -1) {
2394 /* have BX/BP as base, SI/DI index */
2396 goto err; /* shouldn't ever happen, in theory */
2397 if (i != -1 && b != -1 &&
2398 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2399 goto err; /* invalid combinations */
2400 if (b == -1) /* pure offset: handled above */
2401 goto err; /* so if it gets to here, panic! */
2405 switch (i * 256 + b) {
2406 case R_SI * 256 + R_BX:
2409 case R_DI * 256 + R_BX:
2412 case R_SI * 256 + R_BP:
2415 case R_DI * 256 + R_BP:
2433 if (rm == -1) /* can't happen, in theory */
2434 goto err; /* so panic if it does */
2436 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2437 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2439 else if (input->eaflags & EAF_BYTEOFFS ||
2440 (o >= -128 && o <= 127 && seg == NO_SEG &&
2441 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2446 output->sib_present = false; /* no SIB - it's 16-bit */
2447 output->bytes = mod; /* bytes of offset needed */
2448 output->modrm = GEN_MODRM(mod, rfield, rm);
2453 output->size = 1 + output->sib_present + output->bytes;
2454 return output->type;
2457 return output->type = EA_INVALID;
2460 static void add_asp(insn *ins, int addrbits)
2465 valid = (addrbits == 64) ? 64|32 : 32|16;
2467 switch (ins->prefixes[PPS_ASIZE]) {
2478 valid &= (addrbits == 32) ? 16 : 32;
2484 for (j = 0; j < ins->operands; j++) {
2485 if (is_class(MEMORY, ins->oprs[j].type)) {
2488 /* Verify as Register */
2489 if (!is_register(ins->oprs[j].indexreg))
2492 i = nasm_reg_flags[ins->oprs[j].indexreg];
2494 /* Verify as Register */
2495 if (!is_register(ins->oprs[j].basereg))
2498 b = nasm_reg_flags[ins->oprs[j].basereg];
2500 if (ins->oprs[j].scale == 0)
2504 int ds = ins->oprs[j].disp_size;
2505 if ((addrbits != 64 && ds > 8) ||
2506 (addrbits == 64 && ds == 16))
2526 if (valid & addrbits) {
2527 ins->addr_size = addrbits;
2528 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2529 /* Add an address size prefix */
2530 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2531 ins->addr_size = (addrbits == 32) ? 16 : 32;
2534 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2535 ins->addr_size = addrbits; /* Error recovery */
2538 defdisp = ins->addr_size == 16 ? 16 : 32;
2540 for (j = 0; j < ins->operands; j++) {
2541 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2542 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2544 * mem_offs sizes must match the address size; if not,
2545 * strip the MEM_OFFS bit and match only EA instructions
2547 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);