1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
82 * [l0] ll = 0 (.128, .lz)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
172 #include "compiler.h"
176 #include <inttypes.h>
180 #include "assemble.h"
187 * Matching errors. These should be sorted so that more specific
188 * errors come later in the sequence.
200 * Matching success; the conditional ones first
202 MOK_JUMP, /* Matching OK but needs jmp_match() */
203 MOK_GOOD /* Matching unconditionally OK */
207 enum ea_type type; /* what kind of EA is this? */
208 int sib_present; /* is a SIB byte necessary? */
209 int bytes; /* # of bytes of offset needed */
210 int size; /* lazy - this is sib+bytes+1 */
211 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
212 int8_t disp8; /* compressed displacement for EVEX */
215 #define GEN_SIB(scale, index, base) \
216 (((scale) << 6) | ((index) << 3) | ((base)))
218 #define GEN_MODRM(mod, reg, rm) \
219 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
221 static iflag_t cpu; /* cpu level received from nasm.c */
222 static efunc errfunc;
223 static struct ofmt *outfmt;
224 static ListGen *list;
226 static int64_t calcsize(int32_t, int64_t, int, insn *,
227 const struct itemplate *);
228 static void gencode(int32_t segment, int64_t offset, int bits,
229 insn * ins, const struct itemplate *temp,
231 static enum match_result find_match(const struct itemplate **tempp,
233 int32_t segment, int64_t offset, int bits);
234 static enum match_result matches(const struct itemplate *, insn *, int bits);
235 static opflags_t regflag(const operand *);
236 static int32_t regval(const operand *);
237 static int rexflags(int, opflags_t, int);
238 static int op_rexflags(const operand *, int);
239 static int op_evexflags(const operand *, int, uint8_t);
240 static void add_asp(insn *, int);
242 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
244 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
246 return ins->prefixes[pos] == prefix;
249 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
251 if (ins->prefixes[pos])
252 errfunc(ERR_NONFATAL, "invalid %s prefix",
253 prefix_name(ins->prefixes[pos]));
256 static const char *size_name(int size)
280 static void warn_overflow(int pass, int size)
282 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
283 "%s data exceeds bounds", size_name(size));
286 static void warn_overflow_const(int64_t data, int size)
288 if (overflow_general(data, size))
289 warn_overflow(ERR_PASS1, size);
292 static void warn_overflow_opd(const struct operand *o, int size)
294 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
295 if (overflow_general(o->offset, size))
296 warn_overflow(ERR_PASS2, size);
301 * This routine wrappers the real output format's output routine,
302 * in order to pass a copy of the data off to the listing file
303 * generator at the same time.
305 static void out(int64_t offset, int32_t segto, const void *data,
306 enum out_type type, uint64_t size,
307 int32_t segment, int32_t wrt)
309 static int32_t lineno = 0; /* static!!! */
310 static char *lnfname = NULL;
313 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
315 * This is a non-relocated address, and we're going to
316 * convert it into RAWDATA format.
321 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
325 WRITEADDR(q, *(int64_t *)data, size);
330 list->output(offset, data, type, size);
333 * this call to src_get determines when we call the
334 * debug-format-specific "linenum" function
335 * it updates lineno and lnfname to the current values
336 * returning 0 if "same as last time", -2 if lnfname
337 * changed, and the amount by which lineno changed,
338 * if it did. thus, these variables must be static
341 if (src_get(&lineno, &lnfname))
342 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
344 outfmt->output(segto, data, type, size, segment, wrt);
347 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
349 if (opx->segment != NO_SEG) {
350 uint64_t data = opx->offset;
351 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
353 uint8_t byte = opx->offset;
354 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
358 static bool jmp_match(int32_t segment, int64_t offset, int bits,
359 insn * ins, const struct itemplate *temp)
362 const uint8_t *code = temp->code;
366 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
370 if (optimizing < 0 && c == 0371)
373 isize = calcsize(segment, offset, bits, ins, temp);
375 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
376 /* Be optimistic in pass 1 */
379 if (ins->oprs[0].segment != segment)
382 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
383 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
385 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
386 /* jmp short (opcode eb) cannot be used with bnd prefix. */
387 ins->prefixes[PPS_REP] = P_none;
393 int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
394 insn * instruction, struct ofmt *output, efunc error,
397 const struct itemplate *temp;
402 int64_t start = offset;
403 int64_t wsize; /* size for DB etc. */
405 errfunc = error; /* to pass to other functions */
407 outfmt = output; /* likewise */
408 list = listgen; /* and again */
410 wsize = idata_bytes(instruction->opcode);
416 int32_t t = instruction->times;
419 "instruction->times < 0 (%ld) in assemble()", t);
421 while (t--) { /* repeat TIMES times */
422 list_for_each(e, instruction->eops) {
423 if (e->type == EOT_DB_NUMBER) {
425 errfunc(ERR_NONFATAL,
426 "integer supplied to a DT, DO or DY"
429 out(offset, segment, &e->offset,
430 OUT_ADDRESS, wsize, e->segment, e->wrt);
433 } else if (e->type == EOT_DB_STRING ||
434 e->type == EOT_DB_STRING_FREE) {
437 out(offset, segment, e->stringval,
438 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
439 align = e->stringlen % wsize;
442 align = wsize - align;
443 out(offset, segment, zero_buffer,
444 OUT_RAWDATA, align, NO_SEG, NO_SEG);
446 offset += e->stringlen + align;
449 if (t > 0 && t == instruction->times - 1) {
451 * Dummy call to list->output to give the offset to the
454 list->output(offset, NULL, OUT_RAWDATA, 0);
455 list->uplevel(LIST_TIMES);
458 if (instruction->times > 1)
459 list->downlevel(LIST_TIMES);
460 return offset - start;
463 if (instruction->opcode == I_INCBIN) {
464 const char *fname = instruction->eops->stringval;
467 fp = fopen(fname, "rb");
469 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
471 } else if (fseek(fp, 0L, SEEK_END) < 0) {
472 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
476 static char buf[4096];
477 size_t t = instruction->times;
482 if (instruction->eops->next) {
483 base = instruction->eops->next->offset;
485 if (instruction->eops->next->next &&
486 len > (size_t)instruction->eops->next->next->offset)
487 len = (size_t)instruction->eops->next->next->offset;
490 * Dummy call to list->output to give the offset to the
493 list->output(offset, NULL, OUT_RAWDATA, 0);
494 list->uplevel(LIST_INCBIN);
498 fseek(fp, base, SEEK_SET);
502 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
505 * This shouldn't happen unless the file
506 * actually changes while we are reading
510 "`incbin': unexpected EOF while"
511 " reading file `%s'", fname);
512 t = 0; /* Try to exit cleanly */
515 out(offset, segment, buf, OUT_RAWDATA, m,
520 list->downlevel(LIST_INCBIN);
521 if (instruction->times > 1) {
523 * Dummy call to list->output to give the offset to the
526 list->output(offset, NULL, OUT_RAWDATA, 0);
527 list->uplevel(LIST_TIMES);
528 list->downlevel(LIST_TIMES);
531 return instruction->times * len;
533 return 0; /* if we're here, there's an error */
536 /* Check to see if we need an address-size prefix */
537 add_asp(instruction, bits);
539 m = find_match(&temp, instruction, segment, offset, bits);
543 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
544 itimes = instruction->times;
545 if (insn_size < 0) /* shouldn't be, on pass two */
546 error(ERR_PANIC, "errors made it through from pass one");
549 for (j = 0; j < MAXPREFIX; j++) {
551 switch (instruction->prefixes[j]) {
572 error(ERR_WARNING | ERR_PASS2,
573 "cs segment base generated, but will be ignored in 64-bit mode");
579 error(ERR_WARNING | ERR_PASS2,
580 "ds segment base generated, but will be ignored in 64-bit mode");
586 error(ERR_WARNING | ERR_PASS2,
587 "es segment base generated, but will be ignored in 64-bit mode");
599 error(ERR_WARNING | ERR_PASS2,
600 "ss segment base generated, but will be ignored in 64-bit mode");
607 "segr6 and segr7 cannot be used as prefixes");
612 "16-bit addressing is not supported "
614 } else if (bits != 16)
624 "64-bit addressing is only supported "
651 error(ERR_PANIC, "invalid instruction prefix");
654 out(offset, segment, &c, OUT_RAWDATA, 1,
659 insn_end = offset + insn_size;
660 gencode(segment, offset, bits, instruction,
663 if (itimes > 0 && itimes == instruction->times - 1) {
665 * Dummy call to list->output to give the offset to the
668 list->output(offset, NULL, OUT_RAWDATA, 0);
669 list->uplevel(LIST_TIMES);
672 if (instruction->times > 1)
673 list->downlevel(LIST_TIMES);
674 return offset - start;
678 case MERR_OPSIZEMISSING:
679 error(ERR_NONFATAL, "operation size not specified");
681 case MERR_OPSIZEMISMATCH:
682 error(ERR_NONFATAL, "mismatch in operand sizes");
684 case MERR_BRNUMMISMATCH:
686 "mismatch in the number of broadcasting elements");
689 error(ERR_NONFATAL, "no instruction for this cpu level");
692 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
695 case MERR_ENCMISMATCH:
696 error(ERR_NONFATAL, "specific encoding scheme not available");
699 error(ERR_NONFATAL, "bnd prefix is not allowed");
703 "invalid combination of opcode and operands");
710 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
711 insn * instruction, efunc error)
713 const struct itemplate *temp;
716 errfunc = error; /* to pass to other functions */
719 if (instruction->opcode == I_none)
722 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
723 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
724 instruction->opcode == I_DT || instruction->opcode == I_DO ||
725 instruction->opcode == I_DY) {
727 int32_t isize, osize, wsize;
730 wsize = idata_bytes(instruction->opcode);
732 list_for_each(e, instruction->eops) {
736 if (e->type == EOT_DB_NUMBER) {
738 warn_overflow_const(e->offset, wsize);
739 } else if (e->type == EOT_DB_STRING ||
740 e->type == EOT_DB_STRING_FREE)
741 osize = e->stringlen;
743 align = (-osize) % wsize;
746 isize += osize + align;
748 return isize * instruction->times;
751 if (instruction->opcode == I_INCBIN) {
752 const char *fname = instruction->eops->stringval;
757 fp = fopen(fname, "rb");
759 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
761 else if (fseek(fp, 0L, SEEK_END) < 0)
762 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
766 if (instruction->eops->next) {
767 len -= instruction->eops->next->offset;
768 if (instruction->eops->next->next &&
769 len > (size_t)instruction->eops->next->next->offset) {
770 len = (size_t)instruction->eops->next->next->offset;
773 val = instruction->times * len;
780 /* Check to see if we need an address-size prefix */
781 add_asp(instruction, bits);
783 m = find_match(&temp, instruction, segment, offset, bits);
785 /* we've matched an instruction. */
789 isize = calcsize(segment, offset, bits, instruction, temp);
792 for (j = 0; j < MAXPREFIX; j++) {
793 switch (instruction->prefixes[j]) {
820 return isize * instruction->times;
822 return -1; /* didn't match any instruction */
826 static void bad_hle_warn(const insn * ins, uint8_t hleok)
828 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
829 enum whatwarn { w_none, w_lock, w_inval } ww;
830 static const enum whatwarn warn[2][4] =
832 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
833 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
837 n = (unsigned int)rep_pfx - P_XACQUIRE;
839 return; /* Not XACQUIRE/XRELEASE */
842 if (!is_class(MEMORY, ins->oprs[0].type))
843 ww = w_inval; /* HLE requires operand 0 to be memory */
850 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
851 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
852 "%s with this instruction requires lock",
853 prefix_name(rep_pfx));
858 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
859 "%s invalid with this instruction",
860 prefix_name(rep_pfx));
865 /* Common construct */
866 #define case3(x) case (x): case (x)+1: case (x)+2
867 #define case4(x) case3(x): case (x)+3
869 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
870 insn * ins, const struct itemplate *temp)
872 const uint8_t *codes = temp->code;
881 bool lockcheck = true;
882 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
884 ins->rex = 0; /* Ensure REX is reset */
885 eat = EA_SCALAR; /* Expect a scalar EA */
886 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
888 if (ins->prefixes[PPS_OSIZE] == P_O64)
891 (void)segment; /* Don't warn that this parameter is unused */
892 (void)offset; /* Don't warn that this parameter is unused */
896 op1 = (c & 3) + ((opex & 1) << 2);
897 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
898 opx = &ins->oprs[op1];
899 opex = 0; /* For the next iteration */
903 codes += c, length += c;
912 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
917 /* this is an index reg of MIB operand */
918 mib_index = opx->basereg;
931 if (opx->type & (BITS16 | BITS32 | BITS64))
932 length += (opx->type & BITS16) ? 2 : 4;
934 length += (bits == 16) ? 2 : 4;
942 length += ins->addr_size >> 3;
950 length += 8; /* MOV reg64/imm */
958 if (opx->type & (BITS16 | BITS32 | BITS64))
959 length += (opx->type & BITS16) ? 2 : 4;
961 length += (bits == 16) ? 2 : 4;
984 ins->vexreg = regval(opx);
985 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
986 ins->vex_cm = *codes++;
987 ins->vex_wlp = *codes++;
988 ins->evex_tuple = (*codes++ - 0300);
994 ins->vex_cm = *codes++;
995 ins->vex_wlp = *codes++;
996 ins->evex_tuple = (*codes++ - 0300);
1005 ins->vexreg = regval(opx);
1006 ins->vex_cm = *codes++;
1007 ins->vex_wlp = *codes++;
1013 ins->vex_cm = *codes++;
1014 ins->vex_wlp = *codes++;
1031 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1035 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1042 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1043 has_prefix(ins, PPS_ASIZE, P_A32))
1052 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1056 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1058 ins->prefixes[PPS_OSIZE] = P_O16;
1064 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1068 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1070 ins->prefixes[PPS_OSIZE] = P_O32;
1112 if (!ins->prefixes[PPS_REP])
1113 ins->prefixes[PPS_REP] = P_REP;
1117 if (!ins->prefixes[PPS_REP])
1118 ins->prefixes[PPS_REP] = P_REPNE;
1122 if (ins->oprs[0].segment != NO_SEG)
1123 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1124 " quantity of BSS space");
1126 length += ins->oprs[0].offset;
1130 if (!ins->prefixes[PPS_WAIT])
1131 ins->prefixes[PPS_WAIT] = P_WAIT;
1186 struct operand *opy = &ins->oprs[op2];
1187 struct operand *op_er_sae;
1189 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1192 /* pick rfield from operand b (opx) */
1193 rflags = regflag(opx);
1194 rfield = nasm_regvals[opx->basereg];
1200 /* EVEX.b1 : evex_brerop contains the operand position */
1201 op_er_sae = (ins->evex_brerop >= 0 ?
1202 &ins->oprs[ins->evex_brerop] : NULL);
1204 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1206 ins->evex_p[2] |= EVEX_P2B;
1207 if (op_er_sae->decoflags & ER) {
1208 /* set EVEX.RC (rounding control) */
1209 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1213 /* set EVEX.L'L (vector length) */
1214 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1215 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1216 if (opy->decoflags & BRDCAST_MASK) {
1218 ins->evex_p[2] |= EVEX_P2B;
1223 * if a separate form of MIB (ICC style) is used,
1224 * the index reg info is merged into mem operand
1226 if (mib_index != R_none) {
1227 opy->indexreg = mib_index;
1229 opy->hintbase = mib_index;
1230 opy->hinttype = EAH_NOTBASE;
1234 * only for mib operands, make a single reg index [reg*1].
1235 * gas uses this form to explicitly denote index register.
1237 if (itemp_has(temp, IF_MIB) &&
1238 (opy->indexreg == -1 && opy->hintbase == opy->basereg &&
1239 opy->hinttype == EAH_NOTBASE)) {
1240 opy->indexreg = opy->basereg;
1245 if (process_ea(opy, &ea_data, bits,
1246 rfield, rflags, ins) != eat) {
1247 errfunc(ERR_NONFATAL, "invalid effective address");
1250 ins->rex |= ea_data.rex;
1251 length += ea_data.size;
1257 errfunc(ERR_PANIC, "internal instruction table corrupt"
1258 ": instruction code \\%o (0x%02X) given", c, c);
1263 ins->rex &= rex_mask;
1265 if (ins->rex & REX_NH) {
1266 if (ins->rex & REX_H) {
1267 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1270 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1273 if (ins->rex & (REX_V | REX_EV)) {
1274 int bad32 = REX_R|REX_W|REX_X|REX_B;
1276 if (ins->rex & REX_H) {
1277 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1280 switch (ins->vex_wlp & 060) {
1294 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1295 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1297 } else if (!(ins->rex & REX_EV) &&
1298 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1299 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1302 if (ins->rex & REX_EV)
1304 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1308 } else if (ins->rex & REX_REAL) {
1309 if (ins->rex & REX_H) {
1310 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1312 } else if (bits == 64) {
1314 } else if ((ins->rex & REX_L) &&
1315 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1316 iflag_ffs(&cpu) >= IF_X86_64) {
1318 assert_no_prefix(ins, PPS_LOCK);
1319 lockcheck = false; /* Already errored, no need for warning */
1322 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1327 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1328 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1329 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1330 "instruction is not lockable");
1333 bad_hle_warn(ins, hleok);
1338 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1341 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1342 ins->rex = (ins->rex & REX_REAL) | REX_P;
1343 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1352 static void gencode(int32_t segment, int64_t offset, int bits,
1353 insn * ins, const struct itemplate *temp,
1361 struct operand *opx;
1362 const uint8_t *codes = temp->code;
1364 enum ea_type eat = EA_SCALAR;
1368 op1 = (c & 3) + ((opex & 1) << 2);
1369 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1370 opx = &ins->oprs[op1];
1371 opex = 0; /* For the next iteration */
1378 offset += emit_rex(ins, segment, offset, bits);
1379 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1391 offset += emit_rex(ins, segment, offset, bits);
1392 bytes[0] = *codes++ + (regval(opx) & 7);
1393 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1401 if (opx->offset < -256 || opx->offset > 255) {
1402 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1403 "byte value exceeds bounds");
1405 out_imm8(offset, segment, opx);
1410 if (opx->offset < 0 || opx->offset > 255)
1411 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1412 "unsigned byte value exceeds bounds");
1413 out_imm8(offset, segment, opx);
1418 warn_overflow_opd(opx, 2);
1420 out(offset, segment, &data, OUT_ADDRESS, 2,
1421 opx->segment, opx->wrt);
1426 if (opx->type & (BITS16 | BITS32))
1427 size = (opx->type & BITS16) ? 2 : 4;
1429 size = (bits == 16) ? 2 : 4;
1430 warn_overflow_opd(opx, size);
1432 out(offset, segment, &data, OUT_ADDRESS, size,
1433 opx->segment, opx->wrt);
1438 warn_overflow_opd(opx, 4);
1440 out(offset, segment, &data, OUT_ADDRESS, 4,
1441 opx->segment, opx->wrt);
1447 size = ins->addr_size >> 3;
1448 warn_overflow_opd(opx, size);
1449 out(offset, segment, &data, OUT_ADDRESS, size,
1450 opx->segment, opx->wrt);
1455 if (opx->segment != segment) {
1457 out(offset, segment, &data,
1458 OUT_REL1ADR, insn_end - offset,
1459 opx->segment, opx->wrt);
1461 data = opx->offset - insn_end;
1462 if (data > 127 || data < -128)
1463 errfunc(ERR_NONFATAL, "short jump is out of range");
1464 out(offset, segment, &data,
1465 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1471 data = (int64_t)opx->offset;
1472 out(offset, segment, &data, OUT_ADDRESS, 8,
1473 opx->segment, opx->wrt);
1478 if (opx->segment != segment) {
1480 out(offset, segment, &data,
1481 OUT_REL2ADR, insn_end - offset,
1482 opx->segment, opx->wrt);
1484 data = opx->offset - insn_end;
1485 out(offset, segment, &data,
1486 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1492 if (opx->type & (BITS16 | BITS32 | BITS64))
1493 size = (opx->type & BITS16) ? 2 : 4;
1495 size = (bits == 16) ? 2 : 4;
1496 if (opx->segment != segment) {
1498 out(offset, segment, &data,
1499 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1500 insn_end - offset, opx->segment, opx->wrt);
1502 data = opx->offset - insn_end;
1503 out(offset, segment, &data,
1504 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1510 if (opx->segment != segment) {
1512 out(offset, segment, &data,
1513 OUT_REL4ADR, insn_end - offset,
1514 opx->segment, opx->wrt);
1516 data = opx->offset - insn_end;
1517 out(offset, segment, &data,
1518 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1524 if (opx->segment == NO_SEG)
1525 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1528 out(offset, segment, &data, OUT_ADDRESS, 2,
1529 outfmt->segbase(1 + opx->segment),
1536 opx = &ins->oprs[c >> 3];
1537 bytes[0] = nasm_regvals[opx->basereg] << 4;
1538 opx = &ins->oprs[c & 7];
1539 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1540 errfunc(ERR_NONFATAL,
1541 "non-absolute expression not permitted as argument %d",
1544 if (opx->offset & ~15) {
1545 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1546 "four-bit argument exceeds bounds");
1548 bytes[0] |= opx->offset & 15;
1550 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1556 opx = &ins->oprs[c >> 4];
1557 bytes[0] = nasm_regvals[opx->basereg] << 4;
1559 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1564 bytes[0] = nasm_regvals[opx->basereg] << 4;
1565 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1571 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1572 (int32_t)data != (int64_t)data) {
1573 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1574 "signed dword immediate exceeds bounds");
1576 out(offset, segment, &data, OUT_ADDRESS, 4,
1577 opx->segment, opx->wrt);
1584 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1585 EVEX_P2Z | EVEX_P2AAA, 2);
1586 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1588 /* EVEX.X can be set by either REX or EVEX for different reasons */
1589 bytes[1] = ((((ins->rex & 7) << 5) |
1590 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1592 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1593 ((~ins->vexreg & 15) << 3) |
1594 (1 << 2) | (ins->vex_wlp & 3);
1595 bytes[3] = ins->evex_p[2];
1596 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1603 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1604 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1605 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1606 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1607 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1608 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1612 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1613 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1614 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1629 if (ins->rex & REX_W)
1631 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1633 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1638 um = (uint64_t)2 << (s-1);
1641 if (uv > 127 && uv < (uint64_t)-128 &&
1642 (uv < um-128 || uv > um-1)) {
1643 /* If this wasn't explicitly byte-sized, warn as though we
1644 * had fallen through to the imm16/32/64 case.
1646 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1647 "%s value exceeds bounds",
1648 (opx->type & BITS8) ? "signed byte" :
1653 if (opx->segment != NO_SEG) {
1655 out(offset, segment, &data, OUT_ADDRESS, 1,
1656 opx->segment, opx->wrt);
1659 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1670 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1672 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1679 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1681 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1716 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1717 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1726 *bytes = c - 0332 + 0xF2;
1727 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1732 if (ins->rex & REX_R) {
1734 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1737 ins->rex &= ~(REX_L|REX_R);
1748 if (ins->oprs[0].segment != NO_SEG)
1749 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1751 int64_t size = ins->oprs[0].offset;
1753 out(offset, segment, NULL,
1754 OUT_RESERVE, size, NO_SEG, NO_SEG);
1767 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1777 *bytes = c - 0366 + 0x66;
1778 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1786 *bytes = bits == 16 ? 3 : 5;
1787 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1821 struct operand *opy = &ins->oprs[op2];
1824 /* pick rfield from operand b (opx) */
1825 rflags = regflag(opx);
1826 rfield = nasm_regvals[opx->basereg];
1828 /* rfield is constant */
1833 if (process_ea(opy, &ea_data, bits,
1834 rfield, rflags, ins) != eat)
1835 errfunc(ERR_NONFATAL, "invalid effective address");
1838 *p++ = ea_data.modrm;
1839 if (ea_data.sib_present)
1843 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1846 * Make sure the address gets the right offset in case
1847 * the line breaks in the .lst file (BR 1197827)
1852 switch (ea_data.bytes) {
1859 /* use compressed displacement, if available */
1860 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1863 if (opy->segment == segment) {
1865 if (overflow_signed(data, ea_data.bytes))
1866 warn_overflow(ERR_PASS2, ea_data.bytes);
1867 out(offset, segment, &data, OUT_ADDRESS,
1868 ea_data.bytes, NO_SEG, NO_SEG);
1870 /* overflow check in output/linker? */
1871 out(offset, segment, &data, OUT_REL4ADR,
1872 insn_end - offset, opy->segment, opy->wrt);
1875 if (overflow_general(data, ins->addr_size >> 3) ||
1876 signed_bits(data, ins->addr_size) !=
1877 signed_bits(data, ea_data.bytes * 8))
1878 warn_overflow(ERR_PASS2, ea_data.bytes);
1880 out(offset, segment, &data, OUT_ADDRESS,
1881 ea_data.bytes, opy->segment, opy->wrt);
1887 "Invalid amount of bytes (%d) for offset?!",
1896 errfunc(ERR_PANIC, "internal instruction table corrupt"
1897 ": instruction code \\%o (0x%02X) given", c, c);
1903 static opflags_t regflag(const operand * o)
1905 if (!is_register(o->basereg))
1906 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1907 return nasm_reg_flags[o->basereg];
1910 static int32_t regval(const operand * o)
1912 if (!is_register(o->basereg))
1913 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1914 return nasm_regvals[o->basereg];
1917 static int op_rexflags(const operand * o, int mask)
1922 if (!is_register(o->basereg))
1923 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1925 flags = nasm_reg_flags[o->basereg];
1926 val = nasm_regvals[o->basereg];
1928 return rexflags(val, flags, mask);
1931 static int rexflags(int val, opflags_t flags, int mask)
1935 if (val >= 0 && (val & 8))
1936 rex |= REX_B|REX_X|REX_R;
1939 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1941 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1947 static int evexflags(int val, decoflags_t deco,
1948 int mask, uint8_t byte)
1954 if (val >= 0 && (val & 16))
1955 evex |= (EVEX_P0RP | EVEX_P0X);
1958 if (val >= 0 && (val & 16))
1962 if (deco & OPMASK_MASK)
1963 evex |= deco & EVEX_P2AAA;
1969 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1973 if (!is_register(o->basereg))
1974 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1976 val = nasm_regvals[o->basereg];
1978 return evexflags(val, o->decoflags, mask, byte);
1981 static enum match_result find_match(const struct itemplate **tempp,
1983 int32_t segment, int64_t offset, int bits)
1985 const struct itemplate *temp;
1986 enum match_result m, merr;
1987 opflags_t xsizeflags[MAX_OPERANDS];
1988 bool opsizemissing = false;
1989 int8_t broadcast = instruction->evex_brerop;
1992 /* broadcasting uses a different data element size */
1993 for (i = 0; i < instruction->operands; i++)
1995 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
1997 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1999 merr = MERR_INVALOP;
2001 for (temp = nasm_instructions[instruction->opcode];
2002 temp->opcode != I_none; temp++) {
2003 m = matches(temp, instruction, bits);
2004 if (m == MOK_JUMP) {
2005 if (jmp_match(segment, offset, bits, instruction, temp))
2009 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2011 * Missing operand size and a candidate for fuzzy matching...
2013 for (i = 0; i < temp->operands; i++)
2015 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2017 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2018 opsizemissing = true;
2022 if (merr == MOK_GOOD)
2026 /* No match, but see if we can get a fuzzy operand size match... */
2030 for (i = 0; i < instruction->operands; i++) {
2032 * We ignore extrinsic operand sizes on registers, so we should
2033 * never try to fuzzy-match on them. This also resolves the case
2034 * when we have e.g. "xmmrm128" in two different positions.
2036 if (is_class(REGISTER, instruction->oprs[i].type))
2039 /* This tests if xsizeflags[i] has more than one bit set */
2040 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2041 goto done; /* No luck */
2043 if (i == broadcast) {
2044 instruction->oprs[i].decoflags |= xsizeflags[i];
2045 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2048 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2052 /* Try matching again... */
2053 for (temp = nasm_instructions[instruction->opcode];
2054 temp->opcode != I_none; temp++) {
2055 m = matches(temp, instruction, bits);
2056 if (m == MOK_JUMP) {
2057 if (jmp_match(segment, offset, bits, instruction, temp))
2064 if (merr == MOK_GOOD)
2073 static enum match_result matches(const struct itemplate *itemp,
2074 insn *instruction, int bits)
2076 opflags_t size[MAX_OPERANDS], asize;
2077 bool opsizemissing = false;
2083 if (itemp->opcode != instruction->opcode)
2084 return MERR_INVALOP;
2087 * Count the operands
2089 if (itemp->operands != instruction->operands)
2090 return MERR_INVALOP;
2095 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2096 return MERR_INVALOP;
2101 if (instruction->prefixes[PPS_EVEX] && !itemp_has(itemp, IF_EVEX)) {
2102 return MERR_ENCMISMATCH;
2106 * Check that no spurious colons or TOs are present
2108 for (i = 0; i < itemp->operands; i++)
2109 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2110 return MERR_INVALOP;
2113 * Process size flags
2115 switch (itemp_smask(itemp)) {
2116 case IF_GENBIT(IF_SB):
2119 case IF_GENBIT(IF_SW):
2122 case IF_GENBIT(IF_SD):
2125 case IF_GENBIT(IF_SQ):
2128 case IF_GENBIT(IF_SO):
2131 case IF_GENBIT(IF_SY):
2134 case IF_GENBIT(IF_SZ):
2137 case IF_GENBIT(IF_SIZE):
2158 if (itemp_armask(itemp)) {
2159 /* S- flags only apply to a specific operand */
2160 i = itemp_arg(itemp);
2161 memset(size, 0, sizeof size);
2164 /* S- flags apply to all operands */
2165 for (i = 0; i < MAX_OPERANDS; i++)
2170 * Check that the operand flags all match up,
2171 * it's a bit tricky so lets be verbose:
2173 * 1) Find out the size of operand. If instruction
2174 * doesn't have one specified -- we're trying to
2175 * guess it either from template (IF_S* flag) or
2178 * 2) If template operand do not match the instruction OR
2179 * template has an operand size specified AND this size differ
2180 * from which instruction has (perhaps we got it from code bits)
2182 * a) Check that only size of instruction and operand is differ
2183 * other characteristics do match
2184 * b) Perhaps it's a register specified in instruction so
2185 * for such a case we just mark that operand as "size
2186 * missing" and this will turn on fuzzy operand size
2187 * logic facility (handled by a caller)
2189 for (i = 0; i < itemp->operands; i++) {
2190 opflags_t type = instruction->oprs[i].type;
2191 decoflags_t deco = instruction->oprs[i].decoflags;
2192 bool is_broadcast = deco & BRDCAST_MASK;
2193 uint8_t brcast_num = 0;
2194 opflags_t template_opsize, insn_opsize;
2196 if (!(type & SIZE_MASK))
2199 insn_opsize = type & SIZE_MASK;
2200 if (!is_broadcast) {
2201 template_opsize = itemp->opd[i] & SIZE_MASK;
2203 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2205 * when broadcasting, the element size depends on
2206 * the instruction type. decorator flag should match.
2210 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2211 /* calculate the proper number : {1to<brcast_num>} */
2212 brcast_num = (itemp->opd[i] & SIZE_MASK) / BITS128 *
2213 BITS64 / template_opsize * 2;
2215 template_opsize = 0;
2219 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2220 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2221 return MERR_INVALOP;
2222 } else if (template_opsize) {
2223 if (template_opsize != insn_opsize) {
2225 return MERR_INVALOP;
2226 } else if (!is_class(REGISTER, type)) {
2228 * Note: we don't honor extrinsic operand sizes for registers,
2229 * so "missing operand size" for a register should be
2230 * considered a wildcard match rather than an error.
2232 opsizemissing = true;
2234 } else if (is_broadcast &&
2236 (8U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2238 * broadcasting opsize matches but the number of repeated memory
2239 * element does not match.
2240 * if 64b double precision float is broadcasted to zmm (512b),
2241 * broadcasting decorator must be {1to8}.
2243 return MERR_BRNUMMISMATCH;
2249 return MERR_OPSIZEMISSING;
2252 * Check operand sizes
2254 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2255 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2256 for (i = 0; i < oprs; i++) {
2257 asize = itemp->opd[i] & SIZE_MASK;
2259 for (i = 0; i < oprs; i++)
2265 oprs = itemp->operands;
2268 for (i = 0; i < itemp->operands; i++) {
2269 if (!(itemp->opd[i] & SIZE_MASK) &&
2270 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2271 return MERR_OPSIZEMISMATCH;
2275 * Check template is okay at the set cpu level
2277 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2281 * Verify the appropriate long mode flag.
2283 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2284 return MERR_BADMODE;
2287 * If we have a HLE prefix, look for the NOHLE flag
2289 if (itemp_has(itemp, IF_NOHLE) &&
2290 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2291 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2295 * Check if special handling needed for Jumps
2297 if ((itemp->code[0] & ~1) == 0370)
2301 * Check if BND prefix is allowed
2303 if (!itemp_has(itemp, IF_BND) &&
2304 has_prefix(instruction, PPS_REP, P_BND))
2311 * Check if ModR/M.mod should/can be 01.
2312 * - EAF_BYTEOFFS is set
2313 * - offset can fit in a byte when EVEX is not used
2314 * - offset can be compressed when EVEX is used
2316 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2317 (o >= -128 && o <= 127 && \
2318 seg == NO_SEG && !forw_ref && \
2319 !(input->eaflags & EAF_WORDOFFS) && \
2320 !(ins->rex & REX_EV)) || \
2321 (ins->rex & REX_EV && \
2322 is_disp8n(input, ins, &output->disp8)))
2324 static enum ea_type process_ea(operand *input, ea *output, int bits,
2325 int rfield, opflags_t rflags, insn *ins)
2327 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2328 int addrbits = ins->addr_size;
2330 output->type = EA_SCALAR;
2331 output->rip = false;
2334 /* REX flags for the rfield operand */
2335 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2336 /* EVEX.R' flag for the REG operand */
2337 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2339 if (is_class(REGISTER, input->type)) {
2341 * It's a direct register.
2343 if (!is_register(input->basereg))
2346 if (!is_reg_class(REG_EA, input->basereg))
2349 /* broadcasting is not available with a direct register operand. */
2350 if (input->decoflags & BRDCAST_MASK) {
2351 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2355 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2356 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2357 output->sib_present = false; /* no SIB necessary */
2358 output->bytes = 0; /* no offset necessary either */
2359 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2362 * It's a memory reference.
2365 /* Embedded rounding or SAE is not available with a mem ref operand. */
2366 if (input->decoflags & (ER | SAE)) {
2367 nasm_error(ERR_NONFATAL,
2368 "Embedded rounding is available only with reg-reg op.");
2372 if (input->basereg == -1 &&
2373 (input->indexreg == -1 || input->scale == 0)) {
2375 * It's a pure offset.
2377 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2378 input->segment == NO_SEG) {
2379 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2380 input->type &= ~IP_REL;
2381 input->type |= MEMORY;
2384 if (input->eaflags & EAF_BYTEOFFS ||
2385 (input->eaflags & EAF_WORDOFFS &&
2386 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2387 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2390 if (bits == 64 && (~input->type & IP_REL)) {
2391 output->sib_present = true;
2392 output->sib = GEN_SIB(0, 4, 5);
2394 output->modrm = GEN_MODRM(0, rfield, 4);
2395 output->rip = false;
2397 output->sib_present = false;
2398 output->bytes = (addrbits != 16 ? 4 : 2);
2399 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2400 output->rip = bits == 64;
2404 * It's an indirection.
2406 int i = input->indexreg, b = input->basereg, s = input->scale;
2407 int32_t seg = input->segment;
2408 int hb = input->hintbase, ht = input->hinttype;
2409 int t, it, bt; /* register numbers */
2410 opflags_t x, ix, bx; /* register flags */
2413 i = -1; /* make this easy, at least */
2415 if (is_register(i)) {
2416 it = nasm_regvals[i];
2417 ix = nasm_reg_flags[i];
2423 if (is_register(b)) {
2424 bt = nasm_regvals[b];
2425 bx = nasm_reg_flags[b];
2431 /* if either one are a vector register... */
2432 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2433 opflags_t sok = BITS32 | BITS64;
2434 int32_t o = input->offset;
2435 int mod, scale, index, base;
2438 * For a vector SIB, one has to be a vector and the other,
2439 * if present, a GPR. The vector must be the index operand.
2441 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2447 t = bt, bt = it, it = t;
2448 x = bx, bx = ix, ix = x;
2454 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2461 * While we're here, ensure the user didn't specify
2464 if (input->disp_size == 16 || input->disp_size == 64)
2467 if (addrbits == 16 ||
2468 (addrbits == 32 && !(sok & BITS32)) ||
2469 (addrbits == 64 && !(sok & BITS64)))
2472 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2473 : ((ix & YMMREG & ~REG_EA)
2474 ? EA_YMMVSIB : EA_XMMVSIB));
2476 output->rex |= rexflags(it, ix, REX_X);
2477 output->rex |= rexflags(bt, bx, REX_B);
2478 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2480 index = it & 7; /* it is known to be != -1 */
2495 default: /* then what the smeg is it? */
2496 goto err; /* panic */
2504 if (base != REG_NUM_EBP && o == 0 &&
2505 seg == NO_SEG && !forw_ref &&
2506 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2508 else if (IS_MOD_01())
2514 output->sib_present = true;
2515 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2516 output->modrm = GEN_MODRM(mod, rfield, 4);
2517 output->sib = GEN_SIB(scale, index, base);
2518 } else if ((ix|bx) & (BITS32|BITS64)) {
2520 * it must be a 32/64-bit memory reference. Firstly we have
2521 * to check that all registers involved are type E/Rxx.
2523 opflags_t sok = BITS32 | BITS64;
2524 int32_t o = input->offset;
2527 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2535 goto err; /* Invalid register */
2536 if (~sok & bx & SIZE_MASK)
2537 goto err; /* Invalid size */
2542 * While we're here, ensure the user didn't specify
2545 if (input->disp_size == 16 || input->disp_size == 64)
2548 if (addrbits == 16 ||
2549 (addrbits == 32 && !(sok & BITS32)) ||
2550 (addrbits == 64 && !(sok & BITS64)))
2553 /* now reorganize base/index */
2554 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2555 ((hb == b && ht == EAH_NOTBASE) ||
2556 (hb == i && ht == EAH_MAKEBASE))) {
2557 /* swap if hints say so */
2558 t = bt, bt = it, it = t;
2559 x = bx, bx = ix, ix = x;
2561 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2562 bt = -1, bx = 0, s++;
2563 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2564 /* make single reg base, unless hint */
2565 bt = it, bx = ix, it = -1, ix = 0;
2567 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2568 s == 3 || s == 5 || s == 9) && bt == -1)
2569 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2570 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2571 (input->eaflags & EAF_TIMESTWO))
2572 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2573 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2574 if (s == 1 && it == REG_NUM_ESP) {
2575 /* swap ESP into base if scale is 1 */
2576 t = it, it = bt, bt = t;
2577 x = ix, ix = bx, bx = x;
2579 if (it == REG_NUM_ESP ||
2580 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2581 goto err; /* wrong, for various reasons */
2583 output->rex |= rexflags(it, ix, REX_X);
2584 output->rex |= rexflags(bt, bx, REX_B);
2586 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2595 if (rm != REG_NUM_EBP && o == 0 &&
2596 seg == NO_SEG && !forw_ref &&
2597 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2599 else if (IS_MOD_01())
2605 output->sib_present = false;
2606 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2607 output->modrm = GEN_MODRM(mod, rfield, rm);
2610 int mod, scale, index, base;
2630 default: /* then what the smeg is it? */
2631 goto err; /* panic */
2639 if (base != REG_NUM_EBP && o == 0 &&
2640 seg == NO_SEG && !forw_ref &&
2641 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2643 else if (IS_MOD_01())
2649 output->sib_present = true;
2650 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2651 output->modrm = GEN_MODRM(mod, rfield, 4);
2652 output->sib = GEN_SIB(scale, index, base);
2654 } else { /* it's 16-bit */
2656 int16_t o = input->offset;
2658 /* check for 64-bit long mode */
2662 /* check all registers are BX, BP, SI or DI */
2663 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2664 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2667 /* ensure the user didn't specify DWORD/QWORD */
2668 if (input->disp_size == 32 || input->disp_size == 64)
2671 if (s != 1 && i != -1)
2672 goto err; /* no can do, in 16-bit EA */
2673 if (b == -1 && i != -1) {
2678 if ((b == R_SI || b == R_DI) && i != -1) {
2683 /* have BX/BP as base, SI/DI index */
2685 goto err; /* shouldn't ever happen, in theory */
2686 if (i != -1 && b != -1 &&
2687 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2688 goto err; /* invalid combinations */
2689 if (b == -1) /* pure offset: handled above */
2690 goto err; /* so if it gets to here, panic! */
2694 switch (i * 256 + b) {
2695 case R_SI * 256 + R_BX:
2698 case R_DI * 256 + R_BX:
2701 case R_SI * 256 + R_BP:
2704 case R_DI * 256 + R_BP:
2722 if (rm == -1) /* can't happen, in theory */
2723 goto err; /* so panic if it does */
2725 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2726 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2728 else if (IS_MOD_01())
2733 output->sib_present = false; /* no SIB - it's 16-bit */
2734 output->bytes = mod; /* bytes of offset needed */
2735 output->modrm = GEN_MODRM(mod, rfield, rm);
2740 output->size = 1 + output->sib_present + output->bytes;
2741 return output->type;
2744 return output->type = EA_INVALID;
2747 static void add_asp(insn *ins, int addrbits)
2752 valid = (addrbits == 64) ? 64|32 : 32|16;
2754 switch (ins->prefixes[PPS_ASIZE]) {
2765 valid &= (addrbits == 32) ? 16 : 32;
2771 for (j = 0; j < ins->operands; j++) {
2772 if (is_class(MEMORY, ins->oprs[j].type)) {
2775 /* Verify as Register */
2776 if (!is_register(ins->oprs[j].indexreg))
2779 i = nasm_reg_flags[ins->oprs[j].indexreg];
2781 /* Verify as Register */
2782 if (!is_register(ins->oprs[j].basereg))
2785 b = nasm_reg_flags[ins->oprs[j].basereg];
2787 if (ins->oprs[j].scale == 0)
2791 int ds = ins->oprs[j].disp_size;
2792 if ((addrbits != 64 && ds > 8) ||
2793 (addrbits == 64 && ds == 16))
2813 if (valid & addrbits) {
2814 ins->addr_size = addrbits;
2815 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2816 /* Add an address size prefix */
2817 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2818 ins->addr_size = (addrbits == 32) ? 16 : 32;
2821 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2822 ins->addr_size = addrbits; /* Error recovery */
2825 defdisp = ins->addr_size == 16 ? 16 : 32;
2827 for (j = 0; j < ins->operands; j++) {
2828 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2829 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2831 * mem_offs sizes must match the address size; if not,
2832 * strip the MEM_OFFS bit and match only EA instructions
2834 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);