1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \20..\23 - a byte immediate operand, from operand 0..3
46 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
47 * \30..\33 - a word immediate operand, from operand 0..3
48 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
49 * assembly mode or the operand-size override on the operand
50 * \40..\43 - a long immediate operand, from operand 0..3
51 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
52 * depending on the address size of the instruction.
53 * \50..\53 - a byte relative operand, from operand 0..3
54 * \54..\57 - a qword immediate operand, from operand 0..3
55 * \60..\63 - a word relative operand, from operand 0..3
56 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
57 * assembly mode or the operand-size override on the operand
58 * \70..\73 - a long relative operand, from operand 0..3
59 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
60 * \1ab - a ModRM, calculated on EA in operand a, with the spare
61 * field the register value of operand b.
62 * \172\ab - the register number from operand a in bits 7..4, with
63 * the 4-bit immediate from operand b in bits 3..0.
64 * \173\xab - the register number from operand a in bits 7..4, with
65 * the value b in bits 3..0.
66 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
67 * an arbitrary value in bits 3..0 (assembled as zero.)
68 * \2ab - a ModRM, calculated on EA in operand a, with the spare
69 * field equal to digit b.
71 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
72 * V field taken from operand 0..3.
73 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
74 * V field set to 1111b.
75 * EVEX prefixes are followed by the sequence:
76 * \cm\wlp\tup where cm is:
78 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
81 * [l0] ll = 0 (.128, .lz)
84 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
86 * [w0] ww = 0 for W = 0
87 * [w1] ww = 1 for W = 1
88 * [wig] ww = 2 for W don't care (always assembled as 0)
89 * [ww] ww = 3 for W used as REX.W
91 * [p0] pp = 0 for no prefix
92 * [60] pp = 1 for legacy prefix 60
96 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
97 * (compressed displacement encoding)
99 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
100 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
101 * V field taken from operand 0..3.
102 * \270 - this instruction uses VEX/XOP rather than REX, with the
103 * V field set to 1111b.
105 * VEX/XOP prefixes are followed by the sequence:
106 * \tmm\wlp where mm is the M field; and wlp is:
108 * [l0] ll = 0 for L = 0 (.128, .lz)
109 * [l1] ll = 1 for L = 1 (.256)
110 * [lig] ll = 2 for L don't care (always assembled as 0)
112 * [w0] ww = 0 for W = 0
113 * [w1 ] ww = 1 for W = 1
114 * [wig] ww = 2 for W don't care (always assembled as 0)
115 * [ww] ww = 3 for W used as REX.W
117 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
119 * \271 - instruction takes XRELEASE (F3) with or without lock
120 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
121 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
122 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
123 * to the operand size (if o16/o32/o64 present) or the bit size
124 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
125 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
126 * \312 - (disassembler only) invalid with non-default address size.
127 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
128 * \314 - (disassembler only) invalid with REX.B
129 * \315 - (disassembler only) invalid with REX.X
130 * \316 - (disassembler only) invalid with REX.R
131 * \317 - (disassembler only) invalid with REX.W
132 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
133 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
134 * \322 - indicates that this instruction is only valid when the
135 * operand size is the default (instruction to disassembler,
136 * generates no code in the assembler)
137 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
138 * \324 - indicates 64-bit operand size requiring REX prefix.
139 * \325 - instruction which always uses spl/bpl/sil/dil
140 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
141 disassembler only; for SSE instructions.
142 * \330 - a literal byte follows in the code stream, to be added
143 * to the condition code value of the instruction.
144 * \331 - instruction not valid with REP prefix. Hint for
145 * disassembler only; for SSE instructions.
146 * \332 - REP prefix (0xF2 byte) used as opcode extension.
147 * \333 - REP prefix (0xF3 byte) used as opcode extension.
148 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
149 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
150 * \336 - force a REP(E) prefix (0xF3) even if not specified.
151 * \337 - force a REPNE prefix (0xF2) even if not specified.
152 * \336-\337 are still listed as prefixes in the disassembler.
153 * \340 - reserve <operand 0> bytes of uninitialized storage.
154 * Operand 0 had better be a segmentless constant.
155 * \341 - this instruction needs a WAIT "prefix"
156 * \360 - no SSE prefix (== \364\331)
157 * \361 - 66 SSE prefix (== \366\331)
158 * \364 - operand-size prefix (0x66) not permitted
159 * \365 - address-size prefix (0x67) not permitted
160 * \366 - operand-size prefix (0x66) used as opcode extension
161 * \367 - address-size prefix (0x67) used as opcode extension
162 * \370,\371 - match only if operand 0 meets byte jump criteria.
163 * 370 is used for Jcc, 371 is used for JMP.
164 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
165 * used for conditional jump over longer jump
166 * \374 - this instruction takes an XMM VSIB memory EA
167 * \375 - this instruction takes an YMM VSIB memory EA
168 * \376 - this instruction takes an ZMM VSIB memory EA
171 #include "compiler.h"
175 #include <inttypes.h>
179 #include "assemble.h"
185 * Matching errors. These should be sorted so that more specific
186 * errors come later in the sequence.
196 * Matching success; the conditional ones first
198 MOK_JUMP, /* Matching OK but needs jmp_match() */
199 MOK_GOOD /* Matching unconditionally OK */
203 enum ea_type type; /* what kind of EA is this? */
204 int sib_present; /* is a SIB byte necessary? */
205 int bytes; /* # of bytes of offset needed */
206 int size; /* lazy - this is sib+bytes+1 */
207 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
208 int8_t disp8; /* compressed displacement for EVEX */
211 #define GEN_SIB(scale, index, base) \
212 (((scale) << 6) | ((index) << 3) | ((base)))
214 #define GEN_MODRM(mod, reg, rm) \
215 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
217 static iflags_t cpu; /* cpu level received from nasm.c */
218 static efunc errfunc;
219 static struct ofmt *outfmt;
220 static ListGen *list;
222 static int64_t calcsize(int32_t, int64_t, int, insn *,
223 const struct itemplate *);
224 static void gencode(int32_t segment, int64_t offset, int bits,
225 insn * ins, const struct itemplate *temp,
227 static enum match_result find_match(const struct itemplate **tempp,
229 int32_t segment, int64_t offset, int bits);
230 static enum match_result matches(const struct itemplate *, insn *, int bits);
231 static opflags_t regflag(const operand *);
232 static int32_t regval(const operand *);
233 static int rexflags(int, opflags_t, int);
234 static int op_rexflags(const operand *, int);
235 static int op_evexflags(const operand *, int, uint8_t);
236 static void add_asp(insn *, int);
238 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
240 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
242 return ins->prefixes[pos] == prefix;
245 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
247 if (ins->prefixes[pos])
248 errfunc(ERR_NONFATAL, "invalid %s prefix",
249 prefix_name(ins->prefixes[pos]));
252 static const char *size_name(int size)
276 static void warn_overflow(int pass, int size)
278 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
279 "%s data exceeds bounds", size_name(size));
282 static void warn_overflow_const(int64_t data, int size)
284 if (overflow_general(data, size))
285 warn_overflow(ERR_PASS1, size);
288 static void warn_overflow_opd(const struct operand *o, int size)
290 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
291 if (overflow_general(o->offset, size))
292 warn_overflow(ERR_PASS2, size);
297 * This routine wrappers the real output format's output routine,
298 * in order to pass a copy of the data off to the listing file
299 * generator at the same time.
301 static void out(int64_t offset, int32_t segto, const void *data,
302 enum out_type type, uint64_t size,
303 int32_t segment, int32_t wrt)
305 static int32_t lineno = 0; /* static!!! */
306 static char *lnfname = NULL;
309 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
311 * This is a non-relocated address, and we're going to
312 * convert it into RAWDATA format.
317 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
321 WRITEADDR(q, *(int64_t *)data, size);
326 list->output(offset, data, type, size);
329 * this call to src_get determines when we call the
330 * debug-format-specific "linenum" function
331 * it updates lineno and lnfname to the current values
332 * returning 0 if "same as last time", -2 if lnfname
333 * changed, and the amount by which lineno changed,
334 * if it did. thus, these variables must be static
337 if (src_get(&lineno, &lnfname))
338 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
340 outfmt->output(segto, data, type, size, segment, wrt);
343 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
345 if (opx->segment != NO_SEG) {
346 uint64_t data = opx->offset;
347 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
349 uint8_t byte = opx->offset;
350 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
354 static bool jmp_match(int32_t segment, int64_t offset, int bits,
355 insn * ins, const struct itemplate *temp)
358 const uint8_t *code = temp->code;
361 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
365 if (optimizing < 0 && c == 0371)
368 isize = calcsize(segment, offset, bits, ins, temp);
370 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
371 /* Be optimistic in pass 1 */
374 if (ins->oprs[0].segment != segment)
377 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
378 return (isize >= -128 && isize <= 127); /* is it byte size? */
381 int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp,
382 insn * instruction, struct ofmt *output, efunc error,
385 const struct itemplate *temp;
390 int64_t start = offset;
391 int64_t wsize; /* size for DB etc. */
393 errfunc = error; /* to pass to other functions */
395 outfmt = output; /* likewise */
396 list = listgen; /* and again */
398 wsize = idata_bytes(instruction->opcode);
404 int32_t t = instruction->times;
407 "instruction->times < 0 (%ld) in assemble()", t);
409 while (t--) { /* repeat TIMES times */
410 list_for_each(e, instruction->eops) {
411 if (e->type == EOT_DB_NUMBER) {
413 errfunc(ERR_NONFATAL,
414 "integer supplied to a DT, DO or DY"
417 out(offset, segment, &e->offset,
418 OUT_ADDRESS, wsize, e->segment, e->wrt);
421 } else if (e->type == EOT_DB_STRING ||
422 e->type == EOT_DB_STRING_FREE) {
425 out(offset, segment, e->stringval,
426 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
427 align = e->stringlen % wsize;
430 align = wsize - align;
431 out(offset, segment, zero_buffer,
432 OUT_RAWDATA, align, NO_SEG, NO_SEG);
434 offset += e->stringlen + align;
437 if (t > 0 && t == instruction->times - 1) {
439 * Dummy call to list->output to give the offset to the
442 list->output(offset, NULL, OUT_RAWDATA, 0);
443 list->uplevel(LIST_TIMES);
446 if (instruction->times > 1)
447 list->downlevel(LIST_TIMES);
448 return offset - start;
451 if (instruction->opcode == I_INCBIN) {
452 const char *fname = instruction->eops->stringval;
455 fp = fopen(fname, "rb");
457 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
459 } else if (fseek(fp, 0L, SEEK_END) < 0) {
460 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
464 static char buf[4096];
465 size_t t = instruction->times;
470 if (instruction->eops->next) {
471 base = instruction->eops->next->offset;
473 if (instruction->eops->next->next &&
474 len > (size_t)instruction->eops->next->next->offset)
475 len = (size_t)instruction->eops->next->next->offset;
478 * Dummy call to list->output to give the offset to the
481 list->output(offset, NULL, OUT_RAWDATA, 0);
482 list->uplevel(LIST_INCBIN);
486 fseek(fp, base, SEEK_SET);
490 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
493 * This shouldn't happen unless the file
494 * actually changes while we are reading
498 "`incbin': unexpected EOF while"
499 " reading file `%s'", fname);
500 t = 0; /* Try to exit cleanly */
503 out(offset, segment, buf, OUT_RAWDATA, m,
508 list->downlevel(LIST_INCBIN);
509 if (instruction->times > 1) {
511 * Dummy call to list->output to give the offset to the
514 list->output(offset, NULL, OUT_RAWDATA, 0);
515 list->uplevel(LIST_TIMES);
516 list->downlevel(LIST_TIMES);
519 return instruction->times * len;
521 return 0; /* if we're here, there's an error */
524 /* Check to see if we need an address-size prefix */
525 add_asp(instruction, bits);
527 m = find_match(&temp, instruction, segment, offset, bits);
531 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
532 itimes = instruction->times;
533 if (insn_size < 0) /* shouldn't be, on pass two */
534 error(ERR_PANIC, "errors made it through from pass one");
537 for (j = 0; j < MAXPREFIX; j++) {
539 switch (instruction->prefixes[j]) {
559 error(ERR_WARNING | ERR_PASS2,
560 "cs segment base generated, but will be ignored in 64-bit mode");
566 error(ERR_WARNING | ERR_PASS2,
567 "ds segment base generated, but will be ignored in 64-bit mode");
573 error(ERR_WARNING | ERR_PASS2,
574 "es segment base generated, but will be ignored in 64-bit mode");
586 error(ERR_WARNING | ERR_PASS2,
587 "ss segment base generated, but will be ignored in 64-bit mode");
594 "segr6 and segr7 cannot be used as prefixes");
599 "16-bit addressing is not supported "
601 } else if (bits != 16)
611 "64-bit addressing is only supported "
635 error(ERR_PANIC, "invalid instruction prefix");
638 out(offset, segment, &c, OUT_RAWDATA, 1,
643 insn_end = offset + insn_size;
644 gencode(segment, offset, bits, instruction,
647 if (itimes > 0 && itimes == instruction->times - 1) {
649 * Dummy call to list->output to give the offset to the
652 list->output(offset, NULL, OUT_RAWDATA, 0);
653 list->uplevel(LIST_TIMES);
656 if (instruction->times > 1)
657 list->downlevel(LIST_TIMES);
658 return offset - start;
662 case MERR_OPSIZEMISSING:
663 error(ERR_NONFATAL, "operation size not specified");
665 case MERR_OPSIZEMISMATCH:
666 error(ERR_NONFATAL, "mismatch in operand sizes");
669 error(ERR_NONFATAL, "no instruction for this cpu level");
672 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
677 "invalid combination of opcode and operands");
684 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp,
685 insn * instruction, efunc error)
687 const struct itemplate *temp;
690 errfunc = error; /* to pass to other functions */
693 if (instruction->opcode == I_none)
696 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
697 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
698 instruction->opcode == I_DT || instruction->opcode == I_DO ||
699 instruction->opcode == I_DY) {
701 int32_t isize, osize, wsize;
704 wsize = idata_bytes(instruction->opcode);
706 list_for_each(e, instruction->eops) {
710 if (e->type == EOT_DB_NUMBER) {
712 warn_overflow_const(e->offset, wsize);
713 } else if (e->type == EOT_DB_STRING ||
714 e->type == EOT_DB_STRING_FREE)
715 osize = e->stringlen;
717 align = (-osize) % wsize;
720 isize += osize + align;
722 return isize * instruction->times;
725 if (instruction->opcode == I_INCBIN) {
726 const char *fname = instruction->eops->stringval;
731 fp = fopen(fname, "rb");
733 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
735 else if (fseek(fp, 0L, SEEK_END) < 0)
736 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
740 if (instruction->eops->next) {
741 len -= instruction->eops->next->offset;
742 if (instruction->eops->next->next &&
743 len > (size_t)instruction->eops->next->next->offset) {
744 len = (size_t)instruction->eops->next->next->offset;
747 val = instruction->times * len;
754 /* Check to see if we need an address-size prefix */
755 add_asp(instruction, bits);
757 m = find_match(&temp, instruction, segment, offset, bits);
759 /* we've matched an instruction. */
763 isize = calcsize(segment, offset, bits, instruction, temp);
766 for (j = 0; j < MAXPREFIX; j++) {
767 switch (instruction->prefixes[j]) {
793 return isize * instruction->times;
795 return -1; /* didn't match any instruction */
799 static void bad_hle_warn(const insn * ins, uint8_t hleok)
801 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
802 enum whatwarn { w_none, w_lock, w_inval } ww;
803 static const enum whatwarn warn[2][4] =
805 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
806 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
810 n = (unsigned int)rep_pfx - P_XACQUIRE;
812 return; /* Not XACQUIRE/XRELEASE */
815 if (!is_class(MEMORY, ins->oprs[0].type))
816 ww = w_inval; /* HLE requires operand 0 to be memory */
823 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
824 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
825 "%s with this instruction requires lock",
826 prefix_name(rep_pfx));
831 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
832 "%s invalid with this instruction",
833 prefix_name(rep_pfx));
838 /* Common construct */
839 #define case3(x) case (x): case (x)+1: case (x)+2
840 #define case4(x) case3(x): case (x)+3
842 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
843 insn * ins, const struct itemplate *temp)
845 const uint8_t *codes = temp->code;
854 bool lockcheck = true;
856 ins->rex = 0; /* Ensure REX is reset */
857 eat = EA_SCALAR; /* Expect a scalar EA */
858 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
860 if (ins->prefixes[PPS_OSIZE] == P_O64)
863 (void)segment; /* Don't warn that this parameter is unused */
864 (void)offset; /* Don't warn that this parameter is unused */
868 op1 = (c & 3) + ((opex & 1) << 2);
869 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
870 opx = &ins->oprs[op1];
871 opex = 0; /* For the next iteration */
875 codes += c, length += c;
884 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
898 if (opx->type & (BITS16 | BITS32 | BITS64))
899 length += (opx->type & BITS16) ? 2 : 4;
901 length += (bits == 16) ? 2 : 4;
909 length += ins->addr_size >> 3;
917 length += 8; /* MOV reg64/imm */
925 if (opx->type & (BITS16 | BITS32 | BITS64))
926 length += (opx->type & BITS16) ? 2 : 4;
928 length += (bits == 16) ? 2 : 4;
951 ins->vexreg = regval(opx);
952 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
953 ins->vex_cm = *codes++;
954 ins->vex_wlp = *codes++;
955 ins->evex_tuple = (*codes++ - 0300);
961 ins->vex_cm = *codes++;
962 ins->vex_wlp = *codes++;
963 ins->evex_tuple = (*codes++ - 0300);
972 ins->vexreg = regval(opx);
973 ins->vex_cm = *codes++;
974 ins->vex_wlp = *codes++;
980 ins->vex_cm = *codes++;
981 ins->vex_wlp = *codes++;
998 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1002 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1009 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1010 has_prefix(ins, PPS_ASIZE, P_A32))
1019 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1023 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1025 ins->prefixes[PPS_OSIZE] = P_O16;
1031 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1035 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1037 ins->prefixes[PPS_OSIZE] = P_O32;
1079 if (!ins->prefixes[PPS_REP])
1080 ins->prefixes[PPS_REP] = P_REP;
1084 if (!ins->prefixes[PPS_REP])
1085 ins->prefixes[PPS_REP] = P_REPNE;
1089 if (ins->oprs[0].segment != NO_SEG)
1090 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1091 " quantity of BSS space");
1093 length += ins->oprs[0].offset;
1097 if (!ins->prefixes[PPS_WAIT])
1098 ins->prefixes[PPS_WAIT] = P_WAIT;
1152 struct operand *opy = &ins->oprs[op2];
1153 struct operand *oplast;
1155 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1158 /* pick rfield from operand b (opx) */
1159 rflags = regflag(opx);
1160 rfield = nasm_regvals[opx->basereg];
1161 /* find the last SIMD operand where ER decorator resides */
1162 oplast = &ins->oprs[op1 > op2 ? op1 : op2];
1163 while (oplast && is_class(REG_CLASS_GPR, oplast->type))
1171 if (oplast->decoflags & ER) {
1172 /* set EVEX.RC (rounding control) and b */
1173 ins->evex_p[2] |= (((ins->evex_rm - BRC_RN) << 5) & EVEX_P2LL) |
1176 /* set EVEX.L'L (vector length) */
1177 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1178 if ((oplast->decoflags & SAE) ||
1179 (opy->decoflags & BRDCAST_MASK)) {
1181 ins->evex_p[2] |= EVEX_P2B;
1185 if (process_ea(opy, &ea_data, bits,
1186 rfield, rflags, ins) != eat) {
1187 errfunc(ERR_NONFATAL, "invalid effective address");
1190 ins->rex |= ea_data.rex;
1191 length += ea_data.size;
1197 errfunc(ERR_PANIC, "internal instruction table corrupt"
1198 ": instruction code \\%o (0x%02X) given", c, c);
1203 ins->rex &= rex_mask;
1205 if (ins->rex & REX_NH) {
1206 if (ins->rex & REX_H) {
1207 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1210 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1213 if (ins->rex & (REX_V | REX_EV)) {
1214 int bad32 = REX_R|REX_W|REX_X|REX_B;
1216 if (ins->rex & REX_H) {
1217 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1220 switch (ins->vex_wlp & 060) {
1234 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1235 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1237 } else if (!(ins->rex & REX_EV) &&
1238 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1239 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1242 if (ins->rex & REX_EV)
1244 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1248 } else if (ins->rex & REX_REAL) {
1249 if (ins->rex & REX_H) {
1250 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1252 } else if (bits == 64) {
1254 } else if ((ins->rex & REX_L) &&
1255 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1258 assert_no_prefix(ins, PPS_LOCK);
1259 lockcheck = false; /* Already errored, no need for warning */
1262 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1267 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1268 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1269 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1270 "instruction is not lockable");
1273 bad_hle_warn(ins, hleok);
1278 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1281 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1282 ins->rex = (ins->rex & REX_REAL) | REX_P;
1283 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1292 static void gencode(int32_t segment, int64_t offset, int bits,
1293 insn * ins, const struct itemplate *temp,
1301 struct operand *opx;
1302 const uint8_t *codes = temp->code;
1304 enum ea_type eat = EA_SCALAR;
1308 op1 = (c & 3) + ((opex & 1) << 2);
1309 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1310 opx = &ins->oprs[op1];
1311 opex = 0; /* For the next iteration */
1318 offset += emit_rex(ins, segment, offset, bits);
1319 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1331 offset += emit_rex(ins, segment, offset, bits);
1332 bytes[0] = *codes++ + (regval(opx) & 7);
1333 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1338 if (opx->offset < -256 || opx->offset > 255) {
1339 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1340 "byte value exceeds bounds");
1342 out_imm8(offset, segment, opx);
1347 if (opx->offset < 0 || opx->offset > 255)
1348 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1349 "unsigned byte value exceeds bounds");
1350 out_imm8(offset, segment, opx);
1355 warn_overflow_opd(opx, 2);
1357 out(offset, segment, &data, OUT_ADDRESS, 2,
1358 opx->segment, opx->wrt);
1363 if (opx->type & (BITS16 | BITS32))
1364 size = (opx->type & BITS16) ? 2 : 4;
1366 size = (bits == 16) ? 2 : 4;
1367 warn_overflow_opd(opx, size);
1369 out(offset, segment, &data, OUT_ADDRESS, size,
1370 opx->segment, opx->wrt);
1375 warn_overflow_opd(opx, 4);
1377 out(offset, segment, &data, OUT_ADDRESS, 4,
1378 opx->segment, opx->wrt);
1384 size = ins->addr_size >> 3;
1385 warn_overflow_opd(opx, size);
1386 out(offset, segment, &data, OUT_ADDRESS, size,
1387 opx->segment, opx->wrt);
1392 if (opx->segment != segment) {
1394 out(offset, segment, &data,
1395 OUT_REL1ADR, insn_end - offset,
1396 opx->segment, opx->wrt);
1398 data = opx->offset - insn_end;
1399 if (data > 127 || data < -128)
1400 errfunc(ERR_NONFATAL, "short jump is out of range");
1401 out(offset, segment, &data,
1402 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1408 data = (int64_t)opx->offset;
1409 out(offset, segment, &data, OUT_ADDRESS, 8,
1410 opx->segment, opx->wrt);
1415 if (opx->segment != segment) {
1417 out(offset, segment, &data,
1418 OUT_REL2ADR, insn_end - offset,
1419 opx->segment, opx->wrt);
1421 data = opx->offset - insn_end;
1422 out(offset, segment, &data,
1423 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1429 if (opx->type & (BITS16 | BITS32 | BITS64))
1430 size = (opx->type & BITS16) ? 2 : 4;
1432 size = (bits == 16) ? 2 : 4;
1433 if (opx->segment != segment) {
1435 out(offset, segment, &data,
1436 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1437 insn_end - offset, opx->segment, opx->wrt);
1439 data = opx->offset - insn_end;
1440 out(offset, segment, &data,
1441 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1447 if (opx->segment != segment) {
1449 out(offset, segment, &data,
1450 OUT_REL4ADR, insn_end - offset,
1451 opx->segment, opx->wrt);
1453 data = opx->offset - insn_end;
1454 out(offset, segment, &data,
1455 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1461 if (opx->segment == NO_SEG)
1462 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1465 out(offset, segment, &data, OUT_ADDRESS, 2,
1466 outfmt->segbase(1 + opx->segment),
1473 opx = &ins->oprs[c >> 3];
1474 bytes[0] = nasm_regvals[opx->basereg] << 4;
1475 opx = &ins->oprs[c & 7];
1476 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1477 errfunc(ERR_NONFATAL,
1478 "non-absolute expression not permitted as argument %d",
1481 if (opx->offset & ~15) {
1482 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1483 "four-bit argument exceeds bounds");
1485 bytes[0] |= opx->offset & 15;
1487 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1493 opx = &ins->oprs[c >> 4];
1494 bytes[0] = nasm_regvals[opx->basereg] << 4;
1496 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1501 bytes[0] = nasm_regvals[opx->basereg] << 4;
1502 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1508 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1509 (int32_t)data != (int64_t)data) {
1510 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1511 "signed dword immediate exceeds bounds");
1513 out(offset, segment, &data, OUT_ADDRESS, 4,
1514 opx->segment, opx->wrt);
1521 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1522 EVEX_P2Z | EVEX_P2AAA, 2);
1523 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1525 /* EVEX.X can be set by either REX or EVEX for different reasons */
1526 bytes[1] = (~(((ins->rex & 7) << 5) |
1527 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) & 0xf0) |
1529 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1530 ((~ins->vexreg & 15) << 3) |
1531 (1 << 2) | (ins->vex_wlp & 3);
1532 bytes[3] = ins->evex_p[2];
1533 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1540 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1541 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1542 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1543 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1544 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1545 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1549 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1550 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1551 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1566 if (ins->rex & REX_W)
1568 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1570 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1575 um = (uint64_t)2 << (s-1);
1578 if (uv > 127 && uv < (uint64_t)-128 &&
1579 (uv < um-128 || uv > um-1)) {
1580 /* If this wasn't explicitly byte-sized, warn as though we
1581 * had fallen through to the imm16/32/64 case.
1583 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1584 "%s value exceeds bounds",
1585 (opx->type & BITS8) ? "signed byte" :
1590 if (opx->segment != NO_SEG) {
1592 out(offset, segment, &data, OUT_ADDRESS, 1,
1593 opx->segment, opx->wrt);
1596 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1607 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1609 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1616 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1618 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1653 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1654 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1663 *bytes = c - 0332 + 0xF2;
1664 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1669 if (ins->rex & REX_R) {
1671 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1674 ins->rex &= ~(REX_L|REX_R);
1685 if (ins->oprs[0].segment != NO_SEG)
1686 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1688 int64_t size = ins->oprs[0].offset;
1690 out(offset, segment, NULL,
1691 OUT_RESERVE, size, NO_SEG, NO_SEG);
1704 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1714 *bytes = c - 0366 + 0x66;
1715 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1724 *bytes = bits == 16 ? 3 : 5;
1725 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1759 struct operand *opy = &ins->oprs[op2];
1762 /* pick rfield from operand b (opx) */
1763 rflags = regflag(opx);
1764 rfield = nasm_regvals[opx->basereg];
1766 /* rfield is constant */
1771 if (process_ea(opy, &ea_data, bits,
1772 rfield, rflags, ins) != eat)
1773 errfunc(ERR_NONFATAL, "invalid effective address");
1776 *p++ = ea_data.modrm;
1777 if (ea_data.sib_present)
1781 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1784 * Make sure the address gets the right offset in case
1785 * the line breaks in the .lst file (BR 1197827)
1790 switch (ea_data.bytes) {
1797 /* use compressed displacement, if available */
1798 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1801 if (opy->segment == segment) {
1803 if (overflow_signed(data, ea_data.bytes))
1804 warn_overflow(ERR_PASS2, ea_data.bytes);
1805 out(offset, segment, &data, OUT_ADDRESS,
1806 ea_data.bytes, NO_SEG, NO_SEG);
1808 /* overflow check in output/linker? */
1809 out(offset, segment, &data, OUT_REL4ADR,
1810 insn_end - offset, opy->segment, opy->wrt);
1813 if (overflow_general(data, ins->addr_size >> 3) ||
1814 signed_bits(data, ins->addr_size) !=
1815 signed_bits(data, ea_data.bytes * 8))
1816 warn_overflow(ERR_PASS2, ea_data.bytes);
1818 out(offset, segment, &data, OUT_ADDRESS,
1819 ea_data.bytes, opy->segment, opy->wrt);
1825 "Invalid amount of bytes (%d) for offset?!",
1834 errfunc(ERR_PANIC, "internal instruction table corrupt"
1835 ": instruction code \\%o (0x%02X) given", c, c);
1841 static opflags_t regflag(const operand * o)
1843 if (!is_register(o->basereg))
1844 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1845 return nasm_reg_flags[o->basereg];
1848 static int32_t regval(const operand * o)
1850 if (!is_register(o->basereg))
1851 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1852 return nasm_regvals[o->basereg];
1855 static int op_rexflags(const operand * o, int mask)
1860 if (!is_register(o->basereg))
1861 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1863 flags = nasm_reg_flags[o->basereg];
1864 val = nasm_regvals[o->basereg];
1866 return rexflags(val, flags, mask);
1869 static int rexflags(int val, opflags_t flags, int mask)
1874 rex |= REX_B|REX_X|REX_R;
1877 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1879 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1885 static int evexflags(int val, decoflags_t deco,
1886 int mask, uint8_t byte)
1893 evex |= (EVEX_P0RP | EVEX_P0X);
1900 if (deco & OPMASK_MASK)
1901 evex |= deco & EVEX_P2AAA;
1907 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1911 if (!is_register(o->basereg))
1912 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1914 val = nasm_regvals[o->basereg];
1916 return evexflags(val, o->decoflags, mask, byte);
1919 static enum match_result find_match(const struct itemplate **tempp,
1921 int32_t segment, int64_t offset, int bits)
1923 const struct itemplate *temp;
1924 enum match_result m, merr;
1925 opflags_t xsizeflags[MAX_OPERANDS];
1926 bool opsizemissing = false;
1927 int8_t broadcast = -1;
1930 /* find the position of broadcasting operand */
1931 for (i = 0; i < instruction->operands; i++)
1932 if (instruction->oprs[i].decoflags & BRDCAST_MASK) {
1937 /* broadcasting uses a different data element size */
1938 for (i = 0; i < instruction->operands; i++)
1940 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
1942 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1944 merr = MERR_INVALOP;
1946 for (temp = nasm_instructions[instruction->opcode];
1947 temp->opcode != I_none; temp++) {
1948 m = matches(temp, instruction, bits);
1949 if (m == MOK_JUMP) {
1950 if (jmp_match(segment, offset, bits, instruction, temp))
1954 } else if (m == MERR_OPSIZEMISSING &&
1955 (temp->flags & IF_SMASK) != IF_SX) {
1957 * Missing operand size and a candidate for fuzzy matching...
1959 for (i = 0; i < temp->operands; i++)
1961 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
1963 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1964 opsizemissing = true;
1968 if (merr == MOK_GOOD)
1972 /* No match, but see if we can get a fuzzy operand size match... */
1976 for (i = 0; i < instruction->operands; i++) {
1978 * We ignore extrinsic operand sizes on registers, so we should
1979 * never try to fuzzy-match on them. This also resolves the case
1980 * when we have e.g. "xmmrm128" in two different positions.
1982 if (is_class(REGISTER, instruction->oprs[i].type))
1985 /* This tests if xsizeflags[i] has more than one bit set */
1986 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1987 goto done; /* No luck */
1990 instruction->oprs[i].decoflags |= xsizeflags[i];
1992 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1995 /* Try matching again... */
1996 for (temp = nasm_instructions[instruction->opcode];
1997 temp->opcode != I_none; temp++) {
1998 m = matches(temp, instruction, bits);
1999 if (m == MOK_JUMP) {
2000 if (jmp_match(segment, offset, bits, instruction, temp))
2007 if (merr == MOK_GOOD)
2016 static enum match_result matches(const struct itemplate *itemp,
2017 insn *instruction, int bits)
2019 opflags_t size[MAX_OPERANDS], asize;
2020 bool opsizemissing = false;
2026 if (itemp->opcode != instruction->opcode)
2027 return MERR_INVALOP;
2030 * Count the operands
2032 if (itemp->operands != instruction->operands)
2033 return MERR_INVALOP;
2038 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2039 return MERR_INVALOP;
2042 * Check that no spurious colons or TOs are present
2044 for (i = 0; i < itemp->operands; i++)
2045 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2046 return MERR_INVALOP;
2049 * Process size flags
2051 switch (itemp->flags & IF_SMASK) {
2094 if (itemp->flags & IF_ARMASK) {
2095 /* S- flags only apply to a specific operand */
2096 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2097 memset(size, 0, sizeof size);
2100 /* S- flags apply to all operands */
2101 for (i = 0; i < MAX_OPERANDS; i++)
2106 * Check that the operand flags all match up,
2107 * it's a bit tricky so lets be verbose:
2109 * 1) Find out the size of operand. If instruction
2110 * doesn't have one specified -- we're trying to
2111 * guess it either from template (IF_S* flag) or
2114 * 2) If template operand do not match the instruction OR
2115 * template has an operand size specified AND this size differ
2116 * from which instruction has (perhaps we got it from code bits)
2118 * a) Check that only size of instruction and operand is differ
2119 * other characteristics do match
2120 * b) Perhaps it's a register specified in instruction so
2121 * for such a case we just mark that operand as "size
2122 * missing" and this will turn on fuzzy operand size
2123 * logic facility (handled by a caller)
2125 for (i = 0; i < itemp->operands; i++) {
2126 opflags_t type = instruction->oprs[i].type;
2127 decoflags_t deco = instruction->oprs[i].decoflags;
2128 if (!(type & SIZE_MASK))
2131 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2132 (itemp->deco[i] & deco) != deco) {
2133 return MERR_INVALOP;
2134 } else if ((itemp->opd[i] & SIZE_MASK) &&
2135 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2136 if (type & SIZE_MASK) {
2138 * when broadcasting, the element size depends on
2139 * the instruction type. decorator flag should match.
2141 #define MATCH_BRSZ(bits) (((type & SIZE_MASK) == BITS##bits) && \
2142 ((itemp->deco[i] & BRSIZE_MASK) == BR_BITS##bits))
2143 if (!((deco & BRDCAST_MASK) &&
2144 (MATCH_BRSZ(32) || MATCH_BRSZ(64)))) {
2145 return MERR_INVALOP;
2147 } else if (!is_class(REGISTER, type)) {
2149 * Note: we don't honor extrinsic operand sizes for registers,
2150 * so "missing operand size" for a register should be
2151 * considered a wildcard match rather than an error.
2153 opsizemissing = true;
2155 } else if (instruction->oprs[i].basereg >= 16 &&
2156 (itemp->flags & IF_INSMASK) != IF_AVX512) {
2157 return MERR_ENCMISMATCH;
2162 return MERR_OPSIZEMISSING;
2165 * Check operand sizes
2167 if (itemp->flags & (IF_SM | IF_SM2)) {
2168 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2169 for (i = 0; i < oprs; i++) {
2170 asize = itemp->opd[i] & SIZE_MASK;
2172 for (i = 0; i < oprs; i++)
2178 oprs = itemp->operands;
2181 for (i = 0; i < itemp->operands; i++) {
2182 if (!(itemp->opd[i] & SIZE_MASK) &&
2183 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2184 return MERR_OPSIZEMISMATCH;
2188 * Check template is okay at the set cpu level
2190 if (((itemp->flags & IF_PLEVEL) > cpu))
2194 * Verify the appropriate long mode flag.
2196 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2197 return MERR_BADMODE;
2200 * If we have a HLE prefix, look for the NOHLE flag
2202 if ((itemp->flags & IF_NOHLE) &&
2203 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2204 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2208 * Check if special handling needed for Jumps
2210 if ((itemp->code[0] & ~1) == 0370)
2217 * Check if offset is a multiple of N with corresponding tuple type
2218 * if Disp8*N is available, compressed displacement is stored in compdisp
2220 static bool is_disp8n(operand *input, insn *ins, int8_t *compdisp)
2222 const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}},
2223 {{16, 32, 64}, {8, 8, 8}}};
2224 const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}};
2225 const uint8_t dup_n[VLMAX] = {8, 32, 64};
2227 bool evex_b = input->decoflags & BRDCAST_MASK;
2228 enum ttypes tuple = ins->evex_tuple;
2229 /* vex_wlp composed as [wwllpp] */
2230 enum vectlens vectlen = (ins->vex_wlp & 0x0c) >> 2;
2231 /* wig(=2) is treated as w0(=0) */
2232 bool evex_w = (ins->vex_wlp & 0x10) >> 4;
2233 int32_t off = input->offset;
2239 n = fv_n[evex_w][evex_b][vectlen];
2242 n = hv_n[evex_b][vectlen];
2246 /* 16, 32, 64 for VL 128, 256, 512 respectively*/
2247 n = 1 << (vectlen + 4);
2249 case T1S8: /* N = 1 */
2250 case T1S16: /* N = 2 */
2251 n = tuple - T1S8 + 1;
2254 /* N = 4 for 32bit, 8 for 64bit */
2259 /* N = 4 for 32bit, 8 for 64bit */
2260 n = (tuple == T1F32 ? 4 : 8);
2265 if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1))
2268 n = 1 << (tuple - T2 + evex_w + 3);
2273 n = 1 << (OVM - tuple + vectlen + 1);
2286 if (n && !(off & (n - 1))) {
2288 /* if it fits in Disp8 */
2289 if (disp8 >= -128 && disp8 <= 127) {
2300 * Check if ModR/M.mod should/can be 01.
2301 * - EAF_BYTEOFFS is set
2302 * - offset can fit in a byte when EVEX is not used
2303 * - offset can be compressed when EVEX is used
2305 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2306 (o >= -128 && o <= 127 && \
2307 seg == NO_SEG && !forw_ref && \
2308 !(input->eaflags & EAF_WORDOFFS) && \
2309 !(ins->rex & REX_EV)) || \
2310 (ins->rex & REX_EV && \
2311 is_disp8n(input, ins, &output->disp8)))
2313 static enum ea_type process_ea(operand *input, ea *output, int bits,
2314 int rfield, opflags_t rflags, insn *ins)
2316 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2317 int addrbits = ins->addr_size;
2319 output->type = EA_SCALAR;
2320 output->rip = false;
2322 /* REX flags for the rfield operand */
2323 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2324 /* EVEX.R' flag for the REG operand */
2325 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2327 if (is_class(REGISTER, input->type)) {
2329 * It's a direct register.
2331 if (!is_register(input->basereg))
2334 if (!is_reg_class(REG_EA, input->basereg))
2337 /* broadcasting is not available with a direct register operand. */
2338 if (input->decoflags & BRDCAST_MASK) {
2339 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2343 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2344 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2345 output->sib_present = false; /* no SIB necessary */
2346 output->bytes = 0; /* no offset necessary either */
2347 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2350 * It's a memory reference.
2353 /* Embedded rounding or SAE is not available with a mem ref operand. */
2354 if (input->decoflags & (ER | SAE)) {
2355 nasm_error(ERR_NONFATAL,
2356 "Embedded rounding is available only with reg-reg op.");
2360 if (input->basereg == -1 &&
2361 (input->indexreg == -1 || input->scale == 0)) {
2363 * It's a pure offset.
2365 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2366 input->segment == NO_SEG) {
2367 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2368 input->type &= ~IP_REL;
2369 input->type |= MEMORY;
2372 if (input->eaflags & EAF_BYTEOFFS ||
2373 (input->eaflags & EAF_WORDOFFS &&
2374 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2375 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2378 if (bits == 64 && (~input->type & IP_REL)) {
2379 output->sib_present = true;
2380 output->sib = GEN_SIB(0, 4, 5);
2382 output->modrm = GEN_MODRM(0, rfield, 4);
2383 output->rip = false;
2385 output->sib_present = false;
2386 output->bytes = (addrbits != 16 ? 4 : 2);
2387 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2388 output->rip = bits == 64;
2392 * It's an indirection.
2394 int i = input->indexreg, b = input->basereg, s = input->scale;
2395 int32_t seg = input->segment;
2396 int hb = input->hintbase, ht = input->hinttype;
2397 int t, it, bt; /* register numbers */
2398 opflags_t x, ix, bx; /* register flags */
2401 i = -1; /* make this easy, at least */
2403 if (is_register(i)) {
2404 it = nasm_regvals[i];
2405 ix = nasm_reg_flags[i];
2411 if (is_register(b)) {
2412 bt = nasm_regvals[b];
2413 bx = nasm_reg_flags[b];
2419 /* if either one are a vector register... */
2420 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2421 opflags_t sok = BITS32 | BITS64;
2422 int32_t o = input->offset;
2423 int mod, scale, index, base;
2426 * For a vector SIB, one has to be a vector and the other,
2427 * if present, a GPR. The vector must be the index operand.
2429 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2435 t = bt, bt = it, it = t;
2436 x = bx, bx = ix, ix = x;
2442 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2449 * While we're here, ensure the user didn't specify
2452 if (input->disp_size == 16 || input->disp_size == 64)
2455 if (addrbits == 16 ||
2456 (addrbits == 32 && !(sok & BITS32)) ||
2457 (addrbits == 64 && !(sok & BITS64)))
2460 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2461 : ((ix & YMMREG & ~REG_EA)
2462 ? EA_YMMVSIB : EA_XMMVSIB));
2464 output->rex |= rexflags(it, ix, REX_X);
2465 output->rex |= rexflags(bt, bx, REX_B);
2466 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2468 index = it & 7; /* it is known to be != -1 */
2483 default: /* then what the smeg is it? */
2484 goto err; /* panic */
2492 if (base != REG_NUM_EBP && o == 0 &&
2493 seg == NO_SEG && !forw_ref &&
2494 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2496 else if (IS_MOD_01())
2502 output->sib_present = true;
2503 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2504 output->modrm = GEN_MODRM(mod, rfield, 4);
2505 output->sib = GEN_SIB(scale, index, base);
2506 } else if ((ix|bx) & (BITS32|BITS64)) {
2508 * it must be a 32/64-bit memory reference. Firstly we have
2509 * to check that all registers involved are type E/Rxx.
2511 opflags_t sok = BITS32 | BITS64;
2512 int32_t o = input->offset;
2515 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2523 goto err; /* Invalid register */
2524 if (~sok & bx & SIZE_MASK)
2525 goto err; /* Invalid size */
2530 * While we're here, ensure the user didn't specify
2533 if (input->disp_size == 16 || input->disp_size == 64)
2536 if (addrbits == 16 ||
2537 (addrbits == 32 && !(sok & BITS32)) ||
2538 (addrbits == 64 && !(sok & BITS64)))
2541 /* now reorganize base/index */
2542 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2543 ((hb == b && ht == EAH_NOTBASE) ||
2544 (hb == i && ht == EAH_MAKEBASE))) {
2545 /* swap if hints say so */
2546 t = bt, bt = it, it = t;
2547 x = bx, bx = ix, ix = x;
2549 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2550 bt = -1, bx = 0, s++;
2551 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2552 /* make single reg base, unless hint */
2553 bt = it, bx = ix, it = -1, ix = 0;
2555 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2556 s == 3 || s == 5 || s == 9) && bt == -1)
2557 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2558 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2559 (input->eaflags & EAF_TIMESTWO))
2560 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2561 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2562 if (s == 1 && it == REG_NUM_ESP) {
2563 /* swap ESP into base if scale is 1 */
2564 t = it, it = bt, bt = t;
2565 x = ix, ix = bx, bx = x;
2567 if (it == REG_NUM_ESP ||
2568 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2569 goto err; /* wrong, for various reasons */
2571 output->rex |= rexflags(it, ix, REX_X);
2572 output->rex |= rexflags(bt, bx, REX_B);
2574 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2583 if (rm != REG_NUM_EBP && o == 0 &&
2584 seg == NO_SEG && !forw_ref &&
2585 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2587 else if (IS_MOD_01())
2593 output->sib_present = false;
2594 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2595 output->modrm = GEN_MODRM(mod, rfield, rm);
2598 int mod, scale, index, base;
2618 default: /* then what the smeg is it? */
2619 goto err; /* panic */
2627 if (base != REG_NUM_EBP && o == 0 &&
2628 seg == NO_SEG && !forw_ref &&
2629 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2631 else if (IS_MOD_01())
2637 output->sib_present = true;
2638 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2639 output->modrm = GEN_MODRM(mod, rfield, 4);
2640 output->sib = GEN_SIB(scale, index, base);
2642 } else { /* it's 16-bit */
2644 int16_t o = input->offset;
2646 /* check for 64-bit long mode */
2650 /* check all registers are BX, BP, SI or DI */
2651 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2652 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2655 /* ensure the user didn't specify DWORD/QWORD */
2656 if (input->disp_size == 32 || input->disp_size == 64)
2659 if (s != 1 && i != -1)
2660 goto err; /* no can do, in 16-bit EA */
2661 if (b == -1 && i != -1) {
2666 if ((b == R_SI || b == R_DI) && i != -1) {
2671 /* have BX/BP as base, SI/DI index */
2673 goto err; /* shouldn't ever happen, in theory */
2674 if (i != -1 && b != -1 &&
2675 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2676 goto err; /* invalid combinations */
2677 if (b == -1) /* pure offset: handled above */
2678 goto err; /* so if it gets to here, panic! */
2682 switch (i * 256 + b) {
2683 case R_SI * 256 + R_BX:
2686 case R_DI * 256 + R_BX:
2689 case R_SI * 256 + R_BP:
2692 case R_DI * 256 + R_BP:
2710 if (rm == -1) /* can't happen, in theory */
2711 goto err; /* so panic if it does */
2713 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2714 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2716 else if (IS_MOD_01())
2721 output->sib_present = false; /* no SIB - it's 16-bit */
2722 output->bytes = mod; /* bytes of offset needed */
2723 output->modrm = GEN_MODRM(mod, rfield, rm);
2728 output->size = 1 + output->sib_present + output->bytes;
2729 return output->type;
2732 return output->type = EA_INVALID;
2735 static void add_asp(insn *ins, int addrbits)
2740 valid = (addrbits == 64) ? 64|32 : 32|16;
2742 switch (ins->prefixes[PPS_ASIZE]) {
2753 valid &= (addrbits == 32) ? 16 : 32;
2759 for (j = 0; j < ins->operands; j++) {
2760 if (is_class(MEMORY, ins->oprs[j].type)) {
2763 /* Verify as Register */
2764 if (!is_register(ins->oprs[j].indexreg))
2767 i = nasm_reg_flags[ins->oprs[j].indexreg];
2769 /* Verify as Register */
2770 if (!is_register(ins->oprs[j].basereg))
2773 b = nasm_reg_flags[ins->oprs[j].basereg];
2775 if (ins->oprs[j].scale == 0)
2779 int ds = ins->oprs[j].disp_size;
2780 if ((addrbits != 64 && ds > 8) ||
2781 (addrbits == 64 && ds == 16))
2801 if (valid & addrbits) {
2802 ins->addr_size = addrbits;
2803 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2804 /* Add an address size prefix */
2805 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2806 ins->addr_size = (addrbits == 32) ? 16 : 32;
2809 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2810 ins->addr_size = addrbits; /* Error recovery */
2813 defdisp = ins->addr_size == 16 ? 16 : 32;
2815 for (j = 0; j < ins->operands; j++) {
2816 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2817 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2819 * mem_offs sizes must match the address size; if not,
2820 * strip the MEM_OFFS bit and match only EA instructions
2822 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);