1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - a signed byte immediate operand, from operand 0..3
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \140..\143 - an immediate word or signed byte for operand 0..3
64 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
65 * is a signed byte rather than a word. Opcode byte follows.
66 * \150..\153 - an immediate dword or signed byte for operand 0..3
67 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
68 * is a signed byte rather than a dword. Opcode byte follows.
69 * \172\ab - the register number from operand a in bits 7..4, with
70 * the 4-bit immediate from operand b in bits 3..0.
71 * \173\xab - the register number from operand a in bits 7..4, with
72 * the value b in bits 3..0.
73 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
74 * an arbitrary value in bits 3..0 (assembled as zero.)
75 * \2ab - a ModRM, calculated on EA in operand a, with the spare
76 * field equal to digit b.
77 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
78 * is not equal to the truncated and sign-extended 32-bit
79 * operand; used for 32-bit immediates in 64-bit mode.
80 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
81 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
82 * V field taken from operand 0..3.
83 * \270 - this instruction uses VEX/XOP rather than REX, with the
84 * V field set to 1111b.
86 * VEX/XOP prefixes are followed by the sequence:
87 * \tmm\wlp where mm is the M field; and wlp is:
89 * [l0] ll = 0 for L = 0 (.128, .lz)
90 * [l1] ll = 1 for L = 1 (.256)
91 * [lig] ll = 2 for L don't care (always assembled as 0)
93 * [w0] ww = 0 for W = 0
94 * [w1 ] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
98 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
100 * \271 - instruction takes XRELEASE (F3) with or without lock
101 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
102 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
103 * \274..\277 - a signed byte immediate operand, from operand 0..3,
104 * which is to be extended to the operand size.
105 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
106 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
107 * \312 - (disassembler only) invalid with non-default address size.
108 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
109 * \314 - (disassembler only) invalid with REX.B
110 * \315 - (disassembler only) invalid with REX.X
111 * \316 - (disassembler only) invalid with REX.R
112 * \317 - (disassembler only) invalid with REX.W
113 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
114 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
115 * \322 - indicates that this instruction is only valid when the
116 * operand size is the default (instruction to disassembler,
117 * generates no code in the assembler)
118 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
119 * \324 - indicates 64-bit operand size requiring REX prefix.
120 * \325 - instruction which always uses spl/bpl/sil/dil
121 * \330 - a literal byte follows in the code stream, to be added
122 * to the condition code value of the instruction.
123 * \331 - instruction not valid with REP prefix. Hint for
124 * disassembler only; for SSE instructions.
125 * \332 - REP prefix (0xF2 byte) used as opcode extension.
126 * \333 - REP prefix (0xF3 byte) used as opcode extension.
127 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
128 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
129 * \336 - force a REP(E) prefix (0xF2) even if not specified.
130 * \337 - force a REPNE prefix (0xF3) even if not specified.
131 * \336-\337 are still listed as prefixes in the disassembler.
132 * \340 - reserve <operand 0> bytes of uninitialized storage.
133 * Operand 0 had better be a segmentless constant.
134 * \341 - this instruction needs a WAIT "prefix"
135 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
136 * (POP is never used for CS) depending on operand 0
137 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
139 * \360 - no SSE prefix (== \364\331)
140 * \361 - 66 SSE prefix (== \366\331)
141 * \362 - F2 SSE prefix (== \364\332)
142 * \363 - F3 SSE prefix (== \364\333)
143 * \364 - operand-size prefix (0x66) not permitted
144 * \365 - address-size prefix (0x67) not permitted
145 * \366 - operand-size prefix (0x66) used as opcode extension
146 * \367 - address-size prefix (0x67) used as opcode extension
147 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
148 * 370 is used for Jcc, 371 is used for JMP.
149 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
150 * used for conditional jump over longer jump
151 * \374 - this instruction takes an XMM VSIB memory EA
152 * \375 - this instruction takes an YMM VSIB memory EA
155 #include "compiler.h"
159 #include <inttypes.h>
163 #include "assemble.h"
169 * Matching errors. These should be sorted so that more specific
170 * errors come later in the sequence.
178 * Matching success; the conditional ones first
180 MOK_JUMP, /* Matching OK but needs jmp_match() */
181 MOK_GOOD /* Matching unconditionally OK */
185 enum ea_type type; /* what kind of EA is this? */
186 int sib_present; /* is a SIB byte necessary? */
187 int bytes; /* # of bytes of offset needed */
188 int size; /* lazy - this is sib+bytes+1 */
189 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
192 #define GEN_SIB(scale, index, base) \
193 (((scale) << 6) | ((index) << 3) | ((base)))
195 #define GEN_MODRM(mod, reg, rm) \
196 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
198 static uint32_t cpu; /* cpu level received from nasm.c */
199 static efunc errfunc;
200 static struct ofmt *outfmt;
201 static ListGen *list;
203 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
204 static void gencode(int32_t segment, int64_t offset, int bits,
205 insn * ins, const struct itemplate *temp,
207 static enum match_result find_match(const struct itemplate **tempp,
209 int32_t segment, int64_t offset, int bits);
210 static enum match_result matches(const struct itemplate *, insn *, int bits);
211 static opflags_t regflag(const operand *);
212 static int32_t regval(const operand *);
213 static int rexflags(int, opflags_t, int);
214 static int op_rexflags(const operand *, int);
215 static void add_asp(insn *, int);
217 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
219 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
221 return ins->prefixes[pos] == prefix;
224 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
226 if (ins->prefixes[pos])
227 errfunc(ERR_NONFATAL, "invalid %s prefix",
228 prefix_name(ins->prefixes[pos]));
231 static const char *size_name(int size)
253 static void warn_overflow(int pass, int size)
255 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
256 "%s data exceeds bounds", size_name(size));
259 static void warn_overflow_const(int64_t data, int size)
261 if (overflow_general(data, size))
262 warn_overflow(ERR_PASS1, size);
265 static void warn_overflow_opd(const struct operand *o, int size)
267 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
268 if (overflow_general(o->offset, size))
269 warn_overflow(ERR_PASS2, size);
274 * This routine wrappers the real output format's output routine,
275 * in order to pass a copy of the data off to the listing file
276 * generator at the same time.
278 static void out(int64_t offset, int32_t segto, const void *data,
279 enum out_type type, uint64_t size,
280 int32_t segment, int32_t wrt)
282 static int32_t lineno = 0; /* static!!! */
283 static char *lnfname = NULL;
286 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
288 * This is a non-relocated address, and we're going to
289 * convert it into RAWDATA format.
294 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
298 WRITEADDR(q, *(int64_t *)data, size);
303 list->output(offset, data, type, size);
306 * this call to src_get determines when we call the
307 * debug-format-specific "linenum" function
308 * it updates lineno and lnfname to the current values
309 * returning 0 if "same as last time", -2 if lnfname
310 * changed, and the amount by which lineno changed,
311 * if it did. thus, these variables must be static
314 if (src_get(&lineno, &lnfname))
315 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
317 outfmt->output(segto, data, type, size, segment, wrt);
320 static bool jmp_match(int32_t segment, int64_t offset, int bits,
321 insn * ins, const uint8_t *code)
326 if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT))
330 if (optimizing < 0 && c == 0371)
333 isize = calcsize(segment, offset, bits, ins, code);
335 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
336 /* Be optimistic in pass 1 */
339 if (ins->oprs[0].segment != segment)
342 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
343 return (isize >= -128 && isize <= 127); /* is it byte size? */
346 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
347 insn * instruction, struct ofmt *output, efunc error,
350 const struct itemplate *temp;
355 int64_t start = offset;
356 int64_t wsize; /* size for DB etc. */
358 errfunc = error; /* to pass to other functions */
360 outfmt = output; /* likewise */
361 list = listgen; /* and again */
363 wsize = idata_bytes(instruction->opcode);
369 int32_t t = instruction->times;
372 "instruction->times < 0 (%ld) in assemble()", t);
374 while (t--) { /* repeat TIMES times */
375 list_for_each(e, instruction->eops) {
376 if (e->type == EOT_DB_NUMBER) {
378 errfunc(ERR_NONFATAL,
379 "integer supplied to a DT, DO or DY"
382 out(offset, segment, &e->offset,
383 OUT_ADDRESS, wsize, e->segment, e->wrt);
386 } else if (e->type == EOT_DB_STRING ||
387 e->type == EOT_DB_STRING_FREE) {
390 out(offset, segment, e->stringval,
391 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
392 align = e->stringlen % wsize;
395 align = wsize - align;
396 out(offset, segment, zero_buffer,
397 OUT_RAWDATA, align, NO_SEG, NO_SEG);
399 offset += e->stringlen + align;
402 if (t > 0 && t == instruction->times - 1) {
404 * Dummy call to list->output to give the offset to the
407 list->output(offset, NULL, OUT_RAWDATA, 0);
408 list->uplevel(LIST_TIMES);
411 if (instruction->times > 1)
412 list->downlevel(LIST_TIMES);
413 return offset - start;
416 if (instruction->opcode == I_INCBIN) {
417 const char *fname = instruction->eops->stringval;
420 fp = fopen(fname, "rb");
422 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
424 } else if (fseek(fp, 0L, SEEK_END) < 0) {
425 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
428 static char buf[4096];
429 size_t t = instruction->times;
434 if (instruction->eops->next) {
435 base = instruction->eops->next->offset;
437 if (instruction->eops->next->next &&
438 len > (size_t)instruction->eops->next->next->offset)
439 len = (size_t)instruction->eops->next->next->offset;
442 * Dummy call to list->output to give the offset to the
445 list->output(offset, NULL, OUT_RAWDATA, 0);
446 list->uplevel(LIST_INCBIN);
450 fseek(fp, base, SEEK_SET);
454 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
457 * This shouldn't happen unless the file
458 * actually changes while we are reading
462 "`incbin': unexpected EOF while"
463 " reading file `%s'", fname);
464 t = 0; /* Try to exit cleanly */
467 out(offset, segment, buf, OUT_RAWDATA, m,
472 list->downlevel(LIST_INCBIN);
473 if (instruction->times > 1) {
475 * Dummy call to list->output to give the offset to the
478 list->output(offset, NULL, OUT_RAWDATA, 0);
479 list->uplevel(LIST_TIMES);
480 list->downlevel(LIST_TIMES);
483 return instruction->times * len;
485 return 0; /* if we're here, there's an error */
488 /* Check to see if we need an address-size prefix */
489 add_asp(instruction, bits);
491 m = find_match(&temp, instruction, segment, offset, bits);
495 int64_t insn_size = calcsize(segment, offset, bits,
496 instruction, temp->code);
497 itimes = instruction->times;
498 if (insn_size < 0) /* shouldn't be, on pass two */
499 error(ERR_PANIC, "errors made it through from pass one");
502 for (j = 0; j < MAXPREFIX; j++) {
504 switch (instruction->prefixes[j]) {
524 error(ERR_WARNING | ERR_PASS2,
525 "cs segment base generated, but will be ignored in 64-bit mode");
531 error(ERR_WARNING | ERR_PASS2,
532 "ds segment base generated, but will be ignored in 64-bit mode");
538 error(ERR_WARNING | ERR_PASS2,
539 "es segment base generated, but will be ignored in 64-bit mode");
551 error(ERR_WARNING | ERR_PASS2,
552 "ss segment base generated, but will be ignored in 64-bit mode");
559 "segr6 and segr7 cannot be used as prefixes");
564 "16-bit addressing is not supported "
566 } else if (bits != 16)
576 "64-bit addressing is only supported "
600 error(ERR_PANIC, "invalid instruction prefix");
603 out(offset, segment, &c, OUT_RAWDATA, 1,
608 insn_end = offset + insn_size;
609 gencode(segment, offset, bits, instruction,
612 if (itimes > 0 && itimes == instruction->times - 1) {
614 * Dummy call to list->output to give the offset to the
617 list->output(offset, NULL, OUT_RAWDATA, 0);
618 list->uplevel(LIST_TIMES);
621 if (instruction->times > 1)
622 list->downlevel(LIST_TIMES);
623 return offset - start;
627 case MERR_OPSIZEMISSING:
628 error(ERR_NONFATAL, "operation size not specified");
630 case MERR_OPSIZEMISMATCH:
631 error(ERR_NONFATAL, "mismatch in operand sizes");
634 error(ERR_NONFATAL, "no instruction for this cpu level");
637 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
642 "invalid combination of opcode and operands");
649 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
650 insn * instruction, efunc error)
652 const struct itemplate *temp;
655 errfunc = error; /* to pass to other functions */
658 if (instruction->opcode == I_none)
661 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
662 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
663 instruction->opcode == I_DT || instruction->opcode == I_DO ||
664 instruction->opcode == I_DY) {
666 int32_t isize, osize, wsize;
669 wsize = idata_bytes(instruction->opcode);
671 list_for_each(e, instruction->eops) {
675 if (e->type == EOT_DB_NUMBER) {
677 warn_overflow_const(e->offset, wsize);
678 } else if (e->type == EOT_DB_STRING ||
679 e->type == EOT_DB_STRING_FREE)
680 osize = e->stringlen;
682 align = (-osize) % wsize;
685 isize += osize + align;
687 return isize * instruction->times;
690 if (instruction->opcode == I_INCBIN) {
691 const char *fname = instruction->eops->stringval;
696 fp = fopen(fname, "rb");
698 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
700 else if (fseek(fp, 0L, SEEK_END) < 0)
701 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
705 if (instruction->eops->next) {
706 len -= instruction->eops->next->offset;
707 if (instruction->eops->next->next &&
708 len > (size_t)instruction->eops->next->next->offset) {
709 len = (size_t)instruction->eops->next->next->offset;
712 val = instruction->times * len;
719 /* Check to see if we need an address-size prefix */
720 add_asp(instruction, bits);
722 m = find_match(&temp, instruction, segment, offset, bits);
724 /* we've matched an instruction. */
726 const uint8_t *codes = temp->code;
729 isize = calcsize(segment, offset, bits, instruction, codes);
732 for (j = 0; j < MAXPREFIX; j++) {
733 switch (instruction->prefixes[j]) {
759 return isize * instruction->times;
761 return -1; /* didn't match any instruction */
765 static bool possible_sbyte(operand *o)
767 return o->wrt == NO_SEG && o->segment == NO_SEG &&
768 !(o->opflags & OPFLAG_UNKNOWN) &&
769 optimizing >= 0 && !(o->type & STRICT);
772 /* check that opn[op] is a signed byte of size 16 or 32 */
773 static bool is_sbyte16(operand *o)
777 if (!possible_sbyte(o))
781 return v >= -128 && v <= 127;
784 static bool is_sbyte32(operand *o)
788 if (!possible_sbyte(o))
792 return v >= -128 && v <= 127;
795 static void bad_hle_warn(const insn * ins, uint8_t hleok)
797 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
798 enum whatwarn { w_none, w_lock, w_inval };
799 static const enum whatwarn warn[2][4] =
801 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
802 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
806 n = (unsigned int)rep_pfx - P_XACQUIRE;
808 return; /* Not XACQUIRE/XRELEASE */
810 switch (warn[n][hleok]) {
815 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
816 errfunc(ERR_WARNING | ERR_PASS2,
817 "%s with this instruction requires lock",
818 prefix_name(rep_pfx));
823 errfunc(ERR_WARNING | ERR_PASS2,
824 "%s invalid with this instruction",
825 prefix_name(rep_pfx));
830 /* Common construct */
831 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
833 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
834 insn * ins, const uint8_t *codes)
845 ins->rex = 0; /* Ensure REX is reset */
846 eat = EA_SCALAR; /* Expect a scalar EA */
848 if (ins->prefixes[PPS_OSIZE] == P_O64)
851 (void)segment; /* Don't warn that this parameter is unused */
852 (void)offset; /* Don't warn that this parameter is unused */
856 op1 = (c & 3) + ((opex & 1) << 2);
857 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
858 opx = &ins->oprs[op1];
859 opex = 0; /* For the next iteration */
866 codes += c, length += c;
877 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
892 if (opx->type & (BITS16 | BITS32 | BITS64))
893 length += (opx->type & BITS16) ? 2 : 4;
895 length += (bits == 16) ? 2 : 4;
903 length += ins->addr_size >> 3;
911 length += 8; /* MOV reg64/imm */
919 if (opx->type & (BITS16 | BITS32 | BITS64))
920 length += (opx->type & BITS16) ? 2 : 4;
922 length += (bits == 16) ? 2 : 4;
934 length += is_sbyte16(opx) ? 1 : 2;
943 length += is_sbyte32(opx) ? 1 : 4;
962 length += is_sbyte32(opx) ? 1 : 4;
971 ins->vexreg = regval(opx);
972 ins->vex_cm = *codes++;
973 ins->vex_wlp = *codes++;
979 ins->vex_cm = *codes++;
980 ins->vex_wlp = *codes++;
999 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1003 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1010 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1011 has_prefix(ins, PPS_ASIZE, P_A32))
1020 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1024 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1026 ins->prefixes[PPS_OSIZE] = P_O16;
1032 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1036 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1038 ins->prefixes[PPS_OSIZE] = P_O32;
1077 if (!ins->prefixes[PPS_REP])
1078 ins->prefixes[PPS_REP] = P_REP;
1082 if (!ins->prefixes[PPS_REP])
1083 ins->prefixes[PPS_REP] = P_REPNE;
1087 if (ins->oprs[0].segment != NO_SEG)
1088 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1089 " quantity of BSS space");
1091 length += ins->oprs[0].offset;
1095 if (!ins->prefixes[PPS_WAIT])
1096 ins->prefixes[PPS_WAIT] = P_WAIT;
1154 struct operand *opy = &ins->oprs[op2];
1156 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1159 /* pick rfield from operand b (opx) */
1160 rflags = regflag(opx);
1161 rfield = nasm_regvals[opx->basereg];
1166 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1167 rfield, rflags) != eat) {
1168 errfunc(ERR_NONFATAL, "invalid effective address");
1171 ins->rex |= ea_data.rex;
1172 length += ea_data.size;
1178 errfunc(ERR_PANIC, "internal instruction table corrupt"
1179 ": instruction code \\%o (0x%02X) given", c, c);
1184 ins->rex &= rex_mask;
1186 if (ins->rex & REX_NH) {
1187 if (ins->rex & REX_H) {
1188 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1191 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1194 if (ins->rex & REX_V) {
1195 int bad32 = REX_R|REX_W|REX_X|REX_B;
1197 if (ins->rex & REX_H) {
1198 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1201 switch (ins->vex_wlp & 060) {
1215 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1216 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1219 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1223 } else if (ins->rex & REX_REAL) {
1224 if (ins->rex & REX_H) {
1225 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1227 } else if (bits == 64) {
1229 } else if ((ins->rex & REX_L) &&
1230 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1233 assert_no_prefix(ins, PPS_LOCK);
1236 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1241 bad_hle_warn(ins, hleok);
1246 #define EMIT_REX() \
1247 if (!(ins->rex & REX_V) && (ins->rex & REX_REAL) && (bits == 64)) { \
1248 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1249 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1254 static void gencode(int32_t segment, int64_t offset, int bits,
1255 insn * ins, const struct itemplate *temp,
1258 static const char condval[] = { /* conditional opcodes */
1259 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1260 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1261 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1268 struct operand *opx;
1269 const uint8_t *codes = temp->code;
1271 enum ea_type eat = EA_SCALAR;
1275 op1 = (c & 3) + ((opex & 1) << 2);
1276 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1277 opx = &ins->oprs[op1];
1278 opex = 0; /* For the next iteration */
1286 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1299 bytes[0] = *codes++ + (regval(opx) & 7);
1300 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1306 * The test for BITS8 and SBYTE here is intended to avoid
1307 * warning on optimizer actions due to SBYTE, while still
1308 * warn on explicit BYTE directives. Also warn, obviously,
1309 * if the optimizer isn't enabled.
1311 if (((opx->type & BITS8) ||
1312 !(opx->type & temp->opd[op1] & BYTENESS)) &&
1313 (opx->offset < -128 || opx->offset > 127)) {
1314 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1315 "signed byte value exceeds bounds");
1317 if (opx->segment != NO_SEG) {
1319 out(offset, segment, &data, OUT_ADDRESS, 1,
1320 opx->segment, opx->wrt);
1322 bytes[0] = opx->offset;
1323 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1330 if (opx->offset < -256 || opx->offset > 255) {
1331 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1332 "byte value exceeds bounds");
1334 if (opx->segment != NO_SEG) {
1336 out(offset, segment, &data, OUT_ADDRESS, 1,
1337 opx->segment, opx->wrt);
1339 bytes[0] = opx->offset;
1340 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1347 if (opx->offset < 0 || opx->offset > 255)
1348 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1349 "unsigned byte value exceeds bounds");
1350 if (opx->segment != NO_SEG) {
1352 out(offset, segment, &data, OUT_ADDRESS, 1,
1353 opx->segment, opx->wrt);
1355 bytes[0] = opx->offset;
1356 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1363 warn_overflow_opd(opx, 2);
1365 out(offset, segment, &data, OUT_ADDRESS, 2,
1366 opx->segment, opx->wrt);
1371 if (opx->type & (BITS16 | BITS32))
1372 size = (opx->type & BITS16) ? 2 : 4;
1374 size = (bits == 16) ? 2 : 4;
1375 warn_overflow_opd(opx, size);
1377 out(offset, segment, &data, OUT_ADDRESS, size,
1378 opx->segment, opx->wrt);
1383 warn_overflow_opd(opx, 4);
1385 out(offset, segment, &data, OUT_ADDRESS, 4,
1386 opx->segment, opx->wrt);
1392 size = ins->addr_size >> 3;
1393 warn_overflow_opd(opx, size);
1394 out(offset, segment, &data, OUT_ADDRESS, size,
1395 opx->segment, opx->wrt);
1400 if (opx->segment != segment) {
1402 out(offset, segment, &data,
1403 OUT_REL1ADR, insn_end - offset,
1404 opx->segment, opx->wrt);
1406 data = opx->offset - insn_end;
1407 if (data > 127 || data < -128)
1408 errfunc(ERR_NONFATAL, "short jump is out of range");
1409 out(offset, segment, &data,
1410 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1416 data = (int64_t)opx->offset;
1417 out(offset, segment, &data, OUT_ADDRESS, 8,
1418 opx->segment, opx->wrt);
1423 if (opx->segment != segment) {
1425 out(offset, segment, &data,
1426 OUT_REL2ADR, insn_end - offset,
1427 opx->segment, opx->wrt);
1429 data = opx->offset - insn_end;
1430 out(offset, segment, &data,
1431 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1437 if (opx->type & (BITS16 | BITS32 | BITS64))
1438 size = (opx->type & BITS16) ? 2 : 4;
1440 size = (bits == 16) ? 2 : 4;
1441 if (opx->segment != segment) {
1443 out(offset, segment, &data,
1444 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1445 insn_end - offset, opx->segment, opx->wrt);
1447 data = opx->offset - insn_end;
1448 out(offset, segment, &data,
1449 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1455 if (opx->segment != segment) {
1457 out(offset, segment, &data,
1458 OUT_REL4ADR, insn_end - offset,
1459 opx->segment, opx->wrt);
1461 data = opx->offset - insn_end;
1462 out(offset, segment, &data,
1463 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1469 if (opx->segment == NO_SEG)
1470 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1473 out(offset, segment, &data, OUT_ADDRESS, 2,
1474 outfmt->segbase(1 + opx->segment),
1481 warn_overflow_opd(opx, 2);
1482 if (is_sbyte16(opx)) {
1484 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1488 out(offset, segment, &data, OUT_ADDRESS, 2,
1489 opx->segment, opx->wrt);
1496 bytes[0] = *codes++;
1497 if (is_sbyte16(opx))
1498 bytes[0] |= 2; /* s-bit */
1499 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1505 warn_overflow_opd(opx, 4);
1506 if (is_sbyte32(opx)) {
1508 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1512 out(offset, segment, &data, OUT_ADDRESS, 4,
1513 opx->segment, opx->wrt);
1520 bytes[0] = *codes++;
1521 if (is_sbyte32(opx))
1522 bytes[0] |= 2; /* s-bit */
1523 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1529 opx = &ins->oprs[c >> 3];
1530 bytes[0] = nasm_regvals[opx->basereg] << 4;
1531 opx = &ins->oprs[c & 7];
1532 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1533 errfunc(ERR_NONFATAL,
1534 "non-absolute expression not permitted as argument %d",
1537 if (opx->offset & ~15) {
1538 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1539 "four-bit argument exceeds bounds");
1541 bytes[0] |= opx->offset & 15;
1543 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1549 opx = &ins->oprs[c >> 4];
1550 bytes[0] = nasm_regvals[opx->basereg] << 4;
1552 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1557 bytes[0] = nasm_regvals[opx->basereg] << 4;
1558 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1564 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1565 (int32_t)data != (int64_t)data) {
1566 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1567 "signed dword immediate exceeds bounds");
1569 if (is_sbyte32(opx)) {
1571 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1575 out(offset, segment, &data, OUT_ADDRESS, 4,
1576 opx->segment, opx->wrt);
1583 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1584 (int32_t)data != (int64_t)data) {
1585 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1586 "signed dword immediate exceeds bounds");
1588 out(offset, segment, &data, OUT_ADDRESS, 4,
1589 opx->segment, opx->wrt);
1596 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1597 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1598 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1599 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1600 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1601 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1605 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1606 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1607 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1617 if (ins->rex & REX_W)
1619 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1621 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1626 um = (uint64_t)2 << (s-1);
1629 if (uv > 127 && uv < (uint64_t)-128 &&
1630 (uv < um-128 || uv > um-1)) {
1631 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1632 "signed byte value exceeds bounds");
1634 if (opx->segment != NO_SEG) {
1636 out(offset, segment, &data, OUT_ADDRESS, 1,
1637 opx->segment, opx->wrt);
1640 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1651 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1653 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1660 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1662 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1694 *bytes = *codes++ ^ condval[ins->condition];
1695 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1704 *bytes = c - 0332 + 0xF2;
1705 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1710 if (ins->rex & REX_R) {
1712 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1715 ins->rex &= ~(REX_L|REX_R);
1726 if (ins->oprs[0].segment != NO_SEG)
1727 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1729 int64_t size = ins->oprs[0].offset;
1731 out(offset, segment, NULL,
1732 OUT_RESERVE, size, NO_SEG, NO_SEG);
1743 switch (ins->oprs[0].basereg) {
1758 "bizarre 8086 segment register received");
1760 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1767 switch (ins->oprs[0].basereg) {
1776 "bizarre 386 segment register received");
1778 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1787 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1793 bytes[0] = c - 0362 + 0xf2;
1794 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1804 *bytes = c - 0366 + 0x66;
1805 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1815 *bytes = bits == 16 ? 3 : 5;
1816 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1846 struct operand *opy = &ins->oprs[op2];
1849 /* pick rfield from operand b (opx) */
1850 rflags = regflag(opx);
1851 rfield = nasm_regvals[opx->basereg];
1853 /* rfield is constant */
1858 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1859 rfield, rflags) != eat)
1860 errfunc(ERR_NONFATAL, "invalid effective address");
1863 *p++ = ea_data.modrm;
1864 if (ea_data.sib_present)
1868 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1871 * Make sure the address gets the right offset in case
1872 * the line breaks in the .lst file (BR 1197827)
1877 switch (ea_data.bytes) {
1887 if (opy->segment == segment) {
1889 if (overflow_signed(data, ea_data.bytes))
1890 warn_overflow(ERR_PASS2, ea_data.bytes);
1891 out(offset, segment, &data, OUT_ADDRESS,
1892 ea_data.bytes, NO_SEG, NO_SEG);
1894 /* overflow check in output/linker? */
1895 out(offset, segment, &data, OUT_REL4ADR,
1896 insn_end - offset, opy->segment, opy->wrt);
1899 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1900 signed_bits(opy->offset, ins->addr_size) !=
1901 signed_bits(opy->offset, ea_data.bytes * 8))
1902 warn_overflow(ERR_PASS2, ea_data.bytes);
1904 out(offset, segment, &data, OUT_ADDRESS,
1905 ea_data.bytes, opy->segment, opy->wrt);
1911 "Invalid amount of bytes (%d) for offset?!",
1920 errfunc(ERR_PANIC, "internal instruction table corrupt"
1921 ": instruction code \\%o (0x%02X) given", c, c);
1927 static opflags_t regflag(const operand * o)
1929 if (!is_register(o->basereg))
1930 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1931 return nasm_reg_flags[o->basereg];
1934 static int32_t regval(const operand * o)
1936 if (!is_register(o->basereg))
1937 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1938 return nasm_regvals[o->basereg];
1941 static int op_rexflags(const operand * o, int mask)
1946 if (!is_register(o->basereg))
1947 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1949 flags = nasm_reg_flags[o->basereg];
1950 val = nasm_regvals[o->basereg];
1952 return rexflags(val, flags, mask);
1955 static int rexflags(int val, opflags_t flags, int mask)
1960 rex |= REX_B|REX_X|REX_R;
1963 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1965 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1971 static enum match_result find_match(const struct itemplate **tempp,
1973 int32_t segment, int64_t offset, int bits)
1975 const struct itemplate *temp;
1976 enum match_result m, merr;
1977 opflags_t xsizeflags[MAX_OPERANDS];
1978 bool opsizemissing = false;
1981 for (i = 0; i < instruction->operands; i++)
1982 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1984 merr = MERR_INVALOP;
1986 for (temp = nasm_instructions[instruction->opcode];
1987 temp->opcode != I_none; temp++) {
1988 m = matches(temp, instruction, bits);
1989 if (m == MOK_JUMP) {
1990 if (jmp_match(segment, offset, bits, instruction, temp->code))
1994 } else if (m == MERR_OPSIZEMISSING &&
1995 (temp->flags & IF_SMASK) != IF_SX) {
1997 * Missing operand size and a candidate for fuzzy matching...
1999 for (i = 0; i < temp->operands; i++) {
2000 if ((temp->opd[i] & SAME_AS) == 0)
2001 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2003 opsizemissing = true;
2007 if (merr == MOK_GOOD)
2011 /* No match, but see if we can get a fuzzy operand size match... */
2015 for (i = 0; i < instruction->operands; i++) {
2017 * We ignore extrinsic operand sizes on registers, so we should
2018 * never try to fuzzy-match on them. This also resolves the case
2019 * when we have e.g. "xmmrm128" in two different positions.
2021 if (is_class(REGISTER, instruction->oprs[i].type))
2024 /* This tests if xsizeflags[i] has more than one bit set */
2025 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2026 goto done; /* No luck */
2028 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2031 /* Try matching again... */
2032 for (temp = nasm_instructions[instruction->opcode];
2033 temp->opcode != I_none; temp++) {
2034 m = matches(temp, instruction, bits);
2035 if (m == MOK_JUMP) {
2036 if (jmp_match(segment, offset, bits, instruction, temp->code))
2043 if (merr == MOK_GOOD)
2052 static enum match_result matches(const struct itemplate *itemp,
2053 insn *instruction, int bits)
2055 int i, size[MAX_OPERANDS], asize, oprs;
2056 bool opsizemissing = false;
2061 if (itemp->opcode != instruction->opcode)
2062 return MERR_INVALOP;
2065 * Count the operands
2067 if (itemp->operands != instruction->operands)
2068 return MERR_INVALOP;
2073 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2074 return MERR_INVALOP;
2077 * Check that no spurious colons or TOs are present
2079 for (i = 0; i < itemp->operands; i++)
2080 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2081 return MERR_INVALOP;
2084 * Process size flags
2086 switch (itemp->flags & IF_SMASK) {
2126 if (itemp->flags & IF_ARMASK) {
2127 /* S- flags only apply to a specific operand */
2128 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2129 memset(size, 0, sizeof size);
2132 /* S- flags apply to all operands */
2133 for (i = 0; i < MAX_OPERANDS; i++)
2138 * Check that the operand flags all match up,
2139 * it's a bit tricky so lets be verbose:
2141 * 1) Find out the size of operand. If instruction
2142 * doesn't have one specified -- we're trying to
2143 * guess it either from template (IF_S* flag) or
2146 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2147 * (ie the same operand as was specified somewhere in template, and
2148 * this referred operand index is being achieved via ~SAME_AS)
2149 * we are to be sure that both registers (in template and instruction)
2152 * 3) If template operand do not match the instruction OR
2153 * template has an operand size specified AND this size differ
2154 * from which instruction has (perhaps we got it from code bits)
2156 * a) Check that only size of instruction and operand is differ
2157 * other characteristics do match
2158 * b) Perhaps it's a register specified in instruction so
2159 * for such a case we just mark that operand as "size
2160 * missing" and this will turn on fuzzy operand size
2161 * logic facility (handled by a caller)
2163 for (i = 0; i < itemp->operands; i++) {
2164 opflags_t type = instruction->oprs[i].type;
2165 if (!(type & SIZE_MASK))
2168 if (itemp->opd[i] & SAME_AS) {
2169 int j = itemp->opd[i] & ~SAME_AS;
2170 if (type != instruction->oprs[j].type ||
2171 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2172 return MERR_INVALOP;
2173 } else if (itemp->opd[i] & ~type ||
2174 ((itemp->opd[i] & SIZE_MASK) &&
2175 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2176 if ((itemp->opd[i] & ~type & ~SIZE_MASK) || (type & SIZE_MASK)) {
2177 return MERR_INVALOP;
2178 } else if (!is_class(REGISTER, type)) {
2180 * Note: we don't honor extrinsic operand sizes for registers,
2181 * so "missing operand size" for a register should be
2182 * considered a wildcard match rather than an error.
2184 opsizemissing = true;
2190 return MERR_OPSIZEMISSING;
2193 * Check operand sizes
2195 if (itemp->flags & (IF_SM | IF_SM2)) {
2196 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2197 for (i = 0; i < oprs; i++) {
2198 asize = itemp->opd[i] & SIZE_MASK;
2200 for (i = 0; i < oprs; i++)
2206 oprs = itemp->operands;
2209 for (i = 0; i < itemp->operands; i++) {
2210 if (!(itemp->opd[i] & SIZE_MASK) &&
2211 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2212 return MERR_OPSIZEMISMATCH;
2216 * Check template is okay at the set cpu level
2218 if (((itemp->flags & IF_PLEVEL) > cpu))
2222 * Verify the appropriate long mode flag.
2224 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2225 return MERR_BADMODE;
2228 * Check if special handling needed for Jumps
2230 if ((itemp->code[0] & 0374) == 0370)
2236 static enum ea_type process_ea(operand *input, ea *output, int bits,
2237 int addrbits, int rfield, opflags_t rflags)
2239 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2241 output->type = EA_SCALAR;
2242 output->rip = false;
2244 /* REX flags for the rfield operand */
2245 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2247 if (is_class(REGISTER, input->type)) {
2249 * It's a direct register.
2253 if (!is_register(input->basereg))
2258 if (!is_class(REG_EA, f))
2261 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2262 output->sib_present = false; /* no SIB necessary */
2263 output->bytes = 0; /* no offset necessary either */
2264 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2267 * It's a memory reference.
2269 if (input->basereg == -1 &&
2270 (input->indexreg == -1 || input->scale == 0)) {
2272 * It's a pure offset.
2274 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2275 input->segment == NO_SEG) {
2276 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2277 input->type &= ~IP_REL;
2278 input->type |= MEMORY;
2281 if (input->eaflags & EAF_BYTEOFFS ||
2282 (input->eaflags & EAF_WORDOFFS &&
2283 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2284 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2287 if (bits == 64 && (~input->type & IP_REL)) {
2288 output->sib_present = true;
2289 output->sib = GEN_SIB(0, 4, 5);
2291 output->modrm = GEN_MODRM(0, rfield, 4);
2292 output->rip = false;
2294 output->sib_present = false;
2295 output->bytes = (addrbits != 16 ? 4 : 2);
2296 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2297 output->rip = bits == 64;
2301 * It's an indirection.
2303 int i = input->indexreg, b = input->basereg, s = input->scale;
2304 int32_t seg = input->segment;
2305 int hb = input->hintbase, ht = input->hinttype;
2306 int t, it, bt; /* register numbers */
2307 opflags_t x, ix, bx; /* register flags */
2310 i = -1; /* make this easy, at least */
2312 if (is_register(i)) {
2313 it = nasm_regvals[i];
2314 ix = nasm_reg_flags[i];
2320 if (is_register(b)) {
2321 bt = nasm_regvals[b];
2322 bx = nasm_reg_flags[b];
2328 /* if either one are a vector register... */
2329 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2330 int32_t sok = BITS32 | BITS64;
2331 int32_t o = input->offset;
2332 int mod, scale, index, base;
2335 * For a vector SIB, one has to be a vector and the other,
2336 * if present, a GPR. The vector must be the index operand.
2338 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2344 t = bt, bt = it, it = t;
2345 x = bx, bx = ix, ix = x;
2351 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2358 * While we're here, ensure the user didn't specify
2361 if (input->disp_size == 16 || input->disp_size == 64)
2364 if (addrbits == 16 ||
2365 (addrbits == 32 && !(sok & BITS32)) ||
2366 (addrbits == 64 && !(sok & BITS64)))
2369 output->type = (ix & YMMREG & ~REG_EA)
2370 ? EA_YMMVSIB : EA_XMMVSIB;
2372 output->rex |= rexflags(it, ix, REX_X);
2373 output->rex |= rexflags(bt, bx, REX_B);
2375 index = it & 7; /* it is known to be != -1 */
2390 default: /* then what the smeg is it? */
2391 goto err; /* panic */
2399 if (base != REG_NUM_EBP && o == 0 &&
2400 seg == NO_SEG && !forw_ref &&
2401 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2403 else if (input->eaflags & EAF_BYTEOFFS ||
2404 (o >= -128 && o <= 127 &&
2405 seg == NO_SEG && !forw_ref &&
2406 !(input->eaflags & EAF_WORDOFFS)))
2412 output->sib_present = true;
2413 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2414 output->modrm = GEN_MODRM(mod, rfield, 4);
2415 output->sib = GEN_SIB(scale, index, base);
2416 } else if ((ix|bx) & (BITS32|BITS64)) {
2418 * it must be a 32/64-bit memory reference. Firstly we have
2419 * to check that all registers involved are type E/Rxx.
2421 int32_t sok = BITS32 | BITS64;
2422 int32_t o = input->offset;
2425 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2433 goto err; /* Invalid register */
2434 if (~sok & bx & SIZE_MASK)
2435 goto err; /* Invalid size */
2440 * While we're here, ensure the user didn't specify
2443 if (input->disp_size == 16 || input->disp_size == 64)
2446 if (addrbits == 16 ||
2447 (addrbits == 32 && !(sok & BITS32)) ||
2448 (addrbits == 64 && !(sok & BITS64)))
2451 /* now reorganize base/index */
2452 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2453 ((hb == b && ht == EAH_NOTBASE) ||
2454 (hb == i && ht == EAH_MAKEBASE))) {
2455 /* swap if hints say so */
2456 t = bt, bt = it, it = t;
2457 x = bx, bx = ix, ix = x;
2459 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2460 bt = -1, bx = 0, s++;
2461 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2462 /* make single reg base, unless hint */
2463 bt = it, bx = ix, it = -1, ix = 0;
2465 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2466 s == 3 || s == 5 || s == 9) && bt == -1)
2467 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2468 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2469 (input->eaflags & EAF_TIMESTWO))
2470 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2471 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2472 if (s == 1 && it == REG_NUM_ESP) {
2473 /* swap ESP into base if scale is 1 */
2474 t = it, it = bt, bt = t;
2475 x = ix, ix = bx, bx = x;
2477 if (it == REG_NUM_ESP ||
2478 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2479 goto err; /* wrong, for various reasons */
2481 output->rex |= rexflags(it, ix, REX_X);
2482 output->rex |= rexflags(bt, bx, REX_B);
2484 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2493 if (rm != REG_NUM_EBP && o == 0 &&
2494 seg == NO_SEG && !forw_ref &&
2495 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2497 else if (input->eaflags & EAF_BYTEOFFS ||
2498 (o >= -128 && o <= 127 &&
2499 seg == NO_SEG && !forw_ref &&
2500 !(input->eaflags & EAF_WORDOFFS)))
2506 output->sib_present = false;
2507 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2508 output->modrm = GEN_MODRM(mod, rfield, rm);
2511 int mod, scale, index, base;
2531 default: /* then what the smeg is it? */
2532 goto err; /* panic */
2540 if (base != REG_NUM_EBP && o == 0 &&
2541 seg == NO_SEG && !forw_ref &&
2542 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2544 else if (input->eaflags & EAF_BYTEOFFS ||
2545 (o >= -128 && o <= 127 &&
2546 seg == NO_SEG && !forw_ref &&
2547 !(input->eaflags & EAF_WORDOFFS)))
2553 output->sib_present = true;
2554 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2555 output->modrm = GEN_MODRM(mod, rfield, 4);
2556 output->sib = GEN_SIB(scale, index, base);
2558 } else { /* it's 16-bit */
2560 int16_t o = input->offset;
2562 /* check for 64-bit long mode */
2566 /* check all registers are BX, BP, SI or DI */
2567 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2568 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2571 /* ensure the user didn't specify DWORD/QWORD */
2572 if (input->disp_size == 32 || input->disp_size == 64)
2575 if (s != 1 && i != -1)
2576 goto err; /* no can do, in 16-bit EA */
2577 if (b == -1 && i != -1) {
2582 if ((b == R_SI || b == R_DI) && i != -1) {
2587 /* have BX/BP as base, SI/DI index */
2589 goto err; /* shouldn't ever happen, in theory */
2590 if (i != -1 && b != -1 &&
2591 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2592 goto err; /* invalid combinations */
2593 if (b == -1) /* pure offset: handled above */
2594 goto err; /* so if it gets to here, panic! */
2598 switch (i * 256 + b) {
2599 case R_SI * 256 + R_BX:
2602 case R_DI * 256 + R_BX:
2605 case R_SI * 256 + R_BP:
2608 case R_DI * 256 + R_BP:
2626 if (rm == -1) /* can't happen, in theory */
2627 goto err; /* so panic if it does */
2629 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2630 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2632 else if (input->eaflags & EAF_BYTEOFFS ||
2633 (o >= -128 && o <= 127 && seg == NO_SEG &&
2634 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2639 output->sib_present = false; /* no SIB - it's 16-bit */
2640 output->bytes = mod; /* bytes of offset needed */
2641 output->modrm = GEN_MODRM(mod, rfield, rm);
2646 output->size = 1 + output->sib_present + output->bytes;
2647 return output->type;
2650 return output->type = EA_INVALID;
2653 static void add_asp(insn *ins, int addrbits)
2658 valid = (addrbits == 64) ? 64|32 : 32|16;
2660 switch (ins->prefixes[PPS_ASIZE]) {
2671 valid &= (addrbits == 32) ? 16 : 32;
2677 for (j = 0; j < ins->operands; j++) {
2678 if (is_class(MEMORY, ins->oprs[j].type)) {
2681 /* Verify as Register */
2682 if (!is_register(ins->oprs[j].indexreg))
2685 i = nasm_reg_flags[ins->oprs[j].indexreg];
2687 /* Verify as Register */
2688 if (!is_register(ins->oprs[j].basereg))
2691 b = nasm_reg_flags[ins->oprs[j].basereg];
2693 if (ins->oprs[j].scale == 0)
2697 int ds = ins->oprs[j].disp_size;
2698 if ((addrbits != 64 && ds > 8) ||
2699 (addrbits == 64 && ds == 16))
2719 if (valid & addrbits) {
2720 ins->addr_size = addrbits;
2721 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2722 /* Add an address size prefix */
2723 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2724 ins->addr_size = (addrbits == 32) ? 16 : 32;
2727 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2728 ins->addr_size = addrbits; /* Error recovery */
2731 defdisp = ins->addr_size == 16 ? 16 : 32;
2733 for (j = 0; j < ins->operands; j++) {
2734 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2735 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2737 * mem_offs sizes must match the address size; if not,
2738 * strip the MEM_OFFS bit and match only EA instructions
2740 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);