1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \20..\23 - a byte immediate operand, from operand 0..3
46 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
47 * \30..\33 - a word immediate operand, from operand 0..3
48 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
49 * assembly mode or the operand-size override on the operand
50 * \40..\43 - a long immediate operand, from operand 0..3
51 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
52 * depending on the address size of the instruction.
53 * \50..\53 - a byte relative operand, from operand 0..3
54 * \54..\57 - a qword immediate operand, from operand 0..3
55 * \60..\63 - a word relative operand, from operand 0..3
56 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
57 * assembly mode or the operand-size override on the operand
58 * \70..\73 - a long relative operand, from operand 0..3
59 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
60 * \1ab - a ModRM, calculated on EA in operand a, with the spare
61 * field the register value of operand b.
62 * \172\ab - the register number from operand a in bits 7..4, with
63 * the 4-bit immediate from operand b in bits 3..0.
64 * \173\xab - the register number from operand a in bits 7..4, with
65 * the value b in bits 3..0.
66 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
67 * an arbitrary value in bits 3..0 (assembled as zero.)
68 * \2ab - a ModRM, calculated on EA in operand a, with the spare
69 * field equal to digit b.
70 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
71 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
72 * V field taken from operand 0..3.
73 * \270 - this instruction uses VEX/XOP rather than REX, with the
74 * V field set to 1111b.
76 * VEX/XOP prefixes are followed by the sequence:
77 * \tmm\wlp where mm is the M field; and wlp is:
79 * [l0] ll = 0 for L = 0 (.128, .lz)
80 * [l1] ll = 1 for L = 1 (.256)
81 * [lig] ll = 2 for L don't care (always assembled as 0)
83 * [w0] ww = 0 for W = 0
84 * [w1 ] ww = 1 for W = 1
85 * [wig] ww = 2 for W don't care (always assembled as 0)
86 * [ww] ww = 3 for W used as REX.W
88 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
90 * \271 - instruction takes XRELEASE (F3) with or without lock
91 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
92 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
93 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
94 * to the operand size (if o16/o32/o64 present) or the bit size
95 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
96 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
97 * \312 - (disassembler only) invalid with non-default address size.
98 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
99 * \314 - (disassembler only) invalid with REX.B
100 * \315 - (disassembler only) invalid with REX.X
101 * \316 - (disassembler only) invalid with REX.R
102 * \317 - (disassembler only) invalid with REX.W
103 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
104 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
105 * \322 - indicates that this instruction is only valid when the
106 * operand size is the default (instruction to disassembler,
107 * generates no code in the assembler)
108 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
109 * \324 - indicates 64-bit operand size requiring REX prefix.
110 * \325 - instruction which always uses spl/bpl/sil/dil
111 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
112 disassembler only; for SSE instructions.
113 * \330 - a literal byte follows in the code stream, to be added
114 * to the condition code value of the instruction.
115 * \331 - instruction not valid with REP prefix. Hint for
116 * disassembler only; for SSE instructions.
117 * \332 - REP prefix (0xF2 byte) used as opcode extension.
118 * \333 - REP prefix (0xF3 byte) used as opcode extension.
119 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
120 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
121 * \336 - force a REP(E) prefix (0xF3) even if not specified.
122 * \337 - force a REPNE prefix (0xF2) even if not specified.
123 * \336-\337 are still listed as prefixes in the disassembler.
124 * \340 - reserve <operand 0> bytes of uninitialized storage.
125 * Operand 0 had better be a segmentless constant.
126 * \341 - this instruction needs a WAIT "prefix"
127 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
128 * (POP is never used for CS) depending on operand 0
129 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
131 * \360 - no SSE prefix (== \364\331)
132 * \361 - 66 SSE prefix (== \366\331)
133 * \362 - F2 SSE prefix (== \364\332)
134 * \363 - F3 SSE prefix (== \364\333)
135 * \364 - operand-size prefix (0x66) not permitted
136 * \365 - address-size prefix (0x67) not permitted
137 * \366 - operand-size prefix (0x66) used as opcode extension
138 * \367 - address-size prefix (0x67) used as opcode extension
139 * \370,\371 - match only if operand 0 meets byte jump criteria.
140 * 370 is used for Jcc, 371 is used for JMP.
141 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
142 * used for conditional jump over longer jump
143 * \374 - this instruction takes an XMM VSIB memory EA
144 * \375 - this instruction takes an YMM VSIB memory EA
147 #include "compiler.h"
151 #include <inttypes.h>
155 #include "assemble.h"
161 * Matching errors. These should be sorted so that more specific
162 * errors come later in the sequence.
171 * Matching success; the conditional ones first
173 MOK_JUMP, /* Matching OK but needs jmp_match() */
174 MOK_GOOD /* Matching unconditionally OK */
178 enum ea_type type; /* what kind of EA is this? */
179 int sib_present; /* is a SIB byte necessary? */
180 int bytes; /* # of bytes of offset needed */
181 int size; /* lazy - this is sib+bytes+1 */
182 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
185 #define GEN_SIB(scale, index, base) \
186 (((scale) << 6) | ((index) << 3) | ((base)))
188 #define GEN_MODRM(mod, reg, rm) \
189 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
191 static uint32_t cpu; /* cpu level received from nasm.c */
192 static efunc errfunc;
193 static struct ofmt *outfmt;
194 static ListGen *list;
196 static int64_t calcsize(int32_t, int64_t, int, insn *,
197 const struct itemplate *);
198 static void gencode(int32_t segment, int64_t offset, int bits,
199 insn * ins, const struct itemplate *temp,
201 static enum match_result find_match(const struct itemplate **tempp,
203 int32_t segment, int64_t offset, int bits);
204 static enum match_result matches(const struct itemplate *, insn *, int bits);
205 static opflags_t regflag(const operand *);
206 static int32_t regval(const operand *);
207 static int rexflags(int, opflags_t, int);
208 static int op_rexflags(const operand *, int);
209 static void add_asp(insn *, int);
211 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
213 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
215 return ins->prefixes[pos] == prefix;
218 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
220 if (ins->prefixes[pos])
221 errfunc(ERR_NONFATAL, "invalid %s prefix",
222 prefix_name(ins->prefixes[pos]));
225 static const char *size_name(int size)
247 static void warn_overflow(int pass, int size)
249 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
250 "%s data exceeds bounds", size_name(size));
253 static void warn_overflow_const(int64_t data, int size)
255 if (overflow_general(data, size))
256 warn_overflow(ERR_PASS1, size);
259 static void warn_overflow_opd(const struct operand *o, int size)
261 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
262 if (overflow_general(o->offset, size))
263 warn_overflow(ERR_PASS2, size);
268 * This routine wrappers the real output format's output routine,
269 * in order to pass a copy of the data off to the listing file
270 * generator at the same time.
272 static void out(int64_t offset, int32_t segto, const void *data,
273 enum out_type type, uint64_t size,
274 int32_t segment, int32_t wrt)
276 static int32_t lineno = 0; /* static!!! */
277 static char *lnfname = NULL;
280 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
282 * This is a non-relocated address, and we're going to
283 * convert it into RAWDATA format.
288 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
292 WRITEADDR(q, *(int64_t *)data, size);
297 list->output(offset, data, type, size);
300 * this call to src_get determines when we call the
301 * debug-format-specific "linenum" function
302 * it updates lineno and lnfname to the current values
303 * returning 0 if "same as last time", -2 if lnfname
304 * changed, and the amount by which lineno changed,
305 * if it did. thus, these variables must be static
308 if (src_get(&lineno, &lnfname))
309 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
311 outfmt->output(segto, data, type, size, segment, wrt);
314 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
316 if (opx->segment != NO_SEG) {
317 uint64_t data = opx->offset;
318 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
320 uint8_t byte = opx->offset;
321 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
325 static bool jmp_match(int32_t segment, int64_t offset, int bits,
326 insn * ins, const struct itemplate *temp)
329 const uint8_t *code = temp->code;
332 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
336 if (optimizing < 0 && c == 0371)
339 isize = calcsize(segment, offset, bits, ins, temp);
341 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
342 /* Be optimistic in pass 1 */
345 if (ins->oprs[0].segment != segment)
348 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
349 return (isize >= -128 && isize <= 127); /* is it byte size? */
352 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
353 insn * instruction, struct ofmt *output, efunc error,
356 const struct itemplate *temp;
361 int64_t start = offset;
362 int64_t wsize; /* size for DB etc. */
364 errfunc = error; /* to pass to other functions */
366 outfmt = output; /* likewise */
367 list = listgen; /* and again */
369 wsize = idata_bytes(instruction->opcode);
375 int32_t t = instruction->times;
378 "instruction->times < 0 (%ld) in assemble()", t);
380 while (t--) { /* repeat TIMES times */
381 list_for_each(e, instruction->eops) {
382 if (e->type == EOT_DB_NUMBER) {
384 errfunc(ERR_NONFATAL,
385 "integer supplied to a DT, DO or DY"
388 out(offset, segment, &e->offset,
389 OUT_ADDRESS, wsize, e->segment, e->wrt);
392 } else if (e->type == EOT_DB_STRING ||
393 e->type == EOT_DB_STRING_FREE) {
396 out(offset, segment, e->stringval,
397 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
398 align = e->stringlen % wsize;
401 align = wsize - align;
402 out(offset, segment, zero_buffer,
403 OUT_RAWDATA, align, NO_SEG, NO_SEG);
405 offset += e->stringlen + align;
408 if (t > 0 && t == instruction->times - 1) {
410 * Dummy call to list->output to give the offset to the
413 list->output(offset, NULL, OUT_RAWDATA, 0);
414 list->uplevel(LIST_TIMES);
417 if (instruction->times > 1)
418 list->downlevel(LIST_TIMES);
419 return offset - start;
422 if (instruction->opcode == I_INCBIN) {
423 const char *fname = instruction->eops->stringval;
426 fp = fopen(fname, "rb");
428 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
430 } else if (fseek(fp, 0L, SEEK_END) < 0) {
431 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
434 static char buf[4096];
435 size_t t = instruction->times;
440 if (instruction->eops->next) {
441 base = instruction->eops->next->offset;
443 if (instruction->eops->next->next &&
444 len > (size_t)instruction->eops->next->next->offset)
445 len = (size_t)instruction->eops->next->next->offset;
448 * Dummy call to list->output to give the offset to the
451 list->output(offset, NULL, OUT_RAWDATA, 0);
452 list->uplevel(LIST_INCBIN);
456 fseek(fp, base, SEEK_SET);
460 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
463 * This shouldn't happen unless the file
464 * actually changes while we are reading
468 "`incbin': unexpected EOF while"
469 " reading file `%s'", fname);
470 t = 0; /* Try to exit cleanly */
473 out(offset, segment, buf, OUT_RAWDATA, m,
478 list->downlevel(LIST_INCBIN);
479 if (instruction->times > 1) {
481 * Dummy call to list->output to give the offset to the
484 list->output(offset, NULL, OUT_RAWDATA, 0);
485 list->uplevel(LIST_TIMES);
486 list->downlevel(LIST_TIMES);
489 return instruction->times * len;
491 return 0; /* if we're here, there's an error */
494 /* Check to see if we need an address-size prefix */
495 add_asp(instruction, bits);
497 m = find_match(&temp, instruction, segment, offset, bits);
501 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
502 itimes = instruction->times;
503 if (insn_size < 0) /* shouldn't be, on pass two */
504 error(ERR_PANIC, "errors made it through from pass one");
507 for (j = 0; j < MAXPREFIX; j++) {
509 switch (instruction->prefixes[j]) {
529 error(ERR_WARNING | ERR_PASS2,
530 "cs segment base generated, but will be ignored in 64-bit mode");
536 error(ERR_WARNING | ERR_PASS2,
537 "ds segment base generated, but will be ignored in 64-bit mode");
543 error(ERR_WARNING | ERR_PASS2,
544 "es segment base generated, but will be ignored in 64-bit mode");
556 error(ERR_WARNING | ERR_PASS2,
557 "ss segment base generated, but will be ignored in 64-bit mode");
564 "segr6 and segr7 cannot be used as prefixes");
569 "16-bit addressing is not supported "
571 } else if (bits != 16)
581 "64-bit addressing is only supported "
605 error(ERR_PANIC, "invalid instruction prefix");
608 out(offset, segment, &c, OUT_RAWDATA, 1,
613 insn_end = offset + insn_size;
614 gencode(segment, offset, bits, instruction,
617 if (itimes > 0 && itimes == instruction->times - 1) {
619 * Dummy call to list->output to give the offset to the
622 list->output(offset, NULL, OUT_RAWDATA, 0);
623 list->uplevel(LIST_TIMES);
626 if (instruction->times > 1)
627 list->downlevel(LIST_TIMES);
628 return offset - start;
632 case MERR_OPSIZEMISSING:
633 error(ERR_NONFATAL, "operation size not specified");
635 case MERR_OPSIZEMISMATCH:
636 error(ERR_NONFATAL, "mismatch in operand sizes");
639 error(ERR_NONFATAL, "no instruction for this cpu level");
642 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
647 "invalid combination of opcode and operands");
654 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
655 insn * instruction, efunc error)
657 const struct itemplate *temp;
660 errfunc = error; /* to pass to other functions */
663 if (instruction->opcode == I_none)
666 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
667 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
668 instruction->opcode == I_DT || instruction->opcode == I_DO ||
669 instruction->opcode == I_DY) {
671 int32_t isize, osize, wsize;
674 wsize = idata_bytes(instruction->opcode);
676 list_for_each(e, instruction->eops) {
680 if (e->type == EOT_DB_NUMBER) {
682 warn_overflow_const(e->offset, wsize);
683 } else if (e->type == EOT_DB_STRING ||
684 e->type == EOT_DB_STRING_FREE)
685 osize = e->stringlen;
687 align = (-osize) % wsize;
690 isize += osize + align;
692 return isize * instruction->times;
695 if (instruction->opcode == I_INCBIN) {
696 const char *fname = instruction->eops->stringval;
701 fp = fopen(fname, "rb");
703 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
705 else if (fseek(fp, 0L, SEEK_END) < 0)
706 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
710 if (instruction->eops->next) {
711 len -= instruction->eops->next->offset;
712 if (instruction->eops->next->next &&
713 len > (size_t)instruction->eops->next->next->offset) {
714 len = (size_t)instruction->eops->next->next->offset;
717 val = instruction->times * len;
724 /* Check to see if we need an address-size prefix */
725 add_asp(instruction, bits);
727 m = find_match(&temp, instruction, segment, offset, bits);
729 /* we've matched an instruction. */
733 isize = calcsize(segment, offset, bits, instruction, temp);
736 for (j = 0; j < MAXPREFIX; j++) {
737 switch (instruction->prefixes[j]) {
763 return isize * instruction->times;
765 return -1; /* didn't match any instruction */
769 static void bad_hle_warn(const insn * ins, uint8_t hleok)
771 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
772 enum whatwarn { w_none, w_lock, w_inval } ww;
773 static const enum whatwarn warn[2][4] =
775 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
776 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
780 n = (unsigned int)rep_pfx - P_XACQUIRE;
782 return; /* Not XACQUIRE/XRELEASE */
785 if (!is_class(MEMORY, ins->oprs[0].type))
786 ww = w_inval; /* HLE requires operand 0 to be memory */
793 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
794 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
795 "%s with this instruction requires lock",
796 prefix_name(rep_pfx));
801 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
802 "%s invalid with this instruction",
803 prefix_name(rep_pfx));
808 /* Common construct */
809 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
811 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
812 insn * ins, const struct itemplate *temp)
814 const uint8_t *codes = temp->code;
823 bool lockcheck = true;
825 ins->rex = 0; /* Ensure REX is reset */
826 eat = EA_SCALAR; /* Expect a scalar EA */
828 if (ins->prefixes[PPS_OSIZE] == P_O64)
831 (void)segment; /* Don't warn that this parameter is unused */
832 (void)offset; /* Don't warn that this parameter is unused */
836 op1 = (c & 3) + ((opex & 1) << 2);
837 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
838 opx = &ins->oprs[op1];
839 opex = 0; /* For the next iteration */
846 codes += c, length += c;
857 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
871 if (opx->type & (BITS16 | BITS32 | BITS64))
872 length += (opx->type & BITS16) ? 2 : 4;
874 length += (bits == 16) ? 2 : 4;
882 length += ins->addr_size >> 3;
890 length += 8; /* MOV reg64/imm */
898 if (opx->type & (BITS16 | BITS32 | BITS64))
899 length += (opx->type & BITS16) ? 2 : 4;
901 length += (bits == 16) ? 2 : 4;
928 ins->vexreg = regval(opx);
929 ins->vex_cm = *codes++;
930 ins->vex_wlp = *codes++;
936 ins->vex_cm = *codes++;
937 ins->vex_wlp = *codes++;
956 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
960 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
967 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
968 has_prefix(ins, PPS_ASIZE, P_A32))
977 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
981 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
983 ins->prefixes[PPS_OSIZE] = P_O16;
989 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
993 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
995 ins->prefixes[PPS_OSIZE] = P_O32;
1037 if (!ins->prefixes[PPS_REP])
1038 ins->prefixes[PPS_REP] = P_REP;
1042 if (!ins->prefixes[PPS_REP])
1043 ins->prefixes[PPS_REP] = P_REPNE;
1047 if (ins->oprs[0].segment != NO_SEG)
1048 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1049 " quantity of BSS space");
1051 length += ins->oprs[0].offset;
1055 if (!ins->prefixes[PPS_WAIT])
1056 ins->prefixes[PPS_WAIT] = P_WAIT;
1114 struct operand *opy = &ins->oprs[op2];
1116 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1119 /* pick rfield from operand b (opx) */
1120 rflags = regflag(opx);
1121 rfield = nasm_regvals[opx->basereg];
1126 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1127 rfield, rflags) != eat) {
1128 errfunc(ERR_NONFATAL, "invalid effective address");
1131 ins->rex |= ea_data.rex;
1132 length += ea_data.size;
1138 errfunc(ERR_PANIC, "internal instruction table corrupt"
1139 ": instruction code \\%o (0x%02X) given", c, c);
1144 ins->rex &= rex_mask;
1146 if (ins->rex & REX_NH) {
1147 if (ins->rex & REX_H) {
1148 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1151 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1154 if (ins->rex & REX_V) {
1155 int bad32 = REX_R|REX_W|REX_X|REX_B;
1157 if (ins->rex & REX_H) {
1158 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1161 switch (ins->vex_wlp & 060) {
1175 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1176 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1179 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1183 } else if (ins->rex & REX_REAL) {
1184 if (ins->rex & REX_H) {
1185 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1187 } else if (bits == 64) {
1189 } else if ((ins->rex & REX_L) &&
1190 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1193 assert_no_prefix(ins, PPS_LOCK);
1194 lockcheck = false; /* Already errored, no need for warning */
1197 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1202 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1203 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1204 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1205 "instruction is not lockable");
1208 bad_hle_warn(ins, hleok);
1213 #define EMIT_REX() \
1214 if (!(ins->rex & REX_V) && (ins->rex & REX_REAL) && (bits == 64)) { \
1215 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1216 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1221 static void gencode(int32_t segment, int64_t offset, int bits,
1222 insn * ins, const struct itemplate *temp,
1225 static const char condval[] = { /* conditional opcodes */
1226 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1227 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1228 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1235 struct operand *opx;
1236 const uint8_t *codes = temp->code;
1238 enum ea_type eat = EA_SCALAR;
1242 op1 = (c & 3) + ((opex & 1) << 2);
1243 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1244 opx = &ins->oprs[op1];
1245 opex = 0; /* For the next iteration */
1253 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1266 bytes[0] = *codes++ + (regval(opx) & 7);
1267 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1272 if (opx->offset < -256 || opx->offset > 255) {
1273 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1274 "byte value exceeds bounds");
1276 out_imm8(offset, segment, opx);
1281 if (opx->offset < 0 || opx->offset > 255)
1282 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1283 "unsigned byte value exceeds bounds");
1284 out_imm8(offset, segment, opx);
1289 warn_overflow_opd(opx, 2);
1291 out(offset, segment, &data, OUT_ADDRESS, 2,
1292 opx->segment, opx->wrt);
1297 if (opx->type & (BITS16 | BITS32))
1298 size = (opx->type & BITS16) ? 2 : 4;
1300 size = (bits == 16) ? 2 : 4;
1301 warn_overflow_opd(opx, size);
1303 out(offset, segment, &data, OUT_ADDRESS, size,
1304 opx->segment, opx->wrt);
1309 warn_overflow_opd(opx, 4);
1311 out(offset, segment, &data, OUT_ADDRESS, 4,
1312 opx->segment, opx->wrt);
1318 size = ins->addr_size >> 3;
1319 warn_overflow_opd(opx, size);
1320 out(offset, segment, &data, OUT_ADDRESS, size,
1321 opx->segment, opx->wrt);
1326 if (opx->segment != segment) {
1328 out(offset, segment, &data,
1329 OUT_REL1ADR, insn_end - offset,
1330 opx->segment, opx->wrt);
1332 data = opx->offset - insn_end;
1333 if (data > 127 || data < -128)
1334 errfunc(ERR_NONFATAL, "short jump is out of range");
1335 out(offset, segment, &data,
1336 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1342 data = (int64_t)opx->offset;
1343 out(offset, segment, &data, OUT_ADDRESS, 8,
1344 opx->segment, opx->wrt);
1349 if (opx->segment != segment) {
1351 out(offset, segment, &data,
1352 OUT_REL2ADR, insn_end - offset,
1353 opx->segment, opx->wrt);
1355 data = opx->offset - insn_end;
1356 out(offset, segment, &data,
1357 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1363 if (opx->type & (BITS16 | BITS32 | BITS64))
1364 size = (opx->type & BITS16) ? 2 : 4;
1366 size = (bits == 16) ? 2 : 4;
1367 if (opx->segment != segment) {
1369 out(offset, segment, &data,
1370 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1371 insn_end - offset, opx->segment, opx->wrt);
1373 data = opx->offset - insn_end;
1374 out(offset, segment, &data,
1375 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1381 if (opx->segment != segment) {
1383 out(offset, segment, &data,
1384 OUT_REL4ADR, insn_end - offset,
1385 opx->segment, opx->wrt);
1387 data = opx->offset - insn_end;
1388 out(offset, segment, &data,
1389 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1395 if (opx->segment == NO_SEG)
1396 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1399 out(offset, segment, &data, OUT_ADDRESS, 2,
1400 outfmt->segbase(1 + opx->segment),
1407 opx = &ins->oprs[c >> 3];
1408 bytes[0] = nasm_regvals[opx->basereg] << 4;
1409 opx = &ins->oprs[c & 7];
1410 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1411 errfunc(ERR_NONFATAL,
1412 "non-absolute expression not permitted as argument %d",
1415 if (opx->offset & ~15) {
1416 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1417 "four-bit argument exceeds bounds");
1419 bytes[0] |= opx->offset & 15;
1421 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1427 opx = &ins->oprs[c >> 4];
1428 bytes[0] = nasm_regvals[opx->basereg] << 4;
1430 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1435 bytes[0] = nasm_regvals[opx->basereg] << 4;
1436 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1442 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1443 (int32_t)data != (int64_t)data) {
1444 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1445 "signed dword immediate exceeds bounds");
1447 out(offset, segment, &data, OUT_ADDRESS, 4,
1448 opx->segment, opx->wrt);
1455 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1456 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1457 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1458 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1459 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1460 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1464 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1465 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1466 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1481 if (ins->rex & REX_W)
1483 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1485 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1490 um = (uint64_t)2 << (s-1);
1493 if (uv > 127 && uv < (uint64_t)-128 &&
1494 (uv < um-128 || uv > um-1)) {
1495 /* If this wasn't explicitly byte-sized, warn as though we
1496 * had fallen through to the imm16/32/64 case.
1498 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1499 "%s value exceeds bounds",
1500 (opx->type & BITS8) ? "signed byte" :
1505 if (opx->segment != NO_SEG) {
1507 out(offset, segment, &data, OUT_ADDRESS, 1,
1508 opx->segment, opx->wrt);
1511 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1522 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1524 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1531 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1533 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1568 *bytes = *codes++ ^ condval[ins->condition];
1569 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1578 *bytes = c - 0332 + 0xF2;
1579 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1584 if (ins->rex & REX_R) {
1586 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1589 ins->rex &= ~(REX_L|REX_R);
1600 if (ins->oprs[0].segment != NO_SEG)
1601 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1603 int64_t size = ins->oprs[0].offset;
1605 out(offset, segment, NULL,
1606 OUT_RESERVE, size, NO_SEG, NO_SEG);
1617 switch (ins->oprs[0].basereg) {
1632 "bizarre 8086 segment register received");
1634 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1641 switch (ins->oprs[0].basereg) {
1650 "bizarre 386 segment register received");
1652 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1661 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1667 bytes[0] = c - 0362 + 0xf2;
1668 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1678 *bytes = c - 0366 + 0x66;
1679 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1688 *bytes = bits == 16 ? 3 : 5;
1689 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1719 struct operand *opy = &ins->oprs[op2];
1722 /* pick rfield from operand b (opx) */
1723 rflags = regflag(opx);
1724 rfield = nasm_regvals[opx->basereg];
1726 /* rfield is constant */
1731 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1732 rfield, rflags) != eat)
1733 errfunc(ERR_NONFATAL, "invalid effective address");
1736 *p++ = ea_data.modrm;
1737 if (ea_data.sib_present)
1741 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1744 * Make sure the address gets the right offset in case
1745 * the line breaks in the .lst file (BR 1197827)
1750 switch (ea_data.bytes) {
1760 if (opy->segment == segment) {
1762 if (overflow_signed(data, ea_data.bytes))
1763 warn_overflow(ERR_PASS2, ea_data.bytes);
1764 out(offset, segment, &data, OUT_ADDRESS,
1765 ea_data.bytes, NO_SEG, NO_SEG);
1767 /* overflow check in output/linker? */
1768 out(offset, segment, &data, OUT_REL4ADR,
1769 insn_end - offset, opy->segment, opy->wrt);
1772 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1773 signed_bits(opy->offset, ins->addr_size) !=
1774 signed_bits(opy->offset, ea_data.bytes * 8))
1775 warn_overflow(ERR_PASS2, ea_data.bytes);
1777 out(offset, segment, &data, OUT_ADDRESS,
1778 ea_data.bytes, opy->segment, opy->wrt);
1784 "Invalid amount of bytes (%d) for offset?!",
1793 errfunc(ERR_PANIC, "internal instruction table corrupt"
1794 ": instruction code \\%o (0x%02X) given", c, c);
1800 static opflags_t regflag(const operand * o)
1802 if (!is_register(o->basereg))
1803 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1804 return nasm_reg_flags[o->basereg];
1807 static int32_t regval(const operand * o)
1809 if (!is_register(o->basereg))
1810 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1811 return nasm_regvals[o->basereg];
1814 static int op_rexflags(const operand * o, int mask)
1819 if (!is_register(o->basereg))
1820 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1822 flags = nasm_reg_flags[o->basereg];
1823 val = nasm_regvals[o->basereg];
1825 return rexflags(val, flags, mask);
1828 static int rexflags(int val, opflags_t flags, int mask)
1833 rex |= REX_B|REX_X|REX_R;
1836 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1838 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1844 static enum match_result find_match(const struct itemplate **tempp,
1846 int32_t segment, int64_t offset, int bits)
1848 const struct itemplate *temp;
1849 enum match_result m, merr;
1850 opflags_t xsizeflags[MAX_OPERANDS];
1851 bool opsizemissing = false;
1854 for (i = 0; i < instruction->operands; i++)
1855 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1857 merr = MERR_INVALOP;
1859 for (temp = nasm_instructions[instruction->opcode];
1860 temp->opcode != I_none; temp++) {
1861 m = matches(temp, instruction, bits);
1862 if (m == MOK_JUMP) {
1863 if (jmp_match(segment, offset, bits, instruction, temp))
1867 } else if (m == MERR_OPSIZEMISSING &&
1868 (temp->flags & IF_SMASK) != IF_SX) {
1870 * Missing operand size and a candidate for fuzzy matching...
1872 for (i = 0; i < temp->operands; i++) {
1873 if ((temp->opd[i] & SAME_AS) == 0)
1874 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1876 opsizemissing = true;
1880 if (merr == MOK_GOOD)
1884 /* No match, but see if we can get a fuzzy operand size match... */
1888 for (i = 0; i < instruction->operands; i++) {
1890 * We ignore extrinsic operand sizes on registers, so we should
1891 * never try to fuzzy-match on them. This also resolves the case
1892 * when we have e.g. "xmmrm128" in two different positions.
1894 if (is_class(REGISTER, instruction->oprs[i].type))
1897 /* This tests if xsizeflags[i] has more than one bit set */
1898 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1899 goto done; /* No luck */
1901 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1904 /* Try matching again... */
1905 for (temp = nasm_instructions[instruction->opcode];
1906 temp->opcode != I_none; temp++) {
1907 m = matches(temp, instruction, bits);
1908 if (m == MOK_JUMP) {
1909 if (jmp_match(segment, offset, bits, instruction, temp))
1916 if (merr == MOK_GOOD)
1925 static enum match_result matches(const struct itemplate *itemp,
1926 insn *instruction, int bits)
1928 opflags_t size[MAX_OPERANDS], asize;
1929 bool opsizemissing = false;
1935 if (itemp->opcode != instruction->opcode)
1936 return MERR_INVALOP;
1939 * Count the operands
1941 if (itemp->operands != instruction->operands)
1942 return MERR_INVALOP;
1947 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
1948 return MERR_INVALOP;
1951 * Check that no spurious colons or TOs are present
1953 for (i = 0; i < itemp->operands; i++)
1954 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1955 return MERR_INVALOP;
1958 * Process size flags
1960 switch (itemp->flags & IF_SMASK) {
2000 if (itemp->flags & IF_ARMASK) {
2001 /* S- flags only apply to a specific operand */
2002 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2003 memset(size, 0, sizeof size);
2006 /* S- flags apply to all operands */
2007 for (i = 0; i < MAX_OPERANDS; i++)
2012 * Check that the operand flags all match up,
2013 * it's a bit tricky so lets be verbose:
2015 * 1) Find out the size of operand. If instruction
2016 * doesn't have one specified -- we're trying to
2017 * guess it either from template (IF_S* flag) or
2020 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2021 * (ie the same operand as was specified somewhere in template, and
2022 * this referred operand index is being achieved via ~SAME_AS)
2023 * we are to be sure that both registers (in template and instruction)
2026 * 3) If template operand do not match the instruction OR
2027 * template has an operand size specified AND this size differ
2028 * from which instruction has (perhaps we got it from code bits)
2030 * a) Check that only size of instruction and operand is differ
2031 * other characteristics do match
2032 * b) Perhaps it's a register specified in instruction so
2033 * for such a case we just mark that operand as "size
2034 * missing" and this will turn on fuzzy operand size
2035 * logic facility (handled by a caller)
2037 for (i = 0; i < itemp->operands; i++) {
2038 opflags_t type = instruction->oprs[i].type;
2039 if (!(type & SIZE_MASK))
2042 if (itemp->opd[i] & SAME_AS) {
2043 int j = itemp->opd[i] & ~SAME_AS;
2044 if (type != instruction->oprs[j].type ||
2045 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2046 return MERR_INVALOP;
2047 } else if (itemp->opd[i] & ~type & ~SIZE_MASK) {
2048 return MERR_INVALOP;
2049 } else if ((itemp->opd[i] & SIZE_MASK) &&
2050 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2051 if (type & SIZE_MASK) {
2052 return MERR_INVALOP;
2053 } else if (!is_class(REGISTER, type)) {
2055 * Note: we don't honor extrinsic operand sizes for registers,
2056 * so "missing operand size" for a register should be
2057 * considered a wildcard match rather than an error.
2059 opsizemissing = true;
2065 return MERR_OPSIZEMISSING;
2068 * Check operand sizes
2070 if (itemp->flags & (IF_SM | IF_SM2)) {
2071 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2072 for (i = 0; i < oprs; i++) {
2073 asize = itemp->opd[i] & SIZE_MASK;
2075 for (i = 0; i < oprs; i++)
2081 oprs = itemp->operands;
2084 for (i = 0; i < itemp->operands; i++) {
2085 if (!(itemp->opd[i] & SIZE_MASK) &&
2086 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2087 return MERR_OPSIZEMISMATCH;
2091 * Check template is okay at the set cpu level
2093 if (((itemp->flags & IF_PLEVEL) > cpu))
2097 * Verify the appropriate long mode flag.
2099 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2100 return MERR_BADMODE;
2103 * If we have a HLE prefix, look for the NOHLE flag
2105 if ((itemp->flags & IF_NOHLE) &&
2106 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2107 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2111 * Check if special handling needed for Jumps
2113 if ((itemp->code[0] & ~1) == 0370)
2119 static enum ea_type process_ea(operand *input, ea *output, int bits,
2120 int addrbits, int rfield, opflags_t rflags)
2122 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2124 output->type = EA_SCALAR;
2125 output->rip = false;
2127 /* REX flags for the rfield operand */
2128 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2130 if (is_class(REGISTER, input->type)) {
2132 * It's a direct register.
2136 if (!is_register(input->basereg))
2141 if (!is_class(REG_EA, f))
2144 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2145 output->sib_present = false; /* no SIB necessary */
2146 output->bytes = 0; /* no offset necessary either */
2147 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2150 * It's a memory reference.
2152 if (input->basereg == -1 &&
2153 (input->indexreg == -1 || input->scale == 0)) {
2155 * It's a pure offset.
2157 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2158 input->segment == NO_SEG) {
2159 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2160 input->type &= ~IP_REL;
2161 input->type |= MEMORY;
2164 if (input->eaflags & EAF_BYTEOFFS ||
2165 (input->eaflags & EAF_WORDOFFS &&
2166 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2167 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2170 if (bits == 64 && (~input->type & IP_REL)) {
2171 output->sib_present = true;
2172 output->sib = GEN_SIB(0, 4, 5);
2174 output->modrm = GEN_MODRM(0, rfield, 4);
2175 output->rip = false;
2177 output->sib_present = false;
2178 output->bytes = (addrbits != 16 ? 4 : 2);
2179 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2180 output->rip = bits == 64;
2184 * It's an indirection.
2186 int i = input->indexreg, b = input->basereg, s = input->scale;
2187 int32_t seg = input->segment;
2188 int hb = input->hintbase, ht = input->hinttype;
2189 int t, it, bt; /* register numbers */
2190 opflags_t x, ix, bx; /* register flags */
2193 i = -1; /* make this easy, at least */
2195 if (is_register(i)) {
2196 it = nasm_regvals[i];
2197 ix = nasm_reg_flags[i];
2203 if (is_register(b)) {
2204 bt = nasm_regvals[b];
2205 bx = nasm_reg_flags[b];
2211 /* if either one are a vector register... */
2212 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2213 opflags_t sok = BITS32 | BITS64;
2214 int32_t o = input->offset;
2215 int mod, scale, index, base;
2218 * For a vector SIB, one has to be a vector and the other,
2219 * if present, a GPR. The vector must be the index operand.
2221 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2227 t = bt, bt = it, it = t;
2228 x = bx, bx = ix, ix = x;
2234 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2241 * While we're here, ensure the user didn't specify
2244 if (input->disp_size == 16 || input->disp_size == 64)
2247 if (addrbits == 16 ||
2248 (addrbits == 32 && !(sok & BITS32)) ||
2249 (addrbits == 64 && !(sok & BITS64)))
2252 output->type = (ix & YMMREG & ~REG_EA)
2253 ? EA_YMMVSIB : EA_XMMVSIB;
2255 output->rex |= rexflags(it, ix, REX_X);
2256 output->rex |= rexflags(bt, bx, REX_B);
2258 index = it & 7; /* it is known to be != -1 */
2273 default: /* then what the smeg is it? */
2274 goto err; /* panic */
2282 if (base != REG_NUM_EBP && o == 0 &&
2283 seg == NO_SEG && !forw_ref &&
2284 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2286 else if (input->eaflags & EAF_BYTEOFFS ||
2287 (o >= -128 && o <= 127 &&
2288 seg == NO_SEG && !forw_ref &&
2289 !(input->eaflags & EAF_WORDOFFS)))
2295 output->sib_present = true;
2296 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2297 output->modrm = GEN_MODRM(mod, rfield, 4);
2298 output->sib = GEN_SIB(scale, index, base);
2299 } else if ((ix|bx) & (BITS32|BITS64)) {
2301 * it must be a 32/64-bit memory reference. Firstly we have
2302 * to check that all registers involved are type E/Rxx.
2304 opflags_t sok = BITS32 | BITS64;
2305 int32_t o = input->offset;
2308 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2316 goto err; /* Invalid register */
2317 if (~sok & bx & SIZE_MASK)
2318 goto err; /* Invalid size */
2323 * While we're here, ensure the user didn't specify
2326 if (input->disp_size == 16 || input->disp_size == 64)
2329 if (addrbits == 16 ||
2330 (addrbits == 32 && !(sok & BITS32)) ||
2331 (addrbits == 64 && !(sok & BITS64)))
2334 /* now reorganize base/index */
2335 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2336 ((hb == b && ht == EAH_NOTBASE) ||
2337 (hb == i && ht == EAH_MAKEBASE))) {
2338 /* swap if hints say so */
2339 t = bt, bt = it, it = t;
2340 x = bx, bx = ix, ix = x;
2342 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2343 bt = -1, bx = 0, s++;
2344 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2345 /* make single reg base, unless hint */
2346 bt = it, bx = ix, it = -1, ix = 0;
2348 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2349 s == 3 || s == 5 || s == 9) && bt == -1)
2350 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2351 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2352 (input->eaflags & EAF_TIMESTWO))
2353 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2354 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2355 if (s == 1 && it == REG_NUM_ESP) {
2356 /* swap ESP into base if scale is 1 */
2357 t = it, it = bt, bt = t;
2358 x = ix, ix = bx, bx = x;
2360 if (it == REG_NUM_ESP ||
2361 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2362 goto err; /* wrong, for various reasons */
2364 output->rex |= rexflags(it, ix, REX_X);
2365 output->rex |= rexflags(bt, bx, REX_B);
2367 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2376 if (rm != REG_NUM_EBP && o == 0 &&
2377 seg == NO_SEG && !forw_ref &&
2378 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2380 else if (input->eaflags & EAF_BYTEOFFS ||
2381 (o >= -128 && o <= 127 &&
2382 seg == NO_SEG && !forw_ref &&
2383 !(input->eaflags & EAF_WORDOFFS)))
2389 output->sib_present = false;
2390 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2391 output->modrm = GEN_MODRM(mod, rfield, rm);
2394 int mod, scale, index, base;
2414 default: /* then what the smeg is it? */
2415 goto err; /* panic */
2423 if (base != REG_NUM_EBP && o == 0 &&
2424 seg == NO_SEG && !forw_ref &&
2425 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2427 else if (input->eaflags & EAF_BYTEOFFS ||
2428 (o >= -128 && o <= 127 &&
2429 seg == NO_SEG && !forw_ref &&
2430 !(input->eaflags & EAF_WORDOFFS)))
2436 output->sib_present = true;
2437 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2438 output->modrm = GEN_MODRM(mod, rfield, 4);
2439 output->sib = GEN_SIB(scale, index, base);
2441 } else { /* it's 16-bit */
2443 int16_t o = input->offset;
2445 /* check for 64-bit long mode */
2449 /* check all registers are BX, BP, SI or DI */
2450 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2451 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2454 /* ensure the user didn't specify DWORD/QWORD */
2455 if (input->disp_size == 32 || input->disp_size == 64)
2458 if (s != 1 && i != -1)
2459 goto err; /* no can do, in 16-bit EA */
2460 if (b == -1 && i != -1) {
2465 if ((b == R_SI || b == R_DI) && i != -1) {
2470 /* have BX/BP as base, SI/DI index */
2472 goto err; /* shouldn't ever happen, in theory */
2473 if (i != -1 && b != -1 &&
2474 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2475 goto err; /* invalid combinations */
2476 if (b == -1) /* pure offset: handled above */
2477 goto err; /* so if it gets to here, panic! */
2481 switch (i * 256 + b) {
2482 case R_SI * 256 + R_BX:
2485 case R_DI * 256 + R_BX:
2488 case R_SI * 256 + R_BP:
2491 case R_DI * 256 + R_BP:
2509 if (rm == -1) /* can't happen, in theory */
2510 goto err; /* so panic if it does */
2512 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2513 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2515 else if (input->eaflags & EAF_BYTEOFFS ||
2516 (o >= -128 && o <= 127 && seg == NO_SEG &&
2517 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2522 output->sib_present = false; /* no SIB - it's 16-bit */
2523 output->bytes = mod; /* bytes of offset needed */
2524 output->modrm = GEN_MODRM(mod, rfield, rm);
2529 output->size = 1 + output->sib_present + output->bytes;
2530 return output->type;
2533 return output->type = EA_INVALID;
2536 static void add_asp(insn *ins, int addrbits)
2541 valid = (addrbits == 64) ? 64|32 : 32|16;
2543 switch (ins->prefixes[PPS_ASIZE]) {
2554 valid &= (addrbits == 32) ? 16 : 32;
2560 for (j = 0; j < ins->operands; j++) {
2561 if (is_class(MEMORY, ins->oprs[j].type)) {
2564 /* Verify as Register */
2565 if (!is_register(ins->oprs[j].indexreg))
2568 i = nasm_reg_flags[ins->oprs[j].indexreg];
2570 /* Verify as Register */
2571 if (!is_register(ins->oprs[j].basereg))
2574 b = nasm_reg_flags[ins->oprs[j].basereg];
2576 if (ins->oprs[j].scale == 0)
2580 int ds = ins->oprs[j].disp_size;
2581 if ((addrbits != 64 && ds > 8) ||
2582 (addrbits == 64 && ds == 16))
2602 if (valid & addrbits) {
2603 ins->addr_size = addrbits;
2604 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2605 /* Add an address size prefix */
2606 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2607 ins->addr_size = (addrbits == 32) ? 16 : 32;
2610 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2611 ins->addr_size = addrbits; /* Error recovery */
2614 defdisp = ins->addr_size == 16 ? 16 : 32;
2616 for (j = 0; j < ins->operands; j++) {
2617 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2618 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2620 * mem_offs sizes must match the address size; if not,
2621 * strip the MEM_OFFS bit and match only EA instructions
2623 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);