1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
82 * [l0] ll = 0 (.128, .lz)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \372 - BND prefix (0xF2 byte) used for preserving bnd0..3
166 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
167 * used for conditional jump over longer jump
168 * \374 - this instruction takes an XMM VSIB memory EA
169 * \375 - this instruction takes an YMM VSIB memory EA
170 * \376 - this instruction takes an ZMM VSIB memory EA
173 #include "compiler.h"
177 #include <inttypes.h>
181 #include "assemble.h"
187 * Matching errors. These should be sorted so that more specific
188 * errors come later in the sequence.
199 * Matching success; the conditional ones first
201 MOK_JUMP, /* Matching OK but needs jmp_match() */
202 MOK_GOOD /* Matching unconditionally OK */
206 enum ea_type type; /* what kind of EA is this? */
207 int sib_present; /* is a SIB byte necessary? */
208 int bytes; /* # of bytes of offset needed */
209 int size; /* lazy - this is sib+bytes+1 */
210 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
211 int8_t disp8; /* compressed displacement for EVEX */
214 #define GEN_SIB(scale, index, base) \
215 (((scale) << 6) | ((index) << 3) | ((base)))
217 #define GEN_MODRM(mod, reg, rm) \
218 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
220 static iflags_t cpu; /* cpu level received from nasm.c */
221 static efunc errfunc;
222 static struct ofmt *outfmt;
223 static ListGen *list;
225 static int64_t calcsize(int32_t, int64_t, int, insn *,
226 const struct itemplate *);
227 static void gencode(int32_t segment, int64_t offset, int bits,
228 insn * ins, const struct itemplate *temp,
230 static enum match_result find_match(const struct itemplate **tempp,
232 int32_t segment, int64_t offset, int bits);
233 static enum match_result matches(const struct itemplate *, insn *, int bits);
234 static opflags_t regflag(const operand *);
235 static int32_t regval(const operand *);
236 static int rexflags(int, opflags_t, int);
237 static int op_rexflags(const operand *, int);
238 static int op_evexflags(const operand *, int, uint8_t);
239 static void add_asp(insn *, int);
241 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
243 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
245 return ins->prefixes[pos] == prefix;
248 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
250 if (ins->prefixes[pos])
251 errfunc(ERR_NONFATAL, "invalid %s prefix",
252 prefix_name(ins->prefixes[pos]));
255 static const char *size_name(int size)
279 static void warn_overflow(int pass, int size)
281 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
282 "%s data exceeds bounds", size_name(size));
285 static void warn_overflow_const(int64_t data, int size)
287 if (overflow_general(data, size))
288 warn_overflow(ERR_PASS1, size);
291 static void warn_overflow_opd(const struct operand *o, int size)
293 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
294 if (overflow_general(o->offset, size))
295 warn_overflow(ERR_PASS2, size);
300 * This routine wrappers the real output format's output routine,
301 * in order to pass a copy of the data off to the listing file
302 * generator at the same time.
304 static void out(int64_t offset, int32_t segto, const void *data,
305 enum out_type type, uint64_t size,
306 int32_t segment, int32_t wrt)
308 static int32_t lineno = 0; /* static!!! */
309 static char *lnfname = NULL;
312 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
314 * This is a non-relocated address, and we're going to
315 * convert it into RAWDATA format.
320 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
324 WRITEADDR(q, *(int64_t *)data, size);
329 list->output(offset, data, type, size);
332 * this call to src_get determines when we call the
333 * debug-format-specific "linenum" function
334 * it updates lineno and lnfname to the current values
335 * returning 0 if "same as last time", -2 if lnfname
336 * changed, and the amount by which lineno changed,
337 * if it did. thus, these variables must be static
340 if (src_get(&lineno, &lnfname))
341 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
343 outfmt->output(segto, data, type, size, segment, wrt);
346 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
348 if (opx->segment != NO_SEG) {
349 uint64_t data = opx->offset;
350 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
352 uint8_t byte = opx->offset;
353 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
357 static bool jmp_match(int32_t segment, int64_t offset, int bits,
358 insn * ins, const struct itemplate *temp)
361 const uint8_t *code = temp->code;
364 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
368 if (optimizing < 0 && c == 0371)
371 isize = calcsize(segment, offset, bits, ins, temp);
373 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
374 /* Be optimistic in pass 1 */
377 if (ins->oprs[0].segment != segment)
380 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
381 return (isize >= -128 && isize <= 127); /* is it byte size? */
384 int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp,
385 insn * instruction, struct ofmt *output, efunc error,
388 const struct itemplate *temp;
393 int64_t start = offset;
394 int64_t wsize; /* size for DB etc. */
396 errfunc = error; /* to pass to other functions */
398 outfmt = output; /* likewise */
399 list = listgen; /* and again */
401 wsize = idata_bytes(instruction->opcode);
407 int32_t t = instruction->times;
410 "instruction->times < 0 (%ld) in assemble()", t);
412 while (t--) { /* repeat TIMES times */
413 list_for_each(e, instruction->eops) {
414 if (e->type == EOT_DB_NUMBER) {
416 errfunc(ERR_NONFATAL,
417 "integer supplied to a DT, DO or DY"
420 out(offset, segment, &e->offset,
421 OUT_ADDRESS, wsize, e->segment, e->wrt);
424 } else if (e->type == EOT_DB_STRING ||
425 e->type == EOT_DB_STRING_FREE) {
428 out(offset, segment, e->stringval,
429 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
430 align = e->stringlen % wsize;
433 align = wsize - align;
434 out(offset, segment, zero_buffer,
435 OUT_RAWDATA, align, NO_SEG, NO_SEG);
437 offset += e->stringlen + align;
440 if (t > 0 && t == instruction->times - 1) {
442 * Dummy call to list->output to give the offset to the
445 list->output(offset, NULL, OUT_RAWDATA, 0);
446 list->uplevel(LIST_TIMES);
449 if (instruction->times > 1)
450 list->downlevel(LIST_TIMES);
451 return offset - start;
454 if (instruction->opcode == I_INCBIN) {
455 const char *fname = instruction->eops->stringval;
458 fp = fopen(fname, "rb");
460 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
462 } else if (fseek(fp, 0L, SEEK_END) < 0) {
463 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
467 static char buf[4096];
468 size_t t = instruction->times;
473 if (instruction->eops->next) {
474 base = instruction->eops->next->offset;
476 if (instruction->eops->next->next &&
477 len > (size_t)instruction->eops->next->next->offset)
478 len = (size_t)instruction->eops->next->next->offset;
481 * Dummy call to list->output to give the offset to the
484 list->output(offset, NULL, OUT_RAWDATA, 0);
485 list->uplevel(LIST_INCBIN);
489 fseek(fp, base, SEEK_SET);
493 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
496 * This shouldn't happen unless the file
497 * actually changes while we are reading
501 "`incbin': unexpected EOF while"
502 " reading file `%s'", fname);
503 t = 0; /* Try to exit cleanly */
506 out(offset, segment, buf, OUT_RAWDATA, m,
511 list->downlevel(LIST_INCBIN);
512 if (instruction->times > 1) {
514 * Dummy call to list->output to give the offset to the
517 list->output(offset, NULL, OUT_RAWDATA, 0);
518 list->uplevel(LIST_TIMES);
519 list->downlevel(LIST_TIMES);
522 return instruction->times * len;
524 return 0; /* if we're here, there's an error */
527 /* Check to see if we need an address-size prefix */
528 add_asp(instruction, bits);
530 m = find_match(&temp, instruction, segment, offset, bits);
534 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
535 itimes = instruction->times;
536 if (insn_size < 0) /* shouldn't be, on pass two */
537 error(ERR_PANIC, "errors made it through from pass one");
540 for (j = 0; j < MAXPREFIX; j++) {
542 switch (instruction->prefixes[j]) {
563 error(ERR_WARNING | ERR_PASS2,
564 "cs segment base generated, but will be ignored in 64-bit mode");
570 error(ERR_WARNING | ERR_PASS2,
571 "ds segment base generated, but will be ignored in 64-bit mode");
577 error(ERR_WARNING | ERR_PASS2,
578 "es segment base generated, but will be ignored in 64-bit mode");
590 error(ERR_WARNING | ERR_PASS2,
591 "ss segment base generated, but will be ignored in 64-bit mode");
598 "segr6 and segr7 cannot be used as prefixes");
603 "16-bit addressing is not supported "
605 } else if (bits != 16)
615 "64-bit addressing is only supported "
639 error(ERR_PANIC, "invalid instruction prefix");
642 out(offset, segment, &c, OUT_RAWDATA, 1,
647 insn_end = offset + insn_size;
648 gencode(segment, offset, bits, instruction,
651 if (itimes > 0 && itimes == instruction->times - 1) {
653 * Dummy call to list->output to give the offset to the
656 list->output(offset, NULL, OUT_RAWDATA, 0);
657 list->uplevel(LIST_TIMES);
660 if (instruction->times > 1)
661 list->downlevel(LIST_TIMES);
662 return offset - start;
666 case MERR_OPSIZEMISSING:
667 error(ERR_NONFATAL, "operation size not specified");
669 case MERR_OPSIZEMISMATCH:
670 error(ERR_NONFATAL, "mismatch in operand sizes");
673 error(ERR_NONFATAL, "no instruction for this cpu level");
676 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
681 "invalid combination of opcode and operands");
688 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp,
689 insn * instruction, efunc error)
691 const struct itemplate *temp;
694 errfunc = error; /* to pass to other functions */
697 if (instruction->opcode == I_none)
700 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
701 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
702 instruction->opcode == I_DT || instruction->opcode == I_DO ||
703 instruction->opcode == I_DY) {
705 int32_t isize, osize, wsize;
708 wsize = idata_bytes(instruction->opcode);
710 list_for_each(e, instruction->eops) {
714 if (e->type == EOT_DB_NUMBER) {
716 warn_overflow_const(e->offset, wsize);
717 } else if (e->type == EOT_DB_STRING ||
718 e->type == EOT_DB_STRING_FREE)
719 osize = e->stringlen;
721 align = (-osize) % wsize;
724 isize += osize + align;
726 return isize * instruction->times;
729 if (instruction->opcode == I_INCBIN) {
730 const char *fname = instruction->eops->stringval;
735 fp = fopen(fname, "rb");
737 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
739 else if (fseek(fp, 0L, SEEK_END) < 0)
740 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
744 if (instruction->eops->next) {
745 len -= instruction->eops->next->offset;
746 if (instruction->eops->next->next &&
747 len > (size_t)instruction->eops->next->next->offset) {
748 len = (size_t)instruction->eops->next->next->offset;
751 val = instruction->times * len;
758 /* Check to see if we need an address-size prefix */
759 add_asp(instruction, bits);
761 m = find_match(&temp, instruction, segment, offset, bits);
763 /* we've matched an instruction. */
767 isize = calcsize(segment, offset, bits, instruction, temp);
770 for (j = 0; j < MAXPREFIX; j++) {
771 switch (instruction->prefixes[j]) {
797 return isize * instruction->times;
799 return -1; /* didn't match any instruction */
803 static void bad_hle_warn(const insn * ins, uint8_t hleok)
805 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
806 enum whatwarn { w_none, w_lock, w_inval } ww;
807 static const enum whatwarn warn[2][4] =
809 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
810 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
814 n = (unsigned int)rep_pfx - P_XACQUIRE;
816 return; /* Not XACQUIRE/XRELEASE */
819 if (!is_class(MEMORY, ins->oprs[0].type))
820 ww = w_inval; /* HLE requires operand 0 to be memory */
827 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
828 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
829 "%s with this instruction requires lock",
830 prefix_name(rep_pfx));
835 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
836 "%s invalid with this instruction",
837 prefix_name(rep_pfx));
842 /* Common construct */
843 #define case3(x) case (x): case (x)+1: case (x)+2
844 #define case4(x) case3(x): case (x)+3
846 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
847 insn * ins, const struct itemplate *temp)
849 const uint8_t *codes = temp->code;
858 bool lockcheck = true;
859 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
861 ins->rex = 0; /* Ensure REX is reset */
862 eat = EA_SCALAR; /* Expect a scalar EA */
863 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
865 if (ins->prefixes[PPS_OSIZE] == P_O64)
868 (void)segment; /* Don't warn that this parameter is unused */
869 (void)offset; /* Don't warn that this parameter is unused */
873 op1 = (c & 3) + ((opex & 1) << 2);
874 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
875 opx = &ins->oprs[op1];
876 opex = 0; /* For the next iteration */
880 codes += c, length += c;
889 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
894 /* this is an index reg of MIB operand */
895 mib_index = opx->basereg;
908 if (opx->type & (BITS16 | BITS32 | BITS64))
909 length += (opx->type & BITS16) ? 2 : 4;
911 length += (bits == 16) ? 2 : 4;
919 length += ins->addr_size >> 3;
927 length += 8; /* MOV reg64/imm */
935 if (opx->type & (BITS16 | BITS32 | BITS64))
936 length += (opx->type & BITS16) ? 2 : 4;
938 length += (bits == 16) ? 2 : 4;
961 ins->vexreg = regval(opx);
962 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
963 ins->vex_cm = *codes++;
964 ins->vex_wlp = *codes++;
965 ins->evex_tuple = (*codes++ - 0300);
971 ins->vex_cm = *codes++;
972 ins->vex_wlp = *codes++;
973 ins->evex_tuple = (*codes++ - 0300);
982 ins->vexreg = regval(opx);
983 ins->vex_cm = *codes++;
984 ins->vex_wlp = *codes++;
990 ins->vex_cm = *codes++;
991 ins->vex_wlp = *codes++;
1008 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1012 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1019 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1020 has_prefix(ins, PPS_ASIZE, P_A32))
1029 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1033 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1035 ins->prefixes[PPS_OSIZE] = P_O16;
1041 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1045 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1047 ins->prefixes[PPS_OSIZE] = P_O32;
1089 if (!ins->prefixes[PPS_REP])
1090 ins->prefixes[PPS_REP] = P_REP;
1094 if (!ins->prefixes[PPS_REP])
1095 ins->prefixes[PPS_REP] = P_REPNE;
1099 if (ins->oprs[0].segment != NO_SEG)
1100 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1101 " quantity of BSS space");
1103 length += ins->oprs[0].offset;
1107 if (!ins->prefixes[PPS_WAIT])
1108 ins->prefixes[PPS_WAIT] = P_WAIT;
1162 struct operand *opy = &ins->oprs[op2];
1163 struct operand *op_er_sae;
1165 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1168 /* pick rfield from operand b (opx) */
1169 rflags = regflag(opx);
1170 rfield = nasm_regvals[opx->basereg];
1176 /* EVEX.b1 : evex_brerop contains the operand position */
1177 op_er_sae = (ins->evex_brerop >= 0 ?
1178 &ins->oprs[ins->evex_brerop] : NULL);
1180 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1182 ins->evex_p[2] |= EVEX_P2B;
1183 if (op_er_sae->decoflags & ER) {
1184 /* set EVEX.RC (rounding control) */
1185 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1189 /* set EVEX.L'L (vector length) */
1190 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1191 if (opy->decoflags & BRDCAST_MASK) {
1193 ins->evex_p[2] |= EVEX_P2B;
1198 * if a separate form of MIB (ICC style) is used,
1199 * the index reg info is merged into mem operand
1201 if (mib_index != R_none) {
1202 opy->indexreg = mib_index;
1204 opy->hintbase = mib_index;
1205 opy->hinttype = EAH_NOTBASE;
1208 if (process_ea(opy, &ea_data, bits,
1209 rfield, rflags, ins) != eat) {
1210 errfunc(ERR_NONFATAL, "invalid effective address");
1213 ins->rex |= ea_data.rex;
1214 length += ea_data.size;
1220 errfunc(ERR_PANIC, "internal instruction table corrupt"
1221 ": instruction code \\%o (0x%02X) given", c, c);
1226 ins->rex &= rex_mask;
1228 if (ins->rex & REX_NH) {
1229 if (ins->rex & REX_H) {
1230 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1233 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1236 if (ins->rex & (REX_V | REX_EV)) {
1237 int bad32 = REX_R|REX_W|REX_X|REX_B;
1239 if (ins->rex & REX_H) {
1240 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1243 switch (ins->vex_wlp & 060) {
1257 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1258 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1260 } else if (!(ins->rex & REX_EV) &&
1261 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1262 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1265 if (ins->rex & REX_EV)
1267 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1271 } else if (ins->rex & REX_REAL) {
1272 if (ins->rex & REX_H) {
1273 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1275 } else if (bits == 64) {
1277 } else if ((ins->rex & REX_L) &&
1278 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1281 assert_no_prefix(ins, PPS_LOCK);
1282 lockcheck = false; /* Already errored, no need for warning */
1285 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1290 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1291 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1292 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1293 "instruction is not lockable");
1296 bad_hle_warn(ins, hleok);
1301 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1304 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1305 ins->rex = (ins->rex & REX_REAL) | REX_P;
1306 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1315 static void gencode(int32_t segment, int64_t offset, int bits,
1316 insn * ins, const struct itemplate *temp,
1324 struct operand *opx;
1325 const uint8_t *codes = temp->code;
1327 enum ea_type eat = EA_SCALAR;
1331 op1 = (c & 3) + ((opex & 1) << 2);
1332 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1333 opx = &ins->oprs[op1];
1334 opex = 0; /* For the next iteration */
1341 offset += emit_rex(ins, segment, offset, bits);
1342 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1354 offset += emit_rex(ins, segment, offset, bits);
1355 bytes[0] = *codes++ + (regval(opx) & 7);
1356 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1364 if (opx->offset < -256 || opx->offset > 255) {
1365 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1366 "byte value exceeds bounds");
1368 out_imm8(offset, segment, opx);
1373 if (opx->offset < 0 || opx->offset > 255)
1374 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1375 "unsigned byte value exceeds bounds");
1376 out_imm8(offset, segment, opx);
1381 warn_overflow_opd(opx, 2);
1383 out(offset, segment, &data, OUT_ADDRESS, 2,
1384 opx->segment, opx->wrt);
1389 if (opx->type & (BITS16 | BITS32))
1390 size = (opx->type & BITS16) ? 2 : 4;
1392 size = (bits == 16) ? 2 : 4;
1393 warn_overflow_opd(opx, size);
1395 out(offset, segment, &data, OUT_ADDRESS, size,
1396 opx->segment, opx->wrt);
1401 warn_overflow_opd(opx, 4);
1403 out(offset, segment, &data, OUT_ADDRESS, 4,
1404 opx->segment, opx->wrt);
1410 size = ins->addr_size >> 3;
1411 warn_overflow_opd(opx, size);
1412 out(offset, segment, &data, OUT_ADDRESS, size,
1413 opx->segment, opx->wrt);
1418 if (opx->segment != segment) {
1420 out(offset, segment, &data,
1421 OUT_REL1ADR, insn_end - offset,
1422 opx->segment, opx->wrt);
1424 data = opx->offset - insn_end;
1425 if (data > 127 || data < -128)
1426 errfunc(ERR_NONFATAL, "short jump is out of range");
1427 out(offset, segment, &data,
1428 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1434 data = (int64_t)opx->offset;
1435 out(offset, segment, &data, OUT_ADDRESS, 8,
1436 opx->segment, opx->wrt);
1441 if (opx->segment != segment) {
1443 out(offset, segment, &data,
1444 OUT_REL2ADR, insn_end - offset,
1445 opx->segment, opx->wrt);
1447 data = opx->offset - insn_end;
1448 out(offset, segment, &data,
1449 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1455 if (opx->type & (BITS16 | BITS32 | BITS64))
1456 size = (opx->type & BITS16) ? 2 : 4;
1458 size = (bits == 16) ? 2 : 4;
1459 if (opx->segment != segment) {
1461 out(offset, segment, &data,
1462 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1463 insn_end - offset, opx->segment, opx->wrt);
1465 data = opx->offset - insn_end;
1466 out(offset, segment, &data,
1467 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1473 if (opx->segment != segment) {
1475 out(offset, segment, &data,
1476 OUT_REL4ADR, insn_end - offset,
1477 opx->segment, opx->wrt);
1479 data = opx->offset - insn_end;
1480 out(offset, segment, &data,
1481 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1487 if (opx->segment == NO_SEG)
1488 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1491 out(offset, segment, &data, OUT_ADDRESS, 2,
1492 outfmt->segbase(1 + opx->segment),
1499 opx = &ins->oprs[c >> 3];
1500 bytes[0] = nasm_regvals[opx->basereg] << 4;
1501 opx = &ins->oprs[c & 7];
1502 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1503 errfunc(ERR_NONFATAL,
1504 "non-absolute expression not permitted as argument %d",
1507 if (opx->offset & ~15) {
1508 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1509 "four-bit argument exceeds bounds");
1511 bytes[0] |= opx->offset & 15;
1513 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1519 opx = &ins->oprs[c >> 4];
1520 bytes[0] = nasm_regvals[opx->basereg] << 4;
1522 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1527 bytes[0] = nasm_regvals[opx->basereg] << 4;
1528 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1534 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1535 (int32_t)data != (int64_t)data) {
1536 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1537 "signed dword immediate exceeds bounds");
1539 out(offset, segment, &data, OUT_ADDRESS, 4,
1540 opx->segment, opx->wrt);
1547 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1548 EVEX_P2Z | EVEX_P2AAA, 2);
1549 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1551 /* EVEX.X can be set by either REX or EVEX for different reasons */
1552 bytes[1] = ((((ins->rex & 7) << 5) |
1553 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1555 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1556 ((~ins->vexreg & 15) << 3) |
1557 (1 << 2) | (ins->vex_wlp & 3);
1558 bytes[3] = ins->evex_p[2];
1559 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1566 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1567 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1568 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1569 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1570 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1571 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1575 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1576 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1577 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1592 if (ins->rex & REX_W)
1594 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1596 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1601 um = (uint64_t)2 << (s-1);
1604 if (uv > 127 && uv < (uint64_t)-128 &&
1605 (uv < um-128 || uv > um-1)) {
1606 /* If this wasn't explicitly byte-sized, warn as though we
1607 * had fallen through to the imm16/32/64 case.
1609 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1610 "%s value exceeds bounds",
1611 (opx->type & BITS8) ? "signed byte" :
1616 if (opx->segment != NO_SEG) {
1618 out(offset, segment, &data, OUT_ADDRESS, 1,
1619 opx->segment, opx->wrt);
1622 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1633 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1635 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1642 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1644 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1679 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1680 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1689 *bytes = c - 0332 + 0xF2;
1690 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1695 if (ins->rex & REX_R) {
1697 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1700 ins->rex &= ~(REX_L|REX_R);
1711 if (ins->oprs[0].segment != NO_SEG)
1712 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1714 int64_t size = ins->oprs[0].offset;
1716 out(offset, segment, NULL,
1717 OUT_RESERVE, size, NO_SEG, NO_SEG);
1730 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1740 *bytes = c - 0366 + 0x66;
1741 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1749 *bytes = bits == 16 ? 3 : 5;
1750 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1784 struct operand *opy = &ins->oprs[op2];
1787 /* pick rfield from operand b (opx) */
1788 rflags = regflag(opx);
1789 rfield = nasm_regvals[opx->basereg];
1791 /* rfield is constant */
1796 if (process_ea(opy, &ea_data, bits,
1797 rfield, rflags, ins) != eat)
1798 errfunc(ERR_NONFATAL, "invalid effective address");
1801 *p++ = ea_data.modrm;
1802 if (ea_data.sib_present)
1806 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1809 * Make sure the address gets the right offset in case
1810 * the line breaks in the .lst file (BR 1197827)
1815 switch (ea_data.bytes) {
1822 /* use compressed displacement, if available */
1823 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1826 if (opy->segment == segment) {
1828 if (overflow_signed(data, ea_data.bytes))
1829 warn_overflow(ERR_PASS2, ea_data.bytes);
1830 out(offset, segment, &data, OUT_ADDRESS,
1831 ea_data.bytes, NO_SEG, NO_SEG);
1833 /* overflow check in output/linker? */
1834 out(offset, segment, &data, OUT_REL4ADR,
1835 insn_end - offset, opy->segment, opy->wrt);
1838 if (overflow_general(data, ins->addr_size >> 3) ||
1839 signed_bits(data, ins->addr_size) !=
1840 signed_bits(data, ea_data.bytes * 8))
1841 warn_overflow(ERR_PASS2, ea_data.bytes);
1843 out(offset, segment, &data, OUT_ADDRESS,
1844 ea_data.bytes, opy->segment, opy->wrt);
1850 "Invalid amount of bytes (%d) for offset?!",
1859 errfunc(ERR_PANIC, "internal instruction table corrupt"
1860 ": instruction code \\%o (0x%02X) given", c, c);
1866 static opflags_t regflag(const operand * o)
1868 if (!is_register(o->basereg))
1869 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1870 return nasm_reg_flags[o->basereg];
1873 static int32_t regval(const operand * o)
1875 if (!is_register(o->basereg))
1876 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1877 return nasm_regvals[o->basereg];
1880 static int op_rexflags(const operand * o, int mask)
1885 if (!is_register(o->basereg))
1886 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1888 flags = nasm_reg_flags[o->basereg];
1889 val = nasm_regvals[o->basereg];
1891 return rexflags(val, flags, mask);
1894 static int rexflags(int val, opflags_t flags, int mask)
1898 if (val >= 0 && (val & 8))
1899 rex |= REX_B|REX_X|REX_R;
1902 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1904 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1910 static int evexflags(int val, decoflags_t deco,
1911 int mask, uint8_t byte)
1917 if (val >= 0 && (val & 16))
1918 evex |= (EVEX_P0RP | EVEX_P0X);
1921 if (val >= 0 && (val & 16))
1925 if (deco & OPMASK_MASK)
1926 evex |= deco & EVEX_P2AAA;
1932 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1936 if (!is_register(o->basereg))
1937 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1939 val = nasm_regvals[o->basereg];
1941 return evexflags(val, o->decoflags, mask, byte);
1944 static enum match_result find_match(const struct itemplate **tempp,
1946 int32_t segment, int64_t offset, int bits)
1948 const struct itemplate *temp;
1949 enum match_result m, merr;
1950 opflags_t xsizeflags[MAX_OPERANDS];
1951 bool opsizemissing = false;
1952 int8_t broadcast = instruction->evex_brerop;
1955 /* broadcasting uses a different data element size */
1956 for (i = 0; i < instruction->operands; i++)
1958 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
1960 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1962 merr = MERR_INVALOP;
1964 for (temp = nasm_instructions[instruction->opcode];
1965 temp->opcode != I_none; temp++) {
1966 m = matches(temp, instruction, bits);
1967 if (m == MOK_JUMP) {
1968 if (jmp_match(segment, offset, bits, instruction, temp))
1972 } else if (m == MERR_OPSIZEMISSING &&
1973 (temp->flags & IF_SMASK) != IF_SX) {
1975 * Missing operand size and a candidate for fuzzy matching...
1977 for (i = 0; i < temp->operands; i++)
1979 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
1981 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1982 opsizemissing = true;
1986 if (merr == MOK_GOOD)
1990 /* No match, but see if we can get a fuzzy operand size match... */
1994 for (i = 0; i < instruction->operands; i++) {
1996 * We ignore extrinsic operand sizes on registers, so we should
1997 * never try to fuzzy-match on them. This also resolves the case
1998 * when we have e.g. "xmmrm128" in two different positions.
2000 if (is_class(REGISTER, instruction->oprs[i].type))
2003 /* This tests if xsizeflags[i] has more than one bit set */
2004 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2005 goto done; /* No luck */
2008 instruction->oprs[i].decoflags |= xsizeflags[i];
2010 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2013 /* Try matching again... */
2014 for (temp = nasm_instructions[instruction->opcode];
2015 temp->opcode != I_none; temp++) {
2016 m = matches(temp, instruction, bits);
2017 if (m == MOK_JUMP) {
2018 if (jmp_match(segment, offset, bits, instruction, temp))
2025 if (merr == MOK_GOOD)
2034 static enum match_result matches(const struct itemplate *itemp,
2035 insn *instruction, int bits)
2037 opflags_t size[MAX_OPERANDS], asize;
2038 bool opsizemissing = false;
2044 if (itemp->opcode != instruction->opcode)
2045 return MERR_INVALOP;
2048 * Count the operands
2050 if (itemp->operands != instruction->operands)
2051 return MERR_INVALOP;
2056 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2057 return MERR_INVALOP;
2060 * Check that no spurious colons or TOs are present
2062 for (i = 0; i < itemp->operands; i++)
2063 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2064 return MERR_INVALOP;
2067 * Process size flags
2069 switch (itemp->flags & IF_SMASK) {
2112 if (itemp->flags & IF_ARMASK) {
2113 /* S- flags only apply to a specific operand */
2114 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2115 memset(size, 0, sizeof size);
2118 /* S- flags apply to all operands */
2119 for (i = 0; i < MAX_OPERANDS; i++)
2124 * Check that the operand flags all match up,
2125 * it's a bit tricky so lets be verbose:
2127 * 1) Find out the size of operand. If instruction
2128 * doesn't have one specified -- we're trying to
2129 * guess it either from template (IF_S* flag) or
2132 * 2) If template operand do not match the instruction OR
2133 * template has an operand size specified AND this size differ
2134 * from which instruction has (perhaps we got it from code bits)
2136 * a) Check that only size of instruction and operand is differ
2137 * other characteristics do match
2138 * b) Perhaps it's a register specified in instruction so
2139 * for such a case we just mark that operand as "size
2140 * missing" and this will turn on fuzzy operand size
2141 * logic facility (handled by a caller)
2143 for (i = 0; i < itemp->operands; i++) {
2144 opflags_t type = instruction->oprs[i].type;
2145 decoflags_t deco = instruction->oprs[i].decoflags;
2146 if (!(type & SIZE_MASK))
2149 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2150 (itemp->deco[i] & deco) != deco) {
2151 return MERR_INVALOP;
2152 } else if ((itemp->opd[i] & SIZE_MASK) &&
2153 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2154 if (type & SIZE_MASK) {
2156 * when broadcasting, the element size depends on
2157 * the instruction type. decorator flag should match.
2159 #define MATCH_BRSZ(bits) (((type & SIZE_MASK) == BITS##bits) && \
2160 ((itemp->deco[i] & BRSIZE_MASK) == BR_BITS##bits))
2161 if (!((deco & BRDCAST_MASK) &&
2162 (MATCH_BRSZ(32) || MATCH_BRSZ(64)))) {
2163 return MERR_INVALOP;
2165 } else if (!is_class(REGISTER, type)) {
2167 * Note: we don't honor extrinsic operand sizes for registers,
2168 * so "missing operand size" for a register should be
2169 * considered a wildcard match rather than an error.
2171 opsizemissing = true;
2173 } else if (is_register(instruction->oprs[i].basereg) &&
2174 nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
2175 !(itemp->flags & IF_AVX512)) {
2176 return MERR_ENCMISMATCH;
2181 return MERR_OPSIZEMISSING;
2184 * Check operand sizes
2186 if (itemp->flags & (IF_SM | IF_SM2)) {
2187 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2188 for (i = 0; i < oprs; i++) {
2189 asize = itemp->opd[i] & SIZE_MASK;
2191 for (i = 0; i < oprs; i++)
2197 oprs = itemp->operands;
2200 for (i = 0; i < itemp->operands; i++) {
2201 if (!(itemp->opd[i] & SIZE_MASK) &&
2202 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2203 return MERR_OPSIZEMISMATCH;
2207 * Check template is okay at the set cpu level
2209 if (((itemp->flags & IF_PLEVEL) > cpu))
2213 * Verify the appropriate long mode flag.
2215 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2216 return MERR_BADMODE;
2219 * If we have a HLE prefix, look for the NOHLE flag
2221 if ((itemp->flags & IF_NOHLE) &&
2222 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2223 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2227 * Check if special handling needed for Jumps
2229 if ((itemp->code[0] & ~1) == 0370)
2233 * Check if BND prefix is allowed
2235 if ((itemp->code[0] != 0372) &&
2236 has_prefix(instruction, PPS_REP, P_BND))
2243 * Check if offset is a multiple of N with corresponding tuple type
2244 * if Disp8*N is available, compressed displacement is stored in compdisp
2246 static bool is_disp8n(operand *input, insn *ins, int8_t *compdisp)
2248 const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}},
2249 {{16, 32, 64}, {8, 8, 8}}};
2250 const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}};
2251 const uint8_t dup_n[VLMAX] = {8, 32, 64};
2253 bool evex_b = input->decoflags & BRDCAST_MASK;
2254 enum ttypes tuple = ins->evex_tuple;
2255 /* vex_wlp composed as [wwllpp] */
2256 enum vectlens vectlen = (ins->vex_wlp & 0x0c) >> 2;
2257 /* wig(=2) is treated as w0(=0) */
2258 bool evex_w = (ins->vex_wlp & 0x10) >> 4;
2259 int32_t off = input->offset;
2265 n = fv_n[evex_w][evex_b][vectlen];
2268 n = hv_n[evex_b][vectlen];
2272 /* 16, 32, 64 for VL 128, 256, 512 respectively*/
2273 n = 1 << (vectlen + 4);
2275 case T1S8: /* N = 1 */
2276 case T1S16: /* N = 2 */
2277 n = tuple - T1S8 + 1;
2280 /* N = 4 for 32bit, 8 for 64bit */
2285 /* N = 4 for 32bit, 8 for 64bit */
2286 n = (tuple == T1F32 ? 4 : 8);
2291 if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1))
2294 n = 1 << (tuple - T2 + evex_w + 3);
2299 n = 1 << (OVM - tuple + vectlen + 1);
2312 if (n && !(off & (n - 1))) {
2314 /* if it fits in Disp8 */
2315 if (disp8 >= -128 && disp8 <= 127) {
2326 * Check if ModR/M.mod should/can be 01.
2327 * - EAF_BYTEOFFS is set
2328 * - offset can fit in a byte when EVEX is not used
2329 * - offset can be compressed when EVEX is used
2331 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2332 (o >= -128 && o <= 127 && \
2333 seg == NO_SEG && !forw_ref && \
2334 !(input->eaflags & EAF_WORDOFFS) && \
2335 !(ins->rex & REX_EV)) || \
2336 (ins->rex & REX_EV && \
2337 is_disp8n(input, ins, &output->disp8)))
2339 static enum ea_type process_ea(operand *input, ea *output, int bits,
2340 int rfield, opflags_t rflags, insn *ins)
2342 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2343 int addrbits = ins->addr_size;
2345 output->type = EA_SCALAR;
2346 output->rip = false;
2349 /* REX flags for the rfield operand */
2350 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2351 /* EVEX.R' flag for the REG operand */
2352 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2354 if (is_class(REGISTER, input->type)) {
2356 * It's a direct register.
2358 if (!is_register(input->basereg))
2361 if (!is_reg_class(REG_EA, input->basereg))
2364 /* broadcasting is not available with a direct register operand. */
2365 if (input->decoflags & BRDCAST_MASK) {
2366 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2370 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2371 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2372 output->sib_present = false; /* no SIB necessary */
2373 output->bytes = 0; /* no offset necessary either */
2374 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2377 * It's a memory reference.
2380 /* Embedded rounding or SAE is not available with a mem ref operand. */
2381 if (input->decoflags & (ER | SAE)) {
2382 nasm_error(ERR_NONFATAL,
2383 "Embedded rounding is available only with reg-reg op.");
2387 if (input->basereg == -1 &&
2388 (input->indexreg == -1 || input->scale == 0)) {
2390 * It's a pure offset.
2392 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2393 input->segment == NO_SEG) {
2394 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2395 input->type &= ~IP_REL;
2396 input->type |= MEMORY;
2399 if (input->eaflags & EAF_BYTEOFFS ||
2400 (input->eaflags & EAF_WORDOFFS &&
2401 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2402 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2405 if (bits == 64 && (~input->type & IP_REL)) {
2406 output->sib_present = true;
2407 output->sib = GEN_SIB(0, 4, 5);
2409 output->modrm = GEN_MODRM(0, rfield, 4);
2410 output->rip = false;
2412 output->sib_present = false;
2413 output->bytes = (addrbits != 16 ? 4 : 2);
2414 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2415 output->rip = bits == 64;
2419 * It's an indirection.
2421 int i = input->indexreg, b = input->basereg, s = input->scale;
2422 int32_t seg = input->segment;
2423 int hb = input->hintbase, ht = input->hinttype;
2424 int t, it, bt; /* register numbers */
2425 opflags_t x, ix, bx; /* register flags */
2428 i = -1; /* make this easy, at least */
2430 if (is_register(i)) {
2431 it = nasm_regvals[i];
2432 ix = nasm_reg_flags[i];
2438 if (is_register(b)) {
2439 bt = nasm_regvals[b];
2440 bx = nasm_reg_flags[b];
2446 /* if either one are a vector register... */
2447 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2448 opflags_t sok = BITS32 | BITS64;
2449 int32_t o = input->offset;
2450 int mod, scale, index, base;
2453 * For a vector SIB, one has to be a vector and the other,
2454 * if present, a GPR. The vector must be the index operand.
2456 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2462 t = bt, bt = it, it = t;
2463 x = bx, bx = ix, ix = x;
2469 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2476 * While we're here, ensure the user didn't specify
2479 if (input->disp_size == 16 || input->disp_size == 64)
2482 if (addrbits == 16 ||
2483 (addrbits == 32 && !(sok & BITS32)) ||
2484 (addrbits == 64 && !(sok & BITS64)))
2487 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2488 : ((ix & YMMREG & ~REG_EA)
2489 ? EA_YMMVSIB : EA_XMMVSIB));
2491 output->rex |= rexflags(it, ix, REX_X);
2492 output->rex |= rexflags(bt, bx, REX_B);
2493 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2495 index = it & 7; /* it is known to be != -1 */
2510 default: /* then what the smeg is it? */
2511 goto err; /* panic */
2519 if (base != REG_NUM_EBP && o == 0 &&
2520 seg == NO_SEG && !forw_ref &&
2521 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2523 else if (IS_MOD_01())
2529 output->sib_present = true;
2530 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2531 output->modrm = GEN_MODRM(mod, rfield, 4);
2532 output->sib = GEN_SIB(scale, index, base);
2533 } else if ((ix|bx) & (BITS32|BITS64)) {
2535 * it must be a 32/64-bit memory reference. Firstly we have
2536 * to check that all registers involved are type E/Rxx.
2538 opflags_t sok = BITS32 | BITS64;
2539 int32_t o = input->offset;
2542 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2550 goto err; /* Invalid register */
2551 if (~sok & bx & SIZE_MASK)
2552 goto err; /* Invalid size */
2557 * While we're here, ensure the user didn't specify
2560 if (input->disp_size == 16 || input->disp_size == 64)
2563 if (addrbits == 16 ||
2564 (addrbits == 32 && !(sok & BITS32)) ||
2565 (addrbits == 64 && !(sok & BITS64)))
2568 /* now reorganize base/index */
2569 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2570 ((hb == b && ht == EAH_NOTBASE) ||
2571 (hb == i && ht == EAH_MAKEBASE))) {
2572 /* swap if hints say so */
2573 t = bt, bt = it, it = t;
2574 x = bx, bx = ix, ix = x;
2576 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2577 bt = -1, bx = 0, s++;
2578 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2579 /* make single reg base, unless hint */
2580 bt = it, bx = ix, it = -1, ix = 0;
2582 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2583 s == 3 || s == 5 || s == 9) && bt == -1)
2584 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2585 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2586 (input->eaflags & EAF_TIMESTWO))
2587 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2588 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2589 if (s == 1 && it == REG_NUM_ESP) {
2590 /* swap ESP into base if scale is 1 */
2591 t = it, it = bt, bt = t;
2592 x = ix, ix = bx, bx = x;
2594 if (it == REG_NUM_ESP ||
2595 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2596 goto err; /* wrong, for various reasons */
2598 output->rex |= rexflags(it, ix, REX_X);
2599 output->rex |= rexflags(bt, bx, REX_B);
2601 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2610 if (rm != REG_NUM_EBP && o == 0 &&
2611 seg == NO_SEG && !forw_ref &&
2612 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2614 else if (IS_MOD_01())
2620 output->sib_present = false;
2621 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2622 output->modrm = GEN_MODRM(mod, rfield, rm);
2625 int mod, scale, index, base;
2645 default: /* then what the smeg is it? */
2646 goto err; /* panic */
2654 if (base != REG_NUM_EBP && o == 0 &&
2655 seg == NO_SEG && !forw_ref &&
2656 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2658 else if (IS_MOD_01())
2664 output->sib_present = true;
2665 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2666 output->modrm = GEN_MODRM(mod, rfield, 4);
2667 output->sib = GEN_SIB(scale, index, base);
2669 } else { /* it's 16-bit */
2671 int16_t o = input->offset;
2673 /* check for 64-bit long mode */
2677 /* check all registers are BX, BP, SI or DI */
2678 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2679 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2682 /* ensure the user didn't specify DWORD/QWORD */
2683 if (input->disp_size == 32 || input->disp_size == 64)
2686 if (s != 1 && i != -1)
2687 goto err; /* no can do, in 16-bit EA */
2688 if (b == -1 && i != -1) {
2693 if ((b == R_SI || b == R_DI) && i != -1) {
2698 /* have BX/BP as base, SI/DI index */
2700 goto err; /* shouldn't ever happen, in theory */
2701 if (i != -1 && b != -1 &&
2702 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2703 goto err; /* invalid combinations */
2704 if (b == -1) /* pure offset: handled above */
2705 goto err; /* so if it gets to here, panic! */
2709 switch (i * 256 + b) {
2710 case R_SI * 256 + R_BX:
2713 case R_DI * 256 + R_BX:
2716 case R_SI * 256 + R_BP:
2719 case R_DI * 256 + R_BP:
2737 if (rm == -1) /* can't happen, in theory */
2738 goto err; /* so panic if it does */
2740 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2741 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2743 else if (IS_MOD_01())
2748 output->sib_present = false; /* no SIB - it's 16-bit */
2749 output->bytes = mod; /* bytes of offset needed */
2750 output->modrm = GEN_MODRM(mod, rfield, rm);
2755 output->size = 1 + output->sib_present + output->bytes;
2756 return output->type;
2759 return output->type = EA_INVALID;
2762 static void add_asp(insn *ins, int addrbits)
2767 valid = (addrbits == 64) ? 64|32 : 32|16;
2769 switch (ins->prefixes[PPS_ASIZE]) {
2780 valid &= (addrbits == 32) ? 16 : 32;
2786 for (j = 0; j < ins->operands; j++) {
2787 if (is_class(MEMORY, ins->oprs[j].type)) {
2790 /* Verify as Register */
2791 if (!is_register(ins->oprs[j].indexreg))
2794 i = nasm_reg_flags[ins->oprs[j].indexreg];
2796 /* Verify as Register */
2797 if (!is_register(ins->oprs[j].basereg))
2800 b = nasm_reg_flags[ins->oprs[j].basereg];
2802 if (ins->oprs[j].scale == 0)
2806 int ds = ins->oprs[j].disp_size;
2807 if ((addrbits != 64 && ds > 8) ||
2808 (addrbits == 64 && ds == 16))
2828 if (valid & addrbits) {
2829 ins->addr_size = addrbits;
2830 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2831 /* Add an address size prefix */
2832 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2833 ins->addr_size = (addrbits == 32) ? 16 : 32;
2836 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2837 ins->addr_size = addrbits; /* Error recovery */
2840 defdisp = ins->addr_size == 16 ? 16 : 32;
2842 for (j = 0; j < ins->operands; j++) {
2843 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2844 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2846 * mem_offs sizes must match the address size; if not,
2847 * strip the MEM_OFFS bit and match only EA instructions
2849 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);