1 C arm/v6/sha256-compress.asm
4 Copyright (C) 2013 Niels Möller
6 This file is part of GNU Nettle.
8 GNU Nettle is free software: you can redistribute it and/or
9 modify it under the terms of either:
11 * the GNU Lesser General Public License as published by the Free
12 Software Foundation; either version 3 of the License, or (at your
13 option) any later version.
17 * the GNU General Public License as published by the Free
18 Software Foundation; either version 2 of the License, or (at your
19 option) any later version.
21 or both in parallel, as here.
23 GNU Nettle is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
26 General Public License for more details.
28 You should have received copies of the GNU General Public License and
29 the GNU Lesser General Public License along with this program. If
30 not, see http://www.gnu.org/licenses/.
33 .file "sha256-compress.asm"
48 define(<T1>, <r1>) C Overlap INPUT
49 define(<COUNT>, <r0>) C Overlap STATE
59 define(<SHIFT>, <r10>)
60 define(<ILEFT>, <r11>)
63 ldr W, [sp, #+eval(4*$1)]
64 ldr T0, [sp, #+eval(4*(($1 + 14) % 16))]
66 eor T1, T1, T0, ror #19
67 eor T1, T1, T0, lsr #10
69 ldr T0, [sp, #+eval(4*(($1 + 9) % 16))]
71 ldr T0, [sp, #+eval(4*(($1 + 1) % 16))]
73 eor T1, T1, T0, ror #18
74 eor T1, T1, T0, lsr #3
76 str W, [sp, #+eval(4*$1)]
79 C ROUND(A,B,C,D,E,F,G,H)
81 C H += S1(E) + Choice(E,F,G) + K + W
83 C H += S0(A) + Majority(A,B,C)
87 C S1(E) = E<<<26 ^ E<<<21 ^ E<<<7
88 C S0(A) = A<<<30 ^ A<<<19 ^ A<<<10
89 C Choice (E, F, G) = G^(E&(F^G))
90 C Majority (A,B,C) = (A&B) + (C&(A^B))
94 eor T0, T0, $5, ror #11
95 eor T0, T0, $5, ror #25
106 eor T0, T0, $1, ror #13
107 eor T0, T0, $1, ror #22
121 C _nettle_sha256_compress(uint32_t *state, const uint8_t *input, const uint32_t *k)
126 PROLOGUE(_nettle_sha256_compress)
127 push {r4,r5,r6,r7,r8,r10,r11,r14}
129 str STATE, [sp, #+64]
131 C Load data up front, since we don't have enough registers
132 C to load and shift on-the-fly
133 ands SHIFT, INPUT, #3
134 and INPUT, INPUT, $-4
136 addne INPUT, INPUT, #4
141 uadd8 T0, T0, I1 C Sets APSR.GE bits
146 ldm INPUT!, {I1,I2,I3,I4}
159 subs ILEFT, ILEFT, #1
160 stm DST!, {I0,I1,I2,I3}
164 ldm STATE, {SA,SB,SC,SD,SE,SF,SG,SH}
169 NOEXPN(COUNT) ROUND(SA,SB,SC,SD,SE,SF,SG,SH)
170 NOEXPN(COUNT) ROUND(SH,SA,SB,SC,SD,SE,SF,SG)
171 NOEXPN(COUNT) ROUND(SG,SH,SA,SB,SC,SD,SE,SF)
172 NOEXPN(COUNT) ROUND(SF,SG,SH,SA,SB,SC,SD,SE)
173 NOEXPN(COUNT) ROUND(SE,SF,SG,SH,SA,SB,SC,SD)
174 NOEXPN(COUNT) ROUND(SD,SE,SF,SG,SH,SA,SB,SC)
175 NOEXPN(COUNT) ROUND(SC,SD,SE,SF,SG,SH,SA,SB)
176 NOEXPN(COUNT) ROUND(SB,SC,SD,SE,SF,SG,SH,SA)
183 EXPN( 0) ROUND(SA,SB,SC,SD,SE,SF,SG,SH)
184 EXPN( 1) ROUND(SH,SA,SB,SC,SD,SE,SF,SG)
185 EXPN( 2) ROUND(SG,SH,SA,SB,SC,SD,SE,SF)
186 EXPN( 3) ROUND(SF,SG,SH,SA,SB,SC,SD,SE)
187 EXPN( 4) ROUND(SE,SF,SG,SH,SA,SB,SC,SD)
188 EXPN( 5) ROUND(SD,SE,SF,SG,SH,SA,SB,SC)
189 EXPN( 6) ROUND(SC,SD,SE,SF,SG,SH,SA,SB)
190 EXPN( 7) ROUND(SB,SC,SD,SE,SF,SG,SH,SA)
191 EXPN( 8) ROUND(SA,SB,SC,SD,SE,SF,SG,SH)
192 EXPN( 9) ROUND(SH,SA,SB,SC,SD,SE,SF,SG)
193 EXPN(10) ROUND(SG,SH,SA,SB,SC,SD,SE,SF)
194 EXPN(11) ROUND(SF,SG,SH,SA,SB,SC,SD,SE)
195 EXPN(12) ROUND(SE,SF,SG,SH,SA,SB,SC,SD)
196 EXPN(13) ROUND(SD,SE,SF,SG,SH,SA,SB,SC)
197 EXPN(14) ROUND(SC,SD,SE,SF,SG,SH,SA,SB)
198 subs COUNT, COUNT, #1
199 EXPN(15) ROUND(SB,SC,SD,SE,SF,SG,SH,SA)
202 ldr STATE, [sp, #+64]
203 C No longer needed registers
204 ldm STATE, {r1,r2,r12,r14}
209 stm STATE!, {SA,SB,SC,SD}
210 ldm STATE, {r1,r2,r12,r14}
215 stm STATE!, {SE,SF,SG,SH}
217 pop {r4,r5,r6,r7,r8,r10,r11,pc}
218 EPILOGUE(_nettle_sha256_compress)