arch/xtensa/include/asm/regs.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (c) 2006 Tensilica, Inc.  All Rights Reserved.
   4  */
   5
   6 #ifndef _XTENSA_REGS_H
   7 #define _XTENSA_REGS_H
   8
   9 /*  Special registers  */
  10
  11 #define IBREAKA         128
  12 #define DBREAKA         144
  13 #define DBREAKC         160
  14
  15 /*  Special names for read-only and write-only interrupt registers  */
  16
  17 #define INTREAD         226
  18 #define INTSET          226
  19 #define INTCLEAR        227
  20
  21 /*  EXCCAUSE register fields  */
  22
  23 #define EXCCAUSE_EXCCAUSE_SHIFT 0
  24 #define EXCCAUSE_EXCCAUSE_MASK  0x3F
  25
  26 #define EXCCAUSE_ILLEGAL_INSTRUCTION            0
  27 #define EXCCAUSE_SYSTEM_CALL                    1
  28 #define EXCCAUSE_INSTRUCTION_FETCH_ERROR        2
  29 #define EXCCAUSE_LOAD_STORE_ERROR               3
  30 #define EXCCAUSE_LEVEL1_INTERRUPT               4
  31 #define EXCCAUSE_ALLOCA                         5
  32 #define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO         6
  33 #define EXCCAUSE_SPECULATION                    7
  34 #define EXCCAUSE_PRIVILEGED                     8
  35 #define EXCCAUSE_UNALIGNED                      9
  36 #define EXCCAUSE_INSTR_DATA_ERROR               12
  37 #define EXCCAUSE_LOAD_STORE_DATA_ERROR          13
  38 #define EXCCAUSE_INSTR_ADDR_ERROR               14
  39 #define EXCCAUSE_LOAD_STORE_ADDR_ERROR          15
  40 #define EXCCAUSE_ITLB_MISS                      16
  41 #define EXCCAUSE_ITLB_MULTIHIT                  17
  42 #define EXCCAUSE_ITLB_PRIVILEGE                 18
  43 #define EXCCAUSE_ITLB_SIZE_RESTRICTION          19
  44 #define EXCCAUSE_FETCH_CACHE_ATTRIBUTE          20
  45 #define EXCCAUSE_DTLB_MISS                      24
  46 #define EXCCAUSE_DTLB_MULTIHIT                  25
  47 #define EXCCAUSE_DTLB_PRIVILEGE                 26
  48 #define EXCCAUSE_DTLB_SIZE_RESTRICTION          27
  49 #define EXCCAUSE_LOAD_CACHE_ATTRIBUTE           28
  50 #define EXCCAUSE_STORE_CACHE_ATTRIBUTE          29
  51 #define EXCCAUSE_COPROCESSOR0_DISABLED          32
  52 #define EXCCAUSE_COPROCESSOR1_DISABLED          33
  53 #define EXCCAUSE_COPROCESSOR2_DISABLED          34
  54 #define EXCCAUSE_COPROCESSOR3_DISABLED          35
  55 #define EXCCAUSE_COPROCESSOR4_DISABLED          36
  56 #define EXCCAUSE_COPROCESSOR5_DISABLED          37
  57 #define EXCCAUSE_COPROCESSOR6_DISABLED          38
  58 #define EXCCAUSE_COPROCESSOR7_DISABLED          39
  59 #define EXCCAUSE_LAST                           63
  60
  61 /*  PS register fields  */
  62
  63 #define PS_WOE_BIT              18
  64 #define PS_CALLINC_SHIFT        16
  65 #define PS_CALLINC_MASK         0x00030000
  66 #define PS_OWB_SHIFT            8
  67 #define PS_OWB_MASK             0x00000F00
  68 #define PS_RING_SHIFT           6
  69 #define PS_RING_MASK            0x000000C0
  70 #define PS_UM_BIT               5
  71 #define PS_EXCM_BIT             4
  72 #define PS_INTLEVEL_SHIFT       0
  73 #define PS_INTLEVEL_MASK        0x0000000F
  74
  75 /*  DBREAKCn register fields  */
  76
  77 #define DBREAKC_MASK_BIT                0
  78 #define DBREAKC_MASK_MASK               0x0000003F
  79 #define DBREAKC_LOAD_BIT                30
  80 #define DBREAKC_LOAD_MASK               0x40000000
  81 #define DBREAKC_STOR_BIT                31
  82 #define DBREAKC_STOR_MASK               0x80000000
  83
  84 /*  DEBUGCAUSE register fields  */
  85
  86 #define DEBUGCAUSE_DEBUGINT_BIT         5       /* External debug interrupt */
  87 #define DEBUGCAUSE_BREAKN_BIT           4       /* BREAK.N instruction */
  88 #define DEBUGCAUSE_BREAK_BIT            3       /* BREAK instruction */
  89 #define DEBUGCAUSE_DBREAK_BIT           2       /* DBREAK match */
  90 #define DEBUGCAUSE_IBREAK_BIT           1       /* IBREAK match */
  91 #define DEBUGCAUSE_ICOUNT_BIT           0       /* ICOUNT would incr. to zero */
  92
  93 #endif /* _XTENSA_SPECREG_H */