2 * Suspend support specific for i386.
4 * Distribute under GPLv2
6 * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
7 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
10 #include <linux/suspend.h>
11 #include <linux/smp.h>
13 #include <asm/pgtable.h>
14 #include <asm/proto.h>
19 #include <asm/suspend.h>
22 static struct saved_context saved_context;
24 unsigned long saved_context_ebx;
25 unsigned long saved_context_esp, saved_context_ebp;
26 unsigned long saved_context_esi, saved_context_edi;
27 unsigned long saved_context_eflags;
30 static void fix_processor_context(void);
32 struct saved_context saved_context;
36 * __save_processor_state - save CPU registers before creating a
37 * hibernation image and before restoring the memory state from it
38 * @ctxt - structure to store the registers contents in
40 * NOTE: If there is a CPU register the modification of which by the
41 * boot kernel (ie. the kernel used for loading the hibernation image)
42 * might affect the operations of the restored target kernel (ie. the one
43 * saved in the hibernation image), then its contents must be saved by this
44 * function. In other words, if kernel A is hibernated and different
45 * kernel B is used for loading the hibernation image into memory, the
46 * kernel A's __save_processor_state() function must save all registers
47 * needed by kernel A, so that it can operate correctly after the resume
48 * regardless of what kernel B does in the meantime.
50 static void __save_processor_state(struct saved_context *ctxt)
53 mtrr_save_fixed_ranges(NULL);
61 store_gdt(&ctxt->gdt);
62 store_idt(&ctxt->idt);
65 store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
66 store_idt((struct desc_ptr *)&ctxt->idt_limit);
70 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
75 savesegment(es, ctxt->es);
76 savesegment(fs, ctxt->fs);
77 savesegment(gs, ctxt->gs);
78 savesegment(ss, ctxt->ss);
81 asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
82 asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
83 asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
84 asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
85 asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
87 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
88 rdmsrl(MSR_GS_BASE, ctxt->gs_base);
89 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
90 mtrr_save_fixed_ranges(NULL);
92 rdmsrl(MSR_EFER, ctxt->efer);
98 ctxt->cr0 = read_cr0();
99 ctxt->cr2 = read_cr2();
100 ctxt->cr3 = read_cr3();
102 ctxt->cr4 = read_cr4_safe();
105 ctxt->cr4 = read_cr4();
106 ctxt->cr8 = read_cr8();
110 /* Needed by apm.c */
111 void save_processor_state(void)
113 __save_processor_state(&saved_context);
116 EXPORT_SYMBOL(save_processor_state);
119 static void do_fpu_end(void)
122 * Restore FPU regs if necessary.
127 static void fix_processor_context(void)
129 int cpu = smp_processor_id();
130 struct tss_struct *t = &per_cpu(init_tss, cpu);
132 set_tss_desc(cpu, t); /*
133 * This just modifies memory; should not be
134 * necessary. But... This is necessary, because
135 * 386 hardware has concept of busy TSS or some
139 load_TR_desc(); /* This does ltr */
140 load_LDT(¤t->active_mm->context); /* This does lldt */
143 * Now maybe reload the debug registers
145 if (current->thread.debugreg7) {
146 set_debugreg(current->thread.debugreg0, 0);
147 set_debugreg(current->thread.debugreg1, 1);
148 set_debugreg(current->thread.debugreg2, 2);
149 set_debugreg(current->thread.debugreg3, 3);
151 set_debugreg(current->thread.debugreg6, 6);
152 set_debugreg(current->thread.debugreg7, 7);
157 static void __restore_processor_state(struct saved_context *ctxt)
162 /* cr4 was introduced in the Pentium CPU */
164 write_cr4(ctxt->cr4);
165 write_cr3(ctxt->cr3);
166 write_cr2(ctxt->cr2);
167 write_cr0(ctxt->cr0);
170 * now restore the descriptor tables to their proper values
171 * ltr is done i fix_processor_context().
173 load_gdt(&ctxt->gdt);
174 load_idt(&ctxt->idt);
179 loadsegment(es, ctxt->es);
180 loadsegment(fs, ctxt->fs);
181 loadsegment(gs, ctxt->gs);
182 loadsegment(ss, ctxt->ss);
187 if (boot_cpu_has(X86_FEATURE_SEP))
191 * restore XCR0 for xsave capable cpu's.
194 xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
196 fix_processor_context();
199 mcheck_init(&boot_cpu_data);
202 /* Needed by apm.c */
203 void restore_processor_state(void)
205 __restore_processor_state(&saved_context);
207 EXPORT_SYMBOL(restore_processor_state);