2 * Suspend support specific for i386/x86-64.
4 * Distribute under GPLv2
6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
7 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
8 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
11 #include <linux/suspend.h>
12 #include <linux/export.h>
13 #include <linux/smp.h>
15 #include <asm/pgtable.h>
16 #include <asm/proto.h>
21 #include <asm/suspend.h>
22 #include <asm/debugreg.h>
23 #include <asm/fpu-internal.h> /* pcntxt_mask */
27 static struct saved_context saved_context;
29 unsigned long saved_context_ebx;
30 unsigned long saved_context_esp, saved_context_ebp;
31 unsigned long saved_context_esi, saved_context_edi;
32 unsigned long saved_context_eflags;
35 struct saved_context saved_context;
39 * __save_processor_state - save CPU registers before creating a
40 * hibernation image and before restoring the memory state from it
41 * @ctxt - structure to store the registers contents in
43 * NOTE: If there is a CPU register the modification of which by the
44 * boot kernel (ie. the kernel used for loading the hibernation image)
45 * might affect the operations of the restored target kernel (ie. the one
46 * saved in the hibernation image), then its contents must be saved by this
47 * function. In other words, if kernel A is hibernated and different
48 * kernel B is used for loading the hibernation image into memory, the
49 * kernel A's __save_processor_state() function must save all registers
50 * needed by kernel A, so that it can operate correctly after the resume
51 * regardless of what kernel B does in the meantime.
53 static void __save_processor_state(struct saved_context *ctxt)
56 mtrr_save_fixed_ranges(NULL);
64 store_gdt(&ctxt->gdt);
65 store_idt(&ctxt->idt);
68 store_idt((struct desc_ptr *)&ctxt->idt_limit);
72 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
77 savesegment(es, ctxt->es);
78 savesegment(fs, ctxt->fs);
79 savesegment(gs, ctxt->gs);
80 savesegment(ss, ctxt->ss);
83 asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
84 asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
85 asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
86 asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
87 asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
89 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
90 rdmsrl(MSR_GS_BASE, ctxt->gs_base);
91 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
92 mtrr_save_fixed_ranges(NULL);
94 rdmsrl(MSR_EFER, ctxt->efer);
100 ctxt->cr0 = read_cr0();
101 ctxt->cr2 = read_cr2();
102 ctxt->cr3 = read_cr3();
104 ctxt->cr4 = read_cr4_safe();
107 ctxt->cr4 = read_cr4();
108 ctxt->cr8 = read_cr8();
110 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
114 /* Needed by apm.c */
115 void save_processor_state(void)
117 __save_processor_state(&saved_context);
118 x86_platform.save_sched_clock_state();
121 EXPORT_SYMBOL(save_processor_state);
124 static void do_fpu_end(void)
127 * Restore FPU regs if necessary.
132 static void fix_processor_context(void)
134 int cpu = smp_processor_id();
135 struct tss_struct *t = &per_cpu(init_tss, cpu);
137 set_tss_desc(cpu, t); /*
138 * This just modifies memory; should not be
139 * necessary. But... This is necessary, because
140 * 386 hardware has concept of busy TSS or some
145 get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
147 syscall_init(); /* This sets MSR_*STAR and related */
149 load_TR_desc(); /* This does ltr */
150 load_LDT(¤t->active_mm->context); /* This does lldt */
154 * __restore_processor_state - restore the contents of CPU registers saved
155 * by __save_processor_state()
156 * @ctxt - structure to load the registers contents from
158 static void __restore_processor_state(struct saved_context *ctxt)
160 if (ctxt->misc_enable_saved)
161 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
165 /* cr4 was introduced in the Pentium CPU */
168 write_cr4(ctxt->cr4);
171 wrmsrl(MSR_EFER, ctxt->efer);
172 write_cr8(ctxt->cr8);
173 write_cr4(ctxt->cr4);
175 write_cr3(ctxt->cr3);
176 write_cr2(ctxt->cr2);
177 write_cr0(ctxt->cr0);
180 * now restore the descriptor tables to their proper values
181 * ltr is done i fix_processor_context().
184 load_gdt(&ctxt->gdt);
185 load_idt(&ctxt->idt);
188 load_idt((const struct desc_ptr *)&ctxt->idt_limit);
195 loadsegment(es, ctxt->es);
196 loadsegment(fs, ctxt->fs);
197 loadsegment(gs, ctxt->gs);
198 loadsegment(ss, ctxt->ss);
203 if (boot_cpu_has(X86_FEATURE_SEP))
207 asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
208 asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
209 asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
210 load_gs_index(ctxt->gs);
211 asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
213 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
214 wrmsrl(MSR_GS_BASE, ctxt->gs_base);
215 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
219 * restore XCR0 for xsave capable cpu's.
222 xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
224 fix_processor_context();
227 x86_platform.restore_sched_clock_state();
231 /* Needed by apm.c */
232 void restore_processor_state(void)
234 __restore_processor_state(&saved_context);
237 EXPORT_SYMBOL(restore_processor_state);
241 * When bsp_check() is called in hibernate and suspend, cpu hotplug
242 * is disabled already. So it's unnessary to handle race condition between
243 * cpumask query and cpu hotplug.
245 static int bsp_check(void)
247 if (cpumask_first(cpu_online_mask) != 0) {
248 pr_warn("CPU0 is offline.\n");
255 static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
261 case PM_SUSPEND_PREPARE:
262 case PM_HIBERNATION_PREPARE:
265 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0
266 case PM_RESTORE_PREPARE:
268 * When system resumes from hibernation, online CPU0 because
269 * 1. it's required for resume and
270 * 2. the CPU was online before hibernation
273 _debug_hotplug_cpu(0, 1);
275 case PM_POST_RESTORE:
277 * When a resume really happens, this code won't be called.
279 * This code is called only when user space hibernation software
280 * prepares for snapshot device during boot time. So we just
281 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
282 * preparing the snapshot device.
284 * This works for normal boot case in our CPU0 hotplug debug
285 * mode, i.e. CPU0 is offline and user mode hibernation
286 * software initializes during boot time.
288 * If CPU0 is online and user application accesses snapshot
289 * device after boot time, this will offline CPU0 and user may
290 * see different CPU0 state before and after accessing
291 * the snapshot device. But hopefully this is not a case when
292 * user debugging CPU0 hotplug. Even if users hit this case,
293 * they can easily online CPU0 back.
295 * To simplify this debug code, we only consider normal boot
296 * case. Otherwise we need to remember CPU0's state and restore
297 * to that state and resolve racy conditions etc.
299 _debug_hotplug_cpu(0, 0);
305 return notifier_from_errno(ret);
308 static int __init bsp_pm_check_init(void)
311 * Set this bsp_pm_callback as lower priority than
312 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
313 * earlier to disable cpu hotplug before bsp online check.
315 pm_notifier(bsp_pm_callback, -INT_MAX);
319 core_initcall(bsp_pm_check_init);