arch/x86/oprofile/op_model_amd.c

   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2009 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  13  * @author Jason Yeh <jason.yeh@amd.com>
  14  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  15  */
  16
  17 #include <linux/oprofile.h>
  18 #include <linux/device.h>
  19 #include <linux/pci.h>
  20 #include <linux/percpu.h>
  21
  22 #include <asm/ptrace.h>
  23 #include <asm/msr.h>
  24 #include <asm/nmi.h>
  25 #include <asm/apic.h>
  26 #include <asm/processor.h>
  27 #include <asm/cpufeature.h>
  28
  29 #include "op_x86_model.h"
  30 #include "op_counter.h"
  31
  32 #define NUM_COUNTERS 4
  33 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  34 #define NUM_VIRT_COUNTERS 32
  35 #else
  36 #define NUM_VIRT_COUNTERS NUM_COUNTERS
  37 #endif
  38
  39 #define OP_EVENT_MASK                   0x0FFF
  40 #define OP_CTR_OVERFLOW                 (1ULL<<31)
  41
  42 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
  43
  44 static unsigned long reset_value[NUM_VIRT_COUNTERS];
  45
  46 #define IBS_FETCH_SIZE                  6
  47 #define IBS_OP_SIZE                     12
  48
  49 static u32 ibs_caps;
  50
  51 struct ibs_config {
  52         unsigned long op_enabled;
  53         unsigned long fetch_enabled;
  54         unsigned long max_cnt_fetch;
  55         unsigned long max_cnt_op;
  56         unsigned long rand_en;
  57         unsigned long dispatched_ops;
  58 };
  59
  60 struct ibs_state {
  61         u64     ibs_op_ctl;
  62 };
  63
  64 static struct ibs_config ibs_config;
  65 static struct ibs_state ibs_state;
  66
  67 /*
  68  * IBS cpuid feature detection
  69  */
  70
  71 #define IBS_CPUID_FEATURES      0x8000001b
  72
  73 /*
  74  * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
  75  * bit 0 is used to indicate the existence of IBS.
  76  */
  77 #define IBS_CAPS_AVAIL                  (1U<<0)
  78 #define IBS_CAPS_FETCHSAM               (1U<<1)
  79 #define IBS_CAPS_OPSAM                  (1U<<2)
  80 #define IBS_CAPS_RDWROPCNT              (1U<<3)
  81 #define IBS_CAPS_OPCNT                  (1U<<4)
  82
  83 #define IBS_CAPS_DEFAULT                (IBS_CAPS_AVAIL         \
  84                                          | IBS_CAPS_FETCHSAM    \
  85                                          | IBS_CAPS_OPSAM)
  86
  87 /*
  88  * IBS APIC setup
  89  */
  90 #define IBSCTL                          0x1cc
  91 #define IBSCTL_LVT_OFFSET_VALID         (1ULL<<8)
  92 #define IBSCTL_LVT_OFFSET_MASK          0x0F
  93
  94 /*
  95  * IBS randomization macros
  96  */
  97 #define IBS_RANDOM_BITS                 12
  98 #define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
  99 #define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
 100
 101 static u32 get_ibs_caps(void)
 102 {
 103         u32 ibs_caps;
 104         unsigned int max_level;
 105
 106         if (!boot_cpu_has(X86_FEATURE_IBS))
 107                 return 0;
 108
 109         /* check IBS cpuid feature flags */
 110         max_level = cpuid_eax(0x80000000);
 111         if (max_level < IBS_CPUID_FEATURES)
 112                 return IBS_CAPS_DEFAULT;
 113
 114         ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
 115         if (!(ibs_caps & IBS_CAPS_AVAIL))
 116                 /* cpuid flags not valid */
 117                 return IBS_CAPS_DEFAULT;
 118
 119         return ibs_caps;
 120 }
 121
 122 /*
 123  * 16-bit Linear Feedback Shift Register (LFSR)
 124  *
 125  *                       16   14   13    11
 126  * Feedback polynomial = X  + X  + X  +  X  + 1
 127  */
 128 static unsigned int lfsr_random(void)
 129 {
 130         static unsigned int lfsr_value = 0xF00D;
 131         unsigned int bit;
 132
 133         /* Compute next bit to shift in */
 134         bit = ((lfsr_value >> 0) ^
 135                (lfsr_value >> 2) ^
 136                (lfsr_value >> 3) ^
 137                (lfsr_value >> 5)) & 0x0001;
 138
 139         /* Advance to next register value */
 140         lfsr_value = (lfsr_value >> 1) | (bit << 15);
 141
 142         return lfsr_value;
 143 }
 144
 145 /*
 146  * IBS software randomization
 147  *
 148  * The IBS periodic op counter is randomized in software. The lower 12
 149  * bits of the 20 bit counter are randomized. IbsOpCurCnt is
 150  * initialized with a 12 bit random value.
 151  */
 152 static inline u64 op_amd_randomize_ibs_op(u64 val)
 153 {
 154         unsigned int random = lfsr_random();
 155
 156         if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
 157                 /*
 158                  * Work around if the hw can not write to IbsOpCurCnt
 159                  *
 160                  * Randomize the lower 8 bits of the 16 bit
 161                  * IbsOpMaxCnt [15:0] value in the range of -128 to
 162                  * +127 by adding/subtracting an offset to the
 163                  * maximum count (IbsOpMaxCnt).
 164                  *
 165                  * To avoid over or underflows and protect upper bits
 166                  * starting at bit 16, the initial value for
 167                  * IbsOpMaxCnt must fit in the range from 0x0081 to
 168                  * 0xff80.
 169                  */
 170                 val += (s8)(random >> 4);
 171         else
 172                 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
 173
 174         return val;
 175 }
 176
 177 static inline void
 178 op_amd_handle_ibs(struct pt_regs * const regs,
 179                   struct op_msrs const * const msrs)
 180 {
 181         u64 val, ctl;
 182         struct op_entry entry;
 183
 184         if (!ibs_caps)
 185                 return;
 186
 187         if (ibs_config.fetch_enabled) {
 188                 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 189                 if (ctl & IBS_FETCH_VAL) {
 190                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
 191                         oprofile_write_reserve(&entry, regs, val,
 192                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
 193                         oprofile_add_data64(&entry, val);
 194                         oprofile_add_data64(&entry, ctl);
 195                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
 196                         oprofile_add_data64(&entry, val);
 197                         oprofile_write_commit(&entry);
 198
 199                         /* reenable the IRQ */
 200                         ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
 201                         ctl |= IBS_FETCH_ENABLE;
 202                         wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 203                 }
 204         }
 205
 206         if (ibs_config.op_enabled) {
 207                 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
 208                 if (ctl & IBS_OP_VAL) {
 209                         rdmsrl(MSR_AMD64_IBSOPRIP, val);
 210                         oprofile_write_reserve(&entry, regs, val,
 211                                                IBS_OP_CODE, IBS_OP_SIZE);
 212                         oprofile_add_data64(&entry, val);
 213                         rdmsrl(MSR_AMD64_IBSOPDATA, val);
 214                         oprofile_add_data64(&entry, val);
 215                         rdmsrl(MSR_AMD64_IBSOPDATA2, val);
 216                         oprofile_add_data64(&entry, val);
 217                         rdmsrl(MSR_AMD64_IBSOPDATA3, val);
 218                         oprofile_add_data64(&entry, val);
 219                         rdmsrl(MSR_AMD64_IBSDCLINAD, val);
 220                         oprofile_add_data64(&entry, val);
 221                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
 222                         oprofile_add_data64(&entry, val);
 223                         oprofile_write_commit(&entry);
 224
 225                         /* reenable the IRQ */
 226                         ctl = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
 227                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
 228                 }
 229         }
 230 }
 231
 232 static inline void op_amd_start_ibs(void)
 233 {
 234         u64 val;
 235
 236         if (!ibs_caps)
 237                 return;
 238
 239         memset(&ibs_state, 0, sizeof(ibs_state));
 240
 241         if (ibs_config.fetch_enabled) {
 242                 val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT;
 243                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
 244                 val |= IBS_FETCH_ENABLE;
 245                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
 246         }
 247
 248         if (ibs_config.op_enabled) {
 249                 val = ibs_config.max_cnt_op >> 4;
 250                 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
 251                         /*
 252                          * IbsOpCurCnt not supported.  See
 253                          * op_amd_randomize_ibs_op() for details.
 254                          */
 255                         val = clamp(val, 0x0081ULL, 0xFF80ULL);
 256                 } else {
 257                         /*
 258                          * The start value is randomized with a
 259                          * positive offset, we need to compensate it
 260                          * with the half of the randomized range. Also
 261                          * avoid underflows.
 262                          */
 263                         val = min(val + IBS_RANDOM_MAXCNT_OFFSET,
 264                                   IBS_OP_MAX_CNT);
 265                 }
 266                 val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
 267                 val |= IBS_OP_ENABLE;
 268                 ibs_state.ibs_op_ctl = val;
 269                 val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
 270                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
 271         }
 272 }
 273
 274 static void op_amd_stop_ibs(void)
 275 {
 276         if (!ibs_caps)
 277                 return;
 278
 279         if (ibs_config.fetch_enabled)
 280                 /* clear max count and enable */
 281                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
 282
 283         if (ibs_config.op_enabled)
 284                 /* clear max count and enable */
 285                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 286 }
 287
 288 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 289
 290 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
 291                                struct op_msrs const * const msrs)
 292 {
 293         u64 val;
 294         int i;
 295
 296         /* enable active counters */
 297         for (i = 0; i < NUM_COUNTERS; ++i) {
 298                 int virt = op_x86_phys_to_virt(i);
 299                 if (!reset_value[virt])
 300                         continue;
 301                 rdmsrl(msrs->controls[i].addr, val);
 302                 val &= model->reserved;
 303                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 304                 wrmsrl(msrs->controls[i].addr, val);
 305         }
 306 }
 307
 308 #endif
 309
 310 /* functions for op_amd_spec */
 311
 312 static void op_amd_shutdown(struct op_msrs const * const msrs)
 313 {
 314         int i;
 315
 316         for (i = 0; i < NUM_COUNTERS; ++i) {
 317                 if (!msrs->counters[i].addr)
 318                         continue;
 319                 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 320                 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 321         }
 322 }
 323
 324 static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
 325 {
 326         int i;
 327
 328         for (i = 0; i < NUM_COUNTERS; i++) {
 329                 if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
 330                         goto fail;
 331                 if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
 332                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 333                         goto fail;
 334                 }
 335                 /* both registers must be reserved */
 336                 msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
 337                 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
 338                 continue;
 339         fail:
 340                 if (!counter_config[i].enabled)
 341                         continue;
 342                 op_x86_warn_reserved(i);
 343                 op_amd_shutdown(msrs);
 344                 return -EBUSY;
 345         }
 346
 347         return 0;
 348 }
 349
 350 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
 351                               struct op_msrs const * const msrs)
 352 {
 353         u64 val;
 354         int i;
 355
 356         /* setup reset_value */
 357         for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
 358                 if (counter_config[i].enabled
 359                     && msrs->counters[op_x86_virt_to_phys(i)].addr)
 360                         reset_value[i] = counter_config[i].count;
 361                 else
 362                         reset_value[i] = 0;
 363         }
 364
 365         /* clear all counters */
 366         for (i = 0; i < NUM_COUNTERS; ++i) {
 367                 if (!msrs->controls[i].addr)
 368                         continue;
 369                 rdmsrl(msrs->controls[i].addr, val);
 370                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
 371                         op_x86_warn_in_use(i);
 372                 val &= model->reserved;
 373                 wrmsrl(msrs->controls[i].addr, val);
 374                 /*
 375                  * avoid a false detection of ctr overflows in NMI
 376                  * handler
 377                  */
 378                 wrmsrl(msrs->counters[i].addr, -1LL);
 379         }
 380
 381         /* enable active counters */
 382         for (i = 0; i < NUM_COUNTERS; ++i) {
 383                 int virt = op_x86_phys_to_virt(i);
 384                 if (!reset_value[virt])
 385                         continue;
 386
 387                 /* setup counter registers */
 388                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 389
 390                 /* setup control registers */
 391                 rdmsrl(msrs->controls[i].addr, val);
 392                 val &= model->reserved;
 393                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 394                 wrmsrl(msrs->controls[i].addr, val);
 395         }
 396
 397         if (ibs_caps)
 398                 setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
 399 }
 400
 401 static void op_amd_cpu_shutdown(void)
 402 {
 403         if (ibs_caps)
 404                 setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 405 }
 406
 407 static int op_amd_check_ctrs(struct pt_regs * const regs,
 408                              struct op_msrs const * const msrs)
 409 {
 410         u64 val;
 411         int i;
 412
 413         for (i = 0; i < NUM_COUNTERS; ++i) {
 414                 int virt = op_x86_phys_to_virt(i);
 415                 if (!reset_value[virt])
 416                         continue;
 417                 rdmsrl(msrs->counters[i].addr, val);
 418                 /* bit is clear if overflowed: */
 419                 if (val & OP_CTR_OVERFLOW)
 420                         continue;
 421                 oprofile_add_sample(regs, virt);
 422                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 423         }
 424
 425         op_amd_handle_ibs(regs, msrs);
 426
 427         /* See op_model_ppro.c */
 428         return 1;
 429 }
 430
 431 static void op_amd_start(struct op_msrs const * const msrs)
 432 {
 433         u64 val;
 434         int i;
 435
 436         for (i = 0; i < NUM_COUNTERS; ++i) {
 437                 if (!reset_value[op_x86_phys_to_virt(i)])
 438                         continue;
 439                 rdmsrl(msrs->controls[i].addr, val);
 440                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 441                 wrmsrl(msrs->controls[i].addr, val);
 442         }
 443
 444         op_amd_start_ibs();
 445 }
 446
 447 static void op_amd_stop(struct op_msrs const * const msrs)
 448 {
 449         u64 val;
 450         int i;
 451
 452         /*
 453          * Subtle: stop on all counters to avoid race with setting our
 454          * pm callback
 455          */
 456         for (i = 0; i < NUM_COUNTERS; ++i) {
 457                 if (!reset_value[op_x86_phys_to_virt(i)])
 458                         continue;
 459                 rdmsrl(msrs->controls[i].addr, val);
 460                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 461                 wrmsrl(msrs->controls[i].addr, val);
 462         }
 463
 464         op_amd_stop_ibs();
 465 }
 466
 467 static int __init_ibs_nmi(void)
 468 {
 469 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 470 #define IBSCTL                          0x1cc
 471         struct pci_dev *cpu_cfg;
 472         int nodes;
 473         u32 value = 0;
 474         u8 ibs_eilvt_off;
 475
 476         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 477
 478         nodes = 0;
 479         cpu_cfg = NULL;
 480         do {
 481                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 482                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 483                                          cpu_cfg);
 484                 if (!cpu_cfg)
 485                         break;
 486                 ++nodes;
 487                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 488                                        | IBSCTL_LVTOFFSETVAL);
 489                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 490                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
 491                         pci_dev_put(cpu_cfg);
 492                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 493                                 "IBSCTL = 0x%08x", value);
 494                         return 1;
 495                 }
 496         } while (1);
 497
 498         if (!nodes) {
 499                 printk(KERN_DEBUG "No CPU node configured for IBS");
 500                 return 1;
 501         }
 502
 503         return 0;
 504 }
 505
 506 /* initialize the APIC for the IBS interrupts if available */
 507 static void init_ibs(void)
 508 {
 509         ibs_caps = get_ibs_caps();
 510
 511         if (!ibs_caps)
 512                 return;
 513
 514         if (__init_ibs_nmi()) {
 515                 ibs_caps = 0;
 516                 return;
 517         }
 518
 519         printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
 520                (unsigned)ibs_caps);
 521 }
 522
 523 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 524
 525 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 526 {
 527         struct dentry *dir;
 528         int ret = 0;
 529
 530         /* architecture specific files */
 531         if (create_arch_files)
 532                 ret = create_arch_files(sb, root);
 533
 534         if (ret)
 535                 return ret;
 536
 537         if (!ibs_caps)
 538                 return ret;
 539
 540         /* model specific files */
 541
 542         /* setup some reasonable defaults */
 543         ibs_config.max_cnt_fetch = 250000;
 544         ibs_config.fetch_enabled = 0;
 545         ibs_config.max_cnt_op = 250000;
 546         ibs_config.op_enabled = 0;
 547         ibs_config.dispatched_ops = 0;
 548
 549         if (ibs_caps & IBS_CAPS_FETCHSAM) {
 550                 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 551                 oprofilefs_create_ulong(sb, dir, "enable",
 552                                         &ibs_config.fetch_enabled);
 553                 oprofilefs_create_ulong(sb, dir, "max_count",
 554                                         &ibs_config.max_cnt_fetch);
 555                 oprofilefs_create_ulong(sb, dir, "rand_enable",
 556                                         &ibs_config.rand_en);
 557         }
 558
 559         if (ibs_caps & IBS_CAPS_OPSAM) {
 560                 dir = oprofilefs_mkdir(sb, root, "ibs_op");
 561                 oprofilefs_create_ulong(sb, dir, "enable",
 562                                         &ibs_config.op_enabled);
 563                 oprofilefs_create_ulong(sb, dir, "max_count",
 564                                         &ibs_config.max_cnt_op);
 565                 if (ibs_caps & IBS_CAPS_OPCNT)
 566                         oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 567                                                 &ibs_config.dispatched_ops);
 568         }
 569
 570         return 0;
 571 }
 572
 573 static int op_amd_init(struct oprofile_operations *ops)
 574 {
 575         init_ibs();
 576         create_arch_files = ops->create_files;
 577         ops->create_files = setup_ibs_files;
 578         return 0;
 579 }
 580
 581 struct op_x86_model_spec op_amd_spec = {
 582         .num_counters           = NUM_COUNTERS,
 583         .num_controls           = NUM_COUNTERS,
 584         .num_virt_counters      = NUM_VIRT_COUNTERS,
 585         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
 586         .event_mask             = OP_EVENT_MASK,
 587         .init                   = op_amd_init,
 588         .fill_in_addresses      = &op_amd_fill_in_addresses,
 589         .setup_ctrs             = &op_amd_setup_ctrs,
 590         .cpu_down               = &op_amd_cpu_shutdown,
 591         .check_ctrs             = &op_amd_check_ctrs,
 592         .start                  = &op_amd_start,
 593         .stop                   = &op_amd_stop,
 594         .shutdown               = &op_amd_shutdown,
 595 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 596         .switch_ctrl            = &op_mux_switch_ctrl,
 597 #endif
 598 };