1 /* bpf_jit_comp.c : BPF JIT compiler
3 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
4 * Internal BPF Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; version 2
11 #include <linux/netdevice.h>
12 #include <linux/filter.h>
13 #include <linux/if_vlan.h>
14 #include <asm/cacheflush.h>
15 #include <asm/set_memory.h>
16 #include <linux/bpf.h>
18 int bpf_jit_enable __read_mostly;
21 * assembly code in arch/x86/net/bpf_jit.S
23 extern u8 sk_load_word[], sk_load_half[], sk_load_byte[];
24 extern u8 sk_load_word_positive_offset[], sk_load_half_positive_offset[];
25 extern u8 sk_load_byte_positive_offset[];
26 extern u8 sk_load_word_negative_offset[], sk_load_half_negative_offset[];
27 extern u8 sk_load_byte_negative_offset[];
29 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
42 #define EMIT(bytes, len) \
43 do { prog = emit_code(prog, bytes, len); cnt += len; } while (0)
45 #define EMIT1(b1) EMIT(b1, 1)
46 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2)
47 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
48 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
49 #define EMIT1_off32(b1, off) \
50 do {EMIT1(b1); EMIT(off, 4); } while (0)
51 #define EMIT2_off32(b1, b2, off) \
52 do {EMIT2(b1, b2); EMIT(off, 4); } while (0)
53 #define EMIT3_off32(b1, b2, b3, off) \
54 do {EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
55 #define EMIT4_off32(b1, b2, b3, b4, off) \
56 do {EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
58 static bool is_imm8(int value)
60 return value <= 127 && value >= -128;
63 static bool is_simm32(s64 value)
65 return value == (s64) (s32) value;
69 #define EMIT_mov(DST, SRC) \
71 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
74 static int bpf_size_to_x86_bytes(int bpf_size)
76 if (bpf_size == BPF_W)
78 else if (bpf_size == BPF_H)
80 else if (bpf_size == BPF_B)
82 else if (bpf_size == BPF_DW)
88 /* list of x86 cond jumps opcodes (. + s8)
89 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
100 static void bpf_flush_icache(void *start, void *end)
102 mm_segment_t old_fs = get_fs();
106 flush_icache_range((unsigned long)start, (unsigned long)end);
110 #define CHOOSE_LOAD_FUNC(K, func) \
111 ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
113 /* pick a register outside of BPF range for JIT internal work */
114 #define AUX_REG (MAX_BPF_JIT_REG + 1)
116 /* The following table maps BPF registers to x64 registers.
118 * x64 register r12 is unused, since if used as base address
119 * register in load/store instructions, it always needs an
120 * extra byte of encoding and is callee saved.
122 * r9 caches skb->len - skb->data_len
123 * r10 caches skb->data, and used for blinding (if enabled)
125 static const int reg2hex[] = {
126 [BPF_REG_0] = 0, /* rax */
127 [BPF_REG_1] = 7, /* rdi */
128 [BPF_REG_2] = 6, /* rsi */
129 [BPF_REG_3] = 2, /* rdx */
130 [BPF_REG_4] = 1, /* rcx */
131 [BPF_REG_5] = 0, /* r8 */
132 [BPF_REG_6] = 3, /* rbx callee saved */
133 [BPF_REG_7] = 5, /* r13 callee saved */
134 [BPF_REG_8] = 6, /* r14 callee saved */
135 [BPF_REG_9] = 7, /* r15 callee saved */
136 [BPF_REG_FP] = 5, /* rbp readonly */
137 [BPF_REG_AX] = 2, /* r10 temp register */
138 [AUX_REG] = 3, /* r11 temp register */
141 /* is_ereg() == true if BPF register 'reg' maps to x64 r8..r15
142 * which need extra byte of encoding.
143 * rax,rcx,...,rbp have simpler encoding
145 static bool is_ereg(u32 reg)
147 return (1 << reg) & (BIT(BPF_REG_5) |
155 /* add modifiers if 'reg' maps to x64 registers r8..r15 */
156 static u8 add_1mod(u8 byte, u32 reg)
163 static u8 add_2mod(u8 byte, u32 r1, u32 r2)
172 /* encode 'dst_reg' register into x64 opcode 'byte' */
173 static u8 add_1reg(u8 byte, u32 dst_reg)
175 return byte + reg2hex[dst_reg];
178 /* encode 'dst_reg' and 'src_reg' registers into x64 opcode 'byte' */
179 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
181 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
184 static void jit_fill_hole(void *area, unsigned int size)
186 /* fill whole space with int3 instructions */
187 memset(area, 0xcc, size);
191 int cleanup_addr; /* epilogue code offset */
196 /* maximum number of bytes emitted while JITing one eBPF insn */
197 #define BPF_MAX_INSN_SIZE 128
198 #define BPF_INSN_SAFETY 64
202 32 /* space for rbx, r13, r14, r15 */ + \
203 8 /* space for skb_copy_bits() buffer */)
205 #define PROLOGUE_SIZE 48
207 /* emit x64 prologue code for BPF program and check it's size.
208 * bpf_tail_call helper will skip it while jumping into another program
210 static void emit_prologue(u8 **pprog)
215 EMIT1(0x55); /* push rbp */
216 EMIT3(0x48, 0x89, 0xE5); /* mov rbp,rsp */
218 /* sub rsp, STACKSIZE */
219 EMIT3_off32(0x48, 0x81, 0xEC, STACKSIZE);
221 /* all classic BPF filters use R6(rbx) save it */
223 /* mov qword ptr [rbp-X],rbx */
224 EMIT3_off32(0x48, 0x89, 0x9D, -STACKSIZE);
226 /* bpf_convert_filter() maps classic BPF register X to R7 and uses R8
227 * as temporary, so all tcpdump filters need to spill/fill R7(r13) and
228 * R8(r14). R9(r15) spill could be made conditional, but there is only
229 * one 'bpf_error' return path out of helper functions inside bpf_jit.S
230 * The overhead of extra spill is negligible for any filter other
231 * than synthetic ones. Therefore not worth adding complexity.
234 /* mov qword ptr [rbp-X],r13 */
235 EMIT3_off32(0x4C, 0x89, 0xAD, -STACKSIZE + 8);
236 /* mov qword ptr [rbp-X],r14 */
237 EMIT3_off32(0x4C, 0x89, 0xB5, -STACKSIZE + 16);
238 /* mov qword ptr [rbp-X],r15 */
239 EMIT3_off32(0x4C, 0x89, 0xBD, -STACKSIZE + 24);
241 /* Clear the tail call counter (tail_call_cnt): for eBPF tail calls
242 * we need to reset the counter to 0. It's done in two instructions,
243 * resetting rax register to 0 (xor on eax gets 0 extended), and
244 * moving it to the counter location.
249 /* mov qword ptr [rbp-X], rax */
250 EMIT3_off32(0x48, 0x89, 0x85, -STACKSIZE + 32);
252 BUILD_BUG_ON(cnt != PROLOGUE_SIZE);
256 /* generate the following code:
257 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
258 * if (index >= array->map.max_entries)
260 * if (++tail_call_cnt > MAX_TAIL_CALL_CNT)
262 * prog = array->ptrs[index];
265 * goto *(prog->bpf_func + prologue_size);
268 static void emit_bpf_tail_call(u8 **pprog)
271 int label1, label2, label3;
274 /* rdi - pointer to ctx
275 * rsi - pointer to bpf_array
276 * rdx - index in bpf_array
279 /* if (index >= array->map.max_entries)
282 EMIT4(0x48, 0x8B, 0x46, /* mov rax, qword ptr [rsi + 16] */
283 offsetof(struct bpf_array, map.max_entries));
284 EMIT3(0x48, 0x39, 0xD0); /* cmp rax, rdx */
285 #define OFFSET1 47 /* number of bytes to jump */
286 EMIT2(X86_JBE, OFFSET1); /* jbe out */
289 /* if (tail_call_cnt > MAX_TAIL_CALL_CNT)
292 EMIT2_off32(0x8B, 0x85, -STACKSIZE + 36); /* mov eax, dword ptr [rbp - 516] */
293 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
295 EMIT2(X86_JA, OFFSET2); /* ja out */
297 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
298 EMIT2_off32(0x89, 0x85, -STACKSIZE + 36); /* mov dword ptr [rbp - 516], eax */
300 /* prog = array->ptrs[index]; */
301 EMIT4_off32(0x48, 0x8D, 0x84, 0xD6, /* lea rax, [rsi + rdx * 8 + offsetof(...)] */
302 offsetof(struct bpf_array, ptrs));
303 EMIT3(0x48, 0x8B, 0x00); /* mov rax, qword ptr [rax] */
308 EMIT4(0x48, 0x83, 0xF8, 0x00); /* cmp rax, 0 */
310 EMIT2(X86_JE, OFFSET3); /* je out */
313 /* goto *(prog->bpf_func + prologue_size); */
314 EMIT4(0x48, 0x8B, 0x40, /* mov rax, qword ptr [rax + 32] */
315 offsetof(struct bpf_prog, bpf_func));
316 EMIT4(0x48, 0x83, 0xC0, PROLOGUE_SIZE); /* add rax, prologue_size */
318 /* now we're ready to jump into next BPF program
319 * rdi == ctx (1st arg)
320 * rax == prog->bpf_func + prologue_size
322 EMIT2(0xFF, 0xE0); /* jmp rax */
325 BUILD_BUG_ON(cnt - label1 != OFFSET1);
326 BUILD_BUG_ON(cnt - label2 != OFFSET2);
327 BUILD_BUG_ON(cnt - label3 != OFFSET3);
332 static void emit_load_skb_data_hlen(u8 **pprog)
337 /* r9d = skb->len - skb->data_len (headlen)
340 /* mov %r9d, off32(%rdi) */
341 EMIT3_off32(0x44, 0x8b, 0x8f, offsetof(struct sk_buff, len));
343 /* sub %r9d, off32(%rdi) */
344 EMIT3_off32(0x44, 0x2b, 0x8f, offsetof(struct sk_buff, data_len));
346 /* mov %r10, off32(%rdi) */
347 EMIT3_off32(0x4c, 0x8b, 0x97, offsetof(struct sk_buff, data));
351 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
352 int oldproglen, struct jit_context *ctx)
354 struct bpf_insn *insn = bpf_prog->insnsi;
355 int insn_cnt = bpf_prog->len;
356 bool seen_ld_abs = ctx->seen_ld_abs | (oldproglen == 0);
357 bool seen_ax_reg = ctx->seen_ax_reg | (oldproglen == 0);
358 bool seen_exit = false;
359 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
364 emit_prologue(&prog);
367 emit_load_skb_data_hlen(&prog);
369 for (i = 0; i < insn_cnt; i++, insn++) {
370 const s32 imm32 = insn->imm;
371 u32 dst_reg = insn->dst_reg;
372 u32 src_reg = insn->src_reg;
373 u8 b1 = 0, b2 = 0, b3 = 0;
376 bool reload_skb_data;
380 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX)
381 ctx->seen_ax_reg = seen_ax_reg = true;
383 switch (insn->code) {
385 case BPF_ALU | BPF_ADD | BPF_X:
386 case BPF_ALU | BPF_SUB | BPF_X:
387 case BPF_ALU | BPF_AND | BPF_X:
388 case BPF_ALU | BPF_OR | BPF_X:
389 case BPF_ALU | BPF_XOR | BPF_X:
390 case BPF_ALU64 | BPF_ADD | BPF_X:
391 case BPF_ALU64 | BPF_SUB | BPF_X:
392 case BPF_ALU64 | BPF_AND | BPF_X:
393 case BPF_ALU64 | BPF_OR | BPF_X:
394 case BPF_ALU64 | BPF_XOR | BPF_X:
395 switch (BPF_OP(insn->code)) {
396 case BPF_ADD: b2 = 0x01; break;
397 case BPF_SUB: b2 = 0x29; break;
398 case BPF_AND: b2 = 0x21; break;
399 case BPF_OR: b2 = 0x09; break;
400 case BPF_XOR: b2 = 0x31; break;
402 if (BPF_CLASS(insn->code) == BPF_ALU64)
403 EMIT1(add_2mod(0x48, dst_reg, src_reg));
404 else if (is_ereg(dst_reg) || is_ereg(src_reg))
405 EMIT1(add_2mod(0x40, dst_reg, src_reg));
406 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
410 case BPF_ALU64 | BPF_MOV | BPF_X:
411 EMIT_mov(dst_reg, src_reg);
415 case BPF_ALU | BPF_MOV | BPF_X:
416 if (is_ereg(dst_reg) || is_ereg(src_reg))
417 EMIT1(add_2mod(0x40, dst_reg, src_reg));
418 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
422 case BPF_ALU | BPF_NEG:
423 case BPF_ALU64 | BPF_NEG:
424 if (BPF_CLASS(insn->code) == BPF_ALU64)
425 EMIT1(add_1mod(0x48, dst_reg));
426 else if (is_ereg(dst_reg))
427 EMIT1(add_1mod(0x40, dst_reg));
428 EMIT2(0xF7, add_1reg(0xD8, dst_reg));
431 case BPF_ALU | BPF_ADD | BPF_K:
432 case BPF_ALU | BPF_SUB | BPF_K:
433 case BPF_ALU | BPF_AND | BPF_K:
434 case BPF_ALU | BPF_OR | BPF_K:
435 case BPF_ALU | BPF_XOR | BPF_K:
436 case BPF_ALU64 | BPF_ADD | BPF_K:
437 case BPF_ALU64 | BPF_SUB | BPF_K:
438 case BPF_ALU64 | BPF_AND | BPF_K:
439 case BPF_ALU64 | BPF_OR | BPF_K:
440 case BPF_ALU64 | BPF_XOR | BPF_K:
441 if (BPF_CLASS(insn->code) == BPF_ALU64)
442 EMIT1(add_1mod(0x48, dst_reg));
443 else if (is_ereg(dst_reg))
444 EMIT1(add_1mod(0x40, dst_reg));
446 switch (BPF_OP(insn->code)) {
447 case BPF_ADD: b3 = 0xC0; break;
448 case BPF_SUB: b3 = 0xE8; break;
449 case BPF_AND: b3 = 0xE0; break;
450 case BPF_OR: b3 = 0xC8; break;
451 case BPF_XOR: b3 = 0xF0; break;
455 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
457 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
460 case BPF_ALU64 | BPF_MOV | BPF_K:
461 /* optimization: if imm32 is positive,
462 * use 'mov eax, imm32' (which zero-extends imm32)
466 /* 'mov rax, imm32' sign extends imm32 */
467 b1 = add_1mod(0x48, dst_reg);
470 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
474 case BPF_ALU | BPF_MOV | BPF_K:
475 /* optimization: if imm32 is zero, use 'xor <dst>,<dst>'
479 if (is_ereg(dst_reg))
480 EMIT1(add_2mod(0x40, dst_reg, dst_reg));
483 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
487 /* mov %eax, imm32 */
488 if (is_ereg(dst_reg))
489 EMIT1(add_1mod(0x40, dst_reg));
490 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
493 case BPF_LD | BPF_IMM | BPF_DW:
494 /* optimization: if imm64 is zero, use 'xor <dst>,<dst>'
497 if (insn[0].imm == 0 && insn[1].imm == 0) {
498 b1 = add_2mod(0x48, dst_reg, dst_reg);
501 EMIT3(b1, b2, add_2reg(b3, dst_reg, dst_reg));
508 /* movabsq %rax, imm64 */
509 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
510 EMIT(insn[0].imm, 4);
511 EMIT(insn[1].imm, 4);
517 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
518 case BPF_ALU | BPF_MOD | BPF_X:
519 case BPF_ALU | BPF_DIV | BPF_X:
520 case BPF_ALU | BPF_MOD | BPF_K:
521 case BPF_ALU | BPF_DIV | BPF_K:
522 case BPF_ALU64 | BPF_MOD | BPF_X:
523 case BPF_ALU64 | BPF_DIV | BPF_X:
524 case BPF_ALU64 | BPF_MOD | BPF_K:
525 case BPF_ALU64 | BPF_DIV | BPF_K:
526 EMIT1(0x50); /* push rax */
527 EMIT1(0x52); /* push rdx */
529 if (BPF_SRC(insn->code) == BPF_X)
530 /* mov r11, src_reg */
531 EMIT_mov(AUX_REG, src_reg);
534 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
536 /* mov rax, dst_reg */
537 EMIT_mov(BPF_REG_0, dst_reg);
540 * equivalent to 'xor rdx, rdx', but one byte less
544 if (BPF_SRC(insn->code) == BPF_X) {
545 /* if (src_reg == 0) return 0 */
548 EMIT4(0x49, 0x83, 0xFB, 0x00);
550 /* jne .+9 (skip over pop, pop, xor and jmp) */
551 EMIT2(X86_JNE, 1 + 1 + 2 + 5);
552 EMIT1(0x5A); /* pop rdx */
553 EMIT1(0x58); /* pop rax */
554 EMIT2(0x31, 0xc0); /* xor eax, eax */
557 * addrs[i] - 11, because there are 11 bytes
558 * after this insn: div, mov, pop, pop, mov
560 jmp_offset = ctx->cleanup_addr - (addrs[i] - 11);
561 EMIT1_off32(0xE9, jmp_offset);
564 if (BPF_CLASS(insn->code) == BPF_ALU64)
566 EMIT3(0x49, 0xF7, 0xF3);
569 EMIT3(0x41, 0xF7, 0xF3);
571 if (BPF_OP(insn->code) == BPF_MOD)
573 EMIT3(0x49, 0x89, 0xD3);
576 EMIT3(0x49, 0x89, 0xC3);
578 EMIT1(0x5A); /* pop rdx */
579 EMIT1(0x58); /* pop rax */
581 /* mov dst_reg, r11 */
582 EMIT_mov(dst_reg, AUX_REG);
585 case BPF_ALU | BPF_MUL | BPF_K:
586 case BPF_ALU | BPF_MUL | BPF_X:
587 case BPF_ALU64 | BPF_MUL | BPF_K:
588 case BPF_ALU64 | BPF_MUL | BPF_X:
589 EMIT1(0x50); /* push rax */
590 EMIT1(0x52); /* push rdx */
592 /* mov r11, dst_reg */
593 EMIT_mov(AUX_REG, dst_reg);
595 if (BPF_SRC(insn->code) == BPF_X)
596 /* mov rax, src_reg */
597 EMIT_mov(BPF_REG_0, src_reg);
600 EMIT3_off32(0x48, 0xC7, 0xC0, imm32);
602 if (BPF_CLASS(insn->code) == BPF_ALU64)
603 EMIT1(add_1mod(0x48, AUX_REG));
604 else if (is_ereg(AUX_REG))
605 EMIT1(add_1mod(0x40, AUX_REG));
607 EMIT2(0xF7, add_1reg(0xE0, AUX_REG));
610 EMIT_mov(AUX_REG, BPF_REG_0);
612 EMIT1(0x5A); /* pop rdx */
613 EMIT1(0x58); /* pop rax */
615 /* mov dst_reg, r11 */
616 EMIT_mov(dst_reg, AUX_REG);
620 case BPF_ALU | BPF_LSH | BPF_K:
621 case BPF_ALU | BPF_RSH | BPF_K:
622 case BPF_ALU | BPF_ARSH | BPF_K:
623 case BPF_ALU64 | BPF_LSH | BPF_K:
624 case BPF_ALU64 | BPF_RSH | BPF_K:
625 case BPF_ALU64 | BPF_ARSH | BPF_K:
626 if (BPF_CLASS(insn->code) == BPF_ALU64)
627 EMIT1(add_1mod(0x48, dst_reg));
628 else if (is_ereg(dst_reg))
629 EMIT1(add_1mod(0x40, dst_reg));
631 switch (BPF_OP(insn->code)) {
632 case BPF_LSH: b3 = 0xE0; break;
633 case BPF_RSH: b3 = 0xE8; break;
634 case BPF_ARSH: b3 = 0xF8; break;
636 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
639 case BPF_ALU | BPF_LSH | BPF_X:
640 case BPF_ALU | BPF_RSH | BPF_X:
641 case BPF_ALU | BPF_ARSH | BPF_X:
642 case BPF_ALU64 | BPF_LSH | BPF_X:
643 case BPF_ALU64 | BPF_RSH | BPF_X:
644 case BPF_ALU64 | BPF_ARSH | BPF_X:
646 /* check for bad case when dst_reg == rcx */
647 if (dst_reg == BPF_REG_4) {
648 /* mov r11, dst_reg */
649 EMIT_mov(AUX_REG, dst_reg);
653 if (src_reg != BPF_REG_4) { /* common case */
654 EMIT1(0x51); /* push rcx */
656 /* mov rcx, src_reg */
657 EMIT_mov(BPF_REG_4, src_reg);
660 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
661 if (BPF_CLASS(insn->code) == BPF_ALU64)
662 EMIT1(add_1mod(0x48, dst_reg));
663 else if (is_ereg(dst_reg))
664 EMIT1(add_1mod(0x40, dst_reg));
666 switch (BPF_OP(insn->code)) {
667 case BPF_LSH: b3 = 0xE0; break;
668 case BPF_RSH: b3 = 0xE8; break;
669 case BPF_ARSH: b3 = 0xF8; break;
671 EMIT2(0xD3, add_1reg(b3, dst_reg));
673 if (src_reg != BPF_REG_4)
674 EMIT1(0x59); /* pop rcx */
676 if (insn->dst_reg == BPF_REG_4)
677 /* mov dst_reg, r11 */
678 EMIT_mov(insn->dst_reg, AUX_REG);
681 case BPF_ALU | BPF_END | BPF_FROM_BE:
684 /* emit 'ror %ax, 8' to swap lower 2 bytes */
686 if (is_ereg(dst_reg))
688 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
690 /* emit 'movzwl eax, ax' */
691 if (is_ereg(dst_reg))
692 EMIT3(0x45, 0x0F, 0xB7);
695 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
698 /* emit 'bswap eax' to swap lower 4 bytes */
699 if (is_ereg(dst_reg))
703 EMIT1(add_1reg(0xC8, dst_reg));
706 /* emit 'bswap rax' to swap 8 bytes */
707 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
708 add_1reg(0xC8, dst_reg));
713 case BPF_ALU | BPF_END | BPF_FROM_LE:
716 /* emit 'movzwl eax, ax' to zero extend 16-bit
719 if (is_ereg(dst_reg))
720 EMIT3(0x45, 0x0F, 0xB7);
723 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
726 /* emit 'mov eax, eax' to clear upper 32-bits */
727 if (is_ereg(dst_reg))
729 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
737 /* ST: *(u8*)(dst_reg + off) = imm */
738 case BPF_ST | BPF_MEM | BPF_B:
739 if (is_ereg(dst_reg))
744 case BPF_ST | BPF_MEM | BPF_H:
745 if (is_ereg(dst_reg))
746 EMIT3(0x66, 0x41, 0xC7);
750 case BPF_ST | BPF_MEM | BPF_W:
751 if (is_ereg(dst_reg))
756 case BPF_ST | BPF_MEM | BPF_DW:
757 EMIT2(add_1mod(0x48, dst_reg), 0xC7);
759 st: if (is_imm8(insn->off))
760 EMIT2(add_1reg(0x40, dst_reg), insn->off);
762 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
764 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
767 /* STX: *(u8*)(dst_reg + off) = src_reg */
768 case BPF_STX | BPF_MEM | BPF_B:
769 /* emit 'mov byte ptr [rax + off], al' */
770 if (is_ereg(dst_reg) || is_ereg(src_reg) ||
771 /* have to add extra byte for x86 SIL, DIL regs */
772 src_reg == BPF_REG_1 || src_reg == BPF_REG_2)
773 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
777 case BPF_STX | BPF_MEM | BPF_H:
778 if (is_ereg(dst_reg) || is_ereg(src_reg))
779 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
783 case BPF_STX | BPF_MEM | BPF_W:
784 if (is_ereg(dst_reg) || is_ereg(src_reg))
785 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
789 case BPF_STX | BPF_MEM | BPF_DW:
790 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
791 stx: if (is_imm8(insn->off))
792 EMIT2(add_2reg(0x40, dst_reg, src_reg), insn->off);
794 EMIT1_off32(add_2reg(0x80, dst_reg, src_reg),
798 /* LDX: dst_reg = *(u8*)(src_reg + off) */
799 case BPF_LDX | BPF_MEM | BPF_B:
800 /* emit 'movzx rax, byte ptr [rax + off]' */
801 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
803 case BPF_LDX | BPF_MEM | BPF_H:
804 /* emit 'movzx rax, word ptr [rax + off]' */
805 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
807 case BPF_LDX | BPF_MEM | BPF_W:
808 /* emit 'mov eax, dword ptr [rax+0x14]' */
809 if (is_ereg(dst_reg) || is_ereg(src_reg))
810 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
814 case BPF_LDX | BPF_MEM | BPF_DW:
815 /* emit 'mov rax, qword ptr [rax+0x14]' */
816 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
817 ldx: /* if insn->off == 0 we can save one extra byte, but
818 * special case of x86 r13 which always needs an offset
819 * is not worth the hassle
821 if (is_imm8(insn->off))
822 EMIT2(add_2reg(0x40, src_reg, dst_reg), insn->off);
824 EMIT1_off32(add_2reg(0x80, src_reg, dst_reg),
828 /* STX XADD: lock *(u32*)(dst_reg + off) += src_reg */
829 case BPF_STX | BPF_XADD | BPF_W:
830 /* emit 'lock add dword ptr [rax + off], eax' */
831 if (is_ereg(dst_reg) || is_ereg(src_reg))
832 EMIT3(0xF0, add_2mod(0x40, dst_reg, src_reg), 0x01);
836 case BPF_STX | BPF_XADD | BPF_DW:
837 EMIT3(0xF0, add_2mod(0x48, dst_reg, src_reg), 0x01);
838 xadd: if (is_imm8(insn->off))
839 EMIT2(add_2reg(0x40, dst_reg, src_reg), insn->off);
841 EMIT1_off32(add_2reg(0x80, dst_reg, src_reg),
846 case BPF_JMP | BPF_CALL:
847 func = (u8 *) __bpf_call_base + imm32;
848 jmp_offset = func - (image + addrs[i]);
850 reload_skb_data = bpf_helper_changes_pkt_data(func);
851 if (reload_skb_data) {
852 EMIT1(0x57); /* push %rdi */
853 jmp_offset += 22; /* pop, mov, sub, mov */
855 EMIT2(0x41, 0x52); /* push %r10 */
856 EMIT2(0x41, 0x51); /* push %r9 */
857 /* need to adjust jmp offset, since
858 * pop %r9, pop %r10 take 4 bytes after call insn
863 if (!imm32 || !is_simm32(jmp_offset)) {
864 pr_err("unsupported bpf func %d addr %p image %p\n",
868 EMIT1_off32(0xE8, jmp_offset);
870 if (reload_skb_data) {
871 EMIT1(0x5F); /* pop %rdi */
872 emit_load_skb_data_hlen(&prog);
874 EMIT2(0x41, 0x59); /* pop %r9 */
875 EMIT2(0x41, 0x5A); /* pop %r10 */
880 case BPF_JMP | BPF_CALL | BPF_X:
881 emit_bpf_tail_call(&prog);
885 case BPF_JMP | BPF_JEQ | BPF_X:
886 case BPF_JMP | BPF_JNE | BPF_X:
887 case BPF_JMP | BPF_JGT | BPF_X:
888 case BPF_JMP | BPF_JGE | BPF_X:
889 case BPF_JMP | BPF_JSGT | BPF_X:
890 case BPF_JMP | BPF_JSGE | BPF_X:
891 /* cmp dst_reg, src_reg */
892 EMIT3(add_2mod(0x48, dst_reg, src_reg), 0x39,
893 add_2reg(0xC0, dst_reg, src_reg));
896 case BPF_JMP | BPF_JSET | BPF_X:
897 /* test dst_reg, src_reg */
898 EMIT3(add_2mod(0x48, dst_reg, src_reg), 0x85,
899 add_2reg(0xC0, dst_reg, src_reg));
902 case BPF_JMP | BPF_JSET | BPF_K:
903 /* test dst_reg, imm32 */
904 EMIT1(add_1mod(0x48, dst_reg));
905 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
908 case BPF_JMP | BPF_JEQ | BPF_K:
909 case BPF_JMP | BPF_JNE | BPF_K:
910 case BPF_JMP | BPF_JGT | BPF_K:
911 case BPF_JMP | BPF_JGE | BPF_K:
912 case BPF_JMP | BPF_JSGT | BPF_K:
913 case BPF_JMP | BPF_JSGE | BPF_K:
914 /* cmp dst_reg, imm8/32 */
915 EMIT1(add_1mod(0x48, dst_reg));
918 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
920 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
922 emit_cond_jmp: /* convert BPF opcode to x86 */
923 switch (BPF_OP(insn->code)) {
932 /* GT is unsigned '>', JA in x86 */
936 /* GE is unsigned '>=', JAE in x86 */
940 /* signed '>', GT in x86 */
944 /* signed '>=', GE in x86 */
947 default: /* to silence gcc warning */
950 jmp_offset = addrs[i + insn->off] - addrs[i];
951 if (is_imm8(jmp_offset)) {
952 EMIT2(jmp_cond, jmp_offset);
953 } else if (is_simm32(jmp_offset)) {
954 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
956 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
962 case BPF_JMP | BPF_JA:
963 jmp_offset = addrs[i + insn->off] - addrs[i];
965 /* optimize out nop jumps */
968 if (is_imm8(jmp_offset)) {
969 EMIT2(0xEB, jmp_offset);
970 } else if (is_simm32(jmp_offset)) {
971 EMIT1_off32(0xE9, jmp_offset);
973 pr_err("jmp gen bug %llx\n", jmp_offset);
978 case BPF_LD | BPF_IND | BPF_W:
981 case BPF_LD | BPF_ABS | BPF_W:
982 func = CHOOSE_LOAD_FUNC(imm32, sk_load_word);
984 ctx->seen_ld_abs = seen_ld_abs = true;
985 jmp_offset = func - (image + addrs[i]);
986 if (!func || !is_simm32(jmp_offset)) {
987 pr_err("unsupported bpf func %d addr %p image %p\n",
991 if (BPF_MODE(insn->code) == BPF_ABS) {
992 /* mov %esi, imm32 */
993 EMIT1_off32(0xBE, imm32);
995 /* mov %rsi, src_reg */
996 EMIT_mov(BPF_REG_2, src_reg);
1000 EMIT3(0x83, 0xC6, imm32);
1002 /* add %esi, imm32 */
1003 EMIT2_off32(0x81, 0xC6, imm32);
1006 /* skb pointer is in R6 (%rbx), it will be copied into
1007 * %rdi if skb_copy_bits() call is necessary.
1008 * sk_load_* helpers also use %r10 and %r9d.
1012 /* r10 = skb->data, mov %r10, off32(%rbx) */
1013 EMIT3_off32(0x4c, 0x8b, 0x93,
1014 offsetof(struct sk_buff, data));
1015 EMIT1_off32(0xE8, jmp_offset); /* call */
1018 case BPF_LD | BPF_IND | BPF_H:
1019 func = sk_load_half;
1021 case BPF_LD | BPF_ABS | BPF_H:
1022 func = CHOOSE_LOAD_FUNC(imm32, sk_load_half);
1024 case BPF_LD | BPF_IND | BPF_B:
1025 func = sk_load_byte;
1027 case BPF_LD | BPF_ABS | BPF_B:
1028 func = CHOOSE_LOAD_FUNC(imm32, sk_load_byte);
1031 case BPF_JMP | BPF_EXIT:
1033 jmp_offset = ctx->cleanup_addr - addrs[i];
1037 /* update cleanup_addr */
1038 ctx->cleanup_addr = proglen;
1039 /* mov rbx, qword ptr [rbp-X] */
1040 EMIT3_off32(0x48, 0x8B, 0x9D, -STACKSIZE);
1041 /* mov r13, qword ptr [rbp-X] */
1042 EMIT3_off32(0x4C, 0x8B, 0xAD, -STACKSIZE + 8);
1043 /* mov r14, qword ptr [rbp-X] */
1044 EMIT3_off32(0x4C, 0x8B, 0xB5, -STACKSIZE + 16);
1045 /* mov r15, qword ptr [rbp-X] */
1046 EMIT3_off32(0x4C, 0x8B, 0xBD, -STACKSIZE + 24);
1048 EMIT1(0xC9); /* leave */
1049 EMIT1(0xC3); /* ret */
1053 /* By design x64 JIT should support all BPF instructions
1054 * This error will be seen if new instruction was added
1055 * to interpreter, but not to JIT
1056 * or if there is junk in bpf_prog
1058 pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
1063 if (ilen > BPF_MAX_INSN_SIZE) {
1064 pr_err("bpf_jit: fatal insn size error\n");
1069 if (unlikely(proglen + ilen > oldproglen)) {
1070 pr_err("bpf_jit: fatal error\n");
1073 memcpy(image + proglen, temp, ilen);
1082 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
1084 struct bpf_binary_header *header = NULL;
1085 struct bpf_prog *tmp, *orig_prog = prog;
1086 int proglen, oldproglen = 0;
1087 struct jit_context ctx = {};
1088 bool tmp_blinded = false;
1094 if (!bpf_jit_enable)
1097 tmp = bpf_jit_blind_constants(prog);
1098 /* If blinding was requested and we failed during blinding,
1099 * we must fall back to the interpreter.
1108 addrs = kmalloc(prog->len * sizeof(*addrs), GFP_KERNEL);
1114 /* Before first pass, make a rough estimation of addrs[]
1115 * each bpf instruction is translated to less than 64 bytes
1117 for (proglen = 0, i = 0; i < prog->len; i++) {
1121 ctx.cleanup_addr = proglen;
1123 /* JITed image shrinks with every pass and the loop iterates
1124 * until the image stops shrinking. Very large bpf programs
1125 * may converge on the last pass. In such case do one more
1126 * pass to emit the final image
1128 for (pass = 0; pass < 10 || image; pass++) {
1129 proglen = do_jit(prog, addrs, image, oldproglen, &ctx);
1133 bpf_jit_binary_free(header);
1138 if (proglen != oldproglen) {
1139 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
1140 proglen, oldproglen);
1146 if (proglen == oldproglen) {
1147 header = bpf_jit_binary_alloc(proglen, &image,
1154 oldproglen = proglen;
1157 if (bpf_jit_enable > 1)
1158 bpf_jit_dump(prog->len, proglen, pass + 1, image);
1161 bpf_flush_icache(header, image + proglen);
1162 bpf_jit_binary_lock_ro(header);
1163 prog->bpf_func = (void *)image;
1173 bpf_jit_prog_release_other(prog, prog == orig_prog ?