1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
6 * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
8 #include <linux/netdevice.h>
9 #include <linux/filter.h>
10 #include <linux/if_vlan.h>
11 #include <linux/bpf.h>
12 #include <linux/memory.h>
13 #include <linux/sort.h>
14 #include <asm/extable.h>
15 #include <asm/ftrace.h>
16 #include <asm/set_memory.h>
17 #include <asm/nospec-branch.h>
18 #include <asm/text-patching.h>
20 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
33 #define EMIT(bytes, len) \
34 do { prog = emit_code(prog, bytes, len); } while (0)
36 #define EMIT1(b1) EMIT(b1, 1)
37 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2)
38 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
39 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
41 #define EMIT1_off32(b1, off) \
42 do { EMIT1(b1); EMIT(off, 4); } while (0)
43 #define EMIT2_off32(b1, b2, off) \
44 do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
45 #define EMIT3_off32(b1, b2, b3, off) \
46 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
47 #define EMIT4_off32(b1, b2, b3, b4, off) \
48 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
50 #ifdef CONFIG_X86_KERNEL_IBT
51 #define EMIT_ENDBR() EMIT(gen_endbr(), 4)
56 static bool is_imm8(int value)
58 return value <= 127 && value >= -128;
61 static bool is_simm32(s64 value)
63 return value == (s64)(s32)value;
66 static bool is_uimm32(u64 value)
68 return value == (u64)(u32)value;
72 #define EMIT_mov(DST, SRC) \
75 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
78 static int bpf_size_to_x86_bytes(int bpf_size)
80 if (bpf_size == BPF_W)
82 else if (bpf_size == BPF_H)
84 else if (bpf_size == BPF_B)
86 else if (bpf_size == BPF_DW)
93 * List of x86 cond jumps opcodes (. + s8)
94 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
107 /* Pick a register outside of BPF range for JIT internal work */
108 #define AUX_REG (MAX_BPF_JIT_REG + 1)
109 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2)
112 * The following table maps BPF registers to x86-64 registers.
114 * x86-64 register R12 is unused, since if used as base address
115 * register in load/store instructions, it always needs an
116 * extra byte of encoding and is callee saved.
118 * x86-64 register R9 is not used by BPF programs, but can be used by BPF
119 * trampoline. x86-64 register R10 is used for blinding (if enabled).
121 static const int reg2hex[] = {
122 [BPF_REG_0] = 0, /* RAX */
123 [BPF_REG_1] = 7, /* RDI */
124 [BPF_REG_2] = 6, /* RSI */
125 [BPF_REG_3] = 2, /* RDX */
126 [BPF_REG_4] = 1, /* RCX */
127 [BPF_REG_5] = 0, /* R8 */
128 [BPF_REG_6] = 3, /* RBX callee saved */
129 [BPF_REG_7] = 5, /* R13 callee saved */
130 [BPF_REG_8] = 6, /* R14 callee saved */
131 [BPF_REG_9] = 7, /* R15 callee saved */
132 [BPF_REG_FP] = 5, /* RBP readonly */
133 [BPF_REG_AX] = 2, /* R10 temp register */
134 [AUX_REG] = 3, /* R11 temp register */
135 [X86_REG_R9] = 1, /* R9 register, 6th function argument */
138 static const int reg2pt_regs[] = {
139 [BPF_REG_0] = offsetof(struct pt_regs, ax),
140 [BPF_REG_1] = offsetof(struct pt_regs, di),
141 [BPF_REG_2] = offsetof(struct pt_regs, si),
142 [BPF_REG_3] = offsetof(struct pt_regs, dx),
143 [BPF_REG_4] = offsetof(struct pt_regs, cx),
144 [BPF_REG_5] = offsetof(struct pt_regs, r8),
145 [BPF_REG_6] = offsetof(struct pt_regs, bx),
146 [BPF_REG_7] = offsetof(struct pt_regs, r13),
147 [BPF_REG_8] = offsetof(struct pt_regs, r14),
148 [BPF_REG_9] = offsetof(struct pt_regs, r15),
152 * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15
153 * which need extra byte of encoding.
154 * rax,rcx,...,rbp have simpler encoding
156 static bool is_ereg(u32 reg)
158 return (1 << reg) & (BIT(BPF_REG_5) |
168 * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64
169 * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte
170 * of encoding. al,cl,dl,bl have simpler encoding.
172 static bool is_ereg_8l(u32 reg)
174 return is_ereg(reg) ||
175 (1 << reg) & (BIT(BPF_REG_1) |
180 static bool is_axreg(u32 reg)
182 return reg == BPF_REG_0;
185 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */
186 static u8 add_1mod(u8 byte, u32 reg)
193 static u8 add_2mod(u8 byte, u32 r1, u32 r2)
202 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */
203 static u8 add_1reg(u8 byte, u32 dst_reg)
205 return byte + reg2hex[dst_reg];
208 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */
209 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
211 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
214 /* Some 1-byte opcodes for binary ALU operations */
215 static u8 simple_alu_opcodes[] = {
226 static void jit_fill_hole(void *area, unsigned int size)
228 /* Fill whole space with INT3 instructions */
229 memset(area, 0xcc, size);
232 int bpf_arch_text_invalidate(void *dst, size_t len)
234 return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len));
238 int cleanup_addr; /* Epilogue code offset */
241 * Program specific offsets of labels in the code; these rely on the
242 * JIT doing at least 2 passes, recording the position on the first
243 * pass, only to generate the correct offset on the second pass.
245 int tail_call_direct_label;
246 int tail_call_indirect_label;
249 /* Maximum number of bytes emitted while JITing one eBPF insn */
250 #define BPF_MAX_INSN_SIZE 128
251 #define BPF_INSN_SAFETY 64
253 /* Number of bytes emit_patch() needs to generate instructions */
254 #define X86_PATCH_SIZE 5
255 /* Number of bytes that will be skipped on tailcall */
256 #define X86_TAIL_CALL_OFFSET (11 + ENDBR_INSN_SIZE)
258 static void push_callee_regs(u8 **pprog, bool *callee_regs_used)
262 if (callee_regs_used[0])
263 EMIT1(0x53); /* push rbx */
264 if (callee_regs_used[1])
265 EMIT2(0x41, 0x55); /* push r13 */
266 if (callee_regs_used[2])
267 EMIT2(0x41, 0x56); /* push r14 */
268 if (callee_regs_used[3])
269 EMIT2(0x41, 0x57); /* push r15 */
273 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used)
277 if (callee_regs_used[3])
278 EMIT2(0x41, 0x5F); /* pop r15 */
279 if (callee_regs_used[2])
280 EMIT2(0x41, 0x5E); /* pop r14 */
281 if (callee_regs_used[1])
282 EMIT2(0x41, 0x5D); /* pop r13 */
283 if (callee_regs_used[0])
284 EMIT1(0x5B); /* pop rbx */
289 * Emit x86-64 prologue code for BPF program.
290 * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes
291 * while jumping to another program
293 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf,
294 bool tail_call_reachable, bool is_subprog)
298 /* BPF trampoline can be made to work without these nops,
299 * but let's waste 5 bytes for now and optimize later
302 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
303 prog += X86_PATCH_SIZE;
304 if (!ebpf_from_cbpf) {
305 if (tail_call_reachable && !is_subprog)
306 EMIT2(0x31, 0xC0); /* xor eax, eax */
308 EMIT2(0x66, 0x90); /* nop2 */
310 EMIT1(0x55); /* push rbp */
311 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
313 /* X86_TAIL_CALL_OFFSET is here */
316 /* sub rsp, rounded_stack_depth */
318 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8));
319 if (tail_call_reachable)
320 EMIT1(0x50); /* push rax */
324 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode)
329 offset = func - (ip + X86_PATCH_SIZE);
330 if (!is_simm32(offset)) {
331 pr_err("Target call %p is out of range\n", func);
334 EMIT1_off32(opcode, offset);
339 static int emit_call(u8 **pprog, void *func, void *ip)
341 return emit_patch(pprog, func, ip, 0xE8);
344 static int emit_rsb_call(u8 **pprog, void *func, void *ip)
346 OPTIMIZER_HIDE_VAR(func);
347 x86_call_depth_emit_accounting(pprog, func);
348 return emit_patch(pprog, func, ip, 0xE8);
351 static int emit_jump(u8 **pprog, void *func, void *ip)
353 return emit_patch(pprog, func, ip, 0xE9);
356 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
357 void *old_addr, void *new_addr)
359 const u8 *nop_insn = x86_nops[5];
360 u8 old_insn[X86_PATCH_SIZE];
361 u8 new_insn[X86_PATCH_SIZE];
365 memcpy(old_insn, nop_insn, X86_PATCH_SIZE);
368 ret = t == BPF_MOD_CALL ?
369 emit_call(&prog, old_addr, ip) :
370 emit_jump(&prog, old_addr, ip);
375 memcpy(new_insn, nop_insn, X86_PATCH_SIZE);
378 ret = t == BPF_MOD_CALL ?
379 emit_call(&prog, new_addr, ip) :
380 emit_jump(&prog, new_addr, ip);
386 mutex_lock(&text_mutex);
387 if (memcmp(ip, old_insn, X86_PATCH_SIZE))
390 if (memcmp(ip, new_insn, X86_PATCH_SIZE)) {
391 text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL);
395 mutex_unlock(&text_mutex);
399 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
400 void *old_addr, void *new_addr)
402 if (!is_kernel_text((long)ip) &&
403 !is_bpf_text_address((long)ip))
404 /* BPF poking in modules is not supported */
408 * See emit_prologue(), for IBT builds the trampoline hook is preceded
409 * with an ENDBR instruction.
411 if (is_endbr(*(u32 *)ip))
412 ip += ENDBR_INSN_SIZE;
414 return __bpf_arch_text_poke(ip, t, old_addr, new_addr);
417 #define EMIT_LFENCE() EMIT3(0x0F, 0xAE, 0xE8)
419 static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip)
423 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) {
425 EMIT2(0xFF, 0xE0 + reg);
426 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) {
427 OPTIMIZER_HIDE_VAR(reg);
428 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH))
429 emit_jump(&prog, &__x86_indirect_jump_thunk_array[reg], ip);
431 emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip);
433 EMIT2(0xFF, 0xE0 + reg); /* jmp *%\reg */
434 if (IS_ENABLED(CONFIG_RETPOLINE) || IS_ENABLED(CONFIG_SLS))
435 EMIT1(0xCC); /* int3 */
441 static void emit_return(u8 **pprog, u8 *ip)
445 if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) {
446 emit_jump(&prog, x86_return_thunk, ip);
448 EMIT1(0xC3); /* ret */
449 if (IS_ENABLED(CONFIG_SLS))
450 EMIT1(0xCC); /* int3 */
457 * Generate the following code:
459 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
460 * if (index >= array->map.max_entries)
462 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
464 * prog = array->ptrs[index];
467 * goto *(prog->bpf_func + prologue_size);
470 static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used,
471 u32 stack_depth, u8 *ip,
472 struct jit_context *ctx)
474 int tcc_off = -4 - round_up(stack_depth, 8);
475 u8 *prog = *pprog, *start = *pprog;
479 * rdi - pointer to ctx
480 * rsi - pointer to bpf_array
481 * rdx - index in bpf_array
485 * if (index >= array->map.max_entries)
488 EMIT2(0x89, 0xD2); /* mov edx, edx */
489 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */
490 offsetof(struct bpf_array, map.max_entries));
492 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
493 EMIT2(X86_JBE, offset); /* jbe out */
496 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
499 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */
500 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
502 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
503 EMIT2(X86_JAE, offset); /* jae out */
504 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
505 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */
507 /* prog = array->ptrs[index]; */
508 EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6, /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */
509 offsetof(struct bpf_array, ptrs));
515 EMIT3(0x48, 0x85, 0xC9); /* test rcx,rcx */
517 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
518 EMIT2(X86_JE, offset); /* je out */
520 pop_callee_regs(&prog, callee_regs_used);
522 EMIT1(0x58); /* pop rax */
524 EMIT3_off32(0x48, 0x81, 0xC4, /* add rsp, sd */
525 round_up(stack_depth, 8));
527 /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */
528 EMIT4(0x48, 0x8B, 0x49, /* mov rcx, qword ptr [rcx + 32] */
529 offsetof(struct bpf_prog, bpf_func));
530 EMIT4(0x48, 0x83, 0xC1, /* add rcx, X86_TAIL_CALL_OFFSET */
531 X86_TAIL_CALL_OFFSET);
533 * Now we're ready to jump into next BPF program
534 * rdi == ctx (1st arg)
535 * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET
537 emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start));
540 ctx->tail_call_indirect_label = prog - start;
544 static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke,
546 bool *callee_regs_used, u32 stack_depth,
547 struct jit_context *ctx)
549 int tcc_off = -4 - round_up(stack_depth, 8);
550 u8 *prog = *pprog, *start = *pprog;
554 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
557 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */
558 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
560 offset = ctx->tail_call_direct_label - (prog + 2 - start);
561 EMIT2(X86_JAE, offset); /* jae out */
562 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
563 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */
565 poke->tailcall_bypass = ip + (prog - start);
566 poke->adj_off = X86_TAIL_CALL_OFFSET;
567 poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE;
568 poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE;
570 emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE,
571 poke->tailcall_bypass);
573 pop_callee_regs(&prog, callee_regs_used);
574 EMIT1(0x58); /* pop rax */
576 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8));
578 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
579 prog += X86_PATCH_SIZE;
582 ctx->tail_call_direct_label = prog - start;
587 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog)
589 struct bpf_jit_poke_descriptor *poke;
590 struct bpf_array *array;
591 struct bpf_prog *target;
594 for (i = 0; i < prog->aux->size_poke_tab; i++) {
595 poke = &prog->aux->poke_tab[i];
596 if (poke->aux && poke->aux != prog->aux)
599 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable));
601 if (poke->reason != BPF_POKE_REASON_TAIL_CALL)
604 array = container_of(poke->tail_call.map, struct bpf_array, map);
605 mutex_lock(&array->aux->poke_mutex);
606 target = array->ptrs[poke->tail_call.key];
608 ret = __bpf_arch_text_poke(poke->tailcall_target,
610 (u8 *)target->bpf_func +
613 ret = __bpf_arch_text_poke(poke->tailcall_bypass,
615 (u8 *)poke->tailcall_target +
616 X86_PATCH_SIZE, NULL);
619 WRITE_ONCE(poke->tailcall_target_stable, true);
620 mutex_unlock(&array->aux->poke_mutex);
624 static void emit_mov_imm32(u8 **pprog, bool sign_propagate,
625 u32 dst_reg, const u32 imm32)
631 * Optimization: if imm32 is positive, use 'mov %eax, imm32'
632 * (which zero-extends imm32) to save 2 bytes.
634 if (sign_propagate && (s32)imm32 < 0) {
635 /* 'mov %rax, imm32' sign extends imm32 */
636 b1 = add_1mod(0x48, dst_reg);
639 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
644 * Optimization: if imm32 is zero, use 'xor %eax, %eax'
648 if (is_ereg(dst_reg))
649 EMIT1(add_2mod(0x40, dst_reg, dst_reg));
652 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
656 /* mov %eax, imm32 */
657 if (is_ereg(dst_reg))
658 EMIT1(add_1mod(0x40, dst_reg));
659 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
664 static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
665 const u32 imm32_hi, const u32 imm32_lo)
669 if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
671 * For emitting plain u32, where sign bit must not be
672 * propagated LLVM tends to load imm64 over mov32
673 * directly, so save couple of bytes by just doing
674 * 'mov %eax, imm32' instead.
676 emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
678 /* movabsq rax, imm64 */
679 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
687 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg)
693 EMIT_mov(dst_reg, src_reg);
696 if (is_ereg(dst_reg) || is_ereg(src_reg))
697 EMIT1(add_2mod(0x40, dst_reg, src_reg));
698 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
704 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */
705 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off)
710 /* 1-byte signed displacement.
712 * If off == 0 we could skip this and save one extra byte, but
713 * special case of x86 R13 which always needs an offset is not
716 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off);
718 /* 4-byte signed displacement */
719 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off);
725 * Emit a REX byte if it will be necessary to address these registers
727 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64)
732 EMIT1(add_2mod(0x48, dst_reg, src_reg));
733 else if (is_ereg(dst_reg) || is_ereg(src_reg))
734 EMIT1(add_2mod(0x40, dst_reg, src_reg));
739 * Similar version of maybe_emit_mod() for a single register
741 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64)
746 EMIT1(add_1mod(0x48, reg));
747 else if (is_ereg(reg))
748 EMIT1(add_1mod(0x40, reg));
752 /* LDX: dst_reg = *(u8*)(src_reg + off) */
753 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
759 /* Emit 'movzx rax, byte ptr [rax + off]' */
760 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
763 /* Emit 'movzx rax, word ptr [rax + off]' */
764 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
767 /* Emit 'mov eax, dword ptr [rax+0x14]' */
768 if (is_ereg(dst_reg) || is_ereg(src_reg))
769 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
774 /* Emit 'mov rax, qword ptr [rax+0x14]' */
775 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
778 emit_insn_suffix(&prog, src_reg, dst_reg, off);
782 /* STX: *(u8*)(dst_reg + off) = src_reg */
783 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
789 /* Emit 'mov byte ptr [rax + off], al' */
790 if (is_ereg(dst_reg) || is_ereg_8l(src_reg))
791 /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */
792 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
797 if (is_ereg(dst_reg) || is_ereg(src_reg))
798 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
803 if (is_ereg(dst_reg) || is_ereg(src_reg))
804 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
809 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
812 emit_insn_suffix(&prog, dst_reg, src_reg, off);
816 static int emit_atomic(u8 **pprog, u8 atomic_op,
817 u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size)
821 EMIT1(0xF0); /* lock prefix */
823 maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW);
831 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */
832 EMIT1(simple_alu_opcodes[atomic_op]);
834 case BPF_ADD | BPF_FETCH:
835 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */
839 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */
843 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */
847 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op);
851 emit_insn_suffix(&prog, dst_reg, src_reg, off);
857 bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs)
859 u32 reg = x->fixup >> 8;
861 /* jump over faulting load and clear dest register */
862 *(unsigned long *)((void *)regs + reg) = 0;
863 regs->ip += x->fixup & 0xff;
867 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt,
868 bool *regs_used, bool *tail_call_seen)
872 for (i = 1; i <= insn_cnt; i++, insn++) {
873 if (insn->code == (BPF_JMP | BPF_TAIL_CALL))
874 *tail_call_seen = true;
875 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6)
877 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7)
879 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8)
881 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9)
886 static void emit_nops(u8 **pprog, int len)
894 if (noplen > ASM_NOP_MAX)
895 noplen = ASM_NOP_MAX;
897 for (i = 0; i < noplen; i++)
898 EMIT1(x86_nops[noplen][i]);
905 /* emit the 3-byte VEX prefix
907 * r: same as rex.r, extra bit for ModRM reg field
908 * x: same as rex.x, extra bit for SIB index field
909 * b: same as rex.b, extra bit for ModRM r/m, or SIB base
910 * m: opcode map select, encoding escape bytes e.g. 0x0f38
911 * w: same as rex.w (32 bit or 64 bit) or opcode specific
912 * src_reg2: additional source reg (encoded as BPF reg)
913 * l: vector length (128 bit or 256 bit) or reserved
914 * pp: opcode prefix (none, 0x66, 0xf2 or 0xf3)
916 static void emit_3vex(u8 **pprog, bool r, bool x, bool b, u8 m,
917 bool w, u8 src_reg2, bool l, u8 pp)
920 const u8 b0 = 0xc4; /* first byte of 3-byte VEX prefix */
922 u8 vvvv = reg2hex[src_reg2];
924 /* reg2hex gives only the lower 3 bit of vvvv */
925 if (is_ereg(src_reg2))
929 * 2nd byte of 3-byte VEX prefix
930 * ~ means bit inverted encoding
933 * +---+---+---+---+---+---+---+---+
935 * +---+---+---+---+---+---+---+---+
937 b1 = (!r << 7) | (!x << 6) | (!b << 5) | (m & 0x1f);
939 * 3rd byte of 3-byte VEX prefix
942 * +---+---+---+---+---+---+---+---+
943 * | W | ~vvvv | L | pp |
944 * +---+---+---+---+---+---+---+---+
946 b2 = (w << 7) | ((~vvvv & 0xf) << 3) | (l << 2) | (pp & 3);
952 /* emit BMI2 shift instruction */
953 static void emit_shiftx(u8 **pprog, u32 dst_reg, u8 src_reg, bool is64, u8 op)
956 bool r = is_ereg(dst_reg);
957 u8 m = 2; /* escape code 0f38 */
959 emit_3vex(&prog, r, false, r, m, is64, src_reg, false, op);
960 EMIT2(0xf7, add_2reg(0xC0, dst_reg, dst_reg));
964 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp)))
966 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image,
967 int oldproglen, struct jit_context *ctx, bool jmp_padding)
969 bool tail_call_reachable = bpf_prog->aux->tail_call_reachable;
970 struct bpf_insn *insn = bpf_prog->insnsi;
971 bool callee_regs_used[4] = {};
972 int insn_cnt = bpf_prog->len;
973 bool tail_call_seen = false;
974 bool seen_exit = false;
975 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
977 int ilen, proglen = 0;
981 detect_reg_usage(insn, insn_cnt, callee_regs_used,
984 /* tail call's presence in current prog implies it is reachable */
985 tail_call_reachable |= tail_call_seen;
987 emit_prologue(&prog, bpf_prog->aux->stack_depth,
988 bpf_prog_was_classic(bpf_prog), tail_call_reachable,
989 bpf_prog->aux->func_idx != 0);
990 push_callee_regs(&prog, callee_regs_used);
994 memcpy(rw_image + proglen, temp, ilen);
999 for (i = 1; i <= insn_cnt; i++, insn++) {
1000 const s32 imm32 = insn->imm;
1001 u32 dst_reg = insn->dst_reg;
1002 u32 src_reg = insn->src_reg;
1011 switch (insn->code) {
1013 case BPF_ALU | BPF_ADD | BPF_X:
1014 case BPF_ALU | BPF_SUB | BPF_X:
1015 case BPF_ALU | BPF_AND | BPF_X:
1016 case BPF_ALU | BPF_OR | BPF_X:
1017 case BPF_ALU | BPF_XOR | BPF_X:
1018 case BPF_ALU64 | BPF_ADD | BPF_X:
1019 case BPF_ALU64 | BPF_SUB | BPF_X:
1020 case BPF_ALU64 | BPF_AND | BPF_X:
1021 case BPF_ALU64 | BPF_OR | BPF_X:
1022 case BPF_ALU64 | BPF_XOR | BPF_X:
1023 maybe_emit_mod(&prog, dst_reg, src_reg,
1024 BPF_CLASS(insn->code) == BPF_ALU64);
1025 b2 = simple_alu_opcodes[BPF_OP(insn->code)];
1026 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
1029 case BPF_ALU64 | BPF_MOV | BPF_X:
1030 case BPF_ALU | BPF_MOV | BPF_X:
1032 BPF_CLASS(insn->code) == BPF_ALU64,
1037 case BPF_ALU | BPF_NEG:
1038 case BPF_ALU64 | BPF_NEG:
1039 maybe_emit_1mod(&prog, dst_reg,
1040 BPF_CLASS(insn->code) == BPF_ALU64);
1041 EMIT2(0xF7, add_1reg(0xD8, dst_reg));
1044 case BPF_ALU | BPF_ADD | BPF_K:
1045 case BPF_ALU | BPF_SUB | BPF_K:
1046 case BPF_ALU | BPF_AND | BPF_K:
1047 case BPF_ALU | BPF_OR | BPF_K:
1048 case BPF_ALU | BPF_XOR | BPF_K:
1049 case BPF_ALU64 | BPF_ADD | BPF_K:
1050 case BPF_ALU64 | BPF_SUB | BPF_K:
1051 case BPF_ALU64 | BPF_AND | BPF_K:
1052 case BPF_ALU64 | BPF_OR | BPF_K:
1053 case BPF_ALU64 | BPF_XOR | BPF_K:
1054 maybe_emit_1mod(&prog, dst_reg,
1055 BPF_CLASS(insn->code) == BPF_ALU64);
1058 * b3 holds 'normal' opcode, b2 short form only valid
1059 * in case dst is eax/rax.
1061 switch (BPF_OP(insn->code)) {
1085 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
1086 else if (is_axreg(dst_reg))
1087 EMIT1_off32(b2, imm32);
1089 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1092 case BPF_ALU64 | BPF_MOV | BPF_K:
1093 case BPF_ALU | BPF_MOV | BPF_K:
1094 emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64,
1098 case BPF_LD | BPF_IMM | BPF_DW:
1099 emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm);
1104 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
1105 case BPF_ALU | BPF_MOD | BPF_X:
1106 case BPF_ALU | BPF_DIV | BPF_X:
1107 case BPF_ALU | BPF_MOD | BPF_K:
1108 case BPF_ALU | BPF_DIV | BPF_K:
1109 case BPF_ALU64 | BPF_MOD | BPF_X:
1110 case BPF_ALU64 | BPF_DIV | BPF_X:
1111 case BPF_ALU64 | BPF_MOD | BPF_K:
1112 case BPF_ALU64 | BPF_DIV | BPF_K: {
1113 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1115 if (dst_reg != BPF_REG_0)
1116 EMIT1(0x50); /* push rax */
1117 if (dst_reg != BPF_REG_3)
1118 EMIT1(0x52); /* push rdx */
1120 if (BPF_SRC(insn->code) == BPF_X) {
1121 if (src_reg == BPF_REG_0 ||
1122 src_reg == BPF_REG_3) {
1123 /* mov r11, src_reg */
1124 EMIT_mov(AUX_REG, src_reg);
1128 /* mov r11, imm32 */
1129 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
1133 if (dst_reg != BPF_REG_0)
1134 /* mov rax, dst_reg */
1135 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg);
1139 * equivalent to 'xor rdx, rdx', but one byte less
1144 maybe_emit_1mod(&prog, src_reg, is64);
1145 EMIT2(0xF7, add_1reg(0xF0, src_reg));
1147 if (BPF_OP(insn->code) == BPF_MOD &&
1148 dst_reg != BPF_REG_3)
1149 /* mov dst_reg, rdx */
1150 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3);
1151 else if (BPF_OP(insn->code) == BPF_DIV &&
1152 dst_reg != BPF_REG_0)
1153 /* mov dst_reg, rax */
1154 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0);
1156 if (dst_reg != BPF_REG_3)
1157 EMIT1(0x5A); /* pop rdx */
1158 if (dst_reg != BPF_REG_0)
1159 EMIT1(0x58); /* pop rax */
1163 case BPF_ALU | BPF_MUL | BPF_K:
1164 case BPF_ALU64 | BPF_MUL | BPF_K:
1165 maybe_emit_mod(&prog, dst_reg, dst_reg,
1166 BPF_CLASS(insn->code) == BPF_ALU64);
1169 /* imul dst_reg, dst_reg, imm8 */
1170 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg),
1173 /* imul dst_reg, dst_reg, imm32 */
1175 add_2reg(0xC0, dst_reg, dst_reg),
1179 case BPF_ALU | BPF_MUL | BPF_X:
1180 case BPF_ALU64 | BPF_MUL | BPF_X:
1181 maybe_emit_mod(&prog, src_reg, dst_reg,
1182 BPF_CLASS(insn->code) == BPF_ALU64);
1184 /* imul dst_reg, src_reg */
1185 EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg));
1189 case BPF_ALU | BPF_LSH | BPF_K:
1190 case BPF_ALU | BPF_RSH | BPF_K:
1191 case BPF_ALU | BPF_ARSH | BPF_K:
1192 case BPF_ALU64 | BPF_LSH | BPF_K:
1193 case BPF_ALU64 | BPF_RSH | BPF_K:
1194 case BPF_ALU64 | BPF_ARSH | BPF_K:
1195 maybe_emit_1mod(&prog, dst_reg,
1196 BPF_CLASS(insn->code) == BPF_ALU64);
1198 b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1200 EMIT2(0xD1, add_1reg(b3, dst_reg));
1202 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1205 case BPF_ALU | BPF_LSH | BPF_X:
1206 case BPF_ALU | BPF_RSH | BPF_X:
1207 case BPF_ALU | BPF_ARSH | BPF_X:
1208 case BPF_ALU64 | BPF_LSH | BPF_X:
1209 case BPF_ALU64 | BPF_RSH | BPF_X:
1210 case BPF_ALU64 | BPF_ARSH | BPF_X:
1211 /* BMI2 shifts aren't better when shift count is already in rcx */
1212 if (boot_cpu_has(X86_FEATURE_BMI2) && src_reg != BPF_REG_4) {
1213 /* shrx/sarx/shlx dst_reg, dst_reg, src_reg */
1214 bool w = (BPF_CLASS(insn->code) == BPF_ALU64);
1217 switch (BPF_OP(insn->code)) {
1219 op = 1; /* prefix 0x66 */
1222 op = 3; /* prefix 0xf2 */
1225 op = 2; /* prefix 0xf3 */
1229 emit_shiftx(&prog, dst_reg, src_reg, w, op);
1234 if (src_reg != BPF_REG_4) { /* common case */
1235 /* Check for bad case when dst_reg == rcx */
1236 if (dst_reg == BPF_REG_4) {
1237 /* mov r11, dst_reg */
1238 EMIT_mov(AUX_REG, dst_reg);
1241 EMIT1(0x51); /* push rcx */
1243 /* mov rcx, src_reg */
1244 EMIT_mov(BPF_REG_4, src_reg);
1247 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
1248 maybe_emit_1mod(&prog, dst_reg,
1249 BPF_CLASS(insn->code) == BPF_ALU64);
1251 b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1252 EMIT2(0xD3, add_1reg(b3, dst_reg));
1254 if (src_reg != BPF_REG_4) {
1255 if (insn->dst_reg == BPF_REG_4)
1256 /* mov dst_reg, r11 */
1257 EMIT_mov(insn->dst_reg, AUX_REG);
1259 EMIT1(0x59); /* pop rcx */
1264 case BPF_ALU | BPF_END | BPF_FROM_BE:
1267 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
1269 if (is_ereg(dst_reg))
1271 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
1273 /* Emit 'movzwl eax, ax' */
1274 if (is_ereg(dst_reg))
1275 EMIT3(0x45, 0x0F, 0xB7);
1278 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1281 /* Emit 'bswap eax' to swap lower 4 bytes */
1282 if (is_ereg(dst_reg))
1286 EMIT1(add_1reg(0xC8, dst_reg));
1289 /* Emit 'bswap rax' to swap 8 bytes */
1290 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
1291 add_1reg(0xC8, dst_reg));
1296 case BPF_ALU | BPF_END | BPF_FROM_LE:
1300 * Emit 'movzwl eax, ax' to zero extend 16-bit
1303 if (is_ereg(dst_reg))
1304 EMIT3(0x45, 0x0F, 0xB7);
1307 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1310 /* Emit 'mov eax, eax' to clear upper 32-bits */
1311 if (is_ereg(dst_reg))
1313 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
1321 /* speculation barrier */
1322 case BPF_ST | BPF_NOSPEC:
1326 /* ST: *(u8*)(dst_reg + off) = imm */
1327 case BPF_ST | BPF_MEM | BPF_B:
1328 if (is_ereg(dst_reg))
1333 case BPF_ST | BPF_MEM | BPF_H:
1334 if (is_ereg(dst_reg))
1335 EMIT3(0x66, 0x41, 0xC7);
1339 case BPF_ST | BPF_MEM | BPF_W:
1340 if (is_ereg(dst_reg))
1345 case BPF_ST | BPF_MEM | BPF_DW:
1346 EMIT2(add_1mod(0x48, dst_reg), 0xC7);
1348 st: if (is_imm8(insn->off))
1349 EMIT2(add_1reg(0x40, dst_reg), insn->off);
1351 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
1353 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
1356 /* STX: *(u8*)(dst_reg + off) = src_reg */
1357 case BPF_STX | BPF_MEM | BPF_B:
1358 case BPF_STX | BPF_MEM | BPF_H:
1359 case BPF_STX | BPF_MEM | BPF_W:
1360 case BPF_STX | BPF_MEM | BPF_DW:
1361 emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1364 /* LDX: dst_reg = *(u8*)(src_reg + off) */
1365 case BPF_LDX | BPF_MEM | BPF_B:
1366 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1367 case BPF_LDX | BPF_MEM | BPF_H:
1368 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1369 case BPF_LDX | BPF_MEM | BPF_W:
1370 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1371 case BPF_LDX | BPF_MEM | BPF_DW:
1372 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1373 insn_off = insn->off;
1375 if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1376 /* Conservatively check that src_reg + insn->off is a kernel address:
1377 * src_reg + insn->off >= TASK_SIZE_MAX + PAGE_SIZE
1378 * src_reg is used as scratch for src_reg += insn->off and restored
1379 * after emit_ldx if necessary
1382 u64 limit = TASK_SIZE_MAX + PAGE_SIZE;
1385 /* At end of these emitted checks, insn->off will have been added
1386 * to src_reg, so no need to do relative load with insn->off offset
1390 /* movabsq r11, limit */
1391 EMIT2(add_1mod(0x48, AUX_REG), add_1reg(0xB8, AUX_REG));
1392 EMIT((u32)limit, 4);
1393 EMIT(limit >> 32, 4);
1396 /* add src_reg, insn->off */
1397 maybe_emit_1mod(&prog, src_reg, true);
1398 EMIT2_off32(0x81, add_1reg(0xC0, src_reg), insn->off);
1401 /* cmp src_reg, r11 */
1402 maybe_emit_mod(&prog, src_reg, AUX_REG, true);
1403 EMIT2(0x39, add_2reg(0xC0, src_reg, AUX_REG));
1405 /* if unsigned '>=', goto load */
1409 /* xor dst_reg, dst_reg */
1410 emit_mov_imm32(&prog, false, dst_reg, 0);
1411 /* jmp byte_after_ldx */
1414 /* populate jmp_offset for JAE above to jump to start_of_ldx */
1415 start_of_ldx = prog;
1416 end_of_jmp[-1] = start_of_ldx - end_of_jmp;
1418 emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off);
1419 if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1420 struct exception_table_entry *ex;
1421 u8 *_insn = image + proglen + (start_of_ldx - temp);
1424 /* populate jmp_offset for JMP above */
1425 start_of_ldx[-1] = prog - start_of_ldx;
1427 if (insn->off && src_reg != dst_reg) {
1428 /* sub src_reg, insn->off
1429 * Restore src_reg after "add src_reg, insn->off" in prev
1430 * if statement. But if src_reg == dst_reg, emit_ldx
1431 * above already clobbered src_reg, so no need to restore.
1432 * If add src_reg, insn->off was unnecessary, no need to
1435 maybe_emit_1mod(&prog, src_reg, true);
1436 EMIT2_off32(0x81, add_1reg(0xE8, src_reg), insn->off);
1439 if (!bpf_prog->aux->extable)
1442 if (excnt >= bpf_prog->aux->num_exentries) {
1443 pr_err("ex gen bug\n");
1446 ex = &bpf_prog->aux->extable[excnt++];
1448 delta = _insn - (u8 *)&ex->insn;
1449 if (!is_simm32(delta)) {
1450 pr_err("extable->insn doesn't fit into 32-bit\n");
1453 /* switch ex to rw buffer for writes */
1454 ex = (void *)rw_image + ((void *)ex - (void *)image);
1458 ex->data = EX_TYPE_BPF;
1460 if (dst_reg > BPF_REG_9) {
1461 pr_err("verifier error\n");
1465 * Compute size of x86 insn and its target dest x86 register.
1466 * ex_handler_bpf() will use lower 8 bits to adjust
1467 * pt_regs->ip to jump over this x86 instruction
1468 * and upper bits to figure out which pt_regs to zero out.
1469 * End result: x86 insn "mov rbx, qword ptr [rax+0x14]"
1470 * of 4 bytes will be ignored and rbx will be zero inited.
1472 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8);
1476 case BPF_STX | BPF_ATOMIC | BPF_W:
1477 case BPF_STX | BPF_ATOMIC | BPF_DW:
1478 if (insn->imm == (BPF_AND | BPF_FETCH) ||
1479 insn->imm == (BPF_OR | BPF_FETCH) ||
1480 insn->imm == (BPF_XOR | BPF_FETCH)) {
1481 bool is64 = BPF_SIZE(insn->code) == BPF_DW;
1482 u32 real_src_reg = src_reg;
1483 u32 real_dst_reg = dst_reg;
1487 * Can't be implemented with a single x86 insn.
1488 * Need to do a CMPXCHG loop.
1491 /* Will need RAX as a CMPXCHG operand so save R0 */
1492 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0);
1493 if (src_reg == BPF_REG_0)
1494 real_src_reg = BPF_REG_AX;
1495 if (dst_reg == BPF_REG_0)
1496 real_dst_reg = BPF_REG_AX;
1498 branch_target = prog;
1499 /* Load old value */
1500 emit_ldx(&prog, BPF_SIZE(insn->code),
1501 BPF_REG_0, real_dst_reg, insn->off);
1503 * Perform the (commutative) operation locally,
1504 * put the result in the AUX_REG.
1506 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0);
1507 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64);
1508 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)],
1509 add_2reg(0xC0, AUX_REG, real_src_reg));
1510 /* Attempt to swap in new value */
1511 err = emit_atomic(&prog, BPF_CMPXCHG,
1512 real_dst_reg, AUX_REG,
1514 BPF_SIZE(insn->code));
1518 * ZF tells us whether we won the race. If it's
1519 * cleared we need to try again.
1521 EMIT2(X86_JNE, -(prog - branch_target) - 2);
1522 /* Return the pre-modification value */
1523 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0);
1524 /* Restore R0 after clobbering RAX */
1525 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX);
1529 err = emit_atomic(&prog, insn->imm, dst_reg, src_reg,
1530 insn->off, BPF_SIZE(insn->code));
1536 case BPF_JMP | BPF_CALL: {
1539 func = (u8 *) __bpf_call_base + imm32;
1540 if (tail_call_reachable) {
1541 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */
1542 EMIT3_off32(0x48, 0x8B, 0x85,
1543 -round_up(bpf_prog->aux->stack_depth, 8) - 8);
1546 offs = 7 + x86_call_depth_emit_accounting(&prog, func);
1550 offs = x86_call_depth_emit_accounting(&prog, func);
1552 if (emit_call(&prog, func, image + addrs[i - 1] + offs))
1557 case BPF_JMP | BPF_TAIL_CALL:
1559 emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1],
1560 &prog, image + addrs[i - 1],
1562 bpf_prog->aux->stack_depth,
1565 emit_bpf_tail_call_indirect(&prog,
1567 bpf_prog->aux->stack_depth,
1568 image + addrs[i - 1],
1573 case BPF_JMP | BPF_JEQ | BPF_X:
1574 case BPF_JMP | BPF_JNE | BPF_X:
1575 case BPF_JMP | BPF_JGT | BPF_X:
1576 case BPF_JMP | BPF_JLT | BPF_X:
1577 case BPF_JMP | BPF_JGE | BPF_X:
1578 case BPF_JMP | BPF_JLE | BPF_X:
1579 case BPF_JMP | BPF_JSGT | BPF_X:
1580 case BPF_JMP | BPF_JSLT | BPF_X:
1581 case BPF_JMP | BPF_JSGE | BPF_X:
1582 case BPF_JMP | BPF_JSLE | BPF_X:
1583 case BPF_JMP32 | BPF_JEQ | BPF_X:
1584 case BPF_JMP32 | BPF_JNE | BPF_X:
1585 case BPF_JMP32 | BPF_JGT | BPF_X:
1586 case BPF_JMP32 | BPF_JLT | BPF_X:
1587 case BPF_JMP32 | BPF_JGE | BPF_X:
1588 case BPF_JMP32 | BPF_JLE | BPF_X:
1589 case BPF_JMP32 | BPF_JSGT | BPF_X:
1590 case BPF_JMP32 | BPF_JSLT | BPF_X:
1591 case BPF_JMP32 | BPF_JSGE | BPF_X:
1592 case BPF_JMP32 | BPF_JSLE | BPF_X:
1593 /* cmp dst_reg, src_reg */
1594 maybe_emit_mod(&prog, dst_reg, src_reg,
1595 BPF_CLASS(insn->code) == BPF_JMP);
1596 EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg));
1599 case BPF_JMP | BPF_JSET | BPF_X:
1600 case BPF_JMP32 | BPF_JSET | BPF_X:
1601 /* test dst_reg, src_reg */
1602 maybe_emit_mod(&prog, dst_reg, src_reg,
1603 BPF_CLASS(insn->code) == BPF_JMP);
1604 EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg));
1607 case BPF_JMP | BPF_JSET | BPF_K:
1608 case BPF_JMP32 | BPF_JSET | BPF_K:
1609 /* test dst_reg, imm32 */
1610 maybe_emit_1mod(&prog, dst_reg,
1611 BPF_CLASS(insn->code) == BPF_JMP);
1612 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
1615 case BPF_JMP | BPF_JEQ | BPF_K:
1616 case BPF_JMP | BPF_JNE | BPF_K:
1617 case BPF_JMP | BPF_JGT | BPF_K:
1618 case BPF_JMP | BPF_JLT | BPF_K:
1619 case BPF_JMP | BPF_JGE | BPF_K:
1620 case BPF_JMP | BPF_JLE | BPF_K:
1621 case BPF_JMP | BPF_JSGT | BPF_K:
1622 case BPF_JMP | BPF_JSLT | BPF_K:
1623 case BPF_JMP | BPF_JSGE | BPF_K:
1624 case BPF_JMP | BPF_JSLE | BPF_K:
1625 case BPF_JMP32 | BPF_JEQ | BPF_K:
1626 case BPF_JMP32 | BPF_JNE | BPF_K:
1627 case BPF_JMP32 | BPF_JGT | BPF_K:
1628 case BPF_JMP32 | BPF_JLT | BPF_K:
1629 case BPF_JMP32 | BPF_JGE | BPF_K:
1630 case BPF_JMP32 | BPF_JLE | BPF_K:
1631 case BPF_JMP32 | BPF_JSGT | BPF_K:
1632 case BPF_JMP32 | BPF_JSLT | BPF_K:
1633 case BPF_JMP32 | BPF_JSGE | BPF_K:
1634 case BPF_JMP32 | BPF_JSLE | BPF_K:
1635 /* test dst_reg, dst_reg to save one extra byte */
1637 maybe_emit_mod(&prog, dst_reg, dst_reg,
1638 BPF_CLASS(insn->code) == BPF_JMP);
1639 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
1643 /* cmp dst_reg, imm8/32 */
1644 maybe_emit_1mod(&prog, dst_reg,
1645 BPF_CLASS(insn->code) == BPF_JMP);
1648 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
1650 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
1652 emit_cond_jmp: /* Convert BPF opcode to x86 */
1653 switch (BPF_OP(insn->code)) {
1662 /* GT is unsigned '>', JA in x86 */
1666 /* LT is unsigned '<', JB in x86 */
1670 /* GE is unsigned '>=', JAE in x86 */
1674 /* LE is unsigned '<=', JBE in x86 */
1678 /* Signed '>', GT in x86 */
1682 /* Signed '<', LT in x86 */
1686 /* Signed '>=', GE in x86 */
1690 /* Signed '<=', LE in x86 */
1693 default: /* to silence GCC warning */
1696 jmp_offset = addrs[i + insn->off] - addrs[i];
1697 if (is_imm8(jmp_offset)) {
1699 /* To keep the jmp_offset valid, the extra bytes are
1700 * padded before the jump insn, so we subtract the
1701 * 2 bytes of jmp_cond insn from INSN_SZ_DIFF.
1703 * If the previous pass already emits an imm8
1704 * jmp_cond, then this BPF insn won't shrink, so
1707 * On the other hand, if the previous pass emits an
1708 * imm32 jmp_cond, the extra 4 bytes(*) is padded to
1709 * keep the image from shrinking further.
1711 * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond
1712 * is 2 bytes, so the size difference is 4 bytes.
1714 nops = INSN_SZ_DIFF - 2;
1715 if (nops != 0 && nops != 4) {
1716 pr_err("unexpected jmp_cond padding: %d bytes\n",
1720 emit_nops(&prog, nops);
1722 EMIT2(jmp_cond, jmp_offset);
1723 } else if (is_simm32(jmp_offset)) {
1724 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
1726 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
1732 case BPF_JMP | BPF_JA:
1733 if (insn->off == -1)
1734 /* -1 jmp instructions will always jump
1735 * backwards two bytes. Explicitly handling
1736 * this case avoids wasting too many passes
1737 * when there are long sequences of replaced
1742 jmp_offset = addrs[i + insn->off] - addrs[i];
1746 * If jmp_padding is enabled, the extra nops will
1747 * be inserted. Otherwise, optimize out nop jumps.
1750 /* There are 3 possible conditions.
1751 * (1) This BPF_JA is already optimized out in
1752 * the previous run, so there is no need
1753 * to pad any extra byte (0 byte).
1754 * (2) The previous pass emits an imm8 jmp,
1755 * so we pad 2 bytes to match the previous
1757 * (3) Similarly, the previous pass emits an
1758 * imm32 jmp, and 5 bytes is padded.
1760 nops = INSN_SZ_DIFF;
1761 if (nops != 0 && nops != 2 && nops != 5) {
1762 pr_err("unexpected nop jump padding: %d bytes\n",
1766 emit_nops(&prog, nops);
1771 if (is_imm8(jmp_offset)) {
1773 /* To avoid breaking jmp_offset, the extra bytes
1774 * are padded before the actual jmp insn, so
1775 * 2 bytes is subtracted from INSN_SZ_DIFF.
1777 * If the previous pass already emits an imm8
1778 * jmp, there is nothing to pad (0 byte).
1780 * If it emits an imm32 jmp (5 bytes) previously
1781 * and now an imm8 jmp (2 bytes), then we pad
1782 * (5 - 2 = 3) bytes to stop the image from
1783 * shrinking further.
1785 nops = INSN_SZ_DIFF - 2;
1786 if (nops != 0 && nops != 3) {
1787 pr_err("unexpected jump padding: %d bytes\n",
1791 emit_nops(&prog, INSN_SZ_DIFF - 2);
1793 EMIT2(0xEB, jmp_offset);
1794 } else if (is_simm32(jmp_offset)) {
1795 EMIT1_off32(0xE9, jmp_offset);
1797 pr_err("jmp gen bug %llx\n", jmp_offset);
1802 case BPF_JMP | BPF_EXIT:
1804 jmp_offset = ctx->cleanup_addr - addrs[i];
1808 /* Update cleanup_addr */
1809 ctx->cleanup_addr = proglen;
1810 pop_callee_regs(&prog, callee_regs_used);
1811 EMIT1(0xC9); /* leave */
1812 emit_return(&prog, image + addrs[i - 1] + (prog - temp));
1817 * By design x86-64 JIT should support all BPF instructions.
1818 * This error will be seen if new instruction was added
1819 * to the interpreter, but not to the JIT, or if there is
1822 pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
1827 if (ilen > BPF_MAX_INSN_SIZE) {
1828 pr_err("bpf_jit: fatal insn size error\n");
1834 * When populating the image, assert that:
1836 * i) We do not write beyond the allocated space, and
1837 * ii) addrs[i] did not change from the prior run, in order
1838 * to validate assumptions made for computing branch
1841 if (unlikely(proglen + ilen > oldproglen ||
1842 proglen + ilen != addrs[i])) {
1843 pr_err("bpf_jit: fatal error\n");
1846 memcpy(rw_image + proglen, temp, ilen);
1853 if (image && excnt != bpf_prog->aux->num_exentries) {
1854 pr_err("extable is not populated\n");
1860 static void save_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1863 int i, j, arg_size, nr_regs;
1864 /* Store function arguments to stack.
1865 * For a function that accepts two pointers the sequence will be:
1866 * mov QWORD PTR [rbp-0x10],rdi
1867 * mov QWORD PTR [rbp-0x8],rsi
1869 for (i = 0, j = 0; i < min(nr_args, 6); i++) {
1870 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) {
1871 nr_regs = (m->arg_size[i] + 7) / 8;
1875 arg_size = m->arg_size[i];
1879 emit_stx(prog, bytes_to_bpf_size(arg_size),
1881 j == 5 ? X86_REG_R9 : BPF_REG_1 + j,
1882 -(stack_size - j * 8));
1889 static void restore_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1892 int i, j, arg_size, nr_regs;
1894 /* Restore function arguments from stack.
1895 * For a function that accepts two pointers the sequence will be:
1896 * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10]
1897 * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8]
1899 for (i = 0, j = 0; i < min(nr_args, 6); i++) {
1900 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) {
1901 nr_regs = (m->arg_size[i] + 7) / 8;
1905 arg_size = m->arg_size[i];
1909 emit_ldx(prog, bytes_to_bpf_size(arg_size),
1910 j == 5 ? X86_REG_R9 : BPF_REG_1 + j,
1912 -(stack_size - j * 8));
1919 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog,
1920 struct bpf_tramp_link *l, int stack_size,
1921 int run_ctx_off, bool save_ret)
1925 int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie);
1926 struct bpf_prog *p = l->link.prog;
1927 u64 cookie = l->cookie;
1929 /* mov rdi, cookie */
1930 emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie);
1932 /* Prepare struct bpf_tramp_run_ctx.
1934 * bpf_tramp_run_ctx is already preserved by
1935 * arch_prepare_bpf_trampoline().
1937 * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi
1939 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off);
1941 /* arg1: mov rdi, progs[i] */
1942 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1943 /* arg2: lea rsi, [rbp - ctx_cookie_off] */
1944 EMIT4(0x48, 0x8D, 0x75, -run_ctx_off);
1946 if (emit_rsb_call(&prog, bpf_trampoline_enter(p), prog))
1948 /* remember prog start time returned by __bpf_prog_enter */
1949 emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0);
1951 /* if (__bpf_prog_enter*(prog) == 0)
1952 * goto skip_exec_of_prog;
1954 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */
1955 /* emit 2 nops that will be replaced with JE insn */
1957 emit_nops(&prog, 2);
1959 /* arg1: lea rdi, [rbp - stack_size] */
1960 EMIT4(0x48, 0x8D, 0x7D, -stack_size);
1961 /* arg2: progs[i]->insnsi for interpreter */
1963 emit_mov_imm64(&prog, BPF_REG_2,
1964 (long) p->insnsi >> 32,
1965 (u32) (long) p->insnsi);
1966 /* call JITed bpf program or interpreter */
1967 if (emit_rsb_call(&prog, p->bpf_func, prog))
1971 * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return
1972 * of the previous call which is then passed on the stack to
1973 * the next BPF program.
1975 * BPF_TRAMP_FENTRY trampoline may need to return the return
1976 * value of BPF_PROG_TYPE_STRUCT_OPS prog.
1979 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1981 /* replace 2 nops with JE insn, since jmp target is known */
1982 jmp_insn[0] = X86_JE;
1983 jmp_insn[1] = prog - jmp_insn - 2;
1985 /* arg1: mov rdi, progs[i] */
1986 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1987 /* arg2: mov rsi, rbx <- start time in nsec */
1988 emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6);
1989 /* arg3: lea rdx, [rbp - run_ctx_off] */
1990 EMIT4(0x48, 0x8D, 0x55, -run_ctx_off);
1991 if (emit_rsb_call(&prog, bpf_trampoline_exit(p), prog))
1998 static void emit_align(u8 **pprog, u32 align)
2000 u8 *target, *prog = *pprog;
2002 target = PTR_ALIGN(prog, align);
2004 emit_nops(&prog, target - prog);
2009 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond)
2014 offset = func - (ip + 2 + 4);
2015 if (!is_simm32(offset)) {
2016 pr_err("Target %p is out of range\n", func);
2019 EMIT2_off32(0x0F, jmp_cond + 0x10, offset);
2024 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog,
2025 struct bpf_tramp_links *tl, int stack_size,
2026 int run_ctx_off, bool save_ret)
2031 for (i = 0; i < tl->nr_links; i++) {
2032 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size,
2033 run_ctx_off, save_ret))
2040 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog,
2041 struct bpf_tramp_links *tl, int stack_size,
2042 int run_ctx_off, u8 **branches)
2047 /* The first fmod_ret program will receive a garbage return value.
2048 * Set this to 0 to avoid confusing the program.
2050 emit_mov_imm32(&prog, false, BPF_REG_0, 0);
2051 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2052 for (i = 0; i < tl->nr_links; i++) {
2053 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true))
2056 /* mod_ret prog stored return value into [rbp - 8]. Emit:
2057 * if (*(u64 *)(rbp - 8) != 0)
2060 /* cmp QWORD PTR [rbp - 0x8], 0x0 */
2061 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00);
2063 /* Save the location of the branch and Generate 6 nops
2064 * (4 bytes for an offset and 2 bytes for the jump) These nops
2065 * are replaced with a conditional jump once do_fexit (i.e. the
2066 * start of the fexit invocation) is finalized.
2069 emit_nops(&prog, 4 + 2);
2077 * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev);
2078 * its 'struct btf_func_model' will be nr_args=2
2079 * The assembly code when eth_type_trans is executing after trampoline:
2083 * sub rsp, 16 // space for skb and dev
2084 * push rbx // temp regs to pass start time
2085 * mov qword ptr [rbp - 16], rdi // save skb pointer to stack
2086 * mov qword ptr [rbp - 8], rsi // save dev pointer to stack
2087 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
2088 * mov rbx, rax // remember start time in bpf stats are enabled
2089 * lea rdi, [rbp - 16] // R1==ctx of bpf prog
2090 * call addr_of_jited_FENTRY_prog
2091 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
2092 * mov rsi, rbx // prog start time
2093 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
2094 * mov rdi, qword ptr [rbp - 16] // restore skb pointer from stack
2095 * mov rsi, qword ptr [rbp - 8] // restore dev pointer from stack
2100 * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be
2101 * replaced with 'call generated_bpf_trampoline'. When it returns
2102 * eth_type_trans will continue executing with original skb and dev pointers.
2104 * The assembly code when eth_type_trans is called from trampoline:
2108 * sub rsp, 24 // space for skb, dev, return value
2109 * push rbx // temp regs to pass start time
2110 * mov qword ptr [rbp - 24], rdi // save skb pointer to stack
2111 * mov qword ptr [rbp - 16], rsi // save dev pointer to stack
2112 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
2113 * mov rbx, rax // remember start time if bpf stats are enabled
2114 * lea rdi, [rbp - 24] // R1==ctx of bpf prog
2115 * call addr_of_jited_FENTRY_prog // bpf prog can access skb and dev
2116 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
2117 * mov rsi, rbx // prog start time
2118 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
2119 * mov rdi, qword ptr [rbp - 24] // restore skb pointer from stack
2120 * mov rsi, qword ptr [rbp - 16] // restore dev pointer from stack
2121 * call eth_type_trans+5 // execute body of eth_type_trans
2122 * mov qword ptr [rbp - 8], rax // save return value
2123 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
2124 * mov rbx, rax // remember start time in bpf stats are enabled
2125 * lea rdi, [rbp - 24] // R1==ctx of bpf prog
2126 * call addr_of_jited_FEXIT_prog // bpf prog can access skb, dev, return value
2127 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
2128 * mov rsi, rbx // prog start time
2129 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
2130 * mov rax, qword ptr [rbp - 8] // restore eth_type_trans's return value
2133 * add rsp, 8 // skip eth_type_trans's frame
2134 * ret // return to its caller
2136 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end,
2137 const struct btf_func_model *m, u32 flags,
2138 struct bpf_tramp_links *tlinks,
2141 int ret, i, nr_args = m->nr_args, extra_nregs = 0;
2142 int regs_off, ip_off, args_off, stack_size = nr_args * 8, run_ctx_off;
2143 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY];
2144 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT];
2145 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN];
2146 void *orig_call = func_addr;
2147 u8 **branches = NULL;
2151 /* x86-64 supports up to 6 arguments. 7+ can be added in the future */
2155 for (i = 0; i < MAX_BPF_FUNC_ARGS; i++) {
2156 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG)
2157 extra_nregs += (m->arg_size[i] + 7) / 8 - 1;
2159 if (nr_args + extra_nregs > 6)
2161 stack_size += extra_nregs * 8;
2163 /* Generated trampoline stack layout:
2165 * RBP + 8 [ return address ]
2168 * RBP - 8 [ return value ] BPF_TRAMP_F_CALL_ORIG or
2169 * BPF_TRAMP_F_RET_FENTRY_RET flags
2171 * [ reg_argN ] always
2173 * RBP - regs_off [ reg_arg1 ] program's ctx pointer
2175 * RBP - args_off [ arg regs count ] always
2177 * RBP - ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag
2179 * RBP - run_ctx_off [ bpf_tramp_run_ctx ]
2182 /* room for return value of orig_call or fentry prog */
2183 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET);
2187 regs_off = stack_size;
2191 args_off = stack_size;
2193 if (flags & BPF_TRAMP_F_IP_ARG)
2194 stack_size += 8; /* room for IP address argument */
2196 ip_off = stack_size;
2198 stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7;
2199 run_ctx_off = stack_size;
2201 if (flags & BPF_TRAMP_F_SKIP_FRAME) {
2202 /* skip patched call instruction and point orig_call to actual
2203 * body of the kernel function.
2205 if (is_endbr(*(u32 *)orig_call))
2206 orig_call += ENDBR_INSN_SIZE;
2207 orig_call += X86_PATCH_SIZE;
2214 * This is the direct-call trampoline, as such it needs accounting
2215 * for the __fentry__ call.
2217 x86_call_depth_emit_accounting(&prog, NULL);
2218 EMIT1(0x55); /* push rbp */
2219 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
2220 EMIT4(0x48, 0x83, 0xEC, stack_size); /* sub rsp, stack_size */
2221 EMIT1(0x53); /* push rbx */
2223 /* Store number of argument registers of the traced function:
2224 * mov rax, nr_args + extra_nregs
2225 * mov QWORD PTR [rbp - args_off], rax
2227 emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_args + extra_nregs);
2228 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -args_off);
2230 if (flags & BPF_TRAMP_F_IP_ARG) {
2231 /* Store IP address of the traced function:
2232 * movabsq rax, func_addr
2233 * mov QWORD PTR [rbp - ip_off], rax
2235 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr);
2236 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off);
2239 save_regs(m, &prog, nr_args, regs_off);
2241 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2242 /* arg1: mov rdi, im */
2243 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2244 if (emit_rsb_call(&prog, __bpf_tramp_enter, prog)) {
2250 if (fentry->nr_links)
2251 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off,
2252 flags & BPF_TRAMP_F_RET_FENTRY_RET))
2255 if (fmod_ret->nr_links) {
2256 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *),
2261 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off,
2262 run_ctx_off, branches)) {
2268 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2269 restore_regs(m, &prog, nr_args, regs_off);
2271 if (flags & BPF_TRAMP_F_ORIG_STACK) {
2272 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 8);
2273 EMIT2(0xff, 0xd0); /* call *rax */
2275 /* call original function */
2276 if (emit_rsb_call(&prog, orig_call, prog)) {
2281 /* remember return value in a stack for bpf prog to access */
2282 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2283 im->ip_after_call = prog;
2284 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
2285 prog += X86_PATCH_SIZE;
2288 if (fmod_ret->nr_links) {
2289 /* From Intel 64 and IA-32 Architectures Optimization
2290 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2291 * Coding Rule 11: All branch targets should be 16-byte
2294 emit_align(&prog, 16);
2295 /* Update the branches saved in invoke_bpf_mod_ret with the
2296 * aligned address of do_fexit.
2298 for (i = 0; i < fmod_ret->nr_links; i++)
2299 emit_cond_near_jump(&branches[i], prog, branches[i],
2303 if (fexit->nr_links)
2304 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off, false)) {
2309 if (flags & BPF_TRAMP_F_RESTORE_REGS)
2310 restore_regs(m, &prog, nr_args, regs_off);
2312 /* This needs to be done regardless. If there were fmod_ret programs,
2313 * the return value is only updated on the stack and still needs to be
2316 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2317 im->ip_epilogue = prog;
2318 /* arg1: mov rdi, im */
2319 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2320 if (emit_rsb_call(&prog, __bpf_tramp_exit, prog)) {
2325 /* restore return value of orig_call or fentry prog back into RAX */
2327 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8);
2329 EMIT1(0x5B); /* pop rbx */
2330 EMIT1(0xC9); /* leave */
2331 if (flags & BPF_TRAMP_F_SKIP_FRAME)
2332 /* skip our return address and return to parent */
2333 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */
2334 emit_return(&prog, prog);
2335 /* Make sure the trampoline generation logic doesn't overflow */
2336 if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) {
2340 ret = prog - (u8 *)image;
2347 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf)
2349 u8 *jg_reloc, *prog = *pprog;
2350 int pivot, err, jg_bytes = 1;
2354 /* Leaf node of recursion, i.e. not a range of indices
2357 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */
2358 if (!is_simm32(progs[a]))
2360 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
2362 err = emit_cond_near_jump(&prog, /* je func */
2363 (void *)progs[a], image + (prog - buf),
2368 emit_indirect_jump(&prog, 2 /* rdx */, image + (prog - buf));
2374 /* Not a leaf node, so we pivot, and recursively descend into
2375 * the lower and upper ranges.
2377 pivot = (b - a) / 2;
2378 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */
2379 if (!is_simm32(progs[a + pivot]))
2381 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
2383 if (pivot > 2) { /* jg upper_part */
2384 /* Require near jump. */
2386 EMIT2_off32(0x0F, X86_JG + 0x10, 0);
2392 err = emit_bpf_dispatcher(&prog, a, a + pivot, /* emit lower_part */
2397 /* From Intel 64 and IA-32 Architectures Optimization
2398 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2399 * Coding Rule 11: All branch targets should be 16-byte
2402 emit_align(&prog, 16);
2403 jg_offset = prog - jg_reloc;
2404 emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes);
2406 err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */
2407 b, progs, image, buf);
2415 static int cmp_ips(const void *a, const void *b)
2427 int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs)
2431 sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL);
2432 return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf);
2435 struct x64_jit_data {
2436 struct bpf_binary_header *rw_header;
2437 struct bpf_binary_header *header;
2441 struct jit_context ctx;
2444 #define MAX_PASSES 20
2445 #define PADDING_PASSES (MAX_PASSES - 5)
2447 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2449 struct bpf_binary_header *rw_header = NULL;
2450 struct bpf_binary_header *header = NULL;
2451 struct bpf_prog *tmp, *orig_prog = prog;
2452 struct x64_jit_data *jit_data;
2453 int proglen, oldproglen = 0;
2454 struct jit_context ctx = {};
2455 bool tmp_blinded = false;
2456 bool extra_pass = false;
2457 bool padding = false;
2458 u8 *rw_image = NULL;
2464 if (!prog->jit_requested)
2467 tmp = bpf_jit_blind_constants(prog);
2469 * If blinding was requested and we failed during blinding,
2470 * we must fall back to the interpreter.
2479 jit_data = prog->aux->jit_data;
2481 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
2486 prog->aux->jit_data = jit_data;
2488 addrs = jit_data->addrs;
2490 ctx = jit_data->ctx;
2491 oldproglen = jit_data->proglen;
2492 image = jit_data->image;
2493 header = jit_data->header;
2494 rw_header = jit_data->rw_header;
2495 rw_image = (void *)rw_header + ((void *)image - (void *)header);
2498 goto skip_init_addrs;
2500 addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL);
2507 * Before first pass, make a rough estimation of addrs[]
2508 * each BPF instruction is translated to less than 64 bytes
2510 for (proglen = 0, i = 0; i <= prog->len; i++) {
2514 ctx.cleanup_addr = proglen;
2518 * JITed image shrinks with every pass and the loop iterates
2519 * until the image stops shrinking. Very large BPF programs
2520 * may converge on the last pass. In such case do one more
2521 * pass to emit the final image.
2523 for (pass = 0; pass < MAX_PASSES || image; pass++) {
2524 if (!padding && pass >= PADDING_PASSES)
2526 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding);
2531 bpf_arch_text_copy(&header->size, &rw_header->size,
2532 sizeof(rw_header->size));
2533 bpf_jit_binary_pack_free(header, rw_header);
2535 /* Fall back to interpreter mode */
2538 prog->bpf_func = NULL;
2540 prog->jited_len = 0;
2545 if (proglen != oldproglen) {
2546 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2547 proglen, oldproglen);
2552 if (proglen == oldproglen) {
2554 * The number of entries in extable is the number of BPF_LDX
2555 * insns that access kernel memory via "pointer to BTF type".
2556 * The verifier changed their opcode from LDX|MEM|size
2557 * to LDX|PROBE_MEM|size to make JITing easier.
2559 u32 align = __alignof__(struct exception_table_entry);
2560 u32 extable_size = prog->aux->num_exentries *
2561 sizeof(struct exception_table_entry);
2563 /* allocate module memory for x86 insns and extable */
2564 header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size,
2565 &image, align, &rw_header, &rw_image,
2571 prog->aux->extable = (void *) image + roundup(proglen, align);
2573 oldproglen = proglen;
2577 if (bpf_jit_enable > 1)
2578 bpf_jit_dump(prog->len, proglen, pass + 1, image);
2581 if (!prog->is_func || extra_pass) {
2583 * bpf_jit_binary_pack_finalize fails in two scenarios:
2584 * 1) header is not pointing to proper module memory;
2585 * 2) the arch doesn't support bpf_arch_text_copy().
2587 * Both cases are serious bugs and justify WARN_ON.
2589 if (WARN_ON(bpf_jit_binary_pack_finalize(prog, header, rw_header))) {
2590 /* header has been freed */
2595 bpf_tail_call_direct_fixup(prog);
2597 jit_data->addrs = addrs;
2598 jit_data->ctx = ctx;
2599 jit_data->proglen = proglen;
2600 jit_data->image = image;
2601 jit_data->header = header;
2602 jit_data->rw_header = rw_header;
2604 prog->bpf_func = (void *)image;
2606 prog->jited_len = proglen;
2611 if (!image || !prog->is_func || extra_pass) {
2613 bpf_prog_fill_jited_linfo(prog, addrs + 1);
2617 prog->aux->jit_data = NULL;
2621 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2626 bool bpf_jit_supports_kfunc_call(void)
2631 void *bpf_arch_text_copy(void *dst, void *src, size_t len)
2633 if (text_poke_copy(dst, src, len) == NULL)
2634 return ERR_PTR(-EINVAL);
2638 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
2639 bool bpf_jit_supports_subprog_tailcalls(void)
2644 void bpf_jit_free(struct bpf_prog *prog)
2647 struct x64_jit_data *jit_data = prog->aux->jit_data;
2648 struct bpf_binary_header *hdr;
2651 * If we fail the final pass of JIT (from jit_subprogs),
2652 * the program may not be finalized yet. Call finalize here
2653 * before freeing it.
2656 bpf_jit_binary_pack_finalize(prog, jit_data->header,
2657 jit_data->rw_header);
2658 kvfree(jit_data->addrs);
2661 hdr = bpf_jit_binary_pack_hdr(prog);
2662 bpf_jit_binary_pack_free(hdr, NULL);
2663 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog));
2666 bpf_prog_unlock_free(prog);