1 // SPDX-License-Identifier: GPL-2.0-only
3 * bpf_jit_comp.c: BPF JIT compiler
5 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
6 * Internal BPF Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
8 #include <linux/netdevice.h>
9 #include <linux/filter.h>
10 #include <linux/if_vlan.h>
11 #include <linux/bpf.h>
12 #include <linux/memory.h>
13 #include <linux/sort.h>
14 #include <asm/extable.h>
15 #include <asm/set_memory.h>
16 #include <asm/nospec-branch.h>
17 #include <asm/text-patching.h>
19 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
32 #define EMIT(bytes, len) \
33 do { prog = emit_code(prog, bytes, len); } while (0)
35 #define EMIT1(b1) EMIT(b1, 1)
36 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2)
37 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
38 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
40 #define EMIT1_off32(b1, off) \
41 do { EMIT1(b1); EMIT(off, 4); } while (0)
42 #define EMIT2_off32(b1, b2, off) \
43 do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
44 #define EMIT3_off32(b1, b2, b3, off) \
45 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
46 #define EMIT4_off32(b1, b2, b3, b4, off) \
47 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
49 static bool is_imm8(int value)
51 return value <= 127 && value >= -128;
54 static bool is_simm32(s64 value)
56 return value == (s64)(s32)value;
59 static bool is_uimm32(u64 value)
61 return value == (u64)(u32)value;
65 #define EMIT_mov(DST, SRC) \
68 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
71 static int bpf_size_to_x86_bytes(int bpf_size)
73 if (bpf_size == BPF_W)
75 else if (bpf_size == BPF_H)
77 else if (bpf_size == BPF_B)
79 else if (bpf_size == BPF_DW)
86 * List of x86 cond jumps opcodes (. + s8)
87 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
100 /* Pick a register outside of BPF range for JIT internal work */
101 #define AUX_REG (MAX_BPF_JIT_REG + 1)
102 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2)
105 * The following table maps BPF registers to x86-64 registers.
107 * x86-64 register R12 is unused, since if used as base address
108 * register in load/store instructions, it always needs an
109 * extra byte of encoding and is callee saved.
111 * x86-64 register R9 is not used by BPF programs, but can be used by BPF
112 * trampoline. x86-64 register R10 is used for blinding (if enabled).
114 static const int reg2hex[] = {
115 [BPF_REG_0] = 0, /* RAX */
116 [BPF_REG_1] = 7, /* RDI */
117 [BPF_REG_2] = 6, /* RSI */
118 [BPF_REG_3] = 2, /* RDX */
119 [BPF_REG_4] = 1, /* RCX */
120 [BPF_REG_5] = 0, /* R8 */
121 [BPF_REG_6] = 3, /* RBX callee saved */
122 [BPF_REG_7] = 5, /* R13 callee saved */
123 [BPF_REG_8] = 6, /* R14 callee saved */
124 [BPF_REG_9] = 7, /* R15 callee saved */
125 [BPF_REG_FP] = 5, /* RBP readonly */
126 [BPF_REG_AX] = 2, /* R10 temp register */
127 [AUX_REG] = 3, /* R11 temp register */
128 [X86_REG_R9] = 1, /* R9 register, 6th function argument */
131 static const int reg2pt_regs[] = {
132 [BPF_REG_0] = offsetof(struct pt_regs, ax),
133 [BPF_REG_1] = offsetof(struct pt_regs, di),
134 [BPF_REG_2] = offsetof(struct pt_regs, si),
135 [BPF_REG_3] = offsetof(struct pt_regs, dx),
136 [BPF_REG_4] = offsetof(struct pt_regs, cx),
137 [BPF_REG_5] = offsetof(struct pt_regs, r8),
138 [BPF_REG_6] = offsetof(struct pt_regs, bx),
139 [BPF_REG_7] = offsetof(struct pt_regs, r13),
140 [BPF_REG_8] = offsetof(struct pt_regs, r14),
141 [BPF_REG_9] = offsetof(struct pt_regs, r15),
145 * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15
146 * which need extra byte of encoding.
147 * rax,rcx,...,rbp have simpler encoding
149 static bool is_ereg(u32 reg)
151 return (1 << reg) & (BIT(BPF_REG_5) |
161 * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64
162 * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte
163 * of encoding. al,cl,dl,bl have simpler encoding.
165 static bool is_ereg_8l(u32 reg)
167 return is_ereg(reg) ||
168 (1 << reg) & (BIT(BPF_REG_1) |
173 static bool is_axreg(u32 reg)
175 return reg == BPF_REG_0;
178 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */
179 static u8 add_1mod(u8 byte, u32 reg)
186 static u8 add_2mod(u8 byte, u32 r1, u32 r2)
195 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */
196 static u8 add_1reg(u8 byte, u32 dst_reg)
198 return byte + reg2hex[dst_reg];
201 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */
202 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
204 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
207 /* Some 1-byte opcodes for binary ALU operations */
208 static u8 simple_alu_opcodes[] = {
219 static void jit_fill_hole(void *area, unsigned int size)
221 /* Fill whole space with INT3 instructions */
222 memset(area, 0xcc, size);
226 int cleanup_addr; /* Epilogue code offset */
229 * Program specific offsets of labels in the code; these rely on the
230 * JIT doing at least 2 passes, recording the position on the first
231 * pass, only to generate the correct offset on the second pass.
233 int tail_call_direct_label;
234 int tail_call_indirect_label;
237 /* Maximum number of bytes emitted while JITing one eBPF insn */
238 #define BPF_MAX_INSN_SIZE 128
239 #define BPF_INSN_SAFETY 64
241 /* Number of bytes emit_patch() needs to generate instructions */
242 #define X86_PATCH_SIZE 5
243 /* Number of bytes that will be skipped on tailcall */
244 #define X86_TAIL_CALL_OFFSET 11
246 static void push_callee_regs(u8 **pprog, bool *callee_regs_used)
250 if (callee_regs_used[0])
251 EMIT1(0x53); /* push rbx */
252 if (callee_regs_used[1])
253 EMIT2(0x41, 0x55); /* push r13 */
254 if (callee_regs_used[2])
255 EMIT2(0x41, 0x56); /* push r14 */
256 if (callee_regs_used[3])
257 EMIT2(0x41, 0x57); /* push r15 */
261 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used)
265 if (callee_regs_used[3])
266 EMIT2(0x41, 0x5F); /* pop r15 */
267 if (callee_regs_used[2])
268 EMIT2(0x41, 0x5E); /* pop r14 */
269 if (callee_regs_used[1])
270 EMIT2(0x41, 0x5D); /* pop r13 */
271 if (callee_regs_used[0])
272 EMIT1(0x5B); /* pop rbx */
277 * Emit x86-64 prologue code for BPF program.
278 * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes
279 * while jumping to another program
281 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf,
282 bool tail_call_reachable, bool is_subprog)
286 /* BPF trampoline can be made to work without these nops,
287 * but let's waste 5 bytes for now and optimize later
289 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
290 prog += X86_PATCH_SIZE;
291 if (!ebpf_from_cbpf) {
292 if (tail_call_reachable && !is_subprog)
293 EMIT2(0x31, 0xC0); /* xor eax, eax */
295 EMIT2(0x66, 0x90); /* nop2 */
297 EMIT1(0x55); /* push rbp */
298 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
299 /* sub rsp, rounded_stack_depth */
301 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8));
302 if (tail_call_reachable)
303 EMIT1(0x50); /* push rax */
307 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode)
312 offset = func - (ip + X86_PATCH_SIZE);
313 if (!is_simm32(offset)) {
314 pr_err("Target call %p is out of range\n", func);
317 EMIT1_off32(opcode, offset);
322 static int emit_call(u8 **pprog, void *func, void *ip)
324 return emit_patch(pprog, func, ip, 0xE8);
327 static int emit_jump(u8 **pprog, void *func, void *ip)
329 return emit_patch(pprog, func, ip, 0xE9);
332 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
333 void *old_addr, void *new_addr,
334 const bool text_live)
336 const u8 *nop_insn = x86_nops[5];
337 u8 old_insn[X86_PATCH_SIZE];
338 u8 new_insn[X86_PATCH_SIZE];
342 memcpy(old_insn, nop_insn, X86_PATCH_SIZE);
345 ret = t == BPF_MOD_CALL ?
346 emit_call(&prog, old_addr, ip) :
347 emit_jump(&prog, old_addr, ip);
352 memcpy(new_insn, nop_insn, X86_PATCH_SIZE);
355 ret = t == BPF_MOD_CALL ?
356 emit_call(&prog, new_addr, ip) :
357 emit_jump(&prog, new_addr, ip);
363 mutex_lock(&text_mutex);
364 if (memcmp(ip, old_insn, X86_PATCH_SIZE))
367 if (memcmp(ip, new_insn, X86_PATCH_SIZE)) {
369 text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL);
371 memcpy(ip, new_insn, X86_PATCH_SIZE);
375 mutex_unlock(&text_mutex);
379 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
380 void *old_addr, void *new_addr)
382 if (!is_kernel_text((long)ip) &&
383 !is_bpf_text_address((long)ip))
384 /* BPF poking in modules is not supported */
387 return __bpf_arch_text_poke(ip, t, old_addr, new_addr, true);
390 #define EMIT_LFENCE() EMIT3(0x0F, 0xAE, 0xE8)
392 static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip)
396 #ifdef CONFIG_RETPOLINE
397 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) {
399 EMIT2(0xFF, 0xE0 + reg);
400 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) {
401 emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip);
404 EMIT2(0xFF, 0xE0 + reg);
409 static void emit_return(u8 **pprog, u8 *ip)
413 if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) {
414 emit_jump(&prog, &__x86_return_thunk, ip);
416 EMIT1(0xC3); /* ret */
417 if (IS_ENABLED(CONFIG_SLS))
418 EMIT1(0xCC); /* int3 */
425 * Generate the following code:
427 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
428 * if (index >= array->map.max_entries)
430 * if (++tail_call_cnt > MAX_TAIL_CALL_CNT)
432 * prog = array->ptrs[index];
435 * goto *(prog->bpf_func + prologue_size);
438 static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used,
439 u32 stack_depth, u8 *ip,
440 struct jit_context *ctx)
442 int tcc_off = -4 - round_up(stack_depth, 8);
443 u8 *prog = *pprog, *start = *pprog;
447 * rdi - pointer to ctx
448 * rsi - pointer to bpf_array
449 * rdx - index in bpf_array
453 * if (index >= array->map.max_entries)
456 EMIT2(0x89, 0xD2); /* mov edx, edx */
457 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */
458 offsetof(struct bpf_array, map.max_entries));
460 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
461 EMIT2(X86_JBE, offset); /* jbe out */
464 * if (tail_call_cnt > MAX_TAIL_CALL_CNT)
467 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */
468 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
470 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
471 EMIT2(X86_JA, offset); /* ja out */
472 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
473 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */
475 /* prog = array->ptrs[index]; */
476 EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6, /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */
477 offsetof(struct bpf_array, ptrs));
483 EMIT3(0x48, 0x85, 0xC9); /* test rcx,rcx */
485 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
486 EMIT2(X86_JE, offset); /* je out */
488 pop_callee_regs(&prog, callee_regs_used);
490 EMIT1(0x58); /* pop rax */
492 EMIT3_off32(0x48, 0x81, 0xC4, /* add rsp, sd */
493 round_up(stack_depth, 8));
495 /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */
496 EMIT4(0x48, 0x8B, 0x49, /* mov rcx, qword ptr [rcx + 32] */
497 offsetof(struct bpf_prog, bpf_func));
498 EMIT4(0x48, 0x83, 0xC1, /* add rcx, X86_TAIL_CALL_OFFSET */
499 X86_TAIL_CALL_OFFSET);
501 * Now we're ready to jump into next BPF program
502 * rdi == ctx (1st arg)
503 * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET
505 emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start));
508 ctx->tail_call_indirect_label = prog - start;
512 static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke,
514 bool *callee_regs_used, u32 stack_depth,
515 struct jit_context *ctx)
517 int tcc_off = -4 - round_up(stack_depth, 8);
518 u8 *prog = *pprog, *start = *pprog;
522 * if (tail_call_cnt > MAX_TAIL_CALL_CNT)
525 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */
526 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
528 offset = ctx->tail_call_direct_label - (prog + 2 - start);
529 EMIT2(X86_JA, offset); /* ja out */
530 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
531 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */
533 poke->tailcall_bypass = ip + (prog - start);
534 poke->adj_off = X86_TAIL_CALL_OFFSET;
535 poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE;
536 poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE;
538 emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE,
539 poke->tailcall_bypass);
541 pop_callee_regs(&prog, callee_regs_used);
542 EMIT1(0x58); /* pop rax */
544 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8));
546 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
547 prog += X86_PATCH_SIZE;
550 ctx->tail_call_direct_label = prog - start;
555 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog)
557 struct bpf_jit_poke_descriptor *poke;
558 struct bpf_array *array;
559 struct bpf_prog *target;
562 for (i = 0; i < prog->aux->size_poke_tab; i++) {
563 poke = &prog->aux->poke_tab[i];
564 if (poke->aux && poke->aux != prog->aux)
567 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable));
569 if (poke->reason != BPF_POKE_REASON_TAIL_CALL)
572 array = container_of(poke->tail_call.map, struct bpf_array, map);
573 mutex_lock(&array->aux->poke_mutex);
574 target = array->ptrs[poke->tail_call.key];
576 /* Plain memcpy is used when image is not live yet
577 * and still not locked as read-only. Once poke
578 * location is active (poke->tailcall_target_stable),
579 * any parallel bpf_arch_text_poke() might occur
580 * still on the read-write image until we finally
581 * locked it as read-only. Both modifications on
582 * the given image are under text_mutex to avoid
585 ret = __bpf_arch_text_poke(poke->tailcall_target,
587 (u8 *)target->bpf_func +
588 poke->adj_off, false);
590 ret = __bpf_arch_text_poke(poke->tailcall_bypass,
592 (u8 *)poke->tailcall_target +
593 X86_PATCH_SIZE, NULL, false);
596 WRITE_ONCE(poke->tailcall_target_stable, true);
597 mutex_unlock(&array->aux->poke_mutex);
601 static void emit_mov_imm32(u8 **pprog, bool sign_propagate,
602 u32 dst_reg, const u32 imm32)
608 * Optimization: if imm32 is positive, use 'mov %eax, imm32'
609 * (which zero-extends imm32) to save 2 bytes.
611 if (sign_propagate && (s32)imm32 < 0) {
612 /* 'mov %rax, imm32' sign extends imm32 */
613 b1 = add_1mod(0x48, dst_reg);
616 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
621 * Optimization: if imm32 is zero, use 'xor %eax, %eax'
625 if (is_ereg(dst_reg))
626 EMIT1(add_2mod(0x40, dst_reg, dst_reg));
629 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
633 /* mov %eax, imm32 */
634 if (is_ereg(dst_reg))
635 EMIT1(add_1mod(0x40, dst_reg));
636 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
641 static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
642 const u32 imm32_hi, const u32 imm32_lo)
646 if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
648 * For emitting plain u32, where sign bit must not be
649 * propagated LLVM tends to load imm64 over mov32
650 * directly, so save couple of bytes by just doing
651 * 'mov %eax, imm32' instead.
653 emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
655 /* movabsq %rax, imm64 */
656 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
664 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg)
670 EMIT_mov(dst_reg, src_reg);
673 if (is_ereg(dst_reg) || is_ereg(src_reg))
674 EMIT1(add_2mod(0x40, dst_reg, src_reg));
675 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
681 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */
682 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off)
687 /* 1-byte signed displacement.
689 * If off == 0 we could skip this and save one extra byte, but
690 * special case of x86 R13 which always needs an offset is not
693 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off);
695 /* 4-byte signed displacement */
696 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off);
702 * Emit a REX byte if it will be necessary to address these registers
704 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64)
709 EMIT1(add_2mod(0x48, dst_reg, src_reg));
710 else if (is_ereg(dst_reg) || is_ereg(src_reg))
711 EMIT1(add_2mod(0x40, dst_reg, src_reg));
716 * Similar version of maybe_emit_mod() for a single register
718 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64)
723 EMIT1(add_1mod(0x48, reg));
724 else if (is_ereg(reg))
725 EMIT1(add_1mod(0x40, reg));
729 /* LDX: dst_reg = *(u8*)(src_reg + off) */
730 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
736 /* Emit 'movzx rax, byte ptr [rax + off]' */
737 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
740 /* Emit 'movzx rax, word ptr [rax + off]' */
741 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
744 /* Emit 'mov eax, dword ptr [rax+0x14]' */
745 if (is_ereg(dst_reg) || is_ereg(src_reg))
746 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
751 /* Emit 'mov rax, qword ptr [rax+0x14]' */
752 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
755 emit_insn_suffix(&prog, src_reg, dst_reg, off);
759 /* STX: *(u8*)(dst_reg + off) = src_reg */
760 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
766 /* Emit 'mov byte ptr [rax + off], al' */
767 if (is_ereg(dst_reg) || is_ereg_8l(src_reg))
768 /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */
769 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
774 if (is_ereg(dst_reg) || is_ereg(src_reg))
775 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
780 if (is_ereg(dst_reg) || is_ereg(src_reg))
781 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
786 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
789 emit_insn_suffix(&prog, dst_reg, src_reg, off);
793 static int emit_atomic(u8 **pprog, u8 atomic_op,
794 u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size)
798 EMIT1(0xF0); /* lock prefix */
800 maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW);
809 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */
810 EMIT1(simple_alu_opcodes[atomic_op]);
812 case BPF_ADD | BPF_FETCH:
813 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */
817 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */
821 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */
825 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op);
829 emit_insn_suffix(&prog, dst_reg, src_reg, off);
835 static bool ex_handler_bpf(const struct exception_table_entry *x,
836 struct pt_regs *regs, int trapnr,
837 unsigned long error_code, unsigned long fault_addr)
839 u32 reg = x->fixup >> 8;
841 /* jump over faulting load and clear dest register */
842 *(unsigned long *)((void *)regs + reg) = 0;
843 regs->ip += x->fixup & 0xff;
847 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt,
848 bool *regs_used, bool *tail_call_seen)
852 for (i = 1; i <= insn_cnt; i++, insn++) {
853 if (insn->code == (BPF_JMP | BPF_TAIL_CALL))
854 *tail_call_seen = true;
855 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6)
857 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7)
859 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8)
861 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9)
866 static void emit_nops(u8 **pprog, int len)
874 if (noplen > ASM_NOP_MAX)
875 noplen = ASM_NOP_MAX;
877 for (i = 0; i < noplen; i++)
878 EMIT1(x86_nops[noplen][i]);
885 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp)))
887 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
888 int oldproglen, struct jit_context *ctx, bool jmp_padding)
890 bool tail_call_reachable = bpf_prog->aux->tail_call_reachable;
891 struct bpf_insn *insn = bpf_prog->insnsi;
892 bool callee_regs_used[4] = {};
893 int insn_cnt = bpf_prog->len;
894 bool tail_call_seen = false;
895 bool seen_exit = false;
896 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
898 int ilen, proglen = 0;
902 detect_reg_usage(insn, insn_cnt, callee_regs_used,
905 /* tail call's presence in current prog implies it is reachable */
906 tail_call_reachable |= tail_call_seen;
908 emit_prologue(&prog, bpf_prog->aux->stack_depth,
909 bpf_prog_was_classic(bpf_prog), tail_call_reachable,
910 bpf_prog->aux->func_idx != 0);
911 push_callee_regs(&prog, callee_regs_used);
915 memcpy(image + proglen, temp, ilen);
920 for (i = 1; i <= insn_cnt; i++, insn++) {
921 const s32 imm32 = insn->imm;
922 u32 dst_reg = insn->dst_reg;
923 u32 src_reg = insn->src_reg;
931 switch (insn->code) {
933 case BPF_ALU | BPF_ADD | BPF_X:
934 case BPF_ALU | BPF_SUB | BPF_X:
935 case BPF_ALU | BPF_AND | BPF_X:
936 case BPF_ALU | BPF_OR | BPF_X:
937 case BPF_ALU | BPF_XOR | BPF_X:
938 case BPF_ALU64 | BPF_ADD | BPF_X:
939 case BPF_ALU64 | BPF_SUB | BPF_X:
940 case BPF_ALU64 | BPF_AND | BPF_X:
941 case BPF_ALU64 | BPF_OR | BPF_X:
942 case BPF_ALU64 | BPF_XOR | BPF_X:
943 maybe_emit_mod(&prog, dst_reg, src_reg,
944 BPF_CLASS(insn->code) == BPF_ALU64);
945 b2 = simple_alu_opcodes[BPF_OP(insn->code)];
946 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
949 case BPF_ALU64 | BPF_MOV | BPF_X:
950 case BPF_ALU | BPF_MOV | BPF_X:
952 BPF_CLASS(insn->code) == BPF_ALU64,
957 case BPF_ALU | BPF_NEG:
958 case BPF_ALU64 | BPF_NEG:
959 maybe_emit_1mod(&prog, dst_reg,
960 BPF_CLASS(insn->code) == BPF_ALU64);
961 EMIT2(0xF7, add_1reg(0xD8, dst_reg));
964 case BPF_ALU | BPF_ADD | BPF_K:
965 case BPF_ALU | BPF_SUB | BPF_K:
966 case BPF_ALU | BPF_AND | BPF_K:
967 case BPF_ALU | BPF_OR | BPF_K:
968 case BPF_ALU | BPF_XOR | BPF_K:
969 case BPF_ALU64 | BPF_ADD | BPF_K:
970 case BPF_ALU64 | BPF_SUB | BPF_K:
971 case BPF_ALU64 | BPF_AND | BPF_K:
972 case BPF_ALU64 | BPF_OR | BPF_K:
973 case BPF_ALU64 | BPF_XOR | BPF_K:
974 maybe_emit_1mod(&prog, dst_reg,
975 BPF_CLASS(insn->code) == BPF_ALU64);
978 * b3 holds 'normal' opcode, b2 short form only valid
979 * in case dst is eax/rax.
981 switch (BPF_OP(insn->code)) {
1005 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
1006 else if (is_axreg(dst_reg))
1007 EMIT1_off32(b2, imm32);
1009 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1012 case BPF_ALU64 | BPF_MOV | BPF_K:
1013 case BPF_ALU | BPF_MOV | BPF_K:
1014 emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64,
1018 case BPF_LD | BPF_IMM | BPF_DW:
1019 emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm);
1024 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
1025 case BPF_ALU | BPF_MOD | BPF_X:
1026 case BPF_ALU | BPF_DIV | BPF_X:
1027 case BPF_ALU | BPF_MOD | BPF_K:
1028 case BPF_ALU | BPF_DIV | BPF_K:
1029 case BPF_ALU64 | BPF_MOD | BPF_X:
1030 case BPF_ALU64 | BPF_DIV | BPF_X:
1031 case BPF_ALU64 | BPF_MOD | BPF_K:
1032 case BPF_ALU64 | BPF_DIV | BPF_K:
1033 EMIT1(0x50); /* push rax */
1034 EMIT1(0x52); /* push rdx */
1036 if (BPF_SRC(insn->code) == BPF_X)
1037 /* mov r11, src_reg */
1038 EMIT_mov(AUX_REG, src_reg);
1040 /* mov r11, imm32 */
1041 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
1043 /* mov rax, dst_reg */
1044 EMIT_mov(BPF_REG_0, dst_reg);
1048 * equivalent to 'xor rdx, rdx', but one byte less
1052 if (BPF_CLASS(insn->code) == BPF_ALU64)
1054 EMIT3(0x49, 0xF7, 0xF3);
1057 EMIT3(0x41, 0xF7, 0xF3);
1059 if (BPF_OP(insn->code) == BPF_MOD)
1061 EMIT3(0x49, 0x89, 0xD3);
1064 EMIT3(0x49, 0x89, 0xC3);
1066 EMIT1(0x5A); /* pop rdx */
1067 EMIT1(0x58); /* pop rax */
1069 /* mov dst_reg, r11 */
1070 EMIT_mov(dst_reg, AUX_REG);
1073 case BPF_ALU | BPF_MUL | BPF_K:
1074 case BPF_ALU | BPF_MUL | BPF_X:
1075 case BPF_ALU64 | BPF_MUL | BPF_K:
1076 case BPF_ALU64 | BPF_MUL | BPF_X:
1078 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1080 if (dst_reg != BPF_REG_0)
1081 EMIT1(0x50); /* push rax */
1082 if (dst_reg != BPF_REG_3)
1083 EMIT1(0x52); /* push rdx */
1085 /* mov r11, dst_reg */
1086 EMIT_mov(AUX_REG, dst_reg);
1088 if (BPF_SRC(insn->code) == BPF_X)
1089 emit_mov_reg(&prog, is64, BPF_REG_0, src_reg);
1091 emit_mov_imm32(&prog, is64, BPF_REG_0, imm32);
1094 EMIT1(add_1mod(0x48, AUX_REG));
1095 else if (is_ereg(AUX_REG))
1096 EMIT1(add_1mod(0x40, AUX_REG));
1098 EMIT2(0xF7, add_1reg(0xE0, AUX_REG));
1100 if (dst_reg != BPF_REG_3)
1101 EMIT1(0x5A); /* pop rdx */
1102 if (dst_reg != BPF_REG_0) {
1103 /* mov dst_reg, rax */
1104 EMIT_mov(dst_reg, BPF_REG_0);
1105 EMIT1(0x58); /* pop rax */
1110 case BPF_ALU | BPF_LSH | BPF_K:
1111 case BPF_ALU | BPF_RSH | BPF_K:
1112 case BPF_ALU | BPF_ARSH | BPF_K:
1113 case BPF_ALU64 | BPF_LSH | BPF_K:
1114 case BPF_ALU64 | BPF_RSH | BPF_K:
1115 case BPF_ALU64 | BPF_ARSH | BPF_K:
1116 maybe_emit_1mod(&prog, dst_reg,
1117 BPF_CLASS(insn->code) == BPF_ALU64);
1119 b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1121 EMIT2(0xD1, add_1reg(b3, dst_reg));
1123 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1126 case BPF_ALU | BPF_LSH | BPF_X:
1127 case BPF_ALU | BPF_RSH | BPF_X:
1128 case BPF_ALU | BPF_ARSH | BPF_X:
1129 case BPF_ALU64 | BPF_LSH | BPF_X:
1130 case BPF_ALU64 | BPF_RSH | BPF_X:
1131 case BPF_ALU64 | BPF_ARSH | BPF_X:
1133 /* Check for bad case when dst_reg == rcx */
1134 if (dst_reg == BPF_REG_4) {
1135 /* mov r11, dst_reg */
1136 EMIT_mov(AUX_REG, dst_reg);
1140 if (src_reg != BPF_REG_4) { /* common case */
1141 EMIT1(0x51); /* push rcx */
1143 /* mov rcx, src_reg */
1144 EMIT_mov(BPF_REG_4, src_reg);
1147 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
1148 maybe_emit_1mod(&prog, dst_reg,
1149 BPF_CLASS(insn->code) == BPF_ALU64);
1151 b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1152 EMIT2(0xD3, add_1reg(b3, dst_reg));
1154 if (src_reg != BPF_REG_4)
1155 EMIT1(0x59); /* pop rcx */
1157 if (insn->dst_reg == BPF_REG_4)
1158 /* mov dst_reg, r11 */
1159 EMIT_mov(insn->dst_reg, AUX_REG);
1162 case BPF_ALU | BPF_END | BPF_FROM_BE:
1165 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
1167 if (is_ereg(dst_reg))
1169 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
1171 /* Emit 'movzwl eax, ax' */
1172 if (is_ereg(dst_reg))
1173 EMIT3(0x45, 0x0F, 0xB7);
1176 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1179 /* Emit 'bswap eax' to swap lower 4 bytes */
1180 if (is_ereg(dst_reg))
1184 EMIT1(add_1reg(0xC8, dst_reg));
1187 /* Emit 'bswap rax' to swap 8 bytes */
1188 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
1189 add_1reg(0xC8, dst_reg));
1194 case BPF_ALU | BPF_END | BPF_FROM_LE:
1198 * Emit 'movzwl eax, ax' to zero extend 16-bit
1201 if (is_ereg(dst_reg))
1202 EMIT3(0x45, 0x0F, 0xB7);
1205 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1208 /* Emit 'mov eax, eax' to clear upper 32-bits */
1209 if (is_ereg(dst_reg))
1211 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
1219 /* speculation barrier */
1220 case BPF_ST | BPF_NOSPEC:
1221 if (boot_cpu_has(X86_FEATURE_XMM2))
1225 /* ST: *(u8*)(dst_reg + off) = imm */
1226 case BPF_ST | BPF_MEM | BPF_B:
1227 if (is_ereg(dst_reg))
1232 case BPF_ST | BPF_MEM | BPF_H:
1233 if (is_ereg(dst_reg))
1234 EMIT3(0x66, 0x41, 0xC7);
1238 case BPF_ST | BPF_MEM | BPF_W:
1239 if (is_ereg(dst_reg))
1244 case BPF_ST | BPF_MEM | BPF_DW:
1245 EMIT2(add_1mod(0x48, dst_reg), 0xC7);
1247 st: if (is_imm8(insn->off))
1248 EMIT2(add_1reg(0x40, dst_reg), insn->off);
1250 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
1252 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
1255 /* STX: *(u8*)(dst_reg + off) = src_reg */
1256 case BPF_STX | BPF_MEM | BPF_B:
1257 case BPF_STX | BPF_MEM | BPF_H:
1258 case BPF_STX | BPF_MEM | BPF_W:
1259 case BPF_STX | BPF_MEM | BPF_DW:
1260 emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1263 /* LDX: dst_reg = *(u8*)(src_reg + off) */
1264 case BPF_LDX | BPF_MEM | BPF_B:
1265 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1266 case BPF_LDX | BPF_MEM | BPF_H:
1267 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1268 case BPF_LDX | BPF_MEM | BPF_W:
1269 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1270 case BPF_LDX | BPF_MEM | BPF_DW:
1271 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1272 if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1273 /* Though the verifier prevents negative insn->off in BPF_PROBE_MEM
1274 * add abs(insn->off) to the limit to make sure that negative
1275 * offset won't be an issue.
1276 * insn->off is s16, so it won't affect valid pointers.
1278 u64 limit = TASK_SIZE_MAX + PAGE_SIZE + abs(insn->off);
1279 u8 *end_of_jmp1, *end_of_jmp2;
1281 /* Conservatively check that src_reg + insn->off is a kernel address:
1282 * 1. src_reg + insn->off >= limit
1283 * 2. src_reg + insn->off doesn't become small positive.
1284 * Cannot do src_reg + insn->off >= limit in one branch,
1285 * since it needs two spare registers, but JIT has only one.
1288 /* movabsq r11, limit */
1289 EMIT2(add_1mod(0x48, AUX_REG), add_1reg(0xB8, AUX_REG));
1290 EMIT((u32)limit, 4);
1291 EMIT(limit >> 32, 4);
1292 /* cmp src_reg, r11 */
1293 maybe_emit_mod(&prog, src_reg, AUX_REG, true);
1294 EMIT2(0x39, add_2reg(0xC0, src_reg, AUX_REG));
1295 /* if unsigned '<' goto end_of_jmp2 */
1299 /* mov r11, src_reg */
1300 emit_mov_reg(&prog, true, AUX_REG, src_reg);
1301 /* add r11, insn->off */
1302 maybe_emit_1mod(&prog, AUX_REG, true);
1303 EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off);
1304 /* jmp if not carry to start_of_ldx
1305 * Otherwise ERR_PTR(-EINVAL) + 128 will be the user addr
1306 * that has to be rejected.
1308 EMIT2(0x73 /* JNC */, 0);
1311 /* xor dst_reg, dst_reg */
1312 emit_mov_imm32(&prog, false, dst_reg, 0);
1313 /* jmp byte_after_ldx */
1316 /* populate jmp_offset for JB above to jump to xor dst_reg */
1317 end_of_jmp1[-1] = end_of_jmp2 - end_of_jmp1;
1318 /* populate jmp_offset for JNC above to jump to start_of_ldx */
1319 start_of_ldx = prog;
1320 end_of_jmp2[-1] = start_of_ldx - end_of_jmp2;
1322 emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1323 if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1324 struct exception_table_entry *ex;
1325 u8 *_insn = image + proglen + (start_of_ldx - temp);
1328 /* populate jmp_offset for JMP above */
1329 start_of_ldx[-1] = prog - start_of_ldx;
1331 if (!bpf_prog->aux->extable)
1334 if (excnt >= bpf_prog->aux->num_exentries) {
1335 pr_err("ex gen bug\n");
1338 ex = &bpf_prog->aux->extable[excnt++];
1340 delta = _insn - (u8 *)&ex->insn;
1341 if (!is_simm32(delta)) {
1342 pr_err("extable->insn doesn't fit into 32-bit\n");
1347 delta = (u8 *)ex_handler_bpf - (u8 *)&ex->handler;
1348 if (!is_simm32(delta)) {
1349 pr_err("extable->handler doesn't fit into 32-bit\n");
1352 ex->handler = delta;
1354 if (dst_reg > BPF_REG_9) {
1355 pr_err("verifier error\n");
1359 * Compute size of x86 insn and its target dest x86 register.
1360 * ex_handler_bpf() will use lower 8 bits to adjust
1361 * pt_regs->ip to jump over this x86 instruction
1362 * and upper bits to figure out which pt_regs to zero out.
1363 * End result: x86 insn "mov rbx, qword ptr [rax+0x14]"
1364 * of 4 bytes will be ignored and rbx will be zero inited.
1366 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8);
1370 case BPF_STX | BPF_ATOMIC | BPF_W:
1371 case BPF_STX | BPF_ATOMIC | BPF_DW:
1372 if (insn->imm == (BPF_AND | BPF_FETCH) ||
1373 insn->imm == (BPF_OR | BPF_FETCH) ||
1374 insn->imm == (BPF_XOR | BPF_FETCH)) {
1375 bool is64 = BPF_SIZE(insn->code) == BPF_DW;
1376 u32 real_src_reg = src_reg;
1377 u32 real_dst_reg = dst_reg;
1381 * Can't be implemented with a single x86 insn.
1382 * Need to do a CMPXCHG loop.
1385 /* Will need RAX as a CMPXCHG operand so save R0 */
1386 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0);
1387 if (src_reg == BPF_REG_0)
1388 real_src_reg = BPF_REG_AX;
1389 if (dst_reg == BPF_REG_0)
1390 real_dst_reg = BPF_REG_AX;
1392 branch_target = prog;
1393 /* Load old value */
1394 emit_ldx(&prog, BPF_SIZE(insn->code),
1395 BPF_REG_0, real_dst_reg, insn->off);
1397 * Perform the (commutative) operation locally,
1398 * put the result in the AUX_REG.
1400 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0);
1401 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64);
1402 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)],
1403 add_2reg(0xC0, AUX_REG, real_src_reg));
1404 /* Attempt to swap in new value */
1405 err = emit_atomic(&prog, BPF_CMPXCHG,
1406 real_dst_reg, AUX_REG,
1408 BPF_SIZE(insn->code));
1412 * ZF tells us whether we won the race. If it's
1413 * cleared we need to try again.
1415 EMIT2(X86_JNE, -(prog - branch_target) - 2);
1416 /* Return the pre-modification value */
1417 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0);
1418 /* Restore R0 after clobbering RAX */
1419 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX);
1423 err = emit_atomic(&prog, insn->imm, dst_reg, src_reg,
1424 insn->off, BPF_SIZE(insn->code));
1430 case BPF_JMP | BPF_CALL:
1431 func = (u8 *) __bpf_call_base + imm32;
1432 if (tail_call_reachable) {
1433 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */
1434 EMIT3_off32(0x48, 0x8B, 0x85,
1435 -round_up(bpf_prog->aux->stack_depth, 8) - 8);
1436 if (!imm32 || emit_call(&prog, func, image + addrs[i - 1] + 7))
1439 if (!imm32 || emit_call(&prog, func, image + addrs[i - 1]))
1444 case BPF_JMP | BPF_TAIL_CALL:
1446 emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1],
1447 &prog, image + addrs[i - 1],
1449 bpf_prog->aux->stack_depth,
1452 emit_bpf_tail_call_indirect(&prog,
1454 bpf_prog->aux->stack_depth,
1455 image + addrs[i - 1],
1460 case BPF_JMP | BPF_JEQ | BPF_X:
1461 case BPF_JMP | BPF_JNE | BPF_X:
1462 case BPF_JMP | BPF_JGT | BPF_X:
1463 case BPF_JMP | BPF_JLT | BPF_X:
1464 case BPF_JMP | BPF_JGE | BPF_X:
1465 case BPF_JMP | BPF_JLE | BPF_X:
1466 case BPF_JMP | BPF_JSGT | BPF_X:
1467 case BPF_JMP | BPF_JSLT | BPF_X:
1468 case BPF_JMP | BPF_JSGE | BPF_X:
1469 case BPF_JMP | BPF_JSLE | BPF_X:
1470 case BPF_JMP32 | BPF_JEQ | BPF_X:
1471 case BPF_JMP32 | BPF_JNE | BPF_X:
1472 case BPF_JMP32 | BPF_JGT | BPF_X:
1473 case BPF_JMP32 | BPF_JLT | BPF_X:
1474 case BPF_JMP32 | BPF_JGE | BPF_X:
1475 case BPF_JMP32 | BPF_JLE | BPF_X:
1476 case BPF_JMP32 | BPF_JSGT | BPF_X:
1477 case BPF_JMP32 | BPF_JSLT | BPF_X:
1478 case BPF_JMP32 | BPF_JSGE | BPF_X:
1479 case BPF_JMP32 | BPF_JSLE | BPF_X:
1480 /* cmp dst_reg, src_reg */
1481 maybe_emit_mod(&prog, dst_reg, src_reg,
1482 BPF_CLASS(insn->code) == BPF_JMP);
1483 EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg));
1486 case BPF_JMP | BPF_JSET | BPF_X:
1487 case BPF_JMP32 | BPF_JSET | BPF_X:
1488 /* test dst_reg, src_reg */
1489 maybe_emit_mod(&prog, dst_reg, src_reg,
1490 BPF_CLASS(insn->code) == BPF_JMP);
1491 EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg));
1494 case BPF_JMP | BPF_JSET | BPF_K:
1495 case BPF_JMP32 | BPF_JSET | BPF_K:
1496 /* test dst_reg, imm32 */
1497 maybe_emit_1mod(&prog, dst_reg,
1498 BPF_CLASS(insn->code) == BPF_JMP);
1499 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
1502 case BPF_JMP | BPF_JEQ | BPF_K:
1503 case BPF_JMP | BPF_JNE | BPF_K:
1504 case BPF_JMP | BPF_JGT | BPF_K:
1505 case BPF_JMP | BPF_JLT | BPF_K:
1506 case BPF_JMP | BPF_JGE | BPF_K:
1507 case BPF_JMP | BPF_JLE | BPF_K:
1508 case BPF_JMP | BPF_JSGT | BPF_K:
1509 case BPF_JMP | BPF_JSLT | BPF_K:
1510 case BPF_JMP | BPF_JSGE | BPF_K:
1511 case BPF_JMP | BPF_JSLE | BPF_K:
1512 case BPF_JMP32 | BPF_JEQ | BPF_K:
1513 case BPF_JMP32 | BPF_JNE | BPF_K:
1514 case BPF_JMP32 | BPF_JGT | BPF_K:
1515 case BPF_JMP32 | BPF_JLT | BPF_K:
1516 case BPF_JMP32 | BPF_JGE | BPF_K:
1517 case BPF_JMP32 | BPF_JLE | BPF_K:
1518 case BPF_JMP32 | BPF_JSGT | BPF_K:
1519 case BPF_JMP32 | BPF_JSLT | BPF_K:
1520 case BPF_JMP32 | BPF_JSGE | BPF_K:
1521 case BPF_JMP32 | BPF_JSLE | BPF_K:
1522 /* test dst_reg, dst_reg to save one extra byte */
1524 maybe_emit_mod(&prog, dst_reg, dst_reg,
1525 BPF_CLASS(insn->code) == BPF_JMP);
1526 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
1530 /* cmp dst_reg, imm8/32 */
1531 maybe_emit_1mod(&prog, dst_reg,
1532 BPF_CLASS(insn->code) == BPF_JMP);
1535 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
1537 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
1539 emit_cond_jmp: /* Convert BPF opcode to x86 */
1540 switch (BPF_OP(insn->code)) {
1549 /* GT is unsigned '>', JA in x86 */
1553 /* LT is unsigned '<', JB in x86 */
1557 /* GE is unsigned '>=', JAE in x86 */
1561 /* LE is unsigned '<=', JBE in x86 */
1565 /* Signed '>', GT in x86 */
1569 /* Signed '<', LT in x86 */
1573 /* Signed '>=', GE in x86 */
1577 /* Signed '<=', LE in x86 */
1580 default: /* to silence GCC warning */
1583 jmp_offset = addrs[i + insn->off] - addrs[i];
1584 if (is_imm8(jmp_offset)) {
1586 /* To keep the jmp_offset valid, the extra bytes are
1587 * padded before the jump insn, so we subtract the
1588 * 2 bytes of jmp_cond insn from INSN_SZ_DIFF.
1590 * If the previous pass already emits an imm8
1591 * jmp_cond, then this BPF insn won't shrink, so
1594 * On the other hand, if the previous pass emits an
1595 * imm32 jmp_cond, the extra 4 bytes(*) is padded to
1596 * keep the image from shrinking further.
1598 * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond
1599 * is 2 bytes, so the size difference is 4 bytes.
1601 nops = INSN_SZ_DIFF - 2;
1602 if (nops != 0 && nops != 4) {
1603 pr_err("unexpected jmp_cond padding: %d bytes\n",
1607 emit_nops(&prog, nops);
1609 EMIT2(jmp_cond, jmp_offset);
1610 } else if (is_simm32(jmp_offset)) {
1611 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
1613 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
1619 case BPF_JMP | BPF_JA:
1620 if (insn->off == -1)
1621 /* -1 jmp instructions will always jump
1622 * backwards two bytes. Explicitly handling
1623 * this case avoids wasting too many passes
1624 * when there are long sequences of replaced
1629 jmp_offset = addrs[i + insn->off] - addrs[i];
1633 * If jmp_padding is enabled, the extra nops will
1634 * be inserted. Otherwise, optimize out nop jumps.
1637 /* There are 3 possible conditions.
1638 * (1) This BPF_JA is already optimized out in
1639 * the previous run, so there is no need
1640 * to pad any extra byte (0 byte).
1641 * (2) The previous pass emits an imm8 jmp,
1642 * so we pad 2 bytes to match the previous
1644 * (3) Similarly, the previous pass emits an
1645 * imm32 jmp, and 5 bytes is padded.
1647 nops = INSN_SZ_DIFF;
1648 if (nops != 0 && nops != 2 && nops != 5) {
1649 pr_err("unexpected nop jump padding: %d bytes\n",
1653 emit_nops(&prog, nops);
1658 if (is_imm8(jmp_offset)) {
1660 /* To avoid breaking jmp_offset, the extra bytes
1661 * are padded before the actual jmp insn, so
1662 * 2 bytes is subtracted from INSN_SZ_DIFF.
1664 * If the previous pass already emits an imm8
1665 * jmp, there is nothing to pad (0 byte).
1667 * If it emits an imm32 jmp (5 bytes) previously
1668 * and now an imm8 jmp (2 bytes), then we pad
1669 * (5 - 2 = 3) bytes to stop the image from
1670 * shrinking further.
1672 nops = INSN_SZ_DIFF - 2;
1673 if (nops != 0 && nops != 3) {
1674 pr_err("unexpected jump padding: %d bytes\n",
1678 emit_nops(&prog, INSN_SZ_DIFF - 2);
1680 EMIT2(0xEB, jmp_offset);
1681 } else if (is_simm32(jmp_offset)) {
1682 EMIT1_off32(0xE9, jmp_offset);
1684 pr_err("jmp gen bug %llx\n", jmp_offset);
1689 case BPF_JMP | BPF_EXIT:
1691 jmp_offset = ctx->cleanup_addr - addrs[i];
1695 /* Update cleanup_addr */
1696 ctx->cleanup_addr = proglen;
1697 pop_callee_regs(&prog, callee_regs_used);
1698 EMIT1(0xC9); /* leave */
1699 emit_return(&prog, image + addrs[i - 1] + (prog - temp));
1704 * By design x86-64 JIT should support all BPF instructions.
1705 * This error will be seen if new instruction was added
1706 * to the interpreter, but not to the JIT, or if there is
1709 pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
1714 if (ilen > BPF_MAX_INSN_SIZE) {
1715 pr_err("bpf_jit: fatal insn size error\n");
1721 * When populating the image, assert that:
1723 * i) We do not write beyond the allocated space, and
1724 * ii) addrs[i] did not change from the prior run, in order
1725 * to validate assumptions made for computing branch
1728 if (unlikely(proglen + ilen > oldproglen ||
1729 proglen + ilen != addrs[i])) {
1730 pr_err("bpf_jit: fatal error\n");
1733 memcpy(image + proglen, temp, ilen);
1740 if (image && excnt != bpf_prog->aux->num_exentries) {
1741 pr_err("extable is not populated\n");
1747 static void save_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1751 /* Store function arguments to stack.
1752 * For a function that accepts two pointers the sequence will be:
1753 * mov QWORD PTR [rbp-0x10],rdi
1754 * mov QWORD PTR [rbp-0x8],rsi
1756 for (i = 0; i < min(nr_args, 6); i++)
1757 emit_stx(prog, bytes_to_bpf_size(m->arg_size[i]),
1759 i == 5 ? X86_REG_R9 : BPF_REG_1 + i,
1760 -(stack_size - i * 8));
1763 static void restore_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1768 /* Restore function arguments from stack.
1769 * For a function that accepts two pointers the sequence will be:
1770 * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10]
1771 * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8]
1773 for (i = 0; i < min(nr_args, 6); i++)
1774 emit_ldx(prog, bytes_to_bpf_size(m->arg_size[i]),
1775 i == 5 ? X86_REG_R9 : BPF_REG_1 + i,
1777 -(stack_size - i * 8));
1780 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog,
1781 struct bpf_prog *p, int stack_size, bool save_ret)
1786 /* arg1: mov rdi, progs[i] */
1787 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1788 if (emit_call(&prog,
1789 p->aux->sleepable ? __bpf_prog_enter_sleepable :
1790 __bpf_prog_enter, prog))
1792 /* remember prog start time returned by __bpf_prog_enter */
1793 emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0);
1795 /* if (__bpf_prog_enter*(prog) == 0)
1796 * goto skip_exec_of_prog;
1798 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */
1799 /* emit 2 nops that will be replaced with JE insn */
1801 emit_nops(&prog, 2);
1803 /* arg1: lea rdi, [rbp - stack_size] */
1804 EMIT4(0x48, 0x8D, 0x7D, -stack_size);
1805 /* arg2: progs[i]->insnsi for interpreter */
1807 emit_mov_imm64(&prog, BPF_REG_2,
1808 (long) p->insnsi >> 32,
1809 (u32) (long) p->insnsi);
1810 /* call JITed bpf program or interpreter */
1811 if (emit_call(&prog, p->bpf_func, prog))
1815 * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return
1816 * of the previous call which is then passed on the stack to
1817 * the next BPF program.
1819 * BPF_TRAMP_FENTRY trampoline may need to return the return
1820 * value of BPF_PROG_TYPE_STRUCT_OPS prog.
1823 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1825 /* replace 2 nops with JE insn, since jmp target is known */
1826 jmp_insn[0] = X86_JE;
1827 jmp_insn[1] = prog - jmp_insn - 2;
1829 /* arg1: mov rdi, progs[i] */
1830 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1831 /* arg2: mov rsi, rbx <- start time in nsec */
1832 emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6);
1833 if (emit_call(&prog,
1834 p->aux->sleepable ? __bpf_prog_exit_sleepable :
1835 __bpf_prog_exit, prog))
1842 static void emit_align(u8 **pprog, u32 align)
1844 u8 *target, *prog = *pprog;
1846 target = PTR_ALIGN(prog, align);
1848 emit_nops(&prog, target - prog);
1853 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond)
1858 offset = func - (ip + 2 + 4);
1859 if (!is_simm32(offset)) {
1860 pr_err("Target %p is out of range\n", func);
1863 EMIT2_off32(0x0F, jmp_cond + 0x10, offset);
1868 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog,
1869 struct bpf_tramp_progs *tp, int stack_size,
1875 for (i = 0; i < tp->nr_progs; i++) {
1876 if (invoke_bpf_prog(m, &prog, tp->progs[i], stack_size,
1884 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog,
1885 struct bpf_tramp_progs *tp, int stack_size,
1891 /* The first fmod_ret program will receive a garbage return value.
1892 * Set this to 0 to avoid confusing the program.
1894 emit_mov_imm32(&prog, false, BPF_REG_0, 0);
1895 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1896 for (i = 0; i < tp->nr_progs; i++) {
1897 if (invoke_bpf_prog(m, &prog, tp->progs[i], stack_size, true))
1900 /* mod_ret prog stored return value into [rbp - 8]. Emit:
1901 * if (*(u64 *)(rbp - 8) != 0)
1904 /* cmp QWORD PTR [rbp - 0x8], 0x0 */
1905 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00);
1907 /* Save the location of the branch and Generate 6 nops
1908 * (4 bytes for an offset and 2 bytes for the jump) These nops
1909 * are replaced with a conditional jump once do_fexit (i.e. the
1910 * start of the fexit invocation) is finalized.
1913 emit_nops(&prog, 4 + 2);
1920 static bool is_valid_bpf_tramp_flags(unsigned int flags)
1922 if ((flags & BPF_TRAMP_F_RESTORE_REGS) &&
1923 (flags & BPF_TRAMP_F_SKIP_FRAME))
1927 * BPF_TRAMP_F_RET_FENTRY_RET is only used by bpf_struct_ops,
1928 * and it must be used alone.
1930 if ((flags & BPF_TRAMP_F_RET_FENTRY_RET) &&
1931 (flags & ~BPF_TRAMP_F_RET_FENTRY_RET))
1938 * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev);
1939 * its 'struct btf_func_model' will be nr_args=2
1940 * The assembly code when eth_type_trans is executing after trampoline:
1944 * sub rsp, 16 // space for skb and dev
1945 * push rbx // temp regs to pass start time
1946 * mov qword ptr [rbp - 16], rdi // save skb pointer to stack
1947 * mov qword ptr [rbp - 8], rsi // save dev pointer to stack
1948 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
1949 * mov rbx, rax // remember start time in bpf stats are enabled
1950 * lea rdi, [rbp - 16] // R1==ctx of bpf prog
1951 * call addr_of_jited_FENTRY_prog
1952 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
1953 * mov rsi, rbx // prog start time
1954 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
1955 * mov rdi, qword ptr [rbp - 16] // restore skb pointer from stack
1956 * mov rsi, qword ptr [rbp - 8] // restore dev pointer from stack
1961 * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be
1962 * replaced with 'call generated_bpf_trampoline'. When it returns
1963 * eth_type_trans will continue executing with original skb and dev pointers.
1965 * The assembly code when eth_type_trans is called from trampoline:
1969 * sub rsp, 24 // space for skb, dev, return value
1970 * push rbx // temp regs to pass start time
1971 * mov qword ptr [rbp - 24], rdi // save skb pointer to stack
1972 * mov qword ptr [rbp - 16], rsi // save dev pointer to stack
1973 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
1974 * mov rbx, rax // remember start time if bpf stats are enabled
1975 * lea rdi, [rbp - 24] // R1==ctx of bpf prog
1976 * call addr_of_jited_FENTRY_prog // bpf prog can access skb and dev
1977 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
1978 * mov rsi, rbx // prog start time
1979 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
1980 * mov rdi, qword ptr [rbp - 24] // restore skb pointer from stack
1981 * mov rsi, qword ptr [rbp - 16] // restore dev pointer from stack
1982 * call eth_type_trans+5 // execute body of eth_type_trans
1983 * mov qword ptr [rbp - 8], rax // save return value
1984 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
1985 * mov rbx, rax // remember start time in bpf stats are enabled
1986 * lea rdi, [rbp - 24] // R1==ctx of bpf prog
1987 * call addr_of_jited_FEXIT_prog // bpf prog can access skb, dev, return value
1988 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
1989 * mov rsi, rbx // prog start time
1990 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
1991 * mov rax, qword ptr [rbp - 8] // restore eth_type_trans's return value
1994 * add rsp, 8 // skip eth_type_trans's frame
1995 * ret // return to its caller
1997 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end,
1998 const struct btf_func_model *m, u32 flags,
1999 struct bpf_tramp_progs *tprogs,
2002 int ret, i, nr_args = m->nr_args;
2003 int stack_size = nr_args * 8;
2004 struct bpf_tramp_progs *fentry = &tprogs[BPF_TRAMP_FENTRY];
2005 struct bpf_tramp_progs *fexit = &tprogs[BPF_TRAMP_FEXIT];
2006 struct bpf_tramp_progs *fmod_ret = &tprogs[BPF_TRAMP_MODIFY_RETURN];
2007 u8 **branches = NULL;
2011 /* x86-64 supports up to 6 arguments. 7+ can be added in the future */
2015 if (!is_valid_bpf_tramp_flags(flags))
2018 /* room for return value of orig_call or fentry prog */
2019 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET);
2023 if (flags & BPF_TRAMP_F_IP_ARG)
2024 stack_size += 8; /* room for IP address argument */
2026 if (flags & BPF_TRAMP_F_SKIP_FRAME)
2027 /* skip patched call instruction and point orig_call to actual
2028 * body of the kernel function.
2030 orig_call += X86_PATCH_SIZE;
2034 EMIT1(0x55); /* push rbp */
2035 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
2036 EMIT4(0x48, 0x83, 0xEC, stack_size); /* sub rsp, stack_size */
2037 EMIT1(0x53); /* push rbx */
2039 if (flags & BPF_TRAMP_F_IP_ARG) {
2040 /* Store IP address of the traced function:
2041 * mov rax, QWORD PTR [rbp + 8]
2042 * sub rax, X86_PATCH_SIZE
2043 * mov QWORD PTR [rbp - stack_size], rax
2045 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 8);
2046 EMIT4(0x48, 0x83, 0xe8, X86_PATCH_SIZE);
2047 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -stack_size);
2049 /* Continue with stack_size for regs storage, stack will
2050 * be correctly restored with 'leave' instruction.
2055 save_regs(m, &prog, nr_args, stack_size);
2057 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2058 /* arg1: mov rdi, im */
2059 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2060 if (emit_call(&prog, __bpf_tramp_enter, prog)) {
2066 if (fentry->nr_progs)
2067 if (invoke_bpf(m, &prog, fentry, stack_size,
2068 flags & BPF_TRAMP_F_RET_FENTRY_RET))
2071 if (fmod_ret->nr_progs) {
2072 branches = kcalloc(fmod_ret->nr_progs, sizeof(u8 *),
2077 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, stack_size,
2084 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2085 restore_regs(m, &prog, nr_args, stack_size);
2087 /* call original function */
2088 if (emit_call(&prog, orig_call, prog)) {
2092 /* remember return value in a stack for bpf prog to access */
2093 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2094 im->ip_after_call = prog;
2095 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
2096 prog += X86_PATCH_SIZE;
2099 if (fmod_ret->nr_progs) {
2100 /* From Intel 64 and IA-32 Architectures Optimization
2101 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2102 * Coding Rule 11: All branch targets should be 16-byte
2105 emit_align(&prog, 16);
2106 /* Update the branches saved in invoke_bpf_mod_ret with the
2107 * aligned address of do_fexit.
2109 for (i = 0; i < fmod_ret->nr_progs; i++)
2110 emit_cond_near_jump(&branches[i], prog, branches[i],
2114 if (fexit->nr_progs)
2115 if (invoke_bpf(m, &prog, fexit, stack_size, false)) {
2120 if (flags & BPF_TRAMP_F_RESTORE_REGS)
2121 restore_regs(m, &prog, nr_args, stack_size);
2123 /* This needs to be done regardless. If there were fmod_ret programs,
2124 * the return value is only updated on the stack and still needs to be
2127 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2128 im->ip_epilogue = prog;
2129 /* arg1: mov rdi, im */
2130 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2131 if (emit_call(&prog, __bpf_tramp_exit, prog)) {
2136 /* restore return value of orig_call or fentry prog back into RAX */
2138 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8);
2140 EMIT1(0x5B); /* pop rbx */
2141 EMIT1(0xC9); /* leave */
2142 if (flags & BPF_TRAMP_F_SKIP_FRAME)
2143 /* skip our return address and return to parent */
2144 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */
2145 emit_return(&prog, prog);
2146 /* Make sure the trampoline generation logic doesn't overflow */
2147 if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) {
2151 ret = prog - (u8 *)image;
2158 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs)
2160 u8 *jg_reloc, *prog = *pprog;
2161 int pivot, err, jg_bytes = 1;
2165 /* Leaf node of recursion, i.e. not a range of indices
2168 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */
2169 if (!is_simm32(progs[a]))
2171 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
2173 err = emit_cond_near_jump(&prog, /* je func */
2174 (void *)progs[a], prog,
2179 emit_indirect_jump(&prog, 2 /* rdx */, prog);
2185 /* Not a leaf node, so we pivot, and recursively descend into
2186 * the lower and upper ranges.
2188 pivot = (b - a) / 2;
2189 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */
2190 if (!is_simm32(progs[a + pivot]))
2192 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
2194 if (pivot > 2) { /* jg upper_part */
2195 /* Require near jump. */
2197 EMIT2_off32(0x0F, X86_JG + 0x10, 0);
2203 err = emit_bpf_dispatcher(&prog, a, a + pivot, /* emit lower_part */
2208 /* From Intel 64 and IA-32 Architectures Optimization
2209 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2210 * Coding Rule 11: All branch targets should be 16-byte
2213 emit_align(&prog, 16);
2214 jg_offset = prog - jg_reloc;
2215 emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes);
2217 err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */
2226 static int cmp_ips(const void *a, const void *b)
2238 int arch_prepare_bpf_dispatcher(void *image, s64 *funcs, int num_funcs)
2242 sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL);
2243 return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs);
2246 struct x64_jit_data {
2247 struct bpf_binary_header *header;
2251 struct jit_context ctx;
2254 #define MAX_PASSES 20
2255 #define PADDING_PASSES (MAX_PASSES - 5)
2257 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2259 struct bpf_binary_header *header = NULL;
2260 struct bpf_prog *tmp, *orig_prog = prog;
2261 struct x64_jit_data *jit_data;
2262 int proglen, oldproglen = 0;
2263 struct jit_context ctx = {};
2264 bool tmp_blinded = false;
2265 bool extra_pass = false;
2266 bool padding = false;
2272 if (!prog->jit_requested)
2275 tmp = bpf_jit_blind_constants(prog);
2277 * If blinding was requested and we failed during blinding,
2278 * we must fall back to the interpreter.
2287 jit_data = prog->aux->jit_data;
2289 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
2294 prog->aux->jit_data = jit_data;
2296 addrs = jit_data->addrs;
2298 ctx = jit_data->ctx;
2299 oldproglen = jit_data->proglen;
2300 image = jit_data->image;
2301 header = jit_data->header;
2304 goto skip_init_addrs;
2306 addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL);
2313 * Before first pass, make a rough estimation of addrs[]
2314 * each BPF instruction is translated to less than 64 bytes
2316 for (proglen = 0, i = 0; i <= prog->len; i++) {
2320 ctx.cleanup_addr = proglen;
2324 * JITed image shrinks with every pass and the loop iterates
2325 * until the image stops shrinking. Very large BPF programs
2326 * may converge on the last pass. In such case do one more
2327 * pass to emit the final image.
2329 for (pass = 0; pass < MAX_PASSES || image; pass++) {
2330 if (!padding && pass >= PADDING_PASSES)
2332 proglen = do_jit(prog, addrs, image, oldproglen, &ctx, padding);
2337 bpf_jit_binary_free(header);
2342 if (proglen != oldproglen) {
2343 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2344 proglen, oldproglen);
2349 if (proglen == oldproglen) {
2351 * The number of entries in extable is the number of BPF_LDX
2352 * insns that access kernel memory via "pointer to BTF type".
2353 * The verifier changed their opcode from LDX|MEM|size
2354 * to LDX|PROBE_MEM|size to make JITing easier.
2356 u32 align = __alignof__(struct exception_table_entry);
2357 u32 extable_size = prog->aux->num_exentries *
2358 sizeof(struct exception_table_entry);
2360 /* allocate module memory for x86 insns and extable */
2361 header = bpf_jit_binary_alloc(roundup(proglen, align) + extable_size,
2362 &image, align, jit_fill_hole);
2367 prog->aux->extable = (void *) image + roundup(proglen, align);
2369 oldproglen = proglen;
2373 if (bpf_jit_enable > 1)
2374 bpf_jit_dump(prog->len, proglen, pass + 1, image);
2377 if (!prog->is_func || extra_pass) {
2378 bpf_tail_call_direct_fixup(prog);
2379 bpf_jit_binary_lock_ro(header);
2381 jit_data->addrs = addrs;
2382 jit_data->ctx = ctx;
2383 jit_data->proglen = proglen;
2384 jit_data->image = image;
2385 jit_data->header = header;
2387 prog->bpf_func = (void *)image;
2389 prog->jited_len = proglen;
2394 if (!image || !prog->is_func || extra_pass) {
2396 bpf_prog_fill_jited_linfo(prog, addrs + 1);
2400 prog->aux->jit_data = NULL;
2404 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2409 bool bpf_jit_supports_kfunc_call(void)