arch/x86/net/bpf_jit_comp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * BPF JIT compiler
   4  *
   5  * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
   6  * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
   7  */
   8 #include <linux/netdevice.h>
   9 #include <linux/filter.h>
  10 #include <linux/if_vlan.h>
  11 #include <linux/bpf.h>
  12 #include <linux/memory.h>
  13 #include <linux/sort.h>
  14 #include <asm/extable.h>
  15 #include <asm/ftrace.h>
  16 #include <asm/set_memory.h>
  17 #include <asm/nospec-branch.h>
  18 #include <asm/text-patching.h>
  19
  20 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
  21 {
  22         if (len == 1)
  23                 *ptr = bytes;
  24         else if (len == 2)
  25                 *(u16 *)ptr = bytes;
  26         else {
  27                 *(u32 *)ptr = bytes;
  28                 barrier();
  29         }
  30         return ptr + len;
  31 }
  32
  33 #define EMIT(bytes, len) \
  34         do { prog = emit_code(prog, bytes, len); } while (0)
  35
  36 #define EMIT1(b1)               EMIT(b1, 1)
  37 #define EMIT2(b1, b2)           EMIT((b1) + ((b2) << 8), 2)
  38 #define EMIT3(b1, b2, b3)       EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
  39 #define EMIT4(b1, b2, b3, b4)   EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
  40
  41 #define EMIT1_off32(b1, off) \
  42         do { EMIT1(b1); EMIT(off, 4); } while (0)
  43 #define EMIT2_off32(b1, b2, off) \
  44         do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
  45 #define EMIT3_off32(b1, b2, b3, off) \
  46         do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
  47 #define EMIT4_off32(b1, b2, b3, b4, off) \
  48         do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
  49
  50 #ifdef CONFIG_X86_KERNEL_IBT
  51 #define EMIT_ENDBR()    EMIT(gen_endbr(), 4)
  52 #else
  53 #define EMIT_ENDBR()
  54 #endif
  55
  56 static bool is_imm8(int value)
  57 {
  58         return value <= 127 && value >= -128;
  59 }
  60
  61 static bool is_simm32(s64 value)
  62 {
  63         return value == (s64)(s32)value;
  64 }
  65
  66 static bool is_uimm32(u64 value)
  67 {
  68         return value == (u64)(u32)value;
  69 }
  70
  71 /* mov dst, src */
  72 #define EMIT_mov(DST, SRC)                                                               \
  73         do {                                                                             \
  74                 if (DST != SRC)                                                          \
  75                         EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
  76         } while (0)
  77
  78 static int bpf_size_to_x86_bytes(int bpf_size)
  79 {
  80         if (bpf_size == BPF_W)
  81                 return 4;
  82         else if (bpf_size == BPF_H)
  83                 return 2;
  84         else if (bpf_size == BPF_B)
  85                 return 1;
  86         else if (bpf_size == BPF_DW)
  87                 return 4; /* imm32 */
  88         else
  89                 return 0;
  90 }
  91
  92 /*
  93  * List of x86 cond jumps opcodes (. + s8)
  94  * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
  95  */
  96 #define X86_JB  0x72
  97 #define X86_JAE 0x73
  98 #define X86_JE  0x74
  99 #define X86_JNE 0x75
 100 #define X86_JBE 0x76
 101 #define X86_JA  0x77
 102 #define X86_JL  0x7C
 103 #define X86_JGE 0x7D
 104 #define X86_JLE 0x7E
 105 #define X86_JG  0x7F
 106
 107 /* Pick a register outside of BPF range for JIT internal work */
 108 #define AUX_REG (MAX_BPF_JIT_REG + 1)
 109 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2)
 110
 111 /*
 112  * The following table maps BPF registers to x86-64 registers.
 113  *
 114  * x86-64 register R12 is unused, since if used as base address
 115  * register in load/store instructions, it always needs an
 116  * extra byte of encoding and is callee saved.
 117  *
 118  * x86-64 register R9 is not used by BPF programs, but can be used by BPF
 119  * trampoline. x86-64 register R10 is used for blinding (if enabled).
 120  */
 121 static const int reg2hex[] = {
 122         [BPF_REG_0] = 0,  /* RAX */
 123         [BPF_REG_1] = 7,  /* RDI */
 124         [BPF_REG_2] = 6,  /* RSI */
 125         [BPF_REG_3] = 2,  /* RDX */
 126         [BPF_REG_4] = 1,  /* RCX */
 127         [BPF_REG_5] = 0,  /* R8  */
 128         [BPF_REG_6] = 3,  /* RBX callee saved */
 129         [BPF_REG_7] = 5,  /* R13 callee saved */
 130         [BPF_REG_8] = 6,  /* R14 callee saved */
 131         [BPF_REG_9] = 7,  /* R15 callee saved */
 132         [BPF_REG_FP] = 5, /* RBP readonly */
 133         [BPF_REG_AX] = 2, /* R10 temp register */
 134         [AUX_REG] = 3,    /* R11 temp register */
 135         [X86_REG_R9] = 1, /* R9 register, 6th function argument */
 136 };
 137
 138 static const int reg2pt_regs[] = {
 139         [BPF_REG_0] = offsetof(struct pt_regs, ax),
 140         [BPF_REG_1] = offsetof(struct pt_regs, di),
 141         [BPF_REG_2] = offsetof(struct pt_regs, si),
 142         [BPF_REG_3] = offsetof(struct pt_regs, dx),
 143         [BPF_REG_4] = offsetof(struct pt_regs, cx),
 144         [BPF_REG_5] = offsetof(struct pt_regs, r8),
 145         [BPF_REG_6] = offsetof(struct pt_regs, bx),
 146         [BPF_REG_7] = offsetof(struct pt_regs, r13),
 147         [BPF_REG_8] = offsetof(struct pt_regs, r14),
 148         [BPF_REG_9] = offsetof(struct pt_regs, r15),
 149 };
 150
 151 /*
 152  * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15
 153  * which need extra byte of encoding.
 154  * rax,rcx,...,rbp have simpler encoding
 155  */
 156 static bool is_ereg(u32 reg)
 157 {
 158         return (1 << reg) & (BIT(BPF_REG_5) |
 159                              BIT(AUX_REG) |
 160                              BIT(BPF_REG_7) |
 161                              BIT(BPF_REG_8) |
 162                              BIT(BPF_REG_9) |
 163                              BIT(X86_REG_R9) |
 164                              BIT(BPF_REG_AX));
 165 }
 166
 167 /*
 168  * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64
 169  * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte
 170  * of encoding. al,cl,dl,bl have simpler encoding.
 171  */
 172 static bool is_ereg_8l(u32 reg)
 173 {
 174         return is_ereg(reg) ||
 175             (1 << reg) & (BIT(BPF_REG_1) |
 176                           BIT(BPF_REG_2) |
 177                           BIT(BPF_REG_FP));
 178 }
 179
 180 static bool is_axreg(u32 reg)
 181 {
 182         return reg == BPF_REG_0;
 183 }
 184
 185 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */
 186 static u8 add_1mod(u8 byte, u32 reg)
 187 {
 188         if (is_ereg(reg))
 189                 byte |= 1;
 190         return byte;
 191 }
 192
 193 static u8 add_2mod(u8 byte, u32 r1, u32 r2)
 194 {
 195         if (is_ereg(r1))
 196                 byte |= 1;
 197         if (is_ereg(r2))
 198                 byte |= 4;
 199         return byte;
 200 }
 201
 202 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */
 203 static u8 add_1reg(u8 byte, u32 dst_reg)
 204 {
 205         return byte + reg2hex[dst_reg];
 206 }
 207
 208 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */
 209 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
 210 {
 211         return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
 212 }
 213
 214 /* Some 1-byte opcodes for binary ALU operations */
 215 static u8 simple_alu_opcodes[] = {
 216         [BPF_ADD] = 0x01,
 217         [BPF_SUB] = 0x29,
 218         [BPF_AND] = 0x21,
 219         [BPF_OR] = 0x09,
 220         [BPF_XOR] = 0x31,
 221         [BPF_LSH] = 0xE0,
 222         [BPF_RSH] = 0xE8,
 223         [BPF_ARSH] = 0xF8,
 224 };
 225
 226 static void jit_fill_hole(void *area, unsigned int size)
 227 {
 228         /* Fill whole space with INT3 instructions */
 229         memset(area, 0xcc, size);
 230 }
 231
 232 int bpf_arch_text_invalidate(void *dst, size_t len)
 233 {
 234         return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len));
 235 }
 236
 237 struct jit_context {
 238         int cleanup_addr; /* Epilogue code offset */
 239
 240         /*
 241          * Program specific offsets of labels in the code; these rely on the
 242          * JIT doing at least 2 passes, recording the position on the first
 243          * pass, only to generate the correct offset on the second pass.
 244          */
 245         int tail_call_direct_label;
 246         int tail_call_indirect_label;
 247 };
 248
 249 /* Maximum number of bytes emitted while JITing one eBPF insn */
 250 #define BPF_MAX_INSN_SIZE       128
 251 #define BPF_INSN_SAFETY         64
 252
 253 /* Number of bytes emit_patch() needs to generate instructions */
 254 #define X86_PATCH_SIZE          5
 255 /* Number of bytes that will be skipped on tailcall */
 256 #define X86_TAIL_CALL_OFFSET    (11 + ENDBR_INSN_SIZE)
 257
 258 static void push_callee_regs(u8 **pprog, bool *callee_regs_used)
 259 {
 260         u8 *prog = *pprog;
 261
 262         if (callee_regs_used[0])
 263                 EMIT1(0x53);         /* push rbx */
 264         if (callee_regs_used[1])
 265                 EMIT2(0x41, 0x55);   /* push r13 */
 266         if (callee_regs_used[2])
 267                 EMIT2(0x41, 0x56);   /* push r14 */
 268         if (callee_regs_used[3])
 269                 EMIT2(0x41, 0x57);   /* push r15 */
 270         *pprog = prog;
 271 }
 272
 273 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used)
 274 {
 275         u8 *prog = *pprog;
 276
 277         if (callee_regs_used[3])
 278                 EMIT2(0x41, 0x5F);   /* pop r15 */
 279         if (callee_regs_used[2])
 280                 EMIT2(0x41, 0x5E);   /* pop r14 */
 281         if (callee_regs_used[1])
 282                 EMIT2(0x41, 0x5D);   /* pop r13 */
 283         if (callee_regs_used[0])
 284                 EMIT1(0x5B);         /* pop rbx */
 285         *pprog = prog;
 286 }
 287
 288 /*
 289  * Emit x86-64 prologue code for BPF program.
 290  * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes
 291  * while jumping to another program
 292  */
 293 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf,
 294                           bool tail_call_reachable, bool is_subprog)
 295 {
 296         u8 *prog = *pprog;
 297
 298         /* BPF trampoline can be made to work without these nops,
 299          * but let's waste 5 bytes for now and optimize later
 300          */
 301         EMIT_ENDBR();
 302         memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
 303         prog += X86_PATCH_SIZE;
 304         if (!ebpf_from_cbpf) {
 305                 if (tail_call_reachable && !is_subprog)
 306                         EMIT2(0x31, 0xC0); /* xor eax, eax */
 307                 else
 308                         EMIT2(0x66, 0x90); /* nop2 */
 309         }
 310         EMIT1(0x55);             /* push rbp */
 311         EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
 312
 313         /* X86_TAIL_CALL_OFFSET is here */
 314         EMIT_ENDBR();
 315
 316         /* sub rsp, rounded_stack_depth */
 317         if (stack_depth)
 318                 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8));
 319         if (tail_call_reachable)
 320                 EMIT1(0x50);         /* push rax */
 321         *pprog = prog;
 322 }
 323
 324 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode)
 325 {
 326         u8 *prog = *pprog;
 327         s64 offset;
 328
 329         offset = func - (ip + X86_PATCH_SIZE);
 330         if (!is_simm32(offset)) {
 331                 pr_err("Target call %p is out of range\n", func);
 332                 return -ERANGE;
 333         }
 334         EMIT1_off32(opcode, offset);
 335         *pprog = prog;
 336         return 0;
 337 }
 338
 339 static int emit_call(u8 **pprog, void *func, void *ip)
 340 {
 341         return emit_patch(pprog, func, ip, 0xE8);
 342 }
 343
 344 static int emit_rsb_call(u8 **pprog, void *func, void *ip)
 345 {
 346         OPTIMIZER_HIDE_VAR(func);
 347         x86_call_depth_emit_accounting(pprog, func);
 348         return emit_patch(pprog, func, ip, 0xE8);
 349 }
 350
 351 static int emit_jump(u8 **pprog, void *func, void *ip)
 352 {
 353         return emit_patch(pprog, func, ip, 0xE9);
 354 }
 355
 356 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
 357                                 void *old_addr, void *new_addr)
 358 {
 359         const u8 *nop_insn = x86_nops[5];
 360         u8 old_insn[X86_PATCH_SIZE];
 361         u8 new_insn[X86_PATCH_SIZE];
 362         u8 *prog;
 363         int ret;
 364
 365         memcpy(old_insn, nop_insn, X86_PATCH_SIZE);
 366         if (old_addr) {
 367                 prog = old_insn;
 368                 ret = t == BPF_MOD_CALL ?
 369                       emit_call(&prog, old_addr, ip) :
 370                       emit_jump(&prog, old_addr, ip);
 371                 if (ret)
 372                         return ret;
 373         }
 374
 375         memcpy(new_insn, nop_insn, X86_PATCH_SIZE);
 376         if (new_addr) {
 377                 prog = new_insn;
 378                 ret = t == BPF_MOD_CALL ?
 379                       emit_call(&prog, new_addr, ip) :
 380                       emit_jump(&prog, new_addr, ip);
 381                 if (ret)
 382                         return ret;
 383         }
 384
 385         ret = -EBUSY;
 386         mutex_lock(&text_mutex);
 387         if (memcmp(ip, old_insn, X86_PATCH_SIZE))
 388                 goto out;
 389         ret = 1;
 390         if (memcmp(ip, new_insn, X86_PATCH_SIZE)) {
 391                 text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL);
 392                 ret = 0;
 393         }
 394 out:
 395         mutex_unlock(&text_mutex);
 396         return ret;
 397 }
 398
 399 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
 400                        void *old_addr, void *new_addr)
 401 {
 402         if (!is_kernel_text((long)ip) &&
 403             !is_bpf_text_address((long)ip))
 404                 /* BPF poking in modules is not supported */
 405                 return -EINVAL;
 406
 407         /*
 408          * See emit_prologue(), for IBT builds the trampoline hook is preceded
 409          * with an ENDBR instruction.
 410          */
 411         if (is_endbr(*(u32 *)ip))
 412                 ip += ENDBR_INSN_SIZE;
 413
 414         return __bpf_arch_text_poke(ip, t, old_addr, new_addr);
 415 }
 416
 417 #define EMIT_LFENCE()   EMIT3(0x0F, 0xAE, 0xE8)
 418
 419 static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip)
 420 {
 421         u8 *prog = *pprog;
 422
 423         if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) {
 424                 EMIT_LFENCE();
 425                 EMIT2(0xFF, 0xE0 + reg);
 426         } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) {
 427                 OPTIMIZER_HIDE_VAR(reg);
 428                 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH))
 429                         emit_jump(&prog, &__x86_indirect_jump_thunk_array[reg], ip);
 430                 else
 431                         emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip);
 432         } else {
 433                 EMIT2(0xFF, 0xE0 + reg);        /* jmp *%\reg */
 434                 if (IS_ENABLED(CONFIG_RETPOLINE) || IS_ENABLED(CONFIG_SLS))
 435                         EMIT1(0xCC);            /* int3 */
 436         }
 437
 438         *pprog = prog;
 439 }
 440
 441 static void emit_return(u8 **pprog, u8 *ip)
 442 {
 443         u8 *prog = *pprog;
 444
 445         if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) {
 446                 emit_jump(&prog, x86_return_thunk, ip);
 447         } else {
 448                 EMIT1(0xC3);            /* ret */
 449                 if (IS_ENABLED(CONFIG_SLS))
 450                         EMIT1(0xCC);    /* int3 */
 451         }
 452
 453         *pprog = prog;
 454 }
 455
 456 /*
 457  * Generate the following code:
 458  *
 459  * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
 460  *   if (index >= array->map.max_entries)
 461  *     goto out;
 462  *   if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
 463  *     goto out;
 464  *   prog = array->ptrs[index];
 465  *   if (prog == NULL)
 466  *     goto out;
 467  *   goto *(prog->bpf_func + prologue_size);
 468  * out:
 469  */
 470 static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used,
 471                                         u32 stack_depth, u8 *ip,
 472                                         struct jit_context *ctx)
 473 {
 474         int tcc_off = -4 - round_up(stack_depth, 8);
 475         u8 *prog = *pprog, *start = *pprog;
 476         int offset;
 477
 478         /*
 479          * rdi - pointer to ctx
 480          * rsi - pointer to bpf_array
 481          * rdx - index in bpf_array
 482          */
 483
 484         /*
 485          * if (index >= array->map.max_entries)
 486          *      goto out;
 487          */
 488         EMIT2(0x89, 0xD2);                        /* mov edx, edx */
 489         EMIT3(0x39, 0x56,                         /* cmp dword ptr [rsi + 16], edx */
 490               offsetof(struct bpf_array, map.max_entries));
 491
 492         offset = ctx->tail_call_indirect_label - (prog + 2 - start);
 493         EMIT2(X86_JBE, offset);                   /* jbe out */
 494
 495         /*
 496          * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
 497          *      goto out;
 498          */
 499         EMIT2_off32(0x8B, 0x85, tcc_off);         /* mov eax, dword ptr [rbp - tcc_off] */
 500         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);     /* cmp eax, MAX_TAIL_CALL_CNT */
 501
 502         offset = ctx->tail_call_indirect_label - (prog + 2 - start);
 503         EMIT2(X86_JAE, offset);                   /* jae out */
 504         EMIT3(0x83, 0xC0, 0x01);                  /* add eax, 1 */
 505         EMIT2_off32(0x89, 0x85, tcc_off);         /* mov dword ptr [rbp - tcc_off], eax */
 506
 507         /* prog = array->ptrs[index]; */
 508         EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6,       /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */
 509                     offsetof(struct bpf_array, ptrs));
 510
 511         /*
 512          * if (prog == NULL)
 513          *      goto out;
 514          */
 515         EMIT3(0x48, 0x85, 0xC9);                  /* test rcx,rcx */
 516
 517         offset = ctx->tail_call_indirect_label - (prog + 2 - start);
 518         EMIT2(X86_JE, offset);                    /* je out */
 519
 520         pop_callee_regs(&prog, callee_regs_used);
 521
 522         EMIT1(0x58);                              /* pop rax */
 523         if (stack_depth)
 524                 EMIT3_off32(0x48, 0x81, 0xC4,     /* add rsp, sd */
 525                             round_up(stack_depth, 8));
 526
 527         /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */
 528         EMIT4(0x48, 0x8B, 0x49,                   /* mov rcx, qword ptr [rcx + 32] */
 529               offsetof(struct bpf_prog, bpf_func));
 530         EMIT4(0x48, 0x83, 0xC1,                   /* add rcx, X86_TAIL_CALL_OFFSET */
 531               X86_TAIL_CALL_OFFSET);
 532         /*
 533          * Now we're ready to jump into next BPF program
 534          * rdi == ctx (1st arg)
 535          * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET
 536          */
 537         emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start));
 538
 539         /* out: */
 540         ctx->tail_call_indirect_label = prog - start;
 541         *pprog = prog;
 542 }
 543
 544 static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke,
 545                                       u8 **pprog, u8 *ip,
 546                                       bool *callee_regs_used, u32 stack_depth,
 547                                       struct jit_context *ctx)
 548 {
 549         int tcc_off = -4 - round_up(stack_depth, 8);
 550         u8 *prog = *pprog, *start = *pprog;
 551         int offset;
 552
 553         /*
 554          * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
 555          *      goto out;
 556          */
 557         EMIT2_off32(0x8B, 0x85, tcc_off);             /* mov eax, dword ptr [rbp - tcc_off] */
 558         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);         /* cmp eax, MAX_TAIL_CALL_CNT */
 559
 560         offset = ctx->tail_call_direct_label - (prog + 2 - start);
 561         EMIT2(X86_JAE, offset);                       /* jae out */
 562         EMIT3(0x83, 0xC0, 0x01);                      /* add eax, 1 */
 563         EMIT2_off32(0x89, 0x85, tcc_off);             /* mov dword ptr [rbp - tcc_off], eax */
 564
 565         poke->tailcall_bypass = ip + (prog - start);
 566         poke->adj_off = X86_TAIL_CALL_OFFSET;
 567         poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE;
 568         poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE;
 569
 570         emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE,
 571                   poke->tailcall_bypass);
 572
 573         pop_callee_regs(&prog, callee_regs_used);
 574         EMIT1(0x58);                                  /* pop rax */
 575         if (stack_depth)
 576                 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8));
 577
 578         memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
 579         prog += X86_PATCH_SIZE;
 580
 581         /* out: */
 582         ctx->tail_call_direct_label = prog - start;
 583
 584         *pprog = prog;
 585 }
 586
 587 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog)
 588 {
 589         struct bpf_jit_poke_descriptor *poke;
 590         struct bpf_array *array;
 591         struct bpf_prog *target;
 592         int i, ret;
 593
 594         for (i = 0; i < prog->aux->size_poke_tab; i++) {
 595                 poke = &prog->aux->poke_tab[i];
 596                 if (poke->aux && poke->aux != prog->aux)
 597                         continue;
 598
 599                 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable));
 600
 601                 if (poke->reason != BPF_POKE_REASON_TAIL_CALL)
 602                         continue;
 603
 604                 array = container_of(poke->tail_call.map, struct bpf_array, map);
 605                 mutex_lock(&array->aux->poke_mutex);
 606                 target = array->ptrs[poke->tail_call.key];
 607                 if (target) {
 608                         ret = __bpf_arch_text_poke(poke->tailcall_target,
 609                                                    BPF_MOD_JUMP, NULL,
 610                                                    (u8 *)target->bpf_func +
 611                                                    poke->adj_off);
 612                         BUG_ON(ret < 0);
 613                         ret = __bpf_arch_text_poke(poke->tailcall_bypass,
 614                                                    BPF_MOD_JUMP,
 615                                                    (u8 *)poke->tailcall_target +
 616                                                    X86_PATCH_SIZE, NULL);
 617                         BUG_ON(ret < 0);
 618                 }
 619                 WRITE_ONCE(poke->tailcall_target_stable, true);
 620                 mutex_unlock(&array->aux->poke_mutex);
 621         }
 622 }
 623
 624 static void emit_mov_imm32(u8 **pprog, bool sign_propagate,
 625                            u32 dst_reg, const u32 imm32)
 626 {
 627         u8 *prog = *pprog;
 628         u8 b1, b2, b3;
 629
 630         /*
 631          * Optimization: if imm32 is positive, use 'mov %eax, imm32'
 632          * (which zero-extends imm32) to save 2 bytes.
 633          */
 634         if (sign_propagate && (s32)imm32 < 0) {
 635                 /* 'mov %rax, imm32' sign extends imm32 */
 636                 b1 = add_1mod(0x48, dst_reg);
 637                 b2 = 0xC7;
 638                 b3 = 0xC0;
 639                 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
 640                 goto done;
 641         }
 642
 643         /*
 644          * Optimization: if imm32 is zero, use 'xor %eax, %eax'
 645          * to save 3 bytes.
 646          */
 647         if (imm32 == 0) {
 648                 if (is_ereg(dst_reg))
 649                         EMIT1(add_2mod(0x40, dst_reg, dst_reg));
 650                 b2 = 0x31; /* xor */
 651                 b3 = 0xC0;
 652                 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
 653                 goto done;
 654         }
 655
 656         /* mov %eax, imm32 */
 657         if (is_ereg(dst_reg))
 658                 EMIT1(add_1mod(0x40, dst_reg));
 659         EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
 660 done:
 661         *pprog = prog;
 662 }
 663
 664 static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
 665                            const u32 imm32_hi, const u32 imm32_lo)
 666 {
 667         u8 *prog = *pprog;
 668
 669         if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
 670                 /*
 671                  * For emitting plain u32, where sign bit must not be
 672                  * propagated LLVM tends to load imm64 over mov32
 673                  * directly, so save couple of bytes by just doing
 674                  * 'mov %eax, imm32' instead.
 675                  */
 676                 emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
 677         } else {
 678                 /* movabsq rax, imm64 */
 679                 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
 680                 EMIT(imm32_lo, 4);
 681                 EMIT(imm32_hi, 4);
 682         }
 683
 684         *pprog = prog;
 685 }
 686
 687 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg)
 688 {
 689         u8 *prog = *pprog;
 690
 691         if (is64) {
 692                 /* mov dst, src */
 693                 EMIT_mov(dst_reg, src_reg);
 694         } else {
 695                 /* mov32 dst, src */
 696                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 697                         EMIT1(add_2mod(0x40, dst_reg, src_reg));
 698                 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
 699         }
 700
 701         *pprog = prog;
 702 }
 703
 704 static void emit_movsx_reg(u8 **pprog, int num_bits, bool is64, u32 dst_reg,
 705                            u32 src_reg)
 706 {
 707         u8 *prog = *pprog;
 708
 709         if (is64) {
 710                 /* movs[b,w,l]q dst, src */
 711                 if (num_bits == 8)
 712                         EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbe,
 713                               add_2reg(0xC0, src_reg, dst_reg));
 714                 else if (num_bits == 16)
 715                         EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbf,
 716                               add_2reg(0xC0, src_reg, dst_reg));
 717                 else if (num_bits == 32)
 718                         EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x63,
 719                               add_2reg(0xC0, src_reg, dst_reg));
 720         } else {
 721                 /* movs[b,w]l dst, src */
 722                 if (num_bits == 8) {
 723                         EMIT4(add_2mod(0x40, src_reg, dst_reg), 0x0f, 0xbe,
 724                               add_2reg(0xC0, src_reg, dst_reg));
 725                 } else if (num_bits == 16) {
 726                         if (is_ereg(dst_reg) || is_ereg(src_reg))
 727                                 EMIT1(add_2mod(0x40, src_reg, dst_reg));
 728                         EMIT3(add_2mod(0x0f, src_reg, dst_reg), 0xbf,
 729                               add_2reg(0xC0, src_reg, dst_reg));
 730                 }
 731         }
 732
 733         *pprog = prog;
 734 }
 735
 736 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */
 737 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off)
 738 {
 739         u8 *prog = *pprog;
 740
 741         if (is_imm8(off)) {
 742                 /* 1-byte signed displacement.
 743                  *
 744                  * If off == 0 we could skip this and save one extra byte, but
 745                  * special case of x86 R13 which always needs an offset is not
 746                  * worth the hassle
 747                  */
 748                 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off);
 749         } else {
 750                 /* 4-byte signed displacement */
 751                 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off);
 752         }
 753         *pprog = prog;
 754 }
 755
 756 /*
 757  * Emit a REX byte if it will be necessary to address these registers
 758  */
 759 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64)
 760 {
 761         u8 *prog = *pprog;
 762
 763         if (is64)
 764                 EMIT1(add_2mod(0x48, dst_reg, src_reg));
 765         else if (is_ereg(dst_reg) || is_ereg(src_reg))
 766                 EMIT1(add_2mod(0x40, dst_reg, src_reg));
 767         *pprog = prog;
 768 }
 769
 770 /*
 771  * Similar version of maybe_emit_mod() for a single register
 772  */
 773 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64)
 774 {
 775         u8 *prog = *pprog;
 776
 777         if (is64)
 778                 EMIT1(add_1mod(0x48, reg));
 779         else if (is_ereg(reg))
 780                 EMIT1(add_1mod(0x40, reg));
 781         *pprog = prog;
 782 }
 783
 784 /* LDX: dst_reg = *(u8*)(src_reg + off) */
 785 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 786 {
 787         u8 *prog = *pprog;
 788
 789         switch (size) {
 790         case BPF_B:
 791                 /* Emit 'movzx rax, byte ptr [rax + off]' */
 792                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
 793                 break;
 794         case BPF_H:
 795                 /* Emit 'movzx rax, word ptr [rax + off]' */
 796                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
 797                 break;
 798         case BPF_W:
 799                 /* Emit 'mov eax, dword ptr [rax+0x14]' */
 800                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 801                         EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
 802                 else
 803                         EMIT1(0x8B);
 804                 break;
 805         case BPF_DW:
 806                 /* Emit 'mov rax, qword ptr [rax+0x14]' */
 807                 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
 808                 break;
 809         }
 810         emit_insn_suffix(&prog, src_reg, dst_reg, off);
 811         *pprog = prog;
 812 }
 813
 814 /* LDSX: dst_reg = *(s8*)(src_reg + off) */
 815 static void emit_ldsx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 816 {
 817         u8 *prog = *pprog;
 818
 819         switch (size) {
 820         case BPF_B:
 821                 /* Emit 'movsx rax, byte ptr [rax + off]' */
 822                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBE);
 823                 break;
 824         case BPF_H:
 825                 /* Emit 'movsx rax, word ptr [rax + off]' */
 826                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBF);
 827                 break;
 828         case BPF_W:
 829                 /* Emit 'movsx rax, dword ptr [rax+0x14]' */
 830                 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x63);
 831                 break;
 832         }
 833         emit_insn_suffix(&prog, src_reg, dst_reg, off);
 834         *pprog = prog;
 835 }
 836
 837 /* STX: *(u8*)(dst_reg + off) = src_reg */
 838 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 839 {
 840         u8 *prog = *pprog;
 841
 842         switch (size) {
 843         case BPF_B:
 844                 /* Emit 'mov byte ptr [rax + off], al' */
 845                 if (is_ereg(dst_reg) || is_ereg_8l(src_reg))
 846                         /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */
 847                         EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
 848                 else
 849                         EMIT1(0x88);
 850                 break;
 851         case BPF_H:
 852                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 853                         EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
 854                 else
 855                         EMIT2(0x66, 0x89);
 856                 break;
 857         case BPF_W:
 858                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 859                         EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
 860                 else
 861                         EMIT1(0x89);
 862                 break;
 863         case BPF_DW:
 864                 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
 865                 break;
 866         }
 867         emit_insn_suffix(&prog, dst_reg, src_reg, off);
 868         *pprog = prog;
 869 }
 870
 871 static int emit_atomic(u8 **pprog, u8 atomic_op,
 872                        u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size)
 873 {
 874         u8 *prog = *pprog;
 875
 876         EMIT1(0xF0); /* lock prefix */
 877
 878         maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW);
 879
 880         /* emit opcode */
 881         switch (atomic_op) {
 882         case BPF_ADD:
 883         case BPF_AND:
 884         case BPF_OR:
 885         case BPF_XOR:
 886                 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */
 887                 EMIT1(simple_alu_opcodes[atomic_op]);
 888                 break;
 889         case BPF_ADD | BPF_FETCH:
 890                 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */
 891                 EMIT2(0x0F, 0xC1);
 892                 break;
 893         case BPF_XCHG:
 894                 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */
 895                 EMIT1(0x87);
 896                 break;
 897         case BPF_CMPXCHG:
 898                 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */
 899                 EMIT2(0x0F, 0xB1);
 900                 break;
 901         default:
 902                 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op);
 903                 return -EFAULT;
 904         }
 905
 906         emit_insn_suffix(&prog, dst_reg, src_reg, off);
 907
 908         *pprog = prog;
 909         return 0;
 910 }
 911
 912 bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs)
 913 {
 914         u32 reg = x->fixup >> 8;
 915
 916         /* jump over faulting load and clear dest register */
 917         *(unsigned long *)((void *)regs + reg) = 0;
 918         regs->ip += x->fixup & 0xff;
 919         return true;
 920 }
 921
 922 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt,
 923                              bool *regs_used, bool *tail_call_seen)
 924 {
 925         int i;
 926
 927         for (i = 1; i <= insn_cnt; i++, insn++) {
 928                 if (insn->code == (BPF_JMP | BPF_TAIL_CALL))
 929                         *tail_call_seen = true;
 930                 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6)
 931                         regs_used[0] = true;
 932                 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7)
 933                         regs_used[1] = true;
 934                 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8)
 935                         regs_used[2] = true;
 936                 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9)
 937                         regs_used[3] = true;
 938         }
 939 }
 940
 941 static void emit_nops(u8 **pprog, int len)
 942 {
 943         u8 *prog = *pprog;
 944         int i, noplen;
 945
 946         while (len > 0) {
 947                 noplen = len;
 948
 949                 if (noplen > ASM_NOP_MAX)
 950                         noplen = ASM_NOP_MAX;
 951
 952                 for (i = 0; i < noplen; i++)
 953                         EMIT1(x86_nops[noplen][i]);
 954                 len -= noplen;
 955         }
 956
 957         *pprog = prog;
 958 }
 959
 960 /* emit the 3-byte VEX prefix
 961  *
 962  * r: same as rex.r, extra bit for ModRM reg field
 963  * x: same as rex.x, extra bit for SIB index field
 964  * b: same as rex.b, extra bit for ModRM r/m, or SIB base
 965  * m: opcode map select, encoding escape bytes e.g. 0x0f38
 966  * w: same as rex.w (32 bit or 64 bit) or opcode specific
 967  * src_reg2: additional source reg (encoded as BPF reg)
 968  * l: vector length (128 bit or 256 bit) or reserved
 969  * pp: opcode prefix (none, 0x66, 0xf2 or 0xf3)
 970  */
 971 static void emit_3vex(u8 **pprog, bool r, bool x, bool b, u8 m,
 972                       bool w, u8 src_reg2, bool l, u8 pp)
 973 {
 974         u8 *prog = *pprog;
 975         const u8 b0 = 0xc4; /* first byte of 3-byte VEX prefix */
 976         u8 b1, b2;
 977         u8 vvvv = reg2hex[src_reg2];
 978
 979         /* reg2hex gives only the lower 3 bit of vvvv */
 980         if (is_ereg(src_reg2))
 981                 vvvv |= 1 << 3;
 982
 983         /*
 984          * 2nd byte of 3-byte VEX prefix
 985          * ~ means bit inverted encoding
 986          *
 987          *    7                           0
 988          *  +---+---+---+---+---+---+---+---+
 989          *  |~R |~X |~B |         m         |
 990          *  +---+---+---+---+---+---+---+---+
 991          */
 992         b1 = (!r << 7) | (!x << 6) | (!b << 5) | (m & 0x1f);
 993         /*
 994          * 3rd byte of 3-byte VEX prefix
 995          *
 996          *    7                           0
 997          *  +---+---+---+---+---+---+---+---+
 998          *  | W |     ~vvvv     | L |   pp  |
 999          *  +---+---+---+---+---+---+---+---+
1000          */
1001         b2 = (w << 7) | ((~vvvv & 0xf) << 3) | (l << 2) | (pp & 3);
1002
1003         EMIT3(b0, b1, b2);
1004         *pprog = prog;
1005 }
1006
1007 /* emit BMI2 shift instruction */
1008 static void emit_shiftx(u8 **pprog, u32 dst_reg, u8 src_reg, bool is64, u8 op)
1009 {
1010         u8 *prog = *pprog;
1011         bool r = is_ereg(dst_reg);
1012         u8 m = 2; /* escape code 0f38 */
1013
1014         emit_3vex(&prog, r, false, r, m, is64, src_reg, false, op);
1015         EMIT2(0xf7, add_2reg(0xC0, dst_reg, dst_reg));
1016         *pprog = prog;
1017 }
1018
1019 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp)))
1020
1021 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image,
1022                   int oldproglen, struct jit_context *ctx, bool jmp_padding)
1023 {
1024         bool tail_call_reachable = bpf_prog->aux->tail_call_reachable;
1025         struct bpf_insn *insn = bpf_prog->insnsi;
1026         bool callee_regs_used[4] = {};
1027         int insn_cnt = bpf_prog->len;
1028         bool tail_call_seen = false;
1029         bool seen_exit = false;
1030         u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
1031         int i, excnt = 0;
1032         int ilen, proglen = 0;
1033         u8 *prog = temp;
1034         int err;
1035
1036         detect_reg_usage(insn, insn_cnt, callee_regs_used,
1037                          &tail_call_seen);
1038
1039         /* tail call's presence in current prog implies it is reachable */
1040         tail_call_reachable |= tail_call_seen;
1041
1042         emit_prologue(&prog, bpf_prog->aux->stack_depth,
1043                       bpf_prog_was_classic(bpf_prog), tail_call_reachable,
1044                       bpf_prog->aux->func_idx != 0);
1045         push_callee_regs(&prog, callee_regs_used);
1046
1047         ilen = prog - temp;
1048         if (rw_image)
1049                 memcpy(rw_image + proglen, temp, ilen);
1050         proglen += ilen;
1051         addrs[0] = proglen;
1052         prog = temp;
1053
1054         for (i = 1; i <= insn_cnt; i++, insn++) {
1055                 const s32 imm32 = insn->imm;
1056                 u32 dst_reg = insn->dst_reg;
1057                 u32 src_reg = insn->src_reg;
1058                 u8 b2 = 0, b3 = 0;
1059                 u8 *start_of_ldx;
1060                 s64 jmp_offset;
1061                 s16 insn_off;
1062                 u8 jmp_cond;
1063                 u8 *func;
1064                 int nops;
1065
1066                 switch (insn->code) {
1067                         /* ALU */
1068                 case BPF_ALU | BPF_ADD | BPF_X:
1069                 case BPF_ALU | BPF_SUB | BPF_X:
1070                 case BPF_ALU | BPF_AND | BPF_X:
1071                 case BPF_ALU | BPF_OR | BPF_X:
1072                 case BPF_ALU | BPF_XOR | BPF_X:
1073                 case BPF_ALU64 | BPF_ADD | BPF_X:
1074                 case BPF_ALU64 | BPF_SUB | BPF_X:
1075                 case BPF_ALU64 | BPF_AND | BPF_X:
1076                 case BPF_ALU64 | BPF_OR | BPF_X:
1077                 case BPF_ALU64 | BPF_XOR | BPF_X:
1078                         maybe_emit_mod(&prog, dst_reg, src_reg,
1079                                        BPF_CLASS(insn->code) == BPF_ALU64);
1080                         b2 = simple_alu_opcodes[BPF_OP(insn->code)];
1081                         EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
1082                         break;
1083
1084                 case BPF_ALU64 | BPF_MOV | BPF_X:
1085                 case BPF_ALU | BPF_MOV | BPF_X:
1086                         if (insn->off == 0)
1087                                 emit_mov_reg(&prog,
1088                                              BPF_CLASS(insn->code) == BPF_ALU64,
1089                                              dst_reg, src_reg);
1090                         else
1091                                 emit_movsx_reg(&prog, insn->off,
1092                                                BPF_CLASS(insn->code) == BPF_ALU64,
1093                                                dst_reg, src_reg);
1094                         break;
1095
1096                         /* neg dst */
1097                 case BPF_ALU | BPF_NEG:
1098                 case BPF_ALU64 | BPF_NEG:
1099                         maybe_emit_1mod(&prog, dst_reg,
1100                                         BPF_CLASS(insn->code) == BPF_ALU64);
1101                         EMIT2(0xF7, add_1reg(0xD8, dst_reg));
1102                         break;
1103
1104                 case BPF_ALU | BPF_ADD | BPF_K:
1105                 case BPF_ALU | BPF_SUB | BPF_K:
1106                 case BPF_ALU | BPF_AND | BPF_K:
1107                 case BPF_ALU | BPF_OR | BPF_K:
1108                 case BPF_ALU | BPF_XOR | BPF_K:
1109                 case BPF_ALU64 | BPF_ADD | BPF_K:
1110                 case BPF_ALU64 | BPF_SUB | BPF_K:
1111                 case BPF_ALU64 | BPF_AND | BPF_K:
1112                 case BPF_ALU64 | BPF_OR | BPF_K:
1113                 case BPF_ALU64 | BPF_XOR | BPF_K:
1114                         maybe_emit_1mod(&prog, dst_reg,
1115                                         BPF_CLASS(insn->code) == BPF_ALU64);
1116
1117                         /*
1118                          * b3 holds 'normal' opcode, b2 short form only valid
1119                          * in case dst is eax/rax.
1120                          */
1121                         switch (BPF_OP(insn->code)) {
1122                         case BPF_ADD:
1123                                 b3 = 0xC0;
1124                                 b2 = 0x05;
1125                                 break;
1126                         case BPF_SUB:
1127                                 b3 = 0xE8;
1128                                 b2 = 0x2D;
1129                                 break;
1130                         case BPF_AND:
1131                                 b3 = 0xE0;
1132                                 b2 = 0x25;
1133                                 break;
1134                         case BPF_OR:
1135                                 b3 = 0xC8;
1136                                 b2 = 0x0D;
1137                                 break;
1138                         case BPF_XOR:
1139                                 b3 = 0xF0;
1140                                 b2 = 0x35;
1141                                 break;
1142                         }
1143
1144                         if (is_imm8(imm32))
1145                                 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
1146                         else if (is_axreg(dst_reg))
1147                                 EMIT1_off32(b2, imm32);
1148                         else
1149                                 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1150                         break;
1151
1152                 case BPF_ALU64 | BPF_MOV | BPF_K:
1153                 case BPF_ALU | BPF_MOV | BPF_K:
1154                         emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64,
1155                                        dst_reg, imm32);
1156                         break;
1157
1158                 case BPF_LD | BPF_IMM | BPF_DW:
1159                         emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm);
1160                         insn++;
1161                         i++;
1162                         break;
1163
1164                         /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
1165                 case BPF_ALU | BPF_MOD | BPF_X:
1166                 case BPF_ALU | BPF_DIV | BPF_X:
1167                 case BPF_ALU | BPF_MOD | BPF_K:
1168                 case BPF_ALU | BPF_DIV | BPF_K:
1169                 case BPF_ALU64 | BPF_MOD | BPF_X:
1170                 case BPF_ALU64 | BPF_DIV | BPF_X:
1171                 case BPF_ALU64 | BPF_MOD | BPF_K:
1172                 case BPF_ALU64 | BPF_DIV | BPF_K: {
1173                         bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1174
1175                         if (dst_reg != BPF_REG_0)
1176                                 EMIT1(0x50); /* push rax */
1177                         if (dst_reg != BPF_REG_3)
1178                                 EMIT1(0x52); /* push rdx */
1179
1180                         if (BPF_SRC(insn->code) == BPF_X) {
1181                                 if (src_reg == BPF_REG_0 ||
1182                                     src_reg == BPF_REG_3) {
1183                                         /* mov r11, src_reg */
1184                                         EMIT_mov(AUX_REG, src_reg);
1185                                         src_reg = AUX_REG;
1186                                 }
1187                         } else {
1188                                 /* mov r11, imm32 */
1189                                 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
1190                                 src_reg = AUX_REG;
1191                         }
1192
1193                         if (dst_reg != BPF_REG_0)
1194                                 /* mov rax, dst_reg */
1195                                 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg);
1196
1197                         /*
1198                          * xor edx, edx
1199                          * equivalent to 'xor rdx, rdx', but one byte less
1200                          */
1201                         EMIT2(0x31, 0xd2);
1202
1203                         /* div src_reg */
1204                         maybe_emit_1mod(&prog, src_reg, is64);
1205                         EMIT2(0xF7, add_1reg(0xF0, src_reg));
1206
1207                         if (BPF_OP(insn->code) == BPF_MOD &&
1208                             dst_reg != BPF_REG_3)
1209                                 /* mov dst_reg, rdx */
1210                                 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3);
1211                         else if (BPF_OP(insn->code) == BPF_DIV &&
1212                                  dst_reg != BPF_REG_0)
1213                                 /* mov dst_reg, rax */
1214                                 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0);
1215
1216                         if (dst_reg != BPF_REG_3)
1217                                 EMIT1(0x5A); /* pop rdx */
1218                         if (dst_reg != BPF_REG_0)
1219                                 EMIT1(0x58); /* pop rax */
1220                         break;
1221                 }
1222
1223                 case BPF_ALU | BPF_MUL | BPF_K:
1224                 case BPF_ALU64 | BPF_MUL | BPF_K:
1225                         maybe_emit_mod(&prog, dst_reg, dst_reg,
1226                                        BPF_CLASS(insn->code) == BPF_ALU64);
1227
1228                         if (is_imm8(imm32))
1229                                 /* imul dst_reg, dst_reg, imm8 */
1230                                 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg),
1231                                       imm32);
1232                         else
1233                                 /* imul dst_reg, dst_reg, imm32 */
1234                                 EMIT2_off32(0x69,
1235                                             add_2reg(0xC0, dst_reg, dst_reg),
1236                                             imm32);
1237                         break;
1238
1239                 case BPF_ALU | BPF_MUL | BPF_X:
1240                 case BPF_ALU64 | BPF_MUL | BPF_X:
1241                         maybe_emit_mod(&prog, src_reg, dst_reg,
1242                                        BPF_CLASS(insn->code) == BPF_ALU64);
1243
1244                         /* imul dst_reg, src_reg */
1245                         EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg));
1246                         break;
1247
1248                         /* Shifts */
1249                 case BPF_ALU | BPF_LSH | BPF_K:
1250                 case BPF_ALU | BPF_RSH | BPF_K:
1251                 case BPF_ALU | BPF_ARSH | BPF_K:
1252                 case BPF_ALU64 | BPF_LSH | BPF_K:
1253                 case BPF_ALU64 | BPF_RSH | BPF_K:
1254                 case BPF_ALU64 | BPF_ARSH | BPF_K:
1255                         maybe_emit_1mod(&prog, dst_reg,
1256                                         BPF_CLASS(insn->code) == BPF_ALU64);
1257
1258                         b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1259                         if (imm32 == 1)
1260                                 EMIT2(0xD1, add_1reg(b3, dst_reg));
1261                         else
1262                                 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1263                         break;
1264
1265                 case BPF_ALU | BPF_LSH | BPF_X:
1266                 case BPF_ALU | BPF_RSH | BPF_X:
1267                 case BPF_ALU | BPF_ARSH | BPF_X:
1268                 case BPF_ALU64 | BPF_LSH | BPF_X:
1269                 case BPF_ALU64 | BPF_RSH | BPF_X:
1270                 case BPF_ALU64 | BPF_ARSH | BPF_X:
1271                         /* BMI2 shifts aren't better when shift count is already in rcx */
1272                         if (boot_cpu_has(X86_FEATURE_BMI2) && src_reg != BPF_REG_4) {
1273                                 /* shrx/sarx/shlx dst_reg, dst_reg, src_reg */
1274                                 bool w = (BPF_CLASS(insn->code) == BPF_ALU64);
1275                                 u8 op;
1276
1277                                 switch (BPF_OP(insn->code)) {
1278                                 case BPF_LSH:
1279                                         op = 1; /* prefix 0x66 */
1280                                         break;
1281                                 case BPF_RSH:
1282                                         op = 3; /* prefix 0xf2 */
1283                                         break;
1284                                 case BPF_ARSH:
1285                                         op = 2; /* prefix 0xf3 */
1286                                         break;
1287                                 }
1288
1289                                 emit_shiftx(&prog, dst_reg, src_reg, w, op);
1290
1291                                 break;
1292                         }
1293
1294                         if (src_reg != BPF_REG_4) { /* common case */
1295                                 /* Check for bad case when dst_reg == rcx */
1296                                 if (dst_reg == BPF_REG_4) {
1297                                         /* mov r11, dst_reg */
1298                                         EMIT_mov(AUX_REG, dst_reg);
1299                                         dst_reg = AUX_REG;
1300                                 } else {
1301                                         EMIT1(0x51); /* push rcx */
1302                                 }
1303                                 /* mov rcx, src_reg */
1304                                 EMIT_mov(BPF_REG_4, src_reg);
1305                         }
1306
1307                         /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
1308                         maybe_emit_1mod(&prog, dst_reg,
1309                                         BPF_CLASS(insn->code) == BPF_ALU64);
1310
1311                         b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1312                         EMIT2(0xD3, add_1reg(b3, dst_reg));
1313
1314                         if (src_reg != BPF_REG_4) {
1315                                 if (insn->dst_reg == BPF_REG_4)
1316                                         /* mov dst_reg, r11 */
1317                                         EMIT_mov(insn->dst_reg, AUX_REG);
1318                                 else
1319                                         EMIT1(0x59); /* pop rcx */
1320                         }
1321
1322                         break;
1323
1324                 case BPF_ALU | BPF_END | BPF_FROM_BE:
1325                         switch (imm32) {
1326                         case 16:
1327                                 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
1328                                 EMIT1(0x66);
1329                                 if (is_ereg(dst_reg))
1330                                         EMIT1(0x41);
1331                                 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
1332
1333                                 /* Emit 'movzwl eax, ax' */
1334                                 if (is_ereg(dst_reg))
1335                                         EMIT3(0x45, 0x0F, 0xB7);
1336                                 else
1337                                         EMIT2(0x0F, 0xB7);
1338                                 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1339                                 break;
1340                         case 32:
1341                                 /* Emit 'bswap eax' to swap lower 4 bytes */
1342                                 if (is_ereg(dst_reg))
1343                                         EMIT2(0x41, 0x0F);
1344                                 else
1345                                         EMIT1(0x0F);
1346                                 EMIT1(add_1reg(0xC8, dst_reg));
1347                                 break;
1348                         case 64:
1349                                 /* Emit 'bswap rax' to swap 8 bytes */
1350                                 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
1351                                       add_1reg(0xC8, dst_reg));
1352                                 break;
1353                         }
1354                         break;
1355
1356                 case BPF_ALU | BPF_END | BPF_FROM_LE:
1357                         switch (imm32) {
1358                         case 16:
1359                                 /*
1360                                  * Emit 'movzwl eax, ax' to zero extend 16-bit
1361                                  * into 64 bit
1362                                  */
1363                                 if (is_ereg(dst_reg))
1364                                         EMIT3(0x45, 0x0F, 0xB7);
1365                                 else
1366                                         EMIT2(0x0F, 0xB7);
1367                                 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1368                                 break;
1369                         case 32:
1370                                 /* Emit 'mov eax, eax' to clear upper 32-bits */
1371                                 if (is_ereg(dst_reg))
1372                                         EMIT1(0x45);
1373                                 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
1374                                 break;
1375                         case 64:
1376                                 /* nop */
1377                                 break;
1378                         }
1379                         break;
1380
1381                         /* speculation barrier */
1382                 case BPF_ST | BPF_NOSPEC:
1383                         EMIT_LFENCE();
1384                         break;
1385
1386                         /* ST: *(u8*)(dst_reg + off) = imm */
1387                 case BPF_ST | BPF_MEM | BPF_B:
1388                         if (is_ereg(dst_reg))
1389                                 EMIT2(0x41, 0xC6);
1390                         else
1391                                 EMIT1(0xC6);
1392                         goto st;
1393                 case BPF_ST | BPF_MEM | BPF_H:
1394                         if (is_ereg(dst_reg))
1395                                 EMIT3(0x66, 0x41, 0xC7);
1396                         else
1397                                 EMIT2(0x66, 0xC7);
1398                         goto st;
1399                 case BPF_ST | BPF_MEM | BPF_W:
1400                         if (is_ereg(dst_reg))
1401                                 EMIT2(0x41, 0xC7);
1402                         else
1403                                 EMIT1(0xC7);
1404                         goto st;
1405                 case BPF_ST | BPF_MEM | BPF_DW:
1406                         EMIT2(add_1mod(0x48, dst_reg), 0xC7);
1407
1408 st:                     if (is_imm8(insn->off))
1409                                 EMIT2(add_1reg(0x40, dst_reg), insn->off);
1410                         else
1411                                 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
1412
1413                         EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
1414                         break;
1415
1416                         /* STX: *(u8*)(dst_reg + off) = src_reg */
1417                 case BPF_STX | BPF_MEM | BPF_B:
1418                 case BPF_STX | BPF_MEM | BPF_H:
1419                 case BPF_STX | BPF_MEM | BPF_W:
1420                 case BPF_STX | BPF_MEM | BPF_DW:
1421                         emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1422                         break;
1423
1424                         /* LDX: dst_reg = *(u8*)(src_reg + off) */
1425                 case BPF_LDX | BPF_MEM | BPF_B:
1426                 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1427                 case BPF_LDX | BPF_MEM | BPF_H:
1428                 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1429                 case BPF_LDX | BPF_MEM | BPF_W:
1430                 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1431                 case BPF_LDX | BPF_MEM | BPF_DW:
1432                 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1433                         /* LDXS: dst_reg = *(s8*)(src_reg + off) */
1434                 case BPF_LDX | BPF_MEMSX | BPF_B:
1435                 case BPF_LDX | BPF_MEMSX | BPF_H:
1436                 case BPF_LDX | BPF_MEMSX | BPF_W:
1437                 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B:
1438                 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H:
1439                 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W:
1440                         insn_off = insn->off;
1441
1442                         if (BPF_MODE(insn->code) == BPF_PROBE_MEM ||
1443                             BPF_MODE(insn->code) == BPF_PROBE_MEMSX) {
1444                                 /* Conservatively check that src_reg + insn->off is a kernel address:
1445                                  *   src_reg + insn->off >= TASK_SIZE_MAX + PAGE_SIZE
1446                                  * src_reg is used as scratch for src_reg += insn->off and restored
1447                                  * after emit_ldx if necessary
1448                                  */
1449
1450                                 u64 limit = TASK_SIZE_MAX + PAGE_SIZE;
1451                                 u8 *end_of_jmp;
1452
1453                                 /* At end of these emitted checks, insn->off will have been added
1454                                  * to src_reg, so no need to do relative load with insn->off offset
1455                                  */
1456                                 insn_off = 0;
1457
1458                                 /* movabsq r11, limit */
1459                                 EMIT2(add_1mod(0x48, AUX_REG), add_1reg(0xB8, AUX_REG));
1460                                 EMIT((u32)limit, 4);
1461                                 EMIT(limit >> 32, 4);
1462
1463                                 if (insn->off) {
1464                                         /* add src_reg, insn->off */
1465                                         maybe_emit_1mod(&prog, src_reg, true);
1466                                         EMIT2_off32(0x81, add_1reg(0xC0, src_reg), insn->off);
1467                                 }
1468
1469                                 /* cmp src_reg, r11 */
1470                                 maybe_emit_mod(&prog, src_reg, AUX_REG, true);
1471                                 EMIT2(0x39, add_2reg(0xC0, src_reg, AUX_REG));
1472
1473                                 /* if unsigned '>=', goto load */
1474                                 EMIT2(X86_JAE, 0);
1475                                 end_of_jmp = prog;
1476
1477                                 /* xor dst_reg, dst_reg */
1478                                 emit_mov_imm32(&prog, false, dst_reg, 0);
1479                                 /* jmp byte_after_ldx */
1480                                 EMIT2(0xEB, 0);
1481
1482                                 /* populate jmp_offset for JAE above to jump to start_of_ldx */
1483                                 start_of_ldx = prog;
1484                                 end_of_jmp[-1] = start_of_ldx - end_of_jmp;
1485                         }
1486                         if (BPF_MODE(insn->code) == BPF_PROBE_MEMSX ||
1487                             BPF_MODE(insn->code) == BPF_MEMSX)
1488                                 emit_ldsx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off);
1489                         else
1490                                 emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off);
1491                         if (BPF_MODE(insn->code) == BPF_PROBE_MEM ||
1492                             BPF_MODE(insn->code) == BPF_PROBE_MEMSX) {
1493                                 struct exception_table_entry *ex;
1494                                 u8 *_insn = image + proglen + (start_of_ldx - temp);
1495                                 s64 delta;
1496
1497                                 /* populate jmp_offset for JMP above */
1498                                 start_of_ldx[-1] = prog - start_of_ldx;
1499
1500                                 if (insn->off && src_reg != dst_reg) {
1501                                         /* sub src_reg, insn->off
1502                                          * Restore src_reg after "add src_reg, insn->off" in prev
1503                                          * if statement. But if src_reg == dst_reg, emit_ldx
1504                                          * above already clobbered src_reg, so no need to restore.
1505                                          * If add src_reg, insn->off was unnecessary, no need to
1506                                          * restore either.
1507                                          */
1508                                         maybe_emit_1mod(&prog, src_reg, true);
1509                                         EMIT2_off32(0x81, add_1reg(0xE8, src_reg), insn->off);
1510                                 }
1511
1512                                 if (!bpf_prog->aux->extable)
1513                                         break;
1514
1515                                 if (excnt >= bpf_prog->aux->num_exentries) {
1516                                         pr_err("ex gen bug\n");
1517                                         return -EFAULT;
1518                                 }
1519                                 ex = &bpf_prog->aux->extable[excnt++];
1520
1521                                 delta = _insn - (u8 *)&ex->insn;
1522                                 if (!is_simm32(delta)) {
1523                                         pr_err("extable->insn doesn't fit into 32-bit\n");
1524                                         return -EFAULT;
1525                                 }
1526                                 /* switch ex to rw buffer for writes */
1527                                 ex = (void *)rw_image + ((void *)ex - (void *)image);
1528
1529                                 ex->insn = delta;
1530
1531                                 ex->data = EX_TYPE_BPF;
1532
1533                                 if (dst_reg > BPF_REG_9) {
1534                                         pr_err("verifier error\n");
1535                                         return -EFAULT;
1536                                 }
1537                                 /*
1538                                  * Compute size of x86 insn and its target dest x86 register.
1539                                  * ex_handler_bpf() will use lower 8 bits to adjust
1540                                  * pt_regs->ip to jump over this x86 instruction
1541                                  * and upper bits to figure out which pt_regs to zero out.
1542                                  * End result: x86 insn "mov rbx, qword ptr [rax+0x14]"
1543                                  * of 4 bytes will be ignored and rbx will be zero inited.
1544                                  */
1545                                 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8);
1546                         }
1547                         break;
1548
1549                 case BPF_STX | BPF_ATOMIC | BPF_W:
1550                 case BPF_STX | BPF_ATOMIC | BPF_DW:
1551                         if (insn->imm == (BPF_AND | BPF_FETCH) ||
1552                             insn->imm == (BPF_OR | BPF_FETCH) ||
1553                             insn->imm == (BPF_XOR | BPF_FETCH)) {
1554                                 bool is64 = BPF_SIZE(insn->code) == BPF_DW;
1555                                 u32 real_src_reg = src_reg;
1556                                 u32 real_dst_reg = dst_reg;
1557                                 u8 *branch_target;
1558
1559                                 /*
1560                                  * Can't be implemented with a single x86 insn.
1561                                  * Need to do a CMPXCHG loop.
1562                                  */
1563
1564                                 /* Will need RAX as a CMPXCHG operand so save R0 */
1565                                 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0);
1566                                 if (src_reg == BPF_REG_0)
1567                                         real_src_reg = BPF_REG_AX;
1568                                 if (dst_reg == BPF_REG_0)
1569                                         real_dst_reg = BPF_REG_AX;
1570
1571                                 branch_target = prog;
1572                                 /* Load old value */
1573                                 emit_ldx(&prog, BPF_SIZE(insn->code),
1574                                          BPF_REG_0, real_dst_reg, insn->off);
1575                                 /*
1576                                  * Perform the (commutative) operation locally,
1577                                  * put the result in the AUX_REG.
1578                                  */
1579                                 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0);
1580                                 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64);
1581                                 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)],
1582                                       add_2reg(0xC0, AUX_REG, real_src_reg));
1583                                 /* Attempt to swap in new value */
1584                                 err = emit_atomic(&prog, BPF_CMPXCHG,
1585                                                   real_dst_reg, AUX_REG,
1586                                                   insn->off,
1587                                                   BPF_SIZE(insn->code));
1588                                 if (WARN_ON(err))
1589                                         return err;
1590                                 /*
1591                                  * ZF tells us whether we won the race. If it's
1592                                  * cleared we need to try again.
1593                                  */
1594                                 EMIT2(X86_JNE, -(prog - branch_target) - 2);
1595                                 /* Return the pre-modification value */
1596                                 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0);
1597                                 /* Restore R0 after clobbering RAX */
1598                                 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX);
1599                                 break;
1600                         }
1601
1602                         err = emit_atomic(&prog, insn->imm, dst_reg, src_reg,
1603                                           insn->off, BPF_SIZE(insn->code));
1604                         if (err)
1605                                 return err;
1606                         break;
1607
1608                         /* call */
1609                 case BPF_JMP | BPF_CALL: {
1610                         int offs;
1611
1612                         func = (u8 *) __bpf_call_base + imm32;
1613                         if (tail_call_reachable) {
1614                                 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */
1615                                 EMIT3_off32(0x48, 0x8B, 0x85,
1616                                             -round_up(bpf_prog->aux->stack_depth, 8) - 8);
1617                                 if (!imm32)
1618                                         return -EINVAL;
1619                                 offs = 7 + x86_call_depth_emit_accounting(&prog, func);
1620                         } else {
1621                                 if (!imm32)
1622                                         return -EINVAL;
1623                                 offs = x86_call_depth_emit_accounting(&prog, func);
1624                         }
1625                         if (emit_call(&prog, func, image + addrs[i - 1] + offs))
1626                                 return -EINVAL;
1627                         break;
1628                 }
1629
1630                 case BPF_JMP | BPF_TAIL_CALL:
1631                         if (imm32)
1632                                 emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1],
1633                                                           &prog, image + addrs[i - 1],
1634                                                           callee_regs_used,
1635                                                           bpf_prog->aux->stack_depth,
1636                                                           ctx);
1637                         else
1638                                 emit_bpf_tail_call_indirect(&prog,
1639                                                             callee_regs_used,
1640                                                             bpf_prog->aux->stack_depth,
1641                                                             image + addrs[i - 1],
1642                                                             ctx);
1643                         break;
1644
1645                         /* cond jump */
1646                 case BPF_JMP | BPF_JEQ | BPF_X:
1647                 case BPF_JMP | BPF_JNE | BPF_X:
1648                 case BPF_JMP | BPF_JGT | BPF_X:
1649                 case BPF_JMP | BPF_JLT | BPF_X:
1650                 case BPF_JMP | BPF_JGE | BPF_X:
1651                 case BPF_JMP | BPF_JLE | BPF_X:
1652                 case BPF_JMP | BPF_JSGT | BPF_X:
1653                 case BPF_JMP | BPF_JSLT | BPF_X:
1654                 case BPF_JMP | BPF_JSGE | BPF_X:
1655                 case BPF_JMP | BPF_JSLE | BPF_X:
1656                 case BPF_JMP32 | BPF_JEQ | BPF_X:
1657                 case BPF_JMP32 | BPF_JNE | BPF_X:
1658                 case BPF_JMP32 | BPF_JGT | BPF_X:
1659                 case BPF_JMP32 | BPF_JLT | BPF_X:
1660                 case BPF_JMP32 | BPF_JGE | BPF_X:
1661                 case BPF_JMP32 | BPF_JLE | BPF_X:
1662                 case BPF_JMP32 | BPF_JSGT | BPF_X:
1663                 case BPF_JMP32 | BPF_JSLT | BPF_X:
1664                 case BPF_JMP32 | BPF_JSGE | BPF_X:
1665                 case BPF_JMP32 | BPF_JSLE | BPF_X:
1666                         /* cmp dst_reg, src_reg */
1667                         maybe_emit_mod(&prog, dst_reg, src_reg,
1668                                        BPF_CLASS(insn->code) == BPF_JMP);
1669                         EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg));
1670                         goto emit_cond_jmp;
1671
1672                 case BPF_JMP | BPF_JSET | BPF_X:
1673                 case BPF_JMP32 | BPF_JSET | BPF_X:
1674                         /* test dst_reg, src_reg */
1675                         maybe_emit_mod(&prog, dst_reg, src_reg,
1676                                        BPF_CLASS(insn->code) == BPF_JMP);
1677                         EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg));
1678                         goto emit_cond_jmp;
1679
1680                 case BPF_JMP | BPF_JSET | BPF_K:
1681                 case BPF_JMP32 | BPF_JSET | BPF_K:
1682                         /* test dst_reg, imm32 */
1683                         maybe_emit_1mod(&prog, dst_reg,
1684                                         BPF_CLASS(insn->code) == BPF_JMP);
1685                         EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
1686                         goto emit_cond_jmp;
1687
1688                 case BPF_JMP | BPF_JEQ | BPF_K:
1689                 case BPF_JMP | BPF_JNE | BPF_K:
1690                 case BPF_JMP | BPF_JGT | BPF_K:
1691                 case BPF_JMP | BPF_JLT | BPF_K:
1692                 case BPF_JMP | BPF_JGE | BPF_K:
1693                 case BPF_JMP | BPF_JLE | BPF_K:
1694                 case BPF_JMP | BPF_JSGT | BPF_K:
1695                 case BPF_JMP | BPF_JSLT | BPF_K:
1696                 case BPF_JMP | BPF_JSGE | BPF_K:
1697                 case BPF_JMP | BPF_JSLE | BPF_K:
1698                 case BPF_JMP32 | BPF_JEQ | BPF_K:
1699                 case BPF_JMP32 | BPF_JNE | BPF_K:
1700                 case BPF_JMP32 | BPF_JGT | BPF_K:
1701                 case BPF_JMP32 | BPF_JLT | BPF_K:
1702                 case BPF_JMP32 | BPF_JGE | BPF_K:
1703                 case BPF_JMP32 | BPF_JLE | BPF_K:
1704                 case BPF_JMP32 | BPF_JSGT | BPF_K:
1705                 case BPF_JMP32 | BPF_JSLT | BPF_K:
1706                 case BPF_JMP32 | BPF_JSGE | BPF_K:
1707                 case BPF_JMP32 | BPF_JSLE | BPF_K:
1708                         /* test dst_reg, dst_reg to save one extra byte */
1709                         if (imm32 == 0) {
1710                                 maybe_emit_mod(&prog, dst_reg, dst_reg,
1711                                                BPF_CLASS(insn->code) == BPF_JMP);
1712                                 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
1713                                 goto emit_cond_jmp;
1714                         }
1715
1716                         /* cmp dst_reg, imm8/32 */
1717                         maybe_emit_1mod(&prog, dst_reg,
1718                                         BPF_CLASS(insn->code) == BPF_JMP);
1719
1720                         if (is_imm8(imm32))
1721                                 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
1722                         else
1723                                 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
1724
1725 emit_cond_jmp:          /* Convert BPF opcode to x86 */
1726                         switch (BPF_OP(insn->code)) {
1727                         case BPF_JEQ:
1728                                 jmp_cond = X86_JE;
1729                                 break;
1730                         case BPF_JSET:
1731                         case BPF_JNE:
1732                                 jmp_cond = X86_JNE;
1733                                 break;
1734                         case BPF_JGT:
1735                                 /* GT is unsigned '>', JA in x86 */
1736                                 jmp_cond = X86_JA;
1737                                 break;
1738                         case BPF_JLT:
1739                                 /* LT is unsigned '<', JB in x86 */
1740                                 jmp_cond = X86_JB;
1741                                 break;
1742                         case BPF_JGE:
1743                                 /* GE is unsigned '>=', JAE in x86 */
1744                                 jmp_cond = X86_JAE;
1745                                 break;
1746                         case BPF_JLE:
1747                                 /* LE is unsigned '<=', JBE in x86 */
1748                                 jmp_cond = X86_JBE;
1749                                 break;
1750                         case BPF_JSGT:
1751                                 /* Signed '>', GT in x86 */
1752                                 jmp_cond = X86_JG;
1753                                 break;
1754                         case BPF_JSLT:
1755                                 /* Signed '<', LT in x86 */
1756                                 jmp_cond = X86_JL;
1757                                 break;
1758                         case BPF_JSGE:
1759                                 /* Signed '>=', GE in x86 */
1760                                 jmp_cond = X86_JGE;
1761                                 break;
1762                         case BPF_JSLE:
1763                                 /* Signed '<=', LE in x86 */
1764                                 jmp_cond = X86_JLE;
1765                                 break;
1766                         default: /* to silence GCC warning */
1767                                 return -EFAULT;
1768                         }
1769                         jmp_offset = addrs[i + insn->off] - addrs[i];
1770                         if (is_imm8(jmp_offset)) {
1771                                 if (jmp_padding) {
1772                                         /* To keep the jmp_offset valid, the extra bytes are
1773                                          * padded before the jump insn, so we subtract the
1774                                          * 2 bytes of jmp_cond insn from INSN_SZ_DIFF.
1775                                          *
1776                                          * If the previous pass already emits an imm8
1777                                          * jmp_cond, then this BPF insn won't shrink, so
1778                                          * "nops" is 0.
1779                                          *
1780                                          * On the other hand, if the previous pass emits an
1781                                          * imm32 jmp_cond, the extra 4 bytes(*) is padded to
1782                                          * keep the image from shrinking further.
1783                                          *
1784                                          * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond
1785                                          *     is 2 bytes, so the size difference is 4 bytes.
1786                                          */
1787                                         nops = INSN_SZ_DIFF - 2;
1788                                         if (nops != 0 && nops != 4) {
1789                                                 pr_err("unexpected jmp_cond padding: %d bytes\n",
1790                                                        nops);
1791                                                 return -EFAULT;
1792                                         }
1793                                         emit_nops(&prog, nops);
1794                                 }
1795                                 EMIT2(jmp_cond, jmp_offset);
1796                         } else if (is_simm32(jmp_offset)) {
1797                                 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
1798                         } else {
1799                                 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
1800                                 return -EFAULT;
1801                         }
1802
1803                         break;
1804
1805                 case BPF_JMP | BPF_JA:
1806                         if (insn->off == -1)
1807                                 /* -1 jmp instructions will always jump
1808                                  * backwards two bytes. Explicitly handling
1809                                  * this case avoids wasting too many passes
1810                                  * when there are long sequences of replaced
1811                                  * dead code.
1812                                  */
1813                                 jmp_offset = -2;
1814                         else
1815                                 jmp_offset = addrs[i + insn->off] - addrs[i];
1816
1817                         if (!jmp_offset) {
1818                                 /*
1819                                  * If jmp_padding is enabled, the extra nops will
1820                                  * be inserted. Otherwise, optimize out nop jumps.
1821                                  */
1822                                 if (jmp_padding) {
1823                                         /* There are 3 possible conditions.
1824                                          * (1) This BPF_JA is already optimized out in
1825                                          *     the previous run, so there is no need
1826                                          *     to pad any extra byte (0 byte).
1827                                          * (2) The previous pass emits an imm8 jmp,
1828                                          *     so we pad 2 bytes to match the previous
1829                                          *     insn size.
1830                                          * (3) Similarly, the previous pass emits an
1831                                          *     imm32 jmp, and 5 bytes is padded.
1832                                          */
1833                                         nops = INSN_SZ_DIFF;
1834                                         if (nops != 0 && nops != 2 && nops != 5) {
1835                                                 pr_err("unexpected nop jump padding: %d bytes\n",
1836                                                        nops);
1837                                                 return -EFAULT;
1838                                         }
1839                                         emit_nops(&prog, nops);
1840                                 }
1841                                 break;
1842                         }
1843 emit_jmp:
1844                         if (is_imm8(jmp_offset)) {
1845                                 if (jmp_padding) {
1846                                         /* To avoid breaking jmp_offset, the extra bytes
1847                                          * are padded before the actual jmp insn, so
1848                                          * 2 bytes is subtracted from INSN_SZ_DIFF.
1849                                          *
1850                                          * If the previous pass already emits an imm8
1851                                          * jmp, there is nothing to pad (0 byte).
1852                                          *
1853                                          * If it emits an imm32 jmp (5 bytes) previously
1854                                          * and now an imm8 jmp (2 bytes), then we pad
1855                                          * (5 - 2 = 3) bytes to stop the image from
1856                                          * shrinking further.
1857                                          */
1858                                         nops = INSN_SZ_DIFF - 2;
1859                                         if (nops != 0 && nops != 3) {
1860                                                 pr_err("unexpected jump padding: %d bytes\n",
1861                                                        nops);
1862                                                 return -EFAULT;
1863                                         }
1864                                         emit_nops(&prog, INSN_SZ_DIFF - 2);
1865                                 }
1866                                 EMIT2(0xEB, jmp_offset);
1867                         } else if (is_simm32(jmp_offset)) {
1868                                 EMIT1_off32(0xE9, jmp_offset);
1869                         } else {
1870                                 pr_err("jmp gen bug %llx\n", jmp_offset);
1871                                 return -EFAULT;
1872                         }
1873                         break;
1874
1875                 case BPF_JMP | BPF_EXIT:
1876                         if (seen_exit) {
1877                                 jmp_offset = ctx->cleanup_addr - addrs[i];
1878                                 goto emit_jmp;
1879                         }
1880                         seen_exit = true;
1881                         /* Update cleanup_addr */
1882                         ctx->cleanup_addr = proglen;
1883                         pop_callee_regs(&prog, callee_regs_used);
1884                         EMIT1(0xC9);         /* leave */
1885                         emit_return(&prog, image + addrs[i - 1] + (prog - temp));
1886                         break;
1887
1888                 default:
1889                         /*
1890                          * By design x86-64 JIT should support all BPF instructions.
1891                          * This error will be seen if new instruction was added
1892                          * to the interpreter, but not to the JIT, or if there is
1893                          * junk in bpf_prog.
1894                          */
1895                         pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
1896                         return -EINVAL;
1897                 }
1898
1899                 ilen = prog - temp;
1900                 if (ilen > BPF_MAX_INSN_SIZE) {
1901                         pr_err("bpf_jit: fatal insn size error\n");
1902                         return -EFAULT;
1903                 }
1904
1905                 if (image) {
1906                         /*
1907                          * When populating the image, assert that:
1908                          *
1909                          *  i) We do not write beyond the allocated space, and
1910                          * ii) addrs[i] did not change from the prior run, in order
1911                          *     to validate assumptions made for computing branch
1912                          *     displacements.
1913                          */
1914                         if (unlikely(proglen + ilen > oldproglen ||
1915                                      proglen + ilen != addrs[i])) {
1916                                 pr_err("bpf_jit: fatal error\n");
1917                                 return -EFAULT;
1918                         }
1919                         memcpy(rw_image + proglen, temp, ilen);
1920                 }
1921                 proglen += ilen;
1922                 addrs[i] = proglen;
1923                 prog = temp;
1924         }
1925
1926         if (image && excnt != bpf_prog->aux->num_exentries) {
1927                 pr_err("extable is not populated\n");
1928                 return -EFAULT;
1929         }
1930         return proglen;
1931 }
1932
1933 static void clean_stack_garbage(const struct btf_func_model *m,
1934                                 u8 **pprog, int nr_stack_slots,
1935                                 int stack_size)
1936 {
1937         int arg_size, off;
1938         u8 *prog;
1939
1940         /* Generally speaking, the compiler will pass the arguments
1941          * on-stack with "push" instruction, which will take 8-byte
1942          * on the stack. In this case, there won't be garbage values
1943          * while we copy the arguments from origin stack frame to current
1944          * in BPF_DW.
1945          *
1946          * However, sometimes the compiler will only allocate 4-byte on
1947          * the stack for the arguments. For now, this case will only
1948          * happen if there is only one argument on-stack and its size
1949          * not more than 4 byte. In this case, there will be garbage
1950          * values on the upper 4-byte where we store the argument on
1951          * current stack frame.
1952          *
1953          * arguments on origin stack:
1954          *
1955          * stack_arg_1(4-byte) xxx(4-byte)
1956          *
1957          * what we copy:
1958          *
1959          * stack_arg_1(8-byte): stack_arg_1(origin) xxx
1960          *
1961          * and the xxx is the garbage values which we should clean here.
1962          */
1963         if (nr_stack_slots != 1)
1964                 return;
1965
1966         /* the size of the last argument */
1967         arg_size = m->arg_size[m->nr_args - 1];
1968         if (arg_size <= 4) {
1969                 off = -(stack_size - 4);
1970                 prog = *pprog;
1971                 /* mov DWORD PTR [rbp + off], 0 */
1972                 if (!is_imm8(off))
1973                         EMIT2_off32(0xC7, 0x85, off);
1974                 else
1975                         EMIT3(0xC7, 0x45, off);
1976                 EMIT(0, 4);
1977                 *pprog = prog;
1978         }
1979 }
1980
1981 /* get the count of the regs that are used to pass arguments */
1982 static int get_nr_used_regs(const struct btf_func_model *m)
1983 {
1984         int i, arg_regs, nr_used_regs = 0;
1985
1986         for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) {
1987                 arg_regs = (m->arg_size[i] + 7) / 8;
1988                 if (nr_used_regs + arg_regs <= 6)
1989                         nr_used_regs += arg_regs;
1990
1991                 if (nr_used_regs >= 6)
1992                         break;
1993         }
1994
1995         return nr_used_regs;
1996 }
1997
1998 static void save_args(const struct btf_func_model *m, u8 **prog,
1999                       int stack_size, bool for_call_origin)
2000 {
2001         int arg_regs, first_off = 0, nr_regs = 0, nr_stack_slots = 0;
2002         int i, j;
2003
2004         /* Store function arguments to stack.
2005          * For a function that accepts two pointers the sequence will be:
2006          * mov QWORD PTR [rbp-0x10],rdi
2007          * mov QWORD PTR [rbp-0x8],rsi
2008          */
2009         for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) {
2010                 arg_regs = (m->arg_size[i] + 7) / 8;
2011
2012                 /* According to the research of Yonghong, struct members
2013                  * should be all in register or all on the stack.
2014                  * Meanwhile, the compiler will pass the argument on regs
2015                  * if the remaining regs can hold the argument.
2016                  *
2017                  * Disorder of the args can happen. For example:
2018                  *
2019                  * struct foo_struct {
2020                  *     long a;
2021                  *     int b;
2022                  * };
2023                  * int foo(char, char, char, char, char, struct foo_struct,
2024                  *         char);
2025                  *
2026                  * the arg1-5,arg7 will be passed by regs, and arg6 will
2027                  * by stack.
2028                  */
2029                 if (nr_regs + arg_regs > 6) {
2030                         /* copy function arguments from origin stack frame
2031                          * into current stack frame.
2032                          *
2033                          * The starting address of the arguments on-stack
2034                          * is:
2035                          *   rbp + 8(push rbp) +
2036                          *   8(return addr of origin call) +
2037                          *   8(return addr of the caller)
2038                          * which means: rbp + 24
2039                          */
2040                         for (j = 0; j < arg_regs; j++) {
2041                                 emit_ldx(prog, BPF_DW, BPF_REG_0, BPF_REG_FP,
2042                                          nr_stack_slots * 8 + 0x18);
2043                                 emit_stx(prog, BPF_DW, BPF_REG_FP, BPF_REG_0,
2044                                          -stack_size);
2045
2046                                 if (!nr_stack_slots)
2047                                         first_off = stack_size;
2048                                 stack_size -= 8;
2049                                 nr_stack_slots++;
2050                         }
2051                 } else {
2052                         /* Only copy the arguments on-stack to current
2053                          * 'stack_size' and ignore the regs, used to
2054                          * prepare the arguments on-stack for orign call.
2055                          */
2056                         if (for_call_origin) {
2057                                 nr_regs += arg_regs;
2058                                 continue;
2059                         }
2060
2061                         /* copy the arguments from regs into stack */
2062                         for (j = 0; j < arg_regs; j++) {
2063                                 emit_stx(prog, BPF_DW, BPF_REG_FP,
2064                                          nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs,
2065                                          -stack_size);
2066                                 stack_size -= 8;
2067                                 nr_regs++;
2068                         }
2069                 }
2070         }
2071
2072         clean_stack_garbage(m, prog, nr_stack_slots, first_off);
2073 }
2074
2075 static void restore_regs(const struct btf_func_model *m, u8 **prog,
2076                          int stack_size)
2077 {
2078         int i, j, arg_regs, nr_regs = 0;
2079
2080         /* Restore function arguments from stack.
2081          * For a function that accepts two pointers the sequence will be:
2082          * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10]
2083          * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8]
2084          *
2085          * The logic here is similar to what we do in save_args()
2086          */
2087         for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) {
2088                 arg_regs = (m->arg_size[i] + 7) / 8;
2089                 if (nr_regs + arg_regs <= 6) {
2090                         for (j = 0; j < arg_regs; j++) {
2091                                 emit_ldx(prog, BPF_DW,
2092                                          nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs,
2093                                          BPF_REG_FP,
2094                                          -stack_size);
2095                                 stack_size -= 8;
2096                                 nr_regs++;
2097                         }
2098                 } else {
2099                         stack_size -= 8 * arg_regs;
2100                 }
2101
2102                 if (nr_regs >= 6)
2103                         break;
2104         }
2105 }
2106
2107 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog,
2108                            struct bpf_tramp_link *l, int stack_size,
2109                            int run_ctx_off, bool save_ret)
2110 {
2111         u8 *prog = *pprog;
2112         u8 *jmp_insn;
2113         int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie);
2114         struct bpf_prog *p = l->link.prog;
2115         u64 cookie = l->cookie;
2116
2117         /* mov rdi, cookie */
2118         emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie);
2119
2120         /* Prepare struct bpf_tramp_run_ctx.
2121          *
2122          * bpf_tramp_run_ctx is already preserved by
2123          * arch_prepare_bpf_trampoline().
2124          *
2125          * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi
2126          */
2127         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off);
2128
2129         /* arg1: mov rdi, progs[i] */
2130         emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
2131         /* arg2: lea rsi, [rbp - ctx_cookie_off] */
2132         if (!is_imm8(-run_ctx_off))
2133                 EMIT3_off32(0x48, 0x8D, 0xB5, -run_ctx_off);
2134         else
2135                 EMIT4(0x48, 0x8D, 0x75, -run_ctx_off);
2136
2137         if (emit_rsb_call(&prog, bpf_trampoline_enter(p), prog))
2138                 return -EINVAL;
2139         /* remember prog start time returned by __bpf_prog_enter */
2140         emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0);
2141
2142         /* if (__bpf_prog_enter*(prog) == 0)
2143          *      goto skip_exec_of_prog;
2144          */
2145         EMIT3(0x48, 0x85, 0xC0);  /* test rax,rax */
2146         /* emit 2 nops that will be replaced with JE insn */
2147         jmp_insn = prog;
2148         emit_nops(&prog, 2);
2149
2150         /* arg1: lea rdi, [rbp - stack_size] */
2151         if (!is_imm8(-stack_size))
2152                 EMIT3_off32(0x48, 0x8D, 0xBD, -stack_size);
2153         else
2154                 EMIT4(0x48, 0x8D, 0x7D, -stack_size);
2155         /* arg2: progs[i]->insnsi for interpreter */
2156         if (!p->jited)
2157                 emit_mov_imm64(&prog, BPF_REG_2,
2158                                (long) p->insnsi >> 32,
2159                                (u32) (long) p->insnsi);
2160         /* call JITed bpf program or interpreter */
2161         if (emit_rsb_call(&prog, p->bpf_func, prog))
2162                 return -EINVAL;
2163
2164         /*
2165          * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return
2166          * of the previous call which is then passed on the stack to
2167          * the next BPF program.
2168          *
2169          * BPF_TRAMP_FENTRY trampoline may need to return the return
2170          * value of BPF_PROG_TYPE_STRUCT_OPS prog.
2171          */
2172         if (save_ret)
2173                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2174
2175         /* replace 2 nops with JE insn, since jmp target is known */
2176         jmp_insn[0] = X86_JE;
2177         jmp_insn[1] = prog - jmp_insn - 2;
2178
2179         /* arg1: mov rdi, progs[i] */
2180         emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
2181         /* arg2: mov rsi, rbx <- start time in nsec */
2182         emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6);
2183         /* arg3: lea rdx, [rbp - run_ctx_off] */
2184         if (!is_imm8(-run_ctx_off))
2185                 EMIT3_off32(0x48, 0x8D, 0x95, -run_ctx_off);
2186         else
2187                 EMIT4(0x48, 0x8D, 0x55, -run_ctx_off);
2188         if (emit_rsb_call(&prog, bpf_trampoline_exit(p), prog))
2189                 return -EINVAL;
2190
2191         *pprog = prog;
2192         return 0;
2193 }
2194
2195 static void emit_align(u8 **pprog, u32 align)
2196 {
2197         u8 *target, *prog = *pprog;
2198
2199         target = PTR_ALIGN(prog, align);
2200         if (target != prog)
2201                 emit_nops(&prog, target - prog);
2202
2203         *pprog = prog;
2204 }
2205
2206 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond)
2207 {
2208         u8 *prog = *pprog;
2209         s64 offset;
2210
2211         offset = func - (ip + 2 + 4);
2212         if (!is_simm32(offset)) {
2213                 pr_err("Target %p is out of range\n", func);
2214                 return -EINVAL;
2215         }
2216         EMIT2_off32(0x0F, jmp_cond + 0x10, offset);
2217         *pprog = prog;
2218         return 0;
2219 }
2220
2221 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog,
2222                       struct bpf_tramp_links *tl, int stack_size,
2223                       int run_ctx_off, bool save_ret)
2224 {
2225         int i;
2226         u8 *prog = *pprog;
2227
2228         for (i = 0; i < tl->nr_links; i++) {
2229                 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size,
2230                                     run_ctx_off, save_ret))
2231                         return -EINVAL;
2232         }
2233         *pprog = prog;
2234         return 0;
2235 }
2236
2237 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog,
2238                               struct bpf_tramp_links *tl, int stack_size,
2239                               int run_ctx_off, u8 **branches)
2240 {
2241         u8 *prog = *pprog;
2242         int i;
2243
2244         /* The first fmod_ret program will receive a garbage return value.
2245          * Set this to 0 to avoid confusing the program.
2246          */
2247         emit_mov_imm32(&prog, false, BPF_REG_0, 0);
2248         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2249         for (i = 0; i < tl->nr_links; i++) {
2250                 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true))
2251                         return -EINVAL;
2252
2253                 /* mod_ret prog stored return value into [rbp - 8]. Emit:
2254                  * if (*(u64 *)(rbp - 8) !=  0)
2255                  *      goto do_fexit;
2256                  */
2257                 /* cmp QWORD PTR [rbp - 0x8], 0x0 */
2258                 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00);
2259
2260                 /* Save the location of the branch and Generate 6 nops
2261                  * (4 bytes for an offset and 2 bytes for the jump) These nops
2262                  * are replaced with a conditional jump once do_fexit (i.e. the
2263                  * start of the fexit invocation) is finalized.
2264                  */
2265                 branches[i] = prog;
2266                 emit_nops(&prog, 4 + 2);
2267         }
2268
2269         *pprog = prog;
2270         return 0;
2271 }
2272
2273 /* Example:
2274  * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev);
2275  * its 'struct btf_func_model' will be nr_args=2
2276  * The assembly code when eth_type_trans is executing after trampoline:
2277  *
2278  * push rbp
2279  * mov rbp, rsp
2280  * sub rsp, 16                     // space for skb and dev
2281  * push rbx                        // temp regs to pass start time
2282  * mov qword ptr [rbp - 16], rdi   // save skb pointer to stack
2283  * mov qword ptr [rbp - 8], rsi    // save dev pointer to stack
2284  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
2285  * mov rbx, rax                    // remember start time in bpf stats are enabled
2286  * lea rdi, [rbp - 16]             // R1==ctx of bpf prog
2287  * call addr_of_jited_FENTRY_prog
2288  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
2289  * mov rsi, rbx                    // prog start time
2290  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
2291  * mov rdi, qword ptr [rbp - 16]   // restore skb pointer from stack
2292  * mov rsi, qword ptr [rbp - 8]    // restore dev pointer from stack
2293  * pop rbx
2294  * leave
2295  * ret
2296  *
2297  * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be
2298  * replaced with 'call generated_bpf_trampoline'. When it returns
2299  * eth_type_trans will continue executing with original skb and dev pointers.
2300  *
2301  * The assembly code when eth_type_trans is called from trampoline:
2302  *
2303  * push rbp
2304  * mov rbp, rsp
2305  * sub rsp, 24                     // space for skb, dev, return value
2306  * push rbx                        // temp regs to pass start time
2307  * mov qword ptr [rbp - 24], rdi   // save skb pointer to stack
2308  * mov qword ptr [rbp - 16], rsi   // save dev pointer to stack
2309  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
2310  * mov rbx, rax                    // remember start time if bpf stats are enabled
2311  * lea rdi, [rbp - 24]             // R1==ctx of bpf prog
2312  * call addr_of_jited_FENTRY_prog  // bpf prog can access skb and dev
2313  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
2314  * mov rsi, rbx                    // prog start time
2315  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
2316  * mov rdi, qword ptr [rbp - 24]   // restore skb pointer from stack
2317  * mov rsi, qword ptr [rbp - 16]   // restore dev pointer from stack
2318  * call eth_type_trans+5           // execute body of eth_type_trans
2319  * mov qword ptr [rbp - 8], rax    // save return value
2320  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
2321  * mov rbx, rax                    // remember start time in bpf stats are enabled
2322  * lea rdi, [rbp - 24]             // R1==ctx of bpf prog
2323  * call addr_of_jited_FEXIT_prog   // bpf prog can access skb, dev, return value
2324  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
2325  * mov rsi, rbx                    // prog start time
2326  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
2327  * mov rax, qword ptr [rbp - 8]    // restore eth_type_trans's return value
2328  * pop rbx
2329  * leave
2330  * add rsp, 8                      // skip eth_type_trans's frame
2331  * ret                             // return to its caller
2332  */
2333 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end,
2334                                 const struct btf_func_model *m, u32 flags,
2335                                 struct bpf_tramp_links *tlinks,
2336                                 void *func_addr)
2337 {
2338         int i, ret, nr_regs = m->nr_args, stack_size = 0;
2339         int regs_off, nregs_off, ip_off, run_ctx_off, arg_stack_off, rbx_off;
2340         struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY];
2341         struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT];
2342         struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN];
2343         void *orig_call = func_addr;
2344         u8 **branches = NULL;
2345         u8 *prog;
2346         bool save_ret;
2347
2348         /* extra registers for struct arguments */
2349         for (i = 0; i < m->nr_args; i++)
2350                 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG)
2351                         nr_regs += (m->arg_size[i] + 7) / 8 - 1;
2352
2353         /* x86-64 supports up to MAX_BPF_FUNC_ARGS arguments. 1-6
2354          * are passed through regs, the remains are through stack.
2355          */
2356         if (nr_regs > MAX_BPF_FUNC_ARGS)
2357                 return -ENOTSUPP;
2358
2359         /* Generated trampoline stack layout:
2360          *
2361          * RBP + 8         [ return address  ]
2362          * RBP + 0         [ RBP             ]
2363          *
2364          * RBP - 8         [ return value    ]  BPF_TRAMP_F_CALL_ORIG or
2365          *                                      BPF_TRAMP_F_RET_FENTRY_RET flags
2366          *
2367          *                 [ reg_argN        ]  always
2368          *                 [ ...             ]
2369          * RBP - regs_off  [ reg_arg1        ]  program's ctx pointer
2370          *
2371          * RBP - nregs_off [ regs count      ]  always
2372          *
2373          * RBP - ip_off    [ traced function ]  BPF_TRAMP_F_IP_ARG flag
2374          *
2375          * RBP - rbx_off   [ rbx value       ]  always
2376          *
2377          * RBP - run_ctx_off [ bpf_tramp_run_ctx ]
2378          *
2379          *                     [ stack_argN ]  BPF_TRAMP_F_CALL_ORIG
2380          *                     [ ...        ]
2381          *                     [ stack_arg2 ]
2382          * RBP - arg_stack_off [ stack_arg1 ]
2383          */
2384
2385         /* room for return value of orig_call or fentry prog */
2386         save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET);
2387         if (save_ret)
2388                 stack_size += 8;
2389
2390         stack_size += nr_regs * 8;
2391         regs_off = stack_size;
2392
2393         /* regs count  */
2394         stack_size += 8;
2395         nregs_off = stack_size;
2396
2397         if (flags & BPF_TRAMP_F_IP_ARG)
2398                 stack_size += 8; /* room for IP address argument */
2399
2400         ip_off = stack_size;
2401
2402         stack_size += 8;
2403         rbx_off = stack_size;
2404
2405         stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7;
2406         run_ctx_off = stack_size;
2407
2408         if (nr_regs > 6 && (flags & BPF_TRAMP_F_CALL_ORIG)) {
2409                 /* the space that used to pass arguments on-stack */
2410                 stack_size += (nr_regs - get_nr_used_regs(m)) * 8;
2411                 /* make sure the stack pointer is 16-byte aligned if we
2412                  * need pass arguments on stack, which means
2413                  *  [stack_size + 8(rbp) + 8(rip) + 8(origin rip)]
2414                  * should be 16-byte aligned. Following code depend on
2415                  * that stack_size is already 8-byte aligned.
2416                  */
2417                 stack_size += (stack_size % 16) ? 0 : 8;
2418         }
2419
2420         arg_stack_off = stack_size;
2421
2422         if (flags & BPF_TRAMP_F_SKIP_FRAME) {
2423                 /* skip patched call instruction and point orig_call to actual
2424                  * body of the kernel function.
2425                  */
2426                 if (is_endbr(*(u32 *)orig_call))
2427                         orig_call += ENDBR_INSN_SIZE;
2428                 orig_call += X86_PATCH_SIZE;
2429         }
2430
2431         prog = image;
2432
2433         EMIT_ENDBR();
2434         /*
2435          * This is the direct-call trampoline, as such it needs accounting
2436          * for the __fentry__ call.
2437          */
2438         x86_call_depth_emit_accounting(&prog, NULL);
2439         EMIT1(0x55);             /* push rbp */
2440         EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
2441         if (!is_imm8(stack_size))
2442                 /* sub rsp, stack_size */
2443                 EMIT3_off32(0x48, 0x81, 0xEC, stack_size);
2444         else
2445                 /* sub rsp, stack_size */
2446                 EMIT4(0x48, 0x83, 0xEC, stack_size);
2447         /* mov QWORD PTR [rbp - rbx_off], rbx */
2448         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_6, -rbx_off);
2449
2450         /* Store number of argument registers of the traced function:
2451          *   mov rax, nr_regs
2452          *   mov QWORD PTR [rbp - nregs_off], rax
2453          */
2454         emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_regs);
2455         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -nregs_off);
2456
2457         if (flags & BPF_TRAMP_F_IP_ARG) {
2458                 /* Store IP address of the traced function:
2459                  * movabsq rax, func_addr
2460                  * mov QWORD PTR [rbp - ip_off], rax
2461                  */
2462                 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr);
2463                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off);
2464         }
2465
2466         save_args(m, &prog, regs_off, false);
2467
2468         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2469                 /* arg1: mov rdi, im */
2470                 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2471                 if (emit_rsb_call(&prog, __bpf_tramp_enter, prog)) {
2472                         ret = -EINVAL;
2473                         goto cleanup;
2474                 }
2475         }
2476
2477         if (fentry->nr_links)
2478                 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off,
2479                                flags & BPF_TRAMP_F_RET_FENTRY_RET))
2480                         return -EINVAL;
2481
2482         if (fmod_ret->nr_links) {
2483                 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *),
2484                                    GFP_KERNEL);
2485                 if (!branches)
2486                         return -ENOMEM;
2487
2488                 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off,
2489                                        run_ctx_off, branches)) {
2490                         ret = -EINVAL;
2491                         goto cleanup;
2492                 }
2493         }
2494
2495         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2496                 restore_regs(m, &prog, regs_off);
2497                 save_args(m, &prog, arg_stack_off, true);
2498
2499                 if (flags & BPF_TRAMP_F_ORIG_STACK) {
2500                         emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 8);
2501                         EMIT2(0xff, 0xd0); /* call *rax */
2502                 } else {
2503                         /* call original function */
2504                         if (emit_rsb_call(&prog, orig_call, prog)) {
2505                                 ret = -EINVAL;
2506                                 goto cleanup;
2507                         }
2508                 }
2509                 /* remember return value in a stack for bpf prog to access */
2510                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2511                 im->ip_after_call = prog;
2512                 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
2513                 prog += X86_PATCH_SIZE;
2514         }
2515
2516         if (fmod_ret->nr_links) {
2517                 /* From Intel 64 and IA-32 Architectures Optimization
2518                  * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2519                  * Coding Rule 11: All branch targets should be 16-byte
2520                  * aligned.
2521                  */
2522                 emit_align(&prog, 16);
2523                 /* Update the branches saved in invoke_bpf_mod_ret with the
2524                  * aligned address of do_fexit.
2525                  */
2526                 for (i = 0; i < fmod_ret->nr_links; i++)
2527                         emit_cond_near_jump(&branches[i], prog, branches[i],
2528                                             X86_JNE);
2529         }
2530
2531         if (fexit->nr_links)
2532                 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off, false)) {
2533                         ret = -EINVAL;
2534                         goto cleanup;
2535                 }
2536
2537         if (flags & BPF_TRAMP_F_RESTORE_REGS)
2538                 restore_regs(m, &prog, regs_off);
2539
2540         /* This needs to be done regardless. If there were fmod_ret programs,
2541          * the return value is only updated on the stack and still needs to be
2542          * restored to R0.
2543          */
2544         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2545                 im->ip_epilogue = prog;
2546                 /* arg1: mov rdi, im */
2547                 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2548                 if (emit_rsb_call(&prog, __bpf_tramp_exit, prog)) {
2549                         ret = -EINVAL;
2550                         goto cleanup;
2551                 }
2552         }
2553         /* restore return value of orig_call or fentry prog back into RAX */
2554         if (save_ret)
2555                 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8);
2556
2557         emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, -rbx_off);
2558         EMIT1(0xC9); /* leave */
2559         if (flags & BPF_TRAMP_F_SKIP_FRAME)
2560                 /* skip our return address and return to parent */
2561                 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */
2562         emit_return(&prog, prog);
2563         /* Make sure the trampoline generation logic doesn't overflow */
2564         if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) {
2565                 ret = -EFAULT;
2566                 goto cleanup;
2567         }
2568         ret = prog - (u8 *)image;
2569
2570 cleanup:
2571         kfree(branches);
2572         return ret;
2573 }
2574
2575 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf)
2576 {
2577         u8 *jg_reloc, *prog = *pprog;
2578         int pivot, err, jg_bytes = 1;
2579         s64 jg_offset;
2580
2581         if (a == b) {
2582                 /* Leaf node of recursion, i.e. not a range of indices
2583                  * anymore.
2584                  */
2585                 EMIT1(add_1mod(0x48, BPF_REG_3));       /* cmp rdx,func */
2586                 if (!is_simm32(progs[a]))
2587                         return -1;
2588                 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
2589                             progs[a]);
2590                 err = emit_cond_near_jump(&prog,        /* je func */
2591                                           (void *)progs[a], image + (prog - buf),
2592                                           X86_JE);
2593                 if (err)
2594                         return err;
2595
2596                 emit_indirect_jump(&prog, 2 /* rdx */, image + (prog - buf));
2597
2598                 *pprog = prog;
2599                 return 0;
2600         }
2601
2602         /* Not a leaf node, so we pivot, and recursively descend into
2603          * the lower and upper ranges.
2604          */
2605         pivot = (b - a) / 2;
2606         EMIT1(add_1mod(0x48, BPF_REG_3));               /* cmp rdx,func */
2607         if (!is_simm32(progs[a + pivot]))
2608                 return -1;
2609         EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
2610
2611         if (pivot > 2) {                                /* jg upper_part */
2612                 /* Require near jump. */
2613                 jg_bytes = 4;
2614                 EMIT2_off32(0x0F, X86_JG + 0x10, 0);
2615         } else {
2616                 EMIT2(X86_JG, 0);
2617         }
2618         jg_reloc = prog;
2619
2620         err = emit_bpf_dispatcher(&prog, a, a + pivot,  /* emit lower_part */
2621                                   progs, image, buf);
2622         if (err)
2623                 return err;
2624
2625         /* From Intel 64 and IA-32 Architectures Optimization
2626          * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2627          * Coding Rule 11: All branch targets should be 16-byte
2628          * aligned.
2629          */
2630         emit_align(&prog, 16);
2631         jg_offset = prog - jg_reloc;
2632         emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes);
2633
2634         err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */
2635                                   b, progs, image, buf);
2636         if (err)
2637                 return err;
2638
2639         *pprog = prog;
2640         return 0;
2641 }
2642
2643 static int cmp_ips(const void *a, const void *b)
2644 {
2645         const s64 *ipa = a;
2646         const s64 *ipb = b;
2647
2648         if (*ipa > *ipb)
2649                 return 1;
2650         if (*ipa < *ipb)
2651                 return -1;
2652         return 0;
2653 }
2654
2655 int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs)
2656 {
2657         u8 *prog = buf;
2658
2659         sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL);
2660         return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf);
2661 }
2662
2663 struct x64_jit_data {
2664         struct bpf_binary_header *rw_header;
2665         struct bpf_binary_header *header;
2666         int *addrs;
2667         u8 *image;
2668         int proglen;
2669         struct jit_context ctx;
2670 };
2671
2672 #define MAX_PASSES 20
2673 #define PADDING_PASSES (MAX_PASSES - 5)
2674
2675 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2676 {
2677         struct bpf_binary_header *rw_header = NULL;
2678         struct bpf_binary_header *header = NULL;
2679         struct bpf_prog *tmp, *orig_prog = prog;
2680         struct x64_jit_data *jit_data;
2681         int proglen, oldproglen = 0;
2682         struct jit_context ctx = {};
2683         bool tmp_blinded = false;
2684         bool extra_pass = false;
2685         bool padding = false;
2686         u8 *rw_image = NULL;
2687         u8 *image = NULL;
2688         int *addrs;
2689         int pass;
2690         int i;
2691
2692         if (!prog->jit_requested)
2693                 return orig_prog;
2694
2695         tmp = bpf_jit_blind_constants(prog);
2696         /*
2697          * If blinding was requested and we failed during blinding,
2698          * we must fall back to the interpreter.
2699          */
2700         if (IS_ERR(tmp))
2701                 return orig_prog;
2702         if (tmp != prog) {
2703                 tmp_blinded = true;
2704                 prog = tmp;
2705         }
2706
2707         jit_data = prog->aux->jit_data;
2708         if (!jit_data) {
2709                 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
2710                 if (!jit_data) {
2711                         prog = orig_prog;
2712                         goto out;
2713                 }
2714                 prog->aux->jit_data = jit_data;
2715         }
2716         addrs = jit_data->addrs;
2717         if (addrs) {
2718                 ctx = jit_data->ctx;
2719                 oldproglen = jit_data->proglen;
2720                 image = jit_data->image;
2721                 header = jit_data->header;
2722                 rw_header = jit_data->rw_header;
2723                 rw_image = (void *)rw_header + ((void *)image - (void *)header);
2724                 extra_pass = true;
2725                 padding = true;
2726                 goto skip_init_addrs;
2727         }
2728         addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL);
2729         if (!addrs) {
2730                 prog = orig_prog;
2731                 goto out_addrs;
2732         }
2733
2734         /*
2735          * Before first pass, make a rough estimation of addrs[]
2736          * each BPF instruction is translated to less than 64 bytes
2737          */
2738         for (proglen = 0, i = 0; i <= prog->len; i++) {
2739                 proglen += 64;
2740                 addrs[i] = proglen;
2741         }
2742         ctx.cleanup_addr = proglen;
2743 skip_init_addrs:
2744
2745         /*
2746          * JITed image shrinks with every pass and the loop iterates
2747          * until the image stops shrinking. Very large BPF programs
2748          * may converge on the last pass. In such case do one more
2749          * pass to emit the final image.
2750          */
2751         for (pass = 0; pass < MAX_PASSES || image; pass++) {
2752                 if (!padding && pass >= PADDING_PASSES)
2753                         padding = true;
2754                 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding);
2755                 if (proglen <= 0) {
2756 out_image:
2757                         image = NULL;
2758                         if (header) {
2759                                 bpf_arch_text_copy(&header->size, &rw_header->size,
2760                                                    sizeof(rw_header->size));
2761                                 bpf_jit_binary_pack_free(header, rw_header);
2762                         }
2763                         /* Fall back to interpreter mode */
2764                         prog = orig_prog;
2765                         if (extra_pass) {
2766                                 prog->bpf_func = NULL;
2767                                 prog->jited = 0;
2768                                 prog->jited_len = 0;
2769                         }
2770                         goto out_addrs;
2771                 }
2772                 if (image) {
2773                         if (proglen != oldproglen) {
2774                                 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2775                                        proglen, oldproglen);
2776                                 goto out_image;
2777                         }
2778                         break;
2779                 }
2780                 if (proglen == oldproglen) {
2781                         /*
2782                          * The number of entries in extable is the number of BPF_LDX
2783                          * insns that access kernel memory via "pointer to BTF type".
2784                          * The verifier changed their opcode from LDX|MEM|size
2785                          * to LDX|PROBE_MEM|size to make JITing easier.
2786                          */
2787                         u32 align = __alignof__(struct exception_table_entry);
2788                         u32 extable_size = prog->aux->num_exentries *
2789                                 sizeof(struct exception_table_entry);
2790
2791                         /* allocate module memory for x86 insns and extable */
2792                         header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size,
2793                                                            &image, align, &rw_header, &rw_image,
2794                                                            jit_fill_hole);
2795                         if (!header) {
2796                                 prog = orig_prog;
2797                                 goto out_addrs;
2798                         }
2799                         prog->aux->extable = (void *) image + roundup(proglen, align);
2800                 }
2801                 oldproglen = proglen;
2802                 cond_resched();
2803         }
2804
2805         if (bpf_jit_enable > 1)
2806                 bpf_jit_dump(prog->len, proglen, pass + 1, rw_image);
2807
2808         if (image) {
2809                 if (!prog->is_func || extra_pass) {
2810                         /*
2811                          * bpf_jit_binary_pack_finalize fails in two scenarios:
2812                          *   1) header is not pointing to proper module memory;
2813                          *   2) the arch doesn't support bpf_arch_text_copy().
2814                          *
2815                          * Both cases are serious bugs and justify WARN_ON.
2816                          */
2817                         if (WARN_ON(bpf_jit_binary_pack_finalize(prog, header, rw_header))) {
2818                                 /* header has been freed */
2819                                 header = NULL;
2820                                 goto out_image;
2821                         }
2822
2823                         bpf_tail_call_direct_fixup(prog);
2824                 } else {
2825                         jit_data->addrs = addrs;
2826                         jit_data->ctx = ctx;
2827                         jit_data->proglen = proglen;
2828                         jit_data->image = image;
2829                         jit_data->header = header;
2830                         jit_data->rw_header = rw_header;
2831                 }
2832                 prog->bpf_func = (void *)image;
2833                 prog->jited = 1;
2834                 prog->jited_len = proglen;
2835         } else {
2836                 prog = orig_prog;
2837         }
2838
2839         if (!image || !prog->is_func || extra_pass) {
2840                 if (image)
2841                         bpf_prog_fill_jited_linfo(prog, addrs + 1);
2842 out_addrs:
2843                 kvfree(addrs);
2844                 kfree(jit_data);
2845                 prog->aux->jit_data = NULL;
2846         }
2847 out:
2848         if (tmp_blinded)
2849                 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2850                                            tmp : orig_prog);
2851         return prog;
2852 }
2853
2854 bool bpf_jit_supports_kfunc_call(void)
2855 {
2856         return true;
2857 }
2858
2859 void *bpf_arch_text_copy(void *dst, void *src, size_t len)
2860 {
2861         if (text_poke_copy(dst, src, len) == NULL)
2862                 return ERR_PTR(-EINVAL);
2863         return dst;
2864 }
2865
2866 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
2867 bool bpf_jit_supports_subprog_tailcalls(void)
2868 {
2869         return true;
2870 }
2871
2872 void bpf_jit_free(struct bpf_prog *prog)
2873 {
2874         if (prog->jited) {
2875                 struct x64_jit_data *jit_data = prog->aux->jit_data;
2876                 struct bpf_binary_header *hdr;
2877
2878                 /*
2879                  * If we fail the final pass of JIT (from jit_subprogs),
2880                  * the program may not be finalized yet. Call finalize here
2881                  * before freeing it.
2882                  */
2883                 if (jit_data) {
2884                         bpf_jit_binary_pack_finalize(prog, jit_data->header,
2885                                                      jit_data->rw_header);
2886                         kvfree(jit_data->addrs);
2887                         kfree(jit_data);
2888                 }
2889                 hdr = bpf_jit_binary_pack_hdr(prog);
2890                 bpf_jit_binary_pack_free(hdr, NULL);
2891                 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog));
2892         }
2893
2894         bpf_prog_unlock_free(prog);
2895 }