1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Google, Inc
7 #include <debug_uart.h>
15 #include <asm/processor.h>
16 #include <asm-generic/sections.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 __weak int arch_cpu_init_dm(void)
25 static int x86_tpl_init(void)
29 debug("%s starting\n", __func__);
30 ret = x86_cpu_init_tpl();
32 debug("%s: x86_cpu_init_tpl() failed\n", __func__);
37 debug("%s: spl_init() failed\n", __func__);
40 ret = arch_cpu_init();
42 debug("%s: arch_cpu_init() failed\n", __func__);
45 ret = arch_cpu_init_dm();
47 debug("%s: arch_cpu_init_dm() failed\n", __func__);
50 preloader_console_init();
55 void board_init_f(ulong flags)
61 debug("Error %d\n", ret);
62 panic("x86_tpl_init fail");
65 /* Uninit CAR and jump to board_init_f_r() */
69 void board_init_f_r(void)
71 /* Not used since we never call board_init_f_r_trampoline() */
75 u32 spl_boot_device(void)
77 return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT :
81 int spl_start_uboot(void)
86 void spl_board_announce_boot_device(void)
91 static int spl_board_load_image(struct spl_image_info *spl_image,
92 struct spl_boot_device *bootdev)
94 spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
95 spl_image->entry_point = CONFIG_SPL_TEXT_BASE;
96 spl_image->load_addr = CONFIG_SPL_TEXT_BASE;
97 spl_image->os = IH_OS_U_BOOT;
98 spl_image->name = "U-Boot";
100 debug("Loading to %lx\n", spl_image->load_addr);
104 SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
106 int spl_spi_load_image(void)
111 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
113 debug("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point);
114 jump_to_spl(spl_image->entry_point);
118 void spl_board_init(void)
120 preloader_console_init();
123 #if !CONFIG_IS_ENABLED(PCI)
125 * This is a fake PCI bus for TPL when it doesn't have proper PCI. It is enough
126 * to bind the devices on the PCI bus, some of which have early-regs properties
127 * providing fixed BARs. Individual drivers program these BARs themselves so
128 * that they can access the devices. The BARs are allocated statically in the
131 * Once SPL is running it enables PCI properly, but does not auto-assign BARs
132 * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does
133 * the auto allocation (after relocation).
135 static const struct udevice_id tpl_fake_pci_ids[] = {
136 { .compatible = "pci-x86" },
140 U_BOOT_DRIVER(pci_x86) = {
142 .id = UCLASS_SIMPLE_BUS,
143 .of_match = tpl_fake_pci_ids,