1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 Google, Inc
8 #include <debug_uart.h>
19 #include <asm/cpu_common.h>
20 #include <asm/fsp2/fsp_api.h>
21 #include <asm/global_data.h>
22 #include <asm/mrccache.h>
25 #include <asm/processor.h>
27 #include <asm-generic/sections.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 __weak int fsp_setup_pinctrl(void *ctx, struct event *event)
38 static int set_max_freq(void)
40 if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) {
42 * Burst Mode has been factory-configured as disabled and is not
43 * available in this physical processor package
45 debug("Burst Mode is factory-disabled\n");
49 /* Enable burst mode */
50 cpu_set_burst_mode(true);
52 /* Enable speed step */
55 /* Set P-State ratio */
56 cpu_set_p_state_to_turbo_ratio();
62 static int x86_spl_init(void)
66 * TODO(sjg@chromium.org): We use this area of RAM for the stack
67 * and global_data in SPL. Once U-Boot starts up and releocates it
68 * is not needed. We could make this a CONFIG option or perhaps
69 * place it immediately below CONFIG_TEXT_BASE.
71 __maybe_unused char *ptr = (char *)0x110000;
73 struct udevice *punit;
77 debug("%s starting\n", __func__);
79 ret = x86_cpu_reinit_f();
81 ret = x86_cpu_init_f();
84 debug("%s: spl_init() failed\n", __func__);
87 ret = arch_cpu_init();
89 debug("%s: arch_cpu_init() failed\n", __func__);
93 ret = fsp_setup_pinctrl(NULL, NULL);
95 debug("%s: fsp_setup_pinctrl() failed\n", __func__);
99 preloader_console_init();
100 #if !defined(CONFIG_TPL) && !CONFIG_IS_ENABLED(CPU)
101 ret = print_cpuinfo();
103 debug("%s: print_cpuinfo() failed\n", __func__);
109 debug("%s: dram_init() failed\n", __func__);
112 if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
113 ret = mrccache_spl_save();
115 debug("%s: Failed to write to mrccache (err=%d)\n",
119 #ifndef CONFIG_SYS_COREBOOT
120 memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
123 /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
124 ret = interrupt_init();
126 debug("%s: interrupt_init() failed\n", __func__);
131 * The stack grows down from ptr. Put the global data at ptr. This
132 * will only be used for SPL. Once SPL loads U-Boot proper it will
133 * set up its own stack.
135 gd->new_gd = (struct global_data *)ptr;
136 memcpy(gd->new_gd, gd, sizeof(*gd));
137 arch_setup_gd(gd->new_gd);
138 gd->start_addr_sp = (ulong)ptr;
140 /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
141 ret = mtrr_add_request(MTRR_TYPE_WRBACK,
142 (1ULL << 32) - CONFIG_XIP_ROM_SIZE,
143 CONFIG_XIP_ROM_SIZE);
145 debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
150 ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
152 debug("Could not find PUNIT (err=%d)\n", ret);
154 ret = set_max_freq();
156 debug("Failed to set CPU frequency (err=%d)\n", ret);
163 void board_init_f(ulong flags)
167 ret = x86_spl_init();
169 printf("x86_spl_init: error %d\n", ret);
172 #if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT)
173 gd->bd = malloc(sizeof(*gd->bd));
175 printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
180 /* Uninit CAR and jump to board_init_f_r() */
181 board_init_f_r_trampoline(gd->start_addr_sp);
185 void board_init_f_r(void)
188 gd->flags &= ~GD_FLG_SERIAL_READY;
189 debug("cache status %d\n", dcache_status());
193 u32 spl_boot_device(void)
195 return BOOT_DEVICE_SPI_MMAP;
198 int spl_start_uboot(void)
203 void spl_board_announce_boot_device(void)
208 static int spl_board_load_image(struct spl_image_info *spl_image,
209 struct spl_boot_device *bootdev)
211 spl_image->size = CONFIG_SYS_MONITOR_LEN;
212 spl_image->entry_point = CONFIG_TEXT_BASE;
213 spl_image->load_addr = CONFIG_TEXT_BASE;
214 spl_image->os = IH_OS_U_BOOT;
215 spl_image->name = "U-Boot";
217 if (!IS_ENABLED(CONFIG_SYS_COREBOOT)) {
219 * Copy U-Boot from ROM
220 * TODO(sjg@chromium.org): Figure out a way to get the text base
221 * correctly here, and in the device-tree binman definition.
223 * Also consider using FIT so we get the correct image length
226 memcpy((char *)spl_image->load_addr, (char *)0xfff00000,
230 debug("Loading to %lx\n", spl_image->load_addr);
234 SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
236 int spl_spi_load_image(void)
241 #ifdef CONFIG_X86_RUN_64BIT
242 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
246 printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
247 ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
248 debug("ret=%d\n", ret);
253 void spl_board_init(void)
256 preloader_console_init();