2 * From coreboot src/southbridge/intel/bd82x6x/mrccache.c
4 * Copyright (C) 2014 Google Inc.
6 * SPDX-License-Identifier: GPL-2.0
14 #include <spi_flash.h>
15 #include <asm/mrccache.h>
17 static struct mrc_data_container *next_mrc_block(
18 struct mrc_data_container *cache)
20 /* MRC data blocks are aligned within the region */
21 u32 mrc_size = sizeof(*cache) + cache->data_size;
22 u8 *region_ptr = (u8 *)cache;
24 if (mrc_size & (MRC_DATA_ALIGN - 1UL)) {
25 mrc_size &= ~(MRC_DATA_ALIGN - 1UL);
26 mrc_size += MRC_DATA_ALIGN;
29 region_ptr += mrc_size;
31 return (struct mrc_data_container *)region_ptr;
34 static int is_mrc_cache(struct mrc_data_container *cache)
36 return cache && (cache->signature == MRC_DATA_SIGNATURE);
39 struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry)
41 struct mrc_data_container *cache, *next;
42 ulong base_addr, end_addr;
45 base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset;
46 end_addr = base_addr + entry->length;
49 /* Search for the last filled entry in the region */
50 for (id = 0, next = (struct mrc_data_container *)base_addr;
54 next = next_mrc_block(next);
55 if ((ulong)next >= end_addr)
60 debug("%s: No valid MRC cache found.\n", __func__);
65 if (cache->checksum != compute_ip_checksum(cache->data,
67 printf("%s: MRC cache checksum mismatch\n", __func__);
71 debug("%s: picked entry %u from cache block\n", __func__, id);
77 * find_next_mrc_cache() - get next cache entry
79 * @entry: MRC cache flash area
80 * @cache: Entry to start from
82 * @return next cache entry if found, NULL if we got to the end
84 static struct mrc_data_container *find_next_mrc_cache(struct fmap_entry *entry,
85 struct mrc_data_container *cache)
87 ulong base_addr, end_addr;
89 base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset;
90 end_addr = base_addr + entry->length;
92 cache = next_mrc_block(cache);
93 if ((ulong)cache >= end_addr) {
94 /* Crossed the boundary */
96 debug("%s: no available entries found\n", __func__);
98 debug("%s: picked next entry from cache block at %p\n",
105 int mrccache_update(struct udevice *sf, struct fmap_entry *entry,
106 struct mrc_data_container *cur)
108 struct mrc_data_container *cache;
113 if (!is_mrc_cache(cur))
116 /* Find the last used block */
117 base_addr = (1ULL << 32) - CONFIG_ROM_SIZE + entry->offset;
118 debug("Updating MRC cache data\n");
119 cache = mrccache_find_current(entry);
120 if (cache && (cache->data_size == cur->data_size) &&
121 (!memcmp(cache, cur, cache->data_size + sizeof(*cur)))) {
122 debug("MRC data in flash is up to date. No update\n");
126 /* Move to the next block, which will be the first unused block */
128 cache = find_next_mrc_cache(entry, cache);
131 * If we have got to the end, erase the entire mrc-cache area and start
135 debug("Erasing the MRC cache region of %x bytes at %x\n",
136 entry->length, entry->offset);
138 ret = spi_flash_erase_dm(sf, entry->offset, entry->length);
140 debug("Failed to erase flash region\n");
143 cache = (struct mrc_data_container *)base_addr;
146 /* Write the data out */
147 offset = (ulong)cache - base_addr + entry->offset;
148 debug("Write MRC cache update to flash at %lx\n", offset);
149 ret = spi_flash_write_dm(sf, offset, cur->data_size + sizeof(*cur),
152 debug("Failed to write to SPI flash\n");