arch/x86/lib/fsp2/fsp_dram.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 Google LLC
   4  * Written by Simon Glass <sjg@chromium.org>
   5  */
   6
   7 #define LOG_CATEGORY LOGC_ARCH
   8
   9 #include <common.h>
  10 #include <handoff.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <spl.h>
  14 #include <acpi/acpi_s3.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/fsp/fsp_support.h>
  17 #include <asm/fsp2/fsp_api.h>
  18 #include <asm/fsp2/fsp_internal.h>
  19 #include <asm/global_data.h>
  20 #include <linux/sizes.h>
  21
  22 int dram_init(void)
  23 {
  24         int ret;
  25
  26         if (!ll_boot_init()) {
  27                 /* Use a small and safe amount of 1GB */
  28                 gd->ram_size = SZ_1G;
  29
  30                 return 0;
  31         }
  32         if (spl_phase() == PHASE_SPL) {
  33                 bool s3wake = false;
  34
  35                 s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
  36                         gd->arch.prev_sleep_state == ACPI_S3;
  37
  38                 ret = fsp_memory_init(s3wake,
  39                               IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH));
  40                 if (ret) {
  41                         log_debug("Memory init failed (err=%x)\n", ret);
  42                         return ret;
  43                 }
  44
  45                 /* The FSP has already set up DRAM, so grab the info we need */
  46                 ret = fsp_scan_for_ram_size();
  47                 if (ret)
  48                         return ret;
  49
  50 #ifdef CONFIG_ENABLE_MRC_CACHE
  51                 gd->arch.mrc[MRC_TYPE_NORMAL].buf =
  52                         fsp_get_nvs_data(gd->arch.hob_list,
  53                                          &gd->arch.mrc[MRC_TYPE_NORMAL].len);
  54                 gd->arch.mrc[MRC_TYPE_VAR].buf =
  55                         fsp_get_var_nvs_data(gd->arch.hob_list,
  56                                              &gd->arch.mrc[MRC_TYPE_VAR].len);
  57                 log_debug("normal %x, var %x\n",
  58                           gd->arch.mrc[MRC_TYPE_NORMAL].len,
  59                           gd->arch.mrc[MRC_TYPE_VAR].len);
  60 #endif
  61         } else {
  62 #if CONFIG_IS_ENABLED(HANDOFF)
  63                 struct spl_handoff *ho = gd->spl_handoff;
  64
  65                 if (!ho) {
  66                         log_debug("No SPL handoff found\n");
  67                         return -ESTRPIPE;
  68                 }
  69                 gd->ram_size = ho->ram_size;
  70                 handoff_load_dram_banks(ho);
  71 #endif
  72                 ret = arch_fsps_preinit();
  73                 if (ret)
  74                         return log_msg_ret("fsp_s_preinit", ret);
  75         }
  76
  77         return 0;
  78 }
  79
  80 ulong board_get_usable_ram_top(ulong total_size)
  81 {
  82         if (!ll_boot_init())
  83                 return gd->ram_size;
  84
  85 #if CONFIG_IS_ENABLED(HANDOFF)
  86         struct spl_handoff *ho = gd->spl_handoff;
  87
  88         log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top);
  89
  90         return ho->arch.usable_ram_top;
  91 #endif
  92
  93         return gd->ram_top;
  94 }