arch/x86/lib/fsp/fsp_dram.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <handoff.h>
   8 #include <init.h>
   9 #include <asm/fsp/fsp_support.h>
  10 #include <asm/e820.h>
  11 #include <asm/mrccache.h>
  12 #include <asm/post.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 int fsp_scan_for_ram_size(void)
  17 {
  18         phys_size_t ram_size = 0;
  19         const struct hob_header *hdr;
  20         struct hob_res_desc *res_desc;
  21
  22         hdr = gd->arch.hob_list;
  23         while (!end_of_hob(hdr)) {
  24                 if (hdr->type == HOB_TYPE_RES_DESC) {
  25                         res_desc = (struct hob_res_desc *)hdr;
  26                         if (res_desc->type == RES_SYS_MEM ||
  27                             res_desc->type == RES_MEM_RESERVED)
  28                                 ram_size += res_desc->len;
  29                 }
  30                 hdr = get_next_hob(hdr);
  31         }
  32
  33         gd->ram_size = ram_size;
  34         post_code(POST_DRAM);
  35
  36         return 0;
  37 };
  38
  39 int dram_init_banksize(void)
  40 {
  41         const struct hob_header *hdr;
  42         struct hob_res_desc *res_desc;
  43         phys_addr_t low_end;
  44         uint bank;
  45
  46         low_end = 0;
  47         for (bank = 1, hdr = gd->arch.hob_list;
  48              bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
  49              hdr = get_next_hob(hdr)) {
  50                 if (hdr->type != HOB_TYPE_RES_DESC)
  51                         continue;
  52                 res_desc = (struct hob_res_desc *)hdr;
  53                 if (res_desc->type != RES_SYS_MEM &&
  54                     res_desc->type != RES_MEM_RESERVED)
  55                         continue;
  56                 if (res_desc->phys_start < (1ULL << 32)) {
  57                         low_end = max(low_end,
  58                                       res_desc->phys_start + res_desc->len);
  59                         continue;
  60                 }
  61
  62                 gd->bd->bi_dram[bank].start = res_desc->phys_start;
  63                 gd->bd->bi_dram[bank].size = res_desc->len;
  64                 log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
  65                           gd->bd->bi_dram[bank].size);
  66         }
  67
  68         /* Add the memory below 4GB */
  69         gd->bd->bi_dram[0].start = 0;
  70         gd->bd->bi_dram[0].size = low_end;
  71
  72         return 0;
  73 }
  74
  75 unsigned int install_e820_map(unsigned int max_entries,
  76                               struct e820_entry *entries)
  77 {
  78         unsigned int num_entries = 0;
  79         const struct hob_header *hdr;
  80         struct hob_res_desc *res_desc;
  81
  82         hdr = gd->arch.hob_list;
  83
  84         while (!end_of_hob(hdr)) {
  85                 if (hdr->type == HOB_TYPE_RES_DESC) {
  86                         res_desc = (struct hob_res_desc *)hdr;
  87                         entries[num_entries].addr = res_desc->phys_start;
  88                         entries[num_entries].size = res_desc->len;
  89
  90                         if (res_desc->type == RES_SYS_MEM)
  91                                 entries[num_entries].type = E820_RAM;
  92                         else if (res_desc->type == RES_MEM_RESERVED)
  93                                 entries[num_entries].type = E820_RESERVED;
  94
  95                         num_entries++;
  96                 }
  97                 hdr = get_next_hob(hdr);
  98         }
  99
 100         /* Mark PCIe ECAM address range as reserved */
 101         entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
 102         entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
 103         entries[num_entries].type = E820_RESERVED;
 104         num_entries++;
 105
 106 #ifdef CONFIG_HAVE_ACPI_RESUME
 107         /*
 108          * Everything between U-Boot's stack and ram top needs to be
 109          * reserved in order for ACPI S3 resume to work.
 110          */
 111         entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
 112         entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
 113                 CONFIG_STACK_SIZE;
 114         entries[num_entries].type = E820_RESERVED;
 115         num_entries++;
 116 #endif
 117
 118         return num_entries;
 119 }
 120
 121 #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
 122 int handoff_arch_save(struct spl_handoff *ho)
 123 {
 124         ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
 125         ho->arch.hob_list = gd->arch.hob_list;
 126
 127         return 0;
 128 }
 129 #endif