1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
9 #include <asm/fsp/fsp_support.h>
11 #include <asm/mrccache.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 int fsp_scan_for_ram_size(void)
19 phys_size_t ram_size = 0;
20 const struct hob_header *hdr;
21 struct hob_res_desc *res_desc;
23 hdr = gd->arch.hob_list;
24 while (!end_of_hob(hdr)) {
25 if (hdr->type == HOB_TYPE_RES_DESC) {
26 res_desc = (struct hob_res_desc *)hdr;
27 if (res_desc->type == RES_SYS_MEM ||
28 res_desc->type == RES_MEM_RESERVED)
29 ram_size += res_desc->len;
31 hdr = get_next_hob(hdr);
34 gd->ram_size = ram_size;
40 int dram_init_banksize(void)
42 const struct hob_header *hdr;
43 struct hob_res_desc *res_desc;
48 for (bank = 1, hdr = gd->arch.hob_list;
49 bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
50 hdr = get_next_hob(hdr)) {
51 if (hdr->type != HOB_TYPE_RES_DESC)
53 res_desc = (struct hob_res_desc *)hdr;
54 if (res_desc->type != RES_SYS_MEM &&
55 res_desc->type != RES_MEM_RESERVED)
57 if (res_desc->phys_start < (1ULL << 32)) {
58 low_end = max(low_end,
59 res_desc->phys_start + res_desc->len);
63 gd->bd->bi_dram[bank].start = res_desc->phys_start;
64 gd->bd->bi_dram[bank].size = res_desc->len;
65 mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
67 log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
68 gd->bd->bi_dram[bank].size);
71 /* Add the memory below 4GB */
72 gd->bd->bi_dram[0].start = 0;
73 gd->bd->bi_dram[0].size = low_end;
75 mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
80 unsigned int install_e820_map(unsigned int max_entries,
81 struct e820_entry *entries)
83 unsigned int num_entries = 0;
84 const struct hob_header *hdr;
85 struct hob_res_desc *res_desc;
87 hdr = gd->arch.hob_list;
89 while (!end_of_hob(hdr)) {
90 if (hdr->type == HOB_TYPE_RES_DESC) {
91 res_desc = (struct hob_res_desc *)hdr;
92 entries[num_entries].addr = res_desc->phys_start;
93 entries[num_entries].size = res_desc->len;
95 if (res_desc->type == RES_SYS_MEM)
96 entries[num_entries].type = E820_RAM;
97 else if (res_desc->type == RES_MEM_RESERVED)
98 entries[num_entries].type = E820_RESERVED;
102 hdr = get_next_hob(hdr);
105 /* Mark PCIe ECAM address range as reserved */
106 entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
107 entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
108 entries[num_entries].type = E820_RESERVED;
111 #ifdef CONFIG_HAVE_ACPI_RESUME
113 * Everything between U-Boot's stack and ram top needs to be
114 * reserved in order for ACPI S3 resume to work.
116 entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
117 entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
119 entries[num_entries].type = E820_RESERVED;
126 #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
127 int handoff_arch_save(struct spl_handoff *ho)
129 ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
130 ho->arch.hob_list = gd->arch.hob_list;