1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
9 #include <asm/fsp/fsp_support.h>
11 #include <asm/mrccache.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 int fsp_scan_for_ram_size(void)
19 phys_size_t ram_size = 0;
20 const struct hob_header *hdr;
21 struct hob_res_desc *res_desc;
23 hdr = gd->arch.hob_list;
24 while (!end_of_hob(hdr)) {
25 if (hdr->type == HOB_TYPE_RES_DESC) {
26 res_desc = (struct hob_res_desc *)hdr;
27 if (res_desc->type == RES_SYS_MEM ||
28 res_desc->type == RES_MEM_RESERVED)
29 ram_size += res_desc->len;
31 hdr = get_next_hob(hdr);
34 gd->ram_size = ram_size;
40 int dram_init_banksize(void)
42 const struct hob_header *hdr;
43 struct hob_res_desc *res_desc;
47 if (!ll_boot_init()) {
48 gd->bd->bi_dram[0].start = 0;
49 gd->bd->bi_dram[0].size = gd->ram_size;
51 mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
56 for (bank = 1, hdr = gd->arch.hob_list;
57 bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
58 hdr = get_next_hob(hdr)) {
59 if (hdr->type != HOB_TYPE_RES_DESC)
61 res_desc = (struct hob_res_desc *)hdr;
62 if (res_desc->type != RES_SYS_MEM &&
63 res_desc->type != RES_MEM_RESERVED)
65 if (res_desc->phys_start < (1ULL << 32)) {
66 low_end = max(low_end,
67 res_desc->phys_start + res_desc->len);
71 gd->bd->bi_dram[bank].start = res_desc->phys_start;
72 gd->bd->bi_dram[bank].size = res_desc->len;
73 mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
75 log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
76 gd->bd->bi_dram[bank].size);
79 /* Add the memory below 4GB */
80 gd->bd->bi_dram[0].start = 0;
81 gd->bd->bi_dram[0].size = low_end;
83 mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
88 unsigned int install_e820_map(unsigned int max_entries,
89 struct e820_entry *entries)
91 unsigned int num_entries = 0;
92 const struct hob_header *hdr;
93 struct hob_res_desc *res_desc;
95 hdr = gd->arch.hob_list;
97 while (!end_of_hob(hdr)) {
98 if (hdr->type == HOB_TYPE_RES_DESC) {
99 res_desc = (struct hob_res_desc *)hdr;
100 entries[num_entries].addr = res_desc->phys_start;
101 entries[num_entries].size = res_desc->len;
103 if (res_desc->type == RES_SYS_MEM)
104 entries[num_entries].type = E820_RAM;
105 else if (res_desc->type == RES_MEM_RESERVED)
106 entries[num_entries].type = E820_RESERVED;
110 hdr = get_next_hob(hdr);
113 /* Mark PCIe ECAM address range as reserved */
114 entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
115 entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
116 entries[num_entries].type = E820_RESERVED;
119 #ifdef CONFIG_HAVE_ACPI_RESUME
121 * Everything between U-Boot's stack and ram top needs to be
122 * reserved in order for ACPI S3 resume to work.
124 entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
125 entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
127 entries[num_entries].type = E820_RESERVED;
134 #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
135 int handoff_arch_save(struct spl_handoff *ho)
137 ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
138 ho->arch.hob_list = gd->arch.hob_list;