arch/x86/lib/fsp/fsp_dram.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <handoff.h>
   8 #include <init.h>
   9 #include <asm/fsp/fsp_support.h>
  10 #include <asm/e820.h>
  11 #include <asm/mrccache.h>
  12 #include <asm/mtrr.h>
  13 #include <asm/post.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 int fsp_scan_for_ram_size(void)
  18 {
  19         phys_size_t ram_size = 0;
  20         const struct hob_header *hdr;
  21         struct hob_res_desc *res_desc;
  22
  23         hdr = gd->arch.hob_list;
  24         while (!end_of_hob(hdr)) {
  25                 if (hdr->type == HOB_TYPE_RES_DESC) {
  26                         res_desc = (struct hob_res_desc *)hdr;
  27                         if (res_desc->type == RES_SYS_MEM ||
  28                             res_desc->type == RES_MEM_RESERVED)
  29                                 ram_size += res_desc->len;
  30                 }
  31                 hdr = get_next_hob(hdr);
  32         }
  33
  34         gd->ram_size = ram_size;
  35         post_code(POST_DRAM);
  36
  37         return 0;
  38 };
  39
  40 int dram_init_banksize(void)
  41 {
  42         const struct hob_header *hdr;
  43         struct hob_res_desc *res_desc;
  44         phys_addr_t low_end;
  45         uint bank;
  46
  47         low_end = 0;
  48         for (bank = 1, hdr = gd->arch.hob_list;
  49              bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
  50              hdr = get_next_hob(hdr)) {
  51                 if (hdr->type != HOB_TYPE_RES_DESC)
  52                         continue;
  53                 res_desc = (struct hob_res_desc *)hdr;
  54                 if (res_desc->type != RES_SYS_MEM &&
  55                     res_desc->type != RES_MEM_RESERVED)
  56                         continue;
  57                 if (res_desc->phys_start < (1ULL << 32)) {
  58                         low_end = max(low_end,
  59                                       res_desc->phys_start + res_desc->len);
  60                         continue;
  61                 }
  62
  63                 gd->bd->bi_dram[bank].start = res_desc->phys_start;
  64                 gd->bd->bi_dram[bank].size = res_desc->len;
  65                 mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
  66                                  res_desc->len);
  67                 log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
  68                           gd->bd->bi_dram[bank].size);
  69         }
  70
  71         /* Add the memory below 4GB */
  72         gd->bd->bi_dram[0].start = 0;
  73         gd->bd->bi_dram[0].size = low_end;
  74
  75         mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
  76
  77         return 0;
  78 }
  79
  80 unsigned int install_e820_map(unsigned int max_entries,
  81                               struct e820_entry *entries)
  82 {
  83         unsigned int num_entries = 0;
  84         const struct hob_header *hdr;
  85         struct hob_res_desc *res_desc;
  86
  87         hdr = gd->arch.hob_list;
  88
  89         while (!end_of_hob(hdr)) {
  90                 if (hdr->type == HOB_TYPE_RES_DESC) {
  91                         res_desc = (struct hob_res_desc *)hdr;
  92                         entries[num_entries].addr = res_desc->phys_start;
  93                         entries[num_entries].size = res_desc->len;
  94
  95                         if (res_desc->type == RES_SYS_MEM)
  96                                 entries[num_entries].type = E820_RAM;
  97                         else if (res_desc->type == RES_MEM_RESERVED)
  98                                 entries[num_entries].type = E820_RESERVED;
  99
 100                         num_entries++;
 101                 }
 102                 hdr = get_next_hob(hdr);
 103         }
 104
 105         /* Mark PCIe ECAM address range as reserved */
 106         entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
 107         entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
 108         entries[num_entries].type = E820_RESERVED;
 109         num_entries++;
 110
 111 #ifdef CONFIG_HAVE_ACPI_RESUME
 112         /*
 113          * Everything between U-Boot's stack and ram top needs to be
 114          * reserved in order for ACPI S3 resume to work.
 115          */
 116         entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
 117         entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
 118                 CONFIG_STACK_SIZE;
 119         entries[num_entries].type = E820_RESERVED;
 120         num_entries++;
 121 #endif
 122
 123         return num_entries;
 124 }
 125
 126 #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
 127 int handoff_arch_save(struct spl_handoff *ho)
 128 {
 129         ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
 130         ho->arch.hob_list = gd->arch.hob_list;
 131
 132         return 0;
 133 }
 134 #endif