1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on acpi.c from coreboot
5 * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
6 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
9 #define LOG_CATEGORY LOGC_ACPI
16 #include <dm/uclass-internal.h>
19 #include <acpi/acpigen.h>
20 #include <acpi/acpi_device.h>
21 #include <acpi/acpi_table.h>
22 #include <asm/acpi/global_nvs.h>
23 #include <asm/ioapic.h>
24 #include <asm/global_data.h>
25 #include <asm/lapic.h>
26 #include <asm/mpspec.h>
27 #include <asm/tables.h>
28 #include <asm/arch/global_nvs.h>
30 #include <linux/err.h>
32 static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
35 lapic->type = ACPI_APIC_LAPIC;
36 lapic->length = sizeof(struct acpi_madt_lapic);
37 lapic->flags = LOCAL_APIC_FLAG_ENABLED;
38 lapic->processor_id = cpu;
39 lapic->apic_id = apic;
44 int acpi_create_madt_lapics(u32 current)
50 for (uclass_find_first_device(UCLASS_CPU, &dev);
52 uclass_find_next_device(&dev)) {
53 struct cpu_plat *plat = dev_get_parent_plat(dev);
56 length = acpi_create_madt_lapic(
57 (struct acpi_madt_lapic *)current, cpu_num++,
60 total_length += length;
66 int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
67 u32 addr, u32 gsi_base)
69 ioapic->type = ACPI_APIC_IOAPIC;
70 ioapic->length = sizeof(struct acpi_madt_ioapic);
71 ioapic->reserved = 0x00;
72 ioapic->gsi_base = gsi_base;
73 ioapic->ioapic_id = id;
74 ioapic->ioapic_addr = addr;
76 return ioapic->length;
79 int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
80 u8 bus, u8 source, u32 gsirq, u16 flags)
82 irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE;
83 irqoverride->length = sizeof(struct acpi_madt_irqoverride);
84 irqoverride->bus = bus;
85 irqoverride->source = source;
86 irqoverride->gsirq = gsirq;
87 irqoverride->flags = flags;
89 return irqoverride->length;
92 int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
93 u8 cpu, u16 flags, u8 lint)
95 lapic_nmi->type = ACPI_APIC_LAPIC_NMI;
96 lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi);
97 lapic_nmi->flags = flags;
98 lapic_nmi->processor_id = cpu;
99 lapic_nmi->lint = lint;
101 return lapic_nmi->length;
104 static int acpi_create_madt_irq_overrides(u32 current)
106 struct acpi_madt_irqoverride *irqovr;
107 u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
110 irqovr = (void *)current;
111 length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
113 irqovr = (void *)(current + length);
114 length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
119 __weak u32 acpi_fill_madt(u32 current)
121 current += acpi_create_madt_lapics(current);
123 current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
124 io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
126 current += acpi_create_madt_irq_overrides(current);
131 int acpi_write_madt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
133 struct acpi_table_header *header;
134 struct acpi_madt *madt;
139 memset(madt, '\0', sizeof(struct acpi_madt));
140 header = &madt->header;
142 /* Fill out header fields */
143 acpi_fill_header(header, "APIC");
144 header->length = sizeof(struct acpi_madt);
145 header->revision = ACPI_MADT_REV_ACPI_3_0;
147 madt->lapic_addr = LAPIC_DEFAULT_BASE;
148 madt->flags = ACPI_MADT_PCAT_COMPAT;
150 current = (u32)madt + sizeof(struct acpi_madt);
151 current = acpi_fill_madt(current);
153 /* (Re)calculate length and checksum */
154 header->length = current - (u32)madt;
156 header->checksum = table_compute_checksum((void *)madt, header->length);
157 acpi_add_table(ctx, madt);
158 acpi_inc(ctx, madt->header.length);
162 ACPI_WRITER(5x86, NULL, acpi_write_madt, 0);
165 * acpi_create_tcpa() - Create a TCPA table
167 * Trusted Computing Platform Alliance Capabilities Table
168 * TCPA PC Specific Implementation SpecificationTCPA is defined in the PCI
169 * Firmware Specification 3.0
171 int acpi_write_tcpa(struct acpi_ctx *ctx, const struct acpi_writer *entry)
173 struct acpi_table_header *header;
174 struct acpi_tcpa *tcpa;
176 int size = 0x10000; /* Use this as the default size */
180 if (!IS_ENABLED(CONFIG_TPM_V1))
182 if (!CONFIG_IS_ENABLED(BLOBLIST))
186 header = &tcpa->header;
187 memset(tcpa, '\0', sizeof(struct acpi_tcpa));
189 /* Fill out header fields */
190 acpi_fill_header(header, "TCPA");
191 header->length = sizeof(struct acpi_tcpa);
192 header->revision = 1;
194 ret = bloblist_ensure_size_ret(BLOBLISTT_TCPA_LOG, &size, &log);
196 return log_msg_ret("blob", ret);
198 tcpa->platform_class = 0;
200 tcpa->lasa = map_to_sysmem(log);
202 /* (Re)calculate length and checksum */
203 current = (u32)tcpa + sizeof(struct acpi_tcpa);
204 header->length = current - (u32)tcpa;
205 header->checksum = table_compute_checksum(tcpa, header->length);
207 acpi_inc(ctx, tcpa->header.length);
208 acpi_add_table(ctx, tcpa);
212 ACPI_WRITER(5tcpa, "TCPA", acpi_write_tcpa, 0);
214 static int get_tpm2_log(void **ptrp, int *sizep)
216 const int tpm2_default_log_len = 0x10000;
221 size = tpm2_default_log_len;
222 ret = bloblist_ensure_size_ret(BLOBLISTT_TPM2_TCG_LOG, &size, ptrp);
224 return log_msg_ret("blob", ret);
230 static int acpi_write_tpm2(struct acpi_ctx *ctx,
231 const struct acpi_writer *entry)
233 struct acpi_table_header *header;
234 struct acpi_tpm2 *tpm2;
239 if (!IS_ENABLED(CONFIG_TPM_V2))
240 return log_msg_ret("none", -ENOENT);
243 header = &tpm2->header;
244 memset(tpm2, '\0', sizeof(struct acpi_tpm2));
247 * Some payloads like SeaBIOS depend on log area to use TPM2.
248 * Get the memory size and address of TPM2 log area or initialize it.
250 ret = get_tpm2_log(&lasa, &tpm2_log_len);
252 return log_msg_ret("log", ret);
254 /* Fill out header fields. */
255 acpi_fill_header(header, "TPM2");
256 memcpy(header->aslc_id, ASLC_ID, 4);
258 header->length = sizeof(struct acpi_tpm2);
259 header->revision = acpi_get_table_revision(ACPITAB_TPM2);
261 /* Hard to detect for U-Boot. Just set it to 0 */
262 tpm2->platform_class = 0;
264 /* Must be set to 0 for FIFO-interface support */
265 tpm2->control_area = 0;
266 tpm2->start_method = 6;
267 memset(tpm2->msp, 0, sizeof(tpm2->msp));
269 /* Fill the log area size and start address fields. */
270 tpm2->laml = tpm2_log_len;
271 tpm2->lasa = map_to_sysmem(lasa);
273 /* Calculate checksum. */
274 header->checksum = table_compute_checksum(tpm2, header->length);
276 acpi_inc(ctx, tpm2->header.length);
277 acpi_add_table(ctx, tpm2);
281 ACPI_WRITER(5tpm2, "TPM2", acpi_write_tpm2, 0);
283 int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry)
285 struct serial_device_info serial_info = {0};
286 ulong serial_address, serial_offset;
287 struct acpi_table_header *header;
288 struct acpi_spcr *spcr;
297 header = &spcr->header;
299 memset(spcr, '\0', sizeof(struct acpi_spcr));
301 /* Fill out header fields */
302 acpi_fill_header(header, "SPCR");
303 header->length = sizeof(struct acpi_spcr);
304 header->revision = 2;
306 /* Read the device once, here. It is reused below */
307 dev = gd->cur_serial_dev;
309 ret = serial_getinfo(dev, &serial_info);
311 serial_info.type = SERIAL_CHIP_UNKNOWN;
313 /* Encode chip type */
314 switch (serial_info.type) {
315 case SERIAL_CHIP_16550_COMPATIBLE:
316 spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE;
318 case SERIAL_CHIP_UNKNOWN:
320 spcr->interface_type = ACPI_DBG2_UNKNOWN;
324 /* Encode address space */
325 switch (serial_info.addr_space) {
326 case SERIAL_ADDRESS_SPACE_MEMORY:
327 space_id = ACPI_ADDRESS_SPACE_MEMORY;
329 case SERIAL_ADDRESS_SPACE_IO:
331 space_id = ACPI_ADDRESS_SPACE_IO;
335 serial_width = serial_info.reg_width * 8;
336 serial_offset = serial_info.reg_offset << serial_info.reg_shift;
337 serial_address = serial_info.addr + serial_offset;
339 /* Encode register access size */
340 switch (serial_info.reg_shift) {
342 access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
345 access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
348 access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
351 access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;
354 access_size = ACPI_ACCESS_SIZE_UNDEFINED;
358 debug("UART type %u @ %lx\n", spcr->interface_type, serial_address);
361 spcr->serial_port.space_id = space_id;
362 spcr->serial_port.bit_width = serial_width;
363 spcr->serial_port.bit_offset = 0;
364 spcr->serial_port.access_size = access_size;
365 spcr->serial_port.addrl = lower_32_bits(serial_address);
366 spcr->serial_port.addrh = upper_32_bits(serial_address);
368 /* Encode baud rate */
369 switch (serial_info.baudrate) {
387 serial_config = SERIAL_DEFAULT_CONFIG;
389 ret = serial_getconfig(dev, &serial_config);
391 spcr->parity = SERIAL_GET_PARITY(serial_config);
392 spcr->stop_bits = SERIAL_GET_STOP(serial_config);
394 /* No PCI devices for now */
395 spcr->pci_device_id = 0xffff;
396 spcr->pci_vendor_id = 0xffff;
399 * SPCR has no clue if the UART base clock speed is different
400 * to the default one. However, the SPCR 1.04 defines baud rate
401 * 0 as a preconfigured state of UART and OS is supposed not
402 * to touch the configuration of the serial device.
404 if (serial_info.clock != SERIAL_DEFAULT_CLOCK)
408 header->checksum = table_compute_checksum((void *)spcr, header->length);
410 acpi_add_table(ctx, spcr);
411 acpi_inc(ctx, spcr->header.length);
415 ACPI_WRITER(5spcr, "SPCR", acpi_write_spcr, 0);
417 int acpi_write_gnvs(struct acpi_ctx *ctx, const struct acpi_writer *entry)
421 if (!IS_ENABLED(CONFIG_ACPI_GNVS_EXTERNAL)) {
424 /* We need the DSDT to be done */
426 return log_msg_ret("dsdt", -EAGAIN);
428 /* Pack GNVS into the ACPI table area */
429 for (i = 0; i < ctx->dsdt->length; i++) {
430 u32 *gnvs = (u32 *)((u32)ctx->dsdt + i);
432 if (*gnvs == ACPI_GNVS_ADDR) {
433 *gnvs = map_to_sysmem(ctx->current);
434 log_debug("Fix up global NVS in DSDT to %#08x\n",
441 * Recalculate the length and update the DSDT checksum since we
442 * patched the GNVS address. Set the checksum to zero since it
443 * is part of the region being checksummed.
445 ctx->dsdt->checksum = 0;
446 ctx->dsdt->checksum = table_compute_checksum((void *)ctx->dsdt,
450 /* Fill in platform-specific global NVS variables */
451 addr = acpi_create_gnvs(ctx->current);
452 if (IS_ERR_VALUE(addr))
453 return log_msg_ret("gnvs", (int)addr);
455 acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));
459 ACPI_WRITER(4gnvs, "GNVS", acpi_write_gnvs, 0);
461 static int acpi_write_fadt(struct acpi_ctx *ctx,
462 const struct acpi_writer *entry)
464 struct acpi_fadt *fadt;
467 acpi_create_fadt(fadt, ctx->facs, ctx->dsdt);
468 acpi_add_table(ctx, fadt);
470 acpi_inc(ctx, sizeof(struct acpi_fadt));
474 ACPI_WRITER(5fact, "FADT", acpi_write_fadt, 0);
477 * acpi_write_hpet() - Write out a HPET table
479 * Write out the table for High-Precision Event Timers
481 * @hpet: Place to put HPET table
483 static int acpi_create_hpet(struct acpi_hpet *hpet)
485 struct acpi_table_header *header = &hpet->header;
486 struct acpi_gen_regaddr *addr = &hpet->addr;
489 * See IA-PC HPET (High Precision Event Timers) Specification v1.0a
490 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/software-developers-hpet-spec-1-0a.pdf
492 memset((void *)hpet, '\0', sizeof(struct acpi_hpet));
494 /* Fill out header fields. */
495 acpi_fill_header(header, "HPET");
497 header->aslc_revision = ASL_REVISION;
498 header->length = sizeof(struct acpi_hpet);
499 header->revision = acpi_get_table_revision(ACPITAB_HPET);
501 /* Fill out HPET address */
502 addr->space_id = 0; /* Memory */
503 addr->bit_width = 64;
504 addr->bit_offset = 0;
505 addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff;
506 addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32;
508 hpet->id = *(u32 *)CONFIG_HPET_ADDRESS;
510 hpet->min_tick = 0; /* HPET_MIN_TICKS */
512 header->checksum = table_compute_checksum(hpet,
513 sizeof(struct acpi_hpet));
518 int acpi_write_hpet(struct acpi_ctx *ctx)
520 struct acpi_hpet *hpet;
523 log_debug("ACPI: * HPET\n");
526 acpi_inc_align(ctx, sizeof(struct acpi_hpet));
527 acpi_create_hpet(hpet);
528 ret = acpi_add_table(ctx, hpet);
530 return log_msg_ret("add", ret);
535 int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
538 struct acpi_dbg2_header *dbg2 = ctx->current;
539 char path[ACPI_PATH_MAX];
540 struct acpi_gen_regaddr address;
544 if (!device_active(dev)) {
545 log_info("Device not enabled\n");
549 * PCI devices don't remember their resource allocation information in
550 * U-Boot at present. We assume that MMIO is used for the UART and that
551 * the address space is 32 bytes: ns16550 uses 8 registers of up to
552 * 32-bits each. This is only for debugging so it is not a big deal.
554 addr = dm_pci_read_bar32(dev, 0);
555 log_debug("UART addr %lx\n", (ulong)addr);
557 memset(&address, '\0', sizeof(address));
558 address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
559 address.addrl = (uint32_t)addr;
560 address.addrh = (uint32_t)((addr >> 32) & 0xffffffff);
561 address.access_size = access_size;
563 ret = acpi_device_path(dev, path, sizeof(path));
565 return log_msg_ret("path", ret);
566 acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
567 ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);
569 acpi_inc_align(ctx, dbg2->header.length);
570 acpi_add_table(ctx, dbg2);
575 void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
578 struct acpi_table_header *header = &fadt->header;
580 memset((void *)fadt, '\0', sizeof(struct acpi_fadt));
582 acpi_fill_header(header, "FACP");
583 header->length = sizeof(struct acpi_fadt);
584 header->revision = 4;
585 memcpy(header->oem_id, OEM_ID, 6);
586 memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
587 memcpy(header->aslc_id, ASLC_ID, 4);
588 header->aslc_revision = 1;
590 fadt->firmware_ctrl = (unsigned long)facs;
591 fadt->dsdt = (unsigned long)dsdt;
593 fadt->x_firmware_ctl_l = (unsigned long)facs;
594 fadt->x_firmware_ctl_h = 0;
595 fadt->x_dsdt_l = (unsigned long)dsdt;
598 fadt->preferred_pm_profile = ACPI_PM_MOBILE;
600 /* Use ACPI 3.0 revision */
601 fadt->header.revision = 4;
604 void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment,
607 struct dmar_entry *drhd = ctx->current;
609 memset(drhd, '\0', sizeof(*drhd));
610 drhd->type = DMAR_DRHD;
611 drhd->length = sizeof(*drhd); /* will be fixed up later */
613 drhd->segment = segment;
615 acpi_inc(ctx, drhd->length);
618 void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar,
621 struct dmar_rmrr_entry *rmrr = ctx->current;
623 memset(rmrr, '\0', sizeof(*rmrr));
624 rmrr->type = DMAR_RMRR;
625 rmrr->length = sizeof(*rmrr); /* will be fixed up later */
626 rmrr->segment = segment;
629 acpi_inc(ctx, rmrr->length);
632 void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base)
634 struct dmar_entry *drhd = base;
636 drhd->length = ctx->current - base;
639 void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base)
641 struct dmar_rmrr_entry *rmrr = base;
643 rmrr->length = ctx->current - base;
646 static int acpi_create_dmar_ds(struct acpi_ctx *ctx, enum dev_scope_type type,
647 uint enumeration_id, pci_dev_t bdf)
649 /* we don't support longer paths yet */
650 const size_t dev_scope_length = sizeof(struct dev_scope) + 2;
651 struct dev_scope *ds = ctx->current;
653 memset(ds, '\0', dev_scope_length);
655 ds->length = dev_scope_length;
656 ds->enumeration = enumeration_id;
657 ds->start_bus = PCI_BUS(bdf);
658 ds->path[0].dev = PCI_DEV(bdf);
659 ds->path[0].fn = PCI_FUNC(bdf);
664 int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf)
666 return acpi_create_dmar_ds(ctx, SCOPE_PCI_SUB, 0, bdf);
669 int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf)
671 return acpi_create_dmar_ds(ctx, SCOPE_PCI_ENDPOINT, 0, bdf);
674 int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id,
677 return acpi_create_dmar_ds(ctx, SCOPE_IOAPIC, enumeration_id, bdf);
680 int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id,
683 return acpi_create_dmar_ds(ctx, SCOPE_MSI_HPET, enumeration_id, bdf);