1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on acpi.c from coreboot
5 * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
6 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
9 #define LOG_CATEGORY LOGC_ACPI
16 #include <dm/uclass-internal.h>
19 #include <acpi/acpigen.h>
20 #include <acpi/acpi_device.h>
21 #include <acpi/acpi_table.h>
22 #include <asm/acpi/global_nvs.h>
23 #include <asm/ioapic.h>
24 #include <asm/global_data.h>
25 #include <asm/lapic.h>
26 #include <asm/mpspec.h>
27 #include <asm/tables.h>
28 #include <asm/arch/global_nvs.h>
30 #include <linux/err.h>
32 /* ACPI RSDP address to be used in boot parameters */
33 static ulong acpi_rsdp_addr;
35 static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
38 lapic->type = ACPI_APIC_LAPIC;
39 lapic->length = sizeof(struct acpi_madt_lapic);
40 lapic->flags = LOCAL_APIC_FLAG_ENABLED;
41 lapic->processor_id = cpu;
42 lapic->apic_id = apic;
47 int acpi_create_madt_lapics(u32 current)
53 for (uclass_find_first_device(UCLASS_CPU, &dev);
55 uclass_find_next_device(&dev)) {
56 struct cpu_plat *plat = dev_get_parent_plat(dev);
59 length = acpi_create_madt_lapic(
60 (struct acpi_madt_lapic *)current, cpu_num++,
63 total_length += length;
69 int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
70 u32 addr, u32 gsi_base)
72 ioapic->type = ACPI_APIC_IOAPIC;
73 ioapic->length = sizeof(struct acpi_madt_ioapic);
74 ioapic->reserved = 0x00;
75 ioapic->gsi_base = gsi_base;
76 ioapic->ioapic_id = id;
77 ioapic->ioapic_addr = addr;
79 return ioapic->length;
82 int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
83 u8 bus, u8 source, u32 gsirq, u16 flags)
85 irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE;
86 irqoverride->length = sizeof(struct acpi_madt_irqoverride);
87 irqoverride->bus = bus;
88 irqoverride->source = source;
89 irqoverride->gsirq = gsirq;
90 irqoverride->flags = flags;
92 return irqoverride->length;
95 int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
96 u8 cpu, u16 flags, u8 lint)
98 lapic_nmi->type = ACPI_APIC_LAPIC_NMI;
99 lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi);
100 lapic_nmi->flags = flags;
101 lapic_nmi->processor_id = cpu;
102 lapic_nmi->lint = lint;
104 return lapic_nmi->length;
107 static int acpi_create_madt_irq_overrides(u32 current)
109 struct acpi_madt_irqoverride *irqovr;
110 u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
113 irqovr = (void *)current;
114 length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
116 irqovr = (void *)(current + length);
117 length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
122 __weak u32 acpi_fill_madt(u32 current)
124 current += acpi_create_madt_lapics(current);
126 current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
127 io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
129 current += acpi_create_madt_irq_overrides(current);
134 int acpi_write_madt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
136 struct acpi_table_header *header;
137 struct acpi_madt *madt;
142 memset(madt, '\0', sizeof(struct acpi_madt));
143 header = &madt->header;
145 /* Fill out header fields */
146 acpi_fill_header(header, "APIC");
147 header->length = sizeof(struct acpi_madt);
148 header->revision = ACPI_MADT_REV_ACPI_3_0;
150 madt->lapic_addr = LAPIC_DEFAULT_BASE;
151 madt->flags = ACPI_MADT_PCAT_COMPAT;
153 current = (u32)madt + sizeof(struct acpi_madt);
154 current = acpi_fill_madt(current);
156 /* (Re)calculate length and checksum */
157 header->length = current - (u32)madt;
159 header->checksum = table_compute_checksum((void *)madt, header->length);
160 acpi_add_table(ctx, madt);
161 acpi_inc(ctx, madt->header.length);
165 ACPI_WRITER(5x86, NULL, acpi_write_madt, 0);
167 int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
168 u16 seg_nr, u8 start, u8 end)
170 memset(mmconfig, 0, sizeof(*mmconfig));
171 mmconfig->base_address_l = base;
172 mmconfig->base_address_h = 0;
173 mmconfig->pci_segment_group_number = seg_nr;
174 mmconfig->start_bus_number = start;
175 mmconfig->end_bus_number = end;
177 return sizeof(struct acpi_mcfg_mmconfig);
180 __weak u32 acpi_fill_mcfg(u32 current)
182 current += acpi_create_mcfg_mmconfig
183 ((struct acpi_mcfg_mmconfig *)current,
184 CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
190 * acpi_create_tcpa() - Create a TCPA table
192 * Trusted Computing Platform Alliance Capabilities Table
193 * TCPA PC Specific Implementation SpecificationTCPA is defined in the PCI
194 * Firmware Specification 3.0
196 int acpi_write_tcpa(struct acpi_ctx *ctx, const struct acpi_writer *entry)
198 struct acpi_table_header *header;
199 struct acpi_tcpa *tcpa;
201 int size = 0x10000; /* Use this as the default size */
205 if (!IS_ENABLED(CONFIG_TPM_V1))
207 if (!CONFIG_IS_ENABLED(BLOBLIST))
211 header = &tcpa->header;
212 memset(tcpa, '\0', sizeof(struct acpi_tcpa));
214 /* Fill out header fields */
215 acpi_fill_header(header, "TCPA");
216 header->length = sizeof(struct acpi_tcpa);
217 header->revision = 1;
219 ret = bloblist_ensure_size_ret(BLOBLISTT_TCPA_LOG, &size, &log);
221 return log_msg_ret("blob", ret);
223 tcpa->platform_class = 0;
225 tcpa->lasa = map_to_sysmem(log);
227 /* (Re)calculate length and checksum */
228 current = (u32)tcpa + sizeof(struct acpi_tcpa);
229 header->length = current - (u32)tcpa;
230 header->checksum = table_compute_checksum(tcpa, header->length);
232 acpi_inc(ctx, tcpa->header.length);
233 acpi_add_table(ctx, tcpa);
237 ACPI_WRITER(5tcpa, "TCPA", acpi_write_tcpa, 0);
239 static int get_tpm2_log(void **ptrp, int *sizep)
241 const int tpm2_default_log_len = 0x10000;
246 size = tpm2_default_log_len;
247 ret = bloblist_ensure_size_ret(BLOBLISTT_TPM2_TCG_LOG, &size, ptrp);
249 return log_msg_ret("blob", ret);
255 static int acpi_write_tpm2(struct acpi_ctx *ctx,
256 const struct acpi_writer *entry)
258 struct acpi_table_header *header;
259 struct acpi_tpm2 *tpm2;
264 if (!IS_ENABLED(CONFIG_TPM_V2))
265 return log_msg_ret("none", -ENOENT);
268 header = &tpm2->header;
269 memset(tpm2, '\0', sizeof(struct acpi_tpm2));
272 * Some payloads like SeaBIOS depend on log area to use TPM2.
273 * Get the memory size and address of TPM2 log area or initialize it.
275 ret = get_tpm2_log(&lasa, &tpm2_log_len);
277 return log_msg_ret("log", ret);
279 /* Fill out header fields. */
280 acpi_fill_header(header, "TPM2");
281 memcpy(header->aslc_id, ASLC_ID, 4);
283 header->length = sizeof(struct acpi_tpm2);
284 header->revision = acpi_get_table_revision(ACPITAB_TPM2);
286 /* Hard to detect for U-Boot. Just set it to 0 */
287 tpm2->platform_class = 0;
289 /* Must be set to 0 for FIFO-interface support */
290 tpm2->control_area = 0;
291 tpm2->start_method = 6;
292 memset(tpm2->msp, 0, sizeof(tpm2->msp));
294 /* Fill the log area size and start address fields. */
295 tpm2->laml = tpm2_log_len;
296 tpm2->lasa = map_to_sysmem(lasa);
298 /* Calculate checksum. */
299 header->checksum = table_compute_checksum(tpm2, header->length);
301 acpi_inc(ctx, tpm2->header.length);
302 acpi_add_table(ctx, tpm2);
306 ACPI_WRITER(5tpm2, "TPM2", acpi_write_tpm2, 0);
308 int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry)
310 struct serial_device_info serial_info = {0};
311 ulong serial_address, serial_offset;
312 struct acpi_table_header *header;
313 struct acpi_spcr *spcr;
322 header = &spcr->header;
324 memset(spcr, '\0', sizeof(struct acpi_spcr));
326 /* Fill out header fields */
327 acpi_fill_header(header, "SPCR");
328 header->length = sizeof(struct acpi_spcr);
329 header->revision = 2;
331 /* Read the device once, here. It is reused below */
332 dev = gd->cur_serial_dev;
334 ret = serial_getinfo(dev, &serial_info);
336 serial_info.type = SERIAL_CHIP_UNKNOWN;
338 /* Encode chip type */
339 switch (serial_info.type) {
340 case SERIAL_CHIP_16550_COMPATIBLE:
341 spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE;
343 case SERIAL_CHIP_UNKNOWN:
345 spcr->interface_type = ACPI_DBG2_UNKNOWN;
349 /* Encode address space */
350 switch (serial_info.addr_space) {
351 case SERIAL_ADDRESS_SPACE_MEMORY:
352 space_id = ACPI_ADDRESS_SPACE_MEMORY;
354 case SERIAL_ADDRESS_SPACE_IO:
356 space_id = ACPI_ADDRESS_SPACE_IO;
360 serial_width = serial_info.reg_width * 8;
361 serial_offset = serial_info.reg_offset << serial_info.reg_shift;
362 serial_address = serial_info.addr + serial_offset;
364 /* Encode register access size */
365 switch (serial_info.reg_shift) {
367 access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
370 access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
373 access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
376 access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;
379 access_size = ACPI_ACCESS_SIZE_UNDEFINED;
383 debug("UART type %u @ %lx\n", spcr->interface_type, serial_address);
386 spcr->serial_port.space_id = space_id;
387 spcr->serial_port.bit_width = serial_width;
388 spcr->serial_port.bit_offset = 0;
389 spcr->serial_port.access_size = access_size;
390 spcr->serial_port.addrl = lower_32_bits(serial_address);
391 spcr->serial_port.addrh = upper_32_bits(serial_address);
393 /* Encode baud rate */
394 switch (serial_info.baudrate) {
412 serial_config = SERIAL_DEFAULT_CONFIG;
414 ret = serial_getconfig(dev, &serial_config);
416 spcr->parity = SERIAL_GET_PARITY(serial_config);
417 spcr->stop_bits = SERIAL_GET_STOP(serial_config);
419 /* No PCI devices for now */
420 spcr->pci_device_id = 0xffff;
421 spcr->pci_vendor_id = 0xffff;
424 * SPCR has no clue if the UART base clock speed is different
425 * to the default one. However, the SPCR 1.04 defines baud rate
426 * 0 as a preconfigured state of UART and OS is supposed not
427 * to touch the configuration of the serial device.
429 if (serial_info.clock != SERIAL_DEFAULT_CLOCK)
433 header->checksum = table_compute_checksum((void *)spcr, header->length);
435 acpi_add_table(ctx, spcr);
436 acpi_inc(ctx, spcr->header.length);
440 ACPI_WRITER(5spcr, "SPCR", acpi_write_spcr, 0);
442 int acpi_write_gnvs(struct acpi_ctx *ctx, const struct acpi_writer *entry)
446 if (!IS_ENABLED(CONFIG_ACPI_GNVS_EXTERNAL)) {
449 /* We need the DSDT to be done */
451 return log_msg_ret("dsdt", -EAGAIN);
453 /* Pack GNVS into the ACPI table area */
454 for (i = 0; i < ctx->dsdt->length; i++) {
455 u32 *gnvs = (u32 *)((u32)ctx->dsdt + i);
457 if (*gnvs == ACPI_GNVS_ADDR) {
458 *gnvs = map_to_sysmem(ctx->current);
459 log_debug("Fix up global NVS in DSDT to %#08x\n",
466 * Recalculate the length and update the DSDT checksum since we
467 * patched the GNVS address. Set the checksum to zero since it
468 * is part of the region being checksummed.
470 ctx->dsdt->checksum = 0;
471 ctx->dsdt->checksum = table_compute_checksum((void *)ctx->dsdt,
475 /* Fill in platform-specific global NVS variables */
476 addr = acpi_create_gnvs(ctx->current);
477 if (IS_ERR_VALUE(addr))
478 return log_msg_ret("gnvs", (int)addr);
480 acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));
484 ACPI_WRITER(4gnvs, "GNVS", acpi_write_gnvs, 0);
486 /* MCFG is defined in the PCI Firmware Specification 3.0 */
487 int acpi_write_mcfg(struct acpi_ctx *ctx, const struct acpi_writer *entry)
489 struct acpi_table_header *header;
490 struct acpi_mcfg *mcfg;
494 header = &mcfg->header;
496 current = (u32)mcfg + sizeof(struct acpi_mcfg);
498 memset(mcfg, '\0', sizeof(struct acpi_mcfg));
500 /* Fill out header fields */
501 acpi_fill_header(header, "MCFG");
502 header->length = sizeof(struct acpi_mcfg);
503 header->revision = 1;
505 /* (Re)calculate length and checksum */
506 header->length = current - (u32)mcfg;
507 header->checksum = table_compute_checksum(mcfg, header->length);
509 acpi_inc(ctx, mcfg->header.length);
510 acpi_add_table(ctx, mcfg);
514 ACPI_WRITER(5mcfg, "MCFG", acpi_write_mcfg, 0);
517 * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c
519 int write_acpi_tables_x86(struct acpi_ctx *ctx,
520 const struct acpi_writer *entry)
522 acpi_write_dev_tables(ctx);
524 acpi_rsdp_addr = (unsigned long)ctx->rsdp;
525 debug("ACPI: done\n");
529 ACPI_WRITER(9x86, NULL, write_acpi_tables_x86, 0);
531 ulong acpi_get_rsdp_addr(void)
533 return acpi_rsdp_addr;
537 * acpi_write_hpet() - Write out a HPET table
539 * Write out the table for High-Precision Event Timers
541 * @hpet: Place to put HPET table
543 static int acpi_create_hpet(struct acpi_hpet *hpet)
545 struct acpi_table_header *header = &hpet->header;
546 struct acpi_gen_regaddr *addr = &hpet->addr;
549 * See IA-PC HPET (High Precision Event Timers) Specification v1.0a
550 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/software-developers-hpet-spec-1-0a.pdf
552 memset((void *)hpet, '\0', sizeof(struct acpi_hpet));
554 /* Fill out header fields. */
555 acpi_fill_header(header, "HPET");
557 header->aslc_revision = ASL_REVISION;
558 header->length = sizeof(struct acpi_hpet);
559 header->revision = acpi_get_table_revision(ACPITAB_HPET);
561 /* Fill out HPET address */
562 addr->space_id = 0; /* Memory */
563 addr->bit_width = 64;
564 addr->bit_offset = 0;
565 addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff;
566 addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32;
568 hpet->id = *(u32 *)CONFIG_HPET_ADDRESS;
570 hpet->min_tick = 0; /* HPET_MIN_TICKS */
572 header->checksum = table_compute_checksum(hpet,
573 sizeof(struct acpi_hpet));
578 int acpi_write_hpet(struct acpi_ctx *ctx)
580 struct acpi_hpet *hpet;
583 log_debug("ACPI: * HPET\n");
586 acpi_inc_align(ctx, sizeof(struct acpi_hpet));
587 acpi_create_hpet(hpet);
588 ret = acpi_add_table(ctx, hpet);
590 return log_msg_ret("add", ret);
595 int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
598 struct acpi_dbg2_header *dbg2 = ctx->current;
599 char path[ACPI_PATH_MAX];
600 struct acpi_gen_regaddr address;
604 if (!device_active(dev)) {
605 log_info("Device not enabled\n");
609 * PCI devices don't remember their resource allocation information in
610 * U-Boot at present. We assume that MMIO is used for the UART and that
611 * the address space is 32 bytes: ns16550 uses 8 registers of up to
612 * 32-bits each. This is only for debugging so it is not a big deal.
614 addr = dm_pci_read_bar32(dev, 0);
615 log_debug("UART addr %lx\n", (ulong)addr);
617 memset(&address, '\0', sizeof(address));
618 address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
619 address.addrl = (uint32_t)addr;
620 address.addrh = (uint32_t)((addr >> 32) & 0xffffffff);
621 address.access_size = access_size;
623 ret = acpi_device_path(dev, path, sizeof(path));
625 return log_msg_ret("path", ret);
626 acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
627 ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);
629 acpi_inc_align(ctx, dbg2->header.length);
630 acpi_add_table(ctx, dbg2);
635 void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
638 struct acpi_table_header *header = &fadt->header;
640 memset((void *)fadt, '\0', sizeof(struct acpi_fadt));
642 acpi_fill_header(header, "FACP");
643 header->length = sizeof(struct acpi_fadt);
644 header->revision = 4;
645 memcpy(header->oem_id, OEM_ID, 6);
646 memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
647 memcpy(header->aslc_id, ASLC_ID, 4);
648 header->aslc_revision = 1;
650 fadt->firmware_ctrl = (unsigned long)facs;
651 fadt->dsdt = (unsigned long)dsdt;
653 fadt->x_firmware_ctl_l = (unsigned long)facs;
654 fadt->x_firmware_ctl_h = 0;
655 fadt->x_dsdt_l = (unsigned long)dsdt;
658 fadt->preferred_pm_profile = ACPI_PM_MOBILE;
660 /* Use ACPI 3.0 revision */
661 fadt->header.revision = 4;
664 void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment,
667 struct dmar_entry *drhd = ctx->current;
669 memset(drhd, '\0', sizeof(*drhd));
670 drhd->type = DMAR_DRHD;
671 drhd->length = sizeof(*drhd); /* will be fixed up later */
673 drhd->segment = segment;
675 acpi_inc(ctx, drhd->length);
678 void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar,
681 struct dmar_rmrr_entry *rmrr = ctx->current;
683 memset(rmrr, '\0', sizeof(*rmrr));
684 rmrr->type = DMAR_RMRR;
685 rmrr->length = sizeof(*rmrr); /* will be fixed up later */
686 rmrr->segment = segment;
689 acpi_inc(ctx, rmrr->length);
692 void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base)
694 struct dmar_entry *drhd = base;
696 drhd->length = ctx->current - base;
699 void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base)
701 struct dmar_rmrr_entry *rmrr = base;
703 rmrr->length = ctx->current - base;
706 static int acpi_create_dmar_ds(struct acpi_ctx *ctx, enum dev_scope_type type,
707 uint enumeration_id, pci_dev_t bdf)
709 /* we don't support longer paths yet */
710 const size_t dev_scope_length = sizeof(struct dev_scope) + 2;
711 struct dev_scope *ds = ctx->current;
713 memset(ds, '\0', dev_scope_length);
715 ds->length = dev_scope_length;
716 ds->enumeration = enumeration_id;
717 ds->start_bus = PCI_BUS(bdf);
718 ds->path[0].dev = PCI_DEV(bdf);
719 ds->path[0].fn = PCI_FUNC(bdf);
724 int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf)
726 return acpi_create_dmar_ds(ctx, SCOPE_PCI_SUB, 0, bdf);
729 int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf)
731 return acpi_create_dmar_ds(ctx, SCOPE_PCI_ENDPOINT, 0, bdf);
734 int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id,
737 return acpi_create_dmar_ds(ctx, SCOPE_IOAPIC, enumeration_id, bdf);
740 int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id,
743 return acpi_create_dmar_ds(ctx, SCOPE_MSI_HPET, enumeration_id, bdf);