1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on acpi.c from coreboot
5 * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
6 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
9 #define LOG_CATEGORY LOGC_ACPI
16 #include <dm/uclass-internal.h>
19 #include <acpi/acpigen.h>
20 #include <acpi/acpi_device.h>
21 #include <acpi/acpi_table.h>
22 #include <asm/acpi/global_nvs.h>
23 #include <asm/ioapic.h>
24 #include <asm/global_data.h>
25 #include <asm/lapic.h>
26 #include <asm/mpspec.h>
27 #include <asm/tables.h>
28 #include <asm/arch/global_nvs.h>
30 #include <linux/err.h>
32 /* ACPI RSDP address to be used in boot parameters */
33 static ulong acpi_rsdp_addr;
35 static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
38 lapic->type = ACPI_APIC_LAPIC;
39 lapic->length = sizeof(struct acpi_madt_lapic);
40 lapic->flags = LOCAL_APIC_FLAG_ENABLED;
41 lapic->processor_id = cpu;
42 lapic->apic_id = apic;
47 int acpi_create_madt_lapics(u32 current)
53 for (uclass_find_first_device(UCLASS_CPU, &dev);
55 uclass_find_next_device(&dev)) {
56 struct cpu_plat *plat = dev_get_parent_plat(dev);
59 length = acpi_create_madt_lapic(
60 (struct acpi_madt_lapic *)current, cpu_num++,
63 total_length += length;
69 int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
70 u32 addr, u32 gsi_base)
72 ioapic->type = ACPI_APIC_IOAPIC;
73 ioapic->length = sizeof(struct acpi_madt_ioapic);
74 ioapic->reserved = 0x00;
75 ioapic->gsi_base = gsi_base;
76 ioapic->ioapic_id = id;
77 ioapic->ioapic_addr = addr;
79 return ioapic->length;
82 int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
83 u8 bus, u8 source, u32 gsirq, u16 flags)
85 irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE;
86 irqoverride->length = sizeof(struct acpi_madt_irqoverride);
87 irqoverride->bus = bus;
88 irqoverride->source = source;
89 irqoverride->gsirq = gsirq;
90 irqoverride->flags = flags;
92 return irqoverride->length;
95 int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
96 u8 cpu, u16 flags, u8 lint)
98 lapic_nmi->type = ACPI_APIC_LAPIC_NMI;
99 lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi);
100 lapic_nmi->flags = flags;
101 lapic_nmi->processor_id = cpu;
102 lapic_nmi->lint = lint;
104 return lapic_nmi->length;
107 static int acpi_create_madt_irq_overrides(u32 current)
109 struct acpi_madt_irqoverride *irqovr;
110 u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
113 irqovr = (void *)current;
114 length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
116 irqovr = (void *)(current + length);
117 length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
122 __weak u32 acpi_fill_madt(u32 current)
124 current += acpi_create_madt_lapics(current);
126 current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
127 io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
129 current += acpi_create_madt_irq_overrides(current);
134 static void acpi_create_madt(struct acpi_madt *madt)
136 struct acpi_table_header *header = &(madt->header);
137 u32 current = (u32)madt + sizeof(struct acpi_madt);
139 memset((void *)madt, 0, sizeof(struct acpi_madt));
141 /* Fill out header fields */
142 acpi_fill_header(header, "APIC");
143 header->length = sizeof(struct acpi_madt);
144 header->revision = ACPI_MADT_REV_ACPI_3_0;
146 madt->lapic_addr = LAPIC_DEFAULT_BASE;
147 madt->flags = ACPI_MADT_PCAT_COMPAT;
149 current = acpi_fill_madt(current);
151 /* (Re)calculate length and checksum */
152 header->length = current - (u32)madt;
154 header->checksum = table_compute_checksum((void *)madt, header->length);
157 int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
158 u16 seg_nr, u8 start, u8 end)
160 memset(mmconfig, 0, sizeof(*mmconfig));
161 mmconfig->base_address_l = base;
162 mmconfig->base_address_h = 0;
163 mmconfig->pci_segment_group_number = seg_nr;
164 mmconfig->start_bus_number = start;
165 mmconfig->end_bus_number = end;
167 return sizeof(struct acpi_mcfg_mmconfig);
170 __weak u32 acpi_fill_mcfg(u32 current)
172 current += acpi_create_mcfg_mmconfig
173 ((struct acpi_mcfg_mmconfig *)current,
174 CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
180 * acpi_create_tcpa() - Create a TCPA table
182 * @tcpa: Pointer to place to put table
184 * Trusted Computing Platform Alliance Capabilities Table
185 * TCPA PC Specific Implementation SpecificationTCPA is defined in the PCI
186 * Firmware Specification 3.0
188 static int acpi_create_tcpa(struct acpi_tcpa *tcpa)
190 struct acpi_table_header *header = &tcpa->header;
191 u32 current = (u32)tcpa + sizeof(struct acpi_tcpa);
192 int size = 0x10000; /* Use this as the default size */
196 if (!CONFIG_IS_ENABLED(BLOBLIST))
198 memset(tcpa, '\0', sizeof(struct acpi_tcpa));
200 /* Fill out header fields */
201 acpi_fill_header(header, "TCPA");
202 header->length = sizeof(struct acpi_tcpa);
203 header->revision = 1;
205 ret = bloblist_ensure_size_ret(BLOBLISTT_TCPA_LOG, &size, &log);
207 return log_msg_ret("blob", ret);
209 tcpa->platform_class = 0;
211 tcpa->lasa = (ulong)log;
213 /* (Re)calculate length and checksum */
214 header->length = current - (u32)tcpa;
215 header->checksum = table_compute_checksum((void *)tcpa, header->length);
220 static int get_tpm2_log(void **ptrp, int *sizep)
222 const int tpm2_default_log_len = 0x10000;
227 size = tpm2_default_log_len;
228 ret = bloblist_ensure_size_ret(BLOBLISTT_TPM2_TCG_LOG, &size, ptrp);
230 return log_msg_ret("blob", ret);
236 static int acpi_write_tpm2(struct acpi_ctx *ctx,
237 const struct acpi_writer *entry)
239 struct acpi_table_header *header;
240 struct acpi_tpm2 *tpm2;
245 if (!IS_ENABLED(CONFIG_TPM_V2))
246 return log_msg_ret("none", -ENOENT);
249 header = &tpm2->header;
250 memset(tpm2, '\0', sizeof(struct acpi_tpm2));
253 * Some payloads like SeaBIOS depend on log area to use TPM2.
254 * Get the memory size and address of TPM2 log area or initialize it.
256 ret = get_tpm2_log(&lasa, &tpm2_log_len);
258 return log_msg_ret("log", ret);
260 /* Fill out header fields. */
261 acpi_fill_header(header, "TPM2");
262 memcpy(header->aslc_id, ASLC_ID, 4);
264 header->length = sizeof(struct acpi_tpm2);
265 header->revision = acpi_get_table_revision(ACPITAB_TPM2);
267 /* Hard to detect for U-Boot. Just set it to 0 */
268 tpm2->platform_class = 0;
270 /* Must be set to 0 for FIFO-interface support */
271 tpm2->control_area = 0;
272 tpm2->start_method = 6;
273 memset(tpm2->msp, 0, sizeof(tpm2->msp));
275 /* Fill the log area size and start address fields. */
276 tpm2->laml = tpm2_log_len;
277 tpm2->lasa = map_to_sysmem(lasa);
279 /* Calculate checksum. */
280 header->checksum = table_compute_checksum(tpm2, header->length);
282 acpi_inc(ctx, tpm2->header.length);
283 acpi_add_table(ctx, tpm2);
287 ACPI_WRITER(5tpm2, "TPM2", acpi_write_tpm2, 0);
289 __weak u32 acpi_fill_csrt(u32 current)
294 static int acpi_create_csrt(struct acpi_csrt *csrt)
296 struct acpi_table_header *header = &(csrt->header);
297 u32 current = (u32)csrt + sizeof(struct acpi_csrt);
300 memset((void *)csrt, 0, sizeof(struct acpi_csrt));
302 /* Fill out header fields */
303 acpi_fill_header(header, "CSRT");
304 header->length = sizeof(struct acpi_csrt);
305 header->revision = 0;
307 ptr = acpi_fill_csrt(current);
312 /* (Re)calculate length and checksum */
313 header->length = current - (u32)csrt;
314 header->checksum = table_compute_checksum((void *)csrt, header->length);
319 static void acpi_create_spcr(struct acpi_spcr *spcr)
321 struct acpi_table_header *header = &(spcr->header);
322 struct serial_device_info serial_info = {0};
323 ulong serial_address, serial_offset;
331 memset((void *)spcr, 0, sizeof(struct acpi_spcr));
333 /* Fill out header fields */
334 acpi_fill_header(header, "SPCR");
335 header->length = sizeof(struct acpi_spcr);
336 header->revision = 2;
338 /* Read the device once, here. It is reused below */
339 dev = gd->cur_serial_dev;
341 ret = serial_getinfo(dev, &serial_info);
343 serial_info.type = SERIAL_CHIP_UNKNOWN;
345 /* Encode chip type */
346 switch (serial_info.type) {
347 case SERIAL_CHIP_16550_COMPATIBLE:
348 spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE;
350 case SERIAL_CHIP_UNKNOWN:
352 spcr->interface_type = ACPI_DBG2_UNKNOWN;
356 /* Encode address space */
357 switch (serial_info.addr_space) {
358 case SERIAL_ADDRESS_SPACE_MEMORY:
359 space_id = ACPI_ADDRESS_SPACE_MEMORY;
361 case SERIAL_ADDRESS_SPACE_IO:
363 space_id = ACPI_ADDRESS_SPACE_IO;
367 serial_width = serial_info.reg_width * 8;
368 serial_offset = serial_info.reg_offset << serial_info.reg_shift;
369 serial_address = serial_info.addr + serial_offset;
371 /* Encode register access size */
372 switch (serial_info.reg_shift) {
374 access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
377 access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
380 access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
383 access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;
386 access_size = ACPI_ACCESS_SIZE_UNDEFINED;
390 debug("UART type %u @ %lx\n", spcr->interface_type, serial_address);
393 spcr->serial_port.space_id = space_id;
394 spcr->serial_port.bit_width = serial_width;
395 spcr->serial_port.bit_offset = 0;
396 spcr->serial_port.access_size = access_size;
397 spcr->serial_port.addrl = lower_32_bits(serial_address);
398 spcr->serial_port.addrh = upper_32_bits(serial_address);
400 /* Encode baud rate */
401 switch (serial_info.baudrate) {
419 serial_config = SERIAL_DEFAULT_CONFIG;
421 ret = serial_getconfig(dev, &serial_config);
423 spcr->parity = SERIAL_GET_PARITY(serial_config);
424 spcr->stop_bits = SERIAL_GET_STOP(serial_config);
426 /* No PCI devices for now */
427 spcr->pci_device_id = 0xffff;
428 spcr->pci_vendor_id = 0xffff;
431 * SPCR has no clue if the UART base clock speed is different
432 * to the default one. However, the SPCR 1.04 defines baud rate
433 * 0 as a preconfigured state of UART and OS is supposed not
434 * to touch the configuration of the serial device.
436 if (serial_info.clock != SERIAL_DEFAULT_CLOCK)
440 header->checksum = table_compute_checksum((void *)spcr, header->length);
443 int acpi_write_gnvs(struct acpi_ctx *ctx, const struct acpi_writer *entry)
447 if (!IS_ENABLED(CONFIG_ACPI_GNVS_EXTERNAL)) {
450 /* We need the DSDT to be done */
452 return log_msg_ret("dsdt", -EAGAIN);
454 /* Pack GNVS into the ACPI table area */
455 for (i = 0; i < ctx->dsdt->length; i++) {
456 u32 *gnvs = (u32 *)((u32)ctx->dsdt + i);
458 if (*gnvs == ACPI_GNVS_ADDR) {
459 *gnvs = map_to_sysmem(ctx->current);
460 log_debug("Fix up global NVS in DSDT to %#08x\n",
467 * Recalculate the length and update the DSDT checksum since we
468 * patched the GNVS address. Set the checksum to zero since it
469 * is part of the region being checksummed.
471 ctx->dsdt->checksum = 0;
472 ctx->dsdt->checksum = table_compute_checksum((void *)ctx->dsdt,
476 /* Fill in platform-specific global NVS variables */
477 addr = acpi_create_gnvs(ctx->current);
478 if (IS_ERR_VALUE(addr))
479 return log_msg_ret("gnvs", (int)addr);
481 acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));
485 ACPI_WRITER(4gnvs, "GNVS", acpi_write_gnvs, 0);
487 /* MCFG is defined in the PCI Firmware Specification 3.0 */
488 int acpi_write_mcfg(struct acpi_ctx *ctx, const struct acpi_writer *entry)
490 struct acpi_table_header *header;
491 struct acpi_mcfg *mcfg;
495 header = &mcfg->header;
497 current = (u32)mcfg + sizeof(struct acpi_mcfg);
499 memset(mcfg, '\0', sizeof(struct acpi_mcfg));
501 /* Fill out header fields */
502 acpi_fill_header(header, "MCFG");
503 header->length = sizeof(struct acpi_mcfg);
504 header->revision = 1;
506 /* (Re)calculate length and checksum */
507 header->length = current - (u32)mcfg;
508 header->checksum = table_compute_checksum(mcfg, header->length);
510 acpi_inc(ctx, mcfg->header.length);
511 acpi_add_table(ctx, mcfg);
515 ACPI_WRITER(5mcfg, "MCFG", acpi_write_mcfg, 0);
518 * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c
520 int write_acpi_tables_x86(struct acpi_ctx *ctx,
521 const struct acpi_writer *entry)
523 struct acpi_tcpa *tcpa;
524 struct acpi_madt *madt;
525 struct acpi_csrt *csrt;
526 struct acpi_spcr *spcr;
529 debug("ACPI: * MADT\n");
531 acpi_create_madt(madt);
532 acpi_inc_align(ctx, madt->header.length);
533 acpi_add_table(ctx, madt);
535 if (IS_ENABLED(CONFIG_TPM_V1)) {
536 debug("ACPI: * TCPA\n");
537 tcpa = (struct acpi_tcpa *)ctx->current;
538 ret = acpi_create_tcpa(tcpa);
540 log_warning("Failed to create TCPA table (err=%d)\n",
543 acpi_inc_align(ctx, tcpa->header.length);
544 acpi_add_table(ctx, tcpa);
548 debug("ACPI: * CSRT\n");
550 if (!acpi_create_csrt(csrt)) {
551 acpi_inc_align(ctx, csrt->header.length);
552 acpi_add_table(ctx, csrt);
555 debug("ACPI: * SPCR\n");
557 acpi_create_spcr(spcr);
558 acpi_inc_align(ctx, spcr->header.length);
559 acpi_add_table(ctx, spcr);
561 acpi_write_dev_tables(ctx);
563 acpi_rsdp_addr = (unsigned long)ctx->rsdp;
564 debug("ACPI: done\n");
568 ACPI_WRITER(9x86, NULL, write_acpi_tables_x86, 0);
570 ulong acpi_get_rsdp_addr(void)
572 return acpi_rsdp_addr;
576 * acpi_write_hpet() - Write out a HPET table
578 * Write out the table for High-Precision Event Timers
580 * @hpet: Place to put HPET table
582 static int acpi_create_hpet(struct acpi_hpet *hpet)
584 struct acpi_table_header *header = &hpet->header;
585 struct acpi_gen_regaddr *addr = &hpet->addr;
588 * See IA-PC HPET (High Precision Event Timers) Specification v1.0a
589 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/software-developers-hpet-spec-1-0a.pdf
591 memset((void *)hpet, '\0', sizeof(struct acpi_hpet));
593 /* Fill out header fields. */
594 acpi_fill_header(header, "HPET");
596 header->aslc_revision = ASL_REVISION;
597 header->length = sizeof(struct acpi_hpet);
598 header->revision = acpi_get_table_revision(ACPITAB_HPET);
600 /* Fill out HPET address */
601 addr->space_id = 0; /* Memory */
602 addr->bit_width = 64;
603 addr->bit_offset = 0;
604 addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff;
605 addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32;
607 hpet->id = *(u32 *)CONFIG_HPET_ADDRESS;
609 hpet->min_tick = 0; /* HPET_MIN_TICKS */
611 header->checksum = table_compute_checksum(hpet,
612 sizeof(struct acpi_hpet));
617 int acpi_write_hpet(struct acpi_ctx *ctx)
619 struct acpi_hpet *hpet;
622 log_debug("ACPI: * HPET\n");
625 acpi_inc_align(ctx, sizeof(struct acpi_hpet));
626 acpi_create_hpet(hpet);
627 ret = acpi_add_table(ctx, hpet);
629 return log_msg_ret("add", ret);
634 int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
637 struct acpi_dbg2_header *dbg2 = ctx->current;
638 char path[ACPI_PATH_MAX];
639 struct acpi_gen_regaddr address;
643 if (!device_active(dev)) {
644 log_info("Device not enabled\n");
648 * PCI devices don't remember their resource allocation information in
649 * U-Boot at present. We assume that MMIO is used for the UART and that
650 * the address space is 32 bytes: ns16550 uses 8 registers of up to
651 * 32-bits each. This is only for debugging so it is not a big deal.
653 addr = dm_pci_read_bar32(dev, 0);
654 log_debug("UART addr %lx\n", (ulong)addr);
656 memset(&address, '\0', sizeof(address));
657 address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
658 address.addrl = (uint32_t)addr;
659 address.addrh = (uint32_t)((addr >> 32) & 0xffffffff);
660 address.access_size = access_size;
662 ret = acpi_device_path(dev, path, sizeof(path));
664 return log_msg_ret("path", ret);
665 acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
666 ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);
668 acpi_inc_align(ctx, dbg2->header.length);
669 acpi_add_table(ctx, dbg2);
674 void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
677 struct acpi_table_header *header = &fadt->header;
679 memset((void *)fadt, '\0', sizeof(struct acpi_fadt));
681 acpi_fill_header(header, "FACP");
682 header->length = sizeof(struct acpi_fadt);
683 header->revision = 4;
684 memcpy(header->oem_id, OEM_ID, 6);
685 memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
686 memcpy(header->aslc_id, ASLC_ID, 4);
687 header->aslc_revision = 1;
689 fadt->firmware_ctrl = (unsigned long)facs;
690 fadt->dsdt = (unsigned long)dsdt;
692 fadt->x_firmware_ctl_l = (unsigned long)facs;
693 fadt->x_firmware_ctl_h = 0;
694 fadt->x_dsdt_l = (unsigned long)dsdt;
697 fadt->preferred_pm_profile = ACPI_PM_MOBILE;
699 /* Use ACPI 3.0 revision */
700 fadt->header.revision = 4;
703 void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment,
706 struct dmar_entry *drhd = ctx->current;
708 memset(drhd, '\0', sizeof(*drhd));
709 drhd->type = DMAR_DRHD;
710 drhd->length = sizeof(*drhd); /* will be fixed up later */
712 drhd->segment = segment;
714 acpi_inc(ctx, drhd->length);
717 void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar,
720 struct dmar_rmrr_entry *rmrr = ctx->current;
722 memset(rmrr, '\0', sizeof(*rmrr));
723 rmrr->type = DMAR_RMRR;
724 rmrr->length = sizeof(*rmrr); /* will be fixed up later */
725 rmrr->segment = segment;
728 acpi_inc(ctx, rmrr->length);
731 void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base)
733 struct dmar_entry *drhd = base;
735 drhd->length = ctx->current - base;
738 void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base)
740 struct dmar_rmrr_entry *rmrr = base;
742 rmrr->length = ctx->current - base;
745 static int acpi_create_dmar_ds(struct acpi_ctx *ctx, enum dev_scope_type type,
746 uint enumeration_id, pci_dev_t bdf)
748 /* we don't support longer paths yet */
749 const size_t dev_scope_length = sizeof(struct dev_scope) + 2;
750 struct dev_scope *ds = ctx->current;
752 memset(ds, '\0', dev_scope_length);
754 ds->length = dev_scope_length;
755 ds->enumeration = enumeration_id;
756 ds->start_bus = PCI_BUS(bdf);
757 ds->path[0].dev = PCI_DEV(bdf);
758 ds->path[0].fn = PCI_FUNC(bdf);
763 int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf)
765 return acpi_create_dmar_ds(ctx, SCOPE_PCI_SUB, 0, bdf);
768 int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf)
770 return acpi_create_dmar_ds(ctx, SCOPE_PCI_ENDPOINT, 0, bdf);
773 int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id,
776 return acpi_create_dmar_ds(ctx, SCOPE_IOAPIC, enumeration_id, bdf);
779 int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id,
782 return acpi_create_dmar_ds(ctx, SCOPE_MSI_HPET, enumeration_id, bdf);