2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
53 #define CREATE_TRACE_POINTS
56 #include <asm/debugreg.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32 kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109 #define KVM_NR_SHARED_MSRS 16
111 struct kvm_shared_msrs_global {
113 u32 msrs[KVM_NR_SHARED_MSRS];
116 struct kvm_shared_msrs {
117 struct user_return_notifier urn;
119 struct kvm_shared_msr_values {
122 } values[KVM_NR_SHARED_MSRS];
125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
126 static struct kvm_shared_msrs __percpu *shared_msrs;
128 struct kvm_stats_debugfs_item debugfs_entries[] = {
129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
141 { "hypercalls", VCPU_STAT(hypercalls) },
142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
149 { "irq_injections", VCPU_STAT(irq_injections) },
150 { "nmi_injections", VCPU_STAT(nmi_injections) },
151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
158 { "mmu_unsync", VM_STAT(mmu_unsync) },
159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
160 { "largepages", VM_STAT(lpages) },
164 u64 __read_mostly host_xcr0;
166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
175 static void kvm_on_user_return(struct user_return_notifier *urn)
178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
180 struct kvm_shared_msr_values *values;
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
193 static void shared_msr_update(unsigned slot, u32 msr)
196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
210 void kvm_define_shared_msr(unsigned slot, u32 msr)
212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
220 static void kvm_shared_msr_cpu_online(void)
224 for (i = 0; i < shared_msrs_global.nr; ++i)
225 shared_msr_update(i, shared_msrs_global.msrs[i]);
228 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
234 if (((value ^ smsr->values[slot].curr) & mask) == 0)
236 smsr->values[slot].curr = value;
237 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
241 if (!smsr->registered) {
242 smsr->urn.on_user_return = kvm_on_user_return;
243 user_return_notifier_register(&smsr->urn);
244 smsr->registered = true;
248 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
250 static void drop_user_return_notifiers(void *ignore)
252 unsigned int cpu = smp_processor_id();
253 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
255 if (smsr->registered)
256 kvm_on_user_return(&smsr->urn);
259 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
261 return vcpu->arch.apic_base;
263 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
265 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
267 u64 old_state = vcpu->arch.apic_base &
268 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
269 u64 new_state = msr_info->data &
270 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
271 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
272 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
274 if (!msr_info->host_initiated &&
275 ((msr_info->data & reserved_bits) != 0 ||
276 new_state == X2APIC_ENABLE ||
277 (new_state == MSR_IA32_APICBASE_ENABLE &&
278 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
279 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
283 kvm_lapic_set_base(vcpu, msr_info->data);
286 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
288 asmlinkage void kvm_spurious_fault(void)
290 /* Fault while not rebooting. We want the trace. */
293 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
295 #define EXCPT_BENIGN 0
296 #define EXCPT_CONTRIBUTORY 1
299 static int exception_class(int vector)
309 return EXCPT_CONTRIBUTORY;
316 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
317 unsigned nr, bool has_error, u32 error_code,
323 kvm_make_request(KVM_REQ_EVENT, vcpu);
325 if (!vcpu->arch.exception.pending) {
327 vcpu->arch.exception.pending = true;
328 vcpu->arch.exception.has_error_code = has_error;
329 vcpu->arch.exception.nr = nr;
330 vcpu->arch.exception.error_code = error_code;
331 vcpu->arch.exception.reinject = reinject;
335 /* to check exception */
336 prev_nr = vcpu->arch.exception.nr;
337 if (prev_nr == DF_VECTOR) {
338 /* triple fault -> shutdown */
339 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
342 class1 = exception_class(prev_nr);
343 class2 = exception_class(nr);
344 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
345 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
346 /* generate double fault per SDM Table 5-5 */
347 vcpu->arch.exception.pending = true;
348 vcpu->arch.exception.has_error_code = true;
349 vcpu->arch.exception.nr = DF_VECTOR;
350 vcpu->arch.exception.error_code = 0;
352 /* replace previous exception with a new one in a hope
353 that instruction re-execution will regenerate lost
358 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360 kvm_multiple_exception(vcpu, nr, false, 0, false);
362 EXPORT_SYMBOL_GPL(kvm_queue_exception);
364 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
366 kvm_multiple_exception(vcpu, nr, false, 0, true);
368 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
370 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
373 kvm_inject_gp(vcpu, 0);
375 kvm_x86_ops->skip_emulated_instruction(vcpu);
377 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
379 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
381 ++vcpu->stat.pf_guest;
382 vcpu->arch.cr2 = fault->address;
383 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
385 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
387 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
389 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
390 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
392 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
395 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
397 atomic_inc(&vcpu->arch.nmi_queued);
398 kvm_make_request(KVM_REQ_NMI, vcpu);
400 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
402 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404 kvm_multiple_exception(vcpu, nr, true, error_code, false);
406 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
408 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
410 kvm_multiple_exception(vcpu, nr, true, error_code, true);
412 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
415 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
416 * a #GP and return false.
418 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
420 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
422 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
425 EXPORT_SYMBOL_GPL(kvm_require_cpl);
428 * This function will be used to read from the physical memory of the currently
429 * running guest. The difference to kvm_read_guest_page is that this function
430 * can read from guest physical or from the guest's guest physical memory.
432 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
433 gfn_t ngfn, void *data, int offset, int len,
439 ngpa = gfn_to_gpa(ngfn);
440 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
441 if (real_gfn == UNMAPPED_GVA)
444 real_gfn = gpa_to_gfn(real_gfn);
446 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
448 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
450 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
451 void *data, int offset, int len, u32 access)
453 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
454 data, offset, len, access);
458 * Load the pae pdptrs. Return true is they are all valid.
460 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
462 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
463 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
466 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
468 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
469 offset * sizeof(u64), sizeof(pdpte),
470 PFERR_USER_MASK|PFERR_WRITE_MASK);
475 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
476 if (is_present_gpte(pdpte[i]) &&
477 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
484 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
485 __set_bit(VCPU_EXREG_PDPTR,
486 (unsigned long *)&vcpu->arch.regs_avail);
487 __set_bit(VCPU_EXREG_PDPTR,
488 (unsigned long *)&vcpu->arch.regs_dirty);
493 EXPORT_SYMBOL_GPL(load_pdptrs);
495 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
497 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
503 if (is_long_mode(vcpu) || !is_pae(vcpu))
506 if (!test_bit(VCPU_EXREG_PDPTR,
507 (unsigned long *)&vcpu->arch.regs_avail))
510 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
511 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
512 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
513 PFERR_USER_MASK | PFERR_WRITE_MASK);
516 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
522 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
524 unsigned long old_cr0 = kvm_read_cr0(vcpu);
525 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
526 X86_CR0_CD | X86_CR0_NW;
531 if (cr0 & 0xffffffff00000000UL)
535 cr0 &= ~CR0_RESERVED_BITS;
537 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
540 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
543 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
545 if ((vcpu->arch.efer & EFER_LME)) {
550 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
555 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
560 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
563 kvm_x86_ops->set_cr0(vcpu, cr0);
565 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
566 kvm_clear_async_pf_completion_queue(vcpu);
567 kvm_async_pf_hash_reset(vcpu);
570 if ((cr0 ^ old_cr0) & update_bits)
571 kvm_mmu_reset_context(vcpu);
574 EXPORT_SYMBOL_GPL(kvm_set_cr0);
576 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
578 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
580 EXPORT_SYMBOL_GPL(kvm_lmsw);
582 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
584 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
585 !vcpu->guest_xcr0_loaded) {
586 /* kvm_set_xcr() also depends on this */
587 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
588 vcpu->guest_xcr0_loaded = 1;
592 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
594 if (vcpu->guest_xcr0_loaded) {
595 if (vcpu->arch.xcr0 != host_xcr0)
596 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
597 vcpu->guest_xcr0_loaded = 0;
601 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
606 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
607 if (index != XCR_XFEATURE_ENABLED_MASK)
610 if (!(xcr0 & XSTATE_FP))
612 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
616 * Do not allow the guest to set bits that we do not support
617 * saving. However, xcr0 bit 0 is always set, even if the
618 * emulated CPU does not support XSAVE (see fx_init).
620 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
621 if (xcr0 & ~valid_bits)
624 kvm_put_guest_xcr0(vcpu);
625 vcpu->arch.xcr0 = xcr0;
629 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
632 __kvm_set_xcr(vcpu, index, xcr)) {
633 kvm_inject_gp(vcpu, 0);
638 EXPORT_SYMBOL_GPL(kvm_set_xcr);
640 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
642 unsigned long old_cr4 = kvm_read_cr4(vcpu);
643 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
644 X86_CR4_PAE | X86_CR4_SMEP;
645 if (cr4 & CR4_RESERVED_BITS)
648 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
651 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
654 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
657 if (is_long_mode(vcpu)) {
658 if (!(cr4 & X86_CR4_PAE))
660 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
661 && ((cr4 ^ old_cr4) & pdptr_bits)
662 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
666 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
667 if (!guest_cpuid_has_pcid(vcpu))
670 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
671 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
675 if (kvm_x86_ops->set_cr4(vcpu, cr4))
678 if (((cr4 ^ old_cr4) & pdptr_bits) ||
679 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
680 kvm_mmu_reset_context(vcpu);
682 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
683 kvm_update_cpuid(vcpu);
687 EXPORT_SYMBOL_GPL(kvm_set_cr4);
689 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
691 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
692 kvm_mmu_sync_roots(vcpu);
693 kvm_mmu_flush_tlb(vcpu);
697 if (is_long_mode(vcpu)) {
698 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
699 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
702 if (cr3 & CR3_L_MODE_RESERVED_BITS)
706 if (cr3 & CR3_PAE_RESERVED_BITS)
708 if (is_paging(vcpu) &&
709 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
713 * We don't check reserved bits in nonpae mode, because
714 * this isn't enforced, and VMware depends on this.
718 vcpu->arch.cr3 = cr3;
719 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
720 kvm_mmu_new_cr3(vcpu);
723 EXPORT_SYMBOL_GPL(kvm_set_cr3);
725 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
727 if (cr8 & CR8_RESERVED_BITS)
729 if (irqchip_in_kernel(vcpu->kvm))
730 kvm_lapic_set_tpr(vcpu, cr8);
732 vcpu->arch.cr8 = cr8;
735 EXPORT_SYMBOL_GPL(kvm_set_cr8);
737 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
739 if (irqchip_in_kernel(vcpu->kvm))
740 return kvm_lapic_get_cr8(vcpu);
742 return vcpu->arch.cr8;
744 EXPORT_SYMBOL_GPL(kvm_get_cr8);
746 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
748 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
749 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
752 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
756 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
757 dr7 = vcpu->arch.guest_debug_dr7;
759 dr7 = vcpu->arch.dr7;
760 kvm_x86_ops->set_dr7(vcpu, dr7);
761 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
764 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
768 vcpu->arch.db[dr] = val;
769 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
770 vcpu->arch.eff_db[dr] = val;
773 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
777 if (val & 0xffffffff00000000ULL)
779 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
780 kvm_update_dr6(vcpu);
783 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
787 if (val & 0xffffffff00000000ULL)
789 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
790 kvm_update_dr7(vcpu);
797 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
801 res = __kvm_set_dr(vcpu, dr, val);
803 kvm_queue_exception(vcpu, UD_VECTOR);
805 kvm_inject_gp(vcpu, 0);
809 EXPORT_SYMBOL_GPL(kvm_set_dr);
811 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
815 *val = vcpu->arch.db[dr];
818 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
822 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
823 *val = vcpu->arch.dr6;
825 *val = kvm_x86_ops->get_dr6(vcpu);
828 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
832 *val = vcpu->arch.dr7;
839 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
841 if (_kvm_get_dr(vcpu, dr, val)) {
842 kvm_queue_exception(vcpu, UD_VECTOR);
847 EXPORT_SYMBOL_GPL(kvm_get_dr);
849 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
851 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
855 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
858 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
859 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
862 EXPORT_SYMBOL_GPL(kvm_rdpmc);
865 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
866 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
868 * This list is modified at module load time to reflect the
869 * capabilities of the host cpu. This capabilities test skips MSRs that are
870 * kvm-specific. Those are put in the beginning of the list.
873 #define KVM_SAVE_MSRS_BEGIN 12
874 static u32 msrs_to_save[] = {
875 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
876 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
877 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
878 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
879 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
881 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
884 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
886 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
887 MSR_IA32_FEATURE_CONTROL
890 static unsigned num_msrs_to_save;
892 static const u32 emulated_msrs[] = {
894 MSR_IA32_TSCDEADLINE,
895 MSR_IA32_MISC_ENABLE,
900 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
902 if (efer & efer_reserved_bits)
905 if (efer & EFER_FFXSR) {
906 struct kvm_cpuid_entry2 *feat;
908 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
909 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
913 if (efer & EFER_SVME) {
914 struct kvm_cpuid_entry2 *feat;
916 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
917 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
923 EXPORT_SYMBOL_GPL(kvm_valid_efer);
925 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
927 u64 old_efer = vcpu->arch.efer;
929 if (!kvm_valid_efer(vcpu, efer))
933 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
937 efer |= vcpu->arch.efer & EFER_LMA;
939 kvm_x86_ops->set_efer(vcpu, efer);
941 /* Update reserved bits */
942 if ((efer ^ old_efer) & EFER_NX)
943 kvm_mmu_reset_context(vcpu);
948 void kvm_enable_efer_bits(u64 mask)
950 efer_reserved_bits &= ~mask;
952 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
955 * Writes msr value into into the appropriate "register".
956 * Returns 0 on success, non-0 otherwise.
957 * Assumes vcpu_load() was already called.
959 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
961 switch (msr->index) {
964 case MSR_KERNEL_GS_BASE:
967 if (is_noncanonical_address(msr->data))
970 case MSR_IA32_SYSENTER_EIP:
971 case MSR_IA32_SYSENTER_ESP:
973 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
974 * non-canonical address is written on Intel but not on
975 * AMD (which ignores the top 32-bits, because it does
976 * not implement 64-bit SYSENTER).
978 * 64-bit code should hence be able to write a non-canonical
979 * value on AMD. Making the address canonical ensures that
980 * vmentry does not fail on Intel after writing a non-canonical
981 * value, and that something deterministic happens if the guest
982 * invokes 64-bit SYSENTER.
984 msr->data = get_canonical(msr->data);
986 return kvm_x86_ops->set_msr(vcpu, msr);
988 EXPORT_SYMBOL_GPL(kvm_set_msr);
991 * Adapt set_msr() to msr_io()'s calling convention
993 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
999 msr.host_initiated = true;
1000 return kvm_set_msr(vcpu, &msr);
1003 #ifdef CONFIG_X86_64
1004 struct pvclock_gtod_data {
1007 struct { /* extract of a clocksource struct */
1015 /* open coded 'struct timespec' */
1016 u64 monotonic_time_snsec;
1017 time_t monotonic_time_sec;
1020 static struct pvclock_gtod_data pvclock_gtod_data;
1022 static void update_pvclock_gtod(struct timekeeper *tk)
1024 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1026 write_seqcount_begin(&vdata->seq);
1028 /* copy pvclock gtod data */
1029 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1030 vdata->clock.cycle_last = tk->clock->cycle_last;
1031 vdata->clock.mask = tk->clock->mask;
1032 vdata->clock.mult = tk->mult;
1033 vdata->clock.shift = tk->shift;
1035 vdata->monotonic_time_sec = tk->xtime_sec
1036 + tk->wall_to_monotonic.tv_sec;
1037 vdata->monotonic_time_snsec = tk->xtime_nsec
1038 + (tk->wall_to_monotonic.tv_nsec
1040 while (vdata->monotonic_time_snsec >=
1041 (((u64)NSEC_PER_SEC) << tk->shift)) {
1042 vdata->monotonic_time_snsec -=
1043 ((u64)NSEC_PER_SEC) << tk->shift;
1044 vdata->monotonic_time_sec++;
1047 write_seqcount_end(&vdata->seq);
1052 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1056 struct pvclock_wall_clock wc;
1057 struct timespec boot;
1062 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1067 ++version; /* first time write, random junk */
1071 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1074 * The guest calculates current wall clock time by adding
1075 * system time (updated by kvm_guest_time_update below) to the
1076 * wall clock specified here. guest system time equals host
1077 * system time for us, thus we must fill in host boot time here.
1081 if (kvm->arch.kvmclock_offset) {
1082 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1083 boot = timespec_sub(boot, ts);
1085 wc.sec = boot.tv_sec;
1086 wc.nsec = boot.tv_nsec;
1087 wc.version = version;
1089 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1092 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1095 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1097 uint32_t quotient, remainder;
1099 /* Don't try to replace with do_div(), this one calculates
1100 * "(dividend << 32) / divisor" */
1102 : "=a" (quotient), "=d" (remainder)
1103 : "0" (0), "1" (dividend), "r" (divisor) );
1107 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1108 s8 *pshift, u32 *pmultiplier)
1115 tps64 = base_khz * 1000LL;
1116 scaled64 = scaled_khz * 1000LL;
1117 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1122 tps32 = (uint32_t)tps64;
1123 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1124 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1132 *pmultiplier = div_frac(scaled64, tps32);
1134 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1135 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1138 static inline u64 get_kernel_ns(void)
1143 monotonic_to_bootbased(&ts);
1144 return timespec_to_ns(&ts);
1147 #ifdef CONFIG_X86_64
1148 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1151 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1152 unsigned long max_tsc_khz;
1154 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1156 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1157 vcpu->arch.virtual_tsc_shift);
1160 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1162 u64 v = (u64)khz * (1000000 + ppm);
1167 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1169 u32 thresh_lo, thresh_hi;
1170 int use_scaling = 0;
1172 /* tsc_khz can be zero if TSC calibration fails */
1173 if (this_tsc_khz == 0)
1176 /* Compute a scale to convert nanoseconds in TSC cycles */
1177 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1178 &vcpu->arch.virtual_tsc_shift,
1179 &vcpu->arch.virtual_tsc_mult);
1180 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1183 * Compute the variation in TSC rate which is acceptable
1184 * within the range of tolerance and decide if the
1185 * rate being applied is within that bounds of the hardware
1186 * rate. If so, no scaling or compensation need be done.
1188 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1189 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1190 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1191 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1194 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1197 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1199 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1200 vcpu->arch.virtual_tsc_mult,
1201 vcpu->arch.virtual_tsc_shift);
1202 tsc += vcpu->arch.this_tsc_write;
1206 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1208 #ifdef CONFIG_X86_64
1210 bool do_request = false;
1211 struct kvm_arch *ka = &vcpu->kvm->arch;
1212 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1214 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1215 atomic_read(&vcpu->kvm->online_vcpus));
1217 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1218 if (!ka->use_master_clock)
1221 if (!vcpus_matched && ka->use_master_clock)
1225 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1227 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1228 atomic_read(&vcpu->kvm->online_vcpus),
1229 ka->use_master_clock, gtod->clock.vclock_mode);
1233 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1235 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1236 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1239 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1241 struct kvm *kvm = vcpu->kvm;
1242 u64 offset, ns, elapsed;
1243 unsigned long flags;
1246 u64 data = msr->data;
1248 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1249 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1250 ns = get_kernel_ns();
1251 elapsed = ns - kvm->arch.last_tsc_nsec;
1253 if (vcpu->arch.virtual_tsc_khz) {
1256 /* n.b - signed multiplication and division required */
1257 usdiff = data - kvm->arch.last_tsc_write;
1258 #ifdef CONFIG_X86_64
1259 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1261 /* do_div() only does unsigned */
1262 asm("1: idivl %[divisor]\n"
1263 "2: xor %%edx, %%edx\n"
1264 " movl $0, %[faulted]\n"
1266 ".section .fixup,\"ax\"\n"
1267 "4: movl $1, %[faulted]\n"
1271 _ASM_EXTABLE(1b, 4b)
1273 : "=A"(usdiff), [faulted] "=r" (faulted)
1274 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1277 do_div(elapsed, 1000);
1282 /* idivl overflow => difference is larger than USEC_PER_SEC */
1284 usdiff = USEC_PER_SEC;
1286 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1289 * Special case: TSC write with a small delta (1 second) of virtual
1290 * cycle time against real time is interpreted as an attempt to
1291 * synchronize the CPU.
1293 * For a reliable TSC, we can match TSC offsets, and for an unstable
1294 * TSC, we add elapsed time in this computation. We could let the
1295 * compensation code attempt to catch up if we fall behind, but
1296 * it's better to try to match offsets from the beginning.
1298 if (usdiff < USEC_PER_SEC &&
1299 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1300 if (!check_tsc_unstable()) {
1301 offset = kvm->arch.cur_tsc_offset;
1302 pr_debug("kvm: matched tsc offset for %llu\n", data);
1304 u64 delta = nsec_to_cycles(vcpu, elapsed);
1306 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1307 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1312 * We split periods of matched TSC writes into generations.
1313 * For each generation, we track the original measured
1314 * nanosecond time, offset, and write, so if TSCs are in
1315 * sync, we can match exact offset, and if not, we can match
1316 * exact software computation in compute_guest_tsc()
1318 * These values are tracked in kvm->arch.cur_xxx variables.
1320 kvm->arch.cur_tsc_generation++;
1321 kvm->arch.cur_tsc_nsec = ns;
1322 kvm->arch.cur_tsc_write = data;
1323 kvm->arch.cur_tsc_offset = offset;
1325 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1326 kvm->arch.cur_tsc_generation, data);
1330 * We also track th most recent recorded KHZ, write and time to
1331 * allow the matching interval to be extended at each write.
1333 kvm->arch.last_tsc_nsec = ns;
1334 kvm->arch.last_tsc_write = data;
1335 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1337 vcpu->arch.last_guest_tsc = data;
1339 /* Keep track of which generation this VCPU has synchronized to */
1340 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1341 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1342 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1344 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1345 update_ia32_tsc_adjust_msr(vcpu, offset);
1346 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1347 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1349 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1351 kvm->arch.nr_vcpus_matched_tsc++;
1353 kvm->arch.nr_vcpus_matched_tsc = 0;
1355 kvm_track_tsc_matching(vcpu);
1356 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1359 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1361 #ifdef CONFIG_X86_64
1363 static cycle_t read_tsc(void)
1369 * Empirically, a fence (of type that depends on the CPU)
1370 * before rdtsc is enough to ensure that rdtsc is ordered
1371 * with respect to loads. The various CPU manuals are unclear
1372 * as to whether rdtsc can be reordered with later loads,
1373 * but no one has ever seen it happen.
1376 ret = (cycle_t)vget_cycles();
1378 last = pvclock_gtod_data.clock.cycle_last;
1380 if (likely(ret >= last))
1384 * GCC likes to generate cmov here, but this branch is extremely
1385 * predictable (it's just a funciton of time and the likely is
1386 * very likely) and there's a data dependence, so force GCC
1387 * to generate a branch instead. I don't barrier() because
1388 * we don't actually need a barrier, and if this function
1389 * ever gets inlined it will generate worse code.
1395 static inline u64 vgettsc(cycle_t *cycle_now)
1398 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1400 *cycle_now = read_tsc();
1402 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1403 return v * gtod->clock.mult;
1406 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1411 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1415 seq = read_seqcount_begin(>od->seq);
1416 mode = gtod->clock.vclock_mode;
1417 ts->tv_sec = gtod->monotonic_time_sec;
1418 ns = gtod->monotonic_time_snsec;
1419 ns += vgettsc(cycle_now);
1420 ns >>= gtod->clock.shift;
1421 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1422 timespec_add_ns(ts, ns);
1427 /* returns true if host is using tsc clocksource */
1428 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1432 /* checked again under seqlock below */
1433 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1436 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1439 monotonic_to_bootbased(&ts);
1440 *kernel_ns = timespec_to_ns(&ts);
1448 * Assuming a stable TSC across physical CPUS, and a stable TSC
1449 * across virtual CPUs, the following condition is possible.
1450 * Each numbered line represents an event visible to both
1451 * CPUs at the next numbered event.
1453 * "timespecX" represents host monotonic time. "tscX" represents
1456 * VCPU0 on CPU0 | VCPU1 on CPU1
1458 * 1. read timespec0,tsc0
1459 * 2. | timespec1 = timespec0 + N
1461 * 3. transition to guest | transition to guest
1462 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1463 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1464 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1466 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1469 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1471 * - 0 < N - M => M < N
1473 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1474 * always the case (the difference between two distinct xtime instances
1475 * might be smaller then the difference between corresponding TSC reads,
1476 * when updating guest vcpus pvclock areas).
1478 * To avoid that problem, do not allow visibility of distinct
1479 * system_timestamp/tsc_timestamp values simultaneously: use a master
1480 * copy of host monotonic time values. Update that master copy
1483 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1487 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1489 #ifdef CONFIG_X86_64
1490 struct kvm_arch *ka = &kvm->arch;
1492 bool host_tsc_clocksource, vcpus_matched;
1494 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1495 atomic_read(&kvm->online_vcpus));
1498 * If the host uses TSC clock, then passthrough TSC as stable
1501 host_tsc_clocksource = kvm_get_time_and_clockread(
1502 &ka->master_kernel_ns,
1503 &ka->master_cycle_now);
1505 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1507 if (ka->use_master_clock)
1508 atomic_set(&kvm_guest_has_master_clock, 1);
1510 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1511 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1516 static void kvm_gen_update_masterclock(struct kvm *kvm)
1518 #ifdef CONFIG_X86_64
1520 struct kvm_vcpu *vcpu;
1521 struct kvm_arch *ka = &kvm->arch;
1523 spin_lock(&ka->pvclock_gtod_sync_lock);
1524 kvm_make_mclock_inprogress_request(kvm);
1525 /* no guest entries from this point */
1526 pvclock_update_vm_gtod_copy(kvm);
1528 kvm_for_each_vcpu(i, vcpu, kvm)
1529 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1531 /* guest entries allowed */
1532 kvm_for_each_vcpu(i, vcpu, kvm)
1533 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1535 spin_unlock(&ka->pvclock_gtod_sync_lock);
1539 static int kvm_guest_time_update(struct kvm_vcpu *v)
1541 unsigned long flags, this_tsc_khz;
1542 struct kvm_vcpu_arch *vcpu = &v->arch;
1543 struct kvm_arch *ka = &v->kvm->arch;
1545 u64 tsc_timestamp, host_tsc;
1546 struct pvclock_vcpu_time_info guest_hv_clock;
1548 bool use_master_clock;
1554 * If the host uses TSC clock, then passthrough TSC as stable
1557 spin_lock(&ka->pvclock_gtod_sync_lock);
1558 use_master_clock = ka->use_master_clock;
1559 if (use_master_clock) {
1560 host_tsc = ka->master_cycle_now;
1561 kernel_ns = ka->master_kernel_ns;
1563 spin_unlock(&ka->pvclock_gtod_sync_lock);
1565 /* Keep irq disabled to prevent changes to the clock */
1566 local_irq_save(flags);
1567 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1568 if (unlikely(this_tsc_khz == 0)) {
1569 local_irq_restore(flags);
1570 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1573 if (!use_master_clock) {
1574 host_tsc = native_read_tsc();
1575 kernel_ns = get_kernel_ns();
1578 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1581 * We may have to catch up the TSC to match elapsed wall clock
1582 * time for two reasons, even if kvmclock is used.
1583 * 1) CPU could have been running below the maximum TSC rate
1584 * 2) Broken TSC compensation resets the base at each VCPU
1585 * entry to avoid unknown leaps of TSC even when running
1586 * again on the same CPU. This may cause apparent elapsed
1587 * time to disappear, and the guest to stand still or run
1590 if (vcpu->tsc_catchup) {
1591 u64 tsc = compute_guest_tsc(v, kernel_ns);
1592 if (tsc > tsc_timestamp) {
1593 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1594 tsc_timestamp = tsc;
1598 local_irq_restore(flags);
1600 if (!vcpu->pv_time_enabled)
1603 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1604 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1605 &vcpu->hv_clock.tsc_shift,
1606 &vcpu->hv_clock.tsc_to_system_mul);
1607 vcpu->hw_tsc_khz = this_tsc_khz;
1610 /* With all the info we got, fill in the values */
1611 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1612 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1613 vcpu->last_kernel_ns = kernel_ns;
1614 vcpu->last_guest_tsc = tsc_timestamp;
1617 * The interface expects us to write an even number signaling that the
1618 * update is finished. Since the guest won't see the intermediate
1619 * state, we just increase by 2 at the end.
1621 vcpu->hv_clock.version += 2;
1623 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1624 &guest_hv_clock, sizeof(guest_hv_clock))))
1627 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1628 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1630 if (vcpu->pvclock_set_guest_stopped_request) {
1631 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1632 vcpu->pvclock_set_guest_stopped_request = false;
1635 /* If the host uses TSC clocksource, then it is stable */
1636 if (use_master_clock)
1637 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1639 vcpu->hv_clock.flags = pvclock_flags;
1641 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1643 sizeof(vcpu->hv_clock));
1648 * kvmclock updates which are isolated to a given vcpu, such as
1649 * vcpu->cpu migration, should not allow system_timestamp from
1650 * the rest of the vcpus to remain static. Otherwise ntp frequency
1651 * correction applies to one vcpu's system_timestamp but not
1654 * So in those cases, request a kvmclock update for all vcpus.
1655 * The worst case for a remote vcpu to update its kvmclock
1656 * is then bounded by maximum nohz sleep latency.
1659 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1662 struct kvm *kvm = v->kvm;
1663 struct kvm_vcpu *vcpu;
1665 kvm_for_each_vcpu(i, vcpu, kvm) {
1666 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1667 kvm_vcpu_kick(vcpu);
1671 static bool msr_mtrr_valid(unsigned msr)
1674 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1675 case MSR_MTRRfix64K_00000:
1676 case MSR_MTRRfix16K_80000:
1677 case MSR_MTRRfix16K_A0000:
1678 case MSR_MTRRfix4K_C0000:
1679 case MSR_MTRRfix4K_C8000:
1680 case MSR_MTRRfix4K_D0000:
1681 case MSR_MTRRfix4K_D8000:
1682 case MSR_MTRRfix4K_E0000:
1683 case MSR_MTRRfix4K_E8000:
1684 case MSR_MTRRfix4K_F0000:
1685 case MSR_MTRRfix4K_F8000:
1686 case MSR_MTRRdefType:
1687 case MSR_IA32_CR_PAT:
1695 static bool valid_pat_type(unsigned t)
1697 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1700 static bool valid_mtrr_type(unsigned t)
1702 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1705 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1709 if (!msr_mtrr_valid(msr))
1712 if (msr == MSR_IA32_CR_PAT) {
1713 for (i = 0; i < 8; i++)
1714 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1717 } else if (msr == MSR_MTRRdefType) {
1720 return valid_mtrr_type(data & 0xff);
1721 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1722 for (i = 0; i < 8 ; i++)
1723 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1728 /* variable MTRRs */
1729 return valid_mtrr_type(data & 0xff);
1732 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1734 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1736 if (!mtrr_valid(vcpu, msr, data))
1739 if (msr == MSR_MTRRdefType) {
1740 vcpu->arch.mtrr_state.def_type = data;
1741 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1742 } else if (msr == MSR_MTRRfix64K_00000)
1744 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1745 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1746 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1747 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1748 else if (msr == MSR_IA32_CR_PAT)
1749 vcpu->arch.pat = data;
1750 else { /* Variable MTRRs */
1751 int idx, is_mtrr_mask;
1754 idx = (msr - 0x200) / 2;
1755 is_mtrr_mask = msr - 0x200 - 2 * idx;
1758 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1761 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1765 kvm_mmu_reset_context(vcpu);
1769 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1771 u64 mcg_cap = vcpu->arch.mcg_cap;
1772 unsigned bank_num = mcg_cap & 0xff;
1775 case MSR_IA32_MCG_STATUS:
1776 vcpu->arch.mcg_status = data;
1778 case MSR_IA32_MCG_CTL:
1779 if (!(mcg_cap & MCG_CTL_P))
1781 if (data != 0 && data != ~(u64)0)
1783 vcpu->arch.mcg_ctl = data;
1786 if (msr >= MSR_IA32_MC0_CTL &&
1787 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1788 u32 offset = msr - MSR_IA32_MC0_CTL;
1789 /* only 0 or all 1s can be written to IA32_MCi_CTL
1790 * some Linux kernels though clear bit 10 in bank 4 to
1791 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1792 * this to avoid an uncatched #GP in the guest
1794 if ((offset & 0x3) == 0 &&
1795 data != 0 && (data | (1 << 10)) != ~(u64)0)
1797 vcpu->arch.mce_banks[offset] = data;
1805 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1807 struct kvm *kvm = vcpu->kvm;
1808 int lm = is_long_mode(vcpu);
1809 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1810 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1811 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1812 : kvm->arch.xen_hvm_config.blob_size_32;
1813 u32 page_num = data & ~PAGE_MASK;
1814 u64 page_addr = data & PAGE_MASK;
1819 if (page_num >= blob_size)
1822 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1827 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1836 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1838 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1841 static bool kvm_hv_msr_partition_wide(u32 msr)
1845 case HV_X64_MSR_GUEST_OS_ID:
1846 case HV_X64_MSR_HYPERCALL:
1847 case HV_X64_MSR_REFERENCE_TSC:
1848 case HV_X64_MSR_TIME_REF_COUNT:
1856 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1858 struct kvm *kvm = vcpu->kvm;
1861 case HV_X64_MSR_GUEST_OS_ID:
1862 kvm->arch.hv_guest_os_id = data;
1863 /* setting guest os id to zero disables hypercall page */
1864 if (!kvm->arch.hv_guest_os_id)
1865 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1867 case HV_X64_MSR_HYPERCALL: {
1872 /* if guest os id is not set hypercall should remain disabled */
1873 if (!kvm->arch.hv_guest_os_id)
1875 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1876 kvm->arch.hv_hypercall = data;
1879 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1880 addr = gfn_to_hva(kvm, gfn);
1881 if (kvm_is_error_hva(addr))
1883 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1884 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1885 if (__copy_to_user((void __user *)addr, instructions, 4))
1887 kvm->arch.hv_hypercall = data;
1888 mark_page_dirty(kvm, gfn);
1891 case HV_X64_MSR_REFERENCE_TSC: {
1893 HV_REFERENCE_TSC_PAGE tsc_ref;
1894 memset(&tsc_ref, 0, sizeof(tsc_ref));
1895 kvm->arch.hv_tsc_page = data;
1896 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1898 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1899 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
1900 &tsc_ref, sizeof(tsc_ref)))
1902 mark_page_dirty(kvm, gfn);
1906 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1907 "data 0x%llx\n", msr, data);
1913 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1916 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1920 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1921 vcpu->arch.hv_vapic = data;
1924 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1925 addr = gfn_to_hva(vcpu->kvm, gfn);
1926 if (kvm_is_error_hva(addr))
1928 if (__clear_user((void __user *)addr, PAGE_SIZE))
1930 vcpu->arch.hv_vapic = data;
1931 mark_page_dirty(vcpu->kvm, gfn);
1934 case HV_X64_MSR_EOI:
1935 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1936 case HV_X64_MSR_ICR:
1937 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1938 case HV_X64_MSR_TPR:
1939 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1941 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1942 "data 0x%llx\n", msr, data);
1949 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1951 gpa_t gpa = data & ~0x3f;
1953 /* Bits 2:5 are reserved, Should be zero */
1957 vcpu->arch.apf.msr_val = data;
1959 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1960 kvm_clear_async_pf_completion_queue(vcpu);
1961 kvm_async_pf_hash_reset(vcpu);
1965 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1969 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1970 kvm_async_pf_wakeup_all(vcpu);
1974 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1976 vcpu->arch.pv_time_enabled = false;
1979 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1983 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1986 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1987 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1988 vcpu->arch.st.accum_steal = delta;
1991 static void record_steal_time(struct kvm_vcpu *vcpu)
1993 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1996 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1997 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2000 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2001 vcpu->arch.st.steal.version += 2;
2002 vcpu->arch.st.accum_steal = 0;
2004 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2005 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2008 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2011 u32 msr = msr_info->index;
2012 u64 data = msr_info->data;
2015 case MSR_AMD64_NB_CFG:
2016 case MSR_IA32_UCODE_REV:
2017 case MSR_IA32_UCODE_WRITE:
2018 case MSR_VM_HSAVE_PA:
2019 case MSR_AMD64_PATCH_LOADER:
2020 case MSR_AMD64_BU_CFG2:
2024 return set_efer(vcpu, data);
2026 data &= ~(u64)0x40; /* ignore flush filter disable */
2027 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2028 data &= ~(u64)0x8; /* ignore TLB cache disable */
2030 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2035 case MSR_FAM10H_MMIO_CONF_BASE:
2037 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2042 case MSR_IA32_DEBUGCTLMSR:
2044 /* We support the non-activated case already */
2046 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2047 /* Values other than LBR and BTF are vendor-specific,
2048 thus reserved and should throw a #GP */
2051 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2054 case 0x200 ... 0x2ff:
2055 return set_msr_mtrr(vcpu, msr, data);
2056 case MSR_IA32_APICBASE:
2057 return kvm_set_apic_base(vcpu, msr_info);
2058 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2059 return kvm_x2apic_msr_write(vcpu, msr, data);
2060 case MSR_IA32_TSCDEADLINE:
2061 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2063 case MSR_IA32_TSC_ADJUST:
2064 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2065 if (!msr_info->host_initiated) {
2066 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2067 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2069 vcpu->arch.ia32_tsc_adjust_msr = data;
2072 case MSR_IA32_MISC_ENABLE:
2073 vcpu->arch.ia32_misc_enable_msr = data;
2075 case MSR_KVM_WALL_CLOCK_NEW:
2076 case MSR_KVM_WALL_CLOCK:
2077 vcpu->kvm->arch.wall_clock = data;
2078 kvm_write_wall_clock(vcpu->kvm, data);
2080 case MSR_KVM_SYSTEM_TIME_NEW:
2081 case MSR_KVM_SYSTEM_TIME: {
2083 kvmclock_reset(vcpu);
2085 vcpu->arch.time = data;
2086 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2088 /* we verify if the enable bit is set... */
2092 gpa_offset = data & ~(PAGE_MASK | 1);
2094 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2095 &vcpu->arch.pv_time, data & ~1ULL,
2096 sizeof(struct pvclock_vcpu_time_info)))
2097 vcpu->arch.pv_time_enabled = false;
2099 vcpu->arch.pv_time_enabled = true;
2103 case MSR_KVM_ASYNC_PF_EN:
2104 if (kvm_pv_enable_async_pf(vcpu, data))
2107 case MSR_KVM_STEAL_TIME:
2109 if (unlikely(!sched_info_on()))
2112 if (data & KVM_STEAL_RESERVED_MASK)
2115 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2116 data & KVM_STEAL_VALID_BITS,
2117 sizeof(struct kvm_steal_time)))
2120 vcpu->arch.st.msr_val = data;
2122 if (!(data & KVM_MSR_ENABLED))
2125 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2128 accumulate_steal_time(vcpu);
2131 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2134 case MSR_KVM_PV_EOI_EN:
2135 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2139 case MSR_IA32_MCG_CTL:
2140 case MSR_IA32_MCG_STATUS:
2141 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2142 return set_msr_mce(vcpu, msr, data);
2144 /* Performance counters are not protected by a CPUID bit,
2145 * so we should check all of them in the generic path for the sake of
2146 * cross vendor migration.
2147 * Writing a zero into the event select MSRs disables them,
2148 * which we perfectly emulate ;-). Any other value should be at least
2149 * reported, some guests depend on them.
2151 case MSR_K7_EVNTSEL0:
2152 case MSR_K7_EVNTSEL1:
2153 case MSR_K7_EVNTSEL2:
2154 case MSR_K7_EVNTSEL3:
2156 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2157 "0x%x data 0x%llx\n", msr, data);
2159 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2160 * so we ignore writes to make it happy.
2162 case MSR_K7_PERFCTR0:
2163 case MSR_K7_PERFCTR1:
2164 case MSR_K7_PERFCTR2:
2165 case MSR_K7_PERFCTR3:
2166 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2167 "0x%x data 0x%llx\n", msr, data);
2169 case MSR_P6_PERFCTR0:
2170 case MSR_P6_PERFCTR1:
2172 case MSR_P6_EVNTSEL0:
2173 case MSR_P6_EVNTSEL1:
2174 if (kvm_pmu_msr(vcpu, msr))
2175 return kvm_pmu_set_msr(vcpu, msr_info);
2177 if (pr || data != 0)
2178 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2179 "0x%x data 0x%llx\n", msr, data);
2181 case MSR_K7_CLK_CTL:
2183 * Ignore all writes to this no longer documented MSR.
2184 * Writes are only relevant for old K7 processors,
2185 * all pre-dating SVM, but a recommended workaround from
2186 * AMD for these chips. It is possible to specify the
2187 * affected processor models on the command line, hence
2188 * the need to ignore the workaround.
2191 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2192 if (kvm_hv_msr_partition_wide(msr)) {
2194 mutex_lock(&vcpu->kvm->lock);
2195 r = set_msr_hyperv_pw(vcpu, msr, data);
2196 mutex_unlock(&vcpu->kvm->lock);
2199 return set_msr_hyperv(vcpu, msr, data);
2201 case MSR_IA32_BBL_CR_CTL3:
2202 /* Drop writes to this legacy MSR -- see rdmsr
2203 * counterpart for further detail.
2205 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2207 case MSR_AMD64_OSVW_ID_LENGTH:
2208 if (!guest_cpuid_has_osvw(vcpu))
2210 vcpu->arch.osvw.length = data;
2212 case MSR_AMD64_OSVW_STATUS:
2213 if (!guest_cpuid_has_osvw(vcpu))
2215 vcpu->arch.osvw.status = data;
2218 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2219 return xen_hvm_config(vcpu, data);
2220 if (kvm_pmu_msr(vcpu, msr))
2221 return kvm_pmu_set_msr(vcpu, msr_info);
2223 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2227 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2234 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2238 * Reads an msr value (of 'msr_index') into 'pdata'.
2239 * Returns 0 on success, non-0 otherwise.
2240 * Assumes vcpu_load() was already called.
2242 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2244 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2247 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2249 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2251 if (!msr_mtrr_valid(msr))
2254 if (msr == MSR_MTRRdefType)
2255 *pdata = vcpu->arch.mtrr_state.def_type +
2256 (vcpu->arch.mtrr_state.enabled << 10);
2257 else if (msr == MSR_MTRRfix64K_00000)
2259 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2260 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2261 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2262 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2263 else if (msr == MSR_IA32_CR_PAT)
2264 *pdata = vcpu->arch.pat;
2265 else { /* Variable MTRRs */
2266 int idx, is_mtrr_mask;
2269 idx = (msr - 0x200) / 2;
2270 is_mtrr_mask = msr - 0x200 - 2 * idx;
2273 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2276 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2283 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2286 u64 mcg_cap = vcpu->arch.mcg_cap;
2287 unsigned bank_num = mcg_cap & 0xff;
2290 case MSR_IA32_P5_MC_ADDR:
2291 case MSR_IA32_P5_MC_TYPE:
2294 case MSR_IA32_MCG_CAP:
2295 data = vcpu->arch.mcg_cap;
2297 case MSR_IA32_MCG_CTL:
2298 if (!(mcg_cap & MCG_CTL_P))
2300 data = vcpu->arch.mcg_ctl;
2302 case MSR_IA32_MCG_STATUS:
2303 data = vcpu->arch.mcg_status;
2306 if (msr >= MSR_IA32_MC0_CTL &&
2307 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2308 u32 offset = msr - MSR_IA32_MC0_CTL;
2309 data = vcpu->arch.mce_banks[offset];
2318 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2321 struct kvm *kvm = vcpu->kvm;
2324 case HV_X64_MSR_GUEST_OS_ID:
2325 data = kvm->arch.hv_guest_os_id;
2327 case HV_X64_MSR_HYPERCALL:
2328 data = kvm->arch.hv_hypercall;
2330 case HV_X64_MSR_TIME_REF_COUNT: {
2332 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2335 case HV_X64_MSR_REFERENCE_TSC:
2336 data = kvm->arch.hv_tsc_page;
2339 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2347 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2352 case HV_X64_MSR_VP_INDEX: {
2355 kvm_for_each_vcpu(r, v, vcpu->kvm)
2360 case HV_X64_MSR_EOI:
2361 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2362 case HV_X64_MSR_ICR:
2363 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2364 case HV_X64_MSR_TPR:
2365 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2366 case HV_X64_MSR_APIC_ASSIST_PAGE:
2367 data = vcpu->arch.hv_vapic;
2370 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2377 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2382 case MSR_IA32_PLATFORM_ID:
2383 case MSR_IA32_EBL_CR_POWERON:
2384 case MSR_IA32_DEBUGCTLMSR:
2385 case MSR_IA32_LASTBRANCHFROMIP:
2386 case MSR_IA32_LASTBRANCHTOIP:
2387 case MSR_IA32_LASTINTFROMIP:
2388 case MSR_IA32_LASTINTTOIP:
2391 case MSR_VM_HSAVE_PA:
2392 case MSR_K7_EVNTSEL0:
2393 case MSR_K7_PERFCTR0:
2394 case MSR_K8_INT_PENDING_MSG:
2395 case MSR_AMD64_NB_CFG:
2396 case MSR_FAM10H_MMIO_CONF_BASE:
2397 case MSR_AMD64_BU_CFG2:
2400 case MSR_P6_PERFCTR0:
2401 case MSR_P6_PERFCTR1:
2402 case MSR_P6_EVNTSEL0:
2403 case MSR_P6_EVNTSEL1:
2404 if (kvm_pmu_msr(vcpu, msr))
2405 return kvm_pmu_get_msr(vcpu, msr, pdata);
2408 case MSR_IA32_UCODE_REV:
2409 data = 0x100000000ULL;
2412 data = 0x500 | KVM_NR_VAR_MTRR;
2414 case 0x200 ... 0x2ff:
2415 return get_msr_mtrr(vcpu, msr, pdata);
2416 case 0xcd: /* fsb frequency */
2420 * MSR_EBC_FREQUENCY_ID
2421 * Conservative value valid for even the basic CPU models.
2422 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2423 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2424 * and 266MHz for model 3, or 4. Set Core Clock
2425 * Frequency to System Bus Frequency Ratio to 1 (bits
2426 * 31:24) even though these are only valid for CPU
2427 * models > 2, however guests may end up dividing or
2428 * multiplying by zero otherwise.
2430 case MSR_EBC_FREQUENCY_ID:
2433 case MSR_IA32_APICBASE:
2434 data = kvm_get_apic_base(vcpu);
2436 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2437 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2439 case MSR_IA32_TSCDEADLINE:
2440 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2442 case MSR_IA32_TSC_ADJUST:
2443 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2445 case MSR_IA32_MISC_ENABLE:
2446 data = vcpu->arch.ia32_misc_enable_msr;
2448 case MSR_IA32_PERF_STATUS:
2449 /* TSC increment by tick */
2451 /* CPU multiplier */
2452 data |= (((uint64_t)4ULL) << 40);
2455 data = vcpu->arch.efer;
2457 case MSR_KVM_WALL_CLOCK:
2458 case MSR_KVM_WALL_CLOCK_NEW:
2459 data = vcpu->kvm->arch.wall_clock;
2461 case MSR_KVM_SYSTEM_TIME:
2462 case MSR_KVM_SYSTEM_TIME_NEW:
2463 data = vcpu->arch.time;
2465 case MSR_KVM_ASYNC_PF_EN:
2466 data = vcpu->arch.apf.msr_val;
2468 case MSR_KVM_STEAL_TIME:
2469 data = vcpu->arch.st.msr_val;
2471 case MSR_KVM_PV_EOI_EN:
2472 data = vcpu->arch.pv_eoi.msr_val;
2474 case MSR_IA32_P5_MC_ADDR:
2475 case MSR_IA32_P5_MC_TYPE:
2476 case MSR_IA32_MCG_CAP:
2477 case MSR_IA32_MCG_CTL:
2478 case MSR_IA32_MCG_STATUS:
2479 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2480 return get_msr_mce(vcpu, msr, pdata);
2481 case MSR_K7_CLK_CTL:
2483 * Provide expected ramp-up count for K7. All other
2484 * are set to zero, indicating minimum divisors for
2487 * This prevents guest kernels on AMD host with CPU
2488 * type 6, model 8 and higher from exploding due to
2489 * the rdmsr failing.
2493 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2494 if (kvm_hv_msr_partition_wide(msr)) {
2496 mutex_lock(&vcpu->kvm->lock);
2497 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2498 mutex_unlock(&vcpu->kvm->lock);
2501 return get_msr_hyperv(vcpu, msr, pdata);
2503 case MSR_IA32_BBL_CR_CTL3:
2504 /* This legacy MSR exists but isn't fully documented in current
2505 * silicon. It is however accessed by winxp in very narrow
2506 * scenarios where it sets bit #19, itself documented as
2507 * a "reserved" bit. Best effort attempt to source coherent
2508 * read data here should the balance of the register be
2509 * interpreted by the guest:
2511 * L2 cache control register 3: 64GB range, 256KB size,
2512 * enabled, latency 0x1, configured
2516 case MSR_AMD64_OSVW_ID_LENGTH:
2517 if (!guest_cpuid_has_osvw(vcpu))
2519 data = vcpu->arch.osvw.length;
2521 case MSR_AMD64_OSVW_STATUS:
2522 if (!guest_cpuid_has_osvw(vcpu))
2524 data = vcpu->arch.osvw.status;
2527 if (kvm_pmu_msr(vcpu, msr))
2528 return kvm_pmu_get_msr(vcpu, msr, pdata);
2530 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2533 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2541 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2544 * Read or write a bunch of msrs. All parameters are kernel addresses.
2546 * @return number of msrs set successfully.
2548 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2549 struct kvm_msr_entry *entries,
2550 int (*do_msr)(struct kvm_vcpu *vcpu,
2551 unsigned index, u64 *data))
2555 idx = srcu_read_lock(&vcpu->kvm->srcu);
2556 for (i = 0; i < msrs->nmsrs; ++i)
2557 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2559 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2565 * Read or write a bunch of msrs. Parameters are user addresses.
2567 * @return number of msrs set successfully.
2569 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2570 int (*do_msr)(struct kvm_vcpu *vcpu,
2571 unsigned index, u64 *data),
2574 struct kvm_msrs msrs;
2575 struct kvm_msr_entry *entries;
2580 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2584 if (msrs.nmsrs >= MAX_IO_MSRS)
2587 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2588 entries = memdup_user(user_msrs->entries, size);
2589 if (IS_ERR(entries)) {
2590 r = PTR_ERR(entries);
2594 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2599 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2610 int kvm_dev_ioctl_check_extension(long ext)
2615 case KVM_CAP_IRQCHIP:
2617 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2618 case KVM_CAP_SET_TSS_ADDR:
2619 case KVM_CAP_EXT_CPUID:
2620 case KVM_CAP_EXT_EMUL_CPUID:
2621 case KVM_CAP_CLOCKSOURCE:
2623 case KVM_CAP_NOP_IO_DELAY:
2624 case KVM_CAP_MP_STATE:
2625 case KVM_CAP_SYNC_MMU:
2626 case KVM_CAP_USER_NMI:
2627 case KVM_CAP_REINJECT_CONTROL:
2628 case KVM_CAP_IRQ_INJECT_STATUS:
2630 case KVM_CAP_IOEVENTFD:
2632 case KVM_CAP_PIT_STATE2:
2633 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2634 case KVM_CAP_XEN_HVM:
2635 case KVM_CAP_ADJUST_CLOCK:
2636 case KVM_CAP_VCPU_EVENTS:
2637 case KVM_CAP_HYPERV:
2638 case KVM_CAP_HYPERV_VAPIC:
2639 case KVM_CAP_HYPERV_SPIN:
2640 case KVM_CAP_PCI_SEGMENT:
2641 case KVM_CAP_DEBUGREGS:
2642 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2644 case KVM_CAP_ASYNC_PF:
2645 case KVM_CAP_GET_TSC_KHZ:
2646 case KVM_CAP_KVMCLOCK_CTRL:
2647 case KVM_CAP_READONLY_MEM:
2648 case KVM_CAP_HYPERV_TIME:
2649 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2650 case KVM_CAP_ASSIGN_DEV_IRQ:
2651 case KVM_CAP_PCI_2_3:
2655 case KVM_CAP_COALESCED_MMIO:
2656 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2659 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2661 case KVM_CAP_NR_VCPUS:
2662 r = KVM_SOFT_MAX_VCPUS;
2664 case KVM_CAP_MAX_VCPUS:
2667 case KVM_CAP_NR_MEMSLOTS:
2668 r = KVM_USER_MEM_SLOTS;
2670 case KVM_CAP_PV_MMU: /* obsolete */
2673 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2675 r = iommu_present(&pci_bus_type);
2679 r = KVM_MAX_MCE_BANKS;
2684 case KVM_CAP_TSC_CONTROL:
2685 r = kvm_has_tsc_control;
2687 case KVM_CAP_TSC_DEADLINE_TIMER:
2688 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2698 long kvm_arch_dev_ioctl(struct file *filp,
2699 unsigned int ioctl, unsigned long arg)
2701 void __user *argp = (void __user *)arg;
2705 case KVM_GET_MSR_INDEX_LIST: {
2706 struct kvm_msr_list __user *user_msr_list = argp;
2707 struct kvm_msr_list msr_list;
2711 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2714 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2715 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2718 if (n < msr_list.nmsrs)
2721 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2722 num_msrs_to_save * sizeof(u32)))
2724 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2726 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2731 case KVM_GET_SUPPORTED_CPUID:
2732 case KVM_GET_EMULATED_CPUID: {
2733 struct kvm_cpuid2 __user *cpuid_arg = argp;
2734 struct kvm_cpuid2 cpuid;
2737 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2740 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2746 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2751 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2754 mce_cap = KVM_MCE_CAP_SUPPORTED;
2756 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2768 static void wbinvd_ipi(void *garbage)
2773 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2775 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2778 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2780 /* Address WBINVD may be executed by guest */
2781 if (need_emulate_wbinvd(vcpu)) {
2782 if (kvm_x86_ops->has_wbinvd_exit())
2783 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2784 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2785 smp_call_function_single(vcpu->cpu,
2786 wbinvd_ipi, NULL, 1);
2789 kvm_x86_ops->vcpu_load(vcpu, cpu);
2791 /* Apply any externally detected TSC adjustments (due to suspend) */
2792 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2793 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2794 vcpu->arch.tsc_offset_adjustment = 0;
2795 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2798 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2799 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2800 native_read_tsc() - vcpu->arch.last_host_tsc;
2802 mark_tsc_unstable("KVM discovered backwards TSC");
2803 if (check_tsc_unstable()) {
2804 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2805 vcpu->arch.last_guest_tsc);
2806 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2807 vcpu->arch.tsc_catchup = 1;
2810 * On a host with synchronized TSC, there is no need to update
2811 * kvmclock on vcpu->cpu migration
2813 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2814 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2815 if (vcpu->cpu != cpu)
2816 kvm_migrate_timers(vcpu);
2820 accumulate_steal_time(vcpu);
2821 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2824 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2826 kvm_x86_ops->vcpu_put(vcpu);
2827 kvm_put_guest_fpu(vcpu);
2828 vcpu->arch.last_host_tsc = native_read_tsc();
2831 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2832 struct kvm_lapic_state *s)
2834 kvm_x86_ops->sync_pir_to_irr(vcpu);
2835 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2840 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2841 struct kvm_lapic_state *s)
2843 kvm_apic_post_state_restore(vcpu, s);
2844 update_cr8_intercept(vcpu);
2849 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2850 struct kvm_interrupt *irq)
2852 if (irq->irq >= KVM_NR_INTERRUPTS)
2854 if (irqchip_in_kernel(vcpu->kvm))
2857 kvm_queue_interrupt(vcpu, irq->irq, false);
2858 kvm_make_request(KVM_REQ_EVENT, vcpu);
2863 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2865 kvm_inject_nmi(vcpu);
2870 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2871 struct kvm_tpr_access_ctl *tac)
2875 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2879 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2883 unsigned bank_num = mcg_cap & 0xff, bank;
2886 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2888 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2891 vcpu->arch.mcg_cap = mcg_cap;
2892 /* Init IA32_MCG_CTL to all 1s */
2893 if (mcg_cap & MCG_CTL_P)
2894 vcpu->arch.mcg_ctl = ~(u64)0;
2895 /* Init IA32_MCi_CTL to all 1s */
2896 for (bank = 0; bank < bank_num; bank++)
2897 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2902 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2903 struct kvm_x86_mce *mce)
2905 u64 mcg_cap = vcpu->arch.mcg_cap;
2906 unsigned bank_num = mcg_cap & 0xff;
2907 u64 *banks = vcpu->arch.mce_banks;
2909 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2912 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2913 * reporting is disabled
2915 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2916 vcpu->arch.mcg_ctl != ~(u64)0)
2918 banks += 4 * mce->bank;
2920 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2921 * reporting is disabled for the bank
2923 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2925 if (mce->status & MCI_STATUS_UC) {
2926 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2927 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2928 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2931 if (banks[1] & MCI_STATUS_VAL)
2932 mce->status |= MCI_STATUS_OVER;
2933 banks[2] = mce->addr;
2934 banks[3] = mce->misc;
2935 vcpu->arch.mcg_status = mce->mcg_status;
2936 banks[1] = mce->status;
2937 kvm_queue_exception(vcpu, MC_VECTOR);
2938 } else if (!(banks[1] & MCI_STATUS_VAL)
2939 || !(banks[1] & MCI_STATUS_UC)) {
2940 if (banks[1] & MCI_STATUS_VAL)
2941 mce->status |= MCI_STATUS_OVER;
2942 banks[2] = mce->addr;
2943 banks[3] = mce->misc;
2944 banks[1] = mce->status;
2946 banks[1] |= MCI_STATUS_OVER;
2950 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2951 struct kvm_vcpu_events *events)
2954 events->exception.injected =
2955 vcpu->arch.exception.pending &&
2956 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2957 events->exception.nr = vcpu->arch.exception.nr;
2958 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2959 events->exception.pad = 0;
2960 events->exception.error_code = vcpu->arch.exception.error_code;
2962 events->interrupt.injected =
2963 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2964 events->interrupt.nr = vcpu->arch.interrupt.nr;
2965 events->interrupt.soft = 0;
2966 events->interrupt.shadow =
2967 kvm_x86_ops->get_interrupt_shadow(vcpu,
2968 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2970 events->nmi.injected = vcpu->arch.nmi_injected;
2971 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2972 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2973 events->nmi.pad = 0;
2975 events->sipi_vector = 0; /* never valid when reporting to user space */
2977 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2978 | KVM_VCPUEVENT_VALID_SHADOW);
2979 memset(&events->reserved, 0, sizeof(events->reserved));
2982 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2983 struct kvm_vcpu_events *events)
2985 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2986 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2987 | KVM_VCPUEVENT_VALID_SHADOW))
2991 vcpu->arch.exception.pending = events->exception.injected;
2992 vcpu->arch.exception.nr = events->exception.nr;
2993 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2994 vcpu->arch.exception.error_code = events->exception.error_code;
2996 vcpu->arch.interrupt.pending = events->interrupt.injected;
2997 vcpu->arch.interrupt.nr = events->interrupt.nr;
2998 vcpu->arch.interrupt.soft = events->interrupt.soft;
2999 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3000 kvm_x86_ops->set_interrupt_shadow(vcpu,
3001 events->interrupt.shadow);
3003 vcpu->arch.nmi_injected = events->nmi.injected;
3004 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3005 vcpu->arch.nmi_pending = events->nmi.pending;
3006 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3008 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3009 kvm_vcpu_has_lapic(vcpu))
3010 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3012 kvm_make_request(KVM_REQ_EVENT, vcpu);
3017 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3018 struct kvm_debugregs *dbgregs)
3022 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3023 _kvm_get_dr(vcpu, 6, &val);
3025 dbgregs->dr7 = vcpu->arch.dr7;
3027 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3030 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3031 struct kvm_debugregs *dbgregs)
3036 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3037 vcpu->arch.dr6 = dbgregs->dr6;
3038 kvm_update_dr6(vcpu);
3039 vcpu->arch.dr7 = dbgregs->dr7;
3040 kvm_update_dr7(vcpu);
3045 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3046 struct kvm_xsave *guest_xsave)
3048 if (cpu_has_xsave) {
3049 memcpy(guest_xsave->region,
3050 &vcpu->arch.guest_fpu.state->xsave,
3051 vcpu->arch.guest_xstate_size);
3052 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3053 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3055 memcpy(guest_xsave->region,
3056 &vcpu->arch.guest_fpu.state->fxsave,
3057 sizeof(struct i387_fxsave_struct));
3058 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3063 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3064 struct kvm_xsave *guest_xsave)
3067 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3069 if (cpu_has_xsave) {
3071 * Here we allow setting states that are not present in
3072 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3073 * with old userspace.
3075 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3077 if (xstate_bv & ~host_xcr0)
3079 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3080 guest_xsave->region, vcpu->arch.guest_xstate_size);
3082 if (xstate_bv & ~XSTATE_FPSSE)
3084 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3085 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3090 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3091 struct kvm_xcrs *guest_xcrs)
3093 if (!cpu_has_xsave) {
3094 guest_xcrs->nr_xcrs = 0;
3098 guest_xcrs->nr_xcrs = 1;
3099 guest_xcrs->flags = 0;
3100 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3101 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3104 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3105 struct kvm_xcrs *guest_xcrs)
3112 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3115 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3116 /* Only support XCR0 currently */
3117 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3118 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3119 guest_xcrs->xcrs[i].value);
3128 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3129 * stopped by the hypervisor. This function will be called from the host only.
3130 * EINVAL is returned when the host attempts to set the flag for a guest that
3131 * does not support pv clocks.
3133 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3135 if (!vcpu->arch.pv_time_enabled)
3137 vcpu->arch.pvclock_set_guest_stopped_request = true;
3138 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3142 long kvm_arch_vcpu_ioctl(struct file *filp,
3143 unsigned int ioctl, unsigned long arg)
3145 struct kvm_vcpu *vcpu = filp->private_data;
3146 void __user *argp = (void __user *)arg;
3149 struct kvm_lapic_state *lapic;
3150 struct kvm_xsave *xsave;
3151 struct kvm_xcrs *xcrs;
3157 case KVM_GET_LAPIC: {
3159 if (!vcpu->arch.apic)
3161 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3166 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3170 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3175 case KVM_SET_LAPIC: {
3177 if (!vcpu->arch.apic)
3179 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3180 if (IS_ERR(u.lapic))
3181 return PTR_ERR(u.lapic);
3183 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3186 case KVM_INTERRUPT: {
3187 struct kvm_interrupt irq;
3190 if (copy_from_user(&irq, argp, sizeof irq))
3192 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3196 r = kvm_vcpu_ioctl_nmi(vcpu);
3199 case KVM_SET_CPUID: {
3200 struct kvm_cpuid __user *cpuid_arg = argp;
3201 struct kvm_cpuid cpuid;
3204 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3206 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3209 case KVM_SET_CPUID2: {
3210 struct kvm_cpuid2 __user *cpuid_arg = argp;
3211 struct kvm_cpuid2 cpuid;
3214 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3216 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3217 cpuid_arg->entries);
3220 case KVM_GET_CPUID2: {
3221 struct kvm_cpuid2 __user *cpuid_arg = argp;
3222 struct kvm_cpuid2 cpuid;
3225 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3227 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3228 cpuid_arg->entries);
3232 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3238 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3241 r = msr_io(vcpu, argp, do_set_msr, 0);
3243 case KVM_TPR_ACCESS_REPORTING: {
3244 struct kvm_tpr_access_ctl tac;
3247 if (copy_from_user(&tac, argp, sizeof tac))
3249 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3253 if (copy_to_user(argp, &tac, sizeof tac))
3258 case KVM_SET_VAPIC_ADDR: {
3259 struct kvm_vapic_addr va;
3262 if (!irqchip_in_kernel(vcpu->kvm))
3265 if (copy_from_user(&va, argp, sizeof va))
3267 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3270 case KVM_X86_SETUP_MCE: {
3274 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3276 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3279 case KVM_X86_SET_MCE: {
3280 struct kvm_x86_mce mce;
3283 if (copy_from_user(&mce, argp, sizeof mce))
3285 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3288 case KVM_GET_VCPU_EVENTS: {
3289 struct kvm_vcpu_events events;
3291 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3294 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3299 case KVM_SET_VCPU_EVENTS: {
3300 struct kvm_vcpu_events events;
3303 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3306 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3309 case KVM_GET_DEBUGREGS: {
3310 struct kvm_debugregs dbgregs;
3312 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3315 if (copy_to_user(argp, &dbgregs,
3316 sizeof(struct kvm_debugregs)))
3321 case KVM_SET_DEBUGREGS: {
3322 struct kvm_debugregs dbgregs;
3325 if (copy_from_user(&dbgregs, argp,
3326 sizeof(struct kvm_debugregs)))
3329 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3332 case KVM_GET_XSAVE: {
3333 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3338 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3341 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3346 case KVM_SET_XSAVE: {
3347 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3348 if (IS_ERR(u.xsave))
3349 return PTR_ERR(u.xsave);
3351 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3354 case KVM_GET_XCRS: {
3355 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3360 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3363 if (copy_to_user(argp, u.xcrs,
3364 sizeof(struct kvm_xcrs)))
3369 case KVM_SET_XCRS: {
3370 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3372 return PTR_ERR(u.xcrs);
3374 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3377 case KVM_SET_TSC_KHZ: {
3381 user_tsc_khz = (u32)arg;
3383 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3386 if (user_tsc_khz == 0)
3387 user_tsc_khz = tsc_khz;
3389 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3394 case KVM_GET_TSC_KHZ: {
3395 r = vcpu->arch.virtual_tsc_khz;
3398 case KVM_KVMCLOCK_CTRL: {
3399 r = kvm_set_guest_paused(vcpu);
3410 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3412 return VM_FAULT_SIGBUS;
3415 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3419 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3421 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3425 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3428 kvm->arch.ept_identity_map_addr = ident_addr;
3432 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3433 u32 kvm_nr_mmu_pages)
3435 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3438 mutex_lock(&kvm->slots_lock);
3440 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3441 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3443 mutex_unlock(&kvm->slots_lock);
3447 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3449 return kvm->arch.n_max_mmu_pages;
3452 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3457 switch (chip->chip_id) {
3458 case KVM_IRQCHIP_PIC_MASTER:
3459 memcpy(&chip->chip.pic,
3460 &pic_irqchip(kvm)->pics[0],
3461 sizeof(struct kvm_pic_state));
3463 case KVM_IRQCHIP_PIC_SLAVE:
3464 memcpy(&chip->chip.pic,
3465 &pic_irqchip(kvm)->pics[1],
3466 sizeof(struct kvm_pic_state));
3468 case KVM_IRQCHIP_IOAPIC:
3469 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3478 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3483 switch (chip->chip_id) {
3484 case KVM_IRQCHIP_PIC_MASTER:
3485 spin_lock(&pic_irqchip(kvm)->lock);
3486 memcpy(&pic_irqchip(kvm)->pics[0],
3488 sizeof(struct kvm_pic_state));
3489 spin_unlock(&pic_irqchip(kvm)->lock);
3491 case KVM_IRQCHIP_PIC_SLAVE:
3492 spin_lock(&pic_irqchip(kvm)->lock);
3493 memcpy(&pic_irqchip(kvm)->pics[1],
3495 sizeof(struct kvm_pic_state));
3496 spin_unlock(&pic_irqchip(kvm)->lock);
3498 case KVM_IRQCHIP_IOAPIC:
3499 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3505 kvm_pic_update_irq(pic_irqchip(kvm));
3509 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3513 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3514 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3515 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3519 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3523 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3524 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3525 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3526 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3530 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3534 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3535 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3536 sizeof(ps->channels));
3537 ps->flags = kvm->arch.vpit->pit_state.flags;
3538 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3539 memset(&ps->reserved, 0, sizeof(ps->reserved));
3543 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3545 int r = 0, start = 0;
3546 u32 prev_legacy, cur_legacy;
3547 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3548 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3549 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3550 if (!prev_legacy && cur_legacy)
3552 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3553 sizeof(kvm->arch.vpit->pit_state.channels));
3554 kvm->arch.vpit->pit_state.flags = ps->flags;
3555 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3556 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3560 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3561 struct kvm_reinject_control *control)
3563 if (!kvm->arch.vpit)
3565 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3566 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3567 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3572 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3573 * @kvm: kvm instance
3574 * @log: slot id and address to which we copy the log
3576 * We need to keep it in mind that VCPU threads can write to the bitmap
3577 * concurrently. So, to avoid losing data, we keep the following order for
3580 * 1. Take a snapshot of the bit and clear it if needed.
3581 * 2. Write protect the corresponding page.
3582 * 3. Flush TLB's if needed.
3583 * 4. Copy the snapshot to the userspace.
3585 * Between 2 and 3, the guest may write to the page using the remaining TLB
3586 * entry. This is not a problem because the page will be reported dirty at
3587 * step 4 using the snapshot taken before and step 3 ensures that successive
3588 * writes will be logged for the next call.
3590 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3593 struct kvm_memory_slot *memslot;
3595 unsigned long *dirty_bitmap;
3596 unsigned long *dirty_bitmap_buffer;
3597 bool is_dirty = false;
3599 mutex_lock(&kvm->slots_lock);
3602 if (log->slot >= KVM_USER_MEM_SLOTS)
3605 memslot = id_to_memslot(kvm->memslots, log->slot);
3607 dirty_bitmap = memslot->dirty_bitmap;
3612 n = kvm_dirty_bitmap_bytes(memslot);
3614 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3615 memset(dirty_bitmap_buffer, 0, n);
3617 spin_lock(&kvm->mmu_lock);
3619 for (i = 0; i < n / sizeof(long); i++) {
3623 if (!dirty_bitmap[i])
3628 mask = xchg(&dirty_bitmap[i], 0);
3629 dirty_bitmap_buffer[i] = mask;
3631 offset = i * BITS_PER_LONG;
3632 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3635 kvm_flush_remote_tlbs(kvm);
3637 spin_unlock(&kvm->mmu_lock);
3640 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3645 mutex_unlock(&kvm->slots_lock);
3649 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3652 if (!irqchip_in_kernel(kvm))
3655 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3656 irq_event->irq, irq_event->level,
3661 long kvm_arch_vm_ioctl(struct file *filp,
3662 unsigned int ioctl, unsigned long arg)
3664 struct kvm *kvm = filp->private_data;
3665 void __user *argp = (void __user *)arg;
3668 * This union makes it completely explicit to gcc-3.x
3669 * that these two variables' stack usage should be
3670 * combined, not added together.
3673 struct kvm_pit_state ps;
3674 struct kvm_pit_state2 ps2;
3675 struct kvm_pit_config pit_config;
3679 case KVM_SET_TSS_ADDR:
3680 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3682 case KVM_SET_IDENTITY_MAP_ADDR: {
3686 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3688 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3691 case KVM_SET_NR_MMU_PAGES:
3692 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3694 case KVM_GET_NR_MMU_PAGES:
3695 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3697 case KVM_CREATE_IRQCHIP: {
3698 struct kvm_pic *vpic;
3700 mutex_lock(&kvm->lock);
3703 goto create_irqchip_unlock;
3705 if (atomic_read(&kvm->online_vcpus))
3706 goto create_irqchip_unlock;
3708 vpic = kvm_create_pic(kvm);
3710 r = kvm_ioapic_init(kvm);
3712 mutex_lock(&kvm->slots_lock);
3713 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3715 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3717 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3719 mutex_unlock(&kvm->slots_lock);
3721 goto create_irqchip_unlock;
3724 goto create_irqchip_unlock;
3726 kvm->arch.vpic = vpic;
3728 r = kvm_setup_default_irq_routing(kvm);
3730 mutex_lock(&kvm->slots_lock);
3731 mutex_lock(&kvm->irq_lock);
3732 kvm_ioapic_destroy(kvm);
3733 kvm_destroy_pic(kvm);
3734 mutex_unlock(&kvm->irq_lock);
3735 mutex_unlock(&kvm->slots_lock);
3737 create_irqchip_unlock:
3738 mutex_unlock(&kvm->lock);
3741 case KVM_CREATE_PIT:
3742 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3744 case KVM_CREATE_PIT2:
3746 if (copy_from_user(&u.pit_config, argp,
3747 sizeof(struct kvm_pit_config)))
3750 mutex_lock(&kvm->slots_lock);
3753 goto create_pit_unlock;
3755 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3759 mutex_unlock(&kvm->slots_lock);
3761 case KVM_GET_IRQCHIP: {
3762 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3763 struct kvm_irqchip *chip;
3765 chip = memdup_user(argp, sizeof(*chip));
3772 if (!irqchip_in_kernel(kvm))
3773 goto get_irqchip_out;
3774 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3776 goto get_irqchip_out;
3778 if (copy_to_user(argp, chip, sizeof *chip))
3779 goto get_irqchip_out;
3785 case KVM_SET_IRQCHIP: {
3786 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3787 struct kvm_irqchip *chip;
3789 chip = memdup_user(argp, sizeof(*chip));
3796 if (!irqchip_in_kernel(kvm))
3797 goto set_irqchip_out;
3798 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3800 goto set_irqchip_out;
3808 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3811 if (!kvm->arch.vpit)
3813 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3817 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3824 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3827 if (!kvm->arch.vpit)
3829 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3832 case KVM_GET_PIT2: {
3834 if (!kvm->arch.vpit)
3836 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3840 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3845 case KVM_SET_PIT2: {
3847 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3850 if (!kvm->arch.vpit)
3852 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3855 case KVM_REINJECT_CONTROL: {
3856 struct kvm_reinject_control control;
3858 if (copy_from_user(&control, argp, sizeof(control)))
3860 r = kvm_vm_ioctl_reinject(kvm, &control);
3863 case KVM_XEN_HVM_CONFIG: {
3865 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3866 sizeof(struct kvm_xen_hvm_config)))
3869 if (kvm->arch.xen_hvm_config.flags)
3874 case KVM_SET_CLOCK: {
3875 struct kvm_clock_data user_ns;
3880 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3888 local_irq_disable();
3889 now_ns = get_kernel_ns();
3890 delta = user_ns.clock - now_ns;
3892 kvm->arch.kvmclock_offset = delta;
3893 kvm_gen_update_masterclock(kvm);
3896 case KVM_GET_CLOCK: {
3897 struct kvm_clock_data user_ns;
3900 local_irq_disable();
3901 now_ns = get_kernel_ns();
3902 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3905 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3908 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3921 static void kvm_init_msr_list(void)
3926 /* skip the first msrs in the list. KVM-specific */
3927 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3928 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3931 msrs_to_save[j] = msrs_to_save[i];
3934 num_msrs_to_save = j;
3937 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3945 if (!(vcpu->arch.apic &&
3946 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3947 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3958 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3965 if (!(vcpu->arch.apic &&
3966 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3967 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3969 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3979 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3980 struct kvm_segment *var, int seg)
3982 kvm_x86_ops->set_segment(vcpu, var, seg);
3985 void kvm_get_segment(struct kvm_vcpu *vcpu,
3986 struct kvm_segment *var, int seg)
3988 kvm_x86_ops->get_segment(vcpu, var, seg);
3991 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3994 struct x86_exception exception;
3996 BUG_ON(!mmu_is_nested(vcpu));
3998 /* NPT walks are always user-walks */
3999 access |= PFERR_USER_MASK;
4000 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
4005 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4006 struct x86_exception *exception)
4008 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4009 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4012 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4013 struct x86_exception *exception)
4015 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4016 access |= PFERR_FETCH_MASK;
4017 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4020 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4021 struct x86_exception *exception)
4023 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4024 access |= PFERR_WRITE_MASK;
4025 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4028 /* uses this to access any guest's mapped memory without checking CPL */
4029 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4030 struct x86_exception *exception)
4032 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4035 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4036 struct kvm_vcpu *vcpu, u32 access,
4037 struct x86_exception *exception)
4040 int r = X86EMUL_CONTINUE;
4043 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4045 unsigned offset = addr & (PAGE_SIZE-1);
4046 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4049 if (gpa == UNMAPPED_GVA)
4050 return X86EMUL_PROPAGATE_FAULT;
4051 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
4053 r = X86EMUL_IO_NEEDED;
4065 /* used for instruction fetching */
4066 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4067 gva_t addr, void *val, unsigned int bytes,
4068 struct x86_exception *exception)
4070 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4071 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4073 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4074 access | PFERR_FETCH_MASK,
4078 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4079 gva_t addr, void *val, unsigned int bytes,
4080 struct x86_exception *exception)
4082 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4083 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4085 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4088 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4090 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4091 gva_t addr, void *val, unsigned int bytes,
4092 struct x86_exception *exception)
4094 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4095 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4098 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4099 gva_t addr, void *val,
4101 struct x86_exception *exception)
4103 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4105 int r = X86EMUL_CONTINUE;
4108 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4111 unsigned offset = addr & (PAGE_SIZE-1);
4112 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4115 if (gpa == UNMAPPED_GVA)
4116 return X86EMUL_PROPAGATE_FAULT;
4117 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4119 r = X86EMUL_IO_NEEDED;
4130 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4132 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4133 gpa_t *gpa, struct x86_exception *exception,
4136 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4137 | (write ? PFERR_WRITE_MASK : 0);
4139 if (vcpu_match_mmio_gva(vcpu, gva)
4140 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
4141 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4142 (gva & (PAGE_SIZE - 1));
4143 trace_vcpu_match_mmio(gva, *gpa, write, false);
4147 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4149 if (*gpa == UNMAPPED_GVA)
4152 /* For APIC access vmexit */
4153 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4156 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4157 trace_vcpu_match_mmio(gva, *gpa, write, true);
4164 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4165 const void *val, int bytes)
4169 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4172 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4176 struct read_write_emulator_ops {
4177 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4179 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4180 void *val, int bytes);
4181 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4182 int bytes, void *val);
4183 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4184 void *val, int bytes);
4188 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4190 if (vcpu->mmio_read_completed) {
4191 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4192 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4193 vcpu->mmio_read_completed = 0;
4200 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4201 void *val, int bytes)
4203 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4206 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4207 void *val, int bytes)
4209 return emulator_write_phys(vcpu, gpa, val, bytes);
4212 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4214 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4215 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4218 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4219 void *val, int bytes)
4221 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4222 return X86EMUL_IO_NEEDED;
4225 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4226 void *val, int bytes)
4228 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4230 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4231 return X86EMUL_CONTINUE;
4234 static const struct read_write_emulator_ops read_emultor = {
4235 .read_write_prepare = read_prepare,
4236 .read_write_emulate = read_emulate,
4237 .read_write_mmio = vcpu_mmio_read,
4238 .read_write_exit_mmio = read_exit_mmio,
4241 static const struct read_write_emulator_ops write_emultor = {
4242 .read_write_emulate = write_emulate,
4243 .read_write_mmio = write_mmio,
4244 .read_write_exit_mmio = write_exit_mmio,
4248 static int emulator_read_write_onepage(unsigned long addr, void *val,
4250 struct x86_exception *exception,
4251 struct kvm_vcpu *vcpu,
4252 const struct read_write_emulator_ops *ops)
4256 bool write = ops->write;
4257 struct kvm_mmio_fragment *frag;
4259 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4262 return X86EMUL_PROPAGATE_FAULT;
4264 /* For APIC access vmexit */
4268 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4269 return X86EMUL_CONTINUE;
4273 * Is this MMIO handled locally?
4275 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4276 if (handled == bytes)
4277 return X86EMUL_CONTINUE;
4283 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4284 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4288 return X86EMUL_CONTINUE;
4291 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4292 void *val, unsigned int bytes,
4293 struct x86_exception *exception,
4294 const struct read_write_emulator_ops *ops)
4296 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4300 if (ops->read_write_prepare &&
4301 ops->read_write_prepare(vcpu, val, bytes))
4302 return X86EMUL_CONTINUE;
4304 vcpu->mmio_nr_fragments = 0;
4306 /* Crossing a page boundary? */
4307 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4310 now = -addr & ~PAGE_MASK;
4311 rc = emulator_read_write_onepage(addr, val, now, exception,
4314 if (rc != X86EMUL_CONTINUE)
4321 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4323 if (rc != X86EMUL_CONTINUE)
4326 if (!vcpu->mmio_nr_fragments)
4329 gpa = vcpu->mmio_fragments[0].gpa;
4331 vcpu->mmio_needed = 1;
4332 vcpu->mmio_cur_fragment = 0;
4334 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4335 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4336 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4337 vcpu->run->mmio.phys_addr = gpa;
4339 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4342 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4346 struct x86_exception *exception)
4348 return emulator_read_write(ctxt, addr, val, bytes,
4349 exception, &read_emultor);
4352 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4356 struct x86_exception *exception)
4358 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4359 exception, &write_emultor);
4362 #define CMPXCHG_TYPE(t, ptr, old, new) \
4363 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4365 #ifdef CONFIG_X86_64
4366 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4368 # define CMPXCHG64(ptr, old, new) \
4369 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4372 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4377 struct x86_exception *exception)
4379 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4385 /* guests cmpxchg8b have to be emulated atomically */
4386 if (bytes > 8 || (bytes & (bytes - 1)))
4389 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4391 if (gpa == UNMAPPED_GVA ||
4392 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4395 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4398 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4399 if (is_error_page(page))
4402 kaddr = kmap_atomic(page);
4403 kaddr += offset_in_page(gpa);
4406 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4409 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4412 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4415 exchanged = CMPXCHG64(kaddr, old, new);
4420 kunmap_atomic(kaddr);
4421 kvm_release_page_dirty(page);
4424 return X86EMUL_CMPXCHG_FAILED;
4426 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4428 return X86EMUL_CONTINUE;
4431 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4433 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4436 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4438 /* TODO: String I/O for in kernel device */
4441 if (vcpu->arch.pio.in)
4442 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4443 vcpu->arch.pio.size, pd);
4445 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4446 vcpu->arch.pio.port, vcpu->arch.pio.size,
4451 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4452 unsigned short port, void *val,
4453 unsigned int count, bool in)
4455 trace_kvm_pio(!in, port, size, count);
4457 vcpu->arch.pio.port = port;
4458 vcpu->arch.pio.in = in;
4459 vcpu->arch.pio.count = count;
4460 vcpu->arch.pio.size = size;
4462 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4463 vcpu->arch.pio.count = 0;
4467 vcpu->run->exit_reason = KVM_EXIT_IO;
4468 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4469 vcpu->run->io.size = size;
4470 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4471 vcpu->run->io.count = count;
4472 vcpu->run->io.port = port;
4477 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4478 int size, unsigned short port, void *val,
4481 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4484 if (vcpu->arch.pio.count)
4487 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4490 memcpy(val, vcpu->arch.pio_data, size * count);
4491 vcpu->arch.pio.count = 0;
4498 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4499 int size, unsigned short port,
4500 const void *val, unsigned int count)
4502 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4504 memcpy(vcpu->arch.pio_data, val, size * count);
4505 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4508 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4510 return kvm_x86_ops->get_segment_base(vcpu, seg);
4513 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4515 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4518 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4520 if (!need_emulate_wbinvd(vcpu))
4521 return X86EMUL_CONTINUE;
4523 if (kvm_x86_ops->has_wbinvd_exit()) {
4524 int cpu = get_cpu();
4526 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4527 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4528 wbinvd_ipi, NULL, 1);
4530 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4533 return X86EMUL_CONTINUE;
4535 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4537 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4539 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4542 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4544 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4547 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4550 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4553 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4555 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4558 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4560 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4561 unsigned long value;
4565 value = kvm_read_cr0(vcpu);
4568 value = vcpu->arch.cr2;
4571 value = kvm_read_cr3(vcpu);
4574 value = kvm_read_cr4(vcpu);
4577 value = kvm_get_cr8(vcpu);
4580 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4587 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4589 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4594 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4597 vcpu->arch.cr2 = val;
4600 res = kvm_set_cr3(vcpu, val);
4603 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4606 res = kvm_set_cr8(vcpu, val);
4609 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4616 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4618 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4621 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4623 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4626 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4628 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4631 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4633 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4636 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4638 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4641 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4643 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4646 static unsigned long emulator_get_cached_segment_base(
4647 struct x86_emulate_ctxt *ctxt, int seg)
4649 return get_segment_base(emul_to_vcpu(ctxt), seg);
4652 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4653 struct desc_struct *desc, u32 *base3,
4656 struct kvm_segment var;
4658 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4659 *selector = var.selector;
4662 memset(desc, 0, sizeof(*desc));
4668 set_desc_limit(desc, var.limit);
4669 set_desc_base(desc, (unsigned long)var.base);
4670 #ifdef CONFIG_X86_64
4672 *base3 = var.base >> 32;
4674 desc->type = var.type;
4676 desc->dpl = var.dpl;
4677 desc->p = var.present;
4678 desc->avl = var.avl;
4686 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4687 struct desc_struct *desc, u32 base3,
4690 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4691 struct kvm_segment var;
4693 var.selector = selector;
4694 var.base = get_desc_base(desc);
4695 #ifdef CONFIG_X86_64
4696 var.base |= ((u64)base3) << 32;
4698 var.limit = get_desc_limit(desc);
4700 var.limit = (var.limit << 12) | 0xfff;
4701 var.type = desc->type;
4702 var.present = desc->p;
4703 var.dpl = desc->dpl;
4708 var.avl = desc->avl;
4709 var.present = desc->p;
4710 var.unusable = !var.present;
4713 kvm_set_segment(vcpu, &var, seg);
4717 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4718 u32 msr_index, u64 *pdata)
4720 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4723 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4724 u32 msr_index, u64 data)
4726 struct msr_data msr;
4729 msr.index = msr_index;
4730 msr.host_initiated = false;
4731 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4734 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4735 u32 pmc, u64 *pdata)
4737 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4740 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4742 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4745 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4748 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4750 * CR0.TS may reference the host fpu state, not the guest fpu state,
4751 * so it may be clear at this point.
4756 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4761 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4762 struct x86_instruction_info *info,
4763 enum x86_intercept_stage stage)
4765 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4768 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4769 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4771 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4774 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4776 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4779 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4781 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4784 static const struct x86_emulate_ops emulate_ops = {
4785 .read_gpr = emulator_read_gpr,
4786 .write_gpr = emulator_write_gpr,
4787 .read_std = kvm_read_guest_virt_system,
4788 .write_std = kvm_write_guest_virt_system,
4789 .fetch = kvm_fetch_guest_virt,
4790 .read_emulated = emulator_read_emulated,
4791 .write_emulated = emulator_write_emulated,
4792 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4793 .invlpg = emulator_invlpg,
4794 .pio_in_emulated = emulator_pio_in_emulated,
4795 .pio_out_emulated = emulator_pio_out_emulated,
4796 .get_segment = emulator_get_segment,
4797 .set_segment = emulator_set_segment,
4798 .get_cached_segment_base = emulator_get_cached_segment_base,
4799 .get_gdt = emulator_get_gdt,
4800 .get_idt = emulator_get_idt,
4801 .set_gdt = emulator_set_gdt,
4802 .set_idt = emulator_set_idt,
4803 .get_cr = emulator_get_cr,
4804 .set_cr = emulator_set_cr,
4805 .set_rflags = emulator_set_rflags,
4806 .cpl = emulator_get_cpl,
4807 .get_dr = emulator_get_dr,
4808 .set_dr = emulator_set_dr,
4809 .set_msr = emulator_set_msr,
4810 .get_msr = emulator_get_msr,
4811 .read_pmc = emulator_read_pmc,
4812 .halt = emulator_halt,
4813 .wbinvd = emulator_wbinvd,
4814 .fix_hypercall = emulator_fix_hypercall,
4815 .get_fpu = emulator_get_fpu,
4816 .put_fpu = emulator_put_fpu,
4817 .intercept = emulator_intercept,
4818 .get_cpuid = emulator_get_cpuid,
4821 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4823 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4825 * an sti; sti; sequence only disable interrupts for the first
4826 * instruction. So, if the last instruction, be it emulated or
4827 * not, left the system with the INT_STI flag enabled, it
4828 * means that the last instruction is an sti. We should not
4829 * leave the flag on in this case. The same goes for mov ss
4831 if (!(int_shadow & mask))
4832 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4835 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4837 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4838 if (ctxt->exception.vector == PF_VECTOR)
4839 kvm_propagate_fault(vcpu, &ctxt->exception);
4840 else if (ctxt->exception.error_code_valid)
4841 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4842 ctxt->exception.error_code);
4844 kvm_queue_exception(vcpu, ctxt->exception.vector);
4847 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4849 memset(&ctxt->opcode_len, 0,
4850 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
4852 ctxt->fetch.start = 0;
4853 ctxt->fetch.end = 0;
4854 ctxt->io_read.pos = 0;
4855 ctxt->io_read.end = 0;
4856 ctxt->mem_read.pos = 0;
4857 ctxt->mem_read.end = 0;
4860 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4862 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4865 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4867 ctxt->eflags = kvm_get_rflags(vcpu);
4868 ctxt->eip = kvm_rip_read(vcpu);
4869 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4870 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4871 cs_l ? X86EMUL_MODE_PROT64 :
4872 cs_db ? X86EMUL_MODE_PROT32 :
4873 X86EMUL_MODE_PROT16;
4874 ctxt->guest_mode = is_guest_mode(vcpu);
4876 init_decode_cache(ctxt);
4877 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4880 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4882 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4885 init_emulate_ctxt(vcpu);
4889 ctxt->_eip = ctxt->eip + inc_eip;
4890 ret = emulate_int_real(ctxt, irq);
4892 if (ret != X86EMUL_CONTINUE)
4893 return EMULATE_FAIL;
4895 ctxt->eip = ctxt->_eip;
4896 kvm_rip_write(vcpu, ctxt->eip);
4897 kvm_set_rflags(vcpu, ctxt->eflags);
4899 if (irq == NMI_VECTOR)
4900 vcpu->arch.nmi_pending = 0;
4902 vcpu->arch.interrupt.pending = false;
4904 return EMULATE_DONE;
4906 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4908 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4910 int r = EMULATE_DONE;
4912 ++vcpu->stat.insn_emulation_fail;
4913 trace_kvm_emulate_insn_failed(vcpu);
4914 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
4915 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4916 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4917 vcpu->run->internal.ndata = 0;
4920 kvm_queue_exception(vcpu, UD_VECTOR);
4925 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4926 bool write_fault_to_shadow_pgtable,
4932 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4935 if (!vcpu->arch.mmu.direct_map) {
4937 * Write permission should be allowed since only
4938 * write access need to be emulated.
4940 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4943 * If the mapping is invalid in guest, let cpu retry
4944 * it to generate fault.
4946 if (gpa == UNMAPPED_GVA)
4951 * Do not retry the unhandleable instruction if it faults on the
4952 * readonly host memory, otherwise it will goto a infinite loop:
4953 * retry instruction -> write #PF -> emulation fail -> retry
4954 * instruction -> ...
4956 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4959 * If the instruction failed on the error pfn, it can not be fixed,
4960 * report the error to userspace.
4962 if (is_error_noslot_pfn(pfn))
4965 kvm_release_pfn_clean(pfn);
4967 /* The instructions are well-emulated on direct mmu. */
4968 if (vcpu->arch.mmu.direct_map) {
4969 unsigned int indirect_shadow_pages;
4971 spin_lock(&vcpu->kvm->mmu_lock);
4972 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4973 spin_unlock(&vcpu->kvm->mmu_lock);
4975 if (indirect_shadow_pages)
4976 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4982 * if emulation was due to access to shadowed page table
4983 * and it failed try to unshadow page and re-enter the
4984 * guest to let CPU execute the instruction.
4986 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4989 * If the access faults on its page table, it can not
4990 * be fixed by unprotecting shadow page and it should
4991 * be reported to userspace.
4993 return !write_fault_to_shadow_pgtable;
4996 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4997 unsigned long cr2, int emulation_type)
4999 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5000 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5002 last_retry_eip = vcpu->arch.last_retry_eip;
5003 last_retry_addr = vcpu->arch.last_retry_addr;
5006 * If the emulation is caused by #PF and it is non-page_table
5007 * writing instruction, it means the VM-EXIT is caused by shadow
5008 * page protected, we can zap the shadow page and retry this
5009 * instruction directly.
5011 * Note: if the guest uses a non-page-table modifying instruction
5012 * on the PDE that points to the instruction, then we will unmap
5013 * the instruction and go to an infinite loop. So, we cache the
5014 * last retried eip and the last fault address, if we meet the eip
5015 * and the address again, we can break out of the potential infinite
5018 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5020 if (!(emulation_type & EMULTYPE_RETRY))
5023 if (x86_page_table_writing_insn(ctxt))
5026 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5029 vcpu->arch.last_retry_eip = ctxt->eip;
5030 vcpu->arch.last_retry_addr = cr2;
5032 if (!vcpu->arch.mmu.direct_map)
5033 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5035 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5040 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5041 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5043 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5052 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5053 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5058 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5060 struct kvm_run *kvm_run = vcpu->run;
5063 * Use the "raw" value to see if TF was passed to the processor.
5064 * Note that the new value of the flags has not been saved yet.
5066 * This is correct even for TF set by the guest, because "the
5067 * processor will not generate this exception after the instruction
5068 * that sets the TF flag".
5070 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5072 if (unlikely(rflags & X86_EFLAGS_TF)) {
5073 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5074 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5075 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5076 kvm_run->debug.arch.exception = DB_VECTOR;
5077 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5078 *r = EMULATE_USER_EXIT;
5080 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5082 * "Certain debug exceptions may clear bit 0-3. The
5083 * remaining contents of the DR6 register are never
5084 * cleared by the processor".
5086 vcpu->arch.dr6 &= ~15;
5087 vcpu->arch.dr6 |= DR6_BS;
5088 kvm_queue_exception(vcpu, DB_VECTOR);
5093 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5095 struct kvm_run *kvm_run = vcpu->run;
5096 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5099 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5100 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5101 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5102 vcpu->arch.guest_debug_dr7,
5106 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5107 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5108 get_segment_base(vcpu, VCPU_SREG_CS);
5110 kvm_run->debug.arch.exception = DB_VECTOR;
5111 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5112 *r = EMULATE_USER_EXIT;
5117 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5118 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5123 vcpu->arch.dr6 &= ~15;
5124 vcpu->arch.dr6 |= dr6;
5125 kvm_queue_exception(vcpu, DB_VECTOR);
5134 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5141 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5142 bool writeback = true;
5143 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5146 * Clear write_fault_to_shadow_pgtable here to ensure it is
5149 vcpu->arch.write_fault_to_shadow_pgtable = false;
5150 kvm_clear_exception_queue(vcpu);
5152 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5153 init_emulate_ctxt(vcpu);
5156 * We will reenter on the same instruction since
5157 * we do not set complete_userspace_io. This does not
5158 * handle watchpoints yet, those would be handled in
5161 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5164 ctxt->interruptibility = 0;
5165 ctxt->have_exception = false;
5166 ctxt->perm_ok = false;
5168 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5170 r = x86_decode_insn(ctxt, insn, insn_len);
5172 trace_kvm_emulate_insn_start(vcpu);
5173 ++vcpu->stat.insn_emulation;
5174 if (r != EMULATION_OK) {
5175 if (emulation_type & EMULTYPE_TRAP_UD)
5176 return EMULATE_FAIL;
5177 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5179 return EMULATE_DONE;
5180 if (emulation_type & EMULTYPE_SKIP)
5181 return EMULATE_FAIL;
5182 return handle_emulation_failure(vcpu);
5186 if (emulation_type & EMULTYPE_SKIP) {
5187 kvm_rip_write(vcpu, ctxt->_eip);
5188 return EMULATE_DONE;
5191 if (retry_instruction(ctxt, cr2, emulation_type))
5192 return EMULATE_DONE;
5194 /* this is needed for vmware backdoor interface to work since it
5195 changes registers values during IO operation */
5196 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5197 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5198 emulator_invalidate_register_cache(ctxt);
5202 r = x86_emulate_insn(ctxt);
5204 if (r == EMULATION_INTERCEPTED)
5205 return EMULATE_DONE;
5207 if (r == EMULATION_FAILED) {
5208 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5210 return EMULATE_DONE;
5212 return handle_emulation_failure(vcpu);
5215 if (ctxt->have_exception) {
5216 inject_emulated_exception(vcpu);
5218 } else if (vcpu->arch.pio.count) {
5219 if (!vcpu->arch.pio.in) {
5220 /* FIXME: return into emulator if single-stepping. */
5221 vcpu->arch.pio.count = 0;
5224 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5226 r = EMULATE_USER_EXIT;
5227 } else if (vcpu->mmio_needed) {
5228 if (!vcpu->mmio_is_write)
5230 r = EMULATE_USER_EXIT;
5231 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5232 } else if (r == EMULATION_RESTART)
5238 toggle_interruptibility(vcpu, ctxt->interruptibility);
5239 kvm_make_request(KVM_REQ_EVENT, vcpu);
5240 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5241 kvm_rip_write(vcpu, ctxt->eip);
5242 if (r == EMULATE_DONE)
5243 kvm_vcpu_check_singlestep(vcpu, &r);
5244 kvm_set_rflags(vcpu, ctxt->eflags);
5246 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5250 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5252 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5254 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5255 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5256 size, port, &val, 1);
5257 /* do not return to emulator after return from userspace */
5258 vcpu->arch.pio.count = 0;
5261 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5263 static void tsc_bad(void *info)
5265 __this_cpu_write(cpu_tsc_khz, 0);
5268 static void tsc_khz_changed(void *data)
5270 struct cpufreq_freqs *freq = data;
5271 unsigned long khz = 0;
5275 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5276 khz = cpufreq_quick_get(raw_smp_processor_id());
5279 __this_cpu_write(cpu_tsc_khz, khz);
5282 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5285 struct cpufreq_freqs *freq = data;
5287 struct kvm_vcpu *vcpu;
5288 int i, send_ipi = 0;
5291 * We allow guests to temporarily run on slowing clocks,
5292 * provided we notify them after, or to run on accelerating
5293 * clocks, provided we notify them before. Thus time never
5296 * However, we have a problem. We can't atomically update
5297 * the frequency of a given CPU from this function; it is
5298 * merely a notifier, which can be called from any CPU.
5299 * Changing the TSC frequency at arbitrary points in time
5300 * requires a recomputation of local variables related to
5301 * the TSC for each VCPU. We must flag these local variables
5302 * to be updated and be sure the update takes place with the
5303 * new frequency before any guests proceed.
5305 * Unfortunately, the combination of hotplug CPU and frequency
5306 * change creates an intractable locking scenario; the order
5307 * of when these callouts happen is undefined with respect to
5308 * CPU hotplug, and they can race with each other. As such,
5309 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5310 * undefined; you can actually have a CPU frequency change take
5311 * place in between the computation of X and the setting of the
5312 * variable. To protect against this problem, all updates of
5313 * the per_cpu tsc_khz variable are done in an interrupt
5314 * protected IPI, and all callers wishing to update the value
5315 * must wait for a synchronous IPI to complete (which is trivial
5316 * if the caller is on the CPU already). This establishes the
5317 * necessary total order on variable updates.
5319 * Note that because a guest time update may take place
5320 * anytime after the setting of the VCPU's request bit, the
5321 * correct TSC value must be set before the request. However,
5322 * to ensure the update actually makes it to any guest which
5323 * starts running in hardware virtualization between the set
5324 * and the acquisition of the spinlock, we must also ping the
5325 * CPU after setting the request bit.
5329 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5331 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5334 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5336 spin_lock(&kvm_lock);
5337 list_for_each_entry(kvm, &vm_list, vm_list) {
5338 kvm_for_each_vcpu(i, vcpu, kvm) {
5339 if (vcpu->cpu != freq->cpu)
5341 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5342 if (vcpu->cpu != smp_processor_id())
5346 spin_unlock(&kvm_lock);
5348 if (freq->old < freq->new && send_ipi) {
5350 * We upscale the frequency. Must make the guest
5351 * doesn't see old kvmclock values while running with
5352 * the new frequency, otherwise we risk the guest sees
5353 * time go backwards.
5355 * In case we update the frequency for another cpu
5356 * (which might be in guest context) send an interrupt
5357 * to kick the cpu out of guest context. Next time
5358 * guest context is entered kvmclock will be updated,
5359 * so the guest will not see stale values.
5361 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5366 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5367 .notifier_call = kvmclock_cpufreq_notifier
5370 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5371 unsigned long action, void *hcpu)
5373 unsigned int cpu = (unsigned long)hcpu;
5377 case CPU_DOWN_FAILED:
5378 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5380 case CPU_DOWN_PREPARE:
5381 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5387 static struct notifier_block kvmclock_cpu_notifier_block = {
5388 .notifier_call = kvmclock_cpu_notifier,
5389 .priority = -INT_MAX
5392 static void kvm_timer_init(void)
5396 max_tsc_khz = tsc_khz;
5397 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5398 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5399 #ifdef CONFIG_CPU_FREQ
5400 struct cpufreq_policy policy;
5401 memset(&policy, 0, sizeof(policy));
5403 cpufreq_get_policy(&policy, cpu);
5404 if (policy.cpuinfo.max_freq)
5405 max_tsc_khz = policy.cpuinfo.max_freq;
5408 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5409 CPUFREQ_TRANSITION_NOTIFIER);
5411 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5412 for_each_online_cpu(cpu)
5413 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5416 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5418 int kvm_is_in_guest(void)
5420 return __this_cpu_read(current_vcpu) != NULL;
5423 static int kvm_is_user_mode(void)
5427 if (__this_cpu_read(current_vcpu))
5428 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5430 return user_mode != 0;
5433 static unsigned long kvm_get_guest_ip(void)
5435 unsigned long ip = 0;
5437 if (__this_cpu_read(current_vcpu))
5438 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5443 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5444 .is_in_guest = kvm_is_in_guest,
5445 .is_user_mode = kvm_is_user_mode,
5446 .get_guest_ip = kvm_get_guest_ip,
5449 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5451 __this_cpu_write(current_vcpu, vcpu);
5453 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5455 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5457 __this_cpu_write(current_vcpu, NULL);
5459 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5461 static void kvm_set_mmio_spte_mask(void)
5464 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5467 * Set the reserved bits and the present bit of an paging-structure
5468 * entry to generate page fault with PFER.RSV = 1.
5470 /* Mask the reserved physical address bits. */
5471 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5473 /* Bit 62 is always reserved for 32bit host. */
5474 mask |= 0x3ull << 62;
5476 /* Set the present bit. */
5479 #ifdef CONFIG_X86_64
5481 * If reserved bit is not supported, clear the present bit to disable
5484 if (maxphyaddr == 52)
5488 kvm_mmu_set_mmio_spte_mask(mask);
5491 #ifdef CONFIG_X86_64
5492 static void pvclock_gtod_update_fn(struct work_struct *work)
5496 struct kvm_vcpu *vcpu;
5499 spin_lock(&kvm_lock);
5500 list_for_each_entry(kvm, &vm_list, vm_list)
5501 kvm_for_each_vcpu(i, vcpu, kvm)
5502 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5503 atomic_set(&kvm_guest_has_master_clock, 0);
5504 spin_unlock(&kvm_lock);
5507 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5510 * Notification about pvclock gtod data update.
5512 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5515 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5516 struct timekeeper *tk = priv;
5518 update_pvclock_gtod(tk);
5520 /* disable master clock if host does not trust, or does not
5521 * use, TSC clocksource
5523 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5524 atomic_read(&kvm_guest_has_master_clock) != 0)
5525 queue_work(system_long_wq, &pvclock_gtod_work);
5530 static struct notifier_block pvclock_gtod_notifier = {
5531 .notifier_call = pvclock_gtod_notify,
5535 int kvm_arch_init(void *opaque)
5538 struct kvm_x86_ops *ops = opaque;
5541 printk(KERN_ERR "kvm: already loaded the other module\n");
5546 if (!ops->cpu_has_kvm_support()) {
5547 printk(KERN_ERR "kvm: no hardware support\n");
5551 if (ops->disabled_by_bios()) {
5552 printk(KERN_ERR "kvm: disabled by bios\n");
5558 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5560 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5564 r = kvm_mmu_module_init();
5566 goto out_free_percpu;
5568 kvm_set_mmio_spte_mask();
5569 kvm_init_msr_list();
5572 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5573 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5577 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5580 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5583 #ifdef CONFIG_X86_64
5584 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5590 free_percpu(shared_msrs);
5595 void kvm_arch_exit(void)
5597 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5599 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5600 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5601 CPUFREQ_TRANSITION_NOTIFIER);
5602 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5603 #ifdef CONFIG_X86_64
5604 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5607 kvm_mmu_module_exit();
5608 free_percpu(shared_msrs);
5611 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5613 ++vcpu->stat.halt_exits;
5614 if (irqchip_in_kernel(vcpu->kvm)) {
5615 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5618 vcpu->run->exit_reason = KVM_EXIT_HLT;
5622 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5624 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5626 u64 param, ingpa, outgpa, ret;
5627 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5628 bool fast, longmode;
5632 * hypercall generates UD from non zero cpl and real mode
5635 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5636 kvm_queue_exception(vcpu, UD_VECTOR);
5640 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5641 longmode = is_long_mode(vcpu) && cs_l == 1;
5644 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5645 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5646 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5647 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5648 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5649 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5651 #ifdef CONFIG_X86_64
5653 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5654 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5655 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5659 code = param & 0xffff;
5660 fast = (param >> 16) & 0x1;
5661 rep_cnt = (param >> 32) & 0xfff;
5662 rep_idx = (param >> 48) & 0xfff;
5664 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5667 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5668 kvm_vcpu_on_spin(vcpu);
5671 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5675 ret = res | (((u64)rep_done & 0xfff) << 32);
5677 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5679 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5680 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5687 * kvm_pv_kick_cpu_op: Kick a vcpu.
5689 * @apicid - apicid of vcpu to be kicked.
5691 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5693 struct kvm_lapic_irq lapic_irq;
5695 lapic_irq.shorthand = 0;
5696 lapic_irq.dest_mode = 0;
5697 lapic_irq.dest_id = apicid;
5699 lapic_irq.delivery_mode = APIC_DM_REMRD;
5700 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5703 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5705 unsigned long nr, a0, a1, a2, a3, ret;
5708 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5709 return kvm_hv_hypercall(vcpu);
5711 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5712 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5713 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5714 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5715 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5717 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5719 if (!is_long_mode(vcpu)) {
5727 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5733 case KVM_HC_VAPIC_POLL_IRQ:
5736 case KVM_HC_KICK_CPU:
5737 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5745 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5746 ++vcpu->stat.hypercalls;
5749 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5751 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5753 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5754 char instruction[3];
5755 unsigned long rip = kvm_rip_read(vcpu);
5757 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5759 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5763 * Check if userspace requested an interrupt window, and that the
5764 * interrupt window is open.
5766 * No need to exit to userspace if we already have an interrupt queued.
5768 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5770 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5771 vcpu->run->request_interrupt_window &&
5772 kvm_arch_interrupt_allowed(vcpu));
5775 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5777 struct kvm_run *kvm_run = vcpu->run;
5779 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5780 kvm_run->cr8 = kvm_get_cr8(vcpu);
5781 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5782 if (irqchip_in_kernel(vcpu->kvm))
5783 kvm_run->ready_for_interrupt_injection = 1;
5785 kvm_run->ready_for_interrupt_injection =
5786 kvm_arch_interrupt_allowed(vcpu) &&
5787 !kvm_cpu_has_interrupt(vcpu) &&
5788 !kvm_event_needs_reinjection(vcpu);
5791 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5795 if (!kvm_x86_ops->update_cr8_intercept)
5798 if (!vcpu->arch.apic)
5801 if (!vcpu->arch.apic->vapic_addr)
5802 max_irr = kvm_lapic_find_highest_irr(vcpu);
5809 tpr = kvm_lapic_get_cr8(vcpu);
5811 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5814 static void inject_pending_event(struct kvm_vcpu *vcpu)
5816 /* try to reinject previous events if any */
5817 if (vcpu->arch.exception.pending) {
5818 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5819 vcpu->arch.exception.has_error_code,
5820 vcpu->arch.exception.error_code);
5821 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5822 vcpu->arch.exception.has_error_code,
5823 vcpu->arch.exception.error_code,
5824 vcpu->arch.exception.reinject);
5828 if (vcpu->arch.nmi_injected) {
5829 kvm_x86_ops->set_nmi(vcpu);
5833 if (vcpu->arch.interrupt.pending) {
5834 kvm_x86_ops->set_irq(vcpu);
5838 /* try to inject new event if pending */
5839 if (vcpu->arch.nmi_pending) {
5840 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5841 --vcpu->arch.nmi_pending;
5842 vcpu->arch.nmi_injected = true;
5843 kvm_x86_ops->set_nmi(vcpu);
5845 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5846 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5847 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5849 kvm_x86_ops->set_irq(vcpu);
5854 static void process_nmi(struct kvm_vcpu *vcpu)
5859 * x86 is limited to one NMI running, and one NMI pending after it.
5860 * If an NMI is already in progress, limit further NMIs to just one.
5861 * Otherwise, allow two (and we'll inject the first one immediately).
5863 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5866 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5867 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5868 kvm_make_request(KVM_REQ_EVENT, vcpu);
5871 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5873 u64 eoi_exit_bitmap[4];
5876 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5879 memset(eoi_exit_bitmap, 0, 32);
5882 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5883 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5884 kvm_apic_update_tmr(vcpu, tmr);
5888 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5889 * exiting to the userspace. Otherwise, the value will be returned to the
5892 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5895 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5896 vcpu->run->request_interrupt_window;
5897 bool req_immediate_exit = false;
5899 if (vcpu->requests) {
5900 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5901 kvm_mmu_unload(vcpu);
5902 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5903 __kvm_migrate_timers(vcpu);
5904 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5905 kvm_gen_update_masterclock(vcpu->kvm);
5906 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5907 kvm_gen_kvmclock_update(vcpu);
5908 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5909 r = kvm_guest_time_update(vcpu);
5913 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5914 kvm_mmu_sync_roots(vcpu);
5915 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5916 kvm_x86_ops->tlb_flush(vcpu);
5917 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5918 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5922 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5923 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5927 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5928 vcpu->fpu_active = 0;
5929 kvm_x86_ops->fpu_deactivate(vcpu);
5931 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5932 /* Page is swapped out. Do synthetic halt */
5933 vcpu->arch.apf.halted = true;
5937 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5938 record_steal_time(vcpu);
5939 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5941 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5942 kvm_handle_pmu_event(vcpu);
5943 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5944 kvm_deliver_pmi(vcpu);
5945 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5946 vcpu_scan_ioapic(vcpu);
5949 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5950 kvm_apic_accept_events(vcpu);
5951 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5956 inject_pending_event(vcpu);
5958 /* enable NMI/IRQ window open exits if needed */
5959 if (vcpu->arch.nmi_pending)
5960 req_immediate_exit =
5961 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
5962 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5963 req_immediate_exit =
5964 kvm_x86_ops->enable_irq_window(vcpu) != 0;
5966 if (kvm_lapic_enabled(vcpu)) {
5968 * Update architecture specific hints for APIC
5969 * virtual interrupt delivery.
5971 if (kvm_x86_ops->hwapic_irr_update)
5972 kvm_x86_ops->hwapic_irr_update(vcpu,
5973 kvm_lapic_find_highest_irr(vcpu));
5974 update_cr8_intercept(vcpu);
5975 kvm_lapic_sync_to_vapic(vcpu);
5979 r = kvm_mmu_reload(vcpu);
5981 goto cancel_injection;
5986 kvm_x86_ops->prepare_guest_switch(vcpu);
5987 if (vcpu->fpu_active)
5988 kvm_load_guest_fpu(vcpu);
5989 kvm_load_guest_xcr0(vcpu);
5991 vcpu->mode = IN_GUEST_MODE;
5993 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5995 /* We should set ->mode before check ->requests,
5996 * see the comment in make_all_cpus_request.
5998 smp_mb__after_srcu_read_unlock();
6000 local_irq_disable();
6002 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6003 || need_resched() || signal_pending(current)) {
6004 vcpu->mode = OUTSIDE_GUEST_MODE;
6008 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6010 goto cancel_injection;
6013 if (req_immediate_exit)
6014 smp_send_reschedule(vcpu->cpu);
6018 if (unlikely(vcpu->arch.switch_db_regs)) {
6020 set_debugreg(vcpu->arch.eff_db[0], 0);
6021 set_debugreg(vcpu->arch.eff_db[1], 1);
6022 set_debugreg(vcpu->arch.eff_db[2], 2);
6023 set_debugreg(vcpu->arch.eff_db[3], 3);
6026 trace_kvm_entry(vcpu->vcpu_id);
6027 kvm_x86_ops->run(vcpu);
6030 * If the guest has used debug registers, at least dr7
6031 * will be disabled while returning to the host.
6032 * If we don't have active breakpoints in the host, we don't
6033 * care about the messed up debug address registers. But if
6034 * we have some of them active, restore the old state.
6036 if (hw_breakpoint_active())
6037 hw_breakpoint_restore();
6039 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6042 vcpu->mode = OUTSIDE_GUEST_MODE;
6045 /* Interrupt is enabled by handle_external_intr() */
6046 kvm_x86_ops->handle_external_intr(vcpu);
6051 * We must have an instruction between local_irq_enable() and
6052 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6053 * the interrupt shadow. The stat.exits increment will do nicely.
6054 * But we need to prevent reordering, hence this barrier():
6062 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6065 * Profile KVM exit RIPs:
6067 if (unlikely(prof_on == KVM_PROFILING)) {
6068 unsigned long rip = kvm_rip_read(vcpu);
6069 profile_hit(KVM_PROFILING, (void *)rip);
6072 if (unlikely(vcpu->arch.tsc_always_catchup))
6073 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6075 if (vcpu->arch.apic_attention)
6076 kvm_lapic_sync_from_vapic(vcpu);
6078 r = kvm_x86_ops->handle_exit(vcpu);
6082 kvm_x86_ops->cancel_injection(vcpu);
6083 if (unlikely(vcpu->arch.apic_attention))
6084 kvm_lapic_sync_from_vapic(vcpu);
6090 static int __vcpu_run(struct kvm_vcpu *vcpu)
6093 struct kvm *kvm = vcpu->kvm;
6095 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6099 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6100 !vcpu->arch.apf.halted)
6101 r = vcpu_enter_guest(vcpu);
6103 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6104 kvm_vcpu_block(vcpu);
6105 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6106 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6107 kvm_apic_accept_events(vcpu);
6108 switch(vcpu->arch.mp_state) {
6109 case KVM_MP_STATE_HALTED:
6110 vcpu->arch.pv.pv_unhalted = false;
6111 vcpu->arch.mp_state =
6112 KVM_MP_STATE_RUNNABLE;
6113 case KVM_MP_STATE_RUNNABLE:
6114 vcpu->arch.apf.halted = false;
6116 case KVM_MP_STATE_INIT_RECEIVED:
6128 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6129 if (kvm_cpu_has_pending_timer(vcpu))
6130 kvm_inject_pending_timer_irqs(vcpu);
6132 if (dm_request_for_irq_injection(vcpu)) {
6134 vcpu->run->exit_reason = KVM_EXIT_INTR;
6135 ++vcpu->stat.request_irq_exits;
6138 kvm_check_async_pf_completion(vcpu);
6140 if (signal_pending(current)) {
6142 vcpu->run->exit_reason = KVM_EXIT_INTR;
6143 ++vcpu->stat.signal_exits;
6145 if (need_resched()) {
6146 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6148 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6152 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6157 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6160 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6161 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6162 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6163 if (r != EMULATE_DONE)
6168 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6170 BUG_ON(!vcpu->arch.pio.count);
6172 return complete_emulated_io(vcpu);
6176 * Implements the following, as a state machine:
6180 * for each mmio piece in the fragment
6188 * for each mmio piece in the fragment
6193 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6195 struct kvm_run *run = vcpu->run;
6196 struct kvm_mmio_fragment *frag;
6199 BUG_ON(!vcpu->mmio_needed);
6201 /* Complete previous fragment */
6202 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6203 len = min(8u, frag->len);
6204 if (!vcpu->mmio_is_write)
6205 memcpy(frag->data, run->mmio.data, len);
6207 if (frag->len <= 8) {
6208 /* Switch to the next fragment. */
6210 vcpu->mmio_cur_fragment++;
6212 /* Go forward to the next mmio piece. */
6218 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6219 vcpu->mmio_needed = 0;
6221 /* FIXME: return into emulator if single-stepping. */
6222 if (vcpu->mmio_is_write)
6224 vcpu->mmio_read_completed = 1;
6225 return complete_emulated_io(vcpu);
6228 run->exit_reason = KVM_EXIT_MMIO;
6229 run->mmio.phys_addr = frag->gpa;
6230 if (vcpu->mmio_is_write)
6231 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6232 run->mmio.len = min(8u, frag->len);
6233 run->mmio.is_write = vcpu->mmio_is_write;
6234 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6239 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6244 if (!tsk_used_math(current) && init_fpu(current))
6247 if (vcpu->sigset_active)
6248 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6250 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6251 kvm_vcpu_block(vcpu);
6252 kvm_apic_accept_events(vcpu);
6253 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6258 /* re-sync apic's tpr */
6259 if (!irqchip_in_kernel(vcpu->kvm)) {
6260 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6266 if (unlikely(vcpu->arch.complete_userspace_io)) {
6267 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6268 vcpu->arch.complete_userspace_io = NULL;
6273 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6275 r = __vcpu_run(vcpu);
6278 post_kvm_run_save(vcpu);
6279 if (vcpu->sigset_active)
6280 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6285 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6287 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6289 * We are here if userspace calls get_regs() in the middle of
6290 * instruction emulation. Registers state needs to be copied
6291 * back from emulation context to vcpu. Userspace shouldn't do
6292 * that usually, but some bad designed PV devices (vmware
6293 * backdoor interface) need this to work
6295 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6296 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6298 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6299 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6300 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6301 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6302 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6303 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6304 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6305 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6306 #ifdef CONFIG_X86_64
6307 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6308 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6309 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6310 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6311 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6312 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6313 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6314 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6317 regs->rip = kvm_rip_read(vcpu);
6318 regs->rflags = kvm_get_rflags(vcpu);
6323 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6325 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6326 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6328 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6329 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6330 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6331 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6332 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6333 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6334 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6335 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6336 #ifdef CONFIG_X86_64
6337 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6338 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6339 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6340 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6341 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6342 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6343 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6344 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6347 kvm_rip_write(vcpu, regs->rip);
6348 kvm_set_rflags(vcpu, regs->rflags);
6350 vcpu->arch.exception.pending = false;
6352 kvm_make_request(KVM_REQ_EVENT, vcpu);
6357 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6359 struct kvm_segment cs;
6361 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6365 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6367 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6368 struct kvm_sregs *sregs)
6372 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6373 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6374 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6375 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6376 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6377 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6379 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6380 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6382 kvm_x86_ops->get_idt(vcpu, &dt);
6383 sregs->idt.limit = dt.size;
6384 sregs->idt.base = dt.address;
6385 kvm_x86_ops->get_gdt(vcpu, &dt);
6386 sregs->gdt.limit = dt.size;
6387 sregs->gdt.base = dt.address;
6389 sregs->cr0 = kvm_read_cr0(vcpu);
6390 sregs->cr2 = vcpu->arch.cr2;
6391 sregs->cr3 = kvm_read_cr3(vcpu);
6392 sregs->cr4 = kvm_read_cr4(vcpu);
6393 sregs->cr8 = kvm_get_cr8(vcpu);
6394 sregs->efer = vcpu->arch.efer;
6395 sregs->apic_base = kvm_get_apic_base(vcpu);
6397 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6399 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6400 set_bit(vcpu->arch.interrupt.nr,
6401 (unsigned long *)sregs->interrupt_bitmap);
6406 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6407 struct kvm_mp_state *mp_state)
6409 kvm_apic_accept_events(vcpu);
6410 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6411 vcpu->arch.pv.pv_unhalted)
6412 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6414 mp_state->mp_state = vcpu->arch.mp_state;
6419 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6420 struct kvm_mp_state *mp_state)
6422 if (!kvm_vcpu_has_lapic(vcpu) &&
6423 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6426 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6427 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6428 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6430 vcpu->arch.mp_state = mp_state->mp_state;
6431 kvm_make_request(KVM_REQ_EVENT, vcpu);
6435 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6436 int reason, bool has_error_code, u32 error_code)
6438 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6441 init_emulate_ctxt(vcpu);
6443 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6444 has_error_code, error_code);
6447 return EMULATE_FAIL;
6449 kvm_rip_write(vcpu, ctxt->eip);
6450 kvm_set_rflags(vcpu, ctxt->eflags);
6451 kvm_make_request(KVM_REQ_EVENT, vcpu);
6452 return EMULATE_DONE;
6454 EXPORT_SYMBOL_GPL(kvm_task_switch);
6456 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6457 struct kvm_sregs *sregs)
6459 struct msr_data apic_base_msr;
6460 int mmu_reset_needed = 0;
6461 int pending_vec, max_bits, idx;
6464 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6467 dt.size = sregs->idt.limit;
6468 dt.address = sregs->idt.base;
6469 kvm_x86_ops->set_idt(vcpu, &dt);
6470 dt.size = sregs->gdt.limit;
6471 dt.address = sregs->gdt.base;
6472 kvm_x86_ops->set_gdt(vcpu, &dt);
6474 vcpu->arch.cr2 = sregs->cr2;
6475 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6476 vcpu->arch.cr3 = sregs->cr3;
6477 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6479 kvm_set_cr8(vcpu, sregs->cr8);
6481 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6482 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6483 apic_base_msr.data = sregs->apic_base;
6484 apic_base_msr.host_initiated = true;
6485 kvm_set_apic_base(vcpu, &apic_base_msr);
6487 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6488 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6489 vcpu->arch.cr0 = sregs->cr0;
6491 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6492 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6493 if (sregs->cr4 & X86_CR4_OSXSAVE)
6494 kvm_update_cpuid(vcpu);
6496 idx = srcu_read_lock(&vcpu->kvm->srcu);
6497 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6498 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6499 mmu_reset_needed = 1;
6501 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6503 if (mmu_reset_needed)
6504 kvm_mmu_reset_context(vcpu);
6506 max_bits = KVM_NR_INTERRUPTS;
6507 pending_vec = find_first_bit(
6508 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6509 if (pending_vec < max_bits) {
6510 kvm_queue_interrupt(vcpu, pending_vec, false);
6511 pr_debug("Set back pending irq %d\n", pending_vec);
6514 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6515 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6516 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6517 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6518 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6519 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6521 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6522 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6524 update_cr8_intercept(vcpu);
6526 /* Older userspace won't unhalt the vcpu on reset. */
6527 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6528 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6530 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6532 kvm_make_request(KVM_REQ_EVENT, vcpu);
6537 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6538 struct kvm_guest_debug *dbg)
6540 unsigned long rflags;
6543 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6545 if (vcpu->arch.exception.pending)
6547 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6548 kvm_queue_exception(vcpu, DB_VECTOR);
6550 kvm_queue_exception(vcpu, BP_VECTOR);
6554 * Read rflags as long as potentially injected trace flags are still
6557 rflags = kvm_get_rflags(vcpu);
6559 vcpu->guest_debug = dbg->control;
6560 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6561 vcpu->guest_debug = 0;
6563 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6564 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6565 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6566 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6568 for (i = 0; i < KVM_NR_DB_REGS; i++)
6569 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6571 kvm_update_dr7(vcpu);
6573 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6574 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6575 get_segment_base(vcpu, VCPU_SREG_CS);
6578 * Trigger an rflags update that will inject or remove the trace
6581 kvm_set_rflags(vcpu, rflags);
6583 kvm_x86_ops->update_db_bp_intercept(vcpu);
6593 * Translate a guest virtual address to a guest physical address.
6595 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6596 struct kvm_translation *tr)
6598 unsigned long vaddr = tr->linear_address;
6602 idx = srcu_read_lock(&vcpu->kvm->srcu);
6603 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6604 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6605 tr->physical_address = gpa;
6606 tr->valid = gpa != UNMAPPED_GVA;
6613 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6615 struct i387_fxsave_struct *fxsave =
6616 &vcpu->arch.guest_fpu.state->fxsave;
6618 memcpy(fpu->fpr, fxsave->st_space, 128);
6619 fpu->fcw = fxsave->cwd;
6620 fpu->fsw = fxsave->swd;
6621 fpu->ftwx = fxsave->twd;
6622 fpu->last_opcode = fxsave->fop;
6623 fpu->last_ip = fxsave->rip;
6624 fpu->last_dp = fxsave->rdp;
6625 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6630 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6632 struct i387_fxsave_struct *fxsave =
6633 &vcpu->arch.guest_fpu.state->fxsave;
6635 memcpy(fxsave->st_space, fpu->fpr, 128);
6636 fxsave->cwd = fpu->fcw;
6637 fxsave->swd = fpu->fsw;
6638 fxsave->twd = fpu->ftwx;
6639 fxsave->fop = fpu->last_opcode;
6640 fxsave->rip = fpu->last_ip;
6641 fxsave->rdp = fpu->last_dp;
6642 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6647 int fx_init(struct kvm_vcpu *vcpu)
6651 err = fpu_alloc(&vcpu->arch.guest_fpu);
6655 fpu_finit(&vcpu->arch.guest_fpu);
6658 * Ensure guest xcr0 is valid for loading
6660 vcpu->arch.xcr0 = XSTATE_FP;
6662 vcpu->arch.cr0 |= X86_CR0_ET;
6666 EXPORT_SYMBOL_GPL(fx_init);
6668 static void fx_free(struct kvm_vcpu *vcpu)
6670 fpu_free(&vcpu->arch.guest_fpu);
6673 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6675 if (vcpu->guest_fpu_loaded)
6679 * Restore all possible states in the guest,
6680 * and assume host would use all available bits.
6681 * Guest xcr0 would be loaded later.
6683 kvm_put_guest_xcr0(vcpu);
6684 vcpu->guest_fpu_loaded = 1;
6685 __kernel_fpu_begin();
6686 fpu_restore_checking(&vcpu->arch.guest_fpu);
6690 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6692 kvm_put_guest_xcr0(vcpu);
6694 if (!vcpu->guest_fpu_loaded)
6697 vcpu->guest_fpu_loaded = 0;
6698 fpu_save_init(&vcpu->arch.guest_fpu);
6700 ++vcpu->stat.fpu_reload;
6701 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6705 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6707 kvmclock_reset(vcpu);
6709 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6711 kvm_x86_ops->vcpu_free(vcpu);
6714 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6717 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6718 printk_once(KERN_WARNING
6719 "kvm: SMP vm created on host with unstable TSC; "
6720 "guest TSC will not be reliable\n");
6721 return kvm_x86_ops->vcpu_create(kvm, id);
6724 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6728 vcpu->arch.mtrr_state.have_fixed = 1;
6729 r = vcpu_load(vcpu);
6732 kvm_vcpu_reset(vcpu);
6733 kvm_mmu_setup(vcpu);
6739 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6742 struct msr_data msr;
6744 r = vcpu_load(vcpu);
6748 msr.index = MSR_IA32_TSC;
6749 msr.host_initiated = true;
6750 kvm_write_tsc(vcpu, &msr);
6756 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6759 vcpu->arch.apf.msr_val = 0;
6761 r = vcpu_load(vcpu);
6763 kvm_mmu_unload(vcpu);
6767 kvm_x86_ops->vcpu_free(vcpu);
6770 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6772 atomic_set(&vcpu->arch.nmi_queued, 0);
6773 vcpu->arch.nmi_pending = 0;
6774 vcpu->arch.nmi_injected = false;
6776 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6777 vcpu->arch.dr6 = DR6_FIXED_1;
6778 kvm_update_dr6(vcpu);
6779 vcpu->arch.dr7 = DR7_FIXED_1;
6780 kvm_update_dr7(vcpu);
6782 kvm_make_request(KVM_REQ_EVENT, vcpu);
6783 vcpu->arch.apf.msr_val = 0;
6784 vcpu->arch.st.msr_val = 0;
6786 kvmclock_reset(vcpu);
6788 kvm_clear_async_pf_completion_queue(vcpu);
6789 kvm_async_pf_hash_reset(vcpu);
6790 vcpu->arch.apf.halted = false;
6792 kvm_pmu_reset(vcpu);
6794 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6795 vcpu->arch.regs_avail = ~0;
6796 vcpu->arch.regs_dirty = ~0;
6798 kvm_x86_ops->vcpu_reset(vcpu);
6801 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6803 struct kvm_segment cs;
6805 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6806 cs.selector = vector << 8;
6807 cs.base = vector << 12;
6808 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6809 kvm_rip_write(vcpu, 0);
6812 int kvm_arch_hardware_enable(void *garbage)
6815 struct kvm_vcpu *vcpu;
6820 bool stable, backwards_tsc = false;
6822 kvm_shared_msr_cpu_online();
6823 ret = kvm_x86_ops->hardware_enable(garbage);
6827 local_tsc = native_read_tsc();
6828 stable = !check_tsc_unstable();
6829 list_for_each_entry(kvm, &vm_list, vm_list) {
6830 kvm_for_each_vcpu(i, vcpu, kvm) {
6831 if (!stable && vcpu->cpu == smp_processor_id())
6832 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6833 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6834 backwards_tsc = true;
6835 if (vcpu->arch.last_host_tsc > max_tsc)
6836 max_tsc = vcpu->arch.last_host_tsc;
6842 * Sometimes, even reliable TSCs go backwards. This happens on
6843 * platforms that reset TSC during suspend or hibernate actions, but
6844 * maintain synchronization. We must compensate. Fortunately, we can
6845 * detect that condition here, which happens early in CPU bringup,
6846 * before any KVM threads can be running. Unfortunately, we can't
6847 * bring the TSCs fully up to date with real time, as we aren't yet far
6848 * enough into CPU bringup that we know how much real time has actually
6849 * elapsed; our helper function, get_kernel_ns() will be using boot
6850 * variables that haven't been updated yet.
6852 * So we simply find the maximum observed TSC above, then record the
6853 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6854 * the adjustment will be applied. Note that we accumulate
6855 * adjustments, in case multiple suspend cycles happen before some VCPU
6856 * gets a chance to run again. In the event that no KVM threads get a
6857 * chance to run, we will miss the entire elapsed period, as we'll have
6858 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6859 * loose cycle time. This isn't too big a deal, since the loss will be
6860 * uniform across all VCPUs (not to mention the scenario is extremely
6861 * unlikely). It is possible that a second hibernate recovery happens
6862 * much faster than a first, causing the observed TSC here to be
6863 * smaller; this would require additional padding adjustment, which is
6864 * why we set last_host_tsc to the local tsc observed here.
6866 * N.B. - this code below runs only on platforms with reliable TSC,
6867 * as that is the only way backwards_tsc is set above. Also note
6868 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6869 * have the same delta_cyc adjustment applied if backwards_tsc
6870 * is detected. Note further, this adjustment is only done once,
6871 * as we reset last_host_tsc on all VCPUs to stop this from being
6872 * called multiple times (one for each physical CPU bringup).
6874 * Platforms with unreliable TSCs don't have to deal with this, they
6875 * will be compensated by the logic in vcpu_load, which sets the TSC to
6876 * catchup mode. This will catchup all VCPUs to real time, but cannot
6877 * guarantee that they stay in perfect synchronization.
6879 if (backwards_tsc) {
6880 u64 delta_cyc = max_tsc - local_tsc;
6881 list_for_each_entry(kvm, &vm_list, vm_list) {
6882 kvm_for_each_vcpu(i, vcpu, kvm) {
6883 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6884 vcpu->arch.last_host_tsc = local_tsc;
6885 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6890 * We have to disable TSC offset matching.. if you were
6891 * booting a VM while issuing an S4 host suspend....
6892 * you may have some problem. Solving this issue is
6893 * left as an exercise to the reader.
6895 kvm->arch.last_tsc_nsec = 0;
6896 kvm->arch.last_tsc_write = 0;
6903 void kvm_arch_hardware_disable(void *garbage)
6905 kvm_x86_ops->hardware_disable(garbage);
6906 drop_user_return_notifiers(garbage);
6909 int kvm_arch_hardware_setup(void)
6911 return kvm_x86_ops->hardware_setup();
6914 void kvm_arch_hardware_unsetup(void)
6916 kvm_x86_ops->hardware_unsetup();
6919 void kvm_arch_check_processor_compat(void *rtn)
6921 kvm_x86_ops->check_processor_compatibility(rtn);
6924 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6926 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6929 struct static_key kvm_no_apic_vcpu __read_mostly;
6931 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6937 BUG_ON(vcpu->kvm == NULL);
6940 vcpu->arch.pv.pv_unhalted = false;
6941 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6942 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6943 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6945 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6947 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6952 vcpu->arch.pio_data = page_address(page);
6954 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6956 r = kvm_mmu_create(vcpu);
6958 goto fail_free_pio_data;
6960 if (irqchip_in_kernel(kvm)) {
6961 r = kvm_create_lapic(vcpu);
6963 goto fail_mmu_destroy;
6965 static_key_slow_inc(&kvm_no_apic_vcpu);
6967 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6969 if (!vcpu->arch.mce_banks) {
6971 goto fail_free_lapic;
6973 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6975 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6977 goto fail_free_mce_banks;
6982 goto fail_free_wbinvd_dirty_mask;
6984 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6985 vcpu->arch.pv_time_enabled = false;
6987 vcpu->arch.guest_supported_xcr0 = 0;
6988 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
6990 kvm_async_pf_hash_reset(vcpu);
6994 fail_free_wbinvd_dirty_mask:
6995 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6996 fail_free_mce_banks:
6997 kfree(vcpu->arch.mce_banks);
6999 kvm_free_lapic(vcpu);
7001 kvm_mmu_destroy(vcpu);
7003 free_page((unsigned long)vcpu->arch.pio_data);
7008 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7012 kvm_pmu_destroy(vcpu);
7013 kfree(vcpu->arch.mce_banks);
7014 kvm_free_lapic(vcpu);
7015 idx = srcu_read_lock(&vcpu->kvm->srcu);
7016 kvm_mmu_destroy(vcpu);
7017 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7018 free_page((unsigned long)vcpu->arch.pio_data);
7019 if (!irqchip_in_kernel(vcpu->kvm))
7020 static_key_slow_dec(&kvm_no_apic_vcpu);
7023 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7028 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7029 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7030 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7031 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7033 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7034 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7035 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7036 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7037 &kvm->arch.irq_sources_bitmap);
7039 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7040 mutex_init(&kvm->arch.apic_map_lock);
7041 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7043 pvclock_update_vm_gtod_copy(kvm);
7048 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7051 r = vcpu_load(vcpu);
7053 kvm_mmu_unload(vcpu);
7057 static void kvm_free_vcpus(struct kvm *kvm)
7060 struct kvm_vcpu *vcpu;
7063 * Unpin any mmu pages first.
7065 kvm_for_each_vcpu(i, vcpu, kvm) {
7066 kvm_clear_async_pf_completion_queue(vcpu);
7067 kvm_unload_vcpu_mmu(vcpu);
7069 kvm_for_each_vcpu(i, vcpu, kvm)
7070 kvm_arch_vcpu_free(vcpu);
7072 mutex_lock(&kvm->lock);
7073 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7074 kvm->vcpus[i] = NULL;
7076 atomic_set(&kvm->online_vcpus, 0);
7077 mutex_unlock(&kvm->lock);
7080 void kvm_arch_sync_events(struct kvm *kvm)
7082 kvm_free_all_assigned_devices(kvm);
7086 void kvm_arch_destroy_vm(struct kvm *kvm)
7088 if (current->mm == kvm->mm) {
7090 * Free memory regions allocated on behalf of userspace,
7091 * unless the the memory map has changed due to process exit
7094 struct kvm_userspace_memory_region mem;
7095 memset(&mem, 0, sizeof(mem));
7096 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7097 kvm_set_memory_region(kvm, &mem);
7099 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7100 kvm_set_memory_region(kvm, &mem);
7102 mem.slot = TSS_PRIVATE_MEMSLOT;
7103 kvm_set_memory_region(kvm, &mem);
7105 kvm_iommu_unmap_guest(kvm);
7106 kfree(kvm->arch.vpic);
7107 kfree(kvm->arch.vioapic);
7108 kvm_free_vcpus(kvm);
7109 if (kvm->arch.apic_access_page)
7110 put_page(kvm->arch.apic_access_page);
7111 if (kvm->arch.ept_identity_pagetable)
7112 put_page(kvm->arch.ept_identity_pagetable);
7113 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7116 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7117 struct kvm_memory_slot *dont)
7121 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7122 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7123 kvm_kvfree(free->arch.rmap[i]);
7124 free->arch.rmap[i] = NULL;
7129 if (!dont || free->arch.lpage_info[i - 1] !=
7130 dont->arch.lpage_info[i - 1]) {
7131 kvm_kvfree(free->arch.lpage_info[i - 1]);
7132 free->arch.lpage_info[i - 1] = NULL;
7137 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7138 unsigned long npages)
7142 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7147 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7148 slot->base_gfn, level) + 1;
7150 slot->arch.rmap[i] =
7151 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7152 if (!slot->arch.rmap[i])
7157 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7158 sizeof(*slot->arch.lpage_info[i - 1]));
7159 if (!slot->arch.lpage_info[i - 1])
7162 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7163 slot->arch.lpage_info[i - 1][0].write_count = 1;
7164 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7165 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7166 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7168 * If the gfn and userspace address are not aligned wrt each
7169 * other, or if explicitly asked to, disable large page
7170 * support for this slot
7172 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7173 !kvm_largepages_enabled()) {
7176 for (j = 0; j < lpages; ++j)
7177 slot->arch.lpage_info[i - 1][j].write_count = 1;
7184 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7185 kvm_kvfree(slot->arch.rmap[i]);
7186 slot->arch.rmap[i] = NULL;
7190 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7191 slot->arch.lpage_info[i - 1] = NULL;
7196 void kvm_arch_memslots_updated(struct kvm *kvm)
7199 * memslots->generation has been incremented.
7200 * mmio generation may have reached its maximum value.
7202 kvm_mmu_invalidate_mmio_sptes(kvm);
7205 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7206 struct kvm_memory_slot *memslot,
7207 struct kvm_userspace_memory_region *mem,
7208 enum kvm_mr_change change)
7211 * Only private memory slots need to be mapped here since
7212 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7214 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7215 unsigned long userspace_addr;
7218 * MAP_SHARED to prevent internal slot pages from being moved
7221 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7222 PROT_READ | PROT_WRITE,
7223 MAP_SHARED | MAP_ANONYMOUS, 0);
7225 if (IS_ERR((void *)userspace_addr))
7226 return PTR_ERR((void *)userspace_addr);
7228 memslot->userspace_addr = userspace_addr;
7234 void kvm_arch_commit_memory_region(struct kvm *kvm,
7235 struct kvm_userspace_memory_region *mem,
7236 const struct kvm_memory_slot *old,
7237 enum kvm_mr_change change)
7240 int nr_mmu_pages = 0;
7242 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7245 ret = vm_munmap(old->userspace_addr,
7246 old->npages * PAGE_SIZE);
7249 "kvm_vm_ioctl_set_memory_region: "
7250 "failed to munmap memory\n");
7253 if (!kvm->arch.n_requested_mmu_pages)
7254 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7257 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7259 * Write protect all pages for dirty logging.
7260 * Existing largepage mappings are destroyed here and new ones will
7261 * not be created until the end of the logging.
7263 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7264 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7267 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7269 kvm_mmu_invalidate_zap_all_pages(kvm);
7272 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7273 struct kvm_memory_slot *slot)
7275 kvm_mmu_invalidate_zap_all_pages(kvm);
7278 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7280 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7281 !vcpu->arch.apf.halted)
7282 || !list_empty_careful(&vcpu->async_pf.done)
7283 || kvm_apic_has_events(vcpu)
7284 || vcpu->arch.pv.pv_unhalted
7285 || atomic_read(&vcpu->arch.nmi_queued) ||
7286 (kvm_arch_interrupt_allowed(vcpu) &&
7287 kvm_cpu_has_interrupt(vcpu));
7290 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7292 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7295 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7297 return kvm_x86_ops->interrupt_allowed(vcpu);
7300 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7302 unsigned long current_rip = kvm_rip_read(vcpu) +
7303 get_segment_base(vcpu, VCPU_SREG_CS);
7305 return current_rip == linear_rip;
7307 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7309 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7311 unsigned long rflags;
7313 rflags = kvm_x86_ops->get_rflags(vcpu);
7314 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7315 rflags &= ~X86_EFLAGS_TF;
7318 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7320 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7322 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7323 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7324 rflags |= X86_EFLAGS_TF;
7325 kvm_x86_ops->set_rflags(vcpu, rflags);
7326 kvm_make_request(KVM_REQ_EVENT, vcpu);
7328 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7330 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7334 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7338 r = kvm_mmu_reload(vcpu);
7342 if (!vcpu->arch.mmu.direct_map &&
7343 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7346 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7349 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7351 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7354 static inline u32 kvm_async_pf_next_probe(u32 key)
7356 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7359 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7361 u32 key = kvm_async_pf_hash_fn(gfn);
7363 while (vcpu->arch.apf.gfns[key] != ~0)
7364 key = kvm_async_pf_next_probe(key);
7366 vcpu->arch.apf.gfns[key] = gfn;
7369 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7372 u32 key = kvm_async_pf_hash_fn(gfn);
7374 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7375 (vcpu->arch.apf.gfns[key] != gfn &&
7376 vcpu->arch.apf.gfns[key] != ~0); i++)
7377 key = kvm_async_pf_next_probe(key);
7382 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7384 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7387 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7391 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7393 vcpu->arch.apf.gfns[i] = ~0;
7395 j = kvm_async_pf_next_probe(j);
7396 if (vcpu->arch.apf.gfns[j] == ~0)
7398 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7400 * k lies cyclically in ]i,j]
7402 * |....j i.k.| or |.k..j i...|
7404 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7405 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7410 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7413 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7417 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7418 struct kvm_async_pf *work)
7420 struct x86_exception fault;
7422 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7423 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7425 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7426 (vcpu->arch.apf.send_user_only &&
7427 kvm_x86_ops->get_cpl(vcpu) == 0))
7428 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7429 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7430 fault.vector = PF_VECTOR;
7431 fault.error_code_valid = true;
7432 fault.error_code = 0;
7433 fault.nested_page_fault = false;
7434 fault.address = work->arch.token;
7435 kvm_inject_page_fault(vcpu, &fault);
7439 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7440 struct kvm_async_pf *work)
7442 struct x86_exception fault;
7444 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7445 if (work->wakeup_all)
7446 work->arch.token = ~0; /* broadcast wakeup */
7448 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7450 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7451 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7452 fault.vector = PF_VECTOR;
7453 fault.error_code_valid = true;
7454 fault.error_code = 0;
7455 fault.nested_page_fault = false;
7456 fault.address = work->arch.token;
7457 kvm_inject_page_fault(vcpu, &fault);
7459 vcpu->arch.apf.halted = false;
7460 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7463 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7465 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7468 return !kvm_event_needs_reinjection(vcpu) &&
7469 kvm_x86_ops->interrupt_allowed(vcpu);
7472 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7474 atomic_inc(&kvm->arch.noncoherent_dma_count);
7476 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7478 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7480 atomic_dec(&kvm->arch.noncoherent_dma_count);
7482 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7484 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7486 return atomic_read(&kvm->arch.noncoherent_dma_count);
7488 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7490 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7491 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7492 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7493 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7494 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7495 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7496 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7497 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7498 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7499 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7500 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7501 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7502 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);