2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
53 #define CREATE_TRACE_POINTS
56 #include <asm/debugreg.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32 kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109 #define KVM_NR_SHARED_MSRS 16
111 struct kvm_shared_msrs_global {
113 u32 msrs[KVM_NR_SHARED_MSRS];
116 struct kvm_shared_msrs {
117 struct user_return_notifier urn;
119 struct kvm_shared_msr_values {
122 } values[KVM_NR_SHARED_MSRS];
125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
126 static struct kvm_shared_msrs __percpu *shared_msrs;
128 struct kvm_stats_debugfs_item debugfs_entries[] = {
129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
141 { "hypercalls", VCPU_STAT(hypercalls) },
142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
149 { "irq_injections", VCPU_STAT(irq_injections) },
150 { "nmi_injections", VCPU_STAT(nmi_injections) },
151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
158 { "mmu_unsync", VM_STAT(mmu_unsync) },
159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
160 { "largepages", VM_STAT(lpages) },
164 u64 __read_mostly host_xcr0;
166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
175 static void kvm_on_user_return(struct user_return_notifier *urn)
178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
180 struct kvm_shared_msr_values *values;
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
193 static void shared_msr_update(unsigned slot, u32 msr)
196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
210 void kvm_define_shared_msr(unsigned slot, u32 msr)
212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
220 static void kvm_shared_msr_cpu_online(void)
224 for (i = 0; i < shared_msrs_global.nr; ++i)
225 shared_msr_update(i, shared_msrs_global.msrs[i]);
228 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
243 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
245 static void drop_user_return_notifiers(void *ignore)
247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
254 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
256 return vcpu->arch.apic_base;
258 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
260 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
262 /* TODO: reserve bits check */
263 kvm_lapic_set_base(vcpu, data);
265 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
267 asmlinkage void kvm_spurious_fault(void)
269 /* Fault while not rebooting. We want the trace. */
272 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
274 #define EXCPT_BENIGN 0
275 #define EXCPT_CONTRIBUTORY 1
278 static int exception_class(int vector)
288 return EXCPT_CONTRIBUTORY;
295 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
296 unsigned nr, bool has_error, u32 error_code,
302 kvm_make_request(KVM_REQ_EVENT, vcpu);
304 if (!vcpu->arch.exception.pending) {
306 vcpu->arch.exception.pending = true;
307 vcpu->arch.exception.has_error_code = has_error;
308 vcpu->arch.exception.nr = nr;
309 vcpu->arch.exception.error_code = error_code;
310 vcpu->arch.exception.reinject = reinject;
314 /* to check exception */
315 prev_nr = vcpu->arch.exception.nr;
316 if (prev_nr == DF_VECTOR) {
317 /* triple fault -> shutdown */
318 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
321 class1 = exception_class(prev_nr);
322 class2 = exception_class(nr);
323 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
324 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
325 /* generate double fault per SDM Table 5-5 */
326 vcpu->arch.exception.pending = true;
327 vcpu->arch.exception.has_error_code = true;
328 vcpu->arch.exception.nr = DF_VECTOR;
329 vcpu->arch.exception.error_code = 0;
331 /* replace previous exception with a new one in a hope
332 that instruction re-execution will regenerate lost
337 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
339 kvm_multiple_exception(vcpu, nr, false, 0, false);
341 EXPORT_SYMBOL_GPL(kvm_queue_exception);
343 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
345 kvm_multiple_exception(vcpu, nr, false, 0, true);
347 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
349 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
352 kvm_inject_gp(vcpu, 0);
354 kvm_x86_ops->skip_emulated_instruction(vcpu);
356 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
358 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
360 ++vcpu->stat.pf_guest;
361 vcpu->arch.cr2 = fault->address;
362 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
364 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
366 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
368 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
369 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
371 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
374 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
376 atomic_inc(&vcpu->arch.nmi_queued);
377 kvm_make_request(KVM_REQ_NMI, vcpu);
379 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
381 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
383 kvm_multiple_exception(vcpu, nr, true, error_code, false);
385 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
387 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
389 kvm_multiple_exception(vcpu, nr, true, error_code, true);
391 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
394 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
395 * a #GP and return false.
397 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
399 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
401 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
404 EXPORT_SYMBOL_GPL(kvm_require_cpl);
407 * This function will be used to read from the physical memory of the currently
408 * running guest. The difference to kvm_read_guest_page is that this function
409 * can read from guest physical or from the guest's guest physical memory.
411 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
412 gfn_t ngfn, void *data, int offset, int len,
418 ngpa = gfn_to_gpa(ngfn);
419 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
420 if (real_gfn == UNMAPPED_GVA)
423 real_gfn = gpa_to_gfn(real_gfn);
425 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
427 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
429 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
430 void *data, int offset, int len, u32 access)
432 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
433 data, offset, len, access);
437 * Load the pae pdptrs. Return true is they are all valid.
439 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
441 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
442 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
445 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
447 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
448 offset * sizeof(u64), sizeof(pdpte),
449 PFERR_USER_MASK|PFERR_WRITE_MASK);
454 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
455 if (is_present_gpte(pdpte[i]) &&
456 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
463 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
464 __set_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail);
466 __set_bit(VCPU_EXREG_PDPTR,
467 (unsigned long *)&vcpu->arch.regs_dirty);
472 EXPORT_SYMBOL_GPL(load_pdptrs);
474 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
476 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
482 if (is_long_mode(vcpu) || !is_pae(vcpu))
485 if (!test_bit(VCPU_EXREG_PDPTR,
486 (unsigned long *)&vcpu->arch.regs_avail))
489 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
490 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
491 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
492 PFERR_USER_MASK | PFERR_WRITE_MASK);
495 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
501 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
503 unsigned long old_cr0 = kvm_read_cr0(vcpu);
504 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
505 X86_CR0_CD | X86_CR0_NW;
510 if (cr0 & 0xffffffff00000000UL)
514 cr0 &= ~CR0_RESERVED_BITS;
516 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
519 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
522 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
524 if ((vcpu->arch.efer & EFER_LME)) {
529 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
534 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
539 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
542 kvm_x86_ops->set_cr0(vcpu, cr0);
544 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
545 kvm_clear_async_pf_completion_queue(vcpu);
546 kvm_async_pf_hash_reset(vcpu);
549 if ((cr0 ^ old_cr0) & update_bits)
550 kvm_mmu_reset_context(vcpu);
553 EXPORT_SYMBOL_GPL(kvm_set_cr0);
555 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
557 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
559 EXPORT_SYMBOL_GPL(kvm_lmsw);
561 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
563 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
564 !vcpu->guest_xcr0_loaded) {
565 /* kvm_set_xcr() also depends on this */
566 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
567 vcpu->guest_xcr0_loaded = 1;
571 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
573 if (vcpu->guest_xcr0_loaded) {
574 if (vcpu->arch.xcr0 != host_xcr0)
575 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
576 vcpu->guest_xcr0_loaded = 0;
580 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
585 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
586 if (index != XCR_XFEATURE_ENABLED_MASK)
589 if (!(xcr0 & XSTATE_FP))
591 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
595 * Do not allow the guest to set bits that we do not support
596 * saving. However, xcr0 bit 0 is always set, even if the
597 * emulated CPU does not support XSAVE (see fx_init).
599 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
600 if (xcr0 & ~valid_bits)
603 kvm_put_guest_xcr0(vcpu);
604 vcpu->arch.xcr0 = xcr0;
608 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
610 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
611 __kvm_set_xcr(vcpu, index, xcr)) {
612 kvm_inject_gp(vcpu, 0);
617 EXPORT_SYMBOL_GPL(kvm_set_xcr);
619 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
621 unsigned long old_cr4 = kvm_read_cr4(vcpu);
622 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
623 X86_CR4_PAE | X86_CR4_SMEP;
624 if (cr4 & CR4_RESERVED_BITS)
627 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
630 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
633 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
636 if (is_long_mode(vcpu)) {
637 if (!(cr4 & X86_CR4_PAE))
639 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
640 && ((cr4 ^ old_cr4) & pdptr_bits)
641 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
645 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
646 if (!guest_cpuid_has_pcid(vcpu))
649 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
650 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
654 if (kvm_x86_ops->set_cr4(vcpu, cr4))
657 if (((cr4 ^ old_cr4) & pdptr_bits) ||
658 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
659 kvm_mmu_reset_context(vcpu);
661 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
662 kvm_update_cpuid(vcpu);
666 EXPORT_SYMBOL_GPL(kvm_set_cr4);
668 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
670 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
671 kvm_mmu_sync_roots(vcpu);
672 kvm_mmu_flush_tlb(vcpu);
676 if (is_long_mode(vcpu)) {
677 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
678 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
681 if (cr3 & CR3_L_MODE_RESERVED_BITS)
685 if (cr3 & CR3_PAE_RESERVED_BITS)
687 if (is_paging(vcpu) &&
688 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
692 * We don't check reserved bits in nonpae mode, because
693 * this isn't enforced, and VMware depends on this.
697 vcpu->arch.cr3 = cr3;
698 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
699 kvm_mmu_new_cr3(vcpu);
702 EXPORT_SYMBOL_GPL(kvm_set_cr3);
704 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
706 if (cr8 & CR8_RESERVED_BITS)
708 if (irqchip_in_kernel(vcpu->kvm))
709 kvm_lapic_set_tpr(vcpu, cr8);
711 vcpu->arch.cr8 = cr8;
714 EXPORT_SYMBOL_GPL(kvm_set_cr8);
716 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
718 if (irqchip_in_kernel(vcpu->kvm))
719 return kvm_lapic_get_cr8(vcpu);
721 return vcpu->arch.cr8;
723 EXPORT_SYMBOL_GPL(kvm_get_cr8);
725 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
729 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
730 dr7 = vcpu->arch.guest_debug_dr7;
732 dr7 = vcpu->arch.dr7;
733 kvm_x86_ops->set_dr7(vcpu, dr7);
734 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
737 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
741 vcpu->arch.db[dr] = val;
742 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
743 vcpu->arch.eff_db[dr] = val;
746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
750 if (val & 0xffffffff00000000ULL)
752 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
755 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
759 if (val & 0xffffffff00000000ULL)
761 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
762 kvm_update_dr7(vcpu);
769 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
773 res = __kvm_set_dr(vcpu, dr, val);
775 kvm_queue_exception(vcpu, UD_VECTOR);
777 kvm_inject_gp(vcpu, 0);
781 EXPORT_SYMBOL_GPL(kvm_set_dr);
783 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
787 *val = vcpu->arch.db[dr];
790 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
794 *val = vcpu->arch.dr6;
797 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
801 *val = vcpu->arch.dr7;
808 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
810 if (_kvm_get_dr(vcpu, dr, val)) {
811 kvm_queue_exception(vcpu, UD_VECTOR);
816 EXPORT_SYMBOL_GPL(kvm_get_dr);
818 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
820 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
824 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
827 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
828 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
831 EXPORT_SYMBOL_GPL(kvm_rdpmc);
834 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
835 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
837 * This list is modified at module load time to reflect the
838 * capabilities of the host cpu. This capabilities test skips MSRs that are
839 * kvm-specific. Those are put in the beginning of the list.
842 #define KVM_SAVE_MSRS_BEGIN 10
843 static u32 msrs_to_save[] = {
844 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
845 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
846 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
847 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
849 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
852 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
854 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
855 MSR_IA32_FEATURE_CONTROL
858 static unsigned num_msrs_to_save;
860 static const u32 emulated_msrs[] = {
862 MSR_IA32_TSCDEADLINE,
863 MSR_IA32_MISC_ENABLE,
868 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
870 if (efer & efer_reserved_bits)
873 if (efer & EFER_FFXSR) {
874 struct kvm_cpuid_entry2 *feat;
876 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
877 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
881 if (efer & EFER_SVME) {
882 struct kvm_cpuid_entry2 *feat;
884 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
885 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
891 EXPORT_SYMBOL_GPL(kvm_valid_efer);
893 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
895 u64 old_efer = vcpu->arch.efer;
897 if (!kvm_valid_efer(vcpu, efer))
901 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
905 efer |= vcpu->arch.efer & EFER_LMA;
907 kvm_x86_ops->set_efer(vcpu, efer);
909 /* Update reserved bits */
910 if ((efer ^ old_efer) & EFER_NX)
911 kvm_mmu_reset_context(vcpu);
916 void kvm_enable_efer_bits(u64 mask)
918 efer_reserved_bits &= ~mask;
920 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
924 * Writes msr value into into the appropriate "register".
925 * Returns 0 on success, non-0 otherwise.
926 * Assumes vcpu_load() was already called.
928 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
930 return kvm_x86_ops->set_msr(vcpu, msr);
934 * Adapt set_msr() to msr_io()'s calling convention
936 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
942 msr.host_initiated = true;
943 return kvm_set_msr(vcpu, &msr);
947 struct pvclock_gtod_data {
950 struct { /* extract of a clocksource struct */
958 /* open coded 'struct timespec' */
959 u64 monotonic_time_snsec;
960 time_t monotonic_time_sec;
963 static struct pvclock_gtod_data pvclock_gtod_data;
965 static void update_pvclock_gtod(struct timekeeper *tk)
967 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
969 write_seqcount_begin(&vdata->seq);
971 /* copy pvclock gtod data */
972 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
973 vdata->clock.cycle_last = tk->clock->cycle_last;
974 vdata->clock.mask = tk->clock->mask;
975 vdata->clock.mult = tk->mult;
976 vdata->clock.shift = tk->shift;
978 vdata->monotonic_time_sec = tk->xtime_sec
979 + tk->wall_to_monotonic.tv_sec;
980 vdata->monotonic_time_snsec = tk->xtime_nsec
981 + (tk->wall_to_monotonic.tv_nsec
983 while (vdata->monotonic_time_snsec >=
984 (((u64)NSEC_PER_SEC) << tk->shift)) {
985 vdata->monotonic_time_snsec -=
986 ((u64)NSEC_PER_SEC) << tk->shift;
987 vdata->monotonic_time_sec++;
990 write_seqcount_end(&vdata->seq);
995 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
999 struct pvclock_wall_clock wc;
1000 struct timespec boot;
1005 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1010 ++version; /* first time write, random junk */
1014 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1017 * The guest calculates current wall clock time by adding
1018 * system time (updated by kvm_guest_time_update below) to the
1019 * wall clock specified here. guest system time equals host
1020 * system time for us, thus we must fill in host boot time here.
1024 if (kvm->arch.kvmclock_offset) {
1025 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1026 boot = timespec_sub(boot, ts);
1028 wc.sec = boot.tv_sec;
1029 wc.nsec = boot.tv_nsec;
1030 wc.version = version;
1032 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1035 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1038 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1040 uint32_t quotient, remainder;
1042 /* Don't try to replace with do_div(), this one calculates
1043 * "(dividend << 32) / divisor" */
1045 : "=a" (quotient), "=d" (remainder)
1046 : "0" (0), "1" (dividend), "r" (divisor) );
1050 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1051 s8 *pshift, u32 *pmultiplier)
1058 tps64 = base_khz * 1000LL;
1059 scaled64 = scaled_khz * 1000LL;
1060 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1065 tps32 = (uint32_t)tps64;
1066 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1067 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1075 *pmultiplier = div_frac(scaled64, tps32);
1077 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1078 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1081 static inline u64 get_kernel_ns(void)
1085 WARN_ON(preemptible());
1087 monotonic_to_bootbased(&ts);
1088 return timespec_to_ns(&ts);
1091 #ifdef CONFIG_X86_64
1092 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1095 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1096 unsigned long max_tsc_khz;
1098 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1100 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1101 vcpu->arch.virtual_tsc_shift);
1104 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1106 u64 v = (u64)khz * (1000000 + ppm);
1111 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1113 u32 thresh_lo, thresh_hi;
1114 int use_scaling = 0;
1116 /* tsc_khz can be zero if TSC calibration fails */
1117 if (this_tsc_khz == 0)
1120 /* Compute a scale to convert nanoseconds in TSC cycles */
1121 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1122 &vcpu->arch.virtual_tsc_shift,
1123 &vcpu->arch.virtual_tsc_mult);
1124 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1127 * Compute the variation in TSC rate which is acceptable
1128 * within the range of tolerance and decide if the
1129 * rate being applied is within that bounds of the hardware
1130 * rate. If so, no scaling or compensation need be done.
1132 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1133 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1134 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1135 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1138 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1141 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1143 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1144 vcpu->arch.virtual_tsc_mult,
1145 vcpu->arch.virtual_tsc_shift);
1146 tsc += vcpu->arch.this_tsc_write;
1150 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1152 #ifdef CONFIG_X86_64
1154 bool do_request = false;
1155 struct kvm_arch *ka = &vcpu->kvm->arch;
1156 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1158 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1159 atomic_read(&vcpu->kvm->online_vcpus));
1161 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1162 if (!ka->use_master_clock)
1165 if (!vcpus_matched && ka->use_master_clock)
1169 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1171 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1172 atomic_read(&vcpu->kvm->online_vcpus),
1173 ka->use_master_clock, gtod->clock.vclock_mode);
1177 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1179 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1180 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1183 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1185 struct kvm *kvm = vcpu->kvm;
1186 u64 offset, ns, elapsed;
1187 unsigned long flags;
1190 u64 data = msr->data;
1192 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1193 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1194 ns = get_kernel_ns();
1195 elapsed = ns - kvm->arch.last_tsc_nsec;
1197 if (vcpu->arch.virtual_tsc_khz) {
1200 /* n.b - signed multiplication and division required */
1201 usdiff = data - kvm->arch.last_tsc_write;
1202 #ifdef CONFIG_X86_64
1203 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1205 /* do_div() only does unsigned */
1206 asm("1: idivl %[divisor]\n"
1207 "2: xor %%edx, %%edx\n"
1208 " movl $0, %[faulted]\n"
1210 ".section .fixup,\"ax\"\n"
1211 "4: movl $1, %[faulted]\n"
1215 _ASM_EXTABLE(1b, 4b)
1217 : "=A"(usdiff), [faulted] "=r" (faulted)
1218 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1221 do_div(elapsed, 1000);
1226 /* idivl overflow => difference is larger than USEC_PER_SEC */
1228 usdiff = USEC_PER_SEC;
1230 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1233 * Special case: TSC write with a small delta (1 second) of virtual
1234 * cycle time against real time is interpreted as an attempt to
1235 * synchronize the CPU.
1237 * For a reliable TSC, we can match TSC offsets, and for an unstable
1238 * TSC, we add elapsed time in this computation. We could let the
1239 * compensation code attempt to catch up if we fall behind, but
1240 * it's better to try to match offsets from the beginning.
1242 if (usdiff < USEC_PER_SEC &&
1243 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1244 if (!check_tsc_unstable()) {
1245 offset = kvm->arch.cur_tsc_offset;
1246 pr_debug("kvm: matched tsc offset for %llu\n", data);
1248 u64 delta = nsec_to_cycles(vcpu, elapsed);
1250 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1251 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1256 * We split periods of matched TSC writes into generations.
1257 * For each generation, we track the original measured
1258 * nanosecond time, offset, and write, so if TSCs are in
1259 * sync, we can match exact offset, and if not, we can match
1260 * exact software computation in compute_guest_tsc()
1262 * These values are tracked in kvm->arch.cur_xxx variables.
1264 kvm->arch.cur_tsc_generation++;
1265 kvm->arch.cur_tsc_nsec = ns;
1266 kvm->arch.cur_tsc_write = data;
1267 kvm->arch.cur_tsc_offset = offset;
1269 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1270 kvm->arch.cur_tsc_generation, data);
1274 * We also track th most recent recorded KHZ, write and time to
1275 * allow the matching interval to be extended at each write.
1277 kvm->arch.last_tsc_nsec = ns;
1278 kvm->arch.last_tsc_write = data;
1279 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1281 /* Reset of TSC must disable overshoot protection below */
1282 vcpu->arch.hv_clock.tsc_timestamp = 0;
1283 vcpu->arch.last_guest_tsc = data;
1285 /* Keep track of which generation this VCPU has synchronized to */
1286 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1287 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1288 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1290 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1291 update_ia32_tsc_adjust_msr(vcpu, offset);
1292 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1293 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1295 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1297 kvm->arch.nr_vcpus_matched_tsc++;
1299 kvm->arch.nr_vcpus_matched_tsc = 0;
1301 kvm_track_tsc_matching(vcpu);
1302 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1305 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1307 #ifdef CONFIG_X86_64
1309 static cycle_t read_tsc(void)
1315 * Empirically, a fence (of type that depends on the CPU)
1316 * before rdtsc is enough to ensure that rdtsc is ordered
1317 * with respect to loads. The various CPU manuals are unclear
1318 * as to whether rdtsc can be reordered with later loads,
1319 * but no one has ever seen it happen.
1322 ret = (cycle_t)vget_cycles();
1324 last = pvclock_gtod_data.clock.cycle_last;
1326 if (likely(ret >= last))
1330 * GCC likes to generate cmov here, but this branch is extremely
1331 * predictable (it's just a funciton of time and the likely is
1332 * very likely) and there's a data dependence, so force GCC
1333 * to generate a branch instead. I don't barrier() because
1334 * we don't actually need a barrier, and if this function
1335 * ever gets inlined it will generate worse code.
1341 static inline u64 vgettsc(cycle_t *cycle_now)
1344 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1346 *cycle_now = read_tsc();
1348 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1349 return v * gtod->clock.mult;
1352 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1357 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1361 seq = read_seqcount_begin(>od->seq);
1362 mode = gtod->clock.vclock_mode;
1363 ts->tv_sec = gtod->monotonic_time_sec;
1364 ns = gtod->monotonic_time_snsec;
1365 ns += vgettsc(cycle_now);
1366 ns >>= gtod->clock.shift;
1367 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1368 timespec_add_ns(ts, ns);
1373 /* returns true if host is using tsc clocksource */
1374 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1378 /* checked again under seqlock below */
1379 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1382 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1385 monotonic_to_bootbased(&ts);
1386 *kernel_ns = timespec_to_ns(&ts);
1394 * Assuming a stable TSC across physical CPUS, and a stable TSC
1395 * across virtual CPUs, the following condition is possible.
1396 * Each numbered line represents an event visible to both
1397 * CPUs at the next numbered event.
1399 * "timespecX" represents host monotonic time. "tscX" represents
1402 * VCPU0 on CPU0 | VCPU1 on CPU1
1404 * 1. read timespec0,tsc0
1405 * 2. | timespec1 = timespec0 + N
1407 * 3. transition to guest | transition to guest
1408 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1409 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1410 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1412 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1415 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1417 * - 0 < N - M => M < N
1419 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1420 * always the case (the difference between two distinct xtime instances
1421 * might be smaller then the difference between corresponding TSC reads,
1422 * when updating guest vcpus pvclock areas).
1424 * To avoid that problem, do not allow visibility of distinct
1425 * system_timestamp/tsc_timestamp values simultaneously: use a master
1426 * copy of host monotonic time values. Update that master copy
1429 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1433 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1435 #ifdef CONFIG_X86_64
1436 struct kvm_arch *ka = &kvm->arch;
1438 bool host_tsc_clocksource, vcpus_matched;
1440 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1441 atomic_read(&kvm->online_vcpus));
1444 * If the host uses TSC clock, then passthrough TSC as stable
1447 host_tsc_clocksource = kvm_get_time_and_clockread(
1448 &ka->master_kernel_ns,
1449 &ka->master_cycle_now);
1451 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1453 if (ka->use_master_clock)
1454 atomic_set(&kvm_guest_has_master_clock, 1);
1456 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1457 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1462 static void kvm_gen_update_masterclock(struct kvm *kvm)
1464 #ifdef CONFIG_X86_64
1466 struct kvm_vcpu *vcpu;
1467 struct kvm_arch *ka = &kvm->arch;
1469 spin_lock(&ka->pvclock_gtod_sync_lock);
1470 kvm_make_mclock_inprogress_request(kvm);
1471 /* no guest entries from this point */
1472 pvclock_update_vm_gtod_copy(kvm);
1474 kvm_for_each_vcpu(i, vcpu, kvm)
1475 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1477 /* guest entries allowed */
1478 kvm_for_each_vcpu(i, vcpu, kvm)
1479 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1481 spin_unlock(&ka->pvclock_gtod_sync_lock);
1485 static int kvm_guest_time_update(struct kvm_vcpu *v)
1487 unsigned long flags, this_tsc_khz;
1488 struct kvm_vcpu_arch *vcpu = &v->arch;
1489 struct kvm_arch *ka = &v->kvm->arch;
1490 s64 kernel_ns, max_kernel_ns;
1491 u64 tsc_timestamp, host_tsc;
1492 struct pvclock_vcpu_time_info guest_hv_clock;
1494 bool use_master_clock;
1500 * If the host uses TSC clock, then passthrough TSC as stable
1503 spin_lock(&ka->pvclock_gtod_sync_lock);
1504 use_master_clock = ka->use_master_clock;
1505 if (use_master_clock) {
1506 host_tsc = ka->master_cycle_now;
1507 kernel_ns = ka->master_kernel_ns;
1509 spin_unlock(&ka->pvclock_gtod_sync_lock);
1511 /* Keep irq disabled to prevent changes to the clock */
1512 local_irq_save(flags);
1513 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1514 if (unlikely(this_tsc_khz == 0)) {
1515 local_irq_restore(flags);
1516 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1519 if (!use_master_clock) {
1520 host_tsc = native_read_tsc();
1521 kernel_ns = get_kernel_ns();
1524 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1527 * We may have to catch up the TSC to match elapsed wall clock
1528 * time for two reasons, even if kvmclock is used.
1529 * 1) CPU could have been running below the maximum TSC rate
1530 * 2) Broken TSC compensation resets the base at each VCPU
1531 * entry to avoid unknown leaps of TSC even when running
1532 * again on the same CPU. This may cause apparent elapsed
1533 * time to disappear, and the guest to stand still or run
1536 if (vcpu->tsc_catchup) {
1537 u64 tsc = compute_guest_tsc(v, kernel_ns);
1538 if (tsc > tsc_timestamp) {
1539 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1540 tsc_timestamp = tsc;
1544 local_irq_restore(flags);
1546 if (!vcpu->pv_time_enabled)
1550 * Time as measured by the TSC may go backwards when resetting the base
1551 * tsc_timestamp. The reason for this is that the TSC resolution is
1552 * higher than the resolution of the other clock scales. Thus, many
1553 * possible measurments of the TSC correspond to one measurement of any
1554 * other clock, and so a spread of values is possible. This is not a
1555 * problem for the computation of the nanosecond clock; with TSC rates
1556 * around 1GHZ, there can only be a few cycles which correspond to one
1557 * nanosecond value, and any path through this code will inevitably
1558 * take longer than that. However, with the kernel_ns value itself,
1559 * the precision may be much lower, down to HZ granularity. If the
1560 * first sampling of TSC against kernel_ns ends in the low part of the
1561 * range, and the second in the high end of the range, we can get:
1563 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1565 * As the sampling errors potentially range in the thousands of cycles,
1566 * it is possible such a time value has already been observed by the
1567 * guest. To protect against this, we must compute the system time as
1568 * observed by the guest and ensure the new system time is greater.
1571 if (vcpu->hv_clock.tsc_timestamp) {
1572 max_kernel_ns = vcpu->last_guest_tsc -
1573 vcpu->hv_clock.tsc_timestamp;
1574 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1575 vcpu->hv_clock.tsc_to_system_mul,
1576 vcpu->hv_clock.tsc_shift);
1577 max_kernel_ns += vcpu->last_kernel_ns;
1580 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1581 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1582 &vcpu->hv_clock.tsc_shift,
1583 &vcpu->hv_clock.tsc_to_system_mul);
1584 vcpu->hw_tsc_khz = this_tsc_khz;
1587 /* with a master <monotonic time, tsc value> tuple,
1588 * pvclock clock reads always increase at the (scaled) rate
1589 * of guest TSC - no need to deal with sampling errors.
1591 if (!use_master_clock) {
1592 if (max_kernel_ns > kernel_ns)
1593 kernel_ns = max_kernel_ns;
1595 /* With all the info we got, fill in the values */
1596 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1597 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1598 vcpu->last_kernel_ns = kernel_ns;
1599 vcpu->last_guest_tsc = tsc_timestamp;
1602 * The interface expects us to write an even number signaling that the
1603 * update is finished. Since the guest won't see the intermediate
1604 * state, we just increase by 2 at the end.
1606 vcpu->hv_clock.version += 2;
1608 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1609 &guest_hv_clock, sizeof(guest_hv_clock))))
1612 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1613 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1615 if (vcpu->pvclock_set_guest_stopped_request) {
1616 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1617 vcpu->pvclock_set_guest_stopped_request = false;
1620 /* If the host uses TSC clocksource, then it is stable */
1621 if (use_master_clock)
1622 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1624 vcpu->hv_clock.flags = pvclock_flags;
1626 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1628 sizeof(vcpu->hv_clock));
1633 * kvmclock updates which are isolated to a given vcpu, such as
1634 * vcpu->cpu migration, should not allow system_timestamp from
1635 * the rest of the vcpus to remain static. Otherwise ntp frequency
1636 * correction applies to one vcpu's system_timestamp but not
1639 * So in those cases, request a kvmclock update for all vcpus.
1640 * The worst case for a remote vcpu to update its kvmclock
1641 * is then bounded by maximum nohz sleep latency.
1644 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1647 struct kvm *kvm = v->kvm;
1648 struct kvm_vcpu *vcpu;
1650 kvm_for_each_vcpu(i, vcpu, kvm) {
1651 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1652 kvm_vcpu_kick(vcpu);
1656 static bool msr_mtrr_valid(unsigned msr)
1659 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1660 case MSR_MTRRfix64K_00000:
1661 case MSR_MTRRfix16K_80000:
1662 case MSR_MTRRfix16K_A0000:
1663 case MSR_MTRRfix4K_C0000:
1664 case MSR_MTRRfix4K_C8000:
1665 case MSR_MTRRfix4K_D0000:
1666 case MSR_MTRRfix4K_D8000:
1667 case MSR_MTRRfix4K_E0000:
1668 case MSR_MTRRfix4K_E8000:
1669 case MSR_MTRRfix4K_F0000:
1670 case MSR_MTRRfix4K_F8000:
1671 case MSR_MTRRdefType:
1672 case MSR_IA32_CR_PAT:
1680 static bool valid_pat_type(unsigned t)
1682 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1685 static bool valid_mtrr_type(unsigned t)
1687 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1690 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1694 if (!msr_mtrr_valid(msr))
1697 if (msr == MSR_IA32_CR_PAT) {
1698 for (i = 0; i < 8; i++)
1699 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1702 } else if (msr == MSR_MTRRdefType) {
1705 return valid_mtrr_type(data & 0xff);
1706 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1707 for (i = 0; i < 8 ; i++)
1708 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1713 /* variable MTRRs */
1714 return valid_mtrr_type(data & 0xff);
1717 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1719 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1721 if (!mtrr_valid(vcpu, msr, data))
1724 if (msr == MSR_MTRRdefType) {
1725 vcpu->arch.mtrr_state.def_type = data;
1726 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1727 } else if (msr == MSR_MTRRfix64K_00000)
1729 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1730 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1731 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1732 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1733 else if (msr == MSR_IA32_CR_PAT)
1734 vcpu->arch.pat = data;
1735 else { /* Variable MTRRs */
1736 int idx, is_mtrr_mask;
1739 idx = (msr - 0x200) / 2;
1740 is_mtrr_mask = msr - 0x200 - 2 * idx;
1743 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1746 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1750 kvm_mmu_reset_context(vcpu);
1754 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1756 u64 mcg_cap = vcpu->arch.mcg_cap;
1757 unsigned bank_num = mcg_cap & 0xff;
1760 case MSR_IA32_MCG_STATUS:
1761 vcpu->arch.mcg_status = data;
1763 case MSR_IA32_MCG_CTL:
1764 if (!(mcg_cap & MCG_CTL_P))
1766 if (data != 0 && data != ~(u64)0)
1768 vcpu->arch.mcg_ctl = data;
1771 if (msr >= MSR_IA32_MC0_CTL &&
1772 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1773 u32 offset = msr - MSR_IA32_MC0_CTL;
1774 /* only 0 or all 1s can be written to IA32_MCi_CTL
1775 * some Linux kernels though clear bit 10 in bank 4 to
1776 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1777 * this to avoid an uncatched #GP in the guest
1779 if ((offset & 0x3) == 0 &&
1780 data != 0 && (data | (1 << 10)) != ~(u64)0)
1782 vcpu->arch.mce_banks[offset] = data;
1790 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1792 struct kvm *kvm = vcpu->kvm;
1793 int lm = is_long_mode(vcpu);
1794 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1795 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1796 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1797 : kvm->arch.xen_hvm_config.blob_size_32;
1798 u32 page_num = data & ~PAGE_MASK;
1799 u64 page_addr = data & PAGE_MASK;
1804 if (page_num >= blob_size)
1807 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1812 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1821 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1823 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1826 static bool kvm_hv_msr_partition_wide(u32 msr)
1830 case HV_X64_MSR_GUEST_OS_ID:
1831 case HV_X64_MSR_HYPERCALL:
1839 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1841 struct kvm *kvm = vcpu->kvm;
1844 case HV_X64_MSR_GUEST_OS_ID:
1845 kvm->arch.hv_guest_os_id = data;
1846 /* setting guest os id to zero disables hypercall page */
1847 if (!kvm->arch.hv_guest_os_id)
1848 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1850 case HV_X64_MSR_HYPERCALL: {
1855 /* if guest os id is not set hypercall should remain disabled */
1856 if (!kvm->arch.hv_guest_os_id)
1858 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1859 kvm->arch.hv_hypercall = data;
1862 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1863 addr = gfn_to_hva(kvm, gfn);
1864 if (kvm_is_error_hva(addr))
1866 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1867 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1868 if (__copy_to_user((void __user *)addr, instructions, 4))
1870 kvm->arch.hv_hypercall = data;
1874 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1875 "data 0x%llx\n", msr, data);
1881 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1884 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1887 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1888 vcpu->arch.hv_vapic = data;
1891 addr = gfn_to_hva(vcpu->kvm, data >>
1892 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1893 if (kvm_is_error_hva(addr))
1895 if (__clear_user((void __user *)addr, PAGE_SIZE))
1897 vcpu->arch.hv_vapic = data;
1900 case HV_X64_MSR_EOI:
1901 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1902 case HV_X64_MSR_ICR:
1903 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1904 case HV_X64_MSR_TPR:
1905 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1907 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1908 "data 0x%llx\n", msr, data);
1915 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1917 gpa_t gpa = data & ~0x3f;
1919 /* Bits 2:5 are reserved, Should be zero */
1923 vcpu->arch.apf.msr_val = data;
1925 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1926 kvm_clear_async_pf_completion_queue(vcpu);
1927 kvm_async_pf_hash_reset(vcpu);
1931 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1935 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1936 kvm_async_pf_wakeup_all(vcpu);
1940 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1942 vcpu->arch.pv_time_enabled = false;
1945 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1949 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1952 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1953 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1954 vcpu->arch.st.accum_steal = delta;
1957 static void record_steal_time(struct kvm_vcpu *vcpu)
1959 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1962 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1963 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1966 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1967 vcpu->arch.st.steal.version += 2;
1968 vcpu->arch.st.accum_steal = 0;
1970 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1971 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1974 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1977 u32 msr = msr_info->index;
1978 u64 data = msr_info->data;
1981 case MSR_AMD64_NB_CFG:
1982 case MSR_IA32_UCODE_REV:
1983 case MSR_IA32_UCODE_WRITE:
1984 case MSR_VM_HSAVE_PA:
1985 case MSR_AMD64_PATCH_LOADER:
1986 case MSR_AMD64_BU_CFG2:
1990 return set_efer(vcpu, data);
1992 data &= ~(u64)0x40; /* ignore flush filter disable */
1993 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1994 data &= ~(u64)0x8; /* ignore TLB cache disable */
1996 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2001 case MSR_FAM10H_MMIO_CONF_BASE:
2003 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2008 case MSR_IA32_DEBUGCTLMSR:
2010 /* We support the non-activated case already */
2012 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2013 /* Values other than LBR and BTF are vendor-specific,
2014 thus reserved and should throw a #GP */
2017 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2020 case 0x200 ... 0x2ff:
2021 return set_msr_mtrr(vcpu, msr, data);
2022 case MSR_IA32_APICBASE:
2023 kvm_set_apic_base(vcpu, data);
2025 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2026 return kvm_x2apic_msr_write(vcpu, msr, data);
2027 case MSR_IA32_TSCDEADLINE:
2028 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2030 case MSR_IA32_TSC_ADJUST:
2031 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2032 if (!msr_info->host_initiated) {
2033 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2034 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2036 vcpu->arch.ia32_tsc_adjust_msr = data;
2039 case MSR_IA32_MISC_ENABLE:
2040 vcpu->arch.ia32_misc_enable_msr = data;
2042 case MSR_KVM_WALL_CLOCK_NEW:
2043 case MSR_KVM_WALL_CLOCK:
2044 vcpu->kvm->arch.wall_clock = data;
2045 kvm_write_wall_clock(vcpu->kvm, data);
2047 case MSR_KVM_SYSTEM_TIME_NEW:
2048 case MSR_KVM_SYSTEM_TIME: {
2050 kvmclock_reset(vcpu);
2052 vcpu->arch.time = data;
2053 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2055 /* we verify if the enable bit is set... */
2059 gpa_offset = data & ~(PAGE_MASK | 1);
2061 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2062 &vcpu->arch.pv_time, data & ~1ULL,
2063 sizeof(struct pvclock_vcpu_time_info)))
2064 vcpu->arch.pv_time_enabled = false;
2066 vcpu->arch.pv_time_enabled = true;
2070 case MSR_KVM_ASYNC_PF_EN:
2071 if (kvm_pv_enable_async_pf(vcpu, data))
2074 case MSR_KVM_STEAL_TIME:
2076 if (unlikely(!sched_info_on()))
2079 if (data & KVM_STEAL_RESERVED_MASK)
2082 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2083 data & KVM_STEAL_VALID_BITS,
2084 sizeof(struct kvm_steal_time)))
2087 vcpu->arch.st.msr_val = data;
2089 if (!(data & KVM_MSR_ENABLED))
2092 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2095 accumulate_steal_time(vcpu);
2098 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2101 case MSR_KVM_PV_EOI_EN:
2102 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2106 case MSR_IA32_MCG_CTL:
2107 case MSR_IA32_MCG_STATUS:
2108 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2109 return set_msr_mce(vcpu, msr, data);
2111 /* Performance counters are not protected by a CPUID bit,
2112 * so we should check all of them in the generic path for the sake of
2113 * cross vendor migration.
2114 * Writing a zero into the event select MSRs disables them,
2115 * which we perfectly emulate ;-). Any other value should be at least
2116 * reported, some guests depend on them.
2118 case MSR_K7_EVNTSEL0:
2119 case MSR_K7_EVNTSEL1:
2120 case MSR_K7_EVNTSEL2:
2121 case MSR_K7_EVNTSEL3:
2123 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2124 "0x%x data 0x%llx\n", msr, data);
2126 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2127 * so we ignore writes to make it happy.
2129 case MSR_K7_PERFCTR0:
2130 case MSR_K7_PERFCTR1:
2131 case MSR_K7_PERFCTR2:
2132 case MSR_K7_PERFCTR3:
2133 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2134 "0x%x data 0x%llx\n", msr, data);
2136 case MSR_P6_PERFCTR0:
2137 case MSR_P6_PERFCTR1:
2139 case MSR_P6_EVNTSEL0:
2140 case MSR_P6_EVNTSEL1:
2141 if (kvm_pmu_msr(vcpu, msr))
2142 return kvm_pmu_set_msr(vcpu, msr_info);
2144 if (pr || data != 0)
2145 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2146 "0x%x data 0x%llx\n", msr, data);
2148 case MSR_K7_CLK_CTL:
2150 * Ignore all writes to this no longer documented MSR.
2151 * Writes are only relevant for old K7 processors,
2152 * all pre-dating SVM, but a recommended workaround from
2153 * AMD for these chips. It is possible to specify the
2154 * affected processor models on the command line, hence
2155 * the need to ignore the workaround.
2158 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2159 if (kvm_hv_msr_partition_wide(msr)) {
2161 mutex_lock(&vcpu->kvm->lock);
2162 r = set_msr_hyperv_pw(vcpu, msr, data);
2163 mutex_unlock(&vcpu->kvm->lock);
2166 return set_msr_hyperv(vcpu, msr, data);
2168 case MSR_IA32_BBL_CR_CTL3:
2169 /* Drop writes to this legacy MSR -- see rdmsr
2170 * counterpart for further detail.
2172 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2174 case MSR_AMD64_OSVW_ID_LENGTH:
2175 if (!guest_cpuid_has_osvw(vcpu))
2177 vcpu->arch.osvw.length = data;
2179 case MSR_AMD64_OSVW_STATUS:
2180 if (!guest_cpuid_has_osvw(vcpu))
2182 vcpu->arch.osvw.status = data;
2185 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2186 return xen_hvm_config(vcpu, data);
2187 if (kvm_pmu_msr(vcpu, msr))
2188 return kvm_pmu_set_msr(vcpu, msr_info);
2190 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2194 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2201 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2205 * Reads an msr value (of 'msr_index') into 'pdata'.
2206 * Returns 0 on success, non-0 otherwise.
2207 * Assumes vcpu_load() was already called.
2209 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2211 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2214 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2216 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2218 if (!msr_mtrr_valid(msr))
2221 if (msr == MSR_MTRRdefType)
2222 *pdata = vcpu->arch.mtrr_state.def_type +
2223 (vcpu->arch.mtrr_state.enabled << 10);
2224 else if (msr == MSR_MTRRfix64K_00000)
2226 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2227 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2228 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2229 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2230 else if (msr == MSR_IA32_CR_PAT)
2231 *pdata = vcpu->arch.pat;
2232 else { /* Variable MTRRs */
2233 int idx, is_mtrr_mask;
2236 idx = (msr - 0x200) / 2;
2237 is_mtrr_mask = msr - 0x200 - 2 * idx;
2240 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2243 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2250 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2253 u64 mcg_cap = vcpu->arch.mcg_cap;
2254 unsigned bank_num = mcg_cap & 0xff;
2257 case MSR_IA32_P5_MC_ADDR:
2258 case MSR_IA32_P5_MC_TYPE:
2261 case MSR_IA32_MCG_CAP:
2262 data = vcpu->arch.mcg_cap;
2264 case MSR_IA32_MCG_CTL:
2265 if (!(mcg_cap & MCG_CTL_P))
2267 data = vcpu->arch.mcg_ctl;
2269 case MSR_IA32_MCG_STATUS:
2270 data = vcpu->arch.mcg_status;
2273 if (msr >= MSR_IA32_MC0_CTL &&
2274 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2275 u32 offset = msr - MSR_IA32_MC0_CTL;
2276 data = vcpu->arch.mce_banks[offset];
2285 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2288 struct kvm *kvm = vcpu->kvm;
2291 case HV_X64_MSR_GUEST_OS_ID:
2292 data = kvm->arch.hv_guest_os_id;
2294 case HV_X64_MSR_HYPERCALL:
2295 data = kvm->arch.hv_hypercall;
2298 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2306 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2311 case HV_X64_MSR_VP_INDEX: {
2314 kvm_for_each_vcpu(r, v, vcpu->kvm)
2319 case HV_X64_MSR_EOI:
2320 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2321 case HV_X64_MSR_ICR:
2322 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2323 case HV_X64_MSR_TPR:
2324 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2325 case HV_X64_MSR_APIC_ASSIST_PAGE:
2326 data = vcpu->arch.hv_vapic;
2329 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2336 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2341 case MSR_IA32_PLATFORM_ID:
2342 case MSR_IA32_EBL_CR_POWERON:
2343 case MSR_IA32_DEBUGCTLMSR:
2344 case MSR_IA32_LASTBRANCHFROMIP:
2345 case MSR_IA32_LASTBRANCHTOIP:
2346 case MSR_IA32_LASTINTFROMIP:
2347 case MSR_IA32_LASTINTTOIP:
2350 case MSR_VM_HSAVE_PA:
2351 case MSR_K7_EVNTSEL0:
2352 case MSR_K7_PERFCTR0:
2353 case MSR_K8_INT_PENDING_MSG:
2354 case MSR_AMD64_NB_CFG:
2355 case MSR_FAM10H_MMIO_CONF_BASE:
2356 case MSR_AMD64_BU_CFG2:
2359 case MSR_P6_PERFCTR0:
2360 case MSR_P6_PERFCTR1:
2361 case MSR_P6_EVNTSEL0:
2362 case MSR_P6_EVNTSEL1:
2363 if (kvm_pmu_msr(vcpu, msr))
2364 return kvm_pmu_get_msr(vcpu, msr, pdata);
2367 case MSR_IA32_UCODE_REV:
2368 data = 0x100000000ULL;
2371 data = 0x500 | KVM_NR_VAR_MTRR;
2373 case 0x200 ... 0x2ff:
2374 return get_msr_mtrr(vcpu, msr, pdata);
2375 case 0xcd: /* fsb frequency */
2379 * MSR_EBC_FREQUENCY_ID
2380 * Conservative value valid for even the basic CPU models.
2381 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2382 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2383 * and 266MHz for model 3, or 4. Set Core Clock
2384 * Frequency to System Bus Frequency Ratio to 1 (bits
2385 * 31:24) even though these are only valid for CPU
2386 * models > 2, however guests may end up dividing or
2387 * multiplying by zero otherwise.
2389 case MSR_EBC_FREQUENCY_ID:
2392 case MSR_IA32_APICBASE:
2393 data = kvm_get_apic_base(vcpu);
2395 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2396 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2398 case MSR_IA32_TSCDEADLINE:
2399 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2401 case MSR_IA32_TSC_ADJUST:
2402 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2404 case MSR_IA32_MISC_ENABLE:
2405 data = vcpu->arch.ia32_misc_enable_msr;
2407 case MSR_IA32_PERF_STATUS:
2408 /* TSC increment by tick */
2410 /* CPU multiplier */
2411 data |= (((uint64_t)4ULL) << 40);
2414 data = vcpu->arch.efer;
2416 case MSR_KVM_WALL_CLOCK:
2417 case MSR_KVM_WALL_CLOCK_NEW:
2418 data = vcpu->kvm->arch.wall_clock;
2420 case MSR_KVM_SYSTEM_TIME:
2421 case MSR_KVM_SYSTEM_TIME_NEW:
2422 data = vcpu->arch.time;
2424 case MSR_KVM_ASYNC_PF_EN:
2425 data = vcpu->arch.apf.msr_val;
2427 case MSR_KVM_STEAL_TIME:
2428 data = vcpu->arch.st.msr_val;
2430 case MSR_KVM_PV_EOI_EN:
2431 data = vcpu->arch.pv_eoi.msr_val;
2433 case MSR_IA32_P5_MC_ADDR:
2434 case MSR_IA32_P5_MC_TYPE:
2435 case MSR_IA32_MCG_CAP:
2436 case MSR_IA32_MCG_CTL:
2437 case MSR_IA32_MCG_STATUS:
2438 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2439 return get_msr_mce(vcpu, msr, pdata);
2440 case MSR_K7_CLK_CTL:
2442 * Provide expected ramp-up count for K7. All other
2443 * are set to zero, indicating minimum divisors for
2446 * This prevents guest kernels on AMD host with CPU
2447 * type 6, model 8 and higher from exploding due to
2448 * the rdmsr failing.
2452 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2453 if (kvm_hv_msr_partition_wide(msr)) {
2455 mutex_lock(&vcpu->kvm->lock);
2456 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2457 mutex_unlock(&vcpu->kvm->lock);
2460 return get_msr_hyperv(vcpu, msr, pdata);
2462 case MSR_IA32_BBL_CR_CTL3:
2463 /* This legacy MSR exists but isn't fully documented in current
2464 * silicon. It is however accessed by winxp in very narrow
2465 * scenarios where it sets bit #19, itself documented as
2466 * a "reserved" bit. Best effort attempt to source coherent
2467 * read data here should the balance of the register be
2468 * interpreted by the guest:
2470 * L2 cache control register 3: 64GB range, 256KB size,
2471 * enabled, latency 0x1, configured
2475 case MSR_AMD64_OSVW_ID_LENGTH:
2476 if (!guest_cpuid_has_osvw(vcpu))
2478 data = vcpu->arch.osvw.length;
2480 case MSR_AMD64_OSVW_STATUS:
2481 if (!guest_cpuid_has_osvw(vcpu))
2483 data = vcpu->arch.osvw.status;
2486 if (kvm_pmu_msr(vcpu, msr))
2487 return kvm_pmu_get_msr(vcpu, msr, pdata);
2489 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2492 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2500 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2503 * Read or write a bunch of msrs. All parameters are kernel addresses.
2505 * @return number of msrs set successfully.
2507 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2508 struct kvm_msr_entry *entries,
2509 int (*do_msr)(struct kvm_vcpu *vcpu,
2510 unsigned index, u64 *data))
2514 idx = srcu_read_lock(&vcpu->kvm->srcu);
2515 for (i = 0; i < msrs->nmsrs; ++i)
2516 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2518 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2524 * Read or write a bunch of msrs. Parameters are user addresses.
2526 * @return number of msrs set successfully.
2528 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2529 int (*do_msr)(struct kvm_vcpu *vcpu,
2530 unsigned index, u64 *data),
2533 struct kvm_msrs msrs;
2534 struct kvm_msr_entry *entries;
2539 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2543 if (msrs.nmsrs >= MAX_IO_MSRS)
2546 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2547 entries = memdup_user(user_msrs->entries, size);
2548 if (IS_ERR(entries)) {
2549 r = PTR_ERR(entries);
2553 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2558 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2569 int kvm_dev_ioctl_check_extension(long ext)
2574 case KVM_CAP_IRQCHIP:
2576 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2577 case KVM_CAP_SET_TSS_ADDR:
2578 case KVM_CAP_EXT_CPUID:
2579 case KVM_CAP_EXT_EMUL_CPUID:
2580 case KVM_CAP_CLOCKSOURCE:
2582 case KVM_CAP_NOP_IO_DELAY:
2583 case KVM_CAP_MP_STATE:
2584 case KVM_CAP_SYNC_MMU:
2585 case KVM_CAP_USER_NMI:
2586 case KVM_CAP_REINJECT_CONTROL:
2587 case KVM_CAP_IRQ_INJECT_STATUS:
2589 case KVM_CAP_IOEVENTFD:
2591 case KVM_CAP_PIT_STATE2:
2592 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2593 case KVM_CAP_XEN_HVM:
2594 case KVM_CAP_ADJUST_CLOCK:
2595 case KVM_CAP_VCPU_EVENTS:
2596 case KVM_CAP_HYPERV:
2597 case KVM_CAP_HYPERV_VAPIC:
2598 case KVM_CAP_HYPERV_SPIN:
2599 case KVM_CAP_PCI_SEGMENT:
2600 case KVM_CAP_DEBUGREGS:
2601 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2603 case KVM_CAP_ASYNC_PF:
2604 case KVM_CAP_GET_TSC_KHZ:
2605 case KVM_CAP_KVMCLOCK_CTRL:
2606 case KVM_CAP_READONLY_MEM:
2607 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2608 case KVM_CAP_ASSIGN_DEV_IRQ:
2609 case KVM_CAP_PCI_2_3:
2613 case KVM_CAP_COALESCED_MMIO:
2614 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2617 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2619 case KVM_CAP_NR_VCPUS:
2620 r = KVM_SOFT_MAX_VCPUS;
2622 case KVM_CAP_MAX_VCPUS:
2625 case KVM_CAP_NR_MEMSLOTS:
2626 r = KVM_USER_MEM_SLOTS;
2628 case KVM_CAP_PV_MMU: /* obsolete */
2631 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2633 r = iommu_present(&pci_bus_type);
2637 r = KVM_MAX_MCE_BANKS;
2642 case KVM_CAP_TSC_CONTROL:
2643 r = kvm_has_tsc_control;
2645 case KVM_CAP_TSC_DEADLINE_TIMER:
2646 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2656 long kvm_arch_dev_ioctl(struct file *filp,
2657 unsigned int ioctl, unsigned long arg)
2659 void __user *argp = (void __user *)arg;
2663 case KVM_GET_MSR_INDEX_LIST: {
2664 struct kvm_msr_list __user *user_msr_list = argp;
2665 struct kvm_msr_list msr_list;
2669 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2672 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2673 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2676 if (n < msr_list.nmsrs)
2679 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2680 num_msrs_to_save * sizeof(u32)))
2682 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2684 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2689 case KVM_GET_SUPPORTED_CPUID:
2690 case KVM_GET_EMULATED_CPUID: {
2691 struct kvm_cpuid2 __user *cpuid_arg = argp;
2692 struct kvm_cpuid2 cpuid;
2695 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2698 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2704 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2709 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2712 mce_cap = KVM_MCE_CAP_SUPPORTED;
2714 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2726 static void wbinvd_ipi(void *garbage)
2731 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2733 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2736 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2738 /* Address WBINVD may be executed by guest */
2739 if (need_emulate_wbinvd(vcpu)) {
2740 if (kvm_x86_ops->has_wbinvd_exit())
2741 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2742 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2743 smp_call_function_single(vcpu->cpu,
2744 wbinvd_ipi, NULL, 1);
2747 kvm_x86_ops->vcpu_load(vcpu, cpu);
2749 /* Apply any externally detected TSC adjustments (due to suspend) */
2750 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2751 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2752 vcpu->arch.tsc_offset_adjustment = 0;
2753 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2756 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2757 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2758 native_read_tsc() - vcpu->arch.last_host_tsc;
2760 mark_tsc_unstable("KVM discovered backwards TSC");
2761 if (check_tsc_unstable()) {
2762 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2763 vcpu->arch.last_guest_tsc);
2764 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2765 vcpu->arch.tsc_catchup = 1;
2768 * On a host with synchronized TSC, there is no need to update
2769 * kvmclock on vcpu->cpu migration
2771 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2772 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2773 if (vcpu->cpu != cpu)
2774 kvm_migrate_timers(vcpu);
2778 accumulate_steal_time(vcpu);
2779 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2782 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2784 kvm_x86_ops->vcpu_put(vcpu);
2785 kvm_put_guest_fpu(vcpu);
2786 vcpu->arch.last_host_tsc = native_read_tsc();
2789 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2790 struct kvm_lapic_state *s)
2792 kvm_x86_ops->sync_pir_to_irr(vcpu);
2793 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2798 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2799 struct kvm_lapic_state *s)
2801 kvm_apic_post_state_restore(vcpu, s);
2802 update_cr8_intercept(vcpu);
2807 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2808 struct kvm_interrupt *irq)
2810 if (irq->irq >= KVM_NR_INTERRUPTS)
2812 if (irqchip_in_kernel(vcpu->kvm))
2815 kvm_queue_interrupt(vcpu, irq->irq, false);
2816 kvm_make_request(KVM_REQ_EVENT, vcpu);
2821 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2823 kvm_inject_nmi(vcpu);
2828 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2829 struct kvm_tpr_access_ctl *tac)
2833 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2837 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2841 unsigned bank_num = mcg_cap & 0xff, bank;
2844 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2846 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2849 vcpu->arch.mcg_cap = mcg_cap;
2850 /* Init IA32_MCG_CTL to all 1s */
2851 if (mcg_cap & MCG_CTL_P)
2852 vcpu->arch.mcg_ctl = ~(u64)0;
2853 /* Init IA32_MCi_CTL to all 1s */
2854 for (bank = 0; bank < bank_num; bank++)
2855 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2860 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2861 struct kvm_x86_mce *mce)
2863 u64 mcg_cap = vcpu->arch.mcg_cap;
2864 unsigned bank_num = mcg_cap & 0xff;
2865 u64 *banks = vcpu->arch.mce_banks;
2867 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2870 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2871 * reporting is disabled
2873 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2874 vcpu->arch.mcg_ctl != ~(u64)0)
2876 banks += 4 * mce->bank;
2878 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2879 * reporting is disabled for the bank
2881 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2883 if (mce->status & MCI_STATUS_UC) {
2884 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2885 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2886 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2889 if (banks[1] & MCI_STATUS_VAL)
2890 mce->status |= MCI_STATUS_OVER;
2891 banks[2] = mce->addr;
2892 banks[3] = mce->misc;
2893 vcpu->arch.mcg_status = mce->mcg_status;
2894 banks[1] = mce->status;
2895 kvm_queue_exception(vcpu, MC_VECTOR);
2896 } else if (!(banks[1] & MCI_STATUS_VAL)
2897 || !(banks[1] & MCI_STATUS_UC)) {
2898 if (banks[1] & MCI_STATUS_VAL)
2899 mce->status |= MCI_STATUS_OVER;
2900 banks[2] = mce->addr;
2901 banks[3] = mce->misc;
2902 banks[1] = mce->status;
2904 banks[1] |= MCI_STATUS_OVER;
2908 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2909 struct kvm_vcpu_events *events)
2912 events->exception.injected =
2913 vcpu->arch.exception.pending &&
2914 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2915 events->exception.nr = vcpu->arch.exception.nr;
2916 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2917 events->exception.pad = 0;
2918 events->exception.error_code = vcpu->arch.exception.error_code;
2920 events->interrupt.injected =
2921 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2922 events->interrupt.nr = vcpu->arch.interrupt.nr;
2923 events->interrupt.soft = 0;
2924 events->interrupt.shadow =
2925 kvm_x86_ops->get_interrupt_shadow(vcpu,
2926 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2928 events->nmi.injected = vcpu->arch.nmi_injected;
2929 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2930 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2931 events->nmi.pad = 0;
2933 events->sipi_vector = 0; /* never valid when reporting to user space */
2935 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2936 | KVM_VCPUEVENT_VALID_SHADOW);
2937 memset(&events->reserved, 0, sizeof(events->reserved));
2940 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2941 struct kvm_vcpu_events *events)
2943 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2944 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2945 | KVM_VCPUEVENT_VALID_SHADOW))
2949 vcpu->arch.exception.pending = events->exception.injected;
2950 vcpu->arch.exception.nr = events->exception.nr;
2951 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2952 vcpu->arch.exception.error_code = events->exception.error_code;
2954 vcpu->arch.interrupt.pending = events->interrupt.injected;
2955 vcpu->arch.interrupt.nr = events->interrupt.nr;
2956 vcpu->arch.interrupt.soft = events->interrupt.soft;
2957 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2958 kvm_x86_ops->set_interrupt_shadow(vcpu,
2959 events->interrupt.shadow);
2961 vcpu->arch.nmi_injected = events->nmi.injected;
2962 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2963 vcpu->arch.nmi_pending = events->nmi.pending;
2964 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2966 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2967 kvm_vcpu_has_lapic(vcpu))
2968 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2970 kvm_make_request(KVM_REQ_EVENT, vcpu);
2975 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2976 struct kvm_debugregs *dbgregs)
2978 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2979 dbgregs->dr6 = vcpu->arch.dr6;
2980 dbgregs->dr7 = vcpu->arch.dr7;
2982 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2985 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2986 struct kvm_debugregs *dbgregs)
2991 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2992 vcpu->arch.dr6 = dbgregs->dr6;
2993 vcpu->arch.dr7 = dbgregs->dr7;
2998 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2999 struct kvm_xsave *guest_xsave)
3001 if (cpu_has_xsave) {
3002 memcpy(guest_xsave->region,
3003 &vcpu->arch.guest_fpu.state->xsave,
3004 vcpu->arch.guest_xstate_size);
3005 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3006 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3008 memcpy(guest_xsave->region,
3009 &vcpu->arch.guest_fpu.state->fxsave,
3010 sizeof(struct i387_fxsave_struct));
3011 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3016 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3017 struct kvm_xsave *guest_xsave)
3020 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3022 if (cpu_has_xsave) {
3024 * Here we allow setting states that are not present in
3025 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3026 * with old userspace.
3028 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3030 if (xstate_bv & ~host_xcr0)
3032 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3033 guest_xsave->region, vcpu->arch.guest_xstate_size);
3035 if (xstate_bv & ~XSTATE_FPSSE)
3037 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3038 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3043 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3044 struct kvm_xcrs *guest_xcrs)
3046 if (!cpu_has_xsave) {
3047 guest_xcrs->nr_xcrs = 0;
3051 guest_xcrs->nr_xcrs = 1;
3052 guest_xcrs->flags = 0;
3053 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3054 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3057 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3058 struct kvm_xcrs *guest_xcrs)
3065 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3068 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3069 /* Only support XCR0 currently */
3070 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3071 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3072 guest_xcrs->xcrs[i].value);
3081 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3082 * stopped by the hypervisor. This function will be called from the host only.
3083 * EINVAL is returned when the host attempts to set the flag for a guest that
3084 * does not support pv clocks.
3086 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3088 if (!vcpu->arch.pv_time_enabled)
3090 vcpu->arch.pvclock_set_guest_stopped_request = true;
3091 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3095 long kvm_arch_vcpu_ioctl(struct file *filp,
3096 unsigned int ioctl, unsigned long arg)
3098 struct kvm_vcpu *vcpu = filp->private_data;
3099 void __user *argp = (void __user *)arg;
3102 struct kvm_lapic_state *lapic;
3103 struct kvm_xsave *xsave;
3104 struct kvm_xcrs *xcrs;
3110 case KVM_GET_LAPIC: {
3112 if (!vcpu->arch.apic)
3114 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3119 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3123 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3128 case KVM_SET_LAPIC: {
3130 if (!vcpu->arch.apic)
3132 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3133 if (IS_ERR(u.lapic))
3134 return PTR_ERR(u.lapic);
3136 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3139 case KVM_INTERRUPT: {
3140 struct kvm_interrupt irq;
3143 if (copy_from_user(&irq, argp, sizeof irq))
3145 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3149 r = kvm_vcpu_ioctl_nmi(vcpu);
3152 case KVM_SET_CPUID: {
3153 struct kvm_cpuid __user *cpuid_arg = argp;
3154 struct kvm_cpuid cpuid;
3157 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3159 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3162 case KVM_SET_CPUID2: {
3163 struct kvm_cpuid2 __user *cpuid_arg = argp;
3164 struct kvm_cpuid2 cpuid;
3167 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3169 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3170 cpuid_arg->entries);
3173 case KVM_GET_CPUID2: {
3174 struct kvm_cpuid2 __user *cpuid_arg = argp;
3175 struct kvm_cpuid2 cpuid;
3178 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3180 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3181 cpuid_arg->entries);
3185 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3191 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3194 r = msr_io(vcpu, argp, do_set_msr, 0);
3196 case KVM_TPR_ACCESS_REPORTING: {
3197 struct kvm_tpr_access_ctl tac;
3200 if (copy_from_user(&tac, argp, sizeof tac))
3202 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3206 if (copy_to_user(argp, &tac, sizeof tac))
3211 case KVM_SET_VAPIC_ADDR: {
3212 struct kvm_vapic_addr va;
3215 if (!irqchip_in_kernel(vcpu->kvm))
3218 if (copy_from_user(&va, argp, sizeof va))
3221 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3224 case KVM_X86_SETUP_MCE: {
3228 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3230 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3233 case KVM_X86_SET_MCE: {
3234 struct kvm_x86_mce mce;
3237 if (copy_from_user(&mce, argp, sizeof mce))
3239 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3242 case KVM_GET_VCPU_EVENTS: {
3243 struct kvm_vcpu_events events;
3245 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3248 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3253 case KVM_SET_VCPU_EVENTS: {
3254 struct kvm_vcpu_events events;
3257 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3260 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3263 case KVM_GET_DEBUGREGS: {
3264 struct kvm_debugregs dbgregs;
3266 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3269 if (copy_to_user(argp, &dbgregs,
3270 sizeof(struct kvm_debugregs)))
3275 case KVM_SET_DEBUGREGS: {
3276 struct kvm_debugregs dbgregs;
3279 if (copy_from_user(&dbgregs, argp,
3280 sizeof(struct kvm_debugregs)))
3283 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3286 case KVM_GET_XSAVE: {
3287 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3292 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3295 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3300 case KVM_SET_XSAVE: {
3301 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3302 if (IS_ERR(u.xsave))
3303 return PTR_ERR(u.xsave);
3305 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3308 case KVM_GET_XCRS: {
3309 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3314 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3317 if (copy_to_user(argp, u.xcrs,
3318 sizeof(struct kvm_xcrs)))
3323 case KVM_SET_XCRS: {
3324 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3326 return PTR_ERR(u.xcrs);
3328 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3331 case KVM_SET_TSC_KHZ: {
3335 user_tsc_khz = (u32)arg;
3337 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3340 if (user_tsc_khz == 0)
3341 user_tsc_khz = tsc_khz;
3343 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3348 case KVM_GET_TSC_KHZ: {
3349 r = vcpu->arch.virtual_tsc_khz;
3352 case KVM_KVMCLOCK_CTRL: {
3353 r = kvm_set_guest_paused(vcpu);
3364 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3366 return VM_FAULT_SIGBUS;
3369 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3373 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3375 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3379 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3382 kvm->arch.ept_identity_map_addr = ident_addr;
3386 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3387 u32 kvm_nr_mmu_pages)
3389 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3392 mutex_lock(&kvm->slots_lock);
3394 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3395 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3397 mutex_unlock(&kvm->slots_lock);
3401 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3403 return kvm->arch.n_max_mmu_pages;
3406 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3411 switch (chip->chip_id) {
3412 case KVM_IRQCHIP_PIC_MASTER:
3413 memcpy(&chip->chip.pic,
3414 &pic_irqchip(kvm)->pics[0],
3415 sizeof(struct kvm_pic_state));
3417 case KVM_IRQCHIP_PIC_SLAVE:
3418 memcpy(&chip->chip.pic,
3419 &pic_irqchip(kvm)->pics[1],
3420 sizeof(struct kvm_pic_state));
3422 case KVM_IRQCHIP_IOAPIC:
3423 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3432 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3437 switch (chip->chip_id) {
3438 case KVM_IRQCHIP_PIC_MASTER:
3439 spin_lock(&pic_irqchip(kvm)->lock);
3440 memcpy(&pic_irqchip(kvm)->pics[0],
3442 sizeof(struct kvm_pic_state));
3443 spin_unlock(&pic_irqchip(kvm)->lock);
3445 case KVM_IRQCHIP_PIC_SLAVE:
3446 spin_lock(&pic_irqchip(kvm)->lock);
3447 memcpy(&pic_irqchip(kvm)->pics[1],
3449 sizeof(struct kvm_pic_state));
3450 spin_unlock(&pic_irqchip(kvm)->lock);
3452 case KVM_IRQCHIP_IOAPIC:
3453 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3459 kvm_pic_update_irq(pic_irqchip(kvm));
3463 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3467 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3468 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3469 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3473 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3477 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3478 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3479 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3480 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3484 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3488 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3489 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3490 sizeof(ps->channels));
3491 ps->flags = kvm->arch.vpit->pit_state.flags;
3492 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3493 memset(&ps->reserved, 0, sizeof(ps->reserved));
3497 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3499 int r = 0, start = 0;
3500 u32 prev_legacy, cur_legacy;
3501 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3502 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3503 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3504 if (!prev_legacy && cur_legacy)
3506 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3507 sizeof(kvm->arch.vpit->pit_state.channels));
3508 kvm->arch.vpit->pit_state.flags = ps->flags;
3509 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3510 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3514 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3515 struct kvm_reinject_control *control)
3517 if (!kvm->arch.vpit)
3519 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3520 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3521 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3526 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3527 * @kvm: kvm instance
3528 * @log: slot id and address to which we copy the log
3530 * We need to keep it in mind that VCPU threads can write to the bitmap
3531 * concurrently. So, to avoid losing data, we keep the following order for
3534 * 1. Take a snapshot of the bit and clear it if needed.
3535 * 2. Write protect the corresponding page.
3536 * 3. Flush TLB's if needed.
3537 * 4. Copy the snapshot to the userspace.
3539 * Between 2 and 3, the guest may write to the page using the remaining TLB
3540 * entry. This is not a problem because the page will be reported dirty at
3541 * step 4 using the snapshot taken before and step 3 ensures that successive
3542 * writes will be logged for the next call.
3544 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3547 struct kvm_memory_slot *memslot;
3549 unsigned long *dirty_bitmap;
3550 unsigned long *dirty_bitmap_buffer;
3551 bool is_dirty = false;
3553 mutex_lock(&kvm->slots_lock);
3556 if (log->slot >= KVM_USER_MEM_SLOTS)
3559 memslot = id_to_memslot(kvm->memslots, log->slot);
3561 dirty_bitmap = memslot->dirty_bitmap;
3566 n = kvm_dirty_bitmap_bytes(memslot);
3568 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3569 memset(dirty_bitmap_buffer, 0, n);
3571 spin_lock(&kvm->mmu_lock);
3573 for (i = 0; i < n / sizeof(long); i++) {
3577 if (!dirty_bitmap[i])
3582 mask = xchg(&dirty_bitmap[i], 0);
3583 dirty_bitmap_buffer[i] = mask;
3585 offset = i * BITS_PER_LONG;
3586 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3589 kvm_flush_remote_tlbs(kvm);
3591 spin_unlock(&kvm->mmu_lock);
3594 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3599 mutex_unlock(&kvm->slots_lock);
3603 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3606 if (!irqchip_in_kernel(kvm))
3609 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3610 irq_event->irq, irq_event->level,
3615 long kvm_arch_vm_ioctl(struct file *filp,
3616 unsigned int ioctl, unsigned long arg)
3618 struct kvm *kvm = filp->private_data;
3619 void __user *argp = (void __user *)arg;
3622 * This union makes it completely explicit to gcc-3.x
3623 * that these two variables' stack usage should be
3624 * combined, not added together.
3627 struct kvm_pit_state ps;
3628 struct kvm_pit_state2 ps2;
3629 struct kvm_pit_config pit_config;
3633 case KVM_SET_TSS_ADDR:
3634 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3636 case KVM_SET_IDENTITY_MAP_ADDR: {
3640 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3642 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3645 case KVM_SET_NR_MMU_PAGES:
3646 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3648 case KVM_GET_NR_MMU_PAGES:
3649 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3651 case KVM_CREATE_IRQCHIP: {
3652 struct kvm_pic *vpic;
3654 mutex_lock(&kvm->lock);
3657 goto create_irqchip_unlock;
3659 if (atomic_read(&kvm->online_vcpus))
3660 goto create_irqchip_unlock;
3662 vpic = kvm_create_pic(kvm);
3664 r = kvm_ioapic_init(kvm);
3666 mutex_lock(&kvm->slots_lock);
3667 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3669 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3671 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3673 mutex_unlock(&kvm->slots_lock);
3675 goto create_irqchip_unlock;
3678 goto create_irqchip_unlock;
3680 kvm->arch.vpic = vpic;
3682 r = kvm_setup_default_irq_routing(kvm);
3684 mutex_lock(&kvm->slots_lock);
3685 mutex_lock(&kvm->irq_lock);
3686 kvm_ioapic_destroy(kvm);
3687 kvm_destroy_pic(kvm);
3688 mutex_unlock(&kvm->irq_lock);
3689 mutex_unlock(&kvm->slots_lock);
3691 create_irqchip_unlock:
3692 mutex_unlock(&kvm->lock);
3695 case KVM_CREATE_PIT:
3696 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3698 case KVM_CREATE_PIT2:
3700 if (copy_from_user(&u.pit_config, argp,
3701 sizeof(struct kvm_pit_config)))
3704 mutex_lock(&kvm->slots_lock);
3707 goto create_pit_unlock;
3709 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3713 mutex_unlock(&kvm->slots_lock);
3715 case KVM_GET_IRQCHIP: {
3716 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3717 struct kvm_irqchip *chip;
3719 chip = memdup_user(argp, sizeof(*chip));
3726 if (!irqchip_in_kernel(kvm))
3727 goto get_irqchip_out;
3728 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3730 goto get_irqchip_out;
3732 if (copy_to_user(argp, chip, sizeof *chip))
3733 goto get_irqchip_out;
3739 case KVM_SET_IRQCHIP: {
3740 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3741 struct kvm_irqchip *chip;
3743 chip = memdup_user(argp, sizeof(*chip));
3750 if (!irqchip_in_kernel(kvm))
3751 goto set_irqchip_out;
3752 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3754 goto set_irqchip_out;
3762 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3765 if (!kvm->arch.vpit)
3767 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3771 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3778 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3781 if (!kvm->arch.vpit)
3783 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3786 case KVM_GET_PIT2: {
3788 if (!kvm->arch.vpit)
3790 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3794 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3799 case KVM_SET_PIT2: {
3801 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3804 if (!kvm->arch.vpit)
3806 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3809 case KVM_REINJECT_CONTROL: {
3810 struct kvm_reinject_control control;
3812 if (copy_from_user(&control, argp, sizeof(control)))
3814 r = kvm_vm_ioctl_reinject(kvm, &control);
3817 case KVM_XEN_HVM_CONFIG: {
3819 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3820 sizeof(struct kvm_xen_hvm_config)))
3823 if (kvm->arch.xen_hvm_config.flags)
3828 case KVM_SET_CLOCK: {
3829 struct kvm_clock_data user_ns;
3834 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3842 local_irq_disable();
3843 now_ns = get_kernel_ns();
3844 delta = user_ns.clock - now_ns;
3846 kvm->arch.kvmclock_offset = delta;
3847 kvm_gen_update_masterclock(kvm);
3850 case KVM_GET_CLOCK: {
3851 struct kvm_clock_data user_ns;
3854 local_irq_disable();
3855 now_ns = get_kernel_ns();
3856 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3859 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3862 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3875 static void kvm_init_msr_list(void)
3880 /* skip the first msrs in the list. KVM-specific */
3881 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3882 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3885 msrs_to_save[j] = msrs_to_save[i];
3888 num_msrs_to_save = j;
3891 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3899 if (!(vcpu->arch.apic &&
3900 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3901 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3912 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3919 if (!(vcpu->arch.apic &&
3920 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3921 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3923 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3933 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3934 struct kvm_segment *var, int seg)
3936 kvm_x86_ops->set_segment(vcpu, var, seg);
3939 void kvm_get_segment(struct kvm_vcpu *vcpu,
3940 struct kvm_segment *var, int seg)
3942 kvm_x86_ops->get_segment(vcpu, var, seg);
3945 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3948 struct x86_exception exception;
3950 BUG_ON(!mmu_is_nested(vcpu));
3952 /* NPT walks are always user-walks */
3953 access |= PFERR_USER_MASK;
3954 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3959 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3960 struct x86_exception *exception)
3962 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3963 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3966 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3967 struct x86_exception *exception)
3969 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3970 access |= PFERR_FETCH_MASK;
3971 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3974 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3975 struct x86_exception *exception)
3977 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3978 access |= PFERR_WRITE_MASK;
3979 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3982 /* uses this to access any guest's mapped memory without checking CPL */
3983 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3984 struct x86_exception *exception)
3986 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3989 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3990 struct kvm_vcpu *vcpu, u32 access,
3991 struct x86_exception *exception)
3994 int r = X86EMUL_CONTINUE;
3997 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3999 unsigned offset = addr & (PAGE_SIZE-1);
4000 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4003 if (gpa == UNMAPPED_GVA)
4004 return X86EMUL_PROPAGATE_FAULT;
4005 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
4007 r = X86EMUL_IO_NEEDED;
4019 /* used for instruction fetching */
4020 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4021 gva_t addr, void *val, unsigned int bytes,
4022 struct x86_exception *exception)
4024 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4025 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4027 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4028 access | PFERR_FETCH_MASK,
4032 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4033 gva_t addr, void *val, unsigned int bytes,
4034 struct x86_exception *exception)
4036 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4037 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4039 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4042 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4044 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4045 gva_t addr, void *val, unsigned int bytes,
4046 struct x86_exception *exception)
4048 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4049 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4052 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4053 gva_t addr, void *val,
4055 struct x86_exception *exception)
4057 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4059 int r = X86EMUL_CONTINUE;
4062 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4065 unsigned offset = addr & (PAGE_SIZE-1);
4066 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4069 if (gpa == UNMAPPED_GVA)
4070 return X86EMUL_PROPAGATE_FAULT;
4071 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4073 r = X86EMUL_IO_NEEDED;
4084 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4086 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4087 gpa_t *gpa, struct x86_exception *exception,
4090 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4091 | (write ? PFERR_WRITE_MASK : 0);
4093 if (vcpu_match_mmio_gva(vcpu, gva)
4094 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
4095 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4096 (gva & (PAGE_SIZE - 1));
4097 trace_vcpu_match_mmio(gva, *gpa, write, false);
4101 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4103 if (*gpa == UNMAPPED_GVA)
4106 /* For APIC access vmexit */
4107 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4110 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4111 trace_vcpu_match_mmio(gva, *gpa, write, true);
4118 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4119 const void *val, int bytes)
4123 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4126 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4130 struct read_write_emulator_ops {
4131 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4133 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4134 void *val, int bytes);
4135 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4136 int bytes, void *val);
4137 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4138 void *val, int bytes);
4142 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4144 if (vcpu->mmio_read_completed) {
4145 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4146 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4147 vcpu->mmio_read_completed = 0;
4154 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4155 void *val, int bytes)
4157 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4160 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4161 void *val, int bytes)
4163 return emulator_write_phys(vcpu, gpa, val, bytes);
4166 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4168 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4169 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4172 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4173 void *val, int bytes)
4175 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4176 return X86EMUL_IO_NEEDED;
4179 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4180 void *val, int bytes)
4182 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4184 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4185 return X86EMUL_CONTINUE;
4188 static const struct read_write_emulator_ops read_emultor = {
4189 .read_write_prepare = read_prepare,
4190 .read_write_emulate = read_emulate,
4191 .read_write_mmio = vcpu_mmio_read,
4192 .read_write_exit_mmio = read_exit_mmio,
4195 static const struct read_write_emulator_ops write_emultor = {
4196 .read_write_emulate = write_emulate,
4197 .read_write_mmio = write_mmio,
4198 .read_write_exit_mmio = write_exit_mmio,
4202 static int emulator_read_write_onepage(unsigned long addr, void *val,
4204 struct x86_exception *exception,
4205 struct kvm_vcpu *vcpu,
4206 const struct read_write_emulator_ops *ops)
4210 bool write = ops->write;
4211 struct kvm_mmio_fragment *frag;
4213 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4216 return X86EMUL_PROPAGATE_FAULT;
4218 /* For APIC access vmexit */
4222 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4223 return X86EMUL_CONTINUE;
4227 * Is this MMIO handled locally?
4229 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4230 if (handled == bytes)
4231 return X86EMUL_CONTINUE;
4237 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4238 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4242 return X86EMUL_CONTINUE;
4245 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4246 void *val, unsigned int bytes,
4247 struct x86_exception *exception,
4248 const struct read_write_emulator_ops *ops)
4250 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4254 if (ops->read_write_prepare &&
4255 ops->read_write_prepare(vcpu, val, bytes))
4256 return X86EMUL_CONTINUE;
4258 vcpu->mmio_nr_fragments = 0;
4260 /* Crossing a page boundary? */
4261 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4264 now = -addr & ~PAGE_MASK;
4265 rc = emulator_read_write_onepage(addr, val, now, exception,
4268 if (rc != X86EMUL_CONTINUE)
4275 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4277 if (rc != X86EMUL_CONTINUE)
4280 if (!vcpu->mmio_nr_fragments)
4283 gpa = vcpu->mmio_fragments[0].gpa;
4285 vcpu->mmio_needed = 1;
4286 vcpu->mmio_cur_fragment = 0;
4288 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4289 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4290 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4291 vcpu->run->mmio.phys_addr = gpa;
4293 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4296 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4300 struct x86_exception *exception)
4302 return emulator_read_write(ctxt, addr, val, bytes,
4303 exception, &read_emultor);
4306 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4310 struct x86_exception *exception)
4312 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4313 exception, &write_emultor);
4316 #define CMPXCHG_TYPE(t, ptr, old, new) \
4317 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4319 #ifdef CONFIG_X86_64
4320 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4322 # define CMPXCHG64(ptr, old, new) \
4323 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4326 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4331 struct x86_exception *exception)
4333 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4339 /* guests cmpxchg8b have to be emulated atomically */
4340 if (bytes > 8 || (bytes & (bytes - 1)))
4343 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4345 if (gpa == UNMAPPED_GVA ||
4346 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4349 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4352 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4353 if (is_error_page(page))
4356 kaddr = kmap_atomic(page);
4357 kaddr += offset_in_page(gpa);
4360 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4363 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4366 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4369 exchanged = CMPXCHG64(kaddr, old, new);
4374 kunmap_atomic(kaddr);
4375 kvm_release_page_dirty(page);
4378 return X86EMUL_CMPXCHG_FAILED;
4380 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4382 return X86EMUL_CONTINUE;
4385 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4387 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4390 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4392 /* TODO: String I/O for in kernel device */
4395 if (vcpu->arch.pio.in)
4396 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4397 vcpu->arch.pio.size, pd);
4399 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4400 vcpu->arch.pio.port, vcpu->arch.pio.size,
4405 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4406 unsigned short port, void *val,
4407 unsigned int count, bool in)
4409 trace_kvm_pio(!in, port, size, count);
4411 vcpu->arch.pio.port = port;
4412 vcpu->arch.pio.in = in;
4413 vcpu->arch.pio.count = count;
4414 vcpu->arch.pio.size = size;
4416 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4417 vcpu->arch.pio.count = 0;
4421 vcpu->run->exit_reason = KVM_EXIT_IO;
4422 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4423 vcpu->run->io.size = size;
4424 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4425 vcpu->run->io.count = count;
4426 vcpu->run->io.port = port;
4431 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4432 int size, unsigned short port, void *val,
4435 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4438 if (vcpu->arch.pio.count)
4441 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4444 memcpy(val, vcpu->arch.pio_data, size * count);
4445 vcpu->arch.pio.count = 0;
4452 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4453 int size, unsigned short port,
4454 const void *val, unsigned int count)
4456 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4458 memcpy(vcpu->arch.pio_data, val, size * count);
4459 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4462 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4464 return kvm_x86_ops->get_segment_base(vcpu, seg);
4467 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4469 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4472 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4474 if (!need_emulate_wbinvd(vcpu))
4475 return X86EMUL_CONTINUE;
4477 if (kvm_x86_ops->has_wbinvd_exit()) {
4478 int cpu = get_cpu();
4480 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4481 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4482 wbinvd_ipi, NULL, 1);
4484 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4487 return X86EMUL_CONTINUE;
4489 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4491 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4493 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4496 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4498 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4501 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4504 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4507 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4509 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4512 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4514 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4515 unsigned long value;
4519 value = kvm_read_cr0(vcpu);
4522 value = vcpu->arch.cr2;
4525 value = kvm_read_cr3(vcpu);
4528 value = kvm_read_cr4(vcpu);
4531 value = kvm_get_cr8(vcpu);
4534 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4541 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4543 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4548 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4551 vcpu->arch.cr2 = val;
4554 res = kvm_set_cr3(vcpu, val);
4557 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4560 res = kvm_set_cr8(vcpu, val);
4563 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4570 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4572 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4575 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4577 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4580 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4582 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4585 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4587 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4590 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4592 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4595 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4597 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4600 static unsigned long emulator_get_cached_segment_base(
4601 struct x86_emulate_ctxt *ctxt, int seg)
4603 return get_segment_base(emul_to_vcpu(ctxt), seg);
4606 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4607 struct desc_struct *desc, u32 *base3,
4610 struct kvm_segment var;
4612 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4613 *selector = var.selector;
4616 memset(desc, 0, sizeof(*desc));
4622 set_desc_limit(desc, var.limit);
4623 set_desc_base(desc, (unsigned long)var.base);
4624 #ifdef CONFIG_X86_64
4626 *base3 = var.base >> 32;
4628 desc->type = var.type;
4630 desc->dpl = var.dpl;
4631 desc->p = var.present;
4632 desc->avl = var.avl;
4640 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4641 struct desc_struct *desc, u32 base3,
4644 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4645 struct kvm_segment var;
4647 var.selector = selector;
4648 var.base = get_desc_base(desc);
4649 #ifdef CONFIG_X86_64
4650 var.base |= ((u64)base3) << 32;
4652 var.limit = get_desc_limit(desc);
4654 var.limit = (var.limit << 12) | 0xfff;
4655 var.type = desc->type;
4656 var.present = desc->p;
4657 var.dpl = desc->dpl;
4662 var.avl = desc->avl;
4663 var.present = desc->p;
4664 var.unusable = !var.present;
4667 kvm_set_segment(vcpu, &var, seg);
4671 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4672 u32 msr_index, u64 *pdata)
4674 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4677 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4678 u32 msr_index, u64 data)
4680 struct msr_data msr;
4683 msr.index = msr_index;
4684 msr.host_initiated = false;
4685 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4688 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4689 u32 pmc, u64 *pdata)
4691 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4694 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4696 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4699 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4702 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4704 * CR0.TS may reference the host fpu state, not the guest fpu state,
4705 * so it may be clear at this point.
4710 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4715 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4716 struct x86_instruction_info *info,
4717 enum x86_intercept_stage stage)
4719 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4722 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4723 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4725 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4728 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4730 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4733 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4735 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4738 static const struct x86_emulate_ops emulate_ops = {
4739 .read_gpr = emulator_read_gpr,
4740 .write_gpr = emulator_write_gpr,
4741 .read_std = kvm_read_guest_virt_system,
4742 .write_std = kvm_write_guest_virt_system,
4743 .fetch = kvm_fetch_guest_virt,
4744 .read_emulated = emulator_read_emulated,
4745 .write_emulated = emulator_write_emulated,
4746 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4747 .invlpg = emulator_invlpg,
4748 .pio_in_emulated = emulator_pio_in_emulated,
4749 .pio_out_emulated = emulator_pio_out_emulated,
4750 .get_segment = emulator_get_segment,
4751 .set_segment = emulator_set_segment,
4752 .get_cached_segment_base = emulator_get_cached_segment_base,
4753 .get_gdt = emulator_get_gdt,
4754 .get_idt = emulator_get_idt,
4755 .set_gdt = emulator_set_gdt,
4756 .set_idt = emulator_set_idt,
4757 .get_cr = emulator_get_cr,
4758 .set_cr = emulator_set_cr,
4759 .set_rflags = emulator_set_rflags,
4760 .cpl = emulator_get_cpl,
4761 .get_dr = emulator_get_dr,
4762 .set_dr = emulator_set_dr,
4763 .set_msr = emulator_set_msr,
4764 .get_msr = emulator_get_msr,
4765 .read_pmc = emulator_read_pmc,
4766 .halt = emulator_halt,
4767 .wbinvd = emulator_wbinvd,
4768 .fix_hypercall = emulator_fix_hypercall,
4769 .get_fpu = emulator_get_fpu,
4770 .put_fpu = emulator_put_fpu,
4771 .intercept = emulator_intercept,
4772 .get_cpuid = emulator_get_cpuid,
4775 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4777 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4779 * an sti; sti; sequence only disable interrupts for the first
4780 * instruction. So, if the last instruction, be it emulated or
4781 * not, left the system with the INT_STI flag enabled, it
4782 * means that the last instruction is an sti. We should not
4783 * leave the flag on in this case. The same goes for mov ss
4785 if (!(int_shadow & mask))
4786 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4789 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4791 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4792 if (ctxt->exception.vector == PF_VECTOR)
4793 kvm_propagate_fault(vcpu, &ctxt->exception);
4794 else if (ctxt->exception.error_code_valid)
4795 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4796 ctxt->exception.error_code);
4798 kvm_queue_exception(vcpu, ctxt->exception.vector);
4801 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4803 memset(&ctxt->opcode_len, 0,
4804 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
4806 ctxt->fetch.start = 0;
4807 ctxt->fetch.end = 0;
4808 ctxt->io_read.pos = 0;
4809 ctxt->io_read.end = 0;
4810 ctxt->mem_read.pos = 0;
4811 ctxt->mem_read.end = 0;
4814 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4816 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4819 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4821 ctxt->eflags = kvm_get_rflags(vcpu);
4822 ctxt->eip = kvm_rip_read(vcpu);
4823 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4824 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4825 cs_l ? X86EMUL_MODE_PROT64 :
4826 cs_db ? X86EMUL_MODE_PROT32 :
4827 X86EMUL_MODE_PROT16;
4828 ctxt->guest_mode = is_guest_mode(vcpu);
4830 init_decode_cache(ctxt);
4831 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4834 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4836 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4839 init_emulate_ctxt(vcpu);
4843 ctxt->_eip = ctxt->eip + inc_eip;
4844 ret = emulate_int_real(ctxt, irq);
4846 if (ret != X86EMUL_CONTINUE)
4847 return EMULATE_FAIL;
4849 ctxt->eip = ctxt->_eip;
4850 kvm_rip_write(vcpu, ctxt->eip);
4851 kvm_set_rflags(vcpu, ctxt->eflags);
4853 if (irq == NMI_VECTOR)
4854 vcpu->arch.nmi_pending = 0;
4856 vcpu->arch.interrupt.pending = false;
4858 return EMULATE_DONE;
4860 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4862 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4864 int r = EMULATE_DONE;
4866 ++vcpu->stat.insn_emulation_fail;
4867 trace_kvm_emulate_insn_failed(vcpu);
4868 if (!is_guest_mode(vcpu)) {
4869 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4870 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4871 vcpu->run->internal.ndata = 0;
4874 kvm_queue_exception(vcpu, UD_VECTOR);
4879 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4880 bool write_fault_to_shadow_pgtable,
4886 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4889 if (!vcpu->arch.mmu.direct_map) {
4891 * Write permission should be allowed since only
4892 * write access need to be emulated.
4894 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4897 * If the mapping is invalid in guest, let cpu retry
4898 * it to generate fault.
4900 if (gpa == UNMAPPED_GVA)
4905 * Do not retry the unhandleable instruction if it faults on the
4906 * readonly host memory, otherwise it will goto a infinite loop:
4907 * retry instruction -> write #PF -> emulation fail -> retry
4908 * instruction -> ...
4910 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4913 * If the instruction failed on the error pfn, it can not be fixed,
4914 * report the error to userspace.
4916 if (is_error_noslot_pfn(pfn))
4919 kvm_release_pfn_clean(pfn);
4921 /* The instructions are well-emulated on direct mmu. */
4922 if (vcpu->arch.mmu.direct_map) {
4923 unsigned int indirect_shadow_pages;
4925 spin_lock(&vcpu->kvm->mmu_lock);
4926 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4927 spin_unlock(&vcpu->kvm->mmu_lock);
4929 if (indirect_shadow_pages)
4930 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4936 * if emulation was due to access to shadowed page table
4937 * and it failed try to unshadow page and re-enter the
4938 * guest to let CPU execute the instruction.
4940 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4943 * If the access faults on its page table, it can not
4944 * be fixed by unprotecting shadow page and it should
4945 * be reported to userspace.
4947 return !write_fault_to_shadow_pgtable;
4950 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4951 unsigned long cr2, int emulation_type)
4953 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4954 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4956 last_retry_eip = vcpu->arch.last_retry_eip;
4957 last_retry_addr = vcpu->arch.last_retry_addr;
4960 * If the emulation is caused by #PF and it is non-page_table
4961 * writing instruction, it means the VM-EXIT is caused by shadow
4962 * page protected, we can zap the shadow page and retry this
4963 * instruction directly.
4965 * Note: if the guest uses a non-page-table modifying instruction
4966 * on the PDE that points to the instruction, then we will unmap
4967 * the instruction and go to an infinite loop. So, we cache the
4968 * last retried eip and the last fault address, if we meet the eip
4969 * and the address again, we can break out of the potential infinite
4972 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4974 if (!(emulation_type & EMULTYPE_RETRY))
4977 if (x86_page_table_writing_insn(ctxt))
4980 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4983 vcpu->arch.last_retry_eip = ctxt->eip;
4984 vcpu->arch.last_retry_addr = cr2;
4986 if (!vcpu->arch.mmu.direct_map)
4987 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4989 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4994 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4995 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4997 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5006 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5007 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5012 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5014 struct kvm_run *kvm_run = vcpu->run;
5017 * Use the "raw" value to see if TF was passed to the processor.
5018 * Note that the new value of the flags has not been saved yet.
5020 * This is correct even for TF set by the guest, because "the
5021 * processor will not generate this exception after the instruction
5022 * that sets the TF flag".
5024 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5026 if (unlikely(rflags & X86_EFLAGS_TF)) {
5027 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5028 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5029 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5030 kvm_run->debug.arch.exception = DB_VECTOR;
5031 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5032 *r = EMULATE_USER_EXIT;
5034 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5036 * "Certain debug exceptions may clear bit 0-3. The
5037 * remaining contents of the DR6 register are never
5038 * cleared by the processor".
5040 vcpu->arch.dr6 &= ~15;
5041 vcpu->arch.dr6 |= DR6_BS;
5042 kvm_queue_exception(vcpu, DB_VECTOR);
5047 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5049 struct kvm_run *kvm_run = vcpu->run;
5050 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5053 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5054 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5055 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5056 vcpu->arch.guest_debug_dr7,
5060 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5061 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5062 get_segment_base(vcpu, VCPU_SREG_CS);
5064 kvm_run->debug.arch.exception = DB_VECTOR;
5065 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5066 *r = EMULATE_USER_EXIT;
5071 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5072 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5077 vcpu->arch.dr6 &= ~15;
5078 vcpu->arch.dr6 |= dr6;
5079 kvm_queue_exception(vcpu, DB_VECTOR);
5088 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5095 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5096 bool writeback = true;
5097 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5100 * Clear write_fault_to_shadow_pgtable here to ensure it is
5103 vcpu->arch.write_fault_to_shadow_pgtable = false;
5104 kvm_clear_exception_queue(vcpu);
5106 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5107 init_emulate_ctxt(vcpu);
5110 * We will reenter on the same instruction since
5111 * we do not set complete_userspace_io. This does not
5112 * handle watchpoints yet, those would be handled in
5115 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5118 ctxt->interruptibility = 0;
5119 ctxt->have_exception = false;
5120 ctxt->perm_ok = false;
5122 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5124 r = x86_decode_insn(ctxt, insn, insn_len);
5126 trace_kvm_emulate_insn_start(vcpu);
5127 ++vcpu->stat.insn_emulation;
5128 if (r != EMULATION_OK) {
5129 if (emulation_type & EMULTYPE_TRAP_UD)
5130 return EMULATE_FAIL;
5131 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5133 return EMULATE_DONE;
5134 if (emulation_type & EMULTYPE_SKIP)
5135 return EMULATE_FAIL;
5136 return handle_emulation_failure(vcpu);
5140 if (emulation_type & EMULTYPE_SKIP) {
5141 kvm_rip_write(vcpu, ctxt->_eip);
5142 return EMULATE_DONE;
5145 if (retry_instruction(ctxt, cr2, emulation_type))
5146 return EMULATE_DONE;
5148 /* this is needed for vmware backdoor interface to work since it
5149 changes registers values during IO operation */
5150 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5151 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5152 emulator_invalidate_register_cache(ctxt);
5156 r = x86_emulate_insn(ctxt);
5158 if (r == EMULATION_INTERCEPTED)
5159 return EMULATE_DONE;
5161 if (r == EMULATION_FAILED) {
5162 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5164 return EMULATE_DONE;
5166 return handle_emulation_failure(vcpu);
5169 if (ctxt->have_exception) {
5170 inject_emulated_exception(vcpu);
5172 } else if (vcpu->arch.pio.count) {
5173 if (!vcpu->arch.pio.in) {
5174 /* FIXME: return into emulator if single-stepping. */
5175 vcpu->arch.pio.count = 0;
5178 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5180 r = EMULATE_USER_EXIT;
5181 } else if (vcpu->mmio_needed) {
5182 if (!vcpu->mmio_is_write)
5184 r = EMULATE_USER_EXIT;
5185 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5186 } else if (r == EMULATION_RESTART)
5192 toggle_interruptibility(vcpu, ctxt->interruptibility);
5193 kvm_make_request(KVM_REQ_EVENT, vcpu);
5194 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5195 kvm_rip_write(vcpu, ctxt->eip);
5196 if (r == EMULATE_DONE)
5197 kvm_vcpu_check_singlestep(vcpu, &r);
5198 kvm_set_rflags(vcpu, ctxt->eflags);
5200 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5204 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5206 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5208 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5209 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5210 size, port, &val, 1);
5211 /* do not return to emulator after return from userspace */
5212 vcpu->arch.pio.count = 0;
5215 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5217 static void tsc_bad(void *info)
5219 __this_cpu_write(cpu_tsc_khz, 0);
5222 static void tsc_khz_changed(void *data)
5224 struct cpufreq_freqs *freq = data;
5225 unsigned long khz = 0;
5229 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5230 khz = cpufreq_quick_get(raw_smp_processor_id());
5233 __this_cpu_write(cpu_tsc_khz, khz);
5236 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5239 struct cpufreq_freqs *freq = data;
5241 struct kvm_vcpu *vcpu;
5242 int i, send_ipi = 0;
5245 * We allow guests to temporarily run on slowing clocks,
5246 * provided we notify them after, or to run on accelerating
5247 * clocks, provided we notify them before. Thus time never
5250 * However, we have a problem. We can't atomically update
5251 * the frequency of a given CPU from this function; it is
5252 * merely a notifier, which can be called from any CPU.
5253 * Changing the TSC frequency at arbitrary points in time
5254 * requires a recomputation of local variables related to
5255 * the TSC for each VCPU. We must flag these local variables
5256 * to be updated and be sure the update takes place with the
5257 * new frequency before any guests proceed.
5259 * Unfortunately, the combination of hotplug CPU and frequency
5260 * change creates an intractable locking scenario; the order
5261 * of when these callouts happen is undefined with respect to
5262 * CPU hotplug, and they can race with each other. As such,
5263 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5264 * undefined; you can actually have a CPU frequency change take
5265 * place in between the computation of X and the setting of the
5266 * variable. To protect against this problem, all updates of
5267 * the per_cpu tsc_khz variable are done in an interrupt
5268 * protected IPI, and all callers wishing to update the value
5269 * must wait for a synchronous IPI to complete (which is trivial
5270 * if the caller is on the CPU already). This establishes the
5271 * necessary total order on variable updates.
5273 * Note that because a guest time update may take place
5274 * anytime after the setting of the VCPU's request bit, the
5275 * correct TSC value must be set before the request. However,
5276 * to ensure the update actually makes it to any guest which
5277 * starts running in hardware virtualization between the set
5278 * and the acquisition of the spinlock, we must also ping the
5279 * CPU after setting the request bit.
5283 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5285 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5288 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5290 spin_lock(&kvm_lock);
5291 list_for_each_entry(kvm, &vm_list, vm_list) {
5292 kvm_for_each_vcpu(i, vcpu, kvm) {
5293 if (vcpu->cpu != freq->cpu)
5295 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5296 if (vcpu->cpu != smp_processor_id())
5300 spin_unlock(&kvm_lock);
5302 if (freq->old < freq->new && send_ipi) {
5304 * We upscale the frequency. Must make the guest
5305 * doesn't see old kvmclock values while running with
5306 * the new frequency, otherwise we risk the guest sees
5307 * time go backwards.
5309 * In case we update the frequency for another cpu
5310 * (which might be in guest context) send an interrupt
5311 * to kick the cpu out of guest context. Next time
5312 * guest context is entered kvmclock will be updated,
5313 * so the guest will not see stale values.
5315 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5320 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5321 .notifier_call = kvmclock_cpufreq_notifier
5324 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5325 unsigned long action, void *hcpu)
5327 unsigned int cpu = (unsigned long)hcpu;
5331 case CPU_DOWN_FAILED:
5332 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5334 case CPU_DOWN_PREPARE:
5335 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5341 static struct notifier_block kvmclock_cpu_notifier_block = {
5342 .notifier_call = kvmclock_cpu_notifier,
5343 .priority = -INT_MAX
5346 static void kvm_timer_init(void)
5350 max_tsc_khz = tsc_khz;
5351 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5352 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5353 #ifdef CONFIG_CPU_FREQ
5354 struct cpufreq_policy policy;
5355 memset(&policy, 0, sizeof(policy));
5357 cpufreq_get_policy(&policy, cpu);
5358 if (policy.cpuinfo.max_freq)
5359 max_tsc_khz = policy.cpuinfo.max_freq;
5362 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5363 CPUFREQ_TRANSITION_NOTIFIER);
5365 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5366 for_each_online_cpu(cpu)
5367 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5370 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5372 int kvm_is_in_guest(void)
5374 return __this_cpu_read(current_vcpu) != NULL;
5377 static int kvm_is_user_mode(void)
5381 if (__this_cpu_read(current_vcpu))
5382 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5384 return user_mode != 0;
5387 static unsigned long kvm_get_guest_ip(void)
5389 unsigned long ip = 0;
5391 if (__this_cpu_read(current_vcpu))
5392 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5397 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5398 .is_in_guest = kvm_is_in_guest,
5399 .is_user_mode = kvm_is_user_mode,
5400 .get_guest_ip = kvm_get_guest_ip,
5403 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5405 __this_cpu_write(current_vcpu, vcpu);
5407 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5409 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5411 __this_cpu_write(current_vcpu, NULL);
5413 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5415 static void kvm_set_mmio_spte_mask(void)
5418 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5421 * Set the reserved bits and the present bit of an paging-structure
5422 * entry to generate page fault with PFER.RSV = 1.
5424 /* Mask the reserved physical address bits. */
5425 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5427 /* Bit 62 is always reserved for 32bit host. */
5428 mask |= 0x3ull << 62;
5430 /* Set the present bit. */
5433 #ifdef CONFIG_X86_64
5435 * If reserved bit is not supported, clear the present bit to disable
5438 if (maxphyaddr == 52)
5442 kvm_mmu_set_mmio_spte_mask(mask);
5445 #ifdef CONFIG_X86_64
5446 static void pvclock_gtod_update_fn(struct work_struct *work)
5450 struct kvm_vcpu *vcpu;
5453 spin_lock(&kvm_lock);
5454 list_for_each_entry(kvm, &vm_list, vm_list)
5455 kvm_for_each_vcpu(i, vcpu, kvm)
5456 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5457 atomic_set(&kvm_guest_has_master_clock, 0);
5458 spin_unlock(&kvm_lock);
5461 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5464 * Notification about pvclock gtod data update.
5466 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5469 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5470 struct timekeeper *tk = priv;
5472 update_pvclock_gtod(tk);
5474 /* disable master clock if host does not trust, or does not
5475 * use, TSC clocksource
5477 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5478 atomic_read(&kvm_guest_has_master_clock) != 0)
5479 queue_work(system_long_wq, &pvclock_gtod_work);
5484 static struct notifier_block pvclock_gtod_notifier = {
5485 .notifier_call = pvclock_gtod_notify,
5489 int kvm_arch_init(void *opaque)
5492 struct kvm_x86_ops *ops = opaque;
5495 printk(KERN_ERR "kvm: already loaded the other module\n");
5500 if (!ops->cpu_has_kvm_support()) {
5501 printk(KERN_ERR "kvm: no hardware support\n");
5505 if (ops->disabled_by_bios()) {
5506 printk(KERN_ERR "kvm: disabled by bios\n");
5512 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5514 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5518 r = kvm_mmu_module_init();
5520 goto out_free_percpu;
5522 kvm_set_mmio_spte_mask();
5523 kvm_init_msr_list();
5526 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5527 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5531 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5534 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5537 #ifdef CONFIG_X86_64
5538 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5544 free_percpu(shared_msrs);
5549 void kvm_arch_exit(void)
5551 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5553 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5554 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5555 CPUFREQ_TRANSITION_NOTIFIER);
5556 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5557 #ifdef CONFIG_X86_64
5558 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5561 kvm_mmu_module_exit();
5562 free_percpu(shared_msrs);
5565 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5567 ++vcpu->stat.halt_exits;
5568 if (irqchip_in_kernel(vcpu->kvm)) {
5569 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5572 vcpu->run->exit_reason = KVM_EXIT_HLT;
5576 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5578 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5580 u64 param, ingpa, outgpa, ret;
5581 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5582 bool fast, longmode;
5586 * hypercall generates UD from non zero cpl and real mode
5589 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5590 kvm_queue_exception(vcpu, UD_VECTOR);
5594 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5595 longmode = is_long_mode(vcpu) && cs_l == 1;
5598 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5599 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5600 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5601 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5602 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5603 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5605 #ifdef CONFIG_X86_64
5607 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5608 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5609 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5613 code = param & 0xffff;
5614 fast = (param >> 16) & 0x1;
5615 rep_cnt = (param >> 32) & 0xfff;
5616 rep_idx = (param >> 48) & 0xfff;
5618 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5621 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5622 kvm_vcpu_on_spin(vcpu);
5625 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5629 ret = res | (((u64)rep_done & 0xfff) << 32);
5631 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5633 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5634 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5641 * kvm_pv_kick_cpu_op: Kick a vcpu.
5643 * @apicid - apicid of vcpu to be kicked.
5645 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5647 struct kvm_lapic_irq lapic_irq;
5649 lapic_irq.shorthand = 0;
5650 lapic_irq.dest_mode = 0;
5651 lapic_irq.dest_id = apicid;
5653 lapic_irq.delivery_mode = APIC_DM_REMRD;
5654 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5657 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5659 unsigned long nr, a0, a1, a2, a3, ret;
5662 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5663 return kvm_hv_hypercall(vcpu);
5665 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5666 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5667 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5668 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5669 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5671 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5673 if (!is_long_mode(vcpu)) {
5681 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5687 case KVM_HC_VAPIC_POLL_IRQ:
5690 case KVM_HC_KICK_CPU:
5691 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5699 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5700 ++vcpu->stat.hypercalls;
5703 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5705 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5707 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5708 char instruction[3];
5709 unsigned long rip = kvm_rip_read(vcpu);
5711 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5713 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5717 * Check if userspace requested an interrupt window, and that the
5718 * interrupt window is open.
5720 * No need to exit to userspace if we already have an interrupt queued.
5722 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5724 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5725 vcpu->run->request_interrupt_window &&
5726 kvm_arch_interrupt_allowed(vcpu));
5729 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5731 struct kvm_run *kvm_run = vcpu->run;
5733 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5734 kvm_run->cr8 = kvm_get_cr8(vcpu);
5735 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5736 if (irqchip_in_kernel(vcpu->kvm))
5737 kvm_run->ready_for_interrupt_injection = 1;
5739 kvm_run->ready_for_interrupt_injection =
5740 kvm_arch_interrupt_allowed(vcpu) &&
5741 !kvm_cpu_has_interrupt(vcpu) &&
5742 !kvm_event_needs_reinjection(vcpu);
5745 static int vapic_enter(struct kvm_vcpu *vcpu)
5747 struct kvm_lapic *apic = vcpu->arch.apic;
5750 if (!apic || !apic->vapic_addr)
5753 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5754 if (is_error_page(page))
5757 vcpu->arch.apic->vapic_page = page;
5761 static void vapic_exit(struct kvm_vcpu *vcpu)
5763 struct kvm_lapic *apic = vcpu->arch.apic;
5766 if (!apic || !apic->vapic_addr)
5769 idx = srcu_read_lock(&vcpu->kvm->srcu);
5770 kvm_release_page_dirty(apic->vapic_page);
5771 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5772 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5775 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5779 if (!kvm_x86_ops->update_cr8_intercept)
5782 if (!vcpu->arch.apic)
5785 if (!vcpu->arch.apic->vapic_addr)
5786 max_irr = kvm_lapic_find_highest_irr(vcpu);
5793 tpr = kvm_lapic_get_cr8(vcpu);
5795 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5798 static void inject_pending_event(struct kvm_vcpu *vcpu)
5800 /* try to reinject previous events if any */
5801 if (vcpu->arch.exception.pending) {
5802 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5803 vcpu->arch.exception.has_error_code,
5804 vcpu->arch.exception.error_code);
5805 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5806 vcpu->arch.exception.has_error_code,
5807 vcpu->arch.exception.error_code,
5808 vcpu->arch.exception.reinject);
5812 if (vcpu->arch.nmi_injected) {
5813 kvm_x86_ops->set_nmi(vcpu);
5817 if (vcpu->arch.interrupt.pending) {
5818 kvm_x86_ops->set_irq(vcpu);
5822 /* try to inject new event if pending */
5823 if (vcpu->arch.nmi_pending) {
5824 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5825 --vcpu->arch.nmi_pending;
5826 vcpu->arch.nmi_injected = true;
5827 kvm_x86_ops->set_nmi(vcpu);
5829 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5830 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5831 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5833 kvm_x86_ops->set_irq(vcpu);
5838 static void process_nmi(struct kvm_vcpu *vcpu)
5843 * x86 is limited to one NMI running, and one NMI pending after it.
5844 * If an NMI is already in progress, limit further NMIs to just one.
5845 * Otherwise, allow two (and we'll inject the first one immediately).
5847 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5850 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5851 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5852 kvm_make_request(KVM_REQ_EVENT, vcpu);
5855 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5857 u64 eoi_exit_bitmap[4];
5860 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5863 memset(eoi_exit_bitmap, 0, 32);
5866 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5867 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5868 kvm_apic_update_tmr(vcpu, tmr);
5872 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5873 * exiting to the userspace. Otherwise, the value will be returned to the
5876 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5879 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5880 vcpu->run->request_interrupt_window;
5881 bool req_immediate_exit = false;
5883 if (vcpu->requests) {
5884 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5885 kvm_mmu_unload(vcpu);
5886 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5887 __kvm_migrate_timers(vcpu);
5888 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5889 kvm_gen_update_masterclock(vcpu->kvm);
5890 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5891 kvm_gen_kvmclock_update(vcpu);
5892 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5893 r = kvm_guest_time_update(vcpu);
5897 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5898 kvm_mmu_sync_roots(vcpu);
5899 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5900 kvm_x86_ops->tlb_flush(vcpu);
5901 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5902 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5906 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5907 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5911 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5912 vcpu->fpu_active = 0;
5913 kvm_x86_ops->fpu_deactivate(vcpu);
5915 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5916 /* Page is swapped out. Do synthetic halt */
5917 vcpu->arch.apf.halted = true;
5921 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5922 record_steal_time(vcpu);
5923 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5925 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5926 kvm_handle_pmu_event(vcpu);
5927 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5928 kvm_deliver_pmi(vcpu);
5929 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5930 vcpu_scan_ioapic(vcpu);
5933 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5934 kvm_apic_accept_events(vcpu);
5935 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5940 inject_pending_event(vcpu);
5942 /* enable NMI/IRQ window open exits if needed */
5943 if (vcpu->arch.nmi_pending)
5944 req_immediate_exit =
5945 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
5946 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5947 req_immediate_exit =
5948 kvm_x86_ops->enable_irq_window(vcpu) != 0;
5950 if (kvm_lapic_enabled(vcpu)) {
5952 * Update architecture specific hints for APIC
5953 * virtual interrupt delivery.
5955 if (kvm_x86_ops->hwapic_irr_update)
5956 kvm_x86_ops->hwapic_irr_update(vcpu,
5957 kvm_lapic_find_highest_irr(vcpu));
5958 update_cr8_intercept(vcpu);
5959 kvm_lapic_sync_to_vapic(vcpu);
5963 r = kvm_mmu_reload(vcpu);
5965 goto cancel_injection;
5970 kvm_x86_ops->prepare_guest_switch(vcpu);
5971 if (vcpu->fpu_active)
5972 kvm_load_guest_fpu(vcpu);
5973 kvm_load_guest_xcr0(vcpu);
5975 vcpu->mode = IN_GUEST_MODE;
5977 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5979 /* We should set ->mode before check ->requests,
5980 * see the comment in make_all_cpus_request.
5982 smp_mb__after_srcu_read_unlock();
5984 local_irq_disable();
5986 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5987 || need_resched() || signal_pending(current)) {
5988 vcpu->mode = OUTSIDE_GUEST_MODE;
5992 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5994 goto cancel_injection;
5997 if (req_immediate_exit)
5998 smp_send_reschedule(vcpu->cpu);
6002 if (unlikely(vcpu->arch.switch_db_regs)) {
6004 set_debugreg(vcpu->arch.eff_db[0], 0);
6005 set_debugreg(vcpu->arch.eff_db[1], 1);
6006 set_debugreg(vcpu->arch.eff_db[2], 2);
6007 set_debugreg(vcpu->arch.eff_db[3], 3);
6010 trace_kvm_entry(vcpu->vcpu_id);
6011 kvm_x86_ops->run(vcpu);
6014 * If the guest has used debug registers, at least dr7
6015 * will be disabled while returning to the host.
6016 * If we don't have active breakpoints in the host, we don't
6017 * care about the messed up debug address registers. But if
6018 * we have some of them active, restore the old state.
6020 if (hw_breakpoint_active())
6021 hw_breakpoint_restore();
6023 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6026 vcpu->mode = OUTSIDE_GUEST_MODE;
6029 /* Interrupt is enabled by handle_external_intr() */
6030 kvm_x86_ops->handle_external_intr(vcpu);
6035 * We must have an instruction between local_irq_enable() and
6036 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6037 * the interrupt shadow. The stat.exits increment will do nicely.
6038 * But we need to prevent reordering, hence this barrier():
6046 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6049 * Profile KVM exit RIPs:
6051 if (unlikely(prof_on == KVM_PROFILING)) {
6052 unsigned long rip = kvm_rip_read(vcpu);
6053 profile_hit(KVM_PROFILING, (void *)rip);
6056 if (unlikely(vcpu->arch.tsc_always_catchup))
6057 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6059 if (vcpu->arch.apic_attention)
6060 kvm_lapic_sync_from_vapic(vcpu);
6062 r = kvm_x86_ops->handle_exit(vcpu);
6066 kvm_x86_ops->cancel_injection(vcpu);
6067 if (unlikely(vcpu->arch.apic_attention))
6068 kvm_lapic_sync_from_vapic(vcpu);
6074 static int __vcpu_run(struct kvm_vcpu *vcpu)
6077 struct kvm *kvm = vcpu->kvm;
6079 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6080 r = vapic_enter(vcpu);
6082 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6088 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6089 !vcpu->arch.apf.halted)
6090 r = vcpu_enter_guest(vcpu);
6092 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6093 kvm_vcpu_block(vcpu);
6094 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6095 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6096 kvm_apic_accept_events(vcpu);
6097 switch(vcpu->arch.mp_state) {
6098 case KVM_MP_STATE_HALTED:
6099 vcpu->arch.pv.pv_unhalted = false;
6100 vcpu->arch.mp_state =
6101 KVM_MP_STATE_RUNNABLE;
6102 case KVM_MP_STATE_RUNNABLE:
6103 vcpu->arch.apf.halted = false;
6105 case KVM_MP_STATE_INIT_RECEIVED:
6117 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6118 if (kvm_cpu_has_pending_timer(vcpu))
6119 kvm_inject_pending_timer_irqs(vcpu);
6121 if (dm_request_for_irq_injection(vcpu)) {
6123 vcpu->run->exit_reason = KVM_EXIT_INTR;
6124 ++vcpu->stat.request_irq_exits;
6127 kvm_check_async_pf_completion(vcpu);
6129 if (signal_pending(current)) {
6131 vcpu->run->exit_reason = KVM_EXIT_INTR;
6132 ++vcpu->stat.signal_exits;
6134 if (need_resched()) {
6135 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6137 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6141 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6148 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6151 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6152 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6153 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6154 if (r != EMULATE_DONE)
6159 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6161 BUG_ON(!vcpu->arch.pio.count);
6163 return complete_emulated_io(vcpu);
6167 * Implements the following, as a state machine:
6171 * for each mmio piece in the fragment
6179 * for each mmio piece in the fragment
6184 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6186 struct kvm_run *run = vcpu->run;
6187 struct kvm_mmio_fragment *frag;
6190 BUG_ON(!vcpu->mmio_needed);
6192 /* Complete previous fragment */
6193 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6194 len = min(8u, frag->len);
6195 if (!vcpu->mmio_is_write)
6196 memcpy(frag->data, run->mmio.data, len);
6198 if (frag->len <= 8) {
6199 /* Switch to the next fragment. */
6201 vcpu->mmio_cur_fragment++;
6203 /* Go forward to the next mmio piece. */
6209 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6210 vcpu->mmio_needed = 0;
6212 /* FIXME: return into emulator if single-stepping. */
6213 if (vcpu->mmio_is_write)
6215 vcpu->mmio_read_completed = 1;
6216 return complete_emulated_io(vcpu);
6219 run->exit_reason = KVM_EXIT_MMIO;
6220 run->mmio.phys_addr = frag->gpa;
6221 if (vcpu->mmio_is_write)
6222 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6223 run->mmio.len = min(8u, frag->len);
6224 run->mmio.is_write = vcpu->mmio_is_write;
6225 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6230 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6235 if (!tsk_used_math(current) && init_fpu(current))
6238 if (vcpu->sigset_active)
6239 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6241 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6242 kvm_vcpu_block(vcpu);
6243 kvm_apic_accept_events(vcpu);
6244 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6249 /* re-sync apic's tpr */
6250 if (!irqchip_in_kernel(vcpu->kvm)) {
6251 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6257 if (unlikely(vcpu->arch.complete_userspace_io)) {
6258 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6259 vcpu->arch.complete_userspace_io = NULL;
6264 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6266 r = __vcpu_run(vcpu);
6269 post_kvm_run_save(vcpu);
6270 if (vcpu->sigset_active)
6271 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6276 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6278 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6280 * We are here if userspace calls get_regs() in the middle of
6281 * instruction emulation. Registers state needs to be copied
6282 * back from emulation context to vcpu. Userspace shouldn't do
6283 * that usually, but some bad designed PV devices (vmware
6284 * backdoor interface) need this to work
6286 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6287 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6289 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6290 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6291 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6292 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6293 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6294 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6295 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6296 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6297 #ifdef CONFIG_X86_64
6298 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6299 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6300 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6301 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6302 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6303 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6304 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6305 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6308 regs->rip = kvm_rip_read(vcpu);
6309 regs->rflags = kvm_get_rflags(vcpu);
6314 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6316 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6317 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6319 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6320 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6321 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6322 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6323 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6324 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6325 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6326 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6327 #ifdef CONFIG_X86_64
6328 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6329 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6330 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6331 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6332 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6333 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6334 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6335 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6338 kvm_rip_write(vcpu, regs->rip);
6339 kvm_set_rflags(vcpu, regs->rflags);
6341 vcpu->arch.exception.pending = false;
6343 kvm_make_request(KVM_REQ_EVENT, vcpu);
6348 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6350 struct kvm_segment cs;
6352 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6356 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6358 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6359 struct kvm_sregs *sregs)
6363 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6364 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6365 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6366 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6367 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6368 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6370 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6371 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6373 kvm_x86_ops->get_idt(vcpu, &dt);
6374 sregs->idt.limit = dt.size;
6375 sregs->idt.base = dt.address;
6376 kvm_x86_ops->get_gdt(vcpu, &dt);
6377 sregs->gdt.limit = dt.size;
6378 sregs->gdt.base = dt.address;
6380 sregs->cr0 = kvm_read_cr0(vcpu);
6381 sregs->cr2 = vcpu->arch.cr2;
6382 sregs->cr3 = kvm_read_cr3(vcpu);
6383 sregs->cr4 = kvm_read_cr4(vcpu);
6384 sregs->cr8 = kvm_get_cr8(vcpu);
6385 sregs->efer = vcpu->arch.efer;
6386 sregs->apic_base = kvm_get_apic_base(vcpu);
6388 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6390 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6391 set_bit(vcpu->arch.interrupt.nr,
6392 (unsigned long *)sregs->interrupt_bitmap);
6397 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6398 struct kvm_mp_state *mp_state)
6400 kvm_apic_accept_events(vcpu);
6401 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6402 vcpu->arch.pv.pv_unhalted)
6403 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6405 mp_state->mp_state = vcpu->arch.mp_state;
6410 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6411 struct kvm_mp_state *mp_state)
6413 if (!kvm_vcpu_has_lapic(vcpu) &&
6414 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6417 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6418 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6419 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6421 vcpu->arch.mp_state = mp_state->mp_state;
6422 kvm_make_request(KVM_REQ_EVENT, vcpu);
6426 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6427 int reason, bool has_error_code, u32 error_code)
6429 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6432 init_emulate_ctxt(vcpu);
6434 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6435 has_error_code, error_code);
6438 return EMULATE_FAIL;
6440 kvm_rip_write(vcpu, ctxt->eip);
6441 kvm_set_rflags(vcpu, ctxt->eflags);
6442 kvm_make_request(KVM_REQ_EVENT, vcpu);
6443 return EMULATE_DONE;
6445 EXPORT_SYMBOL_GPL(kvm_task_switch);
6447 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6448 struct kvm_sregs *sregs)
6450 int mmu_reset_needed = 0;
6451 int pending_vec, max_bits, idx;
6454 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6457 dt.size = sregs->idt.limit;
6458 dt.address = sregs->idt.base;
6459 kvm_x86_ops->set_idt(vcpu, &dt);
6460 dt.size = sregs->gdt.limit;
6461 dt.address = sregs->gdt.base;
6462 kvm_x86_ops->set_gdt(vcpu, &dt);
6464 vcpu->arch.cr2 = sregs->cr2;
6465 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6466 vcpu->arch.cr3 = sregs->cr3;
6467 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6469 kvm_set_cr8(vcpu, sregs->cr8);
6471 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6472 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6473 kvm_set_apic_base(vcpu, sregs->apic_base);
6475 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6476 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6477 vcpu->arch.cr0 = sregs->cr0;
6479 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6480 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6481 if (sregs->cr4 & X86_CR4_OSXSAVE)
6482 kvm_update_cpuid(vcpu);
6484 idx = srcu_read_lock(&vcpu->kvm->srcu);
6485 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6486 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6487 mmu_reset_needed = 1;
6489 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6491 if (mmu_reset_needed)
6492 kvm_mmu_reset_context(vcpu);
6494 max_bits = KVM_NR_INTERRUPTS;
6495 pending_vec = find_first_bit(
6496 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6497 if (pending_vec < max_bits) {
6498 kvm_queue_interrupt(vcpu, pending_vec, false);
6499 pr_debug("Set back pending irq %d\n", pending_vec);
6502 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6503 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6504 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6505 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6506 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6507 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6509 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6510 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6512 update_cr8_intercept(vcpu);
6514 /* Older userspace won't unhalt the vcpu on reset. */
6515 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6516 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6518 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6520 kvm_make_request(KVM_REQ_EVENT, vcpu);
6525 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6526 struct kvm_guest_debug *dbg)
6528 unsigned long rflags;
6531 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6533 if (vcpu->arch.exception.pending)
6535 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6536 kvm_queue_exception(vcpu, DB_VECTOR);
6538 kvm_queue_exception(vcpu, BP_VECTOR);
6542 * Read rflags as long as potentially injected trace flags are still
6545 rflags = kvm_get_rflags(vcpu);
6547 vcpu->guest_debug = dbg->control;
6548 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6549 vcpu->guest_debug = 0;
6551 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6552 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6553 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6554 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6556 for (i = 0; i < KVM_NR_DB_REGS; i++)
6557 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6559 kvm_update_dr7(vcpu);
6561 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6562 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6563 get_segment_base(vcpu, VCPU_SREG_CS);
6566 * Trigger an rflags update that will inject or remove the trace
6569 kvm_set_rflags(vcpu, rflags);
6571 kvm_x86_ops->update_db_bp_intercept(vcpu);
6581 * Translate a guest virtual address to a guest physical address.
6583 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6584 struct kvm_translation *tr)
6586 unsigned long vaddr = tr->linear_address;
6590 idx = srcu_read_lock(&vcpu->kvm->srcu);
6591 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6592 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6593 tr->physical_address = gpa;
6594 tr->valid = gpa != UNMAPPED_GVA;
6601 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6603 struct i387_fxsave_struct *fxsave =
6604 &vcpu->arch.guest_fpu.state->fxsave;
6606 memcpy(fpu->fpr, fxsave->st_space, 128);
6607 fpu->fcw = fxsave->cwd;
6608 fpu->fsw = fxsave->swd;
6609 fpu->ftwx = fxsave->twd;
6610 fpu->last_opcode = fxsave->fop;
6611 fpu->last_ip = fxsave->rip;
6612 fpu->last_dp = fxsave->rdp;
6613 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6618 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6620 struct i387_fxsave_struct *fxsave =
6621 &vcpu->arch.guest_fpu.state->fxsave;
6623 memcpy(fxsave->st_space, fpu->fpr, 128);
6624 fxsave->cwd = fpu->fcw;
6625 fxsave->swd = fpu->fsw;
6626 fxsave->twd = fpu->ftwx;
6627 fxsave->fop = fpu->last_opcode;
6628 fxsave->rip = fpu->last_ip;
6629 fxsave->rdp = fpu->last_dp;
6630 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6635 int fx_init(struct kvm_vcpu *vcpu)
6639 err = fpu_alloc(&vcpu->arch.guest_fpu);
6643 fpu_finit(&vcpu->arch.guest_fpu);
6646 * Ensure guest xcr0 is valid for loading
6648 vcpu->arch.xcr0 = XSTATE_FP;
6650 vcpu->arch.cr0 |= X86_CR0_ET;
6654 EXPORT_SYMBOL_GPL(fx_init);
6656 static void fx_free(struct kvm_vcpu *vcpu)
6658 fpu_free(&vcpu->arch.guest_fpu);
6661 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6663 if (vcpu->guest_fpu_loaded)
6667 * Restore all possible states in the guest,
6668 * and assume host would use all available bits.
6669 * Guest xcr0 would be loaded later.
6671 kvm_put_guest_xcr0(vcpu);
6672 vcpu->guest_fpu_loaded = 1;
6673 __kernel_fpu_begin();
6674 fpu_restore_checking(&vcpu->arch.guest_fpu);
6678 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6680 kvm_put_guest_xcr0(vcpu);
6682 if (!vcpu->guest_fpu_loaded)
6685 vcpu->guest_fpu_loaded = 0;
6686 fpu_save_init(&vcpu->arch.guest_fpu);
6688 ++vcpu->stat.fpu_reload;
6689 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6693 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6695 kvmclock_reset(vcpu);
6697 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6699 kvm_x86_ops->vcpu_free(vcpu);
6702 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6705 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6706 printk_once(KERN_WARNING
6707 "kvm: SMP vm created on host with unstable TSC; "
6708 "guest TSC will not be reliable\n");
6709 return kvm_x86_ops->vcpu_create(kvm, id);
6712 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6716 vcpu->arch.mtrr_state.have_fixed = 1;
6717 r = vcpu_load(vcpu);
6720 kvm_vcpu_reset(vcpu);
6721 kvm_mmu_setup(vcpu);
6727 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6730 struct msr_data msr;
6732 r = vcpu_load(vcpu);
6736 msr.index = MSR_IA32_TSC;
6737 msr.host_initiated = true;
6738 kvm_write_tsc(vcpu, &msr);
6744 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6747 vcpu->arch.apf.msr_val = 0;
6749 r = vcpu_load(vcpu);
6751 kvm_mmu_unload(vcpu);
6755 kvm_x86_ops->vcpu_free(vcpu);
6758 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6760 atomic_set(&vcpu->arch.nmi_queued, 0);
6761 vcpu->arch.nmi_pending = 0;
6762 vcpu->arch.nmi_injected = false;
6764 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6765 vcpu->arch.dr6 = DR6_FIXED_1;
6766 vcpu->arch.dr7 = DR7_FIXED_1;
6767 kvm_update_dr7(vcpu);
6769 kvm_make_request(KVM_REQ_EVENT, vcpu);
6770 vcpu->arch.apf.msr_val = 0;
6771 vcpu->arch.st.msr_val = 0;
6773 kvmclock_reset(vcpu);
6775 kvm_clear_async_pf_completion_queue(vcpu);
6776 kvm_async_pf_hash_reset(vcpu);
6777 vcpu->arch.apf.halted = false;
6779 kvm_pmu_reset(vcpu);
6781 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6782 vcpu->arch.regs_avail = ~0;
6783 vcpu->arch.regs_dirty = ~0;
6785 kvm_x86_ops->vcpu_reset(vcpu);
6788 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6790 struct kvm_segment cs;
6792 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6793 cs.selector = vector << 8;
6794 cs.base = vector << 12;
6795 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6796 kvm_rip_write(vcpu, 0);
6799 int kvm_arch_hardware_enable(void *garbage)
6802 struct kvm_vcpu *vcpu;
6807 bool stable, backwards_tsc = false;
6809 kvm_shared_msr_cpu_online();
6810 ret = kvm_x86_ops->hardware_enable(garbage);
6814 local_tsc = native_read_tsc();
6815 stable = !check_tsc_unstable();
6816 list_for_each_entry(kvm, &vm_list, vm_list) {
6817 kvm_for_each_vcpu(i, vcpu, kvm) {
6818 if (!stable && vcpu->cpu == smp_processor_id())
6819 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6820 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6821 backwards_tsc = true;
6822 if (vcpu->arch.last_host_tsc > max_tsc)
6823 max_tsc = vcpu->arch.last_host_tsc;
6829 * Sometimes, even reliable TSCs go backwards. This happens on
6830 * platforms that reset TSC during suspend or hibernate actions, but
6831 * maintain synchronization. We must compensate. Fortunately, we can
6832 * detect that condition here, which happens early in CPU bringup,
6833 * before any KVM threads can be running. Unfortunately, we can't
6834 * bring the TSCs fully up to date with real time, as we aren't yet far
6835 * enough into CPU bringup that we know how much real time has actually
6836 * elapsed; our helper function, get_kernel_ns() will be using boot
6837 * variables that haven't been updated yet.
6839 * So we simply find the maximum observed TSC above, then record the
6840 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6841 * the adjustment will be applied. Note that we accumulate
6842 * adjustments, in case multiple suspend cycles happen before some VCPU
6843 * gets a chance to run again. In the event that no KVM threads get a
6844 * chance to run, we will miss the entire elapsed period, as we'll have
6845 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6846 * loose cycle time. This isn't too big a deal, since the loss will be
6847 * uniform across all VCPUs (not to mention the scenario is extremely
6848 * unlikely). It is possible that a second hibernate recovery happens
6849 * much faster than a first, causing the observed TSC here to be
6850 * smaller; this would require additional padding adjustment, which is
6851 * why we set last_host_tsc to the local tsc observed here.
6853 * N.B. - this code below runs only on platforms with reliable TSC,
6854 * as that is the only way backwards_tsc is set above. Also note
6855 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6856 * have the same delta_cyc adjustment applied if backwards_tsc
6857 * is detected. Note further, this adjustment is only done once,
6858 * as we reset last_host_tsc on all VCPUs to stop this from being
6859 * called multiple times (one for each physical CPU bringup).
6861 * Platforms with unreliable TSCs don't have to deal with this, they
6862 * will be compensated by the logic in vcpu_load, which sets the TSC to
6863 * catchup mode. This will catchup all VCPUs to real time, but cannot
6864 * guarantee that they stay in perfect synchronization.
6866 if (backwards_tsc) {
6867 u64 delta_cyc = max_tsc - local_tsc;
6868 list_for_each_entry(kvm, &vm_list, vm_list) {
6869 kvm_for_each_vcpu(i, vcpu, kvm) {
6870 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6871 vcpu->arch.last_host_tsc = local_tsc;
6872 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6877 * We have to disable TSC offset matching.. if you were
6878 * booting a VM while issuing an S4 host suspend....
6879 * you may have some problem. Solving this issue is
6880 * left as an exercise to the reader.
6882 kvm->arch.last_tsc_nsec = 0;
6883 kvm->arch.last_tsc_write = 0;
6890 void kvm_arch_hardware_disable(void *garbage)
6892 kvm_x86_ops->hardware_disable(garbage);
6893 drop_user_return_notifiers(garbage);
6896 int kvm_arch_hardware_setup(void)
6898 return kvm_x86_ops->hardware_setup();
6901 void kvm_arch_hardware_unsetup(void)
6903 kvm_x86_ops->hardware_unsetup();
6906 void kvm_arch_check_processor_compat(void *rtn)
6908 kvm_x86_ops->check_processor_compatibility(rtn);
6911 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6913 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6916 struct static_key kvm_no_apic_vcpu __read_mostly;
6918 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6924 BUG_ON(vcpu->kvm == NULL);
6927 vcpu->arch.pv.pv_unhalted = false;
6928 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6929 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6930 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6932 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6934 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6939 vcpu->arch.pio_data = page_address(page);
6941 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6943 r = kvm_mmu_create(vcpu);
6945 goto fail_free_pio_data;
6947 if (irqchip_in_kernel(kvm)) {
6948 r = kvm_create_lapic(vcpu);
6950 goto fail_mmu_destroy;
6952 static_key_slow_inc(&kvm_no_apic_vcpu);
6954 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6956 if (!vcpu->arch.mce_banks) {
6958 goto fail_free_lapic;
6960 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6962 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6964 goto fail_free_mce_banks;
6969 goto fail_free_wbinvd_dirty_mask;
6971 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6972 vcpu->arch.pv_time_enabled = false;
6974 vcpu->arch.guest_supported_xcr0 = 0;
6975 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
6977 kvm_async_pf_hash_reset(vcpu);
6981 fail_free_wbinvd_dirty_mask:
6982 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6983 fail_free_mce_banks:
6984 kfree(vcpu->arch.mce_banks);
6986 kvm_free_lapic(vcpu);
6988 kvm_mmu_destroy(vcpu);
6990 free_page((unsigned long)vcpu->arch.pio_data);
6995 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6999 kvm_pmu_destroy(vcpu);
7000 kfree(vcpu->arch.mce_banks);
7001 kvm_free_lapic(vcpu);
7002 idx = srcu_read_lock(&vcpu->kvm->srcu);
7003 kvm_mmu_destroy(vcpu);
7004 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7005 free_page((unsigned long)vcpu->arch.pio_data);
7006 if (!irqchip_in_kernel(vcpu->kvm))
7007 static_key_slow_dec(&kvm_no_apic_vcpu);
7010 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7015 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7016 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7017 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7018 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7020 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7021 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7022 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7023 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7024 &kvm->arch.irq_sources_bitmap);
7026 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7027 mutex_init(&kvm->arch.apic_map_lock);
7028 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7030 pvclock_update_vm_gtod_copy(kvm);
7035 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7038 r = vcpu_load(vcpu);
7040 kvm_mmu_unload(vcpu);
7044 static void kvm_free_vcpus(struct kvm *kvm)
7047 struct kvm_vcpu *vcpu;
7050 * Unpin any mmu pages first.
7052 kvm_for_each_vcpu(i, vcpu, kvm) {
7053 kvm_clear_async_pf_completion_queue(vcpu);
7054 kvm_unload_vcpu_mmu(vcpu);
7056 kvm_for_each_vcpu(i, vcpu, kvm)
7057 kvm_arch_vcpu_free(vcpu);
7059 mutex_lock(&kvm->lock);
7060 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7061 kvm->vcpus[i] = NULL;
7063 atomic_set(&kvm->online_vcpus, 0);
7064 mutex_unlock(&kvm->lock);
7067 void kvm_arch_sync_events(struct kvm *kvm)
7069 kvm_free_all_assigned_devices(kvm);
7073 void kvm_arch_destroy_vm(struct kvm *kvm)
7075 if (current->mm == kvm->mm) {
7077 * Free memory regions allocated on behalf of userspace,
7078 * unless the the memory map has changed due to process exit
7081 struct kvm_userspace_memory_region mem;
7082 memset(&mem, 0, sizeof(mem));
7083 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7084 kvm_set_memory_region(kvm, &mem);
7086 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7087 kvm_set_memory_region(kvm, &mem);
7089 mem.slot = TSS_PRIVATE_MEMSLOT;
7090 kvm_set_memory_region(kvm, &mem);
7092 kvm_iommu_unmap_guest(kvm);
7093 kfree(kvm->arch.vpic);
7094 kfree(kvm->arch.vioapic);
7095 kvm_free_vcpus(kvm);
7096 if (kvm->arch.apic_access_page)
7097 put_page(kvm->arch.apic_access_page);
7098 if (kvm->arch.ept_identity_pagetable)
7099 put_page(kvm->arch.ept_identity_pagetable);
7100 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7103 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7104 struct kvm_memory_slot *dont)
7108 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7109 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7110 kvm_kvfree(free->arch.rmap[i]);
7111 free->arch.rmap[i] = NULL;
7116 if (!dont || free->arch.lpage_info[i - 1] !=
7117 dont->arch.lpage_info[i - 1]) {
7118 kvm_kvfree(free->arch.lpage_info[i - 1]);
7119 free->arch.lpage_info[i - 1] = NULL;
7124 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7125 unsigned long npages)
7129 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7134 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7135 slot->base_gfn, level) + 1;
7137 slot->arch.rmap[i] =
7138 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7139 if (!slot->arch.rmap[i])
7144 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7145 sizeof(*slot->arch.lpage_info[i - 1]));
7146 if (!slot->arch.lpage_info[i - 1])
7149 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7150 slot->arch.lpage_info[i - 1][0].write_count = 1;
7151 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7152 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7153 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7155 * If the gfn and userspace address are not aligned wrt each
7156 * other, or if explicitly asked to, disable large page
7157 * support for this slot
7159 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7160 !kvm_largepages_enabled()) {
7163 for (j = 0; j < lpages; ++j)
7164 slot->arch.lpage_info[i - 1][j].write_count = 1;
7171 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7172 kvm_kvfree(slot->arch.rmap[i]);
7173 slot->arch.rmap[i] = NULL;
7177 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7178 slot->arch.lpage_info[i - 1] = NULL;
7183 void kvm_arch_memslots_updated(struct kvm *kvm)
7186 * memslots->generation has been incremented.
7187 * mmio generation may have reached its maximum value.
7189 kvm_mmu_invalidate_mmio_sptes(kvm);
7192 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7193 struct kvm_memory_slot *memslot,
7194 struct kvm_userspace_memory_region *mem,
7195 enum kvm_mr_change change)
7198 * Only private memory slots need to be mapped here since
7199 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7201 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7202 unsigned long userspace_addr;
7205 * MAP_SHARED to prevent internal slot pages from being moved
7208 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7209 PROT_READ | PROT_WRITE,
7210 MAP_SHARED | MAP_ANONYMOUS, 0);
7212 if (IS_ERR((void *)userspace_addr))
7213 return PTR_ERR((void *)userspace_addr);
7215 memslot->userspace_addr = userspace_addr;
7221 void kvm_arch_commit_memory_region(struct kvm *kvm,
7222 struct kvm_userspace_memory_region *mem,
7223 const struct kvm_memory_slot *old,
7224 enum kvm_mr_change change)
7227 int nr_mmu_pages = 0;
7229 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7232 ret = vm_munmap(old->userspace_addr,
7233 old->npages * PAGE_SIZE);
7236 "kvm_vm_ioctl_set_memory_region: "
7237 "failed to munmap memory\n");
7240 if (!kvm->arch.n_requested_mmu_pages)
7241 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7244 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7246 * Write protect all pages for dirty logging.
7247 * Existing largepage mappings are destroyed here and new ones will
7248 * not be created until the end of the logging.
7250 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7251 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7254 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7256 kvm_mmu_invalidate_zap_all_pages(kvm);
7259 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7260 struct kvm_memory_slot *slot)
7262 kvm_mmu_invalidate_zap_all_pages(kvm);
7265 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7267 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7268 !vcpu->arch.apf.halted)
7269 || !list_empty_careful(&vcpu->async_pf.done)
7270 || kvm_apic_has_events(vcpu)
7271 || vcpu->arch.pv.pv_unhalted
7272 || atomic_read(&vcpu->arch.nmi_queued) ||
7273 (kvm_arch_interrupt_allowed(vcpu) &&
7274 kvm_cpu_has_interrupt(vcpu));
7277 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7279 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7282 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7284 return kvm_x86_ops->interrupt_allowed(vcpu);
7287 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7289 unsigned long current_rip = kvm_rip_read(vcpu) +
7290 get_segment_base(vcpu, VCPU_SREG_CS);
7292 return current_rip == linear_rip;
7294 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7296 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7298 unsigned long rflags;
7300 rflags = kvm_x86_ops->get_rflags(vcpu);
7301 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7302 rflags &= ~X86_EFLAGS_TF;
7305 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7307 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7309 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7310 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7311 rflags |= X86_EFLAGS_TF;
7312 kvm_x86_ops->set_rflags(vcpu, rflags);
7313 kvm_make_request(KVM_REQ_EVENT, vcpu);
7315 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7317 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7321 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7325 r = kvm_mmu_reload(vcpu);
7329 if (!vcpu->arch.mmu.direct_map &&
7330 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7333 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7336 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7338 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7341 static inline u32 kvm_async_pf_next_probe(u32 key)
7343 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7346 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7348 u32 key = kvm_async_pf_hash_fn(gfn);
7350 while (vcpu->arch.apf.gfns[key] != ~0)
7351 key = kvm_async_pf_next_probe(key);
7353 vcpu->arch.apf.gfns[key] = gfn;
7356 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7359 u32 key = kvm_async_pf_hash_fn(gfn);
7361 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7362 (vcpu->arch.apf.gfns[key] != gfn &&
7363 vcpu->arch.apf.gfns[key] != ~0); i++)
7364 key = kvm_async_pf_next_probe(key);
7369 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7371 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7374 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7378 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7380 vcpu->arch.apf.gfns[i] = ~0;
7382 j = kvm_async_pf_next_probe(j);
7383 if (vcpu->arch.apf.gfns[j] == ~0)
7385 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7387 * k lies cyclically in ]i,j]
7389 * |....j i.k.| or |.k..j i...|
7391 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7392 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7397 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7400 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7404 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7405 struct kvm_async_pf *work)
7407 struct x86_exception fault;
7409 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7410 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7412 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7413 (vcpu->arch.apf.send_user_only &&
7414 kvm_x86_ops->get_cpl(vcpu) == 0))
7415 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7416 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7417 fault.vector = PF_VECTOR;
7418 fault.error_code_valid = true;
7419 fault.error_code = 0;
7420 fault.nested_page_fault = false;
7421 fault.address = work->arch.token;
7422 kvm_inject_page_fault(vcpu, &fault);
7426 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7427 struct kvm_async_pf *work)
7429 struct x86_exception fault;
7431 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7432 if (work->wakeup_all)
7433 work->arch.token = ~0; /* broadcast wakeup */
7435 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7437 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7438 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7439 fault.vector = PF_VECTOR;
7440 fault.error_code_valid = true;
7441 fault.error_code = 0;
7442 fault.nested_page_fault = false;
7443 fault.address = work->arch.token;
7444 kvm_inject_page_fault(vcpu, &fault);
7446 vcpu->arch.apf.halted = false;
7447 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7450 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7452 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7455 return !kvm_event_needs_reinjection(vcpu) &&
7456 kvm_x86_ops->interrupt_allowed(vcpu);
7459 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7461 atomic_inc(&kvm->arch.noncoherent_dma_count);
7463 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7465 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7467 atomic_dec(&kvm->arch.noncoherent_dma_count);
7469 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7471 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7473 return atomic_read(&kvm->arch.noncoherent_dma_count);
7475 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7477 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7478 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7479 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7480 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7481 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7482 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7483 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7484 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7485 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7486 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7487 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7488 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7489 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);