2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <trace/events/kvm.h>
51 #define CREATE_TRACE_POINTS
54 #include <asm/debugreg.h>
60 #include <asm/fpu-internal.h> /* Ugh! */
62 #include <asm/pvclock.h>
63 #include <asm/div64.h>
65 #define MAX_IO_MSRS 256
66 #define KVM_MAX_MCE_BANKS 32
67 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
69 #define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
78 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
80 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
86 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
87 static void process_nmi(struct kvm_vcpu *vcpu);
89 struct kvm_x86_ops *kvm_x86_ops;
90 EXPORT_SYMBOL_GPL(kvm_x86_ops);
92 static bool ignore_msrs = 0;
93 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
95 bool kvm_has_tsc_control;
96 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97 u32 kvm_max_guest_tsc_khz;
98 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
100 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101 static u32 tsc_tolerance_ppm = 250;
102 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
104 #define KVM_NR_SHARED_MSRS 16
106 struct kvm_shared_msrs_global {
108 u32 msrs[KVM_NR_SHARED_MSRS];
111 struct kvm_shared_msrs {
112 struct user_return_notifier urn;
114 struct kvm_shared_msr_values {
117 } values[KVM_NR_SHARED_MSRS];
120 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
123 struct kvm_stats_debugfs_item debugfs_entries[] = {
124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
136 { "hypercalls", VCPU_STAT(hypercalls) },
137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
144 { "irq_injections", VCPU_STAT(irq_injections) },
145 { "nmi_injections", VCPU_STAT(nmi_injections) },
146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
153 { "mmu_unsync", VM_STAT(mmu_unsync) },
154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
155 { "largepages", VM_STAT(lpages) },
159 u64 __read_mostly host_xcr0;
161 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
163 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167 vcpu->arch.apf.gfns[i] = ~0;
170 static void kvm_on_user_return(struct user_return_notifier *urn)
173 struct kvm_shared_msrs *locals
174 = container_of(urn, struct kvm_shared_msrs, urn);
175 struct kvm_shared_msr_values *values;
177 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
178 values = &locals->values[slot];
179 if (values->host != values->curr) {
180 wrmsrl(shared_msrs_global.msrs[slot], values->host);
181 values->curr = values->host;
184 locals->registered = false;
185 user_return_notifier_unregister(urn);
188 static void shared_msr_update(unsigned slot, u32 msr)
190 struct kvm_shared_msrs *smsr;
193 smsr = &__get_cpu_var(shared_msrs);
194 /* only read, and nobody should modify it at this time,
195 * so don't need lock */
196 if (slot >= shared_msrs_global.nr) {
197 printk(KERN_ERR "kvm: invalid MSR slot!");
200 rdmsrl_safe(msr, &value);
201 smsr->values[slot].host = value;
202 smsr->values[slot].curr = value;
205 void kvm_define_shared_msr(unsigned slot, u32 msr)
207 if (slot >= shared_msrs_global.nr)
208 shared_msrs_global.nr = slot + 1;
209 shared_msrs_global.msrs[slot] = msr;
210 /* we need ensured the shared_msr_global have been updated */
213 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
215 static void kvm_shared_msr_cpu_online(void)
219 for (i = 0; i < shared_msrs_global.nr; ++i)
220 shared_msr_update(i, shared_msrs_global.msrs[i]);
223 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
227 if (((value ^ smsr->values[slot].curr) & mask) == 0)
229 smsr->values[slot].curr = value;
230 wrmsrl(shared_msrs_global.msrs[slot], value);
231 if (!smsr->registered) {
232 smsr->urn.on_user_return = kvm_on_user_return;
233 user_return_notifier_register(&smsr->urn);
234 smsr->registered = true;
237 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
239 static void drop_user_return_notifiers(void *ignore)
241 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
243 if (smsr->registered)
244 kvm_on_user_return(&smsr->urn);
247 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
249 if (irqchip_in_kernel(vcpu->kvm))
250 return vcpu->arch.apic_base;
252 return vcpu->arch.apic_base;
254 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258 /* TODO: reserve bits check */
259 if (irqchip_in_kernel(vcpu->kvm))
260 kvm_lapic_set_base(vcpu, data);
262 vcpu->arch.apic_base = data;
264 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
266 #define EXCPT_BENIGN 0
267 #define EXCPT_CONTRIBUTORY 1
270 static int exception_class(int vector)
280 return EXCPT_CONTRIBUTORY;
287 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
288 unsigned nr, bool has_error, u32 error_code,
294 kvm_make_request(KVM_REQ_EVENT, vcpu);
296 if (!vcpu->arch.exception.pending) {
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = has_error;
300 vcpu->arch.exception.nr = nr;
301 vcpu->arch.exception.error_code = error_code;
302 vcpu->arch.exception.reinject = reinject;
306 /* to check exception */
307 prev_nr = vcpu->arch.exception.nr;
308 if (prev_nr == DF_VECTOR) {
309 /* triple fault -> shutdown */
310 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
313 class1 = exception_class(prev_nr);
314 class2 = exception_class(nr);
315 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317 /* generate double fault per SDM Table 5-5 */
318 vcpu->arch.exception.pending = true;
319 vcpu->arch.exception.has_error_code = true;
320 vcpu->arch.exception.nr = DF_VECTOR;
321 vcpu->arch.exception.error_code = 0;
323 /* replace previous exception with a new one in a hope
324 that instruction re-execution will regenerate lost
329 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
331 kvm_multiple_exception(vcpu, nr, false, 0, false);
333 EXPORT_SYMBOL_GPL(kvm_queue_exception);
335 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
337 kvm_multiple_exception(vcpu, nr, false, 0, true);
339 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
341 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
344 kvm_inject_gp(vcpu, 0);
346 kvm_x86_ops->skip_emulated_instruction(vcpu);
348 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
350 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
352 ++vcpu->stat.pf_guest;
353 vcpu->arch.cr2 = fault->address;
354 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
356 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
358 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
360 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
363 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
366 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
368 atomic_inc(&vcpu->arch.nmi_queued);
369 kvm_make_request(KVM_REQ_NMI, vcpu);
371 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
373 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
375 kvm_multiple_exception(vcpu, nr, true, error_code, false);
377 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
379 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
381 kvm_multiple_exception(vcpu, nr, true, error_code, true);
383 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
386 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
387 * a #GP and return false.
389 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
391 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
393 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
396 EXPORT_SYMBOL_GPL(kvm_require_cpl);
399 * This function will be used to read from the physical memory of the currently
400 * running guest. The difference to kvm_read_guest_page is that this function
401 * can read from guest physical or from the guest's guest physical memory.
403 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404 gfn_t ngfn, void *data, int offset, int len,
410 ngpa = gfn_to_gpa(ngfn);
411 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412 if (real_gfn == UNMAPPED_GVA)
415 real_gfn = gpa_to_gfn(real_gfn);
417 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
419 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
421 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422 void *data, int offset, int len, u32 access)
424 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425 data, offset, len, access);
429 * Load the pae pdptrs. Return true is they are all valid.
431 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
433 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
437 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
439 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440 offset * sizeof(u64), sizeof(pdpte),
441 PFERR_USER_MASK|PFERR_WRITE_MASK);
446 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
447 if (is_present_gpte(pdpte[i]) &&
448 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
455 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_avail);
458 __set_bit(VCPU_EXREG_PDPTR,
459 (unsigned long *)&vcpu->arch.regs_dirty);
464 EXPORT_SYMBOL_GPL(load_pdptrs);
466 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
468 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
474 if (is_long_mode(vcpu) || !is_pae(vcpu))
477 if (!test_bit(VCPU_EXREG_PDPTR,
478 (unsigned long *)&vcpu->arch.regs_avail))
481 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
483 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484 PFERR_USER_MASK | PFERR_WRITE_MASK);
487 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
493 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
495 unsigned long old_cr0 = kvm_read_cr0(vcpu);
496 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497 X86_CR0_CD | X86_CR0_NW;
502 if (cr0 & 0xffffffff00000000UL)
506 cr0 &= ~CR0_RESERVED_BITS;
508 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
511 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
516 if ((vcpu->arch.efer & EFER_LME)) {
521 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
526 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
531 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
534 kvm_x86_ops->set_cr0(vcpu, cr0);
536 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
537 kvm_clear_async_pf_completion_queue(vcpu);
538 kvm_async_pf_hash_reset(vcpu);
541 if ((cr0 ^ old_cr0) & update_bits)
542 kvm_mmu_reset_context(vcpu);
545 EXPORT_SYMBOL_GPL(kvm_set_cr0);
547 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
549 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
551 EXPORT_SYMBOL_GPL(kvm_lmsw);
553 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
557 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
558 if (index != XCR_XFEATURE_ENABLED_MASK)
561 if (kvm_x86_ops->get_cpl(vcpu) != 0)
563 if (!(xcr0 & XSTATE_FP))
565 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
567 if (xcr0 & ~host_xcr0)
569 vcpu->arch.xcr0 = xcr0;
570 vcpu->guest_xcr0_loaded = 0;
574 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
576 if (__kvm_set_xcr(vcpu, index, xcr)) {
577 kvm_inject_gp(vcpu, 0);
582 EXPORT_SYMBOL_GPL(kvm_set_xcr);
584 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
586 unsigned long old_cr4 = kvm_read_cr4(vcpu);
587 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
588 X86_CR4_PAE | X86_CR4_SMEP;
589 if (cr4 & CR4_RESERVED_BITS)
592 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
595 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
598 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
601 if (is_long_mode(vcpu)) {
602 if (!(cr4 & X86_CR4_PAE))
604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
610 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
611 if (!guest_cpuid_has_pcid(vcpu))
614 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
615 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
619 if (kvm_x86_ops->set_cr4(vcpu, cr4))
622 if (((cr4 ^ old_cr4) & pdptr_bits) ||
623 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
624 kvm_mmu_reset_context(vcpu);
626 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
627 kvm_update_cpuid(vcpu);
631 EXPORT_SYMBOL_GPL(kvm_set_cr4);
633 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
635 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
636 kvm_mmu_sync_roots(vcpu);
637 kvm_mmu_flush_tlb(vcpu);
641 if (is_long_mode(vcpu)) {
642 if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
643 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
646 if (cr3 & CR3_L_MODE_RESERVED_BITS)
650 if (cr3 & CR3_PAE_RESERVED_BITS)
652 if (is_paging(vcpu) &&
653 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
657 * We don't check reserved bits in nonpae mode, because
658 * this isn't enforced, and VMware depends on this.
663 * Does the new cr3 value map to physical memory? (Note, we
664 * catch an invalid cr3 even in real-mode, because it would
665 * cause trouble later on when we turn on paging anyway.)
667 * A real CPU would silently accept an invalid cr3 and would
668 * attempt to use it - with largely undefined (and often hard
669 * to debug) behavior on the guest side.
671 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
673 vcpu->arch.cr3 = cr3;
674 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
675 vcpu->arch.mmu.new_cr3(vcpu);
678 EXPORT_SYMBOL_GPL(kvm_set_cr3);
680 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
682 if (cr8 & CR8_RESERVED_BITS)
684 if (irqchip_in_kernel(vcpu->kvm))
685 kvm_lapic_set_tpr(vcpu, cr8);
687 vcpu->arch.cr8 = cr8;
690 EXPORT_SYMBOL_GPL(kvm_set_cr8);
692 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
694 if (irqchip_in_kernel(vcpu->kvm))
695 return kvm_lapic_get_cr8(vcpu);
697 return vcpu->arch.cr8;
699 EXPORT_SYMBOL_GPL(kvm_get_cr8);
701 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
705 vcpu->arch.db[dr] = val;
706 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
707 vcpu->arch.eff_db[dr] = val;
710 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
714 if (val & 0xffffffff00000000ULL)
716 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
719 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
723 if (val & 0xffffffff00000000ULL)
725 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
726 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
727 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
728 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
736 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
740 res = __kvm_set_dr(vcpu, dr, val);
742 kvm_queue_exception(vcpu, UD_VECTOR);
744 kvm_inject_gp(vcpu, 0);
748 EXPORT_SYMBOL_GPL(kvm_set_dr);
750 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
754 *val = vcpu->arch.db[dr];
757 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
761 *val = vcpu->arch.dr6;
764 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
768 *val = vcpu->arch.dr7;
775 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
777 if (_kvm_get_dr(vcpu, dr, val)) {
778 kvm_queue_exception(vcpu, UD_VECTOR);
783 EXPORT_SYMBOL_GPL(kvm_get_dr);
785 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
787 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
791 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
794 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
795 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
798 EXPORT_SYMBOL_GPL(kvm_rdpmc);
801 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
802 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
804 * This list is modified at module load time to reflect the
805 * capabilities of the host cpu. This capabilities test skips MSRs that are
806 * kvm-specific. Those are put in the beginning of the list.
809 #define KVM_SAVE_MSRS_BEGIN 9
810 static u32 msrs_to_save[] = {
811 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
812 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
813 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
814 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
816 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
819 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
821 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
824 static unsigned num_msrs_to_save;
826 static u32 emulated_msrs[] = {
827 MSR_IA32_TSCDEADLINE,
828 MSR_IA32_MISC_ENABLE,
833 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
835 u64 old_efer = vcpu->arch.efer;
837 if (efer & efer_reserved_bits)
841 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
844 if (efer & EFER_FFXSR) {
845 struct kvm_cpuid_entry2 *feat;
847 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
848 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
852 if (efer & EFER_SVME) {
853 struct kvm_cpuid_entry2 *feat;
855 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
856 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
861 efer |= vcpu->arch.efer & EFER_LMA;
863 kvm_x86_ops->set_efer(vcpu, efer);
865 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
867 /* Update reserved bits */
868 if ((efer ^ old_efer) & EFER_NX)
869 kvm_mmu_reset_context(vcpu);
874 void kvm_enable_efer_bits(u64 mask)
876 efer_reserved_bits &= ~mask;
878 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
882 * Writes msr value into into the appropriate "register".
883 * Returns 0 on success, non-0 otherwise.
884 * Assumes vcpu_load() was already called.
886 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
888 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
892 * Adapt set_msr() to msr_io()'s calling convention
894 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
896 return kvm_set_msr(vcpu, index, *data);
899 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
903 struct pvclock_wall_clock wc;
904 struct timespec boot;
909 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
914 ++version; /* first time write, random junk */
918 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
921 * The guest calculates current wall clock time by adding
922 * system time (updated by kvm_guest_time_update below) to the
923 * wall clock specified here. guest system time equals host
924 * system time for us, thus we must fill in host boot time here.
928 wc.sec = boot.tv_sec;
929 wc.nsec = boot.tv_nsec;
930 wc.version = version;
932 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
935 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
938 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
940 uint32_t quotient, remainder;
942 /* Don't try to replace with do_div(), this one calculates
943 * "(dividend << 32) / divisor" */
945 : "=a" (quotient), "=d" (remainder)
946 : "0" (0), "1" (dividend), "r" (divisor) );
950 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
951 s8 *pshift, u32 *pmultiplier)
958 tps64 = base_khz * 1000LL;
959 scaled64 = scaled_khz * 1000LL;
960 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
965 tps32 = (uint32_t)tps64;
966 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
967 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
975 *pmultiplier = div_frac(scaled64, tps32);
977 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
978 __func__, base_khz, scaled_khz, shift, *pmultiplier);
981 static inline u64 get_kernel_ns(void)
985 WARN_ON(preemptible());
987 monotonic_to_bootbased(&ts);
988 return timespec_to_ns(&ts);
991 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
992 unsigned long max_tsc_khz;
994 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
996 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
997 vcpu->arch.virtual_tsc_shift);
1000 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1002 u64 v = (u64)khz * (1000000 + ppm);
1007 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1009 u32 thresh_lo, thresh_hi;
1010 int use_scaling = 0;
1012 /* Compute a scale to convert nanoseconds in TSC cycles */
1013 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1014 &vcpu->arch.virtual_tsc_shift,
1015 &vcpu->arch.virtual_tsc_mult);
1016 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1019 * Compute the variation in TSC rate which is acceptable
1020 * within the range of tolerance and decide if the
1021 * rate being applied is within that bounds of the hardware
1022 * rate. If so, no scaling or compensation need be done.
1024 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1025 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1026 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1027 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1030 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1033 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1035 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1036 vcpu->arch.virtual_tsc_mult,
1037 vcpu->arch.virtual_tsc_shift);
1038 tsc += vcpu->arch.this_tsc_write;
1042 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1044 struct kvm *kvm = vcpu->kvm;
1045 u64 offset, ns, elapsed;
1046 unsigned long flags;
1049 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1050 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1051 ns = get_kernel_ns();
1052 elapsed = ns - kvm->arch.last_tsc_nsec;
1054 /* n.b - signed multiplication and division required */
1055 usdiff = data - kvm->arch.last_tsc_write;
1056 #ifdef CONFIG_X86_64
1057 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1059 /* do_div() only does unsigned */
1060 asm("idivl %2; xor %%edx, %%edx"
1062 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1064 do_div(elapsed, 1000);
1070 * Special case: TSC write with a small delta (1 second) of virtual
1071 * cycle time against real time is interpreted as an attempt to
1072 * synchronize the CPU.
1074 * For a reliable TSC, we can match TSC offsets, and for an unstable
1075 * TSC, we add elapsed time in this computation. We could let the
1076 * compensation code attempt to catch up if we fall behind, but
1077 * it's better to try to match offsets from the beginning.
1079 if (usdiff < USEC_PER_SEC &&
1080 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1081 if (!check_tsc_unstable()) {
1082 offset = kvm->arch.cur_tsc_offset;
1083 pr_debug("kvm: matched tsc offset for %llu\n", data);
1085 u64 delta = nsec_to_cycles(vcpu, elapsed);
1087 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1088 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1092 * We split periods of matched TSC writes into generations.
1093 * For each generation, we track the original measured
1094 * nanosecond time, offset, and write, so if TSCs are in
1095 * sync, we can match exact offset, and if not, we can match
1096 * exact software computation in compute_guest_tsc()
1098 * These values are tracked in kvm->arch.cur_xxx variables.
1100 kvm->arch.cur_tsc_generation++;
1101 kvm->arch.cur_tsc_nsec = ns;
1102 kvm->arch.cur_tsc_write = data;
1103 kvm->arch.cur_tsc_offset = offset;
1104 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1105 kvm->arch.cur_tsc_generation, data);
1109 * We also track th most recent recorded KHZ, write and time to
1110 * allow the matching interval to be extended at each write.
1112 kvm->arch.last_tsc_nsec = ns;
1113 kvm->arch.last_tsc_write = data;
1114 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1116 /* Reset of TSC must disable overshoot protection below */
1117 vcpu->arch.hv_clock.tsc_timestamp = 0;
1118 vcpu->arch.last_guest_tsc = data;
1120 /* Keep track of which generation this VCPU has synchronized to */
1121 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1122 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1123 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1125 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1126 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1129 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1131 static int kvm_guest_time_update(struct kvm_vcpu *v)
1133 unsigned long flags;
1134 struct kvm_vcpu_arch *vcpu = &v->arch;
1136 unsigned long this_tsc_khz;
1137 s64 kernel_ns, max_kernel_ns;
1140 /* Keep irq disabled to prevent changes to the clock */
1141 local_irq_save(flags);
1142 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1143 kernel_ns = get_kernel_ns();
1144 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1145 if (unlikely(this_tsc_khz == 0)) {
1146 local_irq_restore(flags);
1147 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1152 * We may have to catch up the TSC to match elapsed wall clock
1153 * time for two reasons, even if kvmclock is used.
1154 * 1) CPU could have been running below the maximum TSC rate
1155 * 2) Broken TSC compensation resets the base at each VCPU
1156 * entry to avoid unknown leaps of TSC even when running
1157 * again on the same CPU. This may cause apparent elapsed
1158 * time to disappear, and the guest to stand still or run
1161 if (vcpu->tsc_catchup) {
1162 u64 tsc = compute_guest_tsc(v, kernel_ns);
1163 if (tsc > tsc_timestamp) {
1164 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1165 tsc_timestamp = tsc;
1169 local_irq_restore(flags);
1171 if (!vcpu->time_page)
1175 * Time as measured by the TSC may go backwards when resetting the base
1176 * tsc_timestamp. The reason for this is that the TSC resolution is
1177 * higher than the resolution of the other clock scales. Thus, many
1178 * possible measurments of the TSC correspond to one measurement of any
1179 * other clock, and so a spread of values is possible. This is not a
1180 * problem for the computation of the nanosecond clock; with TSC rates
1181 * around 1GHZ, there can only be a few cycles which correspond to one
1182 * nanosecond value, and any path through this code will inevitably
1183 * take longer than that. However, with the kernel_ns value itself,
1184 * the precision may be much lower, down to HZ granularity. If the
1185 * first sampling of TSC against kernel_ns ends in the low part of the
1186 * range, and the second in the high end of the range, we can get:
1188 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1190 * As the sampling errors potentially range in the thousands of cycles,
1191 * it is possible such a time value has already been observed by the
1192 * guest. To protect against this, we must compute the system time as
1193 * observed by the guest and ensure the new system time is greater.
1196 if (vcpu->hv_clock.tsc_timestamp) {
1197 max_kernel_ns = vcpu->last_guest_tsc -
1198 vcpu->hv_clock.tsc_timestamp;
1199 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1200 vcpu->hv_clock.tsc_to_system_mul,
1201 vcpu->hv_clock.tsc_shift);
1202 max_kernel_ns += vcpu->last_kernel_ns;
1205 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1206 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1207 &vcpu->hv_clock.tsc_shift,
1208 &vcpu->hv_clock.tsc_to_system_mul);
1209 vcpu->hw_tsc_khz = this_tsc_khz;
1212 if (max_kernel_ns > kernel_ns)
1213 kernel_ns = max_kernel_ns;
1215 /* With all the info we got, fill in the values */
1216 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1217 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1218 vcpu->last_kernel_ns = kernel_ns;
1219 vcpu->last_guest_tsc = tsc_timestamp;
1220 vcpu->hv_clock.flags = 0;
1223 * The interface expects us to write an even number signaling that the
1224 * update is finished. Since the guest won't see the intermediate
1225 * state, we just increase by 2 at the end.
1227 vcpu->hv_clock.version += 2;
1229 shared_kaddr = kmap_atomic(vcpu->time_page);
1231 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1232 sizeof(vcpu->hv_clock));
1234 kunmap_atomic(shared_kaddr);
1236 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1240 static bool msr_mtrr_valid(unsigned msr)
1243 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1244 case MSR_MTRRfix64K_00000:
1245 case MSR_MTRRfix16K_80000:
1246 case MSR_MTRRfix16K_A0000:
1247 case MSR_MTRRfix4K_C0000:
1248 case MSR_MTRRfix4K_C8000:
1249 case MSR_MTRRfix4K_D0000:
1250 case MSR_MTRRfix4K_D8000:
1251 case MSR_MTRRfix4K_E0000:
1252 case MSR_MTRRfix4K_E8000:
1253 case MSR_MTRRfix4K_F0000:
1254 case MSR_MTRRfix4K_F8000:
1255 case MSR_MTRRdefType:
1256 case MSR_IA32_CR_PAT:
1264 static bool valid_pat_type(unsigned t)
1266 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1269 static bool valid_mtrr_type(unsigned t)
1271 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1274 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1278 if (!msr_mtrr_valid(msr))
1281 if (msr == MSR_IA32_CR_PAT) {
1282 for (i = 0; i < 8; i++)
1283 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1286 } else if (msr == MSR_MTRRdefType) {
1289 return valid_mtrr_type(data & 0xff);
1290 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1291 for (i = 0; i < 8 ; i++)
1292 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1297 /* variable MTRRs */
1298 return valid_mtrr_type(data & 0xff);
1301 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1303 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1305 if (!mtrr_valid(vcpu, msr, data))
1308 if (msr == MSR_MTRRdefType) {
1309 vcpu->arch.mtrr_state.def_type = data;
1310 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1311 } else if (msr == MSR_MTRRfix64K_00000)
1313 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1314 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1315 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1316 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1317 else if (msr == MSR_IA32_CR_PAT)
1318 vcpu->arch.pat = data;
1319 else { /* Variable MTRRs */
1320 int idx, is_mtrr_mask;
1323 idx = (msr - 0x200) / 2;
1324 is_mtrr_mask = msr - 0x200 - 2 * idx;
1327 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1330 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1334 kvm_mmu_reset_context(vcpu);
1338 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1340 u64 mcg_cap = vcpu->arch.mcg_cap;
1341 unsigned bank_num = mcg_cap & 0xff;
1344 case MSR_IA32_MCG_STATUS:
1345 vcpu->arch.mcg_status = data;
1347 case MSR_IA32_MCG_CTL:
1348 if (!(mcg_cap & MCG_CTL_P))
1350 if (data != 0 && data != ~(u64)0)
1352 vcpu->arch.mcg_ctl = data;
1355 if (msr >= MSR_IA32_MC0_CTL &&
1356 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1357 u32 offset = msr - MSR_IA32_MC0_CTL;
1358 /* only 0 or all 1s can be written to IA32_MCi_CTL
1359 * some Linux kernels though clear bit 10 in bank 4 to
1360 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1361 * this to avoid an uncatched #GP in the guest
1363 if ((offset & 0x3) == 0 &&
1364 data != 0 && (data | (1 << 10)) != ~(u64)0)
1366 vcpu->arch.mce_banks[offset] = data;
1374 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1376 struct kvm *kvm = vcpu->kvm;
1377 int lm = is_long_mode(vcpu);
1378 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1379 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1380 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1381 : kvm->arch.xen_hvm_config.blob_size_32;
1382 u32 page_num = data & ~PAGE_MASK;
1383 u64 page_addr = data & PAGE_MASK;
1388 if (page_num >= blob_size)
1391 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1396 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1405 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1407 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1410 static bool kvm_hv_msr_partition_wide(u32 msr)
1414 case HV_X64_MSR_GUEST_OS_ID:
1415 case HV_X64_MSR_HYPERCALL:
1423 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1425 struct kvm *kvm = vcpu->kvm;
1428 case HV_X64_MSR_GUEST_OS_ID:
1429 kvm->arch.hv_guest_os_id = data;
1430 /* setting guest os id to zero disables hypercall page */
1431 if (!kvm->arch.hv_guest_os_id)
1432 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1434 case HV_X64_MSR_HYPERCALL: {
1439 /* if guest os id is not set hypercall should remain disabled */
1440 if (!kvm->arch.hv_guest_os_id)
1442 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1443 kvm->arch.hv_hypercall = data;
1446 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1447 addr = gfn_to_hva(kvm, gfn);
1448 if (kvm_is_error_hva(addr))
1450 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1451 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1452 if (__copy_to_user((void __user *)addr, instructions, 4))
1454 kvm->arch.hv_hypercall = data;
1458 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1459 "data 0x%llx\n", msr, data);
1465 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1468 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1471 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1472 vcpu->arch.hv_vapic = data;
1475 addr = gfn_to_hva(vcpu->kvm, data >>
1476 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1477 if (kvm_is_error_hva(addr))
1479 if (__clear_user((void __user *)addr, PAGE_SIZE))
1481 vcpu->arch.hv_vapic = data;
1484 case HV_X64_MSR_EOI:
1485 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1486 case HV_X64_MSR_ICR:
1487 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1488 case HV_X64_MSR_TPR:
1489 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1491 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1492 "data 0x%llx\n", msr, data);
1499 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1501 gpa_t gpa = data & ~0x3f;
1503 /* Bits 2:5 are reserved, Should be zero */
1507 vcpu->arch.apf.msr_val = data;
1509 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1510 kvm_clear_async_pf_completion_queue(vcpu);
1511 kvm_async_pf_hash_reset(vcpu);
1515 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1518 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1519 kvm_async_pf_wakeup_all(vcpu);
1523 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1525 if (vcpu->arch.time_page) {
1526 kvm_release_page_dirty(vcpu->arch.time_page);
1527 vcpu->arch.time_page = NULL;
1531 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1535 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1538 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1539 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1540 vcpu->arch.st.accum_steal = delta;
1543 static void record_steal_time(struct kvm_vcpu *vcpu)
1545 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1548 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1549 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1552 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1553 vcpu->arch.st.steal.version += 2;
1554 vcpu->arch.st.accum_steal = 0;
1556 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1557 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1560 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1566 return set_efer(vcpu, data);
1568 data &= ~(u64)0x40; /* ignore flush filter disable */
1569 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1570 data &= ~(u64)0x8; /* ignore TLB cache disable */
1572 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1577 case MSR_FAM10H_MMIO_CONF_BASE:
1579 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1584 case MSR_AMD64_NB_CFG:
1586 case MSR_IA32_DEBUGCTLMSR:
1588 /* We support the non-activated case already */
1590 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1591 /* Values other than LBR and BTF are vendor-specific,
1592 thus reserved and should throw a #GP */
1595 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1598 case MSR_IA32_UCODE_REV:
1599 case MSR_IA32_UCODE_WRITE:
1600 case MSR_VM_HSAVE_PA:
1601 case MSR_AMD64_PATCH_LOADER:
1603 case 0x200 ... 0x2ff:
1604 return set_msr_mtrr(vcpu, msr, data);
1605 case MSR_IA32_APICBASE:
1606 kvm_set_apic_base(vcpu, data);
1608 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1609 return kvm_x2apic_msr_write(vcpu, msr, data);
1610 case MSR_IA32_TSCDEADLINE:
1611 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1613 case MSR_IA32_MISC_ENABLE:
1614 vcpu->arch.ia32_misc_enable_msr = data;
1616 case MSR_KVM_WALL_CLOCK_NEW:
1617 case MSR_KVM_WALL_CLOCK:
1618 vcpu->kvm->arch.wall_clock = data;
1619 kvm_write_wall_clock(vcpu->kvm, data);
1621 case MSR_KVM_SYSTEM_TIME_NEW:
1622 case MSR_KVM_SYSTEM_TIME: {
1623 kvmclock_reset(vcpu);
1625 vcpu->arch.time = data;
1626 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1628 /* we verify if the enable bit is set... */
1632 /* ...but clean it before doing the actual write */
1633 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1635 vcpu->arch.time_page =
1636 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1638 if (is_error_page(vcpu->arch.time_page)) {
1639 kvm_release_page_clean(vcpu->arch.time_page);
1640 vcpu->arch.time_page = NULL;
1644 case MSR_KVM_ASYNC_PF_EN:
1645 if (kvm_pv_enable_async_pf(vcpu, data))
1648 case MSR_KVM_STEAL_TIME:
1650 if (unlikely(!sched_info_on()))
1653 if (data & KVM_STEAL_RESERVED_MASK)
1656 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1657 data & KVM_STEAL_VALID_BITS))
1660 vcpu->arch.st.msr_val = data;
1662 if (!(data & KVM_MSR_ENABLED))
1665 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1668 accumulate_steal_time(vcpu);
1671 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1674 case MSR_KVM_PV_EOI_EN:
1675 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1679 case MSR_IA32_MCG_CTL:
1680 case MSR_IA32_MCG_STATUS:
1681 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1682 return set_msr_mce(vcpu, msr, data);
1684 /* Performance counters are not protected by a CPUID bit,
1685 * so we should check all of them in the generic path for the sake of
1686 * cross vendor migration.
1687 * Writing a zero into the event select MSRs disables them,
1688 * which we perfectly emulate ;-). Any other value should be at least
1689 * reported, some guests depend on them.
1691 case MSR_K7_EVNTSEL0:
1692 case MSR_K7_EVNTSEL1:
1693 case MSR_K7_EVNTSEL2:
1694 case MSR_K7_EVNTSEL3:
1696 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1697 "0x%x data 0x%llx\n", msr, data);
1699 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1700 * so we ignore writes to make it happy.
1702 case MSR_K7_PERFCTR0:
1703 case MSR_K7_PERFCTR1:
1704 case MSR_K7_PERFCTR2:
1705 case MSR_K7_PERFCTR3:
1706 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1707 "0x%x data 0x%llx\n", msr, data);
1709 case MSR_P6_PERFCTR0:
1710 case MSR_P6_PERFCTR1:
1712 case MSR_P6_EVNTSEL0:
1713 case MSR_P6_EVNTSEL1:
1714 if (kvm_pmu_msr(vcpu, msr))
1715 return kvm_pmu_set_msr(vcpu, msr, data);
1717 if (pr || data != 0)
1718 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1719 "0x%x data 0x%llx\n", msr, data);
1721 case MSR_K7_CLK_CTL:
1723 * Ignore all writes to this no longer documented MSR.
1724 * Writes are only relevant for old K7 processors,
1725 * all pre-dating SVM, but a recommended workaround from
1726 * AMD for these chips. It is possible to specify the
1727 * affected processor models on the command line, hence
1728 * the need to ignore the workaround.
1731 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1732 if (kvm_hv_msr_partition_wide(msr)) {
1734 mutex_lock(&vcpu->kvm->lock);
1735 r = set_msr_hyperv_pw(vcpu, msr, data);
1736 mutex_unlock(&vcpu->kvm->lock);
1739 return set_msr_hyperv(vcpu, msr, data);
1741 case MSR_IA32_BBL_CR_CTL3:
1742 /* Drop writes to this legacy MSR -- see rdmsr
1743 * counterpart for further detail.
1745 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1747 case MSR_AMD64_OSVW_ID_LENGTH:
1748 if (!guest_cpuid_has_osvw(vcpu))
1750 vcpu->arch.osvw.length = data;
1752 case MSR_AMD64_OSVW_STATUS:
1753 if (!guest_cpuid_has_osvw(vcpu))
1755 vcpu->arch.osvw.status = data;
1758 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1759 return xen_hvm_config(vcpu, data);
1760 if (kvm_pmu_msr(vcpu, msr))
1761 return kvm_pmu_set_msr(vcpu, msr, data);
1763 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1767 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1774 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1778 * Reads an msr value (of 'msr_index') into 'pdata'.
1779 * Returns 0 on success, non-0 otherwise.
1780 * Assumes vcpu_load() was already called.
1782 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1784 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1787 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1789 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1791 if (!msr_mtrr_valid(msr))
1794 if (msr == MSR_MTRRdefType)
1795 *pdata = vcpu->arch.mtrr_state.def_type +
1796 (vcpu->arch.mtrr_state.enabled << 10);
1797 else if (msr == MSR_MTRRfix64K_00000)
1799 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1800 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1801 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1802 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1803 else if (msr == MSR_IA32_CR_PAT)
1804 *pdata = vcpu->arch.pat;
1805 else { /* Variable MTRRs */
1806 int idx, is_mtrr_mask;
1809 idx = (msr - 0x200) / 2;
1810 is_mtrr_mask = msr - 0x200 - 2 * idx;
1813 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1816 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1823 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1826 u64 mcg_cap = vcpu->arch.mcg_cap;
1827 unsigned bank_num = mcg_cap & 0xff;
1830 case MSR_IA32_P5_MC_ADDR:
1831 case MSR_IA32_P5_MC_TYPE:
1834 case MSR_IA32_MCG_CAP:
1835 data = vcpu->arch.mcg_cap;
1837 case MSR_IA32_MCG_CTL:
1838 if (!(mcg_cap & MCG_CTL_P))
1840 data = vcpu->arch.mcg_ctl;
1842 case MSR_IA32_MCG_STATUS:
1843 data = vcpu->arch.mcg_status;
1846 if (msr >= MSR_IA32_MC0_CTL &&
1847 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1848 u32 offset = msr - MSR_IA32_MC0_CTL;
1849 data = vcpu->arch.mce_banks[offset];
1858 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1861 struct kvm *kvm = vcpu->kvm;
1864 case HV_X64_MSR_GUEST_OS_ID:
1865 data = kvm->arch.hv_guest_os_id;
1867 case HV_X64_MSR_HYPERCALL:
1868 data = kvm->arch.hv_hypercall;
1871 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1879 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1884 case HV_X64_MSR_VP_INDEX: {
1887 kvm_for_each_vcpu(r, v, vcpu->kvm)
1892 case HV_X64_MSR_EOI:
1893 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1894 case HV_X64_MSR_ICR:
1895 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1896 case HV_X64_MSR_TPR:
1897 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1898 case HV_X64_MSR_APIC_ASSIST_PAGE:
1899 data = vcpu->arch.hv_vapic;
1902 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1909 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1914 case MSR_IA32_PLATFORM_ID:
1915 case MSR_IA32_EBL_CR_POWERON:
1916 case MSR_IA32_DEBUGCTLMSR:
1917 case MSR_IA32_LASTBRANCHFROMIP:
1918 case MSR_IA32_LASTBRANCHTOIP:
1919 case MSR_IA32_LASTINTFROMIP:
1920 case MSR_IA32_LASTINTTOIP:
1923 case MSR_VM_HSAVE_PA:
1924 case MSR_K7_EVNTSEL0:
1925 case MSR_K7_PERFCTR0:
1926 case MSR_K8_INT_PENDING_MSG:
1927 case MSR_AMD64_NB_CFG:
1928 case MSR_FAM10H_MMIO_CONF_BASE:
1931 case MSR_P6_PERFCTR0:
1932 case MSR_P6_PERFCTR1:
1933 case MSR_P6_EVNTSEL0:
1934 case MSR_P6_EVNTSEL1:
1935 if (kvm_pmu_msr(vcpu, msr))
1936 return kvm_pmu_get_msr(vcpu, msr, pdata);
1939 case MSR_IA32_UCODE_REV:
1940 data = 0x100000000ULL;
1943 data = 0x500 | KVM_NR_VAR_MTRR;
1945 case 0x200 ... 0x2ff:
1946 return get_msr_mtrr(vcpu, msr, pdata);
1947 case 0xcd: /* fsb frequency */
1951 * MSR_EBC_FREQUENCY_ID
1952 * Conservative value valid for even the basic CPU models.
1953 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1954 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1955 * and 266MHz for model 3, or 4. Set Core Clock
1956 * Frequency to System Bus Frequency Ratio to 1 (bits
1957 * 31:24) even though these are only valid for CPU
1958 * models > 2, however guests may end up dividing or
1959 * multiplying by zero otherwise.
1961 case MSR_EBC_FREQUENCY_ID:
1964 case MSR_IA32_APICBASE:
1965 data = kvm_get_apic_base(vcpu);
1967 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1968 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1970 case MSR_IA32_TSCDEADLINE:
1971 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1973 case MSR_IA32_MISC_ENABLE:
1974 data = vcpu->arch.ia32_misc_enable_msr;
1976 case MSR_IA32_PERF_STATUS:
1977 /* TSC increment by tick */
1979 /* CPU multiplier */
1980 data |= (((uint64_t)4ULL) << 40);
1983 data = vcpu->arch.efer;
1985 case MSR_KVM_WALL_CLOCK:
1986 case MSR_KVM_WALL_CLOCK_NEW:
1987 data = vcpu->kvm->arch.wall_clock;
1989 case MSR_KVM_SYSTEM_TIME:
1990 case MSR_KVM_SYSTEM_TIME_NEW:
1991 data = vcpu->arch.time;
1993 case MSR_KVM_ASYNC_PF_EN:
1994 data = vcpu->arch.apf.msr_val;
1996 case MSR_KVM_STEAL_TIME:
1997 data = vcpu->arch.st.msr_val;
1999 case MSR_IA32_P5_MC_ADDR:
2000 case MSR_IA32_P5_MC_TYPE:
2001 case MSR_IA32_MCG_CAP:
2002 case MSR_IA32_MCG_CTL:
2003 case MSR_IA32_MCG_STATUS:
2004 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2005 return get_msr_mce(vcpu, msr, pdata);
2006 case MSR_K7_CLK_CTL:
2008 * Provide expected ramp-up count for K7. All other
2009 * are set to zero, indicating minimum divisors for
2012 * This prevents guest kernels on AMD host with CPU
2013 * type 6, model 8 and higher from exploding due to
2014 * the rdmsr failing.
2018 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2019 if (kvm_hv_msr_partition_wide(msr)) {
2021 mutex_lock(&vcpu->kvm->lock);
2022 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2023 mutex_unlock(&vcpu->kvm->lock);
2026 return get_msr_hyperv(vcpu, msr, pdata);
2028 case MSR_IA32_BBL_CR_CTL3:
2029 /* This legacy MSR exists but isn't fully documented in current
2030 * silicon. It is however accessed by winxp in very narrow
2031 * scenarios where it sets bit #19, itself documented as
2032 * a "reserved" bit. Best effort attempt to source coherent
2033 * read data here should the balance of the register be
2034 * interpreted by the guest:
2036 * L2 cache control register 3: 64GB range, 256KB size,
2037 * enabled, latency 0x1, configured
2041 case MSR_AMD64_OSVW_ID_LENGTH:
2042 if (!guest_cpuid_has_osvw(vcpu))
2044 data = vcpu->arch.osvw.length;
2046 case MSR_AMD64_OSVW_STATUS:
2047 if (!guest_cpuid_has_osvw(vcpu))
2049 data = vcpu->arch.osvw.status;
2052 if (kvm_pmu_msr(vcpu, msr))
2053 return kvm_pmu_get_msr(vcpu, msr, pdata);
2055 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2058 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2066 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2069 * Read or write a bunch of msrs. All parameters are kernel addresses.
2071 * @return number of msrs set successfully.
2073 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2074 struct kvm_msr_entry *entries,
2075 int (*do_msr)(struct kvm_vcpu *vcpu,
2076 unsigned index, u64 *data))
2080 idx = srcu_read_lock(&vcpu->kvm->srcu);
2081 for (i = 0; i < msrs->nmsrs; ++i)
2082 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2084 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2090 * Read or write a bunch of msrs. Parameters are user addresses.
2092 * @return number of msrs set successfully.
2094 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2095 int (*do_msr)(struct kvm_vcpu *vcpu,
2096 unsigned index, u64 *data),
2099 struct kvm_msrs msrs;
2100 struct kvm_msr_entry *entries;
2105 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2109 if (msrs.nmsrs >= MAX_IO_MSRS)
2112 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2113 entries = memdup_user(user_msrs->entries, size);
2114 if (IS_ERR(entries)) {
2115 r = PTR_ERR(entries);
2119 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2124 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2135 int kvm_dev_ioctl_check_extension(long ext)
2140 case KVM_CAP_IRQCHIP:
2142 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2143 case KVM_CAP_SET_TSS_ADDR:
2144 case KVM_CAP_EXT_CPUID:
2145 case KVM_CAP_CLOCKSOURCE:
2147 case KVM_CAP_NOP_IO_DELAY:
2148 case KVM_CAP_MP_STATE:
2149 case KVM_CAP_SYNC_MMU:
2150 case KVM_CAP_USER_NMI:
2151 case KVM_CAP_REINJECT_CONTROL:
2152 case KVM_CAP_IRQ_INJECT_STATUS:
2153 case KVM_CAP_ASSIGN_DEV_IRQ:
2155 case KVM_CAP_IOEVENTFD:
2157 case KVM_CAP_PIT_STATE2:
2158 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2159 case KVM_CAP_XEN_HVM:
2160 case KVM_CAP_ADJUST_CLOCK:
2161 case KVM_CAP_VCPU_EVENTS:
2162 case KVM_CAP_HYPERV:
2163 case KVM_CAP_HYPERV_VAPIC:
2164 case KVM_CAP_HYPERV_SPIN:
2165 case KVM_CAP_PCI_SEGMENT:
2166 case KVM_CAP_DEBUGREGS:
2167 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2169 case KVM_CAP_ASYNC_PF:
2170 case KVM_CAP_GET_TSC_KHZ:
2171 case KVM_CAP_PCI_2_3:
2172 case KVM_CAP_KVMCLOCK_CTRL:
2175 case KVM_CAP_COALESCED_MMIO:
2176 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2179 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2181 case KVM_CAP_NR_VCPUS:
2182 r = KVM_SOFT_MAX_VCPUS;
2184 case KVM_CAP_MAX_VCPUS:
2187 case KVM_CAP_NR_MEMSLOTS:
2188 r = KVM_MEMORY_SLOTS;
2190 case KVM_CAP_PV_MMU: /* obsolete */
2194 r = iommu_present(&pci_bus_type);
2197 r = KVM_MAX_MCE_BANKS;
2202 case KVM_CAP_TSC_CONTROL:
2203 r = kvm_has_tsc_control;
2205 case KVM_CAP_TSC_DEADLINE_TIMER:
2206 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2216 long kvm_arch_dev_ioctl(struct file *filp,
2217 unsigned int ioctl, unsigned long arg)
2219 void __user *argp = (void __user *)arg;
2223 case KVM_GET_MSR_INDEX_LIST: {
2224 struct kvm_msr_list __user *user_msr_list = argp;
2225 struct kvm_msr_list msr_list;
2229 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2232 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2233 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2236 if (n < msr_list.nmsrs)
2239 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2240 num_msrs_to_save * sizeof(u32)))
2242 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2244 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2249 case KVM_GET_SUPPORTED_CPUID: {
2250 struct kvm_cpuid2 __user *cpuid_arg = argp;
2251 struct kvm_cpuid2 cpuid;
2254 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2256 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2257 cpuid_arg->entries);
2262 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2267 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2270 mce_cap = KVM_MCE_CAP_SUPPORTED;
2272 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2284 static void wbinvd_ipi(void *garbage)
2289 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2291 return vcpu->kvm->arch.iommu_domain &&
2292 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2295 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2297 /* Address WBINVD may be executed by guest */
2298 if (need_emulate_wbinvd(vcpu)) {
2299 if (kvm_x86_ops->has_wbinvd_exit())
2300 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2301 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2302 smp_call_function_single(vcpu->cpu,
2303 wbinvd_ipi, NULL, 1);
2306 kvm_x86_ops->vcpu_load(vcpu, cpu);
2308 /* Apply any externally detected TSC adjustments (due to suspend) */
2309 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2310 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2311 vcpu->arch.tsc_offset_adjustment = 0;
2312 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2315 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2316 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2317 native_read_tsc() - vcpu->arch.last_host_tsc;
2319 mark_tsc_unstable("KVM discovered backwards TSC");
2320 if (check_tsc_unstable()) {
2321 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2322 vcpu->arch.last_guest_tsc);
2323 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2324 vcpu->arch.tsc_catchup = 1;
2326 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2327 if (vcpu->cpu != cpu)
2328 kvm_migrate_timers(vcpu);
2332 accumulate_steal_time(vcpu);
2333 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2336 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2338 kvm_x86_ops->vcpu_put(vcpu);
2339 kvm_put_guest_fpu(vcpu);
2340 vcpu->arch.last_host_tsc = native_read_tsc();
2343 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2344 struct kvm_lapic_state *s)
2346 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2351 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2352 struct kvm_lapic_state *s)
2354 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2355 kvm_apic_post_state_restore(vcpu);
2356 update_cr8_intercept(vcpu);
2361 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2362 struct kvm_interrupt *irq)
2364 if (irq->irq < 0 || irq->irq >= 256)
2366 if (irqchip_in_kernel(vcpu->kvm))
2369 kvm_queue_interrupt(vcpu, irq->irq, false);
2370 kvm_make_request(KVM_REQ_EVENT, vcpu);
2375 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2377 kvm_inject_nmi(vcpu);
2382 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2383 struct kvm_tpr_access_ctl *tac)
2387 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2391 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2395 unsigned bank_num = mcg_cap & 0xff, bank;
2398 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2400 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2403 vcpu->arch.mcg_cap = mcg_cap;
2404 /* Init IA32_MCG_CTL to all 1s */
2405 if (mcg_cap & MCG_CTL_P)
2406 vcpu->arch.mcg_ctl = ~(u64)0;
2407 /* Init IA32_MCi_CTL to all 1s */
2408 for (bank = 0; bank < bank_num; bank++)
2409 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2414 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2415 struct kvm_x86_mce *mce)
2417 u64 mcg_cap = vcpu->arch.mcg_cap;
2418 unsigned bank_num = mcg_cap & 0xff;
2419 u64 *banks = vcpu->arch.mce_banks;
2421 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2424 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2425 * reporting is disabled
2427 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2428 vcpu->arch.mcg_ctl != ~(u64)0)
2430 banks += 4 * mce->bank;
2432 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2433 * reporting is disabled for the bank
2435 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2437 if (mce->status & MCI_STATUS_UC) {
2438 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2439 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2440 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2443 if (banks[1] & MCI_STATUS_VAL)
2444 mce->status |= MCI_STATUS_OVER;
2445 banks[2] = mce->addr;
2446 banks[3] = mce->misc;
2447 vcpu->arch.mcg_status = mce->mcg_status;
2448 banks[1] = mce->status;
2449 kvm_queue_exception(vcpu, MC_VECTOR);
2450 } else if (!(banks[1] & MCI_STATUS_VAL)
2451 || !(banks[1] & MCI_STATUS_UC)) {
2452 if (banks[1] & MCI_STATUS_VAL)
2453 mce->status |= MCI_STATUS_OVER;
2454 banks[2] = mce->addr;
2455 banks[3] = mce->misc;
2456 banks[1] = mce->status;
2458 banks[1] |= MCI_STATUS_OVER;
2462 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2463 struct kvm_vcpu_events *events)
2466 events->exception.injected =
2467 vcpu->arch.exception.pending &&
2468 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2469 events->exception.nr = vcpu->arch.exception.nr;
2470 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2471 events->exception.pad = 0;
2472 events->exception.error_code = vcpu->arch.exception.error_code;
2474 events->interrupt.injected =
2475 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2476 events->interrupt.nr = vcpu->arch.interrupt.nr;
2477 events->interrupt.soft = 0;
2478 events->interrupt.shadow =
2479 kvm_x86_ops->get_interrupt_shadow(vcpu,
2480 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2482 events->nmi.injected = vcpu->arch.nmi_injected;
2483 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2484 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2485 events->nmi.pad = 0;
2487 events->sipi_vector = vcpu->arch.sipi_vector;
2489 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2490 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2491 | KVM_VCPUEVENT_VALID_SHADOW);
2492 memset(&events->reserved, 0, sizeof(events->reserved));
2495 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2496 struct kvm_vcpu_events *events)
2498 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2499 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2500 | KVM_VCPUEVENT_VALID_SHADOW))
2504 vcpu->arch.exception.pending = events->exception.injected;
2505 vcpu->arch.exception.nr = events->exception.nr;
2506 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2507 vcpu->arch.exception.error_code = events->exception.error_code;
2509 vcpu->arch.interrupt.pending = events->interrupt.injected;
2510 vcpu->arch.interrupt.nr = events->interrupt.nr;
2511 vcpu->arch.interrupt.soft = events->interrupt.soft;
2512 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2513 kvm_x86_ops->set_interrupt_shadow(vcpu,
2514 events->interrupt.shadow);
2516 vcpu->arch.nmi_injected = events->nmi.injected;
2517 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2518 vcpu->arch.nmi_pending = events->nmi.pending;
2519 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2521 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2522 vcpu->arch.sipi_vector = events->sipi_vector;
2524 kvm_make_request(KVM_REQ_EVENT, vcpu);
2529 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2530 struct kvm_debugregs *dbgregs)
2532 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2533 dbgregs->dr6 = vcpu->arch.dr6;
2534 dbgregs->dr7 = vcpu->arch.dr7;
2536 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2539 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2540 struct kvm_debugregs *dbgregs)
2545 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2546 vcpu->arch.dr6 = dbgregs->dr6;
2547 vcpu->arch.dr7 = dbgregs->dr7;
2552 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2553 struct kvm_xsave *guest_xsave)
2556 memcpy(guest_xsave->region,
2557 &vcpu->arch.guest_fpu.state->xsave,
2560 memcpy(guest_xsave->region,
2561 &vcpu->arch.guest_fpu.state->fxsave,
2562 sizeof(struct i387_fxsave_struct));
2563 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2568 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2569 struct kvm_xsave *guest_xsave)
2572 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2575 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2576 guest_xsave->region, xstate_size);
2578 if (xstate_bv & ~XSTATE_FPSSE)
2580 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2581 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2586 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2587 struct kvm_xcrs *guest_xcrs)
2589 if (!cpu_has_xsave) {
2590 guest_xcrs->nr_xcrs = 0;
2594 guest_xcrs->nr_xcrs = 1;
2595 guest_xcrs->flags = 0;
2596 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2597 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2600 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2601 struct kvm_xcrs *guest_xcrs)
2608 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2611 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2612 /* Only support XCR0 currently */
2613 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2614 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2615 guest_xcrs->xcrs[0].value);
2624 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2625 * stopped by the hypervisor. This function will be called from the host only.
2626 * EINVAL is returned when the host attempts to set the flag for a guest that
2627 * does not support pv clocks.
2629 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2631 struct pvclock_vcpu_time_info *src = &vcpu->arch.hv_clock;
2632 if (!vcpu->arch.time_page)
2634 src->flags |= PVCLOCK_GUEST_STOPPED;
2635 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2639 long kvm_arch_vcpu_ioctl(struct file *filp,
2640 unsigned int ioctl, unsigned long arg)
2642 struct kvm_vcpu *vcpu = filp->private_data;
2643 void __user *argp = (void __user *)arg;
2646 struct kvm_lapic_state *lapic;
2647 struct kvm_xsave *xsave;
2648 struct kvm_xcrs *xcrs;
2654 case KVM_GET_LAPIC: {
2656 if (!vcpu->arch.apic)
2658 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2663 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2667 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2672 case KVM_SET_LAPIC: {
2674 if (!vcpu->arch.apic)
2676 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2677 if (IS_ERR(u.lapic)) {
2678 r = PTR_ERR(u.lapic);
2682 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2688 case KVM_INTERRUPT: {
2689 struct kvm_interrupt irq;
2692 if (copy_from_user(&irq, argp, sizeof irq))
2694 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2701 r = kvm_vcpu_ioctl_nmi(vcpu);
2707 case KVM_SET_CPUID: {
2708 struct kvm_cpuid __user *cpuid_arg = argp;
2709 struct kvm_cpuid cpuid;
2712 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2714 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2719 case KVM_SET_CPUID2: {
2720 struct kvm_cpuid2 __user *cpuid_arg = argp;
2721 struct kvm_cpuid2 cpuid;
2724 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2726 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2727 cpuid_arg->entries);
2732 case KVM_GET_CPUID2: {
2733 struct kvm_cpuid2 __user *cpuid_arg = argp;
2734 struct kvm_cpuid2 cpuid;
2737 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2739 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2740 cpuid_arg->entries);
2744 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2750 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2753 r = msr_io(vcpu, argp, do_set_msr, 0);
2755 case KVM_TPR_ACCESS_REPORTING: {
2756 struct kvm_tpr_access_ctl tac;
2759 if (copy_from_user(&tac, argp, sizeof tac))
2761 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2765 if (copy_to_user(argp, &tac, sizeof tac))
2770 case KVM_SET_VAPIC_ADDR: {
2771 struct kvm_vapic_addr va;
2774 if (!irqchip_in_kernel(vcpu->kvm))
2777 if (copy_from_user(&va, argp, sizeof va))
2780 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2783 case KVM_X86_SETUP_MCE: {
2787 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2789 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2792 case KVM_X86_SET_MCE: {
2793 struct kvm_x86_mce mce;
2796 if (copy_from_user(&mce, argp, sizeof mce))
2798 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2801 case KVM_GET_VCPU_EVENTS: {
2802 struct kvm_vcpu_events events;
2804 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2807 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2812 case KVM_SET_VCPU_EVENTS: {
2813 struct kvm_vcpu_events events;
2816 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2819 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2822 case KVM_GET_DEBUGREGS: {
2823 struct kvm_debugregs dbgregs;
2825 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2828 if (copy_to_user(argp, &dbgregs,
2829 sizeof(struct kvm_debugregs)))
2834 case KVM_SET_DEBUGREGS: {
2835 struct kvm_debugregs dbgregs;
2838 if (copy_from_user(&dbgregs, argp,
2839 sizeof(struct kvm_debugregs)))
2842 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2845 case KVM_GET_XSAVE: {
2846 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2851 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2854 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2859 case KVM_SET_XSAVE: {
2860 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2861 if (IS_ERR(u.xsave)) {
2862 r = PTR_ERR(u.xsave);
2866 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2869 case KVM_GET_XCRS: {
2870 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2875 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2878 if (copy_to_user(argp, u.xcrs,
2879 sizeof(struct kvm_xcrs)))
2884 case KVM_SET_XCRS: {
2885 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2886 if (IS_ERR(u.xcrs)) {
2887 r = PTR_ERR(u.xcrs);
2891 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2894 case KVM_SET_TSC_KHZ: {
2898 user_tsc_khz = (u32)arg;
2900 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2903 if (user_tsc_khz == 0)
2904 user_tsc_khz = tsc_khz;
2906 kvm_set_tsc_khz(vcpu, user_tsc_khz);
2911 case KVM_GET_TSC_KHZ: {
2912 r = vcpu->arch.virtual_tsc_khz;
2915 case KVM_KVMCLOCK_CTRL: {
2916 r = kvm_set_guest_paused(vcpu);
2927 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2929 return VM_FAULT_SIGBUS;
2932 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2936 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2938 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2942 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2945 kvm->arch.ept_identity_map_addr = ident_addr;
2949 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2950 u32 kvm_nr_mmu_pages)
2952 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2955 mutex_lock(&kvm->slots_lock);
2956 spin_lock(&kvm->mmu_lock);
2958 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2959 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2961 spin_unlock(&kvm->mmu_lock);
2962 mutex_unlock(&kvm->slots_lock);
2966 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2968 return kvm->arch.n_max_mmu_pages;
2971 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2976 switch (chip->chip_id) {
2977 case KVM_IRQCHIP_PIC_MASTER:
2978 memcpy(&chip->chip.pic,
2979 &pic_irqchip(kvm)->pics[0],
2980 sizeof(struct kvm_pic_state));
2982 case KVM_IRQCHIP_PIC_SLAVE:
2983 memcpy(&chip->chip.pic,
2984 &pic_irqchip(kvm)->pics[1],
2985 sizeof(struct kvm_pic_state));
2987 case KVM_IRQCHIP_IOAPIC:
2988 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
2997 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3002 switch (chip->chip_id) {
3003 case KVM_IRQCHIP_PIC_MASTER:
3004 spin_lock(&pic_irqchip(kvm)->lock);
3005 memcpy(&pic_irqchip(kvm)->pics[0],
3007 sizeof(struct kvm_pic_state));
3008 spin_unlock(&pic_irqchip(kvm)->lock);
3010 case KVM_IRQCHIP_PIC_SLAVE:
3011 spin_lock(&pic_irqchip(kvm)->lock);
3012 memcpy(&pic_irqchip(kvm)->pics[1],
3014 sizeof(struct kvm_pic_state));
3015 spin_unlock(&pic_irqchip(kvm)->lock);
3017 case KVM_IRQCHIP_IOAPIC:
3018 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3024 kvm_pic_update_irq(pic_irqchip(kvm));
3028 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3032 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3033 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3034 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3038 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3042 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3043 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3044 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3045 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3049 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3053 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3054 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3055 sizeof(ps->channels));
3056 ps->flags = kvm->arch.vpit->pit_state.flags;
3057 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3058 memset(&ps->reserved, 0, sizeof(ps->reserved));
3062 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3064 int r = 0, start = 0;
3065 u32 prev_legacy, cur_legacy;
3066 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3067 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3068 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3069 if (!prev_legacy && cur_legacy)
3071 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3072 sizeof(kvm->arch.vpit->pit_state.channels));
3073 kvm->arch.vpit->pit_state.flags = ps->flags;
3074 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3075 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3079 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3080 struct kvm_reinject_control *control)
3082 if (!kvm->arch.vpit)
3084 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3085 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3086 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3091 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3092 * @kvm: kvm instance
3093 * @log: slot id and address to which we copy the log
3095 * We need to keep it in mind that VCPU threads can write to the bitmap
3096 * concurrently. So, to avoid losing data, we keep the following order for
3099 * 1. Take a snapshot of the bit and clear it if needed.
3100 * 2. Write protect the corresponding page.
3101 * 3. Flush TLB's if needed.
3102 * 4. Copy the snapshot to the userspace.
3104 * Between 2 and 3, the guest may write to the page using the remaining TLB
3105 * entry. This is not a problem because the page will be reported dirty at
3106 * step 4 using the snapshot taken before and step 3 ensures that successive
3107 * writes will be logged for the next call.
3109 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3112 struct kvm_memory_slot *memslot;
3114 unsigned long *dirty_bitmap;
3115 unsigned long *dirty_bitmap_buffer;
3116 bool is_dirty = false;
3118 mutex_lock(&kvm->slots_lock);
3121 if (log->slot >= KVM_MEMORY_SLOTS)
3124 memslot = id_to_memslot(kvm->memslots, log->slot);
3126 dirty_bitmap = memslot->dirty_bitmap;
3131 n = kvm_dirty_bitmap_bytes(memslot);
3133 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3134 memset(dirty_bitmap_buffer, 0, n);
3136 spin_lock(&kvm->mmu_lock);
3138 for (i = 0; i < n / sizeof(long); i++) {
3142 if (!dirty_bitmap[i])
3147 mask = xchg(&dirty_bitmap[i], 0);
3148 dirty_bitmap_buffer[i] = mask;
3150 offset = i * BITS_PER_LONG;
3151 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3154 kvm_flush_remote_tlbs(kvm);
3156 spin_unlock(&kvm->mmu_lock);
3159 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3164 mutex_unlock(&kvm->slots_lock);
3168 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3170 if (!irqchip_in_kernel(kvm))
3173 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3174 irq_event->irq, irq_event->level);
3178 long kvm_arch_vm_ioctl(struct file *filp,
3179 unsigned int ioctl, unsigned long arg)
3181 struct kvm *kvm = filp->private_data;
3182 void __user *argp = (void __user *)arg;
3185 * This union makes it completely explicit to gcc-3.x
3186 * that these two variables' stack usage should be
3187 * combined, not added together.
3190 struct kvm_pit_state ps;
3191 struct kvm_pit_state2 ps2;
3192 struct kvm_pit_config pit_config;
3196 case KVM_SET_TSS_ADDR:
3197 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3201 case KVM_SET_IDENTITY_MAP_ADDR: {
3205 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3207 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3212 case KVM_SET_NR_MMU_PAGES:
3213 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3217 case KVM_GET_NR_MMU_PAGES:
3218 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3220 case KVM_CREATE_IRQCHIP: {
3221 struct kvm_pic *vpic;
3223 mutex_lock(&kvm->lock);
3226 goto create_irqchip_unlock;
3228 if (atomic_read(&kvm->online_vcpus))
3229 goto create_irqchip_unlock;
3231 vpic = kvm_create_pic(kvm);
3233 r = kvm_ioapic_init(kvm);
3235 mutex_lock(&kvm->slots_lock);
3236 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3238 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3240 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3242 mutex_unlock(&kvm->slots_lock);
3244 goto create_irqchip_unlock;
3247 goto create_irqchip_unlock;
3249 kvm->arch.vpic = vpic;
3251 r = kvm_setup_default_irq_routing(kvm);
3253 mutex_lock(&kvm->slots_lock);
3254 mutex_lock(&kvm->irq_lock);
3255 kvm_ioapic_destroy(kvm);
3256 kvm_destroy_pic(kvm);
3257 mutex_unlock(&kvm->irq_lock);
3258 mutex_unlock(&kvm->slots_lock);
3260 create_irqchip_unlock:
3261 mutex_unlock(&kvm->lock);
3264 case KVM_CREATE_PIT:
3265 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3267 case KVM_CREATE_PIT2:
3269 if (copy_from_user(&u.pit_config, argp,
3270 sizeof(struct kvm_pit_config)))
3273 mutex_lock(&kvm->slots_lock);
3276 goto create_pit_unlock;
3278 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3282 mutex_unlock(&kvm->slots_lock);
3284 case KVM_GET_IRQCHIP: {
3285 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3286 struct kvm_irqchip *chip;
3288 chip = memdup_user(argp, sizeof(*chip));
3295 if (!irqchip_in_kernel(kvm))
3296 goto get_irqchip_out;
3297 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3299 goto get_irqchip_out;
3301 if (copy_to_user(argp, chip, sizeof *chip))
3302 goto get_irqchip_out;
3310 case KVM_SET_IRQCHIP: {
3311 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3312 struct kvm_irqchip *chip;
3314 chip = memdup_user(argp, sizeof(*chip));
3321 if (!irqchip_in_kernel(kvm))
3322 goto set_irqchip_out;
3323 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3325 goto set_irqchip_out;
3335 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3338 if (!kvm->arch.vpit)
3340 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3344 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3351 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3354 if (!kvm->arch.vpit)
3356 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3362 case KVM_GET_PIT2: {
3364 if (!kvm->arch.vpit)
3366 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3370 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3375 case KVM_SET_PIT2: {
3377 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3380 if (!kvm->arch.vpit)
3382 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3388 case KVM_REINJECT_CONTROL: {
3389 struct kvm_reinject_control control;
3391 if (copy_from_user(&control, argp, sizeof(control)))
3393 r = kvm_vm_ioctl_reinject(kvm, &control);
3399 case KVM_XEN_HVM_CONFIG: {
3401 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3402 sizeof(struct kvm_xen_hvm_config)))
3405 if (kvm->arch.xen_hvm_config.flags)
3410 case KVM_SET_CLOCK: {
3411 struct kvm_clock_data user_ns;
3416 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3424 local_irq_disable();
3425 now_ns = get_kernel_ns();
3426 delta = user_ns.clock - now_ns;
3428 kvm->arch.kvmclock_offset = delta;
3431 case KVM_GET_CLOCK: {
3432 struct kvm_clock_data user_ns;
3435 local_irq_disable();
3436 now_ns = get_kernel_ns();
3437 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3440 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3443 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3456 static void kvm_init_msr_list(void)
3461 /* skip the first msrs in the list. KVM-specific */
3462 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3463 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3466 msrs_to_save[j] = msrs_to_save[i];
3469 num_msrs_to_save = j;
3472 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3480 if (!(vcpu->arch.apic &&
3481 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3482 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3493 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3500 if (!(vcpu->arch.apic &&
3501 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3502 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3504 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3514 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3515 struct kvm_segment *var, int seg)
3517 kvm_x86_ops->set_segment(vcpu, var, seg);
3520 void kvm_get_segment(struct kvm_vcpu *vcpu,
3521 struct kvm_segment *var, int seg)
3523 kvm_x86_ops->get_segment(vcpu, var, seg);
3526 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3529 struct x86_exception exception;
3531 BUG_ON(!mmu_is_nested(vcpu));
3533 /* NPT walks are always user-walks */
3534 access |= PFERR_USER_MASK;
3535 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3540 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3541 struct x86_exception *exception)
3543 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3544 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3547 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3548 struct x86_exception *exception)
3550 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3551 access |= PFERR_FETCH_MASK;
3552 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3555 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3556 struct x86_exception *exception)
3558 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3559 access |= PFERR_WRITE_MASK;
3560 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3563 /* uses this to access any guest's mapped memory without checking CPL */
3564 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3565 struct x86_exception *exception)
3567 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3570 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3571 struct kvm_vcpu *vcpu, u32 access,
3572 struct x86_exception *exception)
3575 int r = X86EMUL_CONTINUE;
3578 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3580 unsigned offset = addr & (PAGE_SIZE-1);
3581 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3584 if (gpa == UNMAPPED_GVA)
3585 return X86EMUL_PROPAGATE_FAULT;
3586 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3588 r = X86EMUL_IO_NEEDED;
3600 /* used for instruction fetching */
3601 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3602 gva_t addr, void *val, unsigned int bytes,
3603 struct x86_exception *exception)
3605 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3606 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3608 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3609 access | PFERR_FETCH_MASK,
3613 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3614 gva_t addr, void *val, unsigned int bytes,
3615 struct x86_exception *exception)
3617 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3618 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3620 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3623 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3625 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3626 gva_t addr, void *val, unsigned int bytes,
3627 struct x86_exception *exception)
3629 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3630 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3633 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3634 gva_t addr, void *val,
3636 struct x86_exception *exception)
3638 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3640 int r = X86EMUL_CONTINUE;
3643 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3646 unsigned offset = addr & (PAGE_SIZE-1);
3647 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3650 if (gpa == UNMAPPED_GVA)
3651 return X86EMUL_PROPAGATE_FAULT;
3652 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3654 r = X86EMUL_IO_NEEDED;
3665 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3667 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3668 gpa_t *gpa, struct x86_exception *exception,
3671 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3673 if (vcpu_match_mmio_gva(vcpu, gva) &&
3674 check_write_user_access(vcpu, write, access,
3675 vcpu->arch.access)) {
3676 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3677 (gva & (PAGE_SIZE - 1));
3678 trace_vcpu_match_mmio(gva, *gpa, write, false);
3683 access |= PFERR_WRITE_MASK;
3685 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3687 if (*gpa == UNMAPPED_GVA)
3690 /* For APIC access vmexit */
3691 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3694 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3695 trace_vcpu_match_mmio(gva, *gpa, write, true);
3702 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3703 const void *val, int bytes)
3707 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3710 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
3714 struct read_write_emulator_ops {
3715 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3717 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3718 void *val, int bytes);
3719 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3720 int bytes, void *val);
3721 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3722 void *val, int bytes);
3726 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3728 if (vcpu->mmio_read_completed) {
3729 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3730 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
3731 vcpu->mmio_read_completed = 0;
3738 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3739 void *val, int bytes)
3741 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3744 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3745 void *val, int bytes)
3747 return emulator_write_phys(vcpu, gpa, val, bytes);
3750 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3752 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3753 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3756 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3757 void *val, int bytes)
3759 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3760 return X86EMUL_IO_NEEDED;
3763 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3764 void *val, int bytes)
3766 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3768 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
3769 return X86EMUL_CONTINUE;
3772 static struct read_write_emulator_ops read_emultor = {
3773 .read_write_prepare = read_prepare,
3774 .read_write_emulate = read_emulate,
3775 .read_write_mmio = vcpu_mmio_read,
3776 .read_write_exit_mmio = read_exit_mmio,
3779 static struct read_write_emulator_ops write_emultor = {
3780 .read_write_emulate = write_emulate,
3781 .read_write_mmio = write_mmio,
3782 .read_write_exit_mmio = write_exit_mmio,
3786 static int emulator_read_write_onepage(unsigned long addr, void *val,
3788 struct x86_exception *exception,
3789 struct kvm_vcpu *vcpu,
3790 struct read_write_emulator_ops *ops)
3794 bool write = ops->write;
3795 struct kvm_mmio_fragment *frag;
3797 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
3800 return X86EMUL_PROPAGATE_FAULT;
3802 /* For APIC access vmexit */
3806 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
3807 return X86EMUL_CONTINUE;
3811 * Is this MMIO handled locally?
3813 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
3814 if (handled == bytes)
3815 return X86EMUL_CONTINUE;
3822 unsigned now = min(bytes, 8U);
3824 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3833 return X86EMUL_CONTINUE;
3836 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3837 void *val, unsigned int bytes,
3838 struct x86_exception *exception,
3839 struct read_write_emulator_ops *ops)
3841 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3845 if (ops->read_write_prepare &&
3846 ops->read_write_prepare(vcpu, val, bytes))
3847 return X86EMUL_CONTINUE;
3849 vcpu->mmio_nr_fragments = 0;
3851 /* Crossing a page boundary? */
3852 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3855 now = -addr & ~PAGE_MASK;
3856 rc = emulator_read_write_onepage(addr, val, now, exception,
3859 if (rc != X86EMUL_CONTINUE)
3866 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3868 if (rc != X86EMUL_CONTINUE)
3871 if (!vcpu->mmio_nr_fragments)
3874 gpa = vcpu->mmio_fragments[0].gpa;
3876 vcpu->mmio_needed = 1;
3877 vcpu->mmio_cur_fragment = 0;
3879 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3880 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3881 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3882 vcpu->run->mmio.phys_addr = gpa;
3884 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
3887 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3891 struct x86_exception *exception)
3893 return emulator_read_write(ctxt, addr, val, bytes,
3894 exception, &read_emultor);
3897 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3901 struct x86_exception *exception)
3903 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3904 exception, &write_emultor);
3907 #define CMPXCHG_TYPE(t, ptr, old, new) \
3908 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3910 #ifdef CONFIG_X86_64
3911 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3913 # define CMPXCHG64(ptr, old, new) \
3914 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3917 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3922 struct x86_exception *exception)
3924 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3930 /* guests cmpxchg8b have to be emulated atomically */
3931 if (bytes > 8 || (bytes & (bytes - 1)))
3934 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3936 if (gpa == UNMAPPED_GVA ||
3937 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3940 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3943 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3944 if (is_error_page(page)) {
3945 kvm_release_page_clean(page);
3949 kaddr = kmap_atomic(page);
3950 kaddr += offset_in_page(gpa);
3953 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3956 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3959 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3962 exchanged = CMPXCHG64(kaddr, old, new);
3967 kunmap_atomic(kaddr);
3968 kvm_release_page_dirty(page);
3971 return X86EMUL_CMPXCHG_FAILED;
3973 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
3975 return X86EMUL_CONTINUE;
3978 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3980 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
3983 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3985 /* TODO: String I/O for in kernel device */
3988 if (vcpu->arch.pio.in)
3989 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3990 vcpu->arch.pio.size, pd);
3992 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3993 vcpu->arch.pio.port, vcpu->arch.pio.size,
3998 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3999 unsigned short port, void *val,
4000 unsigned int count, bool in)
4002 trace_kvm_pio(!in, port, size, count);
4004 vcpu->arch.pio.port = port;
4005 vcpu->arch.pio.in = in;
4006 vcpu->arch.pio.count = count;
4007 vcpu->arch.pio.size = size;
4009 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4010 vcpu->arch.pio.count = 0;
4014 vcpu->run->exit_reason = KVM_EXIT_IO;
4015 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4016 vcpu->run->io.size = size;
4017 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4018 vcpu->run->io.count = count;
4019 vcpu->run->io.port = port;
4024 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4025 int size, unsigned short port, void *val,
4028 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4031 if (vcpu->arch.pio.count)
4034 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4037 memcpy(val, vcpu->arch.pio_data, size * count);
4038 vcpu->arch.pio.count = 0;
4045 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4046 int size, unsigned short port,
4047 const void *val, unsigned int count)
4049 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4051 memcpy(vcpu->arch.pio_data, val, size * count);
4052 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4055 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4057 return kvm_x86_ops->get_segment_base(vcpu, seg);
4060 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4062 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4065 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4067 if (!need_emulate_wbinvd(vcpu))
4068 return X86EMUL_CONTINUE;
4070 if (kvm_x86_ops->has_wbinvd_exit()) {
4071 int cpu = get_cpu();
4073 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4074 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4075 wbinvd_ipi, NULL, 1);
4077 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4080 return X86EMUL_CONTINUE;
4082 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4084 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4086 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4089 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4091 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4094 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4097 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4100 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4102 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4105 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4107 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4108 unsigned long value;
4112 value = kvm_read_cr0(vcpu);
4115 value = vcpu->arch.cr2;
4118 value = kvm_read_cr3(vcpu);
4121 value = kvm_read_cr4(vcpu);
4124 value = kvm_get_cr8(vcpu);
4127 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4134 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4136 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4141 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4144 vcpu->arch.cr2 = val;
4147 res = kvm_set_cr3(vcpu, val);
4150 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4153 res = kvm_set_cr8(vcpu, val);
4156 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4163 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4165 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4168 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4170 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4173 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4175 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4178 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4180 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4183 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4185 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4188 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4190 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4193 static unsigned long emulator_get_cached_segment_base(
4194 struct x86_emulate_ctxt *ctxt, int seg)
4196 return get_segment_base(emul_to_vcpu(ctxt), seg);
4199 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4200 struct desc_struct *desc, u32 *base3,
4203 struct kvm_segment var;
4205 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4206 *selector = var.selector;
4213 set_desc_limit(desc, var.limit);
4214 set_desc_base(desc, (unsigned long)var.base);
4215 #ifdef CONFIG_X86_64
4217 *base3 = var.base >> 32;
4219 desc->type = var.type;
4221 desc->dpl = var.dpl;
4222 desc->p = var.present;
4223 desc->avl = var.avl;
4231 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4232 struct desc_struct *desc, u32 base3,
4235 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4236 struct kvm_segment var;
4238 var.selector = selector;
4239 var.base = get_desc_base(desc);
4240 #ifdef CONFIG_X86_64
4241 var.base |= ((u64)base3) << 32;
4243 var.limit = get_desc_limit(desc);
4245 var.limit = (var.limit << 12) | 0xfff;
4246 var.type = desc->type;
4247 var.present = desc->p;
4248 var.dpl = desc->dpl;
4253 var.avl = desc->avl;
4254 var.present = desc->p;
4255 var.unusable = !var.present;
4258 kvm_set_segment(vcpu, &var, seg);
4262 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4263 u32 msr_index, u64 *pdata)
4265 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4268 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4269 u32 msr_index, u64 data)
4271 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4274 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4275 u32 pmc, u64 *pdata)
4277 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4280 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4282 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4285 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4288 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4290 * CR0.TS may reference the host fpu state, not the guest fpu state,
4291 * so it may be clear at this point.
4296 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4301 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4302 struct x86_instruction_info *info,
4303 enum x86_intercept_stage stage)
4305 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4308 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4309 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4311 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4314 static struct x86_emulate_ops emulate_ops = {
4315 .read_std = kvm_read_guest_virt_system,
4316 .write_std = kvm_write_guest_virt_system,
4317 .fetch = kvm_fetch_guest_virt,
4318 .read_emulated = emulator_read_emulated,
4319 .write_emulated = emulator_write_emulated,
4320 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4321 .invlpg = emulator_invlpg,
4322 .pio_in_emulated = emulator_pio_in_emulated,
4323 .pio_out_emulated = emulator_pio_out_emulated,
4324 .get_segment = emulator_get_segment,
4325 .set_segment = emulator_set_segment,
4326 .get_cached_segment_base = emulator_get_cached_segment_base,
4327 .get_gdt = emulator_get_gdt,
4328 .get_idt = emulator_get_idt,
4329 .set_gdt = emulator_set_gdt,
4330 .set_idt = emulator_set_idt,
4331 .get_cr = emulator_get_cr,
4332 .set_cr = emulator_set_cr,
4333 .set_rflags = emulator_set_rflags,
4334 .cpl = emulator_get_cpl,
4335 .get_dr = emulator_get_dr,
4336 .set_dr = emulator_set_dr,
4337 .set_msr = emulator_set_msr,
4338 .get_msr = emulator_get_msr,
4339 .read_pmc = emulator_read_pmc,
4340 .halt = emulator_halt,
4341 .wbinvd = emulator_wbinvd,
4342 .fix_hypercall = emulator_fix_hypercall,
4343 .get_fpu = emulator_get_fpu,
4344 .put_fpu = emulator_put_fpu,
4345 .intercept = emulator_intercept,
4346 .get_cpuid = emulator_get_cpuid,
4349 static void cache_all_regs(struct kvm_vcpu *vcpu)
4351 kvm_register_read(vcpu, VCPU_REGS_RAX);
4352 kvm_register_read(vcpu, VCPU_REGS_RSP);
4353 kvm_register_read(vcpu, VCPU_REGS_RIP);
4354 vcpu->arch.regs_dirty = ~0;
4357 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4359 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4361 * an sti; sti; sequence only disable interrupts for the first
4362 * instruction. So, if the last instruction, be it emulated or
4363 * not, left the system with the INT_STI flag enabled, it
4364 * means that the last instruction is an sti. We should not
4365 * leave the flag on in this case. The same goes for mov ss
4367 if (!(int_shadow & mask))
4368 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4371 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4373 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4374 if (ctxt->exception.vector == PF_VECTOR)
4375 kvm_propagate_fault(vcpu, &ctxt->exception);
4376 else if (ctxt->exception.error_code_valid)
4377 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4378 ctxt->exception.error_code);
4380 kvm_queue_exception(vcpu, ctxt->exception.vector);
4383 static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
4384 const unsigned long *regs)
4386 memset(&ctxt->twobyte, 0,
4387 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4388 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
4390 ctxt->fetch.start = 0;
4391 ctxt->fetch.end = 0;
4392 ctxt->io_read.pos = 0;
4393 ctxt->io_read.end = 0;
4394 ctxt->mem_read.pos = 0;
4395 ctxt->mem_read.end = 0;
4398 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4400 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4404 * TODO: fix emulate.c to use guest_read/write_register
4405 * instead of direct ->regs accesses, can save hundred cycles
4406 * on Intel for instructions that don't read/change RSP, for
4409 cache_all_regs(vcpu);
4411 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4413 ctxt->eflags = kvm_get_rflags(vcpu);
4414 ctxt->eip = kvm_rip_read(vcpu);
4415 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4416 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4417 cs_l ? X86EMUL_MODE_PROT64 :
4418 cs_db ? X86EMUL_MODE_PROT32 :
4419 X86EMUL_MODE_PROT16;
4420 ctxt->guest_mode = is_guest_mode(vcpu);
4422 init_decode_cache(ctxt, vcpu->arch.regs);
4423 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4426 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4428 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4431 init_emulate_ctxt(vcpu);
4435 ctxt->_eip = ctxt->eip + inc_eip;
4436 ret = emulate_int_real(ctxt, irq);
4438 if (ret != X86EMUL_CONTINUE)
4439 return EMULATE_FAIL;
4441 ctxt->eip = ctxt->_eip;
4442 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4443 kvm_rip_write(vcpu, ctxt->eip);
4444 kvm_set_rflags(vcpu, ctxt->eflags);
4446 if (irq == NMI_VECTOR)
4447 vcpu->arch.nmi_pending = 0;
4449 vcpu->arch.interrupt.pending = false;
4451 return EMULATE_DONE;
4453 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4455 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4457 int r = EMULATE_DONE;
4459 ++vcpu->stat.insn_emulation_fail;
4460 trace_kvm_emulate_insn_failed(vcpu);
4461 if (!is_guest_mode(vcpu)) {
4462 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4463 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4464 vcpu->run->internal.ndata = 0;
4467 kvm_queue_exception(vcpu, UD_VECTOR);
4472 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4480 * if emulation was due to access to shadowed page table
4481 * and it failed try to unshadow page and re-enter the
4482 * guest to let CPU execute the instruction.
4484 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4487 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4489 if (gpa == UNMAPPED_GVA)
4490 return true; /* let cpu generate fault */
4492 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4498 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4499 unsigned long cr2, int emulation_type)
4501 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4502 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4504 last_retry_eip = vcpu->arch.last_retry_eip;
4505 last_retry_addr = vcpu->arch.last_retry_addr;
4508 * If the emulation is caused by #PF and it is non-page_table
4509 * writing instruction, it means the VM-EXIT is caused by shadow
4510 * page protected, we can zap the shadow page and retry this
4511 * instruction directly.
4513 * Note: if the guest uses a non-page-table modifying instruction
4514 * on the PDE that points to the instruction, then we will unmap
4515 * the instruction and go to an infinite loop. So, we cache the
4516 * last retried eip and the last fault address, if we meet the eip
4517 * and the address again, we can break out of the potential infinite
4520 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4522 if (!(emulation_type & EMULTYPE_RETRY))
4525 if (x86_page_table_writing_insn(ctxt))
4528 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4531 vcpu->arch.last_retry_eip = ctxt->eip;
4532 vcpu->arch.last_retry_addr = cr2;
4534 if (!vcpu->arch.mmu.direct_map)
4535 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4537 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4542 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4549 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4550 bool writeback = true;
4552 kvm_clear_exception_queue(vcpu);
4554 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4555 init_emulate_ctxt(vcpu);
4556 ctxt->interruptibility = 0;
4557 ctxt->have_exception = false;
4558 ctxt->perm_ok = false;
4560 ctxt->only_vendor_specific_insn
4561 = emulation_type & EMULTYPE_TRAP_UD;
4563 r = x86_decode_insn(ctxt, insn, insn_len);
4565 trace_kvm_emulate_insn_start(vcpu);
4566 ++vcpu->stat.insn_emulation;
4567 if (r != EMULATION_OK) {
4568 if (emulation_type & EMULTYPE_TRAP_UD)
4569 return EMULATE_FAIL;
4570 if (reexecute_instruction(vcpu, cr2))
4571 return EMULATE_DONE;
4572 if (emulation_type & EMULTYPE_SKIP)
4573 return EMULATE_FAIL;
4574 return handle_emulation_failure(vcpu);
4578 if (emulation_type & EMULTYPE_SKIP) {
4579 kvm_rip_write(vcpu, ctxt->_eip);
4580 return EMULATE_DONE;
4583 if (retry_instruction(ctxt, cr2, emulation_type))
4584 return EMULATE_DONE;
4586 /* this is needed for vmware backdoor interface to work since it
4587 changes registers values during IO operation */
4588 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4589 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4590 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
4594 r = x86_emulate_insn(ctxt);
4596 if (r == EMULATION_INTERCEPTED)
4597 return EMULATE_DONE;
4599 if (r == EMULATION_FAILED) {
4600 if (reexecute_instruction(vcpu, cr2))
4601 return EMULATE_DONE;
4603 return handle_emulation_failure(vcpu);
4606 if (ctxt->have_exception) {
4607 inject_emulated_exception(vcpu);
4609 } else if (vcpu->arch.pio.count) {
4610 if (!vcpu->arch.pio.in)
4611 vcpu->arch.pio.count = 0;
4614 r = EMULATE_DO_MMIO;
4615 } else if (vcpu->mmio_needed) {
4616 if (!vcpu->mmio_is_write)
4618 r = EMULATE_DO_MMIO;
4619 } else if (r == EMULATION_RESTART)
4625 toggle_interruptibility(vcpu, ctxt->interruptibility);
4626 kvm_set_rflags(vcpu, ctxt->eflags);
4627 kvm_make_request(KVM_REQ_EVENT, vcpu);
4628 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4629 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4630 kvm_rip_write(vcpu, ctxt->eip);
4632 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4636 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4638 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4640 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4641 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4642 size, port, &val, 1);
4643 /* do not return to emulator after return from userspace */
4644 vcpu->arch.pio.count = 0;
4647 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4649 static void tsc_bad(void *info)
4651 __this_cpu_write(cpu_tsc_khz, 0);
4654 static void tsc_khz_changed(void *data)
4656 struct cpufreq_freqs *freq = data;
4657 unsigned long khz = 0;
4661 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4662 khz = cpufreq_quick_get(raw_smp_processor_id());
4665 __this_cpu_write(cpu_tsc_khz, khz);
4668 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4671 struct cpufreq_freqs *freq = data;
4673 struct kvm_vcpu *vcpu;
4674 int i, send_ipi = 0;
4677 * We allow guests to temporarily run on slowing clocks,
4678 * provided we notify them after, or to run on accelerating
4679 * clocks, provided we notify them before. Thus time never
4682 * However, we have a problem. We can't atomically update
4683 * the frequency of a given CPU from this function; it is
4684 * merely a notifier, which can be called from any CPU.
4685 * Changing the TSC frequency at arbitrary points in time
4686 * requires a recomputation of local variables related to
4687 * the TSC for each VCPU. We must flag these local variables
4688 * to be updated and be sure the update takes place with the
4689 * new frequency before any guests proceed.
4691 * Unfortunately, the combination of hotplug CPU and frequency
4692 * change creates an intractable locking scenario; the order
4693 * of when these callouts happen is undefined with respect to
4694 * CPU hotplug, and they can race with each other. As such,
4695 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4696 * undefined; you can actually have a CPU frequency change take
4697 * place in between the computation of X and the setting of the
4698 * variable. To protect against this problem, all updates of
4699 * the per_cpu tsc_khz variable are done in an interrupt
4700 * protected IPI, and all callers wishing to update the value
4701 * must wait for a synchronous IPI to complete (which is trivial
4702 * if the caller is on the CPU already). This establishes the
4703 * necessary total order on variable updates.
4705 * Note that because a guest time update may take place
4706 * anytime after the setting of the VCPU's request bit, the
4707 * correct TSC value must be set before the request. However,
4708 * to ensure the update actually makes it to any guest which
4709 * starts running in hardware virtualization between the set
4710 * and the acquisition of the spinlock, we must also ping the
4711 * CPU after setting the request bit.
4715 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4717 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4720 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4722 raw_spin_lock(&kvm_lock);
4723 list_for_each_entry(kvm, &vm_list, vm_list) {
4724 kvm_for_each_vcpu(i, vcpu, kvm) {
4725 if (vcpu->cpu != freq->cpu)
4727 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4728 if (vcpu->cpu != smp_processor_id())
4732 raw_spin_unlock(&kvm_lock);
4734 if (freq->old < freq->new && send_ipi) {
4736 * We upscale the frequency. Must make the guest
4737 * doesn't see old kvmclock values while running with
4738 * the new frequency, otherwise we risk the guest sees
4739 * time go backwards.
4741 * In case we update the frequency for another cpu
4742 * (which might be in guest context) send an interrupt
4743 * to kick the cpu out of guest context. Next time
4744 * guest context is entered kvmclock will be updated,
4745 * so the guest will not see stale values.
4747 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4752 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4753 .notifier_call = kvmclock_cpufreq_notifier
4756 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4757 unsigned long action, void *hcpu)
4759 unsigned int cpu = (unsigned long)hcpu;
4763 case CPU_DOWN_FAILED:
4764 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4766 case CPU_DOWN_PREPARE:
4767 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4773 static struct notifier_block kvmclock_cpu_notifier_block = {
4774 .notifier_call = kvmclock_cpu_notifier,
4775 .priority = -INT_MAX
4778 static void kvm_timer_init(void)
4782 max_tsc_khz = tsc_khz;
4783 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4784 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4785 #ifdef CONFIG_CPU_FREQ
4786 struct cpufreq_policy policy;
4787 memset(&policy, 0, sizeof(policy));
4789 cpufreq_get_policy(&policy, cpu);
4790 if (policy.cpuinfo.max_freq)
4791 max_tsc_khz = policy.cpuinfo.max_freq;
4794 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4795 CPUFREQ_TRANSITION_NOTIFIER);
4797 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4798 for_each_online_cpu(cpu)
4799 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4802 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4804 int kvm_is_in_guest(void)
4806 return __this_cpu_read(current_vcpu) != NULL;
4809 static int kvm_is_user_mode(void)
4813 if (__this_cpu_read(current_vcpu))
4814 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
4816 return user_mode != 0;
4819 static unsigned long kvm_get_guest_ip(void)
4821 unsigned long ip = 0;
4823 if (__this_cpu_read(current_vcpu))
4824 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
4829 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4830 .is_in_guest = kvm_is_in_guest,
4831 .is_user_mode = kvm_is_user_mode,
4832 .get_guest_ip = kvm_get_guest_ip,
4835 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4837 __this_cpu_write(current_vcpu, vcpu);
4839 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4841 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4843 __this_cpu_write(current_vcpu, NULL);
4845 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4847 static void kvm_set_mmio_spte_mask(void)
4850 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4853 * Set the reserved bits and the present bit of an paging-structure
4854 * entry to generate page fault with PFER.RSV = 1.
4856 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4859 #ifdef CONFIG_X86_64
4861 * If reserved bit is not supported, clear the present bit to disable
4864 if (maxphyaddr == 52)
4868 kvm_mmu_set_mmio_spte_mask(mask);
4871 int kvm_arch_init(void *opaque)
4874 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4877 printk(KERN_ERR "kvm: already loaded the other module\n");
4882 if (!ops->cpu_has_kvm_support()) {
4883 printk(KERN_ERR "kvm: no hardware support\n");
4887 if (ops->disabled_by_bios()) {
4888 printk(KERN_ERR "kvm: disabled by bios\n");
4893 r = kvm_mmu_module_init();
4897 kvm_set_mmio_spte_mask();
4898 kvm_init_msr_list();
4901 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4902 PT_DIRTY_MASK, PT64_NX_MASK, 0);
4906 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4909 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4917 void kvm_arch_exit(void)
4919 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4921 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4922 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4923 CPUFREQ_TRANSITION_NOTIFIER);
4924 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4926 kvm_mmu_module_exit();
4929 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4931 ++vcpu->stat.halt_exits;
4932 if (irqchip_in_kernel(vcpu->kvm)) {
4933 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4936 vcpu->run->exit_reason = KVM_EXIT_HLT;
4940 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4942 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4944 u64 param, ingpa, outgpa, ret;
4945 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4946 bool fast, longmode;
4950 * hypercall generates UD from non zero cpl and real mode
4953 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4954 kvm_queue_exception(vcpu, UD_VECTOR);
4958 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4959 longmode = is_long_mode(vcpu) && cs_l == 1;
4962 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4963 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4964 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4965 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4966 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4967 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4969 #ifdef CONFIG_X86_64
4971 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4972 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4973 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4977 code = param & 0xffff;
4978 fast = (param >> 16) & 0x1;
4979 rep_cnt = (param >> 32) & 0xfff;
4980 rep_idx = (param >> 48) & 0xfff;
4982 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4985 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4986 kvm_vcpu_on_spin(vcpu);
4989 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4993 ret = res | (((u64)rep_done & 0xfff) << 32);
4995 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4997 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4998 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5004 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5006 unsigned long nr, a0, a1, a2, a3, ret;
5009 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5010 return kvm_hv_hypercall(vcpu);
5012 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5013 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5014 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5015 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5016 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5018 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5020 if (!is_long_mode(vcpu)) {
5028 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5034 case KVM_HC_VAPIC_POLL_IRQ:
5042 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5043 ++vcpu->stat.hypercalls;
5046 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5048 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5050 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5051 char instruction[3];
5052 unsigned long rip = kvm_rip_read(vcpu);
5055 * Blow out the MMU to ensure that no other VCPU has an active mapping
5056 * to ensure that the updated hypercall appears atomically across all
5059 kvm_mmu_zap_all(vcpu->kvm);
5061 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5063 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5067 * Check if userspace requested an interrupt window, and that the
5068 * interrupt window is open.
5070 * No need to exit to userspace if we already have an interrupt queued.
5072 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5074 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5075 vcpu->run->request_interrupt_window &&
5076 kvm_arch_interrupt_allowed(vcpu));
5079 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5081 struct kvm_run *kvm_run = vcpu->run;
5083 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5084 kvm_run->cr8 = kvm_get_cr8(vcpu);
5085 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5086 if (irqchip_in_kernel(vcpu->kvm))
5087 kvm_run->ready_for_interrupt_injection = 1;
5089 kvm_run->ready_for_interrupt_injection =
5090 kvm_arch_interrupt_allowed(vcpu) &&
5091 !kvm_cpu_has_interrupt(vcpu) &&
5092 !kvm_event_needs_reinjection(vcpu);
5095 static void vapic_enter(struct kvm_vcpu *vcpu)
5097 struct kvm_lapic *apic = vcpu->arch.apic;
5100 if (!apic || !apic->vapic_addr)
5103 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5105 vcpu->arch.apic->vapic_page = page;
5108 static void vapic_exit(struct kvm_vcpu *vcpu)
5110 struct kvm_lapic *apic = vcpu->arch.apic;
5113 if (!apic || !apic->vapic_addr)
5116 idx = srcu_read_lock(&vcpu->kvm->srcu);
5117 kvm_release_page_dirty(apic->vapic_page);
5118 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5119 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5122 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5126 if (!kvm_x86_ops->update_cr8_intercept)
5129 if (!vcpu->arch.apic)
5132 if (!vcpu->arch.apic->vapic_addr)
5133 max_irr = kvm_lapic_find_highest_irr(vcpu);
5140 tpr = kvm_lapic_get_cr8(vcpu);
5142 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5145 static void inject_pending_event(struct kvm_vcpu *vcpu)
5147 /* try to reinject previous events if any */
5148 if (vcpu->arch.exception.pending) {
5149 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5150 vcpu->arch.exception.has_error_code,
5151 vcpu->arch.exception.error_code);
5152 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5153 vcpu->arch.exception.has_error_code,
5154 vcpu->arch.exception.error_code,
5155 vcpu->arch.exception.reinject);
5159 if (vcpu->arch.nmi_injected) {
5160 kvm_x86_ops->set_nmi(vcpu);
5164 if (vcpu->arch.interrupt.pending) {
5165 kvm_x86_ops->set_irq(vcpu);
5169 /* try to inject new event if pending */
5170 if (vcpu->arch.nmi_pending) {
5171 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5172 --vcpu->arch.nmi_pending;
5173 vcpu->arch.nmi_injected = true;
5174 kvm_x86_ops->set_nmi(vcpu);
5176 } else if (kvm_cpu_has_interrupt(vcpu)) {
5177 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5178 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5180 kvm_x86_ops->set_irq(vcpu);
5185 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5187 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5188 !vcpu->guest_xcr0_loaded) {
5189 /* kvm_set_xcr() also depends on this */
5190 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5191 vcpu->guest_xcr0_loaded = 1;
5195 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5197 if (vcpu->guest_xcr0_loaded) {
5198 if (vcpu->arch.xcr0 != host_xcr0)
5199 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5200 vcpu->guest_xcr0_loaded = 0;
5204 static void process_nmi(struct kvm_vcpu *vcpu)
5209 * x86 is limited to one NMI running, and one NMI pending after it.
5210 * If an NMI is already in progress, limit further NMIs to just one.
5211 * Otherwise, allow two (and we'll inject the first one immediately).
5213 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5216 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5217 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5218 kvm_make_request(KVM_REQ_EVENT, vcpu);
5221 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5224 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5225 vcpu->run->request_interrupt_window;
5226 bool req_immediate_exit = 0;
5228 if (vcpu->requests) {
5229 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5230 kvm_mmu_unload(vcpu);
5231 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5232 __kvm_migrate_timers(vcpu);
5233 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5234 r = kvm_guest_time_update(vcpu);
5238 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5239 kvm_mmu_sync_roots(vcpu);
5240 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5241 kvm_x86_ops->tlb_flush(vcpu);
5242 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5243 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5247 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5248 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5252 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5253 vcpu->fpu_active = 0;
5254 kvm_x86_ops->fpu_deactivate(vcpu);
5256 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5257 /* Page is swapped out. Do synthetic halt */
5258 vcpu->arch.apf.halted = true;
5262 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5263 record_steal_time(vcpu);
5264 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5266 req_immediate_exit =
5267 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5268 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5269 kvm_handle_pmu_event(vcpu);
5270 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5271 kvm_deliver_pmi(vcpu);
5274 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5275 inject_pending_event(vcpu);
5277 /* enable NMI/IRQ window open exits if needed */
5278 if (vcpu->arch.nmi_pending)
5279 kvm_x86_ops->enable_nmi_window(vcpu);
5280 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5281 kvm_x86_ops->enable_irq_window(vcpu);
5283 if (kvm_lapic_enabled(vcpu)) {
5284 update_cr8_intercept(vcpu);
5285 kvm_lapic_sync_to_vapic(vcpu);
5289 r = kvm_mmu_reload(vcpu);
5291 goto cancel_injection;
5296 kvm_x86_ops->prepare_guest_switch(vcpu);
5297 if (vcpu->fpu_active)
5298 kvm_load_guest_fpu(vcpu);
5299 kvm_load_guest_xcr0(vcpu);
5301 vcpu->mode = IN_GUEST_MODE;
5303 /* We should set ->mode before check ->requests,
5304 * see the comment in make_all_cpus_request.
5308 local_irq_disable();
5310 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5311 || need_resched() || signal_pending(current)) {
5312 vcpu->mode = OUTSIDE_GUEST_MODE;
5317 goto cancel_injection;
5320 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5322 if (req_immediate_exit)
5323 smp_send_reschedule(vcpu->cpu);
5327 if (unlikely(vcpu->arch.switch_db_regs)) {
5329 set_debugreg(vcpu->arch.eff_db[0], 0);
5330 set_debugreg(vcpu->arch.eff_db[1], 1);
5331 set_debugreg(vcpu->arch.eff_db[2], 2);
5332 set_debugreg(vcpu->arch.eff_db[3], 3);
5335 trace_kvm_entry(vcpu->vcpu_id);
5336 kvm_x86_ops->run(vcpu);
5339 * If the guest has used debug registers, at least dr7
5340 * will be disabled while returning to the host.
5341 * If we don't have active breakpoints in the host, we don't
5342 * care about the messed up debug address registers. But if
5343 * we have some of them active, restore the old state.
5345 if (hw_breakpoint_active())
5346 hw_breakpoint_restore();
5348 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5350 vcpu->mode = OUTSIDE_GUEST_MODE;
5357 * We must have an instruction between local_irq_enable() and
5358 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5359 * the interrupt shadow. The stat.exits increment will do nicely.
5360 * But we need to prevent reordering, hence this barrier():
5368 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5371 * Profile KVM exit RIPs:
5373 if (unlikely(prof_on == KVM_PROFILING)) {
5374 unsigned long rip = kvm_rip_read(vcpu);
5375 profile_hit(KVM_PROFILING, (void *)rip);
5378 if (unlikely(vcpu->arch.tsc_always_catchup))
5379 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5381 if (vcpu->arch.apic_attention)
5382 kvm_lapic_sync_from_vapic(vcpu);
5384 r = kvm_x86_ops->handle_exit(vcpu);
5388 kvm_x86_ops->cancel_injection(vcpu);
5389 if (unlikely(vcpu->arch.apic_attention))
5390 kvm_lapic_sync_from_vapic(vcpu);
5396 static int __vcpu_run(struct kvm_vcpu *vcpu)
5399 struct kvm *kvm = vcpu->kvm;
5401 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5402 pr_debug("vcpu %d received sipi with vector # %x\n",
5403 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5404 kvm_lapic_reset(vcpu);
5405 r = kvm_arch_vcpu_reset(vcpu);
5408 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5411 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5416 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5417 !vcpu->arch.apf.halted)
5418 r = vcpu_enter_guest(vcpu);
5420 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5421 kvm_vcpu_block(vcpu);
5422 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5423 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5425 switch(vcpu->arch.mp_state) {
5426 case KVM_MP_STATE_HALTED:
5427 vcpu->arch.mp_state =
5428 KVM_MP_STATE_RUNNABLE;
5429 case KVM_MP_STATE_RUNNABLE:
5430 vcpu->arch.apf.halted = false;
5432 case KVM_MP_STATE_SIPI_RECEIVED:
5443 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5444 if (kvm_cpu_has_pending_timer(vcpu))
5445 kvm_inject_pending_timer_irqs(vcpu);
5447 if (dm_request_for_irq_injection(vcpu)) {
5449 vcpu->run->exit_reason = KVM_EXIT_INTR;
5450 ++vcpu->stat.request_irq_exits;
5453 kvm_check_async_pf_completion(vcpu);
5455 if (signal_pending(current)) {
5457 vcpu->run->exit_reason = KVM_EXIT_INTR;
5458 ++vcpu->stat.signal_exits;
5460 if (need_resched()) {
5461 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5463 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5467 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5475 * Implements the following, as a state machine:
5490 static int complete_mmio(struct kvm_vcpu *vcpu)
5492 struct kvm_run *run = vcpu->run;
5493 struct kvm_mmio_fragment *frag;
5496 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5499 if (vcpu->mmio_needed) {
5500 /* Complete previous fragment */
5501 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5502 if (!vcpu->mmio_is_write)
5503 memcpy(frag->data, run->mmio.data, frag->len);
5504 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5505 vcpu->mmio_needed = 0;
5506 if (vcpu->mmio_is_write)
5508 vcpu->mmio_read_completed = 1;
5511 /* Initiate next fragment */
5513 run->exit_reason = KVM_EXIT_MMIO;
5514 run->mmio.phys_addr = frag->gpa;
5515 if (vcpu->mmio_is_write)
5516 memcpy(run->mmio.data, frag->data, frag->len);
5517 run->mmio.len = frag->len;
5518 run->mmio.is_write = vcpu->mmio_is_write;
5523 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5524 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5525 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5526 if (r != EMULATE_DONE)
5531 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5536 if (!tsk_used_math(current) && init_fpu(current))
5539 if (vcpu->sigset_active)
5540 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5542 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5543 kvm_vcpu_block(vcpu);
5544 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5549 /* re-sync apic's tpr */
5550 if (!irqchip_in_kernel(vcpu->kvm)) {
5551 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5557 r = complete_mmio(vcpu);
5561 r = __vcpu_run(vcpu);
5564 post_kvm_run_save(vcpu);
5565 if (vcpu->sigset_active)
5566 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5571 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5573 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5575 * We are here if userspace calls get_regs() in the middle of
5576 * instruction emulation. Registers state needs to be copied
5577 * back from emulation context to vcpu. Userspace shouldn't do
5578 * that usually, but some bad designed PV devices (vmware
5579 * backdoor interface) need this to work
5581 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5582 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5583 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5585 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5586 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5587 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5588 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5589 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5590 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5591 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5592 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5593 #ifdef CONFIG_X86_64
5594 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5595 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5596 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5597 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5598 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5599 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5600 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5601 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5604 regs->rip = kvm_rip_read(vcpu);
5605 regs->rflags = kvm_get_rflags(vcpu);
5610 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5612 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5613 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5615 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5616 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5617 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5618 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5619 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5620 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5621 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5622 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5623 #ifdef CONFIG_X86_64
5624 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5625 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5626 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5627 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5628 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5629 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5630 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5631 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5634 kvm_rip_write(vcpu, regs->rip);
5635 kvm_set_rflags(vcpu, regs->rflags);
5637 vcpu->arch.exception.pending = false;
5639 kvm_make_request(KVM_REQ_EVENT, vcpu);
5644 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5646 struct kvm_segment cs;
5648 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5652 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5654 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5655 struct kvm_sregs *sregs)
5659 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5660 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5661 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5662 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5663 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5664 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5666 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5667 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5669 kvm_x86_ops->get_idt(vcpu, &dt);
5670 sregs->idt.limit = dt.size;
5671 sregs->idt.base = dt.address;
5672 kvm_x86_ops->get_gdt(vcpu, &dt);
5673 sregs->gdt.limit = dt.size;
5674 sregs->gdt.base = dt.address;
5676 sregs->cr0 = kvm_read_cr0(vcpu);
5677 sregs->cr2 = vcpu->arch.cr2;
5678 sregs->cr3 = kvm_read_cr3(vcpu);
5679 sregs->cr4 = kvm_read_cr4(vcpu);
5680 sregs->cr8 = kvm_get_cr8(vcpu);
5681 sregs->efer = vcpu->arch.efer;
5682 sregs->apic_base = kvm_get_apic_base(vcpu);
5684 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5686 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5687 set_bit(vcpu->arch.interrupt.nr,
5688 (unsigned long *)sregs->interrupt_bitmap);
5693 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5694 struct kvm_mp_state *mp_state)
5696 mp_state->mp_state = vcpu->arch.mp_state;
5700 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5701 struct kvm_mp_state *mp_state)
5703 vcpu->arch.mp_state = mp_state->mp_state;
5704 kvm_make_request(KVM_REQ_EVENT, vcpu);
5708 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5709 int reason, bool has_error_code, u32 error_code)
5711 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5714 init_emulate_ctxt(vcpu);
5716 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
5717 has_error_code, error_code);
5720 return EMULATE_FAIL;
5722 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5723 kvm_rip_write(vcpu, ctxt->eip);
5724 kvm_set_rflags(vcpu, ctxt->eflags);
5725 kvm_make_request(KVM_REQ_EVENT, vcpu);
5726 return EMULATE_DONE;
5728 EXPORT_SYMBOL_GPL(kvm_task_switch);
5730 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5731 struct kvm_sregs *sregs)
5733 int mmu_reset_needed = 0;
5734 int pending_vec, max_bits, idx;
5737 dt.size = sregs->idt.limit;
5738 dt.address = sregs->idt.base;
5739 kvm_x86_ops->set_idt(vcpu, &dt);
5740 dt.size = sregs->gdt.limit;
5741 dt.address = sregs->gdt.base;
5742 kvm_x86_ops->set_gdt(vcpu, &dt);
5744 vcpu->arch.cr2 = sregs->cr2;
5745 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
5746 vcpu->arch.cr3 = sregs->cr3;
5747 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5749 kvm_set_cr8(vcpu, sregs->cr8);
5751 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5752 kvm_x86_ops->set_efer(vcpu, sregs->efer);
5753 kvm_set_apic_base(vcpu, sregs->apic_base);
5755 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5756 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5757 vcpu->arch.cr0 = sregs->cr0;
5759 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5760 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5761 if (sregs->cr4 & X86_CR4_OSXSAVE)
5762 kvm_update_cpuid(vcpu);
5764 idx = srcu_read_lock(&vcpu->kvm->srcu);
5765 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5766 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
5767 mmu_reset_needed = 1;
5769 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5771 if (mmu_reset_needed)
5772 kvm_mmu_reset_context(vcpu);
5774 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5775 pending_vec = find_first_bit(
5776 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5777 if (pending_vec < max_bits) {
5778 kvm_queue_interrupt(vcpu, pending_vec, false);
5779 pr_debug("Set back pending irq %d\n", pending_vec);
5782 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5783 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5784 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5785 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5786 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5787 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5789 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5790 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5792 update_cr8_intercept(vcpu);
5794 /* Older userspace won't unhalt the vcpu on reset. */
5795 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5796 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5798 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5800 kvm_make_request(KVM_REQ_EVENT, vcpu);
5805 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5806 struct kvm_guest_debug *dbg)
5808 unsigned long rflags;
5811 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5813 if (vcpu->arch.exception.pending)
5815 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5816 kvm_queue_exception(vcpu, DB_VECTOR);
5818 kvm_queue_exception(vcpu, BP_VECTOR);
5822 * Read rflags as long as potentially injected trace flags are still
5825 rflags = kvm_get_rflags(vcpu);
5827 vcpu->guest_debug = dbg->control;
5828 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5829 vcpu->guest_debug = 0;
5831 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5832 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5833 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5834 vcpu->arch.switch_db_regs =
5835 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5837 for (i = 0; i < KVM_NR_DB_REGS; i++)
5838 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5839 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5842 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5843 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5844 get_segment_base(vcpu, VCPU_SREG_CS);
5847 * Trigger an rflags update that will inject or remove the trace
5850 kvm_set_rflags(vcpu, rflags);
5852 kvm_x86_ops->set_guest_debug(vcpu, dbg);
5862 * Translate a guest virtual address to a guest physical address.
5864 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5865 struct kvm_translation *tr)
5867 unsigned long vaddr = tr->linear_address;
5871 idx = srcu_read_lock(&vcpu->kvm->srcu);
5872 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5873 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5874 tr->physical_address = gpa;
5875 tr->valid = gpa != UNMAPPED_GVA;
5882 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5884 struct i387_fxsave_struct *fxsave =
5885 &vcpu->arch.guest_fpu.state->fxsave;
5887 memcpy(fpu->fpr, fxsave->st_space, 128);
5888 fpu->fcw = fxsave->cwd;
5889 fpu->fsw = fxsave->swd;
5890 fpu->ftwx = fxsave->twd;
5891 fpu->last_opcode = fxsave->fop;
5892 fpu->last_ip = fxsave->rip;
5893 fpu->last_dp = fxsave->rdp;
5894 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5899 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5901 struct i387_fxsave_struct *fxsave =
5902 &vcpu->arch.guest_fpu.state->fxsave;
5904 memcpy(fxsave->st_space, fpu->fpr, 128);
5905 fxsave->cwd = fpu->fcw;
5906 fxsave->swd = fpu->fsw;
5907 fxsave->twd = fpu->ftwx;
5908 fxsave->fop = fpu->last_opcode;
5909 fxsave->rip = fpu->last_ip;
5910 fxsave->rdp = fpu->last_dp;
5911 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5916 int fx_init(struct kvm_vcpu *vcpu)
5920 err = fpu_alloc(&vcpu->arch.guest_fpu);
5924 fpu_finit(&vcpu->arch.guest_fpu);
5927 * Ensure guest xcr0 is valid for loading
5929 vcpu->arch.xcr0 = XSTATE_FP;
5931 vcpu->arch.cr0 |= X86_CR0_ET;
5935 EXPORT_SYMBOL_GPL(fx_init);
5937 static void fx_free(struct kvm_vcpu *vcpu)
5939 fpu_free(&vcpu->arch.guest_fpu);
5942 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5944 if (vcpu->guest_fpu_loaded)
5948 * Restore all possible states in the guest,
5949 * and assume host would use all available bits.
5950 * Guest xcr0 would be loaded later.
5952 kvm_put_guest_xcr0(vcpu);
5953 vcpu->guest_fpu_loaded = 1;
5954 unlazy_fpu(current);
5955 fpu_restore_checking(&vcpu->arch.guest_fpu);
5959 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5961 kvm_put_guest_xcr0(vcpu);
5963 if (!vcpu->guest_fpu_loaded)
5966 vcpu->guest_fpu_loaded = 0;
5967 fpu_save_init(&vcpu->arch.guest_fpu);
5968 ++vcpu->stat.fpu_reload;
5969 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5973 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5975 kvmclock_reset(vcpu);
5977 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5979 kvm_x86_ops->vcpu_free(vcpu);
5982 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5985 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5986 printk_once(KERN_WARNING
5987 "kvm: SMP vm created on host with unstable TSC; "
5988 "guest TSC will not be reliable\n");
5989 return kvm_x86_ops->vcpu_create(kvm, id);
5992 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5996 vcpu->arch.mtrr_state.have_fixed = 1;
5998 r = kvm_arch_vcpu_reset(vcpu);
6000 r = kvm_mmu_setup(vcpu);
6006 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6008 vcpu->arch.apf.msr_val = 0;
6011 kvm_mmu_unload(vcpu);
6015 kvm_x86_ops->vcpu_free(vcpu);
6018 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6020 atomic_set(&vcpu->arch.nmi_queued, 0);
6021 vcpu->arch.nmi_pending = 0;
6022 vcpu->arch.nmi_injected = false;
6024 vcpu->arch.switch_db_regs = 0;
6025 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6026 vcpu->arch.dr6 = DR6_FIXED_1;
6027 vcpu->arch.dr7 = DR7_FIXED_1;
6029 kvm_make_request(KVM_REQ_EVENT, vcpu);
6030 vcpu->arch.apf.msr_val = 0;
6031 vcpu->arch.st.msr_val = 0;
6033 kvmclock_reset(vcpu);
6035 kvm_clear_async_pf_completion_queue(vcpu);
6036 kvm_async_pf_hash_reset(vcpu);
6037 vcpu->arch.apf.halted = false;
6039 kvm_pmu_reset(vcpu);
6041 return kvm_x86_ops->vcpu_reset(vcpu);
6044 int kvm_arch_hardware_enable(void *garbage)
6047 struct kvm_vcpu *vcpu;
6052 bool stable, backwards_tsc = false;
6054 kvm_shared_msr_cpu_online();
6055 ret = kvm_x86_ops->hardware_enable(garbage);
6059 local_tsc = native_read_tsc();
6060 stable = !check_tsc_unstable();
6061 list_for_each_entry(kvm, &vm_list, vm_list) {
6062 kvm_for_each_vcpu(i, vcpu, kvm) {
6063 if (!stable && vcpu->cpu == smp_processor_id())
6064 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6065 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6066 backwards_tsc = true;
6067 if (vcpu->arch.last_host_tsc > max_tsc)
6068 max_tsc = vcpu->arch.last_host_tsc;
6074 * Sometimes, even reliable TSCs go backwards. This happens on
6075 * platforms that reset TSC during suspend or hibernate actions, but
6076 * maintain synchronization. We must compensate. Fortunately, we can
6077 * detect that condition here, which happens early in CPU bringup,
6078 * before any KVM threads can be running. Unfortunately, we can't
6079 * bring the TSCs fully up to date with real time, as we aren't yet far
6080 * enough into CPU bringup that we know how much real time has actually
6081 * elapsed; our helper function, get_kernel_ns() will be using boot
6082 * variables that haven't been updated yet.
6084 * So we simply find the maximum observed TSC above, then record the
6085 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6086 * the adjustment will be applied. Note that we accumulate
6087 * adjustments, in case multiple suspend cycles happen before some VCPU
6088 * gets a chance to run again. In the event that no KVM threads get a
6089 * chance to run, we will miss the entire elapsed period, as we'll have
6090 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6091 * loose cycle time. This isn't too big a deal, since the loss will be
6092 * uniform across all VCPUs (not to mention the scenario is extremely
6093 * unlikely). It is possible that a second hibernate recovery happens
6094 * much faster than a first, causing the observed TSC here to be
6095 * smaller; this would require additional padding adjustment, which is
6096 * why we set last_host_tsc to the local tsc observed here.
6098 * N.B. - this code below runs only on platforms with reliable TSC,
6099 * as that is the only way backwards_tsc is set above. Also note
6100 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6101 * have the same delta_cyc adjustment applied if backwards_tsc
6102 * is detected. Note further, this adjustment is only done once,
6103 * as we reset last_host_tsc on all VCPUs to stop this from being
6104 * called multiple times (one for each physical CPU bringup).
6106 * Platforms with unreliable TSCs don't have to deal with this, they
6107 * will be compensated by the logic in vcpu_load, which sets the TSC to
6108 * catchup mode. This will catchup all VCPUs to real time, but cannot
6109 * guarantee that they stay in perfect synchronization.
6111 if (backwards_tsc) {
6112 u64 delta_cyc = max_tsc - local_tsc;
6113 list_for_each_entry(kvm, &vm_list, vm_list) {
6114 kvm_for_each_vcpu(i, vcpu, kvm) {
6115 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6116 vcpu->arch.last_host_tsc = local_tsc;
6120 * We have to disable TSC offset matching.. if you were
6121 * booting a VM while issuing an S4 host suspend....
6122 * you may have some problem. Solving this issue is
6123 * left as an exercise to the reader.
6125 kvm->arch.last_tsc_nsec = 0;
6126 kvm->arch.last_tsc_write = 0;
6133 void kvm_arch_hardware_disable(void *garbage)
6135 kvm_x86_ops->hardware_disable(garbage);
6136 drop_user_return_notifiers(garbage);
6139 int kvm_arch_hardware_setup(void)
6141 return kvm_x86_ops->hardware_setup();
6144 void kvm_arch_hardware_unsetup(void)
6146 kvm_x86_ops->hardware_unsetup();
6149 void kvm_arch_check_processor_compat(void *rtn)
6151 kvm_x86_ops->check_processor_compatibility(rtn);
6154 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6156 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6159 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6165 BUG_ON(vcpu->kvm == NULL);
6168 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6169 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6170 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6172 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6174 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6179 vcpu->arch.pio_data = page_address(page);
6181 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6183 r = kvm_mmu_create(vcpu);
6185 goto fail_free_pio_data;
6187 if (irqchip_in_kernel(kvm)) {
6188 r = kvm_create_lapic(vcpu);
6190 goto fail_mmu_destroy;
6193 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6195 if (!vcpu->arch.mce_banks) {
6197 goto fail_free_lapic;
6199 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6201 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6202 goto fail_free_mce_banks;
6204 kvm_async_pf_hash_reset(vcpu);
6208 fail_free_mce_banks:
6209 kfree(vcpu->arch.mce_banks);
6211 kvm_free_lapic(vcpu);
6213 kvm_mmu_destroy(vcpu);
6215 free_page((unsigned long)vcpu->arch.pio_data);
6220 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6224 kvm_pmu_destroy(vcpu);
6225 kfree(vcpu->arch.mce_banks);
6226 kvm_free_lapic(vcpu);
6227 idx = srcu_read_lock(&vcpu->kvm->srcu);
6228 kvm_mmu_destroy(vcpu);
6229 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6230 free_page((unsigned long)vcpu->arch.pio_data);
6233 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6238 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6239 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6241 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6242 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6244 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6249 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6252 kvm_mmu_unload(vcpu);
6256 static void kvm_free_vcpus(struct kvm *kvm)
6259 struct kvm_vcpu *vcpu;
6262 * Unpin any mmu pages first.
6264 kvm_for_each_vcpu(i, vcpu, kvm) {
6265 kvm_clear_async_pf_completion_queue(vcpu);
6266 kvm_unload_vcpu_mmu(vcpu);
6268 kvm_for_each_vcpu(i, vcpu, kvm)
6269 kvm_arch_vcpu_free(vcpu);
6271 mutex_lock(&kvm->lock);
6272 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6273 kvm->vcpus[i] = NULL;
6275 atomic_set(&kvm->online_vcpus, 0);
6276 mutex_unlock(&kvm->lock);
6279 void kvm_arch_sync_events(struct kvm *kvm)
6281 kvm_free_all_assigned_devices(kvm);
6285 void kvm_arch_destroy_vm(struct kvm *kvm)
6287 kvm_iommu_unmap_guest(kvm);
6288 kfree(kvm->arch.vpic);
6289 kfree(kvm->arch.vioapic);
6290 kvm_free_vcpus(kvm);
6291 if (kvm->arch.apic_access_page)
6292 put_page(kvm->arch.apic_access_page);
6293 if (kvm->arch.ept_identity_pagetable)
6294 put_page(kvm->arch.ept_identity_pagetable);
6297 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6298 struct kvm_memory_slot *dont)
6302 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6303 if (!dont || free->arch.rmap_pde[i] != dont->arch.rmap_pde[i]) {
6304 kvm_kvfree(free->arch.rmap_pde[i]);
6305 free->arch.rmap_pde[i] = NULL;
6307 if (!dont || free->arch.lpage_info[i] != dont->arch.lpage_info[i]) {
6308 kvm_kvfree(free->arch.lpage_info[i]);
6309 free->arch.lpage_info[i] = NULL;
6314 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6318 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6323 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6324 slot->base_gfn, level) + 1;
6326 slot->arch.rmap_pde[i] =
6327 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap_pde[i]));
6328 if (!slot->arch.rmap_pde[i])
6331 slot->arch.lpage_info[i] =
6332 kvm_kvzalloc(lpages * sizeof(*slot->arch.lpage_info[i]));
6333 if (!slot->arch.lpage_info[i])
6336 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6337 slot->arch.lpage_info[i][0].write_count = 1;
6338 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6339 slot->arch.lpage_info[i][lpages - 1].write_count = 1;
6340 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6342 * If the gfn and userspace address are not aligned wrt each
6343 * other, or if explicitly asked to, disable large page
6344 * support for this slot
6346 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6347 !kvm_largepages_enabled()) {
6350 for (j = 0; j < lpages; ++j)
6351 slot->arch.lpage_info[i][j].write_count = 1;
6358 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6359 kvm_kvfree(slot->arch.rmap_pde[i]);
6360 kvm_kvfree(slot->arch.lpage_info[i]);
6361 slot->arch.rmap_pde[i] = NULL;
6362 slot->arch.lpage_info[i] = NULL;
6367 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6368 struct kvm_memory_slot *memslot,
6369 struct kvm_memory_slot old,
6370 struct kvm_userspace_memory_region *mem,
6373 int npages = memslot->npages;
6374 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6376 /* Prevent internal slot pages from being moved by fork()/COW. */
6377 if (memslot->id >= KVM_MEMORY_SLOTS)
6378 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6380 /*To keep backward compatibility with older userspace,
6381 *x86 needs to handle !user_alloc case.
6384 if (npages && !old.rmap) {
6385 unsigned long userspace_addr;
6387 userspace_addr = vm_mmap(NULL, 0,
6389 PROT_READ | PROT_WRITE,
6393 if (IS_ERR((void *)userspace_addr))
6394 return PTR_ERR((void *)userspace_addr);
6396 memslot->userspace_addr = userspace_addr;
6404 void kvm_arch_commit_memory_region(struct kvm *kvm,
6405 struct kvm_userspace_memory_region *mem,
6406 struct kvm_memory_slot old,
6410 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6412 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6415 ret = vm_munmap(old.userspace_addr,
6416 old.npages * PAGE_SIZE);
6419 "kvm_vm_ioctl_set_memory_region: "
6420 "failed to munmap memory\n");
6423 if (!kvm->arch.n_requested_mmu_pages)
6424 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6426 spin_lock(&kvm->mmu_lock);
6428 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6429 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6430 spin_unlock(&kvm->mmu_lock);
6433 void kvm_arch_flush_shadow(struct kvm *kvm)
6435 kvm_mmu_zap_all(kvm);
6436 kvm_reload_remote_mmus(kvm);
6439 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6441 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6442 !vcpu->arch.apf.halted)
6443 || !list_empty_careful(&vcpu->async_pf.done)
6444 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6445 || atomic_read(&vcpu->arch.nmi_queued) ||
6446 (kvm_arch_interrupt_allowed(vcpu) &&
6447 kvm_cpu_has_interrupt(vcpu));
6450 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
6452 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
6455 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6457 return kvm_x86_ops->interrupt_allowed(vcpu);
6460 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6462 unsigned long current_rip = kvm_rip_read(vcpu) +
6463 get_segment_base(vcpu, VCPU_SREG_CS);
6465 return current_rip == linear_rip;
6467 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6469 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6471 unsigned long rflags;
6473 rflags = kvm_x86_ops->get_rflags(vcpu);
6474 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6475 rflags &= ~X86_EFLAGS_TF;
6478 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6480 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6482 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6483 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6484 rflags |= X86_EFLAGS_TF;
6485 kvm_x86_ops->set_rflags(vcpu, rflags);
6486 kvm_make_request(KVM_REQ_EVENT, vcpu);
6488 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6490 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6494 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
6495 is_error_page(work->page))
6498 r = kvm_mmu_reload(vcpu);
6502 if (!vcpu->arch.mmu.direct_map &&
6503 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6506 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6509 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6511 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6514 static inline u32 kvm_async_pf_next_probe(u32 key)
6516 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6519 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6521 u32 key = kvm_async_pf_hash_fn(gfn);
6523 while (vcpu->arch.apf.gfns[key] != ~0)
6524 key = kvm_async_pf_next_probe(key);
6526 vcpu->arch.apf.gfns[key] = gfn;
6529 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6532 u32 key = kvm_async_pf_hash_fn(gfn);
6534 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6535 (vcpu->arch.apf.gfns[key] != gfn &&
6536 vcpu->arch.apf.gfns[key] != ~0); i++)
6537 key = kvm_async_pf_next_probe(key);
6542 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6544 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6547 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6551 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6553 vcpu->arch.apf.gfns[i] = ~0;
6555 j = kvm_async_pf_next_probe(j);
6556 if (vcpu->arch.apf.gfns[j] == ~0)
6558 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6560 * k lies cyclically in ]i,j]
6562 * |....j i.k.| or |.k..j i...|
6564 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6565 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6570 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6573 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6577 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6578 struct kvm_async_pf *work)
6580 struct x86_exception fault;
6582 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
6583 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
6585 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
6586 (vcpu->arch.apf.send_user_only &&
6587 kvm_x86_ops->get_cpl(vcpu) == 0))
6588 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6589 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6590 fault.vector = PF_VECTOR;
6591 fault.error_code_valid = true;
6592 fault.error_code = 0;
6593 fault.nested_page_fault = false;
6594 fault.address = work->arch.token;
6595 kvm_inject_page_fault(vcpu, &fault);
6599 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6600 struct kvm_async_pf *work)
6602 struct x86_exception fault;
6604 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6605 if (is_error_page(work->page))
6606 work->arch.token = ~0; /* broadcast wakeup */
6608 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6610 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6611 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6612 fault.vector = PF_VECTOR;
6613 fault.error_code_valid = true;
6614 fault.error_code = 0;
6615 fault.nested_page_fault = false;
6616 fault.address = work->arch.token;
6617 kvm_inject_page_fault(vcpu, &fault);
6619 vcpu->arch.apf.halted = false;
6620 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6623 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6625 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6628 return !kvm_event_needs_reinjection(vcpu) &&
6629 kvm_x86_ops->interrupt_allowed(vcpu);
6632 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6633 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6634 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6635 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6636 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6637 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6638 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6639 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6640 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6641 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6642 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6643 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);