1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
35 #include <linux/clocksource.h>
36 #include <linux/interrupt.h>
37 #include <linux/kvm.h>
39 #include <linux/vmalloc.h>
40 #include <linux/export.h>
41 #include <linux/moduleparam.h>
42 #include <linux/mman.h>
43 #include <linux/highmem.h>
44 #include <linux/iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <linux/sched/stat.h>
58 #include <linux/sched/isolation.h>
59 #include <linux/mem_encrypt.h>
60 #include <linux/entry-kvm.h>
61 #include <linux/suspend.h>
63 #include <trace/events/kvm.h>
65 #include <asm/debugreg.h>
70 #include <linux/kernel_stat.h>
71 #include <asm/fpu/api.h>
72 #include <asm/fpu/xcr.h>
73 #include <asm/fpu/xstate.h>
74 #include <asm/pvclock.h>
75 #include <asm/div64.h>
76 #include <asm/irq_remapping.h>
77 #include <asm/mshyperv.h>
78 #include <asm/hypervisor.h>
79 #include <asm/tlbflush.h>
80 #include <asm/intel_pt.h>
81 #include <asm/emulate_prefix.h>
83 #include <clocksource/hyperv_timer.h>
85 #define CREATE_TRACE_POINTS
88 #define MAX_IO_MSRS 256
89 #define KVM_MAX_MCE_BANKS 32
91 struct kvm_caps kvm_caps __read_mostly = {
92 .supported_mce_cap = MCG_CTL_P | MCG_SER_P,
94 EXPORT_SYMBOL_GPL(kvm_caps);
96 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
98 #define emul_to_vcpu(ctxt) \
99 ((struct kvm_vcpu *)(ctxt)->vcpu)
102 * - enable syscall per default because its emulated by KVM
103 * - enable LME and LMA per default on 64 bit KVM
107 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
109 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
112 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
114 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
116 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
118 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
119 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
121 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
122 static void process_nmi(struct kvm_vcpu *vcpu);
123 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
124 static void store_regs(struct kvm_vcpu *vcpu);
125 static int sync_regs(struct kvm_vcpu *vcpu);
126 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
128 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
129 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
131 struct kvm_x86_ops kvm_x86_ops __read_mostly;
133 #define KVM_X86_OP(func) \
134 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
135 *(((struct kvm_x86_ops *)0)->func));
136 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
137 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
138 #include <asm/kvm-x86-ops.h>
139 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
140 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
142 static bool __read_mostly ignore_msrs = 0;
143 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
145 bool __read_mostly report_ignored_msrs = true;
146 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
147 EXPORT_SYMBOL_GPL(report_ignored_msrs);
149 unsigned int min_timer_period_us = 200;
150 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
152 static bool __read_mostly kvmclock_periodic_sync = true;
153 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
155 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
156 static u32 __read_mostly tsc_tolerance_ppm = 250;
157 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
160 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
161 * adaptive tuning starting from default advancement of 1000ns. '0' disables
162 * advancement entirely. Any other value is used as-is and disables adaptive
163 * tuning, i.e. allows privileged userspace to set an exact advancement time.
165 static int __read_mostly lapic_timer_advance_ns = -1;
166 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
168 static bool __read_mostly vector_hashing = true;
169 module_param(vector_hashing, bool, S_IRUGO);
171 bool __read_mostly enable_vmware_backdoor = false;
172 module_param(enable_vmware_backdoor, bool, S_IRUGO);
173 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
176 * Flags to manipulate forced emulation behavior (any non-zero value will
177 * enable forced emulation).
179 #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1)
180 static int __read_mostly force_emulation_prefix;
181 module_param(force_emulation_prefix, int, 0644);
183 int __read_mostly pi_inject_timer = -1;
184 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
186 /* Enable/disable PMU virtualization */
187 bool __read_mostly enable_pmu = true;
188 EXPORT_SYMBOL_GPL(enable_pmu);
189 module_param(enable_pmu, bool, 0444);
191 bool __read_mostly eager_page_split = true;
192 module_param(eager_page_split, bool, 0644);
195 * Restoring the host value for MSRs that are only consumed when running in
196 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
197 * returns to userspace, i.e. the kernel can run with the guest's value.
199 #define KVM_MAX_NR_USER_RETURN_MSRS 16
201 struct kvm_user_return_msrs {
202 struct user_return_notifier urn;
204 struct kvm_user_return_msr_values {
207 } values[KVM_MAX_NR_USER_RETURN_MSRS];
210 u32 __read_mostly kvm_nr_uret_msrs;
211 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
212 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
213 static struct kvm_user_return_msrs __percpu *user_return_msrs;
215 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
216 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
217 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
218 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
220 u64 __read_mostly host_efer;
221 EXPORT_SYMBOL_GPL(host_efer);
223 bool __read_mostly allow_smaller_maxphyaddr = 0;
224 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
226 bool __read_mostly enable_apicv = true;
227 EXPORT_SYMBOL_GPL(enable_apicv);
229 u64 __read_mostly host_xss;
230 EXPORT_SYMBOL_GPL(host_xss);
232 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
233 KVM_GENERIC_VM_STATS(),
234 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
235 STATS_DESC_COUNTER(VM, mmu_pte_write),
236 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
237 STATS_DESC_COUNTER(VM, mmu_flooded),
238 STATS_DESC_COUNTER(VM, mmu_recycled),
239 STATS_DESC_COUNTER(VM, mmu_cache_miss),
240 STATS_DESC_ICOUNTER(VM, mmu_unsync),
241 STATS_DESC_ICOUNTER(VM, pages_4k),
242 STATS_DESC_ICOUNTER(VM, pages_2m),
243 STATS_DESC_ICOUNTER(VM, pages_1g),
244 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
245 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
246 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
249 const struct kvm_stats_header kvm_vm_stats_header = {
250 .name_size = KVM_STATS_NAME_SIZE,
251 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
252 .id_offset = sizeof(struct kvm_stats_header),
253 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
254 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
255 sizeof(kvm_vm_stats_desc),
258 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
259 KVM_GENERIC_VCPU_STATS(),
260 STATS_DESC_COUNTER(VCPU, pf_taken),
261 STATS_DESC_COUNTER(VCPU, pf_fixed),
262 STATS_DESC_COUNTER(VCPU, pf_emulate),
263 STATS_DESC_COUNTER(VCPU, pf_spurious),
264 STATS_DESC_COUNTER(VCPU, pf_fast),
265 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created),
266 STATS_DESC_COUNTER(VCPU, pf_guest),
267 STATS_DESC_COUNTER(VCPU, tlb_flush),
268 STATS_DESC_COUNTER(VCPU, invlpg),
269 STATS_DESC_COUNTER(VCPU, exits),
270 STATS_DESC_COUNTER(VCPU, io_exits),
271 STATS_DESC_COUNTER(VCPU, mmio_exits),
272 STATS_DESC_COUNTER(VCPU, signal_exits),
273 STATS_DESC_COUNTER(VCPU, irq_window_exits),
274 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
275 STATS_DESC_COUNTER(VCPU, l1d_flush),
276 STATS_DESC_COUNTER(VCPU, halt_exits),
277 STATS_DESC_COUNTER(VCPU, request_irq_exits),
278 STATS_DESC_COUNTER(VCPU, irq_exits),
279 STATS_DESC_COUNTER(VCPU, host_state_reload),
280 STATS_DESC_COUNTER(VCPU, fpu_reload),
281 STATS_DESC_COUNTER(VCPU, insn_emulation),
282 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
283 STATS_DESC_COUNTER(VCPU, hypercalls),
284 STATS_DESC_COUNTER(VCPU, irq_injections),
285 STATS_DESC_COUNTER(VCPU, nmi_injections),
286 STATS_DESC_COUNTER(VCPU, req_event),
287 STATS_DESC_COUNTER(VCPU, nested_run),
288 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
289 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
290 STATS_DESC_COUNTER(VCPU, preemption_reported),
291 STATS_DESC_COUNTER(VCPU, preemption_other),
292 STATS_DESC_IBOOLEAN(VCPU, guest_mode),
293 STATS_DESC_COUNTER(VCPU, notify_window_exits),
296 const struct kvm_stats_header kvm_vcpu_stats_header = {
297 .name_size = KVM_STATS_NAME_SIZE,
298 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
299 .id_offset = sizeof(struct kvm_stats_header),
300 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
301 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
302 sizeof(kvm_vcpu_stats_desc),
305 u64 __read_mostly host_xcr0;
307 static struct kmem_cache *x86_emulator_cache;
310 * When called, it means the previous get/set msr reached an invalid msr.
311 * Return true if we want to ignore/silent this failed msr access.
313 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
315 const char *op = write ? "wrmsr" : "rdmsr";
318 if (report_ignored_msrs)
319 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
324 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
330 static struct kmem_cache *kvm_alloc_emulator_cache(void)
332 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
333 unsigned int size = sizeof(struct x86_emulate_ctxt);
335 return kmem_cache_create_usercopy("x86_emulator", size,
336 __alignof__(struct x86_emulate_ctxt),
337 SLAB_ACCOUNT, useroffset,
338 size - useroffset, NULL);
341 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
343 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
346 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
347 vcpu->arch.apf.gfns[i] = ~0;
350 static void kvm_on_user_return(struct user_return_notifier *urn)
353 struct kvm_user_return_msrs *msrs
354 = container_of(urn, struct kvm_user_return_msrs, urn);
355 struct kvm_user_return_msr_values *values;
359 * Disabling irqs at this point since the following code could be
360 * interrupted and executed through kvm_arch_hardware_disable()
362 local_irq_save(flags);
363 if (msrs->registered) {
364 msrs->registered = false;
365 user_return_notifier_unregister(urn);
367 local_irq_restore(flags);
368 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
369 values = &msrs->values[slot];
370 if (values->host != values->curr) {
371 wrmsrl(kvm_uret_msrs_list[slot], values->host);
372 values->curr = values->host;
377 static int kvm_probe_user_return_msr(u32 msr)
383 ret = rdmsrl_safe(msr, &val);
386 ret = wrmsrl_safe(msr, val);
392 int kvm_add_user_return_msr(u32 msr)
394 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
396 if (kvm_probe_user_return_msr(msr))
399 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
400 return kvm_nr_uret_msrs++;
402 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
404 int kvm_find_user_return_msr(u32 msr)
408 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
409 if (kvm_uret_msrs_list[i] == msr)
414 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
416 static void kvm_user_return_msr_cpu_online(void)
418 unsigned int cpu = smp_processor_id();
419 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
423 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
424 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
425 msrs->values[i].host = value;
426 msrs->values[i].curr = value;
430 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
432 unsigned int cpu = smp_processor_id();
433 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
436 value = (value & mask) | (msrs->values[slot].host & ~mask);
437 if (value == msrs->values[slot].curr)
439 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
443 msrs->values[slot].curr = value;
444 if (!msrs->registered) {
445 msrs->urn.on_user_return = kvm_on_user_return;
446 user_return_notifier_register(&msrs->urn);
447 msrs->registered = true;
451 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
453 static void drop_user_return_notifiers(void)
455 unsigned int cpu = smp_processor_id();
456 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
458 if (msrs->registered)
459 kvm_on_user_return(&msrs->urn);
462 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
464 return vcpu->arch.apic_base;
467 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
469 return kvm_apic_mode(kvm_get_apic_base(vcpu));
471 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
473 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
475 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
476 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
477 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
478 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
480 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
482 if (!msr_info->host_initiated) {
483 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
485 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
489 kvm_lapic_set_base(vcpu, msr_info->data);
490 kvm_recalculate_apic_map(vcpu->kvm);
495 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
497 * Hardware virtualization extension instructions may fault if a reboot turns
498 * off virtualization while processes are running. Usually after catching the
499 * fault we just panic; during reboot instead the instruction is ignored.
501 noinstr void kvm_spurious_fault(void)
503 /* Fault while not rebooting. We want the trace. */
504 BUG_ON(!kvm_rebooting);
506 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
508 #define EXCPT_BENIGN 0
509 #define EXCPT_CONTRIBUTORY 1
512 static int exception_class(int vector)
522 return EXCPT_CONTRIBUTORY;
529 #define EXCPT_FAULT 0
531 #define EXCPT_ABORT 2
532 #define EXCPT_INTERRUPT 3
535 static int exception_type(int vector)
539 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
540 return EXCPT_INTERRUPT;
545 * #DBs can be trap-like or fault-like, the caller must check other CPU
546 * state, e.g. DR6, to determine whether a #DB is a trap or fault.
548 if (mask & (1 << DB_VECTOR))
551 if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR)))
554 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
557 /* Reserved exceptions will result in fault */
561 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
562 struct kvm_queued_exception *ex)
564 if (!ex->has_payload)
567 switch (ex->vector) {
570 * "Certain debug exceptions may clear bit 0-3. The
571 * remaining contents of the DR6 register are never
572 * cleared by the processor".
574 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
576 * In order to reflect the #DB exception payload in guest
577 * dr6, three components need to be considered: active low
578 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
580 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
581 * In the target guest dr6:
582 * FIXED_1 bits should always be set.
583 * Active low bits should be cleared if 1-setting in payload.
584 * Active high bits should be set if 1-setting in payload.
586 * Note, the payload is compatible with the pending debug
587 * exceptions/exit qualification under VMX, that active_low bits
588 * are active high in payload.
589 * So they need to be flipped for DR6.
591 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
592 vcpu->arch.dr6 |= ex->payload;
593 vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW;
596 * The #DB payload is defined as compatible with the 'pending
597 * debug exceptions' field under VMX, not DR6. While bit 12 is
598 * defined in the 'pending debug exceptions' field (enabled
599 * breakpoint), it is reserved and must be zero in DR6.
601 vcpu->arch.dr6 &= ~BIT(12);
604 vcpu->arch.cr2 = ex->payload;
608 ex->has_payload = false;
611 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
613 static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector,
614 bool has_error_code, u32 error_code,
615 bool has_payload, unsigned long payload)
617 struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit;
620 ex->injected = false;
622 ex->has_error_code = has_error_code;
623 ex->error_code = error_code;
624 ex->has_payload = has_payload;
625 ex->payload = payload;
628 /* Forcibly leave the nested mode in cases like a vCPU reset */
629 static void kvm_leave_nested(struct kvm_vcpu *vcpu)
631 kvm_x86_ops.nested_ops->leave_nested(vcpu);
634 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
635 unsigned nr, bool has_error, u32 error_code,
636 bool has_payload, unsigned long payload, bool reinject)
641 kvm_make_request(KVM_REQ_EVENT, vcpu);
644 * If the exception is destined for L2 and isn't being reinjected,
645 * morph it to a VM-Exit if L1 wants to intercept the exception. A
646 * previously injected exception is not checked because it was checked
647 * when it was original queued, and re-checking is incorrect if _L1_
648 * injected the exception, in which case it's exempt from interception.
650 if (!reinject && is_guest_mode(vcpu) &&
651 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) {
652 kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code,
653 has_payload, payload);
657 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
661 * On VM-Entry, an exception can be pending if and only
662 * if event injection was blocked by nested_run_pending.
663 * In that case, however, vcpu_enter_guest() requests an
664 * immediate exit, and the guest shouldn't proceed far
665 * enough to need reinjection.
667 WARN_ON_ONCE(kvm_is_exception_pending(vcpu));
668 vcpu->arch.exception.injected = true;
669 if (WARN_ON_ONCE(has_payload)) {
671 * A reinjected event has already
672 * delivered its payload.
678 vcpu->arch.exception.pending = true;
679 vcpu->arch.exception.injected = false;
681 vcpu->arch.exception.has_error_code = has_error;
682 vcpu->arch.exception.vector = nr;
683 vcpu->arch.exception.error_code = error_code;
684 vcpu->arch.exception.has_payload = has_payload;
685 vcpu->arch.exception.payload = payload;
686 if (!is_guest_mode(vcpu))
687 kvm_deliver_exception_payload(vcpu,
688 &vcpu->arch.exception);
692 /* to check exception */
693 prev_nr = vcpu->arch.exception.vector;
694 if (prev_nr == DF_VECTOR) {
695 /* triple fault -> shutdown */
696 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
699 class1 = exception_class(prev_nr);
700 class2 = exception_class(nr);
701 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) ||
702 (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
704 * Synthesize #DF. Clear the previously injected or pending
705 * exception so as not to incorrectly trigger shutdown.
707 vcpu->arch.exception.injected = false;
708 vcpu->arch.exception.pending = false;
710 kvm_queue_exception_e(vcpu, DF_VECTOR, 0);
712 /* replace previous exception with a new one in a hope
713 that instruction re-execution will regenerate lost
719 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
721 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
723 EXPORT_SYMBOL_GPL(kvm_queue_exception);
725 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
727 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
729 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
731 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
732 unsigned long payload)
734 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
736 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
738 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
739 u32 error_code, unsigned long payload)
741 kvm_multiple_exception(vcpu, nr, true, error_code,
742 true, payload, false);
745 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
748 kvm_inject_gp(vcpu, 0);
750 return kvm_skip_emulated_instruction(vcpu);
754 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
756 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
759 kvm_inject_gp(vcpu, 0);
763 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
764 EMULTYPE_COMPLETE_USER_EXIT);
767 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
769 ++vcpu->stat.pf_guest;
772 * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of
773 * whether or not L1 wants to intercept "regular" #PF.
775 if (is_guest_mode(vcpu) && fault->async_page_fault)
776 kvm_queue_exception_vmexit(vcpu, PF_VECTOR,
777 true, fault->error_code,
778 true, fault->address);
780 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
784 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
785 struct x86_exception *fault)
787 struct kvm_mmu *fault_mmu;
788 WARN_ON_ONCE(fault->vector != PF_VECTOR);
790 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
794 * Invalidate the TLB entry for the faulting address, if it exists,
795 * else the access will fault indefinitely (and to emulate hardware).
797 if ((fault->error_code & PFERR_PRESENT_MASK) &&
798 !(fault->error_code & PFERR_RSVD_MASK))
799 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
800 fault_mmu->root.hpa);
802 fault_mmu->inject_page_fault(vcpu, fault);
804 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
806 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
808 atomic_inc(&vcpu->arch.nmi_queued);
809 kvm_make_request(KVM_REQ_NMI, vcpu);
812 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
814 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
816 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
818 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
820 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
822 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
825 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
826 * a #GP and return false.
828 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
830 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
832 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
836 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
838 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
841 kvm_queue_exception(vcpu, UD_VECTOR);
844 EXPORT_SYMBOL_GPL(kvm_require_dr);
846 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
848 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
852 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
854 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
856 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
857 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
861 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
864 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
867 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
868 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
869 if (real_gpa == INVALID_GPA)
872 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
873 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
874 cr3 & GENMASK(11, 5), sizeof(pdpte));
878 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
879 if ((pdpte[i] & PT_PRESENT_MASK) &&
880 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
886 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
887 * Shadow page roots need to be reconstructed instead.
889 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
890 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
892 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
893 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
894 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
895 vcpu->arch.pdptrs_from_userspace = false;
899 EXPORT_SYMBOL_GPL(load_pdptrs);
901 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
903 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
904 kvm_clear_async_pf_completion_queue(vcpu);
905 kvm_async_pf_hash_reset(vcpu);
908 * Clearing CR0.PG is defined to flush the TLB from the guest's
911 if (!(cr0 & X86_CR0_PG))
912 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
915 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
916 kvm_mmu_reset_context(vcpu);
918 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
919 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
920 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
921 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
923 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
925 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
927 unsigned long old_cr0 = kvm_read_cr0(vcpu);
932 if (cr0 & 0xffffffff00000000UL)
936 cr0 &= ~CR0_RESERVED_BITS;
938 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
941 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
945 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
946 (cr0 & X86_CR0_PG)) {
951 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
956 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
957 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
958 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
961 if (!(cr0 & X86_CR0_PG) &&
962 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)))
965 static_call(kvm_x86_set_cr0)(vcpu, cr0);
967 kvm_post_set_cr0(vcpu, old_cr0, cr0);
971 EXPORT_SYMBOL_GPL(kvm_set_cr0);
973 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
975 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
977 EXPORT_SYMBOL_GPL(kvm_lmsw);
979 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
981 if (vcpu->arch.guest_state_protected)
984 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
986 if (vcpu->arch.xcr0 != host_xcr0)
987 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
989 if (vcpu->arch.xsaves_enabled &&
990 vcpu->arch.ia32_xss != host_xss)
991 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
994 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
995 if (static_cpu_has(X86_FEATURE_PKU) &&
996 vcpu->arch.pkru != vcpu->arch.host_pkru &&
997 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
998 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)))
999 write_pkru(vcpu->arch.pkru);
1000 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
1002 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
1004 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
1006 if (vcpu->arch.guest_state_protected)
1009 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
1010 if (static_cpu_has(X86_FEATURE_PKU) &&
1011 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1012 kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) {
1013 vcpu->arch.pkru = rdpkru();
1014 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
1015 write_pkru(vcpu->arch.host_pkru);
1017 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
1019 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
1021 if (vcpu->arch.xcr0 != host_xcr0)
1022 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
1024 if (vcpu->arch.xsaves_enabled &&
1025 vcpu->arch.ia32_xss != host_xss)
1026 wrmsrl(MSR_IA32_XSS, host_xss);
1030 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1032 #ifdef CONFIG_X86_64
1033 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1035 return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC;
1039 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1042 u64 old_xcr0 = vcpu->arch.xcr0;
1045 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1046 if (index != XCR_XFEATURE_ENABLED_MASK)
1048 if (!(xcr0 & XFEATURE_MASK_FP))
1050 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1054 * Do not allow the guest to set bits that we do not support
1055 * saving. However, xcr0 bit 0 is always set, even if the
1056 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1058 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
1059 if (xcr0 & ~valid_bits)
1062 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1063 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1066 if (xcr0 & XFEATURE_MASK_AVX512) {
1067 if (!(xcr0 & XFEATURE_MASK_YMM))
1069 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1073 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1074 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1077 vcpu->arch.xcr0 = xcr0;
1079 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1080 kvm_update_cpuid_runtime(vcpu);
1084 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1086 /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
1087 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1088 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1089 kvm_inject_gp(vcpu, 0);
1093 return kvm_skip_emulated_instruction(vcpu);
1095 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1097 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1099 if (cr4 & cr4_reserved_bits)
1102 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1107 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4);
1109 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1111 return __kvm_is_valid_cr4(vcpu, cr4) &&
1112 static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1115 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1117 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1118 kvm_mmu_reset_context(vcpu);
1121 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1122 * according to the SDM; however, stale prev_roots could be reused
1123 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1124 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1125 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1129 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1130 kvm_mmu_unload(vcpu);
1133 * The TLB has to be flushed for all PCIDs if any of the following
1134 * (architecturally required) changes happen:
1135 * - CR4.PCIDE is changed from 1 to 0
1136 * - CR4.PGE is toggled
1138 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1140 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1141 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1142 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1145 * The TLB has to be flushed for the current PCID if any of the
1146 * following (architecturally required) changes happen:
1147 * - CR4.SMEP is changed from 0 to 1
1148 * - CR4.PAE is toggled
1150 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1151 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1152 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1155 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1157 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1159 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1161 if (!kvm_is_valid_cr4(vcpu, cr4))
1164 if (is_long_mode(vcpu)) {
1165 if (!(cr4 & X86_CR4_PAE))
1167 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1169 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1170 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1171 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1174 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1175 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1178 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1179 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1183 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1185 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1189 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1191 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1193 struct kvm_mmu *mmu = vcpu->arch.mmu;
1194 unsigned long roots_to_free = 0;
1198 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1199 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1200 * also via the emulator. KVM's TDP page tables are not in the scope of
1201 * the invalidation, but the guest's TLB entries need to be flushed as
1202 * the CPU may have cached entries in its TLB for the target PCID.
1204 if (unlikely(tdp_enabled)) {
1205 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1210 * If neither the current CR3 nor any of the prev_roots use the given
1211 * PCID, then nothing needs to be done here because a resync will
1212 * happen anyway before switching to any other CR3.
1214 if (kvm_get_active_pcid(vcpu) == pcid) {
1215 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1216 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1220 * If PCID is disabled, there is no need to free prev_roots even if the
1221 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1224 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
1227 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1228 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1229 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1231 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1234 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1236 bool skip_tlb_flush = false;
1237 unsigned long pcid = 0;
1238 #ifdef CONFIG_X86_64
1239 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1242 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1243 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1244 pcid = cr3 & X86_CR3_PCID_MASK;
1248 /* PDPTRs are always reloaded for PAE paging. */
1249 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1250 goto handle_tlb_flush;
1253 * Do not condition the GPA check on long mode, this helper is used to
1254 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1255 * the current vCPU mode is accurate.
1257 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1260 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1263 if (cr3 != kvm_read_cr3(vcpu))
1264 kvm_mmu_new_pgd(vcpu, cr3);
1266 vcpu->arch.cr3 = cr3;
1267 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1268 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1272 * A load of CR3 that flushes the TLB flushes only the current PCID,
1273 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1274 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1275 * and it's impossible to use a non-zero PCID when PCID is disabled,
1276 * i.e. only PCID=0 can be relevant.
1278 if (!skip_tlb_flush)
1279 kvm_invalidate_pcid(vcpu, pcid);
1283 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1285 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1287 if (cr8 & CR8_RESERVED_BITS)
1289 if (lapic_in_kernel(vcpu))
1290 kvm_lapic_set_tpr(vcpu, cr8);
1292 vcpu->arch.cr8 = cr8;
1295 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1297 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1299 if (lapic_in_kernel(vcpu))
1300 return kvm_lapic_get_cr8(vcpu);
1302 return vcpu->arch.cr8;
1304 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1306 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1310 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1311 for (i = 0; i < KVM_NR_DB_REGS; i++)
1312 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1316 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1320 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1321 dr7 = vcpu->arch.guest_debug_dr7;
1323 dr7 = vcpu->arch.dr7;
1324 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1325 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1326 if (dr7 & DR7_BP_EN_MASK)
1327 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1329 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1331 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1333 u64 fixed = DR6_FIXED_1;
1335 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1338 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1339 fixed |= DR6_BUS_LOCK;
1343 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1345 size_t size = ARRAY_SIZE(vcpu->arch.db);
1349 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1350 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1351 vcpu->arch.eff_db[dr] = val;
1355 if (!kvm_dr6_valid(val))
1357 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1361 if (!kvm_dr7_valid(val))
1363 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1364 kvm_update_dr7(vcpu);
1370 EXPORT_SYMBOL_GPL(kvm_set_dr);
1372 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1374 size_t size = ARRAY_SIZE(vcpu->arch.db);
1378 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1382 *val = vcpu->arch.dr6;
1386 *val = vcpu->arch.dr7;
1390 EXPORT_SYMBOL_GPL(kvm_get_dr);
1392 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1394 u32 ecx = kvm_rcx_read(vcpu);
1397 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1398 kvm_inject_gp(vcpu, 0);
1402 kvm_rax_write(vcpu, (u32)data);
1403 kvm_rdx_write(vcpu, data >> 32);
1404 return kvm_skip_emulated_instruction(vcpu);
1406 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1409 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1410 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1412 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1413 * extract the supported MSRs from the related const lists.
1414 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1415 * capabilities of the host cpu. This capabilities test skips MSRs that are
1416 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1417 * may depend on host virtualization features rather than host cpu features.
1420 static const u32 msrs_to_save_all[] = {
1421 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1423 #ifdef CONFIG_X86_64
1424 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1426 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1427 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1429 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1430 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1431 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1432 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1433 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1434 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1435 MSR_IA32_UMWAIT_CONTROL,
1437 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1438 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1439 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1440 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1441 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1443 /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
1444 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1445 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1446 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1447 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1448 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1449 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1450 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1451 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1453 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1454 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1456 /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
1457 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1458 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1459 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1460 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1462 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1465 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1466 static unsigned num_msrs_to_save;
1468 static const u32 emulated_msrs_all[] = {
1469 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1470 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1471 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1472 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1473 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1474 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1475 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1477 HV_X64_MSR_VP_INDEX,
1478 HV_X64_MSR_VP_RUNTIME,
1479 HV_X64_MSR_SCONTROL,
1480 HV_X64_MSR_STIMER0_CONFIG,
1481 HV_X64_MSR_VP_ASSIST_PAGE,
1482 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1483 HV_X64_MSR_TSC_EMULATION_STATUS,
1484 HV_X64_MSR_SYNDBG_OPTIONS,
1485 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1486 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1487 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1489 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1490 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1492 MSR_IA32_TSC_ADJUST,
1493 MSR_IA32_TSC_DEADLINE,
1494 MSR_IA32_ARCH_CAPABILITIES,
1495 MSR_IA32_PERF_CAPABILITIES,
1496 MSR_IA32_MISC_ENABLE,
1497 MSR_IA32_MCG_STATUS,
1499 MSR_IA32_MCG_EXT_CTL,
1503 MSR_MISC_FEATURES_ENABLES,
1504 MSR_AMD64_VIRT_SPEC_CTRL,
1505 MSR_AMD64_TSC_RATIO,
1510 * The following list leaves out MSRs whose values are determined
1511 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1512 * We always support the "true" VMX control MSRs, even if the host
1513 * processor does not, so I am putting these registers here rather
1514 * than in msrs_to_save_all.
1517 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1518 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1519 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1520 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1522 MSR_IA32_VMX_CR0_FIXED0,
1523 MSR_IA32_VMX_CR4_FIXED0,
1524 MSR_IA32_VMX_VMCS_ENUM,
1525 MSR_IA32_VMX_PROCBASED_CTLS2,
1526 MSR_IA32_VMX_EPT_VPID_CAP,
1527 MSR_IA32_VMX_VMFUNC,
1530 MSR_KVM_POLL_CONTROL,
1533 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1534 static unsigned num_emulated_msrs;
1537 * List of msr numbers which are used to expose MSR-based features that
1538 * can be used by a hypervisor to validate requested CPU features.
1540 static const u32 msr_based_features_all[] = {
1542 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1543 MSR_IA32_VMX_PINBASED_CTLS,
1544 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1545 MSR_IA32_VMX_PROCBASED_CTLS,
1546 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1547 MSR_IA32_VMX_EXIT_CTLS,
1548 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1549 MSR_IA32_VMX_ENTRY_CTLS,
1551 MSR_IA32_VMX_CR0_FIXED0,
1552 MSR_IA32_VMX_CR0_FIXED1,
1553 MSR_IA32_VMX_CR4_FIXED0,
1554 MSR_IA32_VMX_CR4_FIXED1,
1555 MSR_IA32_VMX_VMCS_ENUM,
1556 MSR_IA32_VMX_PROCBASED_CTLS2,
1557 MSR_IA32_VMX_EPT_VPID_CAP,
1558 MSR_IA32_VMX_VMFUNC,
1562 MSR_IA32_ARCH_CAPABILITIES,
1563 MSR_IA32_PERF_CAPABILITIES,
1566 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1567 static unsigned int num_msr_based_features;
1570 * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM
1571 * does not yet virtualize. These include:
1572 * 10 - MISC_PACKAGE_CTRLS
1573 * 11 - ENERGY_FILTERING_CTL
1575 * 18 - FB_CLEAR_CTRL
1576 * 21 - XAPIC_DISABLE_STATUS
1577 * 23 - OVERCLOCKING_STATUS
1580 #define KVM_SUPPORTED_ARCH_CAP \
1581 (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \
1582 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \
1583 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \
1584 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \
1585 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO)
1587 static u64 kvm_get_arch_capabilities(void)
1591 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
1592 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1593 data &= KVM_SUPPORTED_ARCH_CAP;
1597 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1598 * the nested hypervisor runs with NX huge pages. If it is not,
1599 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1600 * L1 guests, so it need not worry about its own (L2) guests.
1602 data |= ARCH_CAP_PSCHANGE_MC_NO;
1605 * If we're doing cache flushes (either "always" or "cond")
1606 * we will do one whenever the guest does a vmlaunch/vmresume.
1607 * If an outer hypervisor is doing the cache flush for us
1608 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1609 * capability to the guest too, and if EPT is disabled we're not
1610 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1611 * require a nested hypervisor to do a flush of its own.
1613 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1614 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1616 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1617 data |= ARCH_CAP_RDCL_NO;
1618 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1619 data |= ARCH_CAP_SSB_NO;
1620 if (!boot_cpu_has_bug(X86_BUG_MDS))
1621 data |= ARCH_CAP_MDS_NO;
1623 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1625 * If RTM=0 because the kernel has disabled TSX, the host might
1626 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1627 * and therefore knows that there cannot be TAA) but keep
1628 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1629 * and we want to allow migrating those guests to tsx=off hosts.
1631 data &= ~ARCH_CAP_TAA_NO;
1632 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1633 data |= ARCH_CAP_TAA_NO;
1636 * Nothing to do here; we emulate TSX_CTRL if present on the
1637 * host so the guest can choose between disabling TSX or
1638 * using VERW to clear CPU buffers.
1645 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1647 switch (msr->index) {
1648 case MSR_IA32_ARCH_CAPABILITIES:
1649 msr->data = kvm_get_arch_capabilities();
1651 case MSR_IA32_PERF_CAPABILITIES:
1652 msr->data = kvm_caps.supported_perf_cap;
1654 case MSR_IA32_UCODE_REV:
1655 rdmsrl_safe(msr->index, &msr->data);
1658 return static_call(kvm_x86_get_msr_feature)(msr);
1663 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1665 struct kvm_msr_entry msr;
1669 r = kvm_get_msr_feature(&msr);
1671 if (r == KVM_MSR_RET_INVALID) {
1672 /* Unconditionally clear the output for simplicity */
1674 if (kvm_msr_ignored_check(index, 0, false))
1686 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1688 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1691 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1694 if (efer & (EFER_LME | EFER_LMA) &&
1695 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1698 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1704 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1706 if (efer & efer_reserved_bits)
1709 return __kvm_valid_efer(vcpu, efer);
1711 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1713 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1715 u64 old_efer = vcpu->arch.efer;
1716 u64 efer = msr_info->data;
1719 if (efer & efer_reserved_bits)
1722 if (!msr_info->host_initiated) {
1723 if (!__kvm_valid_efer(vcpu, efer))
1726 if (is_paging(vcpu) &&
1727 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1732 efer |= vcpu->arch.efer & EFER_LMA;
1734 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1740 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1741 kvm_mmu_reset_context(vcpu);
1746 void kvm_enable_efer_bits(u64 mask)
1748 efer_reserved_bits &= ~mask;
1750 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1752 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1754 struct kvm_x86_msr_filter *msr_filter;
1755 struct msr_bitmap_range *ranges;
1756 struct kvm *kvm = vcpu->kvm;
1761 /* x2APIC MSRs do not support filtering. */
1762 if (index >= 0x800 && index <= 0x8ff)
1765 idx = srcu_read_lock(&kvm->srcu);
1767 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1773 allowed = msr_filter->default_allow;
1774 ranges = msr_filter->ranges;
1776 for (i = 0; i < msr_filter->count; i++) {
1777 u32 start = ranges[i].base;
1778 u32 end = start + ranges[i].nmsrs;
1779 u32 flags = ranges[i].flags;
1780 unsigned long *bitmap = ranges[i].bitmap;
1782 if ((index >= start) && (index < end) && (flags & type)) {
1783 allowed = !!test_bit(index - start, bitmap);
1789 srcu_read_unlock(&kvm->srcu, idx);
1793 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1796 * Write @data into the MSR specified by @index. Select MSR specific fault
1797 * checks are bypassed if @host_initiated is %true.
1798 * Returns 0 on success, non-0 otherwise.
1799 * Assumes vcpu_load() was already called.
1801 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1802 bool host_initiated)
1804 struct msr_data msr;
1809 case MSR_KERNEL_GS_BASE:
1812 if (is_noncanonical_address(data, vcpu))
1815 case MSR_IA32_SYSENTER_EIP:
1816 case MSR_IA32_SYSENTER_ESP:
1818 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1819 * non-canonical address is written on Intel but not on
1820 * AMD (which ignores the top 32-bits, because it does
1821 * not implement 64-bit SYSENTER).
1823 * 64-bit code should hence be able to write a non-canonical
1824 * value on AMD. Making the address canonical ensures that
1825 * vmentry does not fail on Intel after writing a non-canonical
1826 * value, and that something deterministic happens if the guest
1827 * invokes 64-bit SYSENTER.
1829 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1832 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1835 if (!host_initiated &&
1836 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1837 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1841 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1842 * incomplete and conflicting architectural behavior. Current
1843 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1844 * reserved and always read as zeros. Enforce Intel's reserved
1845 * bits check if and only if the guest CPU is Intel, and clear
1846 * the bits in all other cases. This ensures cross-vendor
1847 * migration will provide consistent behavior for the guest.
1849 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1858 msr.host_initiated = host_initiated;
1860 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1863 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1864 u32 index, u64 data, bool host_initiated)
1866 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1868 if (ret == KVM_MSR_RET_INVALID)
1869 if (kvm_msr_ignored_check(index, data, true))
1876 * Read the MSR specified by @index into @data. Select MSR specific fault
1877 * checks are bypassed if @host_initiated is %true.
1878 * Returns 0 on success, non-0 otherwise.
1879 * Assumes vcpu_load() was already called.
1881 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1882 bool host_initiated)
1884 struct msr_data msr;
1889 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1892 if (!host_initiated &&
1893 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1894 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1900 msr.host_initiated = host_initiated;
1902 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1908 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1909 u32 index, u64 *data, bool host_initiated)
1911 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1913 if (ret == KVM_MSR_RET_INVALID) {
1914 /* Unconditionally clear *data for simplicity */
1916 if (kvm_msr_ignored_check(index, 0, false))
1923 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1925 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1926 return KVM_MSR_RET_FILTERED;
1927 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1930 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1932 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1933 return KVM_MSR_RET_FILTERED;
1934 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1937 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1939 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1941 EXPORT_SYMBOL_GPL(kvm_get_msr);
1943 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1945 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1947 EXPORT_SYMBOL_GPL(kvm_set_msr);
1949 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1951 if (!vcpu->run->msr.error) {
1952 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1953 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1957 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1959 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
1962 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1964 complete_userspace_rdmsr(vcpu);
1965 return complete_emulated_msr_access(vcpu);
1968 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
1970 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
1973 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
1975 complete_userspace_rdmsr(vcpu);
1976 return complete_fast_msr_access(vcpu);
1979 static u64 kvm_msr_reason(int r)
1982 case KVM_MSR_RET_INVALID:
1983 return KVM_MSR_EXIT_REASON_UNKNOWN;
1984 case KVM_MSR_RET_FILTERED:
1985 return KVM_MSR_EXIT_REASON_FILTER;
1987 return KVM_MSR_EXIT_REASON_INVAL;
1991 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1992 u32 exit_reason, u64 data,
1993 int (*completion)(struct kvm_vcpu *vcpu),
1996 u64 msr_reason = kvm_msr_reason(r);
1998 /* Check if the user wanted to know about this MSR fault */
1999 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
2002 vcpu->run->exit_reason = exit_reason;
2003 vcpu->run->msr.error = 0;
2004 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
2005 vcpu->run->msr.reason = msr_reason;
2006 vcpu->run->msr.index = index;
2007 vcpu->run->msr.data = data;
2008 vcpu->arch.complete_userspace_io = completion;
2013 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
2015 u32 ecx = kvm_rcx_read(vcpu);
2019 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
2022 trace_kvm_msr_read(ecx, data);
2024 kvm_rax_write(vcpu, data & -1u);
2025 kvm_rdx_write(vcpu, (data >> 32) & -1u);
2027 /* MSR read failed? See if we should ask user space */
2028 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
2029 complete_fast_rdmsr, r))
2031 trace_kvm_msr_read_ex(ecx);
2034 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2036 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
2038 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
2040 u32 ecx = kvm_rcx_read(vcpu);
2041 u64 data = kvm_read_edx_eax(vcpu);
2044 r = kvm_set_msr_with_filter(vcpu, ecx, data);
2047 trace_kvm_msr_write(ecx, data);
2049 /* MSR write failed? See if we should ask user space */
2050 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2051 complete_fast_msr_access, r))
2053 /* Signal all other negative errors to userspace */
2056 trace_kvm_msr_write_ex(ecx, data);
2059 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2061 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2063 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2065 return kvm_skip_emulated_instruction(vcpu);
2068 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2070 /* Treat an INVD instruction as a NOP and just skip it. */
2071 return kvm_emulate_as_nop(vcpu);
2073 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2075 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2077 kvm_queue_exception(vcpu, UD_VECTOR);
2080 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2083 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
2085 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) &&
2086 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT))
2087 return kvm_handle_invalid_op(vcpu);
2089 pr_warn_once("kvm: %s instruction emulated as NOP!\n", insn);
2090 return kvm_emulate_as_nop(vcpu);
2092 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2094 return kvm_emulate_monitor_mwait(vcpu, "MWAIT");
2096 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2098 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2100 return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
2102 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2104 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2106 xfer_to_guest_mode_prepare();
2107 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2108 xfer_to_guest_mode_work_pending();
2112 * The fast path for frequent and performance sensitive wrmsr emulation,
2113 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2114 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2115 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2116 * other cases which must be called after interrupts are enabled on the host.
2118 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2120 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2123 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2124 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2125 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2126 ((u32)(data >> 32) != X2APIC_BROADCAST))
2127 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2132 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2134 if (!kvm_can_use_hv_timer(vcpu))
2137 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2141 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2143 u32 msr = kvm_rcx_read(vcpu);
2145 fastpath_t ret = EXIT_FASTPATH_NONE;
2148 case APIC_BASE_MSR + (APIC_ICR >> 4):
2149 data = kvm_read_edx_eax(vcpu);
2150 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2151 kvm_skip_emulated_instruction(vcpu);
2152 ret = EXIT_FASTPATH_EXIT_HANDLED;
2155 case MSR_IA32_TSC_DEADLINE:
2156 data = kvm_read_edx_eax(vcpu);
2157 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2158 kvm_skip_emulated_instruction(vcpu);
2159 ret = EXIT_FASTPATH_REENTER_GUEST;
2166 if (ret != EXIT_FASTPATH_NONE)
2167 trace_kvm_msr_write(msr, data);
2171 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2174 * Adapt set_msr() to msr_io()'s calling convention
2176 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2178 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2181 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2183 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2186 #ifdef CONFIG_X86_64
2187 struct pvclock_clock {
2197 struct pvclock_gtod_data {
2200 struct pvclock_clock clock; /* extract of a clocksource struct */
2201 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2207 static struct pvclock_gtod_data pvclock_gtod_data;
2209 static void update_pvclock_gtod(struct timekeeper *tk)
2211 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2213 write_seqcount_begin(&vdata->seq);
2215 /* copy pvclock gtod data */
2216 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2217 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2218 vdata->clock.mask = tk->tkr_mono.mask;
2219 vdata->clock.mult = tk->tkr_mono.mult;
2220 vdata->clock.shift = tk->tkr_mono.shift;
2221 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2222 vdata->clock.offset = tk->tkr_mono.base;
2224 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2225 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2226 vdata->raw_clock.mask = tk->tkr_raw.mask;
2227 vdata->raw_clock.mult = tk->tkr_raw.mult;
2228 vdata->raw_clock.shift = tk->tkr_raw.shift;
2229 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2230 vdata->raw_clock.offset = tk->tkr_raw.base;
2232 vdata->wall_time_sec = tk->xtime_sec;
2234 vdata->offs_boot = tk->offs_boot;
2236 write_seqcount_end(&vdata->seq);
2239 static s64 get_kvmclock_base_ns(void)
2241 /* Count up from boot time, but with the frequency of the raw clock. */
2242 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2245 static s64 get_kvmclock_base_ns(void)
2247 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2248 return ktime_get_boottime_ns();
2252 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2256 struct pvclock_wall_clock wc;
2263 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2268 ++version; /* first time write, random junk */
2272 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2276 * The guest calculates current wall clock time by adding
2277 * system time (updated by kvm_guest_time_update below) to the
2278 * wall clock specified here. We do the reverse here.
2280 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2282 wc.nsec = do_div(wall_nsec, 1000000000);
2283 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2284 wc.version = version;
2286 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2289 wc_sec_hi = wall_nsec >> 32;
2290 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2291 &wc_sec_hi, sizeof(wc_sec_hi));
2295 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2298 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2299 bool old_msr, bool host_initiated)
2301 struct kvm_arch *ka = &vcpu->kvm->arch;
2303 if (vcpu->vcpu_id == 0 && !host_initiated) {
2304 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2305 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2307 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2310 vcpu->arch.time = system_time;
2311 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2313 /* we verify if the enable bit is set... */
2314 if (system_time & 1)
2315 kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL,
2316 sizeof(struct pvclock_vcpu_time_info));
2318 kvm_gpc_deactivate(&vcpu->arch.pv_time);
2323 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2325 do_shl32_div32(dividend, divisor);
2329 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2330 s8 *pshift, u32 *pmultiplier)
2338 scaled64 = scaled_hz;
2339 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2344 tps32 = (uint32_t)tps64;
2345 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2346 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2354 *pmultiplier = div_frac(scaled64, tps32);
2357 #ifdef CONFIG_X86_64
2358 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2361 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2362 static unsigned long max_tsc_khz;
2364 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2366 u64 v = (u64)khz * (1000000 + ppm);
2371 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2373 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2377 /* Guest TSC same frequency as host TSC? */
2379 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2383 /* TSC scaling supported? */
2384 if (!kvm_caps.has_tsc_control) {
2385 if (user_tsc_khz > tsc_khz) {
2386 vcpu->arch.tsc_catchup = 1;
2387 vcpu->arch.tsc_always_catchup = 1;
2390 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2395 /* TSC scaling required - calculate ratio */
2396 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
2397 user_tsc_khz, tsc_khz);
2399 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
2400 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2405 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2409 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2411 u32 thresh_lo, thresh_hi;
2412 int use_scaling = 0;
2414 /* tsc_khz can be zero if TSC calibration fails */
2415 if (user_tsc_khz == 0) {
2416 /* set tsc_scaling_ratio to a safe value */
2417 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2421 /* Compute a scale to convert nanoseconds in TSC cycles */
2422 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2423 &vcpu->arch.virtual_tsc_shift,
2424 &vcpu->arch.virtual_tsc_mult);
2425 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2428 * Compute the variation in TSC rate which is acceptable
2429 * within the range of tolerance and decide if the
2430 * rate being applied is within that bounds of the hardware
2431 * rate. If so, no scaling or compensation need be done.
2433 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2434 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2435 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2436 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2439 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2442 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2444 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2445 vcpu->arch.virtual_tsc_mult,
2446 vcpu->arch.virtual_tsc_shift);
2447 tsc += vcpu->arch.this_tsc_write;
2451 #ifdef CONFIG_X86_64
2452 static inline int gtod_is_based_on_tsc(int mode)
2454 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2458 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2460 #ifdef CONFIG_X86_64
2462 struct kvm_arch *ka = &vcpu->kvm->arch;
2463 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2465 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2466 atomic_read(&vcpu->kvm->online_vcpus));
2469 * Once the masterclock is enabled, always perform request in
2470 * order to update it.
2472 * In order to enable masterclock, the host clocksource must be TSC
2473 * and the vcpus need to have matched TSCs. When that happens,
2474 * perform request to enable masterclock.
2476 if (ka->use_master_clock ||
2477 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2478 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2480 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2481 atomic_read(&vcpu->kvm->online_vcpus),
2482 ka->use_master_clock, gtod->clock.vclock_mode);
2487 * Multiply tsc by a fixed point number represented by ratio.
2489 * The most significant 64-N bits (mult) of ratio represent the
2490 * integral part of the fixed point number; the remaining N bits
2491 * (frac) represent the fractional part, ie. ratio represents a fixed
2492 * point number (mult + frac * 2^(-N)).
2494 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
2496 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2498 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
2501 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2505 if (ratio != kvm_caps.default_tsc_scaling_ratio)
2506 _tsc = __scale_tsc(ratio, tsc);
2511 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2515 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2517 return target_tsc - tsc;
2520 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2522 return vcpu->arch.l1_tsc_offset +
2523 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2525 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2527 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2531 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
2532 nested_offset = l1_offset;
2534 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2535 kvm_caps.tsc_scaling_ratio_frac_bits);
2537 nested_offset += l2_offset;
2538 return nested_offset;
2540 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2542 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2544 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
2545 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2546 kvm_caps.tsc_scaling_ratio_frac_bits);
2548 return l1_multiplier;
2550 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2552 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2554 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2555 vcpu->arch.l1_tsc_offset,
2558 vcpu->arch.l1_tsc_offset = l1_offset;
2561 * If we are here because L1 chose not to trap WRMSR to TSC then
2562 * according to the spec this should set L1's TSC (as opposed to
2563 * setting L1's offset for L2).
2565 if (is_guest_mode(vcpu))
2566 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2568 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2569 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2571 vcpu->arch.tsc_offset = l1_offset;
2573 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset);
2576 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2578 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2580 /* Userspace is changing the multiplier while L2 is active */
2581 if (is_guest_mode(vcpu))
2582 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2584 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2586 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2588 if (kvm_caps.has_tsc_control)
2589 static_call(kvm_x86_write_tsc_multiplier)(
2590 vcpu, vcpu->arch.tsc_scaling_ratio);
2593 static inline bool kvm_check_tsc_unstable(void)
2595 #ifdef CONFIG_X86_64
2597 * TSC is marked unstable when we're running on Hyper-V,
2598 * 'TSC page' clocksource is good.
2600 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2603 return check_tsc_unstable();
2607 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2608 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2611 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2612 u64 ns, bool matched)
2614 struct kvm *kvm = vcpu->kvm;
2616 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2619 * We also track th most recent recorded KHZ, write and time to
2620 * allow the matching interval to be extended at each write.
2622 kvm->arch.last_tsc_nsec = ns;
2623 kvm->arch.last_tsc_write = tsc;
2624 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2625 kvm->arch.last_tsc_offset = offset;
2627 vcpu->arch.last_guest_tsc = tsc;
2629 kvm_vcpu_write_tsc_offset(vcpu, offset);
2633 * We split periods of matched TSC writes into generations.
2634 * For each generation, we track the original measured
2635 * nanosecond time, offset, and write, so if TSCs are in
2636 * sync, we can match exact offset, and if not, we can match
2637 * exact software computation in compute_guest_tsc()
2639 * These values are tracked in kvm->arch.cur_xxx variables.
2641 kvm->arch.cur_tsc_generation++;
2642 kvm->arch.cur_tsc_nsec = ns;
2643 kvm->arch.cur_tsc_write = tsc;
2644 kvm->arch.cur_tsc_offset = offset;
2645 kvm->arch.nr_vcpus_matched_tsc = 0;
2646 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2647 kvm->arch.nr_vcpus_matched_tsc++;
2650 /* Keep track of which generation this VCPU has synchronized to */
2651 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2652 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2653 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2655 kvm_track_tsc_matching(vcpu);
2658 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2660 struct kvm *kvm = vcpu->kvm;
2661 u64 offset, ns, elapsed;
2662 unsigned long flags;
2663 bool matched = false;
2664 bool synchronizing = false;
2666 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2667 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2668 ns = get_kvmclock_base_ns();
2669 elapsed = ns - kvm->arch.last_tsc_nsec;
2671 if (vcpu->arch.virtual_tsc_khz) {
2674 * detection of vcpu initialization -- need to sync
2675 * with other vCPUs. This particularly helps to keep
2676 * kvm_clock stable after CPU hotplug
2678 synchronizing = true;
2680 u64 tsc_exp = kvm->arch.last_tsc_write +
2681 nsec_to_cycles(vcpu, elapsed);
2682 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2684 * Special case: TSC write with a small delta (1 second)
2685 * of virtual cycle time against real time is
2686 * interpreted as an attempt to synchronize the CPU.
2688 synchronizing = data < tsc_exp + tsc_hz &&
2689 data + tsc_hz > tsc_exp;
2694 * For a reliable TSC, we can match TSC offsets, and for an unstable
2695 * TSC, we add elapsed time in this computation. We could let the
2696 * compensation code attempt to catch up if we fall behind, but
2697 * it's better to try to match offsets from the beginning.
2699 if (synchronizing &&
2700 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2701 if (!kvm_check_tsc_unstable()) {
2702 offset = kvm->arch.cur_tsc_offset;
2704 u64 delta = nsec_to_cycles(vcpu, elapsed);
2706 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2711 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2712 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2715 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2718 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2719 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2722 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2724 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
2725 WARN_ON(adjustment < 0);
2726 adjustment = kvm_scale_tsc((u64) adjustment,
2727 vcpu->arch.l1_tsc_scaling_ratio);
2728 adjust_tsc_offset_guest(vcpu, adjustment);
2731 #ifdef CONFIG_X86_64
2733 static u64 read_tsc(void)
2735 u64 ret = (u64)rdtsc_ordered();
2736 u64 last = pvclock_gtod_data.clock.cycle_last;
2738 if (likely(ret >= last))
2742 * GCC likes to generate cmov here, but this branch is extremely
2743 * predictable (it's just a function of time and the likely is
2744 * very likely) and there's a data dependence, so force GCC
2745 * to generate a branch instead. I don't barrier() because
2746 * we don't actually need a barrier, and if this function
2747 * ever gets inlined it will generate worse code.
2753 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2759 switch (clock->vclock_mode) {
2760 case VDSO_CLOCKMODE_HVCLOCK:
2761 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2763 if (tsc_pg_val != U64_MAX) {
2764 /* TSC page valid */
2765 *mode = VDSO_CLOCKMODE_HVCLOCK;
2766 v = (tsc_pg_val - clock->cycle_last) &
2769 /* TSC page invalid */
2770 *mode = VDSO_CLOCKMODE_NONE;
2773 case VDSO_CLOCKMODE_TSC:
2774 *mode = VDSO_CLOCKMODE_TSC;
2775 *tsc_timestamp = read_tsc();
2776 v = (*tsc_timestamp - clock->cycle_last) &
2780 *mode = VDSO_CLOCKMODE_NONE;
2783 if (*mode == VDSO_CLOCKMODE_NONE)
2784 *tsc_timestamp = v = 0;
2786 return v * clock->mult;
2789 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2791 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2797 seq = read_seqcount_begin(>od->seq);
2798 ns = gtod->raw_clock.base_cycles;
2799 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2800 ns >>= gtod->raw_clock.shift;
2801 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2802 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2808 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2810 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2816 seq = read_seqcount_begin(>od->seq);
2817 ts->tv_sec = gtod->wall_time_sec;
2818 ns = gtod->clock.base_cycles;
2819 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2820 ns >>= gtod->clock.shift;
2821 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2823 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2829 /* returns true if host is using TSC based clocksource */
2830 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2832 /* checked again under seqlock below */
2833 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2836 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2840 /* returns true if host is using TSC based clocksource */
2841 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2844 /* checked again under seqlock below */
2845 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2848 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2854 * Assuming a stable TSC across physical CPUS, and a stable TSC
2855 * across virtual CPUs, the following condition is possible.
2856 * Each numbered line represents an event visible to both
2857 * CPUs at the next numbered event.
2859 * "timespecX" represents host monotonic time. "tscX" represents
2862 * VCPU0 on CPU0 | VCPU1 on CPU1
2864 * 1. read timespec0,tsc0
2865 * 2. | timespec1 = timespec0 + N
2867 * 3. transition to guest | transition to guest
2868 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2869 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2870 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2872 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2875 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2877 * - 0 < N - M => M < N
2879 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2880 * always the case (the difference between two distinct xtime instances
2881 * might be smaller then the difference between corresponding TSC reads,
2882 * when updating guest vcpus pvclock areas).
2884 * To avoid that problem, do not allow visibility of distinct
2885 * system_timestamp/tsc_timestamp values simultaneously: use a master
2886 * copy of host monotonic time values. Update that master copy
2889 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2893 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2895 #ifdef CONFIG_X86_64
2896 struct kvm_arch *ka = &kvm->arch;
2898 bool host_tsc_clocksource, vcpus_matched;
2900 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2901 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2902 atomic_read(&kvm->online_vcpus));
2905 * If the host uses TSC clock, then passthrough TSC as stable
2908 host_tsc_clocksource = kvm_get_time_and_clockread(
2909 &ka->master_kernel_ns,
2910 &ka->master_cycle_now);
2912 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2913 && !ka->backwards_tsc_observed
2914 && !ka->boot_vcpu_runs_old_kvmclock;
2916 if (ka->use_master_clock)
2917 atomic_set(&kvm_guest_has_master_clock, 1);
2919 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2920 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2925 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2927 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2930 static void __kvm_start_pvclock_update(struct kvm *kvm)
2932 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2933 write_seqcount_begin(&kvm->arch.pvclock_sc);
2936 static void kvm_start_pvclock_update(struct kvm *kvm)
2938 kvm_make_mclock_inprogress_request(kvm);
2940 /* no guest entries from this point */
2941 __kvm_start_pvclock_update(kvm);
2944 static void kvm_end_pvclock_update(struct kvm *kvm)
2946 struct kvm_arch *ka = &kvm->arch;
2947 struct kvm_vcpu *vcpu;
2950 write_seqcount_end(&ka->pvclock_sc);
2951 raw_spin_unlock_irq(&ka->tsc_write_lock);
2952 kvm_for_each_vcpu(i, vcpu, kvm)
2953 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2955 /* guest entries allowed */
2956 kvm_for_each_vcpu(i, vcpu, kvm)
2957 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2960 static void kvm_update_masterclock(struct kvm *kvm)
2962 kvm_hv_request_tsc_page_update(kvm);
2963 kvm_start_pvclock_update(kvm);
2964 pvclock_update_vm_gtod_copy(kvm);
2965 kvm_end_pvclock_update(kvm);
2969 * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's
2970 * per-CPU value (which may be zero if a CPU is going offline). Note, tsc_khz
2971 * can change during boot even if the TSC is constant, as it's possible for KVM
2972 * to be loaded before TSC calibration completes. Ideally, KVM would get a
2973 * notification when calibration completes, but practically speaking calibration
2974 * will complete before userspace is alive enough to create VMs.
2976 static unsigned long get_cpu_tsc_khz(void)
2978 if (static_cpu_has(X86_FEATURE_CONSTANT_TSC))
2981 return __this_cpu_read(cpu_tsc_khz);
2984 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
2985 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2987 struct kvm_arch *ka = &kvm->arch;
2988 struct pvclock_vcpu_time_info hv_clock;
2990 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2994 if (ka->use_master_clock &&
2995 (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) {
2996 #ifdef CONFIG_X86_64
2997 struct timespec64 ts;
2999 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
3000 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
3001 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
3004 data->host_tsc = rdtsc();
3006 data->flags |= KVM_CLOCK_TSC_STABLE;
3007 hv_clock.tsc_timestamp = ka->master_cycle_now;
3008 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3009 kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL,
3010 &hv_clock.tsc_shift,
3011 &hv_clock.tsc_to_system_mul);
3012 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
3014 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
3020 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3022 struct kvm_arch *ka = &kvm->arch;
3026 seq = read_seqcount_begin(&ka->pvclock_sc);
3027 __get_kvmclock(kvm, data);
3028 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3031 u64 get_kvmclock_ns(struct kvm *kvm)
3033 struct kvm_clock_data data;
3035 get_kvmclock(kvm, &data);
3039 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
3040 struct gfn_to_pfn_cache *gpc,
3041 unsigned int offset)
3043 struct kvm_vcpu_arch *vcpu = &v->arch;
3044 struct pvclock_vcpu_time_info *guest_hv_clock;
3045 unsigned long flags;
3047 read_lock_irqsave(&gpc->lock, flags);
3048 while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) {
3049 read_unlock_irqrestore(&gpc->lock, flags);
3051 if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock)))
3054 read_lock_irqsave(&gpc->lock, flags);
3057 guest_hv_clock = (void *)(gpc->khva + offset);
3060 * This VCPU is paused, but it's legal for a guest to read another
3061 * VCPU's kvmclock, so we really have to follow the specification where
3062 * it says that version is odd if data is being modified, and even after
3066 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
3069 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3070 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3072 if (vcpu->pvclock_set_guest_stopped_request) {
3073 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3074 vcpu->pvclock_set_guest_stopped_request = false;
3077 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3080 guest_hv_clock->version = ++vcpu->hv_clock.version;
3082 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT);
3083 read_unlock_irqrestore(&gpc->lock, flags);
3085 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3088 static int kvm_guest_time_update(struct kvm_vcpu *v)
3090 unsigned long flags, tgt_tsc_khz;
3092 struct kvm_vcpu_arch *vcpu = &v->arch;
3093 struct kvm_arch *ka = &v->kvm->arch;
3095 u64 tsc_timestamp, host_tsc;
3097 bool use_master_clock;
3103 * If the host uses TSC clock, then passthrough TSC as stable
3107 seq = read_seqcount_begin(&ka->pvclock_sc);
3108 use_master_clock = ka->use_master_clock;
3109 if (use_master_clock) {
3110 host_tsc = ka->master_cycle_now;
3111 kernel_ns = ka->master_kernel_ns;
3113 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3115 /* Keep irq disabled to prevent changes to the clock */
3116 local_irq_save(flags);
3117 tgt_tsc_khz = get_cpu_tsc_khz();
3118 if (unlikely(tgt_tsc_khz == 0)) {
3119 local_irq_restore(flags);
3120 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3123 if (!use_master_clock) {
3125 kernel_ns = get_kvmclock_base_ns();
3128 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3131 * We may have to catch up the TSC to match elapsed wall clock
3132 * time for two reasons, even if kvmclock is used.
3133 * 1) CPU could have been running below the maximum TSC rate
3134 * 2) Broken TSC compensation resets the base at each VCPU
3135 * entry to avoid unknown leaps of TSC even when running
3136 * again on the same CPU. This may cause apparent elapsed
3137 * time to disappear, and the guest to stand still or run
3140 if (vcpu->tsc_catchup) {
3141 u64 tsc = compute_guest_tsc(v, kernel_ns);
3142 if (tsc > tsc_timestamp) {
3143 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3144 tsc_timestamp = tsc;
3148 local_irq_restore(flags);
3150 /* With all the info we got, fill in the values */
3152 if (kvm_caps.has_tsc_control)
3153 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3154 v->arch.l1_tsc_scaling_ratio);
3156 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3157 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3158 &vcpu->hv_clock.tsc_shift,
3159 &vcpu->hv_clock.tsc_to_system_mul);
3160 vcpu->hw_tsc_khz = tgt_tsc_khz;
3163 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3164 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3165 vcpu->last_guest_tsc = tsc_timestamp;
3167 /* If the host uses TSC clocksource, then it is stable */
3169 if (use_master_clock)
3170 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3172 vcpu->hv_clock.flags = pvclock_flags;
3174 if (vcpu->pv_time.active)
3175 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0);
3176 if (vcpu->xen.vcpu_info_cache.active)
3177 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3178 offsetof(struct compat_vcpu_info, time));
3179 if (vcpu->xen.vcpu_time_info_cache.active)
3180 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0);
3181 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3186 * kvmclock updates which are isolated to a given vcpu, such as
3187 * vcpu->cpu migration, should not allow system_timestamp from
3188 * the rest of the vcpus to remain static. Otherwise ntp frequency
3189 * correction applies to one vcpu's system_timestamp but not
3192 * So in those cases, request a kvmclock update for all vcpus.
3193 * We need to rate-limit these requests though, as they can
3194 * considerably slow guests that have a large number of vcpus.
3195 * The time for a remote vcpu to update its kvmclock is bound
3196 * by the delay we use to rate-limit the updates.
3199 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3201 static void kvmclock_update_fn(struct work_struct *work)
3204 struct delayed_work *dwork = to_delayed_work(work);
3205 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3206 kvmclock_update_work);
3207 struct kvm *kvm = container_of(ka, struct kvm, arch);
3208 struct kvm_vcpu *vcpu;
3210 kvm_for_each_vcpu(i, vcpu, kvm) {
3211 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3212 kvm_vcpu_kick(vcpu);
3216 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3218 struct kvm *kvm = v->kvm;
3220 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3221 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3222 KVMCLOCK_UPDATE_DELAY);
3225 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3227 static void kvmclock_sync_fn(struct work_struct *work)
3229 struct delayed_work *dwork = to_delayed_work(work);
3230 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3231 kvmclock_sync_work);
3232 struct kvm *kvm = container_of(ka, struct kvm, arch);
3234 if (!kvmclock_periodic_sync)
3237 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3238 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3239 KVMCLOCK_SYNC_PERIOD);
3242 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
3243 static bool is_mci_control_msr(u32 msr)
3245 return (msr & 3) == 0;
3247 static bool is_mci_status_msr(u32 msr)
3249 return (msr & 3) == 1;
3253 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3255 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3257 /* McStatusWrEn enabled? */
3258 if (guest_cpuid_is_amd_or_hygon(vcpu))
3259 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3264 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3266 u64 mcg_cap = vcpu->arch.mcg_cap;
3267 unsigned bank_num = mcg_cap & 0xff;
3268 u32 msr = msr_info->index;
3269 u64 data = msr_info->data;
3270 u32 offset, last_msr;
3273 case MSR_IA32_MCG_STATUS:
3274 vcpu->arch.mcg_status = data;
3276 case MSR_IA32_MCG_CTL:
3277 if (!(mcg_cap & MCG_CTL_P) &&
3278 (data || !msr_info->host_initiated))
3280 if (data != 0 && data != ~(u64)0)
3282 vcpu->arch.mcg_ctl = data;
3284 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3285 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3289 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
3291 /* An attempt to write a 1 to a reserved bit raises #GP */
3292 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
3294 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3295 last_msr + 1 - MSR_IA32_MC0_CTL2);
3296 vcpu->arch.mci_ctl2_banks[offset] = data;
3298 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3299 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3304 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other
3305 * values are architecturally undefined. But, some Linux
3306 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
3307 * issue on AMD K8s, allow bit 10 to be clear when setting all
3308 * other bits in order to avoid an uncaught #GP in the guest.
3310 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable,
3311 * single-bit ECC data errors.
3313 if (is_mci_control_msr(msr) &&
3314 data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
3318 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
3319 * AMD-based CPUs allow non-zero values, but if and only if
3320 * HWCR[McStatusWrEn] is set.
3322 if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
3323 data != 0 && !can_set_mci_status(vcpu))
3326 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3327 last_msr + 1 - MSR_IA32_MC0_CTL);
3328 vcpu->arch.mce_banks[offset] = data;
3336 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3338 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3340 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3343 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3345 gpa_t gpa = data & ~0x3f;
3347 /* Bits 4:5 are reserved, Should be zero */
3351 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3352 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3355 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3356 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3359 if (!lapic_in_kernel(vcpu))
3360 return data ? 1 : 0;
3362 vcpu->arch.apf.msr_en_val = data;
3364 if (!kvm_pv_async_pf_enabled(vcpu)) {
3365 kvm_clear_async_pf_completion_queue(vcpu);
3366 kvm_async_pf_hash_reset(vcpu);
3370 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3374 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3375 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3377 kvm_async_pf_wakeup_all(vcpu);
3382 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3384 /* Bits 8-63 are reserved */
3388 if (!lapic_in_kernel(vcpu))
3391 vcpu->arch.apf.msr_int_val = data;
3393 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3398 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3400 kvm_gpc_deactivate(&vcpu->arch.pv_time);
3401 vcpu->arch.time = 0;
3404 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3406 ++vcpu->stat.tlb_flush;
3407 static_call(kvm_x86_flush_tlb_all)(vcpu);
3409 /* Flushing all ASIDs flushes the current ASID... */
3410 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3413 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3415 ++vcpu->stat.tlb_flush;
3419 * A TLB flush on behalf of the guest is equivalent to
3420 * INVPCID(all), toggling CR4.PGE, etc., which requires
3421 * a forced sync of the shadow page tables. Ensure all the
3422 * roots are synced and the guest TLB in hardware is clean.
3424 kvm_mmu_sync_roots(vcpu);
3425 kvm_mmu_sync_prev_roots(vcpu);
3428 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3431 * Flushing all "guest" TLB is always a superset of Hyper-V's fine
3434 kvm_hv_vcpu_purge_flush_tlb(vcpu);
3438 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3440 ++vcpu->stat.tlb_flush;
3441 static_call(kvm_x86_flush_tlb_current)(vcpu);
3445 * Service "local" TLB flush requests, which are specific to the current MMU
3446 * context. In addition to the generic event handling in vcpu_enter_guest(),
3447 * TLB flushes that are targeted at an MMU context also need to be serviced
3448 * prior before nested VM-Enter/VM-Exit.
3450 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3452 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3453 kvm_vcpu_flush_tlb_current(vcpu);
3455 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3456 kvm_vcpu_flush_tlb_guest(vcpu);
3458 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3460 static void record_steal_time(struct kvm_vcpu *vcpu)
3462 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3463 struct kvm_steal_time __user *st;
3464 struct kvm_memslots *slots;
3465 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3469 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3470 kvm_xen_runstate_set_running(vcpu);
3474 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3477 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3480 slots = kvm_memslots(vcpu->kvm);
3482 if (unlikely(slots->generation != ghc->generation ||
3484 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3485 /* We rely on the fact that it fits in a single page. */
3486 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3488 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) ||
3489 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3493 st = (struct kvm_steal_time __user *)ghc->hva;
3495 * Doing a TLB flush here, on the guest's behalf, can avoid
3498 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3499 u8 st_preempted = 0;
3502 if (!user_access_begin(st, sizeof(*st)))
3505 asm volatile("1: xchgb %0, %2\n"
3508 _ASM_EXTABLE_UA(1b, 2b)
3509 : "+q" (st_preempted),
3511 "+m" (st->preempted));
3517 vcpu->arch.st.preempted = 0;
3519 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3520 st_preempted & KVM_VCPU_FLUSH_TLB);
3521 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3522 kvm_vcpu_flush_tlb_guest(vcpu);
3524 if (!user_access_begin(st, sizeof(*st)))
3527 if (!user_access_begin(st, sizeof(*st)))
3530 unsafe_put_user(0, &st->preempted, out);
3531 vcpu->arch.st.preempted = 0;
3534 unsafe_get_user(version, &st->version, out);
3536 version += 1; /* first time write, random junk */
3539 unsafe_put_user(version, &st->version, out);
3543 unsafe_get_user(steal, &st->steal, out);
3544 steal += current->sched_info.run_delay -
3545 vcpu->arch.st.last_steal;
3546 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3547 unsafe_put_user(steal, &st->steal, out);
3550 unsafe_put_user(version, &st->version, out);
3555 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3558 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3561 u32 msr = msr_info->index;
3562 u64 data = msr_info->data;
3564 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3565 return kvm_xen_write_hypercall_page(vcpu, data);
3568 case MSR_AMD64_NB_CFG:
3569 case MSR_IA32_UCODE_WRITE:
3570 case MSR_VM_HSAVE_PA:
3571 case MSR_AMD64_PATCH_LOADER:
3572 case MSR_AMD64_BU_CFG2:
3573 case MSR_AMD64_DC_CFG:
3574 case MSR_F15H_EX_CFG:
3577 case MSR_IA32_UCODE_REV:
3578 if (msr_info->host_initiated)
3579 vcpu->arch.microcode_version = data;
3581 case MSR_IA32_ARCH_CAPABILITIES:
3582 if (!msr_info->host_initiated)
3584 vcpu->arch.arch_capabilities = data;
3586 case MSR_IA32_PERF_CAPABILITIES:
3587 if (!msr_info->host_initiated)
3589 if (data & ~kvm_caps.supported_perf_cap)
3592 vcpu->arch.perf_capabilities = data;
3593 kvm_pmu_refresh(vcpu);
3596 return set_efer(vcpu, msr_info);
3598 data &= ~(u64)0x40; /* ignore flush filter disable */
3599 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3600 data &= ~(u64)0x8; /* ignore TLB cache disable */
3602 /* Handle McStatusWrEn */
3603 if (data == BIT_ULL(18)) {
3604 vcpu->arch.msr_hwcr = data;
3605 } else if (data != 0) {
3606 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3611 case MSR_FAM10H_MMIO_CONF_BASE:
3613 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3618 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
3619 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
3620 return kvm_mtrr_set_msr(vcpu, msr, data);
3621 case MSR_IA32_APICBASE:
3622 return kvm_set_apic_base(vcpu, msr_info);
3623 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3624 return kvm_x2apic_msr_write(vcpu, msr, data);
3625 case MSR_IA32_TSC_DEADLINE:
3626 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3628 case MSR_IA32_TSC_ADJUST:
3629 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3630 if (!msr_info->host_initiated) {
3631 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3632 adjust_tsc_offset_guest(vcpu, adj);
3633 /* Before back to guest, tsc_timestamp must be adjusted
3634 * as well, otherwise guest's percpu pvclock time could jump.
3636 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3638 vcpu->arch.ia32_tsc_adjust_msr = data;
3641 case MSR_IA32_MISC_ENABLE: {
3642 u64 old_val = vcpu->arch.ia32_misc_enable_msr;
3644 if (!msr_info->host_initiated) {
3646 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)
3649 /* R bits, i.e. writes are ignored, but don't fault. */
3650 data = data & ~MSR_IA32_MISC_ENABLE_EMON;
3651 data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
3654 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3655 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3656 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3658 vcpu->arch.ia32_misc_enable_msr = data;
3659 kvm_update_cpuid_runtime(vcpu);
3661 vcpu->arch.ia32_misc_enable_msr = data;
3665 case MSR_IA32_SMBASE:
3666 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
3668 vcpu->arch.smbase = data;
3670 case MSR_IA32_POWER_CTL:
3671 vcpu->arch.msr_ia32_power_ctl = data;
3674 if (msr_info->host_initiated) {
3675 kvm_synchronize_tsc(vcpu, data);
3677 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3678 adjust_tsc_offset_guest(vcpu, adj);
3679 vcpu->arch.ia32_tsc_adjust_msr += adj;
3683 if (!msr_info->host_initiated &&
3684 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3687 * KVM supports exposing PT to the guest, but does not support
3688 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3689 * XSAVES/XRSTORS to save/restore PT MSRs.
3691 if (data & ~kvm_caps.supported_xss)
3693 vcpu->arch.ia32_xss = data;
3694 kvm_update_cpuid_runtime(vcpu);
3697 if (!msr_info->host_initiated)
3699 vcpu->arch.smi_count = data;
3701 case MSR_KVM_WALL_CLOCK_NEW:
3702 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3705 vcpu->kvm->arch.wall_clock = data;
3706 kvm_write_wall_clock(vcpu->kvm, data, 0);
3708 case MSR_KVM_WALL_CLOCK:
3709 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3712 vcpu->kvm->arch.wall_clock = data;
3713 kvm_write_wall_clock(vcpu->kvm, data, 0);
3715 case MSR_KVM_SYSTEM_TIME_NEW:
3716 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3719 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3721 case MSR_KVM_SYSTEM_TIME:
3722 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3725 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3727 case MSR_KVM_ASYNC_PF_EN:
3728 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3731 if (kvm_pv_enable_async_pf(vcpu, data))
3734 case MSR_KVM_ASYNC_PF_INT:
3735 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3738 if (kvm_pv_enable_async_pf_int(vcpu, data))
3741 case MSR_KVM_ASYNC_PF_ACK:
3742 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3745 vcpu->arch.apf.pageready_pending = false;
3746 kvm_check_async_pf_completion(vcpu);
3749 case MSR_KVM_STEAL_TIME:
3750 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3753 if (unlikely(!sched_info_on()))
3756 if (data & KVM_STEAL_RESERVED_MASK)
3759 vcpu->arch.st.msr_val = data;
3761 if (!(data & KVM_MSR_ENABLED))
3764 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3767 case MSR_KVM_PV_EOI_EN:
3768 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3771 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3775 case MSR_KVM_POLL_CONTROL:
3776 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3779 /* only enable bit supported */
3780 if (data & (-1ULL << 1))
3783 vcpu->arch.msr_kvm_poll_control = data;
3786 case MSR_IA32_MCG_CTL:
3787 case MSR_IA32_MCG_STATUS:
3788 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3789 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3790 return set_msr_mce(vcpu, msr_info);
3792 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3793 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3796 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3797 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3798 if (kvm_pmu_is_valid_msr(vcpu, msr))
3799 return kvm_pmu_set_msr(vcpu, msr_info);
3801 if (pr || data != 0)
3802 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3803 "0x%x data 0x%llx\n", msr, data);
3805 case MSR_K7_CLK_CTL:
3807 * Ignore all writes to this no longer documented MSR.
3808 * Writes are only relevant for old K7 processors,
3809 * all pre-dating SVM, but a recommended workaround from
3810 * AMD for these chips. It is possible to specify the
3811 * affected processor models on the command line, hence
3812 * the need to ignore the workaround.
3815 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3816 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3817 case HV_X64_MSR_SYNDBG_OPTIONS:
3818 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3819 case HV_X64_MSR_CRASH_CTL:
3820 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3821 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3822 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3823 case HV_X64_MSR_TSC_EMULATION_STATUS:
3824 return kvm_hv_set_msr_common(vcpu, msr, data,
3825 msr_info->host_initiated);
3826 case MSR_IA32_BBL_CR_CTL3:
3827 /* Drop writes to this legacy MSR -- see rdmsr
3828 * counterpart for further detail.
3830 if (report_ignored_msrs)
3831 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3834 case MSR_AMD64_OSVW_ID_LENGTH:
3835 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3837 vcpu->arch.osvw.length = data;
3839 case MSR_AMD64_OSVW_STATUS:
3840 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3842 vcpu->arch.osvw.status = data;
3844 case MSR_PLATFORM_INFO:
3845 if (!msr_info->host_initiated ||
3846 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3847 cpuid_fault_enabled(vcpu)))
3849 vcpu->arch.msr_platform_info = data;
3851 case MSR_MISC_FEATURES_ENABLES:
3852 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3853 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3854 !supports_cpuid_fault(vcpu)))
3856 vcpu->arch.msr_misc_features_enables = data;
3858 #ifdef CONFIG_X86_64
3860 if (!msr_info->host_initiated &&
3861 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3864 if (data & ~kvm_guest_supported_xfd(vcpu))
3867 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3869 case MSR_IA32_XFD_ERR:
3870 if (!msr_info->host_initiated &&
3871 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3874 if (data & ~kvm_guest_supported_xfd(vcpu))
3877 vcpu->arch.guest_fpu.xfd_err = data;
3880 case MSR_IA32_PEBS_ENABLE:
3881 case MSR_IA32_DS_AREA:
3882 case MSR_PEBS_DATA_CFG:
3883 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3884 if (kvm_pmu_is_valid_msr(vcpu, msr))
3885 return kvm_pmu_set_msr(vcpu, msr_info);
3887 * Userspace is allowed to write '0' to MSRs that KVM reports
3888 * as to-be-saved, even if an MSRs isn't fully supported.
3890 return !msr_info->host_initiated || data;
3892 if (kvm_pmu_is_valid_msr(vcpu, msr))
3893 return kvm_pmu_set_msr(vcpu, msr_info);
3894 return KVM_MSR_RET_INVALID;
3898 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3900 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3903 u64 mcg_cap = vcpu->arch.mcg_cap;
3904 unsigned bank_num = mcg_cap & 0xff;
3905 u32 offset, last_msr;
3908 case MSR_IA32_P5_MC_ADDR:
3909 case MSR_IA32_P5_MC_TYPE:
3912 case MSR_IA32_MCG_CAP:
3913 data = vcpu->arch.mcg_cap;
3915 case MSR_IA32_MCG_CTL:
3916 if (!(mcg_cap & MCG_CTL_P) && !host)
3918 data = vcpu->arch.mcg_ctl;
3920 case MSR_IA32_MCG_STATUS:
3921 data = vcpu->arch.mcg_status;
3923 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3924 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3928 if (!(mcg_cap & MCG_CMCI_P) && !host)
3930 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3931 last_msr + 1 - MSR_IA32_MC0_CTL2);
3932 data = vcpu->arch.mci_ctl2_banks[offset];
3934 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3935 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3939 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3940 last_msr + 1 - MSR_IA32_MC0_CTL);
3941 data = vcpu->arch.mce_banks[offset];
3950 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3952 switch (msr_info->index) {
3953 case MSR_IA32_PLATFORM_ID:
3954 case MSR_IA32_EBL_CR_POWERON:
3955 case MSR_IA32_LASTBRANCHFROMIP:
3956 case MSR_IA32_LASTBRANCHTOIP:
3957 case MSR_IA32_LASTINTFROMIP:
3958 case MSR_IA32_LASTINTTOIP:
3959 case MSR_AMD64_SYSCFG:
3960 case MSR_K8_TSEG_ADDR:
3961 case MSR_K8_TSEG_MASK:
3962 case MSR_VM_HSAVE_PA:
3963 case MSR_K8_INT_PENDING_MSG:
3964 case MSR_AMD64_NB_CFG:
3965 case MSR_FAM10H_MMIO_CONF_BASE:
3966 case MSR_AMD64_BU_CFG2:
3967 case MSR_IA32_PERF_CTL:
3968 case MSR_AMD64_DC_CFG:
3969 case MSR_F15H_EX_CFG:
3971 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3972 * limit) MSRs. Just return 0, as we do not want to expose the host
3973 * data here. Do not conditionalize this on CPUID, as KVM does not do
3974 * so for existing CPU-specific MSRs.
3976 case MSR_RAPL_POWER_UNIT:
3977 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3978 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3979 case MSR_PKG_ENERGY_STATUS: /* Total package */
3980 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3983 case MSR_IA32_PEBS_ENABLE:
3984 case MSR_IA32_DS_AREA:
3985 case MSR_PEBS_DATA_CFG:
3986 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3987 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3988 return kvm_pmu_get_msr(vcpu, msr_info);
3990 * Userspace is allowed to read MSRs that KVM reports as
3991 * to-be-saved, even if an MSR isn't fully supported.
3993 if (!msr_info->host_initiated)
3997 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3998 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3999 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
4000 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
4001 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4002 return kvm_pmu_get_msr(vcpu, msr_info);
4005 case MSR_IA32_UCODE_REV:
4006 msr_info->data = vcpu->arch.microcode_version;
4008 case MSR_IA32_ARCH_CAPABILITIES:
4009 if (!msr_info->host_initiated &&
4010 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4012 msr_info->data = vcpu->arch.arch_capabilities;
4014 case MSR_IA32_PERF_CAPABILITIES:
4015 if (!msr_info->host_initiated &&
4016 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
4018 msr_info->data = vcpu->arch.perf_capabilities;
4020 case MSR_IA32_POWER_CTL:
4021 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
4023 case MSR_IA32_TSC: {
4025 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
4026 * even when not intercepted. AMD manual doesn't explicitly
4027 * state this but appears to behave the same.
4029 * On userspace reads and writes, however, we unconditionally
4030 * return L1's TSC value to ensure backwards-compatible
4031 * behavior for migration.
4035 if (msr_info->host_initiated) {
4036 offset = vcpu->arch.l1_tsc_offset;
4037 ratio = vcpu->arch.l1_tsc_scaling_ratio;
4039 offset = vcpu->arch.tsc_offset;
4040 ratio = vcpu->arch.tsc_scaling_ratio;
4043 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
4047 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
4048 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
4049 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
4050 case 0xcd: /* fsb frequency */
4054 * MSR_EBC_FREQUENCY_ID
4055 * Conservative value valid for even the basic CPU models.
4056 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
4057 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
4058 * and 266MHz for model 3, or 4. Set Core Clock
4059 * Frequency to System Bus Frequency Ratio to 1 (bits
4060 * 31:24) even though these are only valid for CPU
4061 * models > 2, however guests may end up dividing or
4062 * multiplying by zero otherwise.
4064 case MSR_EBC_FREQUENCY_ID:
4065 msr_info->data = 1 << 24;
4067 case MSR_IA32_APICBASE:
4068 msr_info->data = kvm_get_apic_base(vcpu);
4070 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
4071 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
4072 case MSR_IA32_TSC_DEADLINE:
4073 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
4075 case MSR_IA32_TSC_ADJUST:
4076 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
4078 case MSR_IA32_MISC_ENABLE:
4079 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
4081 case MSR_IA32_SMBASE:
4082 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
4084 msr_info->data = vcpu->arch.smbase;
4087 msr_info->data = vcpu->arch.smi_count;
4089 case MSR_IA32_PERF_STATUS:
4090 /* TSC increment by tick */
4091 msr_info->data = 1000ULL;
4092 /* CPU multiplier */
4093 msr_info->data |= (((uint64_t)4ULL) << 40);
4096 msr_info->data = vcpu->arch.efer;
4098 case MSR_KVM_WALL_CLOCK:
4099 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4102 msr_info->data = vcpu->kvm->arch.wall_clock;
4104 case MSR_KVM_WALL_CLOCK_NEW:
4105 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4108 msr_info->data = vcpu->kvm->arch.wall_clock;
4110 case MSR_KVM_SYSTEM_TIME:
4111 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4114 msr_info->data = vcpu->arch.time;
4116 case MSR_KVM_SYSTEM_TIME_NEW:
4117 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4120 msr_info->data = vcpu->arch.time;
4122 case MSR_KVM_ASYNC_PF_EN:
4123 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4126 msr_info->data = vcpu->arch.apf.msr_en_val;
4128 case MSR_KVM_ASYNC_PF_INT:
4129 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4132 msr_info->data = vcpu->arch.apf.msr_int_val;
4134 case MSR_KVM_ASYNC_PF_ACK:
4135 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4140 case MSR_KVM_STEAL_TIME:
4141 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4144 msr_info->data = vcpu->arch.st.msr_val;
4146 case MSR_KVM_PV_EOI_EN:
4147 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4150 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4152 case MSR_KVM_POLL_CONTROL:
4153 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4156 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4158 case MSR_IA32_P5_MC_ADDR:
4159 case MSR_IA32_P5_MC_TYPE:
4160 case MSR_IA32_MCG_CAP:
4161 case MSR_IA32_MCG_CTL:
4162 case MSR_IA32_MCG_STATUS:
4163 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4164 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4165 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4166 msr_info->host_initiated);
4168 if (!msr_info->host_initiated &&
4169 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4171 msr_info->data = vcpu->arch.ia32_xss;
4173 case MSR_K7_CLK_CTL:
4175 * Provide expected ramp-up count for K7. All other
4176 * are set to zero, indicating minimum divisors for
4179 * This prevents guest kernels on AMD host with CPU
4180 * type 6, model 8 and higher from exploding due to
4181 * the rdmsr failing.
4183 msr_info->data = 0x20000000;
4185 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4186 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4187 case HV_X64_MSR_SYNDBG_OPTIONS:
4188 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4189 case HV_X64_MSR_CRASH_CTL:
4190 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4191 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4192 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4193 case HV_X64_MSR_TSC_EMULATION_STATUS:
4194 return kvm_hv_get_msr_common(vcpu,
4195 msr_info->index, &msr_info->data,
4196 msr_info->host_initiated);
4197 case MSR_IA32_BBL_CR_CTL3:
4198 /* This legacy MSR exists but isn't fully documented in current
4199 * silicon. It is however accessed by winxp in very narrow
4200 * scenarios where it sets bit #19, itself documented as
4201 * a "reserved" bit. Best effort attempt to source coherent
4202 * read data here should the balance of the register be
4203 * interpreted by the guest:
4205 * L2 cache control register 3: 64GB range, 256KB size,
4206 * enabled, latency 0x1, configured
4208 msr_info->data = 0xbe702111;
4210 case MSR_AMD64_OSVW_ID_LENGTH:
4211 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4213 msr_info->data = vcpu->arch.osvw.length;
4215 case MSR_AMD64_OSVW_STATUS:
4216 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4218 msr_info->data = vcpu->arch.osvw.status;
4220 case MSR_PLATFORM_INFO:
4221 if (!msr_info->host_initiated &&
4222 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4224 msr_info->data = vcpu->arch.msr_platform_info;
4226 case MSR_MISC_FEATURES_ENABLES:
4227 msr_info->data = vcpu->arch.msr_misc_features_enables;
4230 msr_info->data = vcpu->arch.msr_hwcr;
4232 #ifdef CONFIG_X86_64
4234 if (!msr_info->host_initiated &&
4235 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4238 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4240 case MSR_IA32_XFD_ERR:
4241 if (!msr_info->host_initiated &&
4242 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4245 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4249 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4250 return kvm_pmu_get_msr(vcpu, msr_info);
4251 return KVM_MSR_RET_INVALID;
4255 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4258 * Read or write a bunch of msrs. All parameters are kernel addresses.
4260 * @return number of msrs set successfully.
4262 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4263 struct kvm_msr_entry *entries,
4264 int (*do_msr)(struct kvm_vcpu *vcpu,
4265 unsigned index, u64 *data))
4269 for (i = 0; i < msrs->nmsrs; ++i)
4270 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4277 * Read or write a bunch of msrs. Parameters are user addresses.
4279 * @return number of msrs set successfully.
4281 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4282 int (*do_msr)(struct kvm_vcpu *vcpu,
4283 unsigned index, u64 *data),
4286 struct kvm_msrs msrs;
4287 struct kvm_msr_entry *entries;
4292 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4296 if (msrs.nmsrs >= MAX_IO_MSRS)
4299 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4300 entries = memdup_user(user_msrs->entries, size);
4301 if (IS_ERR(entries)) {
4302 r = PTR_ERR(entries);
4306 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
4311 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4322 static inline bool kvm_can_mwait_in_guest(void)
4324 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4325 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4326 boot_cpu_has(X86_FEATURE_ARAT);
4329 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4330 struct kvm_cpuid2 __user *cpuid_arg)
4332 struct kvm_cpuid2 cpuid;
4336 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4339 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4344 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4350 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4355 case KVM_CAP_IRQCHIP:
4357 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4358 case KVM_CAP_SET_TSS_ADDR:
4359 case KVM_CAP_EXT_CPUID:
4360 case KVM_CAP_EXT_EMUL_CPUID:
4361 case KVM_CAP_CLOCKSOURCE:
4363 case KVM_CAP_NOP_IO_DELAY:
4364 case KVM_CAP_MP_STATE:
4365 case KVM_CAP_SYNC_MMU:
4366 case KVM_CAP_USER_NMI:
4367 case KVM_CAP_REINJECT_CONTROL:
4368 case KVM_CAP_IRQ_INJECT_STATUS:
4369 case KVM_CAP_IOEVENTFD:
4370 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4372 case KVM_CAP_PIT_STATE2:
4373 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4374 case KVM_CAP_VCPU_EVENTS:
4375 case KVM_CAP_HYPERV:
4376 case KVM_CAP_HYPERV_VAPIC:
4377 case KVM_CAP_HYPERV_SPIN:
4378 case KVM_CAP_HYPERV_SYNIC:
4379 case KVM_CAP_HYPERV_SYNIC2:
4380 case KVM_CAP_HYPERV_VP_INDEX:
4381 case KVM_CAP_HYPERV_EVENTFD:
4382 case KVM_CAP_HYPERV_TLBFLUSH:
4383 case KVM_CAP_HYPERV_SEND_IPI:
4384 case KVM_CAP_HYPERV_CPUID:
4385 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4386 case KVM_CAP_SYS_HYPERV_CPUID:
4387 case KVM_CAP_PCI_SEGMENT:
4388 case KVM_CAP_DEBUGREGS:
4389 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4391 case KVM_CAP_ASYNC_PF:
4392 case KVM_CAP_ASYNC_PF_INT:
4393 case KVM_CAP_GET_TSC_KHZ:
4394 case KVM_CAP_KVMCLOCK_CTRL:
4395 case KVM_CAP_READONLY_MEM:
4396 case KVM_CAP_HYPERV_TIME:
4397 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4398 case KVM_CAP_TSC_DEADLINE_TIMER:
4399 case KVM_CAP_DISABLE_QUIRKS:
4400 case KVM_CAP_SET_BOOT_CPU_ID:
4401 case KVM_CAP_SPLIT_IRQCHIP:
4402 case KVM_CAP_IMMEDIATE_EXIT:
4403 case KVM_CAP_PMU_EVENT_FILTER:
4404 case KVM_CAP_GET_MSR_FEATURES:
4405 case KVM_CAP_MSR_PLATFORM_INFO:
4406 case KVM_CAP_EXCEPTION_PAYLOAD:
4407 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
4408 case KVM_CAP_SET_GUEST_DEBUG:
4409 case KVM_CAP_LAST_CPU:
4410 case KVM_CAP_X86_USER_SPACE_MSR:
4411 case KVM_CAP_X86_MSR_FILTER:
4412 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4413 #ifdef CONFIG_X86_SGX_KVM
4414 case KVM_CAP_SGX_ATTRIBUTE:
4416 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4417 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4418 case KVM_CAP_SREGS2:
4419 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4420 case KVM_CAP_VCPU_ATTRIBUTES:
4421 case KVM_CAP_SYS_ATTRIBUTES:
4423 case KVM_CAP_ENABLE_CAP:
4424 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
4427 case KVM_CAP_EXIT_HYPERCALL:
4428 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4430 case KVM_CAP_SET_GUEST_DEBUG2:
4431 return KVM_GUESTDBG_VALID_MASK;
4432 #ifdef CONFIG_KVM_XEN
4433 case KVM_CAP_XEN_HVM:
4434 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4435 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4436 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4437 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4438 KVM_XEN_HVM_CONFIG_EVTCHN_SEND;
4439 if (sched_info_on())
4440 r |= KVM_XEN_HVM_CONFIG_RUNSTATE |
4441 KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG;
4444 case KVM_CAP_SYNC_REGS:
4445 r = KVM_SYNC_X86_VALID_FIELDS;
4447 case KVM_CAP_ADJUST_CLOCK:
4448 r = KVM_CLOCK_VALID_FLAGS;
4450 case KVM_CAP_X86_DISABLE_EXITS:
4451 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
4452 KVM_X86_DISABLE_EXITS_CSTATE;
4453 if(kvm_can_mwait_in_guest())
4454 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4456 case KVM_CAP_X86_SMM:
4457 if (!IS_ENABLED(CONFIG_KVM_SMM))
4460 /* SMBASE is usually relocated above 1M on modern chipsets,
4461 * and SMM handlers might indeed rely on 4G segment limits,
4462 * so do not report SMM to be available if real mode is
4463 * emulated via vm86 mode. Still, do not go to great lengths
4464 * to avoid userspace's usage of the feature, because it is a
4465 * fringe case that is not enabled except via specific settings
4466 * of the module parameters.
4468 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4470 case KVM_CAP_NR_VCPUS:
4471 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4473 case KVM_CAP_MAX_VCPUS:
4476 case KVM_CAP_MAX_VCPU_ID:
4477 r = KVM_MAX_VCPU_IDS;
4479 case KVM_CAP_PV_MMU: /* obsolete */
4483 r = KVM_MAX_MCE_BANKS;
4486 r = boot_cpu_has(X86_FEATURE_XSAVE);
4488 case KVM_CAP_TSC_CONTROL:
4489 case KVM_CAP_VM_TSC_CONTROL:
4490 r = kvm_caps.has_tsc_control;
4492 case KVM_CAP_X2APIC_API:
4493 r = KVM_X2APIC_API_VALID_FLAGS;
4495 case KVM_CAP_NESTED_STATE:
4496 r = kvm_x86_ops.nested_ops->get_state ?
4497 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4499 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4500 r = kvm_x86_ops.enable_l2_tlb_flush != NULL;
4502 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4503 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4505 case KVM_CAP_SMALLER_MAXPHYADDR:
4506 r = (int) allow_smaller_maxphyaddr;
4508 case KVM_CAP_STEAL_TIME:
4509 r = sched_info_on();
4511 case KVM_CAP_X86_BUS_LOCK_EXIT:
4512 if (kvm_caps.has_bus_lock_exit)
4513 r = KVM_BUS_LOCK_DETECTION_OFF |
4514 KVM_BUS_LOCK_DETECTION_EXIT;
4518 case KVM_CAP_XSAVE2: {
4519 u64 guest_perm = xstate_get_guest_group_perm();
4521 r = xstate_required_size(kvm_caps.supported_xcr0 & guest_perm, false);
4522 if (r < sizeof(struct kvm_xsave))
4523 r = sizeof(struct kvm_xsave);
4526 case KVM_CAP_PMU_CAPABILITY:
4527 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4529 case KVM_CAP_DISABLE_QUIRKS2:
4530 r = KVM_X86_VALID_QUIRKS;
4532 case KVM_CAP_X86_NOTIFY_VMEXIT:
4533 r = kvm_caps.has_notify_vmexit;
4541 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4543 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4545 if ((u64)(unsigned long)uaddr != attr->addr)
4546 return ERR_PTR_USR(-EFAULT);
4550 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4552 u64 __user *uaddr = kvm_get_attr_addr(attr);
4558 return PTR_ERR(uaddr);
4560 switch (attr->attr) {
4561 case KVM_X86_XCOMP_GUEST_SUPP:
4562 if (put_user(kvm_caps.supported_xcr0, uaddr))
4571 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4576 switch (attr->attr) {
4577 case KVM_X86_XCOMP_GUEST_SUPP:
4584 long kvm_arch_dev_ioctl(struct file *filp,
4585 unsigned int ioctl, unsigned long arg)
4587 void __user *argp = (void __user *)arg;
4591 case KVM_GET_MSR_INDEX_LIST: {
4592 struct kvm_msr_list __user *user_msr_list = argp;
4593 struct kvm_msr_list msr_list;
4597 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4600 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4601 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4604 if (n < msr_list.nmsrs)
4607 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4608 num_msrs_to_save * sizeof(u32)))
4610 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4612 num_emulated_msrs * sizeof(u32)))
4617 case KVM_GET_SUPPORTED_CPUID:
4618 case KVM_GET_EMULATED_CPUID: {
4619 struct kvm_cpuid2 __user *cpuid_arg = argp;
4620 struct kvm_cpuid2 cpuid;
4623 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4626 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4632 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4637 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4639 if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
4640 sizeof(kvm_caps.supported_mce_cap)))
4644 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4645 struct kvm_msr_list __user *user_msr_list = argp;
4646 struct kvm_msr_list msr_list;
4650 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4653 msr_list.nmsrs = num_msr_based_features;
4654 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4657 if (n < msr_list.nmsrs)
4660 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4661 num_msr_based_features * sizeof(u32)))
4667 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4669 case KVM_GET_SUPPORTED_HV_CPUID:
4670 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4672 case KVM_GET_DEVICE_ATTR: {
4673 struct kvm_device_attr attr;
4675 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4677 r = kvm_x86_dev_get_attr(&attr);
4680 case KVM_HAS_DEVICE_ATTR: {
4681 struct kvm_device_attr attr;
4683 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4685 r = kvm_x86_dev_has_attr(&attr);
4696 static void wbinvd_ipi(void *garbage)
4701 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4703 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4706 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4708 /* Address WBINVD may be executed by guest */
4709 if (need_emulate_wbinvd(vcpu)) {
4710 if (static_call(kvm_x86_has_wbinvd_exit)())
4711 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4712 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4713 smp_call_function_single(vcpu->cpu,
4714 wbinvd_ipi, NULL, 1);
4717 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4719 /* Save host pkru register if supported */
4720 vcpu->arch.host_pkru = read_pkru();
4722 /* Apply any externally detected TSC adjustments (due to suspend) */
4723 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4724 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4725 vcpu->arch.tsc_offset_adjustment = 0;
4726 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4729 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4730 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4731 rdtsc() - vcpu->arch.last_host_tsc;
4733 mark_tsc_unstable("KVM discovered backwards TSC");
4735 if (kvm_check_tsc_unstable()) {
4736 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4737 vcpu->arch.last_guest_tsc);
4738 kvm_vcpu_write_tsc_offset(vcpu, offset);
4739 vcpu->arch.tsc_catchup = 1;
4742 if (kvm_lapic_hv_timer_in_use(vcpu))
4743 kvm_lapic_restart_hv_timer(vcpu);
4746 * On a host with synchronized TSC, there is no need to update
4747 * kvmclock on vcpu->cpu migration
4749 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4750 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4751 if (vcpu->cpu != cpu)
4752 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4756 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4759 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4761 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4762 struct kvm_steal_time __user *st;
4763 struct kvm_memslots *slots;
4764 static const u8 preempted = KVM_VCPU_PREEMPTED;
4765 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
4768 * The vCPU can be marked preempted if and only if the VM-Exit was on
4769 * an instruction boundary and will not trigger guest emulation of any
4770 * kind (see vcpu_run). Vendor specific code controls (conservatively)
4771 * when this is true, for example allowing the vCPU to be marked
4772 * preempted if and only if the VM-Exit was due to a host interrupt.
4774 if (!vcpu->arch.at_instruction_boundary) {
4775 vcpu->stat.preemption_other++;
4779 vcpu->stat.preemption_reported++;
4780 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4783 if (vcpu->arch.st.preempted)
4786 /* This happens on process exit */
4787 if (unlikely(current->mm != vcpu->kvm->mm))
4790 slots = kvm_memslots(vcpu->kvm);
4792 if (unlikely(slots->generation != ghc->generation ||
4794 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4797 st = (struct kvm_steal_time __user *)ghc->hva;
4798 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4800 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4801 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4803 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4806 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4810 if (vcpu->preempted) {
4811 if (!vcpu->arch.guest_state_protected)
4812 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4815 * Take the srcu lock as memslots will be accessed to check the gfn
4816 * cache generation against the memslots generation.
4818 idx = srcu_read_lock(&vcpu->kvm->srcu);
4819 if (kvm_xen_msr_enabled(vcpu->kvm))
4820 kvm_xen_runstate_set_preempted(vcpu);
4822 kvm_steal_time_set_preempted(vcpu);
4823 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4826 static_call(kvm_x86_vcpu_put)(vcpu);
4827 vcpu->arch.last_host_tsc = rdtsc();
4830 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4831 struct kvm_lapic_state *s)
4833 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4835 return kvm_apic_get_state(vcpu, s);
4838 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4839 struct kvm_lapic_state *s)
4843 r = kvm_apic_set_state(vcpu, s);
4846 update_cr8_intercept(vcpu);
4851 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4854 * We can accept userspace's request for interrupt injection
4855 * as long as we have a place to store the interrupt number.
4856 * The actual injection will happen when the CPU is able to
4857 * deliver the interrupt.
4859 if (kvm_cpu_has_extint(vcpu))
4862 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4863 return (!lapic_in_kernel(vcpu) ||
4864 kvm_apic_accept_pic_intr(vcpu));
4867 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4870 * Do not cause an interrupt window exit if an exception
4871 * is pending or an event needs reinjection; userspace
4872 * might want to inject the interrupt manually using KVM_SET_REGS
4873 * or KVM_SET_SREGS. For that to work, we must be at an
4874 * instruction boundary and with no events half-injected.
4876 return (kvm_arch_interrupt_allowed(vcpu) &&
4877 kvm_cpu_accept_dm_intr(vcpu) &&
4878 !kvm_event_needs_reinjection(vcpu) &&
4879 !kvm_is_exception_pending(vcpu));
4882 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4883 struct kvm_interrupt *irq)
4885 if (irq->irq >= KVM_NR_INTERRUPTS)
4888 if (!irqchip_in_kernel(vcpu->kvm)) {
4889 kvm_queue_interrupt(vcpu, irq->irq, false);
4890 kvm_make_request(KVM_REQ_EVENT, vcpu);
4895 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4896 * fail for in-kernel 8259.
4898 if (pic_in_kernel(vcpu->kvm))
4901 if (vcpu->arch.pending_external_vector != -1)
4904 vcpu->arch.pending_external_vector = irq->irq;
4905 kvm_make_request(KVM_REQ_EVENT, vcpu);
4909 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4911 kvm_inject_nmi(vcpu);
4916 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4917 struct kvm_tpr_access_ctl *tac)
4921 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4925 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4929 unsigned bank_num = mcg_cap & 0xff, bank;
4932 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4934 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
4937 vcpu->arch.mcg_cap = mcg_cap;
4938 /* Init IA32_MCG_CTL to all 1s */
4939 if (mcg_cap & MCG_CTL_P)
4940 vcpu->arch.mcg_ctl = ~(u64)0;
4941 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
4942 for (bank = 0; bank < bank_num; bank++) {
4943 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4944 if (mcg_cap & MCG_CMCI_P)
4945 vcpu->arch.mci_ctl2_banks[bank] = 0;
4948 kvm_apic_after_set_mcg_cap(vcpu);
4950 static_call(kvm_x86_setup_mce)(vcpu);
4956 * Validate this is an UCNA (uncorrectable no action) error by checking the
4957 * MCG_STATUS and MCi_STATUS registers:
4958 * - none of the bits for Machine Check Exceptions are set
4959 * - both the VAL (valid) and UC (uncorrectable) bits are set
4960 * MCI_STATUS_PCC - Processor Context Corrupted
4961 * MCI_STATUS_S - Signaled as a Machine Check Exception
4962 * MCI_STATUS_AR - Software recoverable Action Required
4964 static bool is_ucna(struct kvm_x86_mce *mce)
4966 return !mce->mcg_status &&
4967 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) &&
4968 (mce->status & MCI_STATUS_VAL) &&
4969 (mce->status & MCI_STATUS_UC);
4972 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks)
4974 u64 mcg_cap = vcpu->arch.mcg_cap;
4976 banks[1] = mce->status;
4977 banks[2] = mce->addr;
4978 banks[3] = mce->misc;
4979 vcpu->arch.mcg_status = mce->mcg_status;
4981 if (!(mcg_cap & MCG_CMCI_P) ||
4982 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
4985 if (lapic_in_kernel(vcpu))
4986 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);
4991 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4992 struct kvm_x86_mce *mce)
4994 u64 mcg_cap = vcpu->arch.mcg_cap;
4995 unsigned bank_num = mcg_cap & 0xff;
4996 u64 *banks = vcpu->arch.mce_banks;
4998 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
5001 banks += array_index_nospec(4 * mce->bank, 4 * bank_num);
5004 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks);
5007 * if IA32_MCG_CTL is not all 1s, the uncorrected error
5008 * reporting is disabled
5010 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
5011 vcpu->arch.mcg_ctl != ~(u64)0)
5014 * if IA32_MCi_CTL is not all 1s, the uncorrected error
5015 * reporting is disabled for the bank
5017 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
5019 if (mce->status & MCI_STATUS_UC) {
5020 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
5021 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
5022 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5025 if (banks[1] & MCI_STATUS_VAL)
5026 mce->status |= MCI_STATUS_OVER;
5027 banks[2] = mce->addr;
5028 banks[3] = mce->misc;
5029 vcpu->arch.mcg_status = mce->mcg_status;
5030 banks[1] = mce->status;
5031 kvm_queue_exception(vcpu, MC_VECTOR);
5032 } else if (!(banks[1] & MCI_STATUS_VAL)
5033 || !(banks[1] & MCI_STATUS_UC)) {
5034 if (banks[1] & MCI_STATUS_VAL)
5035 mce->status |= MCI_STATUS_OVER;
5036 banks[2] = mce->addr;
5037 banks[3] = mce->misc;
5038 banks[1] = mce->status;
5040 banks[1] |= MCI_STATUS_OVER;
5044 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
5045 struct kvm_vcpu_events *events)
5047 struct kvm_queued_exception *ex;
5051 #ifdef CONFIG_KVM_SMM
5052 if (kvm_check_request(KVM_REQ_SMI, vcpu))
5057 * KVM's ABI only allows for one exception to be migrated. Luckily,
5058 * the only time there can be two queued exceptions is if there's a
5059 * non-exiting _injected_ exception, and a pending exiting exception.
5060 * In that case, ignore the VM-Exiting exception as it's an extension
5061 * of the injected exception.
5063 if (vcpu->arch.exception_vmexit.pending &&
5064 !vcpu->arch.exception.pending &&
5065 !vcpu->arch.exception.injected)
5066 ex = &vcpu->arch.exception_vmexit;
5068 ex = &vcpu->arch.exception;
5071 * In guest mode, payload delivery should be deferred if the exception
5072 * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1
5073 * intercepts #PF, ditto for DR6 and #DBs. If the per-VM capability,
5074 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not
5075 * propagate the payload and so it cannot be safely deferred. Deliver
5076 * the payload if the capability hasn't been requested.
5078 if (!vcpu->kvm->arch.exception_payload_enabled &&
5079 ex->pending && ex->has_payload)
5080 kvm_deliver_exception_payload(vcpu, ex);
5082 memset(events, 0, sizeof(*events));
5085 * The API doesn't provide the instruction length for software
5086 * exceptions, so don't report them. As long as the guest RIP
5087 * isn't advanced, we should expect to encounter the exception
5090 if (!kvm_exception_is_soft(ex->vector)) {
5091 events->exception.injected = ex->injected;
5092 events->exception.pending = ex->pending;
5094 * For ABI compatibility, deliberately conflate
5095 * pending and injected exceptions when
5096 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
5098 if (!vcpu->kvm->arch.exception_payload_enabled)
5099 events->exception.injected |= ex->pending;
5101 events->exception.nr = ex->vector;
5102 events->exception.has_error_code = ex->has_error_code;
5103 events->exception.error_code = ex->error_code;
5104 events->exception_has_payload = ex->has_payload;
5105 events->exception_payload = ex->payload;
5107 events->interrupt.injected =
5108 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
5109 events->interrupt.nr = vcpu->arch.interrupt.nr;
5110 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
5112 events->nmi.injected = vcpu->arch.nmi_injected;
5113 events->nmi.pending = vcpu->arch.nmi_pending != 0;
5114 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
5116 /* events->sipi_vector is never valid when reporting to user space */
5118 #ifdef CONFIG_KVM_SMM
5119 events->smi.smm = is_smm(vcpu);
5120 events->smi.pending = vcpu->arch.smi_pending;
5121 events->smi.smm_inside_nmi =
5122 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
5124 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
5126 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
5127 | KVM_VCPUEVENT_VALID_SHADOW
5128 | KVM_VCPUEVENT_VALID_SMM);
5129 if (vcpu->kvm->arch.exception_payload_enabled)
5130 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5131 if (vcpu->kvm->arch.triple_fault_event) {
5132 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5133 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5137 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
5138 struct kvm_vcpu_events *events)
5140 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
5141 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
5142 | KVM_VCPUEVENT_VALID_SHADOW
5143 | KVM_VCPUEVENT_VALID_SMM
5144 | KVM_VCPUEVENT_VALID_PAYLOAD
5145 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
5148 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5149 if (!vcpu->kvm->arch.exception_payload_enabled)
5151 if (events->exception.pending)
5152 events->exception.injected = 0;
5154 events->exception_has_payload = 0;
5156 events->exception.pending = 0;
5157 events->exception_has_payload = 0;
5160 if ((events->exception.injected || events->exception.pending) &&
5161 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
5164 /* INITs are latched while in SMM */
5165 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
5166 (events->smi.smm || events->smi.pending) &&
5167 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
5173 * Flag that userspace is stuffing an exception, the next KVM_RUN will
5174 * morph the exception to a VM-Exit if appropriate. Do this only for
5175 * pending exceptions, already-injected exceptions are not subject to
5176 * intercpetion. Note, userspace that conflates pending and injected
5177 * is hosed, and will incorrectly convert an injected exception into a
5178 * pending exception, which in turn may cause a spurious VM-Exit.
5180 vcpu->arch.exception_from_userspace = events->exception.pending;
5182 vcpu->arch.exception_vmexit.pending = false;
5184 vcpu->arch.exception.injected = events->exception.injected;
5185 vcpu->arch.exception.pending = events->exception.pending;
5186 vcpu->arch.exception.vector = events->exception.nr;
5187 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
5188 vcpu->arch.exception.error_code = events->exception.error_code;
5189 vcpu->arch.exception.has_payload = events->exception_has_payload;
5190 vcpu->arch.exception.payload = events->exception_payload;
5192 vcpu->arch.interrupt.injected = events->interrupt.injected;
5193 vcpu->arch.interrupt.nr = events->interrupt.nr;
5194 vcpu->arch.interrupt.soft = events->interrupt.soft;
5195 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
5196 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
5197 events->interrupt.shadow);
5199 vcpu->arch.nmi_injected = events->nmi.injected;
5200 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
5201 vcpu->arch.nmi_pending = events->nmi.pending;
5202 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
5204 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
5205 lapic_in_kernel(vcpu))
5206 vcpu->arch.apic->sipi_vector = events->sipi_vector;
5208 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
5209 #ifdef CONFIG_KVM_SMM
5210 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
5211 kvm_leave_nested(vcpu);
5212 kvm_smm_changed(vcpu, events->smi.smm);
5215 vcpu->arch.smi_pending = events->smi.pending;
5217 if (events->smi.smm) {
5218 if (events->smi.smm_inside_nmi)
5219 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
5221 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
5225 if (events->smi.smm || events->smi.pending ||
5226 events->smi.smm_inside_nmi)
5230 if (lapic_in_kernel(vcpu)) {
5231 if (events->smi.latched_init)
5232 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5234 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5238 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5239 if (!vcpu->kvm->arch.triple_fault_event)
5241 if (events->triple_fault.pending)
5242 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5244 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5247 kvm_make_request(KVM_REQ_EVENT, vcpu);
5252 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
5253 struct kvm_debugregs *dbgregs)
5257 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5258 kvm_get_dr(vcpu, 6, &val);
5260 dbgregs->dr7 = vcpu->arch.dr7;
5262 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
5265 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5266 struct kvm_debugregs *dbgregs)
5271 if (!kvm_dr6_valid(dbgregs->dr6))
5273 if (!kvm_dr7_valid(dbgregs->dr7))
5276 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5277 kvm_update_dr0123(vcpu);
5278 vcpu->arch.dr6 = dbgregs->dr6;
5279 vcpu->arch.dr7 = dbgregs->dr7;
5280 kvm_update_dr7(vcpu);
5285 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5286 struct kvm_xsave *guest_xsave)
5288 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5291 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5292 guest_xsave->region,
5293 sizeof(guest_xsave->region),
5297 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5298 u8 *state, unsigned int size)
5300 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5303 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5304 state, size, vcpu->arch.pkru);
5307 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5308 struct kvm_xsave *guest_xsave)
5310 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5313 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5314 guest_xsave->region,
5315 kvm_caps.supported_xcr0,
5319 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5320 struct kvm_xcrs *guest_xcrs)
5322 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5323 guest_xcrs->nr_xcrs = 0;
5327 guest_xcrs->nr_xcrs = 1;
5328 guest_xcrs->flags = 0;
5329 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5330 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5333 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5334 struct kvm_xcrs *guest_xcrs)
5338 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5341 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5344 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5345 /* Only support XCR0 currently */
5346 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5347 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5348 guest_xcrs->xcrs[i].value);
5357 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5358 * stopped by the hypervisor. This function will be called from the host only.
5359 * EINVAL is returned when the host attempts to set the flag for a guest that
5360 * does not support pv clocks.
5362 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5364 if (!vcpu->arch.pv_time.active)
5366 vcpu->arch.pvclock_set_guest_stopped_request = true;
5367 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5371 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5372 struct kvm_device_attr *attr)
5376 switch (attr->attr) {
5377 case KVM_VCPU_TSC_OFFSET:
5387 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5388 struct kvm_device_attr *attr)
5390 u64 __user *uaddr = kvm_get_attr_addr(attr);
5394 return PTR_ERR(uaddr);
5396 switch (attr->attr) {
5397 case KVM_VCPU_TSC_OFFSET:
5399 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5410 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5411 struct kvm_device_attr *attr)
5413 u64 __user *uaddr = kvm_get_attr_addr(attr);
5414 struct kvm *kvm = vcpu->kvm;
5418 return PTR_ERR(uaddr);
5420 switch (attr->attr) {
5421 case KVM_VCPU_TSC_OFFSET: {
5422 u64 offset, tsc, ns;
5423 unsigned long flags;
5427 if (get_user(offset, uaddr))
5430 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5432 matched = (vcpu->arch.virtual_tsc_khz &&
5433 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5434 kvm->arch.last_tsc_offset == offset);
5436 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5437 ns = get_kvmclock_base_ns();
5439 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5440 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5452 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5456 struct kvm_device_attr attr;
5459 if (copy_from_user(&attr, argp, sizeof(attr)))
5462 if (attr.group != KVM_VCPU_TSC_CTRL)
5466 case KVM_HAS_DEVICE_ATTR:
5467 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5469 case KVM_GET_DEVICE_ATTR:
5470 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5472 case KVM_SET_DEVICE_ATTR:
5473 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5480 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5481 struct kvm_enable_cap *cap)
5484 uint16_t vmcs_version;
5485 void __user *user_ptr;
5491 case KVM_CAP_HYPERV_SYNIC2:
5496 case KVM_CAP_HYPERV_SYNIC:
5497 if (!irqchip_in_kernel(vcpu->kvm))
5499 return kvm_hv_activate_synic(vcpu, cap->cap ==
5500 KVM_CAP_HYPERV_SYNIC2);
5501 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5502 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5504 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5506 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5507 if (copy_to_user(user_ptr, &vmcs_version,
5508 sizeof(vmcs_version)))
5512 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5513 if (!kvm_x86_ops.enable_l2_tlb_flush)
5516 return static_call(kvm_x86_enable_l2_tlb_flush)(vcpu);
5518 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5519 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5521 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5522 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5523 if (vcpu->arch.pv_cpuid.enforce)
5524 kvm_update_pv_runtime(vcpu);
5532 long kvm_arch_vcpu_ioctl(struct file *filp,
5533 unsigned int ioctl, unsigned long arg)
5535 struct kvm_vcpu *vcpu = filp->private_data;
5536 void __user *argp = (void __user *)arg;
5539 struct kvm_sregs2 *sregs2;
5540 struct kvm_lapic_state *lapic;
5541 struct kvm_xsave *xsave;
5542 struct kvm_xcrs *xcrs;
5550 case KVM_GET_LAPIC: {
5552 if (!lapic_in_kernel(vcpu))
5554 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5555 GFP_KERNEL_ACCOUNT);
5560 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5564 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5569 case KVM_SET_LAPIC: {
5571 if (!lapic_in_kernel(vcpu))
5573 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5574 if (IS_ERR(u.lapic)) {
5575 r = PTR_ERR(u.lapic);
5579 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5582 case KVM_INTERRUPT: {
5583 struct kvm_interrupt irq;
5586 if (copy_from_user(&irq, argp, sizeof(irq)))
5588 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5592 r = kvm_vcpu_ioctl_nmi(vcpu);
5596 r = kvm_inject_smi(vcpu);
5599 case KVM_SET_CPUID: {
5600 struct kvm_cpuid __user *cpuid_arg = argp;
5601 struct kvm_cpuid cpuid;
5604 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5606 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5609 case KVM_SET_CPUID2: {
5610 struct kvm_cpuid2 __user *cpuid_arg = argp;
5611 struct kvm_cpuid2 cpuid;
5614 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5616 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5617 cpuid_arg->entries);
5620 case KVM_GET_CPUID2: {
5621 struct kvm_cpuid2 __user *cpuid_arg = argp;
5622 struct kvm_cpuid2 cpuid;
5625 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5627 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5628 cpuid_arg->entries);
5632 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5637 case KVM_GET_MSRS: {
5638 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5639 r = msr_io(vcpu, argp, do_get_msr, 1);
5640 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5643 case KVM_SET_MSRS: {
5644 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5645 r = msr_io(vcpu, argp, do_set_msr, 0);
5646 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5649 case KVM_TPR_ACCESS_REPORTING: {
5650 struct kvm_tpr_access_ctl tac;
5653 if (copy_from_user(&tac, argp, sizeof(tac)))
5655 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5659 if (copy_to_user(argp, &tac, sizeof(tac)))
5664 case KVM_SET_VAPIC_ADDR: {
5665 struct kvm_vapic_addr va;
5669 if (!lapic_in_kernel(vcpu))
5672 if (copy_from_user(&va, argp, sizeof(va)))
5674 idx = srcu_read_lock(&vcpu->kvm->srcu);
5675 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5676 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5679 case KVM_X86_SETUP_MCE: {
5683 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5685 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5688 case KVM_X86_SET_MCE: {
5689 struct kvm_x86_mce mce;
5692 if (copy_from_user(&mce, argp, sizeof(mce)))
5694 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5697 case KVM_GET_VCPU_EVENTS: {
5698 struct kvm_vcpu_events events;
5700 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5703 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5708 case KVM_SET_VCPU_EVENTS: {
5709 struct kvm_vcpu_events events;
5712 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5715 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5718 case KVM_GET_DEBUGREGS: {
5719 struct kvm_debugregs dbgregs;
5721 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5724 if (copy_to_user(argp, &dbgregs,
5725 sizeof(struct kvm_debugregs)))
5730 case KVM_SET_DEBUGREGS: {
5731 struct kvm_debugregs dbgregs;
5734 if (copy_from_user(&dbgregs, argp,
5735 sizeof(struct kvm_debugregs)))
5738 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5741 case KVM_GET_XSAVE: {
5743 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5746 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5751 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5754 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5759 case KVM_SET_XSAVE: {
5760 int size = vcpu->arch.guest_fpu.uabi_size;
5762 u.xsave = memdup_user(argp, size);
5763 if (IS_ERR(u.xsave)) {
5764 r = PTR_ERR(u.xsave);
5768 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5772 case KVM_GET_XSAVE2: {
5773 int size = vcpu->arch.guest_fpu.uabi_size;
5775 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5780 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5783 if (copy_to_user(argp, u.xsave, size))
5790 case KVM_GET_XCRS: {
5791 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5796 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5799 if (copy_to_user(argp, u.xcrs,
5800 sizeof(struct kvm_xcrs)))
5805 case KVM_SET_XCRS: {
5806 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5807 if (IS_ERR(u.xcrs)) {
5808 r = PTR_ERR(u.xcrs);
5812 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5815 case KVM_SET_TSC_KHZ: {
5819 user_tsc_khz = (u32)arg;
5821 if (kvm_caps.has_tsc_control &&
5822 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
5825 if (user_tsc_khz == 0)
5826 user_tsc_khz = tsc_khz;
5828 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5833 case KVM_GET_TSC_KHZ: {
5834 r = vcpu->arch.virtual_tsc_khz;
5837 case KVM_KVMCLOCK_CTRL: {
5838 r = kvm_set_guest_paused(vcpu);
5841 case KVM_ENABLE_CAP: {
5842 struct kvm_enable_cap cap;
5845 if (copy_from_user(&cap, argp, sizeof(cap)))
5847 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5850 case KVM_GET_NESTED_STATE: {
5851 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5855 if (!kvm_x86_ops.nested_ops->get_state)
5858 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5860 if (get_user(user_data_size, &user_kvm_nested_state->size))
5863 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5868 if (r > user_data_size) {
5869 if (put_user(r, &user_kvm_nested_state->size))
5879 case KVM_SET_NESTED_STATE: {
5880 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5881 struct kvm_nested_state kvm_state;
5885 if (!kvm_x86_ops.nested_ops->set_state)
5889 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5893 if (kvm_state.size < sizeof(kvm_state))
5896 if (kvm_state.flags &
5897 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5898 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5899 | KVM_STATE_NESTED_GIF_SET))
5902 /* nested_run_pending implies guest_mode. */
5903 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5904 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5907 idx = srcu_read_lock(&vcpu->kvm->srcu);
5908 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5909 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5912 case KVM_GET_SUPPORTED_HV_CPUID:
5913 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5915 #ifdef CONFIG_KVM_XEN
5916 case KVM_XEN_VCPU_GET_ATTR: {
5917 struct kvm_xen_vcpu_attr xva;
5920 if (copy_from_user(&xva, argp, sizeof(xva)))
5922 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
5923 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
5927 case KVM_XEN_VCPU_SET_ATTR: {
5928 struct kvm_xen_vcpu_attr xva;
5931 if (copy_from_user(&xva, argp, sizeof(xva)))
5933 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
5937 case KVM_GET_SREGS2: {
5938 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
5942 __get_sregs2(vcpu, u.sregs2);
5944 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
5949 case KVM_SET_SREGS2: {
5950 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
5951 if (IS_ERR(u.sregs2)) {
5952 r = PTR_ERR(u.sregs2);
5956 r = __set_sregs2(vcpu, u.sregs2);
5959 case KVM_HAS_DEVICE_ATTR:
5960 case KVM_GET_DEVICE_ATTR:
5961 case KVM_SET_DEVICE_ATTR:
5962 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
5974 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5976 return VM_FAULT_SIGBUS;
5979 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5983 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5985 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
5989 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5992 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
5995 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5996 unsigned long kvm_nr_mmu_pages)
5998 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
6001 mutex_lock(&kvm->slots_lock);
6003 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
6004 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
6006 mutex_unlock(&kvm->slots_lock);
6010 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
6012 return kvm->arch.n_max_mmu_pages;
6015 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6017 struct kvm_pic *pic = kvm->arch.vpic;
6021 switch (chip->chip_id) {
6022 case KVM_IRQCHIP_PIC_MASTER:
6023 memcpy(&chip->chip.pic, &pic->pics[0],
6024 sizeof(struct kvm_pic_state));
6026 case KVM_IRQCHIP_PIC_SLAVE:
6027 memcpy(&chip->chip.pic, &pic->pics[1],
6028 sizeof(struct kvm_pic_state));
6030 case KVM_IRQCHIP_IOAPIC:
6031 kvm_get_ioapic(kvm, &chip->chip.ioapic);
6040 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6042 struct kvm_pic *pic = kvm->arch.vpic;
6046 switch (chip->chip_id) {
6047 case KVM_IRQCHIP_PIC_MASTER:
6048 spin_lock(&pic->lock);
6049 memcpy(&pic->pics[0], &chip->chip.pic,
6050 sizeof(struct kvm_pic_state));
6051 spin_unlock(&pic->lock);
6053 case KVM_IRQCHIP_PIC_SLAVE:
6054 spin_lock(&pic->lock);
6055 memcpy(&pic->pics[1], &chip->chip.pic,
6056 sizeof(struct kvm_pic_state));
6057 spin_unlock(&pic->lock);
6059 case KVM_IRQCHIP_IOAPIC:
6060 kvm_set_ioapic(kvm, &chip->chip.ioapic);
6066 kvm_pic_update_irq(pic);
6070 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6072 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
6074 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
6076 mutex_lock(&kps->lock);
6077 memcpy(ps, &kps->channels, sizeof(*ps));
6078 mutex_unlock(&kps->lock);
6082 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6085 struct kvm_pit *pit = kvm->arch.vpit;
6087 mutex_lock(&pit->pit_state.lock);
6088 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
6089 for (i = 0; i < 3; i++)
6090 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
6091 mutex_unlock(&pit->pit_state.lock);
6095 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6097 mutex_lock(&kvm->arch.vpit->pit_state.lock);
6098 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
6099 sizeof(ps->channels));
6100 ps->flags = kvm->arch.vpit->pit_state.flags;
6101 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
6102 memset(&ps->reserved, 0, sizeof(ps->reserved));
6106 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6110 u32 prev_legacy, cur_legacy;
6111 struct kvm_pit *pit = kvm->arch.vpit;
6113 mutex_lock(&pit->pit_state.lock);
6114 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
6115 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
6116 if (!prev_legacy && cur_legacy)
6118 memcpy(&pit->pit_state.channels, &ps->channels,
6119 sizeof(pit->pit_state.channels));
6120 pit->pit_state.flags = ps->flags;
6121 for (i = 0; i < 3; i++)
6122 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
6124 mutex_unlock(&pit->pit_state.lock);
6128 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
6129 struct kvm_reinject_control *control)
6131 struct kvm_pit *pit = kvm->arch.vpit;
6133 /* pit->pit_state.lock was overloaded to prevent userspace from getting
6134 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
6135 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
6137 mutex_lock(&pit->pit_state.lock);
6138 kvm_pit_set_reinject(pit, control->pit_reinject);
6139 mutex_unlock(&pit->pit_state.lock);
6144 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
6148 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
6149 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
6150 * on all VM-Exits, thus we only need to kick running vCPUs to force a
6153 struct kvm_vcpu *vcpu;
6156 kvm_for_each_vcpu(i, vcpu, kvm)
6157 kvm_vcpu_kick(vcpu);
6160 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
6163 if (!irqchip_in_kernel(kvm))
6166 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
6167 irq_event->irq, irq_event->level,
6172 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
6173 struct kvm_enable_cap *cap)
6181 case KVM_CAP_DISABLE_QUIRKS2:
6183 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
6186 case KVM_CAP_DISABLE_QUIRKS:
6187 kvm->arch.disabled_quirks = cap->args[0];
6190 case KVM_CAP_SPLIT_IRQCHIP: {
6191 mutex_lock(&kvm->lock);
6193 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
6194 goto split_irqchip_unlock;
6196 if (irqchip_in_kernel(kvm))
6197 goto split_irqchip_unlock;
6198 if (kvm->created_vcpus)
6199 goto split_irqchip_unlock;
6200 r = kvm_setup_empty_irq_routing(kvm);
6202 goto split_irqchip_unlock;
6203 /* Pairs with irqchip_in_kernel. */
6205 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
6206 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
6207 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6209 split_irqchip_unlock:
6210 mutex_unlock(&kvm->lock);
6213 case KVM_CAP_X2APIC_API:
6215 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
6218 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
6219 kvm->arch.x2apic_format = true;
6220 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
6221 kvm->arch.x2apic_broadcast_quirk_disabled = true;
6225 case KVM_CAP_X86_DISABLE_EXITS:
6227 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
6230 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
6231 kvm_can_mwait_in_guest())
6232 kvm->arch.mwait_in_guest = true;
6233 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
6234 kvm->arch.hlt_in_guest = true;
6235 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
6236 kvm->arch.pause_in_guest = true;
6237 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
6238 kvm->arch.cstate_in_guest = true;
6241 case KVM_CAP_MSR_PLATFORM_INFO:
6242 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
6245 case KVM_CAP_EXCEPTION_PAYLOAD:
6246 kvm->arch.exception_payload_enabled = cap->args[0];
6249 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
6250 kvm->arch.triple_fault_event = cap->args[0];
6253 case KVM_CAP_X86_USER_SPACE_MSR:
6255 if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK)
6257 kvm->arch.user_space_msr_mask = cap->args[0];
6260 case KVM_CAP_X86_BUS_LOCK_EXIT:
6262 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6265 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6266 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6269 if (kvm_caps.has_bus_lock_exit &&
6270 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6271 kvm->arch.bus_lock_detection_enabled = true;
6274 #ifdef CONFIG_X86_SGX_KVM
6275 case KVM_CAP_SGX_ATTRIBUTE: {
6276 unsigned long allowed_attributes = 0;
6278 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6282 /* KVM only supports the PROVISIONKEY privileged attribute. */
6283 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6284 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6285 kvm->arch.sgx_provisioning_allowed = true;
6291 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6293 if (!kvm_x86_ops.vm_copy_enc_context_from)
6296 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6298 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6300 if (!kvm_x86_ops.vm_move_enc_context_from)
6303 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6305 case KVM_CAP_EXIT_HYPERCALL:
6306 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6310 kvm->arch.hypercall_exit_enabled = cap->args[0];
6313 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6315 if (cap->args[0] & ~1)
6317 kvm->arch.exit_on_emulation_error = cap->args[0];
6320 case KVM_CAP_PMU_CAPABILITY:
6322 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6325 mutex_lock(&kvm->lock);
6326 if (!kvm->created_vcpus) {
6327 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6330 mutex_unlock(&kvm->lock);
6332 case KVM_CAP_MAX_VCPU_ID:
6334 if (cap->args[0] > KVM_MAX_VCPU_IDS)
6337 mutex_lock(&kvm->lock);
6338 if (kvm->arch.max_vcpu_ids == cap->args[0]) {
6340 } else if (!kvm->arch.max_vcpu_ids) {
6341 kvm->arch.max_vcpu_ids = cap->args[0];
6344 mutex_unlock(&kvm->lock);
6346 case KVM_CAP_X86_NOTIFY_VMEXIT:
6348 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
6350 if (!kvm_caps.has_notify_vmexit)
6352 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
6354 mutex_lock(&kvm->lock);
6355 if (!kvm->created_vcpus) {
6356 kvm->arch.notify_window = cap->args[0] >> 32;
6357 kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
6360 mutex_unlock(&kvm->lock);
6362 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
6366 * Since the risk of disabling NX hugepages is a guest crashing
6367 * the system, ensure the userspace process has permission to
6368 * reboot the system.
6370 * Note that unlike the reboot() syscall, the process must have
6371 * this capability in the root namespace because exposing
6372 * /dev/kvm into a container does not limit the scope of the
6373 * iTLB multihit bug to that container. In other words,
6374 * this must use capable(), not ns_capable().
6376 if (!capable(CAP_SYS_BOOT)) {
6384 mutex_lock(&kvm->lock);
6385 if (!kvm->created_vcpus) {
6386 kvm->arch.disable_nx_huge_pages = true;
6389 mutex_unlock(&kvm->lock);
6398 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6400 struct kvm_x86_msr_filter *msr_filter;
6402 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6406 msr_filter->default_allow = default_allow;
6410 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6417 for (i = 0; i < msr_filter->count; i++)
6418 kfree(msr_filter->ranges[i].bitmap);
6423 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6424 struct kvm_msr_filter_range *user_range)
6426 unsigned long *bitmap = NULL;
6429 if (!user_range->nmsrs)
6432 if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK)
6435 if (!user_range->flags)
6438 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6439 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6442 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6444 return PTR_ERR(bitmap);
6446 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6447 .flags = user_range->flags,
6448 .base = user_range->base,
6449 .nmsrs = user_range->nmsrs,
6453 msr_filter->count++;
6457 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm,
6458 struct kvm_msr_filter *filter)
6460 struct kvm_x86_msr_filter *new_filter, *old_filter;
6466 if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK)
6469 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++)
6470 empty &= !filter->ranges[i].nmsrs;
6472 default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY);
6473 if (empty && !default_allow)
6476 new_filter = kvm_alloc_msr_filter(default_allow);
6480 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) {
6481 r = kvm_add_msr_filter(new_filter, &filter->ranges[i]);
6483 kvm_free_msr_filter(new_filter);
6488 mutex_lock(&kvm->lock);
6490 /* The per-VM filter is protected by kvm->lock... */
6491 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1);
6493 rcu_assign_pointer(kvm->arch.msr_filter, new_filter);
6494 synchronize_srcu(&kvm->srcu);
6496 kvm_free_msr_filter(old_filter);
6498 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6499 mutex_unlock(&kvm->lock);
6504 #ifdef CONFIG_KVM_COMPAT
6505 /* for KVM_X86_SET_MSR_FILTER */
6506 struct kvm_msr_filter_range_compat {
6513 struct kvm_msr_filter_compat {
6515 struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES];
6518 #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat)
6520 long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl,
6523 void __user *argp = (void __user *)arg;
6524 struct kvm *kvm = filp->private_data;
6528 case KVM_X86_SET_MSR_FILTER_COMPAT: {
6529 struct kvm_msr_filter __user *user_msr_filter = argp;
6530 struct kvm_msr_filter_compat filter_compat;
6531 struct kvm_msr_filter filter;
6534 if (copy_from_user(&filter_compat, user_msr_filter,
6535 sizeof(filter_compat)))
6538 filter.flags = filter_compat.flags;
6539 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6540 struct kvm_msr_filter_range_compat *cr;
6542 cr = &filter_compat.ranges[i];
6543 filter.ranges[i] = (struct kvm_msr_filter_range) {
6547 .bitmap = (__u8 *)(ulong)cr->bitmap,
6551 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
6560 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6561 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6563 struct kvm_vcpu *vcpu;
6567 mutex_lock(&kvm->lock);
6568 kvm_for_each_vcpu(i, vcpu, kvm) {
6569 if (!vcpu->arch.pv_time.active)
6572 ret = kvm_set_guest_paused(vcpu);
6574 kvm_err("Failed to pause guest VCPU%d: %d\n",
6575 vcpu->vcpu_id, ret);
6579 mutex_unlock(&kvm->lock);
6581 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6584 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6587 case PM_HIBERNATION_PREPARE:
6588 case PM_SUSPEND_PREPARE:
6589 return kvm_arch_suspend_notifier(kvm);
6594 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6596 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6598 struct kvm_clock_data data = { 0 };
6600 get_kvmclock(kvm, &data);
6601 if (copy_to_user(argp, &data, sizeof(data)))
6607 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6609 struct kvm_arch *ka = &kvm->arch;
6610 struct kvm_clock_data data;
6613 if (copy_from_user(&data, argp, sizeof(data)))
6617 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6618 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6620 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6623 kvm_hv_request_tsc_page_update(kvm);
6624 kvm_start_pvclock_update(kvm);
6625 pvclock_update_vm_gtod_copy(kvm);
6628 * This pairs with kvm_guest_time_update(): when masterclock is
6629 * in use, we use master_kernel_ns + kvmclock_offset to set
6630 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6631 * is slightly ahead) here we risk going negative on unsigned
6632 * 'system_time' when 'data.clock' is very small.
6634 if (data.flags & KVM_CLOCK_REALTIME) {
6635 u64 now_real_ns = ktime_get_real_ns();
6638 * Avoid stepping the kvmclock backwards.
6640 if (now_real_ns > data.realtime)
6641 data.clock += now_real_ns - data.realtime;
6644 if (ka->use_master_clock)
6645 now_raw_ns = ka->master_kernel_ns;
6647 now_raw_ns = get_kvmclock_base_ns();
6648 ka->kvmclock_offset = data.clock - now_raw_ns;
6649 kvm_end_pvclock_update(kvm);
6653 long kvm_arch_vm_ioctl(struct file *filp,
6654 unsigned int ioctl, unsigned long arg)
6656 struct kvm *kvm = filp->private_data;
6657 void __user *argp = (void __user *)arg;
6660 * This union makes it completely explicit to gcc-3.x
6661 * that these two variables' stack usage should be
6662 * combined, not added together.
6665 struct kvm_pit_state ps;
6666 struct kvm_pit_state2 ps2;
6667 struct kvm_pit_config pit_config;
6671 case KVM_SET_TSS_ADDR:
6672 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6674 case KVM_SET_IDENTITY_MAP_ADDR: {
6677 mutex_lock(&kvm->lock);
6679 if (kvm->created_vcpus)
6680 goto set_identity_unlock;
6682 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6683 goto set_identity_unlock;
6684 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6685 set_identity_unlock:
6686 mutex_unlock(&kvm->lock);
6689 case KVM_SET_NR_MMU_PAGES:
6690 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6692 case KVM_GET_NR_MMU_PAGES:
6693 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
6695 case KVM_CREATE_IRQCHIP: {
6696 mutex_lock(&kvm->lock);
6699 if (irqchip_in_kernel(kvm))
6700 goto create_irqchip_unlock;
6703 if (kvm->created_vcpus)
6704 goto create_irqchip_unlock;
6706 r = kvm_pic_init(kvm);
6708 goto create_irqchip_unlock;
6710 r = kvm_ioapic_init(kvm);
6712 kvm_pic_destroy(kvm);
6713 goto create_irqchip_unlock;
6716 r = kvm_setup_default_irq_routing(kvm);
6718 kvm_ioapic_destroy(kvm);
6719 kvm_pic_destroy(kvm);
6720 goto create_irqchip_unlock;
6722 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6724 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6725 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6726 create_irqchip_unlock:
6727 mutex_unlock(&kvm->lock);
6730 case KVM_CREATE_PIT:
6731 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6733 case KVM_CREATE_PIT2:
6735 if (copy_from_user(&u.pit_config, argp,
6736 sizeof(struct kvm_pit_config)))
6739 mutex_lock(&kvm->lock);
6742 goto create_pit_unlock;
6744 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6748 mutex_unlock(&kvm->lock);
6750 case KVM_GET_IRQCHIP: {
6751 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6752 struct kvm_irqchip *chip;
6754 chip = memdup_user(argp, sizeof(*chip));
6761 if (!irqchip_kernel(kvm))
6762 goto get_irqchip_out;
6763 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6765 goto get_irqchip_out;
6767 if (copy_to_user(argp, chip, sizeof(*chip)))
6768 goto get_irqchip_out;
6774 case KVM_SET_IRQCHIP: {
6775 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6776 struct kvm_irqchip *chip;
6778 chip = memdup_user(argp, sizeof(*chip));
6785 if (!irqchip_kernel(kvm))
6786 goto set_irqchip_out;
6787 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6794 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6797 if (!kvm->arch.vpit)
6799 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6803 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6810 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6812 mutex_lock(&kvm->lock);
6814 if (!kvm->arch.vpit)
6816 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6818 mutex_unlock(&kvm->lock);
6821 case KVM_GET_PIT2: {
6823 if (!kvm->arch.vpit)
6825 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6829 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6834 case KVM_SET_PIT2: {
6836 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6838 mutex_lock(&kvm->lock);
6840 if (!kvm->arch.vpit)
6842 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6844 mutex_unlock(&kvm->lock);
6847 case KVM_REINJECT_CONTROL: {
6848 struct kvm_reinject_control control;
6850 if (copy_from_user(&control, argp, sizeof(control)))
6853 if (!kvm->arch.vpit)
6855 r = kvm_vm_ioctl_reinject(kvm, &control);
6858 case KVM_SET_BOOT_CPU_ID:
6860 mutex_lock(&kvm->lock);
6861 if (kvm->created_vcpus)
6864 kvm->arch.bsp_vcpu_id = arg;
6865 mutex_unlock(&kvm->lock);
6867 #ifdef CONFIG_KVM_XEN
6868 case KVM_XEN_HVM_CONFIG: {
6869 struct kvm_xen_hvm_config xhc;
6871 if (copy_from_user(&xhc, argp, sizeof(xhc)))
6873 r = kvm_xen_hvm_config(kvm, &xhc);
6876 case KVM_XEN_HVM_GET_ATTR: {
6877 struct kvm_xen_hvm_attr xha;
6880 if (copy_from_user(&xha, argp, sizeof(xha)))
6882 r = kvm_xen_hvm_get_attr(kvm, &xha);
6883 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
6887 case KVM_XEN_HVM_SET_ATTR: {
6888 struct kvm_xen_hvm_attr xha;
6891 if (copy_from_user(&xha, argp, sizeof(xha)))
6893 r = kvm_xen_hvm_set_attr(kvm, &xha);
6896 case KVM_XEN_HVM_EVTCHN_SEND: {
6897 struct kvm_irq_routing_xen_evtchn uxe;
6900 if (copy_from_user(&uxe, argp, sizeof(uxe)))
6902 r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
6907 r = kvm_vm_ioctl_set_clock(kvm, argp);
6910 r = kvm_vm_ioctl_get_clock(kvm, argp);
6912 case KVM_SET_TSC_KHZ: {
6916 user_tsc_khz = (u32)arg;
6918 if (kvm_caps.has_tsc_control &&
6919 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
6922 if (user_tsc_khz == 0)
6923 user_tsc_khz = tsc_khz;
6925 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
6930 case KVM_GET_TSC_KHZ: {
6931 r = READ_ONCE(kvm->arch.default_tsc_khz);
6934 case KVM_MEMORY_ENCRYPT_OP: {
6936 if (!kvm_x86_ops.mem_enc_ioctl)
6939 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
6942 case KVM_MEMORY_ENCRYPT_REG_REGION: {
6943 struct kvm_enc_region region;
6946 if (copy_from_user(®ion, argp, sizeof(region)))
6950 if (!kvm_x86_ops.mem_enc_register_region)
6953 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
6956 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
6957 struct kvm_enc_region region;
6960 if (copy_from_user(®ion, argp, sizeof(region)))
6964 if (!kvm_x86_ops.mem_enc_unregister_region)
6967 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
6970 case KVM_HYPERV_EVENTFD: {
6971 struct kvm_hyperv_eventfd hvevfd;
6974 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
6976 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
6979 case KVM_SET_PMU_EVENT_FILTER:
6980 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
6982 case KVM_X86_SET_MSR_FILTER: {
6983 struct kvm_msr_filter __user *user_msr_filter = argp;
6984 struct kvm_msr_filter filter;
6986 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
6989 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
6999 static void kvm_init_msr_list(void)
7004 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
7005 "Please update the fixed PMCs in msrs_to_saved_all[]");
7007 num_msrs_to_save = 0;
7008 num_emulated_msrs = 0;
7009 num_msr_based_features = 0;
7011 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
7012 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
7016 * Even MSRs that are valid in the host may not be exposed
7017 * to the guests in some cases.
7019 switch (msrs_to_save_all[i]) {
7020 case MSR_IA32_BNDCFGS:
7021 if (!kvm_mpx_supported())
7025 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
7026 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
7029 case MSR_IA32_UMWAIT_CONTROL:
7030 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
7033 case MSR_IA32_RTIT_CTL:
7034 case MSR_IA32_RTIT_STATUS:
7035 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
7038 case MSR_IA32_RTIT_CR3_MATCH:
7039 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7040 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
7043 case MSR_IA32_RTIT_OUTPUT_BASE:
7044 case MSR_IA32_RTIT_OUTPUT_MASK:
7045 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7046 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
7047 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
7050 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
7051 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7052 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
7053 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
7056 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
7057 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
7058 min(KVM_INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
7061 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
7062 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
7063 min(KVM_INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
7067 case MSR_IA32_XFD_ERR:
7068 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
7075 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
7078 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
7079 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
7082 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
7085 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
7086 struct kvm_msr_entry msr;
7088 msr.index = msr_based_features_all[i];
7089 if (kvm_get_msr_feature(&msr))
7092 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
7096 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
7104 if (!(lapic_in_kernel(vcpu) &&
7105 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
7106 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
7117 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
7124 if (!(lapic_in_kernel(vcpu) &&
7125 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
7127 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
7129 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
7139 void kvm_set_segment(struct kvm_vcpu *vcpu,
7140 struct kvm_segment *var, int seg)
7142 static_call(kvm_x86_set_segment)(vcpu, var, seg);
7145 void kvm_get_segment(struct kvm_vcpu *vcpu,
7146 struct kvm_segment *var, int seg)
7148 static_call(kvm_x86_get_segment)(vcpu, var, seg);
7151 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
7152 struct x86_exception *exception)
7154 struct kvm_mmu *mmu = vcpu->arch.mmu;
7157 BUG_ON(!mmu_is_nested(vcpu));
7159 /* NPT walks are always user-walks */
7160 access |= PFERR_USER_MASK;
7161 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
7166 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
7167 struct x86_exception *exception)
7169 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7171 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7172 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7174 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
7176 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
7177 struct x86_exception *exception)
7179 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7181 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7182 access |= PFERR_WRITE_MASK;
7183 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7185 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
7187 /* uses this to access any guest's mapped memory without checking CPL */
7188 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
7189 struct x86_exception *exception)
7191 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7193 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
7196 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7197 struct kvm_vcpu *vcpu, u64 access,
7198 struct x86_exception *exception)
7200 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7202 int r = X86EMUL_CONTINUE;
7205 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7206 unsigned offset = addr & (PAGE_SIZE-1);
7207 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
7210 if (gpa == INVALID_GPA)
7211 return X86EMUL_PROPAGATE_FAULT;
7212 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
7215 r = X86EMUL_IO_NEEDED;
7227 /* used for instruction fetching */
7228 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
7229 gva_t addr, void *val, unsigned int bytes,
7230 struct x86_exception *exception)
7232 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7233 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7234 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7238 /* Inline kvm_read_guest_virt_helper for speed. */
7239 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
7241 if (unlikely(gpa == INVALID_GPA))
7242 return X86EMUL_PROPAGATE_FAULT;
7244 offset = addr & (PAGE_SIZE-1);
7245 if (WARN_ON(offset + bytes > PAGE_SIZE))
7246 bytes = (unsigned)PAGE_SIZE - offset;
7247 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
7249 if (unlikely(ret < 0))
7250 return X86EMUL_IO_NEEDED;
7252 return X86EMUL_CONTINUE;
7255 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
7256 gva_t addr, void *val, unsigned int bytes,
7257 struct x86_exception *exception)
7259 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7262 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
7263 * is returned, but our callers are not ready for that and they blindly
7264 * call kvm_inject_page_fault. Ensure that they at least do not leak
7265 * uninitialized kernel stack memory into cr2 and error code.
7267 memset(exception, 0, sizeof(*exception));
7268 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
7271 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
7273 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
7274 gva_t addr, void *val, unsigned int bytes,
7275 struct x86_exception *exception, bool system)
7277 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7281 access |= PFERR_IMPLICIT_ACCESS;
7282 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7283 access |= PFERR_USER_MASK;
7285 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
7288 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7289 struct kvm_vcpu *vcpu, u64 access,
7290 struct x86_exception *exception)
7292 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7294 int r = X86EMUL_CONTINUE;
7297 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7298 unsigned offset = addr & (PAGE_SIZE-1);
7299 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
7302 if (gpa == INVALID_GPA)
7303 return X86EMUL_PROPAGATE_FAULT;
7304 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
7306 r = X86EMUL_IO_NEEDED;
7318 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
7319 unsigned int bytes, struct x86_exception *exception,
7322 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7323 u64 access = PFERR_WRITE_MASK;
7326 access |= PFERR_IMPLICIT_ACCESS;
7327 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7328 access |= PFERR_USER_MASK;
7330 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7334 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
7335 unsigned int bytes, struct x86_exception *exception)
7337 /* kvm_write_guest_virt_system can pull in tons of pages. */
7338 vcpu->arch.l1tf_flush_l1d = true;
7340 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7341 PFERR_WRITE_MASK, exception);
7343 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
7345 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
7346 void *insn, int insn_len)
7348 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
7352 int handle_ud(struct kvm_vcpu *vcpu)
7354 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
7355 int fep_flags = READ_ONCE(force_emulation_prefix);
7356 int emul_type = EMULTYPE_TRAP_UD;
7357 char sig[5]; /* ud2; .ascii "kvm" */
7358 struct x86_exception e;
7360 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
7364 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
7365 sig, sizeof(sig), &e) == 0 &&
7366 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
7367 if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF)
7368 kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF);
7369 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
7370 emul_type = EMULTYPE_TRAP_UD_FORCED;
7373 return kvm_emulate_instruction(vcpu, emul_type);
7375 EXPORT_SYMBOL_GPL(handle_ud);
7377 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7378 gpa_t gpa, bool write)
7380 /* For APIC access vmexit */
7381 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7384 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7385 trace_vcpu_match_mmio(gva, gpa, write, true);
7392 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7393 gpa_t *gpa, struct x86_exception *exception,
7396 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7397 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7398 | (write ? PFERR_WRITE_MASK : 0);
7401 * currently PKRU is only applied to ept enabled guest so
7402 * there is no pkey in EPT page table for L1 guest or EPT
7403 * shadow page table for L2 guest.
7405 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7406 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7407 vcpu->arch.mmio_access, 0, access))) {
7408 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7409 (gva & (PAGE_SIZE - 1));
7410 trace_vcpu_match_mmio(gva, *gpa, write, false);
7414 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7416 if (*gpa == INVALID_GPA)
7419 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7422 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7423 const void *val, int bytes)
7427 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7430 kvm_page_track_write(vcpu, gpa, val, bytes);
7434 struct read_write_emulator_ops {
7435 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7437 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7438 void *val, int bytes);
7439 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7440 int bytes, void *val);
7441 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7442 void *val, int bytes);
7446 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7448 if (vcpu->mmio_read_completed) {
7449 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7450 vcpu->mmio_fragments[0].gpa, val);
7451 vcpu->mmio_read_completed = 0;
7458 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7459 void *val, int bytes)
7461 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7464 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7465 void *val, int bytes)
7467 return emulator_write_phys(vcpu, gpa, val, bytes);
7470 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7472 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7473 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7476 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7477 void *val, int bytes)
7479 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7480 return X86EMUL_IO_NEEDED;
7483 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7484 void *val, int bytes)
7486 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7488 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7489 return X86EMUL_CONTINUE;
7492 static const struct read_write_emulator_ops read_emultor = {
7493 .read_write_prepare = read_prepare,
7494 .read_write_emulate = read_emulate,
7495 .read_write_mmio = vcpu_mmio_read,
7496 .read_write_exit_mmio = read_exit_mmio,
7499 static const struct read_write_emulator_ops write_emultor = {
7500 .read_write_emulate = write_emulate,
7501 .read_write_mmio = write_mmio,
7502 .read_write_exit_mmio = write_exit_mmio,
7506 static int emulator_read_write_onepage(unsigned long addr, void *val,
7508 struct x86_exception *exception,
7509 struct kvm_vcpu *vcpu,
7510 const struct read_write_emulator_ops *ops)
7514 bool write = ops->write;
7515 struct kvm_mmio_fragment *frag;
7516 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7519 * If the exit was due to a NPF we may already have a GPA.
7520 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7521 * Note, this cannot be used on string operations since string
7522 * operation using rep will only have the initial GPA from the NPF
7525 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7526 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7527 gpa = ctxt->gpa_val;
7528 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7530 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7532 return X86EMUL_PROPAGATE_FAULT;
7535 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7536 return X86EMUL_CONTINUE;
7539 * Is this MMIO handled locally?
7541 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7542 if (handled == bytes)
7543 return X86EMUL_CONTINUE;
7549 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7550 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7554 return X86EMUL_CONTINUE;
7557 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7559 void *val, unsigned int bytes,
7560 struct x86_exception *exception,
7561 const struct read_write_emulator_ops *ops)
7563 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7567 if (ops->read_write_prepare &&
7568 ops->read_write_prepare(vcpu, val, bytes))
7569 return X86EMUL_CONTINUE;
7571 vcpu->mmio_nr_fragments = 0;
7573 /* Crossing a page boundary? */
7574 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7577 now = -addr & ~PAGE_MASK;
7578 rc = emulator_read_write_onepage(addr, val, now, exception,
7581 if (rc != X86EMUL_CONTINUE)
7584 if (ctxt->mode != X86EMUL_MODE_PROT64)
7590 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7592 if (rc != X86EMUL_CONTINUE)
7595 if (!vcpu->mmio_nr_fragments)
7598 gpa = vcpu->mmio_fragments[0].gpa;
7600 vcpu->mmio_needed = 1;
7601 vcpu->mmio_cur_fragment = 0;
7603 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7604 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7605 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7606 vcpu->run->mmio.phys_addr = gpa;
7608 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7611 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7615 struct x86_exception *exception)
7617 return emulator_read_write(ctxt, addr, val, bytes,
7618 exception, &read_emultor);
7621 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7625 struct x86_exception *exception)
7627 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7628 exception, &write_emultor);
7631 #define emulator_try_cmpxchg_user(t, ptr, old, new) \
7632 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t))
7634 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7639 struct x86_exception *exception)
7641 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7647 /* guests cmpxchg8b have to be emulated atomically */
7648 if (bytes > 8 || (bytes & (bytes - 1)))
7651 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7653 if (gpa == INVALID_GPA ||
7654 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7658 * Emulate the atomic as a straight write to avoid #AC if SLD is
7659 * enabled in the host and the access splits a cache line.
7661 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7662 page_line_mask = ~(cache_line_size() - 1);
7664 page_line_mask = PAGE_MASK;
7666 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7669 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa));
7670 if (kvm_is_error_hva(hva))
7673 hva += offset_in_page(gpa);
7677 r = emulator_try_cmpxchg_user(u8, hva, old, new);
7680 r = emulator_try_cmpxchg_user(u16, hva, old, new);
7683 r = emulator_try_cmpxchg_user(u32, hva, old, new);
7686 r = emulator_try_cmpxchg_user(u64, hva, old, new);
7693 return X86EMUL_UNHANDLEABLE;
7695 return X86EMUL_CMPXCHG_FAILED;
7697 kvm_page_track_write(vcpu, gpa, new, bytes);
7699 return X86EMUL_CONTINUE;
7702 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
7704 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7707 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7708 unsigned short port, void *data,
7709 unsigned int count, bool in)
7714 WARN_ON_ONCE(vcpu->arch.pio.count);
7715 for (i = 0; i < count; i++) {
7717 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data);
7719 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data);
7726 * Userspace must have unregistered the device while PIO
7727 * was running. Drop writes / read as 0.
7730 memset(data, 0, size * (count - i));
7739 vcpu->arch.pio.port = port;
7740 vcpu->arch.pio.in = in;
7741 vcpu->arch.pio.count = count;
7742 vcpu->arch.pio.size = size;
7745 memset(vcpu->arch.pio_data, 0, size * count);
7747 memcpy(vcpu->arch.pio_data, data, size * count);
7749 vcpu->run->exit_reason = KVM_EXIT_IO;
7750 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7751 vcpu->run->io.size = size;
7752 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7753 vcpu->run->io.count = count;
7754 vcpu->run->io.port = port;
7758 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7759 unsigned short port, void *val, unsigned int count)
7761 int r = emulator_pio_in_out(vcpu, size, port, val, count, true);
7763 trace_kvm_pio(KVM_PIO_IN, port, size, count, val);
7768 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7770 int size = vcpu->arch.pio.size;
7771 unsigned int count = vcpu->arch.pio.count;
7772 memcpy(val, vcpu->arch.pio_data, size * count);
7773 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7774 vcpu->arch.pio.count = 0;
7777 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7778 int size, unsigned short port, void *val,
7781 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7782 if (vcpu->arch.pio.count) {
7784 * Complete a previous iteration that required userspace I/O.
7785 * Note, @count isn't guaranteed to match pio.count as userspace
7786 * can modify ECX before rerunning the vCPU. Ignore any such
7787 * shenanigans as KVM doesn't support modifying the rep count,
7788 * and the emulator ensures @count doesn't overflow the buffer.
7790 complete_emulator_pio_in(vcpu, val);
7794 return emulator_pio_in(vcpu, size, port, val, count);
7797 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7798 unsigned short port, const void *val,
7801 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val);
7802 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
7805 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7806 int size, unsigned short port,
7807 const void *val, unsigned int count)
7809 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7812 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7814 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7817 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7819 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7822 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7824 if (!need_emulate_wbinvd(vcpu))
7825 return X86EMUL_CONTINUE;
7827 if (static_call(kvm_x86_has_wbinvd_exit)()) {
7828 int cpu = get_cpu();
7830 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7831 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7832 wbinvd_ipi, NULL, 1);
7834 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7837 return X86EMUL_CONTINUE;
7840 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
7842 kvm_emulate_wbinvd_noskip(vcpu);
7843 return kvm_skip_emulated_instruction(vcpu);
7845 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
7849 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
7851 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
7854 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
7855 unsigned long *dest)
7857 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
7860 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
7861 unsigned long value)
7864 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
7867 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
7869 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
7872 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
7874 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7875 unsigned long value;
7879 value = kvm_read_cr0(vcpu);
7882 value = vcpu->arch.cr2;
7885 value = kvm_read_cr3(vcpu);
7888 value = kvm_read_cr4(vcpu);
7891 value = kvm_get_cr8(vcpu);
7894 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7901 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
7903 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7908 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
7911 vcpu->arch.cr2 = val;
7914 res = kvm_set_cr3(vcpu, val);
7917 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
7920 res = kvm_set_cr8(vcpu, val);
7923 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7930 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
7932 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
7935 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7937 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
7940 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7942 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
7945 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7947 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
7950 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7952 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
7955 static unsigned long emulator_get_cached_segment_base(
7956 struct x86_emulate_ctxt *ctxt, int seg)
7958 return get_segment_base(emul_to_vcpu(ctxt), seg);
7961 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
7962 struct desc_struct *desc, u32 *base3,
7965 struct kvm_segment var;
7967 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
7968 *selector = var.selector;
7971 memset(desc, 0, sizeof(*desc));
7979 set_desc_limit(desc, var.limit);
7980 set_desc_base(desc, (unsigned long)var.base);
7981 #ifdef CONFIG_X86_64
7983 *base3 = var.base >> 32;
7985 desc->type = var.type;
7987 desc->dpl = var.dpl;
7988 desc->p = var.present;
7989 desc->avl = var.avl;
7997 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
7998 struct desc_struct *desc, u32 base3,
8001 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8002 struct kvm_segment var;
8004 var.selector = selector;
8005 var.base = get_desc_base(desc);
8006 #ifdef CONFIG_X86_64
8007 var.base |= ((u64)base3) << 32;
8009 var.limit = get_desc_limit(desc);
8011 var.limit = (var.limit << 12) | 0xfff;
8012 var.type = desc->type;
8013 var.dpl = desc->dpl;
8018 var.avl = desc->avl;
8019 var.present = desc->p;
8020 var.unusable = !var.present;
8023 kvm_set_segment(vcpu, &var, seg);
8027 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8028 u32 msr_index, u64 *pdata)
8030 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8033 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
8035 return X86EMUL_UNHANDLEABLE;
8038 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
8039 complete_emulated_rdmsr, r))
8040 return X86EMUL_IO_NEEDED;
8042 trace_kvm_msr_read_ex(msr_index);
8043 return X86EMUL_PROPAGATE_FAULT;
8046 trace_kvm_msr_read(msr_index, *pdata);
8047 return X86EMUL_CONTINUE;
8050 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8051 u32 msr_index, u64 data)
8053 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8056 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
8058 return X86EMUL_UNHANDLEABLE;
8061 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
8062 complete_emulated_msr_access, r))
8063 return X86EMUL_IO_NEEDED;
8065 trace_kvm_msr_write_ex(msr_index, data);
8066 return X86EMUL_PROPAGATE_FAULT;
8069 trace_kvm_msr_write(msr_index, data);
8070 return X86EMUL_CONTINUE;
8073 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
8074 u32 msr_index, u64 *pdata)
8076 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
8079 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
8082 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
8087 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
8088 u32 pmc, u64 *pdata)
8090 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
8093 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
8095 emul_to_vcpu(ctxt)->arch.halt_request = 1;
8098 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8099 struct x86_instruction_info *info,
8100 enum x86_intercept_stage stage)
8102 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
8106 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
8107 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
8110 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
8113 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
8115 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
8118 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
8120 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
8123 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
8125 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
8128 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
8130 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
8133 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
8135 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
8138 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
8140 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
8143 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
8145 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
8148 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
8150 return emul_to_vcpu(ctxt)->arch.hflags;
8153 #ifndef CONFIG_KVM_SMM
8154 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt)
8157 return X86EMUL_UNHANDLEABLE;
8161 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
8163 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
8166 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
8168 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
8171 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
8173 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
8175 if (!kvm->vm_bugged)
8179 static const struct x86_emulate_ops emulate_ops = {
8180 .vm_bugged = emulator_vm_bugged,
8181 .read_gpr = emulator_read_gpr,
8182 .write_gpr = emulator_write_gpr,
8183 .read_std = emulator_read_std,
8184 .write_std = emulator_write_std,
8185 .fetch = kvm_fetch_guest_virt,
8186 .read_emulated = emulator_read_emulated,
8187 .write_emulated = emulator_write_emulated,
8188 .cmpxchg_emulated = emulator_cmpxchg_emulated,
8189 .invlpg = emulator_invlpg,
8190 .pio_in_emulated = emulator_pio_in_emulated,
8191 .pio_out_emulated = emulator_pio_out_emulated,
8192 .get_segment = emulator_get_segment,
8193 .set_segment = emulator_set_segment,
8194 .get_cached_segment_base = emulator_get_cached_segment_base,
8195 .get_gdt = emulator_get_gdt,
8196 .get_idt = emulator_get_idt,
8197 .set_gdt = emulator_set_gdt,
8198 .set_idt = emulator_set_idt,
8199 .get_cr = emulator_get_cr,
8200 .set_cr = emulator_set_cr,
8201 .cpl = emulator_get_cpl,
8202 .get_dr = emulator_get_dr,
8203 .set_dr = emulator_set_dr,
8204 .set_msr_with_filter = emulator_set_msr_with_filter,
8205 .get_msr_with_filter = emulator_get_msr_with_filter,
8206 .get_msr = emulator_get_msr,
8207 .check_pmc = emulator_check_pmc,
8208 .read_pmc = emulator_read_pmc,
8209 .halt = emulator_halt,
8210 .wbinvd = emulator_wbinvd,
8211 .fix_hypercall = emulator_fix_hypercall,
8212 .intercept = emulator_intercept,
8213 .get_cpuid = emulator_get_cpuid,
8214 .guest_has_long_mode = emulator_guest_has_long_mode,
8215 .guest_has_movbe = emulator_guest_has_movbe,
8216 .guest_has_fxsr = emulator_guest_has_fxsr,
8217 .guest_has_rdpid = emulator_guest_has_rdpid,
8218 .set_nmi_mask = emulator_set_nmi_mask,
8219 .get_hflags = emulator_get_hflags,
8220 .leave_smm = emulator_leave_smm,
8221 .triple_fault = emulator_triple_fault,
8222 .set_xcr = emulator_set_xcr,
8225 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
8227 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8229 * an sti; sti; sequence only disable interrupts for the first
8230 * instruction. So, if the last instruction, be it emulated or
8231 * not, left the system with the INT_STI flag enabled, it
8232 * means that the last instruction is an sti. We should not
8233 * leave the flag on in this case. The same goes for mov ss
8235 if (int_shadow & mask)
8237 if (unlikely(int_shadow || mask)) {
8238 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
8240 kvm_make_request(KVM_REQ_EVENT, vcpu);
8244 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
8246 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8248 if (ctxt->exception.vector == PF_VECTOR)
8249 kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
8250 else if (ctxt->exception.error_code_valid)
8251 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
8252 ctxt->exception.error_code);
8254 kvm_queue_exception(vcpu, ctxt->exception.vector);
8257 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
8259 struct x86_emulate_ctxt *ctxt;
8261 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
8263 pr_err("kvm: failed to allocate vcpu's emulator\n");
8268 ctxt->ops = &emulate_ops;
8269 vcpu->arch.emulate_ctxt = ctxt;
8274 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
8276 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8279 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
8281 ctxt->gpa_available = false;
8282 ctxt->eflags = kvm_get_rflags(vcpu);
8283 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
8285 ctxt->eip = kvm_rip_read(vcpu);
8286 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
8287 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
8288 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
8289 cs_db ? X86EMUL_MODE_PROT32 :
8290 X86EMUL_MODE_PROT16;
8291 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
8293 ctxt->interruptibility = 0;
8294 ctxt->have_exception = false;
8295 ctxt->exception.vector = -1;
8296 ctxt->perm_ok = false;
8298 init_decode_cache(ctxt);
8299 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8302 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
8304 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8307 init_emulate_ctxt(vcpu);
8311 ctxt->_eip = ctxt->eip + inc_eip;
8312 ret = emulate_int_real(ctxt, irq);
8314 if (ret != X86EMUL_CONTINUE) {
8315 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8317 ctxt->eip = ctxt->_eip;
8318 kvm_rip_write(vcpu, ctxt->eip);
8319 kvm_set_rflags(vcpu, ctxt->eflags);
8322 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
8324 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8325 u8 ndata, u8 *insn_bytes, u8 insn_size)
8327 struct kvm_run *run = vcpu->run;
8332 * Zero the whole array used to retrieve the exit info, as casting to
8333 * u32 for select entries will leave some chunks uninitialized.
8335 memset(&info, 0, sizeof(info));
8337 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
8338 &info[2], (u32 *)&info[3],
8341 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8342 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
8345 * There's currently space for 13 entries, but 5 are used for the exit
8346 * reason and info. Restrict to 4 to reduce the maintenance burden
8347 * when expanding kvm_run.emulation_failure in the future.
8349 if (WARN_ON_ONCE(ndata > 4))
8352 /* Always include the flags as a 'data' entry. */
8354 run->emulation_failure.flags = 0;
8357 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8358 sizeof(run->emulation_failure.insn_bytes) != 16));
8360 run->emulation_failure.flags |=
8361 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8362 run->emulation_failure.insn_size = insn_size;
8363 memset(run->emulation_failure.insn_bytes, 0x90,
8364 sizeof(run->emulation_failure.insn_bytes));
8365 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8368 memcpy(&run->internal.data[info_start], info, sizeof(info));
8369 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8370 ndata * sizeof(data[0]));
8372 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8375 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8377 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8379 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8380 ctxt->fetch.end - ctxt->fetch.data);
8383 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8386 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8388 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8390 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8392 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8394 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8396 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8398 struct kvm *kvm = vcpu->kvm;
8400 ++vcpu->stat.insn_emulation_fail;
8401 trace_kvm_emulate_insn_failed(vcpu);
8403 if (emulation_type & EMULTYPE_VMWARE_GP) {
8404 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8408 if (kvm->arch.exit_on_emulation_error ||
8409 (emulation_type & EMULTYPE_SKIP)) {
8410 prepare_emulation_ctxt_failure_exit(vcpu);
8414 kvm_queue_exception(vcpu, UD_VECTOR);
8416 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8417 prepare_emulation_ctxt_failure_exit(vcpu);
8424 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8425 bool write_fault_to_shadow_pgtable,
8428 gpa_t gpa = cr2_or_gpa;
8431 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8434 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8435 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8438 if (!vcpu->arch.mmu->root_role.direct) {
8440 * Write permission should be allowed since only
8441 * write access need to be emulated.
8443 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8446 * If the mapping is invalid in guest, let cpu retry
8447 * it to generate fault.
8449 if (gpa == INVALID_GPA)
8454 * Do not retry the unhandleable instruction if it faults on the
8455 * readonly host memory, otherwise it will goto a infinite loop:
8456 * retry instruction -> write #PF -> emulation fail -> retry
8457 * instruction -> ...
8459 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8462 * If the instruction failed on the error pfn, it can not be fixed,
8463 * report the error to userspace.
8465 if (is_error_noslot_pfn(pfn))
8468 kvm_release_pfn_clean(pfn);
8470 /* The instructions are well-emulated on direct mmu. */
8471 if (vcpu->arch.mmu->root_role.direct) {
8472 unsigned int indirect_shadow_pages;
8474 write_lock(&vcpu->kvm->mmu_lock);
8475 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8476 write_unlock(&vcpu->kvm->mmu_lock);
8478 if (indirect_shadow_pages)
8479 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8485 * if emulation was due to access to shadowed page table
8486 * and it failed try to unshadow page and re-enter the
8487 * guest to let CPU execute the instruction.
8489 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8492 * If the access faults on its page table, it can not
8493 * be fixed by unprotecting shadow page and it should
8494 * be reported to userspace.
8496 return !write_fault_to_shadow_pgtable;
8499 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8500 gpa_t cr2_or_gpa, int emulation_type)
8502 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8503 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8505 last_retry_eip = vcpu->arch.last_retry_eip;
8506 last_retry_addr = vcpu->arch.last_retry_addr;
8509 * If the emulation is caused by #PF and it is non-page_table
8510 * writing instruction, it means the VM-EXIT is caused by shadow
8511 * page protected, we can zap the shadow page and retry this
8512 * instruction directly.
8514 * Note: if the guest uses a non-page-table modifying instruction
8515 * on the PDE that points to the instruction, then we will unmap
8516 * the instruction and go to an infinite loop. So, we cache the
8517 * last retried eip and the last fault address, if we meet the eip
8518 * and the address again, we can break out of the potential infinite
8521 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8523 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8526 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8527 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8530 if (x86_page_table_writing_insn(ctxt))
8533 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8536 vcpu->arch.last_retry_eip = ctxt->eip;
8537 vcpu->arch.last_retry_addr = cr2_or_gpa;
8539 if (!vcpu->arch.mmu->root_role.direct)
8540 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8542 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8547 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8548 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8550 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8559 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8560 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8565 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8567 struct kvm_run *kvm_run = vcpu->run;
8569 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8570 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8571 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8572 kvm_run->debug.arch.exception = DB_VECTOR;
8573 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8576 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8580 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8582 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8585 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8589 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8592 * rflags is the old, "raw" value of the flags. The new value has
8593 * not been saved yet.
8595 * This is correct even for TF set by the guest, because "the
8596 * processor will not generate this exception after the instruction
8597 * that sets the TF flag".
8599 if (unlikely(rflags & X86_EFLAGS_TF))
8600 r = kvm_vcpu_do_singlestep(vcpu);
8603 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8605 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
8609 if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
8613 * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
8614 * but AMD CPUs do not. MOV/POP SS blocking is rare, check that first
8615 * to avoid the relatively expensive CPUID lookup.
8617 shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8618 return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
8619 guest_cpuid_is_intel(vcpu);
8622 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,
8623 int emulation_type, int *r)
8625 WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE);
8628 * Do not check for code breakpoints if hardware has already done the
8629 * checks, as inferred from the emulation type. On NO_DECODE and SKIP,
8630 * the instruction has passed all exception checks, and all intercepted
8631 * exceptions that trigger emulation have lower priority than code
8632 * breakpoints, i.e. the fact that the intercepted exception occurred
8633 * means any code breakpoints have already been serviced.
8635 * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as
8636 * hardware has checked the RIP of the magic prefix, but not the RIP of
8637 * the instruction being emulated. The intent of forced emulation is
8638 * to behave as if KVM intercepted the instruction without an exception
8639 * and without a prefix.
8641 if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
8642 EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF))
8645 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8646 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8647 struct kvm_run *kvm_run = vcpu->run;
8648 unsigned long eip = kvm_get_linear_rip(vcpu);
8649 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8650 vcpu->arch.guest_debug_dr7,
8654 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8655 kvm_run->debug.arch.pc = eip;
8656 kvm_run->debug.arch.exception = DB_VECTOR;
8657 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8663 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8664 !kvm_is_code_breakpoint_inhibited(vcpu)) {
8665 unsigned long eip = kvm_get_linear_rip(vcpu);
8666 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8671 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8680 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8682 switch (ctxt->opcode_len) {
8689 case 0xe6: /* OUT */
8693 case 0x6c: /* INS */
8695 case 0x6e: /* OUTS */
8702 case 0x33: /* RDPMC */
8712 * Decode an instruction for emulation. The caller is responsible for handling
8713 * code breakpoints. Note, manually detecting code breakpoints is unnecessary
8714 * (and wrong) when emulating on an intercepted fault-like exception[*], as
8715 * code breakpoints have higher priority and thus have already been done by
8718 * [*] Except #MC, which is higher priority, but KVM should never emulate in
8719 * response to a machine check.
8721 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8722 void *insn, int insn_len)
8724 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8727 init_emulate_ctxt(vcpu);
8729 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8731 trace_kvm_emulate_insn_start(vcpu);
8732 ++vcpu->stat.insn_emulation;
8736 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8738 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8739 int emulation_type, void *insn, int insn_len)
8742 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8743 bool writeback = true;
8744 bool write_fault_to_spt;
8746 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8749 vcpu->arch.l1tf_flush_l1d = true;
8752 * Clear write_fault_to_shadow_pgtable here to ensure it is
8755 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
8756 vcpu->arch.write_fault_to_shadow_pgtable = false;
8758 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8759 kvm_clear_exception_queue(vcpu);
8762 * Return immediately if RIP hits a code breakpoint, such #DBs
8763 * are fault-like and are higher priority than any faults on
8764 * the code fetch itself.
8766 if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r))
8769 r = x86_decode_emulated_instruction(vcpu, emulation_type,
8771 if (r != EMULATION_OK) {
8772 if ((emulation_type & EMULTYPE_TRAP_UD) ||
8773 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8774 kvm_queue_exception(vcpu, UD_VECTOR);
8777 if (reexecute_instruction(vcpu, cr2_or_gpa,
8782 if (ctxt->have_exception &&
8783 !(emulation_type & EMULTYPE_SKIP)) {
8785 * #UD should result in just EMULATION_FAILED, and trap-like
8786 * exception should not be encountered during decode.
8788 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8789 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8790 inject_emulated_exception(vcpu);
8793 return handle_emulation_failure(vcpu, emulation_type);
8797 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8798 !is_vmware_backdoor_opcode(ctxt)) {
8799 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8804 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8805 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8806 * The caller is responsible for updating interruptibility state and
8807 * injecting single-step #DBs.
8809 if (emulation_type & EMULTYPE_SKIP) {
8810 if (ctxt->mode != X86EMUL_MODE_PROT64)
8811 ctxt->eip = (u32)ctxt->_eip;
8813 ctxt->eip = ctxt->_eip;
8815 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8820 kvm_rip_write(vcpu, ctxt->eip);
8821 if (ctxt->eflags & X86_EFLAGS_RF)
8822 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8826 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8829 /* this is needed for vmware backdoor interface to work since it
8830 changes registers values during IO operation */
8831 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8832 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8833 emulator_invalidate_register_cache(ctxt);
8837 if (emulation_type & EMULTYPE_PF) {
8838 /* Save the faulting GPA (cr2) in the address field */
8839 ctxt->exception.address = cr2_or_gpa;
8841 /* With shadow page tables, cr2 contains a GVA or nGPA. */
8842 if (vcpu->arch.mmu->root_role.direct) {
8843 ctxt->gpa_available = true;
8844 ctxt->gpa_val = cr2_or_gpa;
8847 /* Sanitize the address out of an abundance of paranoia. */
8848 ctxt->exception.address = 0;
8851 r = x86_emulate_insn(ctxt);
8853 if (r == EMULATION_INTERCEPTED)
8856 if (r == EMULATION_FAILED) {
8857 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
8861 return handle_emulation_failure(vcpu, emulation_type);
8864 if (ctxt->have_exception) {
8866 inject_emulated_exception(vcpu);
8867 } else if (vcpu->arch.pio.count) {
8868 if (!vcpu->arch.pio.in) {
8869 /* FIXME: return into emulator if single-stepping. */
8870 vcpu->arch.pio.count = 0;
8873 vcpu->arch.complete_userspace_io = complete_emulated_pio;
8876 } else if (vcpu->mmio_needed) {
8877 ++vcpu->stat.mmio_exits;
8879 if (!vcpu->mmio_is_write)
8882 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8883 } else if (vcpu->arch.complete_userspace_io) {
8886 } else if (r == EMULATION_RESTART)
8893 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8894 toggle_interruptibility(vcpu, ctxt->interruptibility);
8895 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8898 * Note, EXCPT_DB is assumed to be fault-like as the emulator
8899 * only supports code breakpoints and general detect #DB, both
8900 * of which are fault-like.
8902 if (!ctxt->have_exception ||
8903 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
8904 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8905 if (ctxt->is_branch)
8906 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
8907 kvm_rip_write(vcpu, ctxt->eip);
8908 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
8909 r = kvm_vcpu_do_singlestep(vcpu);
8910 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
8911 __kvm_set_rflags(vcpu, ctxt->eflags);
8915 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
8916 * do nothing, and it will be requested again as soon as
8917 * the shadow expires. But we still need to check here,
8918 * because POPF has no interrupt shadow.
8920 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
8921 kvm_make_request(KVM_REQ_EVENT, vcpu);
8923 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
8928 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
8930 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
8932 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
8934 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
8935 void *insn, int insn_len)
8937 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
8939 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
8941 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
8943 vcpu->arch.pio.count = 0;
8947 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
8949 vcpu->arch.pio.count = 0;
8951 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
8954 return kvm_skip_emulated_instruction(vcpu);
8957 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
8958 unsigned short port)
8960 unsigned long val = kvm_rax_read(vcpu);
8961 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
8967 * Workaround userspace that relies on old KVM behavior of %rip being
8968 * incremented prior to exiting to userspace to handle "OUT 0x7e".
8971 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
8972 vcpu->arch.complete_userspace_io =
8973 complete_fast_pio_out_port_0x7e;
8974 kvm_skip_emulated_instruction(vcpu);
8976 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8977 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
8982 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
8986 /* We should only ever be called with arch.pio.count equal to 1 */
8987 BUG_ON(vcpu->arch.pio.count != 1);
8989 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
8990 vcpu->arch.pio.count = 0;
8994 /* For size less than 4 we merge, else we zero extend */
8995 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8997 complete_emulator_pio_in(vcpu, &val);
8998 kvm_rax_write(vcpu, val);
9000 return kvm_skip_emulated_instruction(vcpu);
9003 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
9004 unsigned short port)
9009 /* For size less than 4 we merge, else we zero extend */
9010 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
9012 ret = emulator_pio_in(vcpu, size, port, &val, 1);
9014 kvm_rax_write(vcpu, val);
9018 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9019 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
9024 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
9029 ret = kvm_fast_pio_in(vcpu, size, port);
9031 ret = kvm_fast_pio_out(vcpu, size, port);
9032 return ret && kvm_skip_emulated_instruction(vcpu);
9034 EXPORT_SYMBOL_GPL(kvm_fast_pio);
9036 static int kvmclock_cpu_down_prep(unsigned int cpu)
9038 __this_cpu_write(cpu_tsc_khz, 0);
9042 static void tsc_khz_changed(void *data)
9044 struct cpufreq_freqs *freq = data;
9045 unsigned long khz = 0;
9047 WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC));
9052 khz = cpufreq_quick_get(raw_smp_processor_id());
9055 __this_cpu_write(cpu_tsc_khz, khz);
9058 #ifdef CONFIG_X86_64
9059 static void kvm_hyperv_tsc_notifier(void)
9064 mutex_lock(&kvm_lock);
9065 list_for_each_entry(kvm, &vm_list, vm_list)
9066 kvm_make_mclock_inprogress_request(kvm);
9068 /* no guest entries from this point */
9069 hyperv_stop_tsc_emulation();
9071 /* TSC frequency always matches when on Hyper-V */
9072 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9073 for_each_present_cpu(cpu)
9074 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
9076 kvm_caps.max_guest_tsc_khz = tsc_khz;
9078 list_for_each_entry(kvm, &vm_list, vm_list) {
9079 __kvm_start_pvclock_update(kvm);
9080 pvclock_update_vm_gtod_copy(kvm);
9081 kvm_end_pvclock_update(kvm);
9084 mutex_unlock(&kvm_lock);
9088 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
9091 struct kvm_vcpu *vcpu;
9096 * We allow guests to temporarily run on slowing clocks,
9097 * provided we notify them after, or to run on accelerating
9098 * clocks, provided we notify them before. Thus time never
9101 * However, we have a problem. We can't atomically update
9102 * the frequency of a given CPU from this function; it is
9103 * merely a notifier, which can be called from any CPU.
9104 * Changing the TSC frequency at arbitrary points in time
9105 * requires a recomputation of local variables related to
9106 * the TSC for each VCPU. We must flag these local variables
9107 * to be updated and be sure the update takes place with the
9108 * new frequency before any guests proceed.
9110 * Unfortunately, the combination of hotplug CPU and frequency
9111 * change creates an intractable locking scenario; the order
9112 * of when these callouts happen is undefined with respect to
9113 * CPU hotplug, and they can race with each other. As such,
9114 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
9115 * undefined; you can actually have a CPU frequency change take
9116 * place in between the computation of X and the setting of the
9117 * variable. To protect against this problem, all updates of
9118 * the per_cpu tsc_khz variable are done in an interrupt
9119 * protected IPI, and all callers wishing to update the value
9120 * must wait for a synchronous IPI to complete (which is trivial
9121 * if the caller is on the CPU already). This establishes the
9122 * necessary total order on variable updates.
9124 * Note that because a guest time update may take place
9125 * anytime after the setting of the VCPU's request bit, the
9126 * correct TSC value must be set before the request. However,
9127 * to ensure the update actually makes it to any guest which
9128 * starts running in hardware virtualization between the set
9129 * and the acquisition of the spinlock, we must also ping the
9130 * CPU after setting the request bit.
9134 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9136 mutex_lock(&kvm_lock);
9137 list_for_each_entry(kvm, &vm_list, vm_list) {
9138 kvm_for_each_vcpu(i, vcpu, kvm) {
9139 if (vcpu->cpu != cpu)
9141 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9142 if (vcpu->cpu != raw_smp_processor_id())
9146 mutex_unlock(&kvm_lock);
9148 if (freq->old < freq->new && send_ipi) {
9150 * We upscale the frequency. Must make the guest
9151 * doesn't see old kvmclock values while running with
9152 * the new frequency, otherwise we risk the guest sees
9153 * time go backwards.
9155 * In case we update the frequency for another cpu
9156 * (which might be in guest context) send an interrupt
9157 * to kick the cpu out of guest context. Next time
9158 * guest context is entered kvmclock will be updated,
9159 * so the guest will not see stale values.
9161 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9165 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
9168 struct cpufreq_freqs *freq = data;
9171 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
9173 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
9176 for_each_cpu(cpu, freq->policy->cpus)
9177 __kvmclock_cpufreq_notifier(freq, cpu);
9182 static struct notifier_block kvmclock_cpufreq_notifier_block = {
9183 .notifier_call = kvmclock_cpufreq_notifier
9186 static int kvmclock_cpu_online(unsigned int cpu)
9188 tsc_khz_changed(NULL);
9192 static void kvm_timer_init(void)
9194 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9195 max_tsc_khz = tsc_khz;
9197 if (IS_ENABLED(CONFIG_CPU_FREQ)) {
9198 struct cpufreq_policy *policy;
9202 policy = cpufreq_cpu_get(cpu);
9204 if (policy->cpuinfo.max_freq)
9205 max_tsc_khz = policy->cpuinfo.max_freq;
9206 cpufreq_cpu_put(policy);
9210 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
9211 CPUFREQ_TRANSITION_NOTIFIER);
9213 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
9214 kvmclock_cpu_online, kvmclock_cpu_down_prep);
9218 #ifdef CONFIG_X86_64
9219 static void pvclock_gtod_update_fn(struct work_struct *work)
9222 struct kvm_vcpu *vcpu;
9225 mutex_lock(&kvm_lock);
9226 list_for_each_entry(kvm, &vm_list, vm_list)
9227 kvm_for_each_vcpu(i, vcpu, kvm)
9228 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9229 atomic_set(&kvm_guest_has_master_clock, 0);
9230 mutex_unlock(&kvm_lock);
9233 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
9236 * Indirection to move queue_work() out of the tk_core.seq write held
9237 * region to prevent possible deadlocks against time accessors which
9238 * are invoked with work related locks held.
9240 static void pvclock_irq_work_fn(struct irq_work *w)
9242 queue_work(system_long_wq, &pvclock_gtod_work);
9245 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
9248 * Notification about pvclock gtod data update.
9250 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
9253 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
9254 struct timekeeper *tk = priv;
9256 update_pvclock_gtod(tk);
9259 * Disable master clock if host does not trust, or does not use,
9260 * TSC based clocksource. Delegate queue_work() to irq_work as
9261 * this is invoked with tk_core.seq write held.
9263 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
9264 atomic_read(&kvm_guest_has_master_clock) != 0)
9265 irq_work_queue(&pvclock_irq_work);
9269 static struct notifier_block pvclock_gtod_notifier = {
9270 .notifier_call = pvclock_gtod_notify,
9274 int kvm_arch_init(void *opaque)
9276 struct kvm_x86_init_ops *ops = opaque;
9280 if (kvm_x86_ops.hardware_enable) {
9281 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name);
9285 if (!ops->cpu_has_kvm_support()) {
9286 pr_err_ratelimited("kvm: no hardware support for '%s'\n",
9287 ops->runtime_ops->name);
9290 if (ops->disabled_by_bios()) {
9291 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n",
9292 ops->runtime_ops->name);
9297 * KVM explicitly assumes that the guest has an FPU and
9298 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
9299 * vCPU's FPU state as a fxregs_state struct.
9301 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
9302 printk(KERN_ERR "kvm: inadequate fpu\n");
9306 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9307 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
9312 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes
9313 * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something
9314 * other than WB. Note, EPT doesn't utilize the PAT, but don't bother
9315 * with an exception. PAT[0] is set to WB on RESET and also by the
9316 * kernel, i.e. failure indicates a kernel bug or broken firmware.
9318 if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) ||
9319 (host_pat & GENMASK(2, 0)) != 6) {
9320 pr_err("kvm: host PAT[0] is not WB\n");
9324 x86_emulator_cache = kvm_alloc_emulator_cache();
9325 if (!x86_emulator_cache) {
9326 pr_err("kvm: failed to allocate cache for x86 emulator\n");
9330 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
9331 if (!user_return_msrs) {
9332 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
9334 goto out_free_x86_emulator_cache;
9336 kvm_nr_uret_msrs = 0;
9338 r = kvm_mmu_vendor_module_init();
9340 goto out_free_percpu;
9344 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
9345 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
9346 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
9349 if (pi_inject_timer == -1)
9350 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
9351 #ifdef CONFIG_X86_64
9352 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
9354 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9355 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
9361 free_percpu(user_return_msrs);
9362 out_free_x86_emulator_cache:
9363 kmem_cache_destroy(x86_emulator_cache);
9367 void kvm_arch_exit(void)
9369 #ifdef CONFIG_X86_64
9370 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9371 clear_hv_tscchange_cb();
9375 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9376 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
9377 CPUFREQ_TRANSITION_NOTIFIER);
9378 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
9380 #ifdef CONFIG_X86_64
9381 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9382 irq_work_sync(&pvclock_irq_work);
9383 cancel_work_sync(&pvclock_gtod_work);
9385 kvm_x86_ops.hardware_enable = NULL;
9386 kvm_mmu_vendor_module_exit();
9387 free_percpu(user_return_msrs);
9388 kmem_cache_destroy(x86_emulator_cache);
9389 #ifdef CONFIG_KVM_XEN
9390 static_key_deferred_flush(&kvm_xen_enabled);
9391 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9395 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9398 * The vCPU has halted, e.g. executed HLT. Update the run state if the
9399 * local APIC is in-kernel, the run loop will detect the non-runnable
9400 * state and halt the vCPU. Exit to userspace if the local APIC is
9401 * managed by userspace, in which case userspace is responsible for
9402 * handling wake events.
9404 ++vcpu->stat.halt_exits;
9405 if (lapic_in_kernel(vcpu)) {
9406 vcpu->arch.mp_state = state;
9409 vcpu->run->exit_reason = reason;
9414 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9416 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9418 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9420 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9422 int ret = kvm_skip_emulated_instruction(vcpu);
9424 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9425 * KVM_EXIT_DEBUG here.
9427 return kvm_emulate_halt_noskip(vcpu) && ret;
9429 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9431 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9433 int ret = kvm_skip_emulated_instruction(vcpu);
9435 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9436 KVM_EXIT_AP_RESET_HOLD) && ret;
9438 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9440 #ifdef CONFIG_X86_64
9441 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9442 unsigned long clock_type)
9444 struct kvm_clock_pairing clock_pairing;
9445 struct timespec64 ts;
9449 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9450 return -KVM_EOPNOTSUPP;
9453 * When tsc is in permanent catchup mode guests won't be able to use
9454 * pvclock_read_retry loop to get consistent view of pvclock
9456 if (vcpu->arch.tsc_always_catchup)
9457 return -KVM_EOPNOTSUPP;
9459 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9460 return -KVM_EOPNOTSUPP;
9462 clock_pairing.sec = ts.tv_sec;
9463 clock_pairing.nsec = ts.tv_nsec;
9464 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9465 clock_pairing.flags = 0;
9466 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9469 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9470 sizeof(struct kvm_clock_pairing)))
9478 * kvm_pv_kick_cpu_op: Kick a vcpu.
9480 * @apicid - apicid of vcpu to be kicked.
9482 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9485 * All other fields are unused for APIC_DM_REMRD, but may be consumed by
9486 * common code, e.g. for tracing. Defer initialization to the compiler.
9488 struct kvm_lapic_irq lapic_irq = {
9489 .delivery_mode = APIC_DM_REMRD,
9490 .dest_mode = APIC_DEST_PHYSICAL,
9491 .shorthand = APIC_DEST_NOSHORT,
9495 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9498 bool kvm_apicv_activated(struct kvm *kvm)
9500 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9502 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9504 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
9506 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
9507 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
9509 return (vm_reasons | vcpu_reasons) == 0;
9511 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
9513 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9514 enum kvm_apicv_inhibit reason, bool set)
9517 __set_bit(reason, inhibits);
9519 __clear_bit(reason, inhibits);
9521 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9524 static void kvm_apicv_init(struct kvm *kvm)
9526 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9528 init_rwsem(&kvm->arch.apicv_update_lock);
9530 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9533 set_or_clear_apicv_inhibit(inhibits,
9534 APICV_INHIBIT_REASON_DISABLE, true);
9537 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9539 struct kvm_vcpu *target = NULL;
9540 struct kvm_apic_map *map;
9542 vcpu->stat.directed_yield_attempted++;
9544 if (single_task_running())
9548 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9550 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9551 target = map->phys_map[dest_id]->vcpu;
9555 if (!target || !READ_ONCE(target->ready))
9558 /* Ignore requests to yield to self */
9562 if (kvm_vcpu_yield_to(target) <= 0)
9565 vcpu->stat.directed_yield_successful++;
9571 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9573 u64 ret = vcpu->run->hypercall.ret;
9575 if (!is_64_bit_mode(vcpu))
9577 kvm_rax_write(vcpu, ret);
9578 ++vcpu->stat.hypercalls;
9579 return kvm_skip_emulated_instruction(vcpu);
9582 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9584 unsigned long nr, a0, a1, a2, a3, ret;
9587 if (kvm_xen_hypercall_enabled(vcpu->kvm))
9588 return kvm_xen_hypercall(vcpu);
9590 if (kvm_hv_hypercall_enabled(vcpu))
9591 return kvm_hv_hypercall(vcpu);
9593 nr = kvm_rax_read(vcpu);
9594 a0 = kvm_rbx_read(vcpu);
9595 a1 = kvm_rcx_read(vcpu);
9596 a2 = kvm_rdx_read(vcpu);
9597 a3 = kvm_rsi_read(vcpu);
9599 trace_kvm_hypercall(nr, a0, a1, a2, a3);
9601 op_64_bit = is_64_bit_hypercall(vcpu);
9610 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9618 case KVM_HC_VAPIC_POLL_IRQ:
9621 case KVM_HC_KICK_CPU:
9622 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9625 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9626 kvm_sched_yield(vcpu, a1);
9629 #ifdef CONFIG_X86_64
9630 case KVM_HC_CLOCK_PAIRING:
9631 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9634 case KVM_HC_SEND_IPI:
9635 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9638 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9640 case KVM_HC_SCHED_YIELD:
9641 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9644 kvm_sched_yield(vcpu, a0);
9647 case KVM_HC_MAP_GPA_RANGE: {
9648 u64 gpa = a0, npages = a1, attrs = a2;
9651 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9654 if (!PAGE_ALIGNED(gpa) || !npages ||
9655 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9660 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
9661 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
9662 vcpu->run->hypercall.args[0] = gpa;
9663 vcpu->run->hypercall.args[1] = npages;
9664 vcpu->run->hypercall.args[2] = attrs;
9665 vcpu->run->hypercall.longmode = op_64_bit;
9666 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9676 kvm_rax_write(vcpu, ret);
9678 ++vcpu->stat.hypercalls;
9679 return kvm_skip_emulated_instruction(vcpu);
9681 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9683 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9685 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9686 char instruction[3];
9687 unsigned long rip = kvm_rip_read(vcpu);
9690 * If the quirk is disabled, synthesize a #UD and let the guest pick up
9693 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
9694 ctxt->exception.error_code_valid = false;
9695 ctxt->exception.vector = UD_VECTOR;
9696 ctxt->have_exception = true;
9697 return X86EMUL_PROPAGATE_FAULT;
9700 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9702 return emulator_write_emulated(ctxt, rip, instruction, 3,
9706 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9708 return vcpu->run->request_interrupt_window &&
9709 likely(!pic_in_kernel(vcpu->kvm));
9712 /* Called within kvm->srcu read side. */
9713 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9715 struct kvm_run *kvm_run = vcpu->run;
9717 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9718 kvm_run->cr8 = kvm_get_cr8(vcpu);
9719 kvm_run->apic_base = kvm_get_apic_base(vcpu);
9721 kvm_run->ready_for_interrupt_injection =
9722 pic_in_kernel(vcpu->kvm) ||
9723 kvm_vcpu_ready_for_interrupt_injection(vcpu);
9726 kvm_run->flags |= KVM_RUN_X86_SMM;
9729 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9733 if (!kvm_x86_ops.update_cr8_intercept)
9736 if (!lapic_in_kernel(vcpu))
9739 if (vcpu->arch.apic->apicv_active)
9742 if (!vcpu->arch.apic->vapic_addr)
9743 max_irr = kvm_lapic_find_highest_irr(vcpu);
9750 tpr = kvm_lapic_get_cr8(vcpu);
9752 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
9756 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
9758 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9759 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9763 return kvm_x86_ops.nested_ops->check_events(vcpu);
9766 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
9768 trace_kvm_inj_exception(vcpu->arch.exception.vector,
9769 vcpu->arch.exception.has_error_code,
9770 vcpu->arch.exception.error_code,
9771 vcpu->arch.exception.injected);
9773 if (vcpu->arch.exception.error_code && !is_protmode(vcpu))
9774 vcpu->arch.exception.error_code = false;
9775 static_call(kvm_x86_inject_exception)(vcpu);
9779 * Check for any event (interrupt or exception) that is ready to be injected,
9780 * and if there is at least one event, inject the event with the highest
9781 * priority. This handles both "pending" events, i.e. events that have never
9782 * been injected into the guest, and "injected" events, i.e. events that were
9783 * injected as part of a previous VM-Enter, but weren't successfully delivered
9784 * and need to be re-injected.
9786 * Note, this is not guaranteed to be invoked on a guest instruction boundary,
9787 * i.e. doesn't guarantee that there's an event window in the guest. KVM must
9788 * be able to inject exceptions in the "middle" of an instruction, and so must
9789 * also be able to re-inject NMIs and IRQs in the middle of an instruction.
9790 * I.e. for exceptions and re-injected events, NOT invoking this on instruction
9791 * boundaries is necessary and correct.
9793 * For simplicity, KVM uses a single path to inject all events (except events
9794 * that are injected directly from L1 to L2) and doesn't explicitly track
9795 * instruction boundaries for asynchronous events. However, because VM-Exits
9796 * that can occur during instruction execution typically result in KVM skipping
9797 * the instruction or injecting an exception, e.g. instruction and exception
9798 * intercepts, and because pending exceptions have higher priority than pending
9799 * interrupts, KVM still honors instruction boundaries in most scenarios.
9801 * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip
9802 * the instruction or inject an exception, then KVM can incorrecty inject a new
9803 * asynchrounous event if the event became pending after the CPU fetched the
9804 * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation)
9805 * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be
9806 * injected on the restarted instruction instead of being deferred until the
9807 * instruction completes.
9809 * In practice, this virtualization hole is unlikely to be observed by the
9810 * guest, and even less likely to cause functional problems. To detect the
9811 * hole, the guest would have to trigger an event on a side effect of an early
9812 * phase of instruction execution, e.g. on the instruction fetch from memory.
9813 * And for it to be a functional problem, the guest would need to depend on the
9814 * ordering between that side effect, the instruction completing, _and_ the
9815 * delivery of the asynchronous event.
9817 static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu,
9818 bool *req_immediate_exit)
9824 * Process nested events first, as nested VM-Exit supercedes event
9825 * re-injection. If there's an event queued for re-injection, it will
9826 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit.
9828 if (is_guest_mode(vcpu))
9829 r = kvm_check_nested_events(vcpu);
9834 * Re-inject exceptions and events *especially* if immediate entry+exit
9835 * to/from L2 is needed, as any event that has already been injected
9836 * into L2 needs to complete its lifecycle before injecting a new event.
9838 * Don't re-inject an NMI or interrupt if there is a pending exception.
9839 * This collision arises if an exception occurred while vectoring the
9840 * injected event, KVM intercepted said exception, and KVM ultimately
9841 * determined the fault belongs to the guest and queues the exception
9842 * for injection back into the guest.
9844 * "Injected" interrupts can also collide with pending exceptions if
9845 * userspace ignores the "ready for injection" flag and blindly queues
9846 * an interrupt. In that case, prioritizing the exception is correct,
9847 * as the exception "occurred" before the exit to userspace. Trap-like
9848 * exceptions, e.g. most #DBs, have higher priority than interrupts.
9849 * And while fault-like exceptions, e.g. #GP and #PF, are the lowest
9850 * priority, they're only generated (pended) during instruction
9851 * execution, and interrupts are recognized at instruction boundaries.
9852 * Thus a pending fault-like exception means the fault occurred on the
9853 * *previous* instruction and must be serviced prior to recognizing any
9854 * new events in order to fully complete the previous instruction.
9856 if (vcpu->arch.exception.injected)
9857 kvm_inject_exception(vcpu);
9858 else if (kvm_is_exception_pending(vcpu))
9860 else if (vcpu->arch.nmi_injected)
9861 static_call(kvm_x86_inject_nmi)(vcpu);
9862 else if (vcpu->arch.interrupt.injected)
9863 static_call(kvm_x86_inject_irq)(vcpu, true);
9866 * Exceptions that morph to VM-Exits are handled above, and pending
9867 * exceptions on top of injected exceptions that do not VM-Exit should
9868 * either morph to #DF or, sadly, override the injected exception.
9870 WARN_ON_ONCE(vcpu->arch.exception.injected &&
9871 vcpu->arch.exception.pending);
9874 * Bail if immediate entry+exit to/from the guest is needed to complete
9875 * nested VM-Enter or event re-injection so that a different pending
9876 * event can be serviced (or if KVM needs to exit to userspace).
9878 * Otherwise, continue processing events even if VM-Exit occurred. The
9879 * VM-Exit will have cleared exceptions that were meant for L2, but
9880 * there may now be events that can be injected into L1.
9886 * A pending exception VM-Exit should either result in nested VM-Exit
9887 * or force an immediate re-entry and exit to/from L2, and exception
9888 * VM-Exits cannot be injected (flag should _never_ be set).
9890 WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected ||
9891 vcpu->arch.exception_vmexit.pending);
9894 * New events, other than exceptions, cannot be injected if KVM needs
9895 * to re-inject a previous event. See above comments on re-injecting
9896 * for why pending exceptions get priority.
9898 can_inject = !kvm_event_needs_reinjection(vcpu);
9900 if (vcpu->arch.exception.pending) {
9902 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS
9903 * value pushed on the stack. Trap-like exception and all #DBs
9904 * leave RF as-is (KVM follows Intel's behavior in this regard;
9905 * AMD states that code breakpoint #DBs excplitly clear RF=0).
9907 * Note, most versions of Intel's SDM and AMD's APM incorrectly
9908 * describe the behavior of General Detect #DBs, which are
9909 * fault-like. They do _not_ set RF, a la code breakpoints.
9911 if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT)
9912 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
9915 if (vcpu->arch.exception.vector == DB_VECTOR) {
9916 kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception);
9917 if (vcpu->arch.dr7 & DR7_GD) {
9918 vcpu->arch.dr7 &= ~DR7_GD;
9919 kvm_update_dr7(vcpu);
9923 kvm_inject_exception(vcpu);
9925 vcpu->arch.exception.pending = false;
9926 vcpu->arch.exception.injected = true;
9931 /* Don't inject interrupts if the user asked to avoid doing so */
9932 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
9936 * Finally, inject interrupt events. If an event cannot be injected
9937 * due to architectural conditions (e.g. IF=0) a window-open exit
9938 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
9939 * and can architecturally be injected, but we cannot do it right now:
9940 * an interrupt could have arrived just now and we have to inject it
9941 * as a vmexit, or there could already an event in the queue, which is
9942 * indicated by can_inject. In that case we request an immediate exit
9943 * in order to make progress and get back here for another iteration.
9944 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
9946 #ifdef CONFIG_KVM_SMM
9947 if (vcpu->arch.smi_pending) {
9948 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
9952 vcpu->arch.smi_pending = false;
9953 ++vcpu->arch.smi_count;
9957 static_call(kvm_x86_enable_smi_window)(vcpu);
9961 if (vcpu->arch.nmi_pending) {
9962 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
9966 --vcpu->arch.nmi_pending;
9967 vcpu->arch.nmi_injected = true;
9968 static_call(kvm_x86_inject_nmi)(vcpu);
9970 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
9972 if (vcpu->arch.nmi_pending)
9973 static_call(kvm_x86_enable_nmi_window)(vcpu);
9976 if (kvm_cpu_has_injectable_intr(vcpu)) {
9977 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
9981 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
9982 static_call(kvm_x86_inject_irq)(vcpu, false);
9983 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
9985 if (kvm_cpu_has_injectable_intr(vcpu))
9986 static_call(kvm_x86_enable_irq_window)(vcpu);
9989 if (is_guest_mode(vcpu) &&
9990 kvm_x86_ops.nested_ops->has_events &&
9991 kvm_x86_ops.nested_ops->has_events(vcpu))
9992 *req_immediate_exit = true;
9995 * KVM must never queue a new exception while injecting an event; KVM
9996 * is done emulating and should only propagate the to-be-injected event
9997 * to the VMCS/VMCB. Queueing a new exception can put the vCPU into an
9998 * infinite loop as KVM will bail from VM-Enter to inject the pending
9999 * exception and start the cycle all over.
10001 * Exempt triple faults as they have special handling and won't put the
10002 * vCPU into an infinite loop. Triple fault can be queued when running
10003 * VMX without unrestricted guest, as that requires KVM to emulate Real
10004 * Mode events (see kvm_inject_realmode_interrupt()).
10006 WARN_ON_ONCE(vcpu->arch.exception.pending ||
10007 vcpu->arch.exception_vmexit.pending);
10012 *req_immediate_exit = true;
10018 static void process_nmi(struct kvm_vcpu *vcpu)
10020 unsigned limit = 2;
10023 * x86 is limited to one NMI running, and one NMI pending after it.
10024 * If an NMI is already in progress, limit further NMIs to just one.
10025 * Otherwise, allow two (and we'll inject the first one immediately).
10027 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
10030 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
10031 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
10032 kvm_make_request(KVM_REQ_EVENT, vcpu);
10035 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
10036 unsigned long *vcpu_bitmap)
10038 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
10041 void kvm_make_scan_ioapic_request(struct kvm *kvm)
10043 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
10046 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10048 struct kvm_lapic *apic = vcpu->arch.apic;
10051 if (!lapic_in_kernel(vcpu))
10054 down_read(&vcpu->kvm->arch.apicv_update_lock);
10057 /* Do not activate APICV when APIC is disabled */
10058 activate = kvm_vcpu_apicv_activated(vcpu) &&
10059 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED);
10061 if (apic->apicv_active == activate)
10064 apic->apicv_active = activate;
10065 kvm_apic_update_apicv(vcpu);
10066 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
10069 * When APICv gets disabled, we may still have injected interrupts
10070 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10071 * still active when the interrupt got accepted. Make sure
10072 * kvm_check_and_inject_events() is called to check for that.
10074 if (!apic->apicv_active)
10075 kvm_make_request(KVM_REQ_EVENT, vcpu);
10079 up_read(&vcpu->kvm->arch.apicv_update_lock);
10081 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
10083 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10084 enum kvm_apicv_inhibit reason, bool set)
10086 unsigned long old, new;
10088 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
10090 if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(reason))
10093 old = new = kvm->arch.apicv_inhibit_reasons;
10095 set_or_clear_apicv_inhibit(&new, reason, set);
10097 if (!!old != !!new) {
10099 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
10100 * false positives in the sanity check WARN in svm_vcpu_run().
10101 * This task will wait for all vCPUs to ack the kick IRQ before
10102 * updating apicv_inhibit_reasons, and all other vCPUs will
10103 * block on acquiring apicv_update_lock so that vCPUs can't
10104 * redo svm_vcpu_run() without seeing the new inhibit state.
10106 * Note, holding apicv_update_lock and taking it in the read
10107 * side (handling the request) also prevents other vCPUs from
10108 * servicing the request with a stale apicv_inhibit_reasons.
10110 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
10111 kvm->arch.apicv_inhibit_reasons = new;
10113 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
10114 int idx = srcu_read_lock(&kvm->srcu);
10116 kvm_zap_gfn_range(kvm, gfn, gfn+1);
10117 srcu_read_unlock(&kvm->srcu, idx);
10120 kvm->arch.apicv_inhibit_reasons = new;
10124 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10125 enum kvm_apicv_inhibit reason, bool set)
10130 down_write(&kvm->arch.apicv_update_lock);
10131 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10132 up_write(&kvm->arch.apicv_update_lock);
10134 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
10136 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
10138 if (!kvm_apic_present(vcpu))
10141 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
10143 if (irqchip_split(vcpu->kvm))
10144 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
10146 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10147 if (ioapic_in_kernel(vcpu->kvm))
10148 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
10151 if (is_guest_mode(vcpu))
10152 vcpu->arch.load_eoi_exitmap_pending = true;
10154 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
10157 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
10159 u64 eoi_exit_bitmap[4];
10161 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
10164 if (to_hv_vcpu(vcpu)) {
10165 bitmap_or((ulong *)eoi_exit_bitmap,
10166 vcpu->arch.ioapic_handled_vectors,
10167 to_hv_synic(vcpu)->vec_bitmap, 256);
10168 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
10172 static_call_cond(kvm_x86_load_eoi_exitmap)(
10173 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
10176 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
10177 unsigned long start, unsigned long end)
10179 unsigned long apic_address;
10182 * The physical address of apic access page is stored in the VMCS.
10183 * Update it when it becomes invalid.
10185 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
10186 if (start <= apic_address && apic_address < end)
10187 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
10190 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
10192 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
10195 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
10197 if (!lapic_in_kernel(vcpu))
10200 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
10203 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
10205 smp_send_reschedule(vcpu->cpu);
10207 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
10210 * Called within kvm->srcu read side.
10211 * Returns 1 to let vcpu_run() continue the guest execution loop without
10212 * exiting to the userspace. Otherwise, the value will be returned to the
10215 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
10219 dm_request_for_irq_injection(vcpu) &&
10220 kvm_cpu_accept_dm_intr(vcpu);
10221 fastpath_t exit_fastpath;
10223 bool req_immediate_exit = false;
10225 if (kvm_request_pending(vcpu)) {
10226 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
10231 if (kvm_dirty_ring_check_request(vcpu)) {
10236 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
10237 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
10242 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
10243 kvm_mmu_free_obsolete_roots(vcpu);
10244 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
10245 __kvm_migrate_timers(vcpu);
10246 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
10247 kvm_update_masterclock(vcpu->kvm);
10248 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
10249 kvm_gen_kvmclock_update(vcpu);
10250 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
10251 r = kvm_guest_time_update(vcpu);
10255 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10256 kvm_mmu_sync_roots(vcpu);
10257 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10258 kvm_mmu_load_pgd(vcpu);
10261 * Note, the order matters here, as flushing "all" TLB entries
10262 * also flushes the "current" TLB entries, i.e. servicing the
10263 * flush "all" will clear any request to flush "current".
10265 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
10266 kvm_vcpu_flush_tlb_all(vcpu);
10268 kvm_service_local_tlb_flush_requests(vcpu);
10271 * Fall back to a "full" guest flush if Hyper-V's precise
10272 * flushing fails. Note, Hyper-V's flushing is per-vCPU, but
10273 * the flushes are considered "remote" and not "local" because
10274 * the requests can be initiated from other vCPUs.
10276 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) &&
10277 kvm_hv_vcpu_flush_tlb(vcpu))
10278 kvm_vcpu_flush_tlb_guest(vcpu);
10280 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10281 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10285 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10286 if (is_guest_mode(vcpu))
10287 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10289 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10290 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10291 vcpu->mmio_needed = 0;
10296 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10297 /* Page is swapped out. Do synthetic halt */
10298 vcpu->arch.apf.halted = true;
10302 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10303 record_steal_time(vcpu);
10304 #ifdef CONFIG_KVM_SMM
10305 if (kvm_check_request(KVM_REQ_SMI, vcpu))
10308 if (kvm_check_request(KVM_REQ_NMI, vcpu))
10310 if (kvm_check_request(KVM_REQ_PMU, vcpu))
10311 kvm_pmu_handle_event(vcpu);
10312 if (kvm_check_request(KVM_REQ_PMI, vcpu))
10313 kvm_pmu_deliver_pmi(vcpu);
10314 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10315 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10316 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10317 vcpu->arch.ioapic_handled_vectors)) {
10318 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10319 vcpu->run->eoi.vector =
10320 vcpu->arch.pending_ioapic_eoi;
10325 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10326 vcpu_scan_ioapic(vcpu);
10327 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10328 vcpu_load_eoi_exitmap(vcpu);
10329 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10330 kvm_vcpu_reload_apic_access_page(vcpu);
10331 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10332 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10333 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10334 vcpu->run->system_event.ndata = 0;
10338 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10339 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10340 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10341 vcpu->run->system_event.ndata = 0;
10345 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10346 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10348 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10349 vcpu->run->hyperv = hv_vcpu->exit;
10355 * KVM_REQ_HV_STIMER has to be processed after
10356 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10357 * depend on the guest clock being up-to-date
10359 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10360 kvm_hv_process_stimers(vcpu);
10361 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10362 kvm_vcpu_update_apicv(vcpu);
10363 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10364 kvm_check_async_pf_completion(vcpu);
10365 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10366 static_call(kvm_x86_msr_filter_changed)(vcpu);
10368 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10369 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10372 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10373 kvm_xen_has_interrupt(vcpu)) {
10374 ++vcpu->stat.req_event;
10375 r = kvm_apic_accept_events(vcpu);
10380 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10385 r = kvm_check_and_inject_events(vcpu, &req_immediate_exit);
10391 static_call(kvm_x86_enable_irq_window)(vcpu);
10393 if (kvm_lapic_enabled(vcpu)) {
10394 update_cr8_intercept(vcpu);
10395 kvm_lapic_sync_to_vapic(vcpu);
10399 r = kvm_mmu_reload(vcpu);
10401 goto cancel_injection;
10406 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10409 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10410 * IPI are then delayed after guest entry, which ensures that they
10411 * result in virtual interrupt delivery.
10413 local_irq_disable();
10415 /* Store vcpu->apicv_active before vcpu->mode. */
10416 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10418 kvm_vcpu_srcu_read_unlock(vcpu);
10421 * 1) We should set ->mode before checking ->requests. Please see
10422 * the comment in kvm_vcpu_exiting_guest_mode().
10424 * 2) For APICv, we should set ->mode before checking PID.ON. This
10425 * pairs with the memory barrier implicit in pi_test_and_set_on
10426 * (see vmx_deliver_posted_interrupt).
10428 * 3) This also orders the write to mode from any reads to the page
10429 * tables done while the VCPU is running. Please see the comment
10430 * in kvm_flush_remote_tlbs.
10432 smp_mb__after_srcu_read_unlock();
10435 * Process pending posted interrupts to handle the case where the
10436 * notification IRQ arrived in the host, or was never sent (because the
10437 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10438 * status, KVM doesn't update assigned devices when APICv is inhibited,
10439 * i.e. they can post interrupts even if APICv is temporarily disabled.
10441 if (kvm_lapic_enabled(vcpu))
10442 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10444 if (kvm_vcpu_exit_request(vcpu)) {
10445 vcpu->mode = OUTSIDE_GUEST_MODE;
10447 local_irq_enable();
10449 kvm_vcpu_srcu_read_lock(vcpu);
10451 goto cancel_injection;
10454 if (req_immediate_exit) {
10455 kvm_make_request(KVM_REQ_EVENT, vcpu);
10456 static_call(kvm_x86_request_immediate_exit)(vcpu);
10459 fpregs_assert_state_consistent();
10460 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10461 switch_fpu_return();
10463 if (vcpu->arch.guest_fpu.xfd_err)
10464 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10466 if (unlikely(vcpu->arch.switch_db_regs)) {
10467 set_debugreg(0, 7);
10468 set_debugreg(vcpu->arch.eff_db[0], 0);
10469 set_debugreg(vcpu->arch.eff_db[1], 1);
10470 set_debugreg(vcpu->arch.eff_db[2], 2);
10471 set_debugreg(vcpu->arch.eff_db[3], 3);
10472 } else if (unlikely(hw_breakpoint_active())) {
10473 set_debugreg(0, 7);
10476 guest_timing_enter_irqoff();
10480 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10481 * update must kick and wait for all vCPUs before toggling the
10482 * per-VM state, and responsing vCPUs must wait for the update
10483 * to complete before servicing KVM_REQ_APICV_UPDATE.
10485 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&
10486 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED));
10488 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10489 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10492 if (kvm_lapic_enabled(vcpu))
10493 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10495 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10496 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10502 * Do this here before restoring debug registers on the host. And
10503 * since we do this before handling the vmexit, a DR access vmexit
10504 * can (a) read the correct value of the debug registers, (b) set
10505 * KVM_DEBUGREG_WONT_EXIT again.
10507 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10508 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10509 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10510 kvm_update_dr0123(vcpu);
10511 kvm_update_dr7(vcpu);
10515 * If the guest has used debug registers, at least dr7
10516 * will be disabled while returning to the host.
10517 * If we don't have active breakpoints in the host, we don't
10518 * care about the messed up debug address registers. But if
10519 * we have some of them active, restore the old state.
10521 if (hw_breakpoint_active())
10522 hw_breakpoint_restore();
10524 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10525 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10527 vcpu->mode = OUTSIDE_GUEST_MODE;
10531 * Sync xfd before calling handle_exit_irqoff() which may
10532 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10533 * in #NM irqoff handler).
10535 if (vcpu->arch.xfd_no_write_intercept)
10536 fpu_sync_guest_vmexit_xfd_state();
10538 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10540 if (vcpu->arch.guest_fpu.xfd_err)
10541 wrmsrl(MSR_IA32_XFD_ERR, 0);
10544 * Consume any pending interrupts, including the possible source of
10545 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10546 * An instruction is required after local_irq_enable() to fully unblock
10547 * interrupts on processors that implement an interrupt shadow, the
10548 * stat.exits increment will do nicely.
10550 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10551 local_irq_enable();
10552 ++vcpu->stat.exits;
10553 local_irq_disable();
10554 kvm_after_interrupt(vcpu);
10557 * Wait until after servicing IRQs to account guest time so that any
10558 * ticks that occurred while running the guest are properly accounted
10559 * to the guest. Waiting until IRQs are enabled degrades the accuracy
10560 * of accounting via context tracking, but the loss of accuracy is
10561 * acceptable for all known use cases.
10563 guest_timing_exit_irqoff();
10565 local_irq_enable();
10568 kvm_vcpu_srcu_read_lock(vcpu);
10571 * Profile KVM exit RIPs:
10573 if (unlikely(prof_on == KVM_PROFILING)) {
10574 unsigned long rip = kvm_rip_read(vcpu);
10575 profile_hit(KVM_PROFILING, (void *)rip);
10578 if (unlikely(vcpu->arch.tsc_always_catchup))
10579 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10581 if (vcpu->arch.apic_attention)
10582 kvm_lapic_sync_from_vapic(vcpu);
10584 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10588 if (req_immediate_exit)
10589 kvm_make_request(KVM_REQ_EVENT, vcpu);
10590 static_call(kvm_x86_cancel_injection)(vcpu);
10591 if (unlikely(vcpu->arch.apic_attention))
10592 kvm_lapic_sync_from_vapic(vcpu);
10597 /* Called within kvm->srcu read side. */
10598 static inline int vcpu_block(struct kvm_vcpu *vcpu)
10602 if (!kvm_arch_vcpu_runnable(vcpu)) {
10604 * Switch to the software timer before halt-polling/blocking as
10605 * the guest's timer may be a break event for the vCPU, and the
10606 * hypervisor timer runs only when the CPU is in guest mode.
10607 * Switch before halt-polling so that KVM recognizes an expired
10608 * timer before blocking.
10610 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10612 kvm_lapic_switch_to_sw_timer(vcpu);
10614 kvm_vcpu_srcu_read_unlock(vcpu);
10615 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10616 kvm_vcpu_halt(vcpu);
10618 kvm_vcpu_block(vcpu);
10619 kvm_vcpu_srcu_read_lock(vcpu);
10622 kvm_lapic_switch_to_hv_timer(vcpu);
10625 * If the vCPU is not runnable, a signal or another host event
10626 * of some kind is pending; service it without changing the
10627 * vCPU's activity state.
10629 if (!kvm_arch_vcpu_runnable(vcpu))
10634 * Evaluate nested events before exiting the halted state. This allows
10635 * the halt state to be recorded properly in the VMCS12's activity
10636 * state field (AMD does not have a similar field and a VM-Exit always
10637 * causes a spurious wakeup from HLT).
10639 if (is_guest_mode(vcpu)) {
10640 if (kvm_check_nested_events(vcpu) < 0)
10644 if (kvm_apic_accept_events(vcpu) < 0)
10646 switch(vcpu->arch.mp_state) {
10647 case KVM_MP_STATE_HALTED:
10648 case KVM_MP_STATE_AP_RESET_HOLD:
10649 vcpu->arch.pv.pv_unhalted = false;
10650 vcpu->arch.mp_state =
10651 KVM_MP_STATE_RUNNABLE;
10653 case KVM_MP_STATE_RUNNABLE:
10654 vcpu->arch.apf.halted = false;
10656 case KVM_MP_STATE_INIT_RECEIVED:
10665 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10667 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10668 !vcpu->arch.apf.halted);
10671 /* Called within kvm->srcu read side. */
10672 static int vcpu_run(struct kvm_vcpu *vcpu)
10676 vcpu->arch.l1tf_flush_l1d = true;
10680 * If another guest vCPU requests a PV TLB flush in the middle
10681 * of instruction emulation, the rest of the emulation could
10682 * use a stale page translation. Assume that any code after
10683 * this point can start executing an instruction.
10685 vcpu->arch.at_instruction_boundary = false;
10686 if (kvm_vcpu_running(vcpu)) {
10687 r = vcpu_enter_guest(vcpu);
10689 r = vcpu_block(vcpu);
10695 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
10696 if (kvm_xen_has_pending_events(vcpu))
10697 kvm_xen_inject_pending_events(vcpu);
10699 if (kvm_cpu_has_pending_timer(vcpu))
10700 kvm_inject_pending_timer_irqs(vcpu);
10702 if (dm_request_for_irq_injection(vcpu) &&
10703 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
10705 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
10706 ++vcpu->stat.request_irq_exits;
10710 if (__xfer_to_guest_mode_work_pending()) {
10711 kvm_vcpu_srcu_read_unlock(vcpu);
10712 r = xfer_to_guest_mode_handle_work(vcpu);
10713 kvm_vcpu_srcu_read_lock(vcpu);
10722 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
10724 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
10727 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
10729 BUG_ON(!vcpu->arch.pio.count);
10731 return complete_emulated_io(vcpu);
10735 * Implements the following, as a state machine:
10738 * for each fragment
10739 * for each mmio piece in the fragment
10746 * for each fragment
10747 * for each mmio piece in the fragment
10752 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
10754 struct kvm_run *run = vcpu->run;
10755 struct kvm_mmio_fragment *frag;
10758 BUG_ON(!vcpu->mmio_needed);
10760 /* Complete previous fragment */
10761 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
10762 len = min(8u, frag->len);
10763 if (!vcpu->mmio_is_write)
10764 memcpy(frag->data, run->mmio.data, len);
10766 if (frag->len <= 8) {
10767 /* Switch to the next fragment. */
10769 vcpu->mmio_cur_fragment++;
10771 /* Go forward to the next mmio piece. */
10777 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
10778 vcpu->mmio_needed = 0;
10780 /* FIXME: return into emulator if single-stepping. */
10781 if (vcpu->mmio_is_write)
10783 vcpu->mmio_read_completed = 1;
10784 return complete_emulated_io(vcpu);
10787 run->exit_reason = KVM_EXIT_MMIO;
10788 run->mmio.phys_addr = frag->gpa;
10789 if (vcpu->mmio_is_write)
10790 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
10791 run->mmio.len = min(8u, frag->len);
10792 run->mmio.is_write = vcpu->mmio_is_write;
10793 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
10797 /* Swap (qemu) user FPU context for the guest FPU context. */
10798 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
10800 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
10801 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
10805 /* When vcpu_run ends, restore user space FPU context. */
10806 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
10808 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
10809 ++vcpu->stat.fpu_reload;
10813 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
10815 struct kvm_queued_exception *ex = &vcpu->arch.exception;
10816 struct kvm_run *kvm_run = vcpu->run;
10820 kvm_sigset_activate(vcpu);
10821 kvm_run->flags = 0;
10822 kvm_load_guest_fpu(vcpu);
10824 kvm_vcpu_srcu_read_lock(vcpu);
10825 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
10826 if (kvm_run->immediate_exit) {
10831 * It should be impossible for the hypervisor timer to be in
10832 * use before KVM has ever run the vCPU.
10834 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu));
10836 kvm_vcpu_srcu_read_unlock(vcpu);
10837 kvm_vcpu_block(vcpu);
10838 kvm_vcpu_srcu_read_lock(vcpu);
10840 if (kvm_apic_accept_events(vcpu) < 0) {
10845 if (signal_pending(current)) {
10847 kvm_run->exit_reason = KVM_EXIT_INTR;
10848 ++vcpu->stat.signal_exits;
10853 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
10854 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
10859 if (kvm_run->kvm_dirty_regs) {
10860 r = sync_regs(vcpu);
10865 /* re-sync apic's tpr */
10866 if (!lapic_in_kernel(vcpu)) {
10867 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
10874 * If userspace set a pending exception and L2 is active, convert it to
10875 * a pending VM-Exit if L1 wants to intercept the exception.
10877 if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) &&
10878 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector,
10880 kvm_queue_exception_vmexit(vcpu, ex->vector,
10881 ex->has_error_code, ex->error_code,
10882 ex->has_payload, ex->payload);
10883 ex->injected = false;
10884 ex->pending = false;
10886 vcpu->arch.exception_from_userspace = false;
10888 if (unlikely(vcpu->arch.complete_userspace_io)) {
10889 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
10890 vcpu->arch.complete_userspace_io = NULL;
10895 WARN_ON_ONCE(vcpu->arch.pio.count);
10896 WARN_ON_ONCE(vcpu->mmio_needed);
10899 if (kvm_run->immediate_exit) {
10904 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
10908 r = vcpu_run(vcpu);
10911 kvm_put_guest_fpu(vcpu);
10912 if (kvm_run->kvm_valid_regs)
10914 post_kvm_run_save(vcpu);
10915 kvm_vcpu_srcu_read_unlock(vcpu);
10917 kvm_sigset_deactivate(vcpu);
10922 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10924 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
10926 * We are here if userspace calls get_regs() in the middle of
10927 * instruction emulation. Registers state needs to be copied
10928 * back from emulation context to vcpu. Userspace shouldn't do
10929 * that usually, but some bad designed PV devices (vmware
10930 * backdoor interface) need this to work
10932 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
10933 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10935 regs->rax = kvm_rax_read(vcpu);
10936 regs->rbx = kvm_rbx_read(vcpu);
10937 regs->rcx = kvm_rcx_read(vcpu);
10938 regs->rdx = kvm_rdx_read(vcpu);
10939 regs->rsi = kvm_rsi_read(vcpu);
10940 regs->rdi = kvm_rdi_read(vcpu);
10941 regs->rsp = kvm_rsp_read(vcpu);
10942 regs->rbp = kvm_rbp_read(vcpu);
10943 #ifdef CONFIG_X86_64
10944 regs->r8 = kvm_r8_read(vcpu);
10945 regs->r9 = kvm_r9_read(vcpu);
10946 regs->r10 = kvm_r10_read(vcpu);
10947 regs->r11 = kvm_r11_read(vcpu);
10948 regs->r12 = kvm_r12_read(vcpu);
10949 regs->r13 = kvm_r13_read(vcpu);
10950 regs->r14 = kvm_r14_read(vcpu);
10951 regs->r15 = kvm_r15_read(vcpu);
10954 regs->rip = kvm_rip_read(vcpu);
10955 regs->rflags = kvm_get_rflags(vcpu);
10958 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10961 __get_regs(vcpu, regs);
10966 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10968 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
10969 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10971 kvm_rax_write(vcpu, regs->rax);
10972 kvm_rbx_write(vcpu, regs->rbx);
10973 kvm_rcx_write(vcpu, regs->rcx);
10974 kvm_rdx_write(vcpu, regs->rdx);
10975 kvm_rsi_write(vcpu, regs->rsi);
10976 kvm_rdi_write(vcpu, regs->rdi);
10977 kvm_rsp_write(vcpu, regs->rsp);
10978 kvm_rbp_write(vcpu, regs->rbp);
10979 #ifdef CONFIG_X86_64
10980 kvm_r8_write(vcpu, regs->r8);
10981 kvm_r9_write(vcpu, regs->r9);
10982 kvm_r10_write(vcpu, regs->r10);
10983 kvm_r11_write(vcpu, regs->r11);
10984 kvm_r12_write(vcpu, regs->r12);
10985 kvm_r13_write(vcpu, regs->r13);
10986 kvm_r14_write(vcpu, regs->r14);
10987 kvm_r15_write(vcpu, regs->r15);
10990 kvm_rip_write(vcpu, regs->rip);
10991 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
10993 vcpu->arch.exception.pending = false;
10994 vcpu->arch.exception_vmexit.pending = false;
10996 kvm_make_request(KVM_REQ_EVENT, vcpu);
10999 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11002 __set_regs(vcpu, regs);
11007 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11009 struct desc_ptr dt;
11011 if (vcpu->arch.guest_state_protected)
11012 goto skip_protected_regs;
11014 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11015 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11016 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11017 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11018 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11019 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11021 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11022 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11024 static_call(kvm_x86_get_idt)(vcpu, &dt);
11025 sregs->idt.limit = dt.size;
11026 sregs->idt.base = dt.address;
11027 static_call(kvm_x86_get_gdt)(vcpu, &dt);
11028 sregs->gdt.limit = dt.size;
11029 sregs->gdt.base = dt.address;
11031 sregs->cr2 = vcpu->arch.cr2;
11032 sregs->cr3 = kvm_read_cr3(vcpu);
11034 skip_protected_regs:
11035 sregs->cr0 = kvm_read_cr0(vcpu);
11036 sregs->cr4 = kvm_read_cr4(vcpu);
11037 sregs->cr8 = kvm_get_cr8(vcpu);
11038 sregs->efer = vcpu->arch.efer;
11039 sregs->apic_base = kvm_get_apic_base(vcpu);
11042 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11044 __get_sregs_common(vcpu, sregs);
11046 if (vcpu->arch.guest_state_protected)
11049 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
11050 set_bit(vcpu->arch.interrupt.nr,
11051 (unsigned long *)sregs->interrupt_bitmap);
11054 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11058 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
11060 if (vcpu->arch.guest_state_protected)
11063 if (is_pae_paging(vcpu)) {
11064 for (i = 0 ; i < 4 ; i++)
11065 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
11066 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
11070 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
11071 struct kvm_sregs *sregs)
11074 __get_sregs(vcpu, sregs);
11079 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
11080 struct kvm_mp_state *mp_state)
11085 if (kvm_mpx_supported())
11086 kvm_load_guest_fpu(vcpu);
11088 r = kvm_apic_accept_events(vcpu);
11093 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
11094 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
11095 vcpu->arch.pv.pv_unhalted)
11096 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
11098 mp_state->mp_state = vcpu->arch.mp_state;
11101 if (kvm_mpx_supported())
11102 kvm_put_guest_fpu(vcpu);
11107 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
11108 struct kvm_mp_state *mp_state)
11114 switch (mp_state->mp_state) {
11115 case KVM_MP_STATE_UNINITIALIZED:
11116 case KVM_MP_STATE_HALTED:
11117 case KVM_MP_STATE_AP_RESET_HOLD:
11118 case KVM_MP_STATE_INIT_RECEIVED:
11119 case KVM_MP_STATE_SIPI_RECEIVED:
11120 if (!lapic_in_kernel(vcpu))
11124 case KVM_MP_STATE_RUNNABLE:
11132 * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow
11133 * forcing the guest into INIT/SIPI if those events are supposed to be
11134 * blocked. KVM prioritizes SMI over INIT, so reject INIT/SIPI state
11135 * if an SMI is pending as well.
11137 if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) &&
11138 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
11139 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
11142 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
11143 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
11144 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
11146 vcpu->arch.mp_state = mp_state->mp_state;
11147 kvm_make_request(KVM_REQ_EVENT, vcpu);
11155 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
11156 int reason, bool has_error_code, u32 error_code)
11158 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
11161 init_emulate_ctxt(vcpu);
11163 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
11164 has_error_code, error_code);
11166 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11167 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11168 vcpu->run->internal.ndata = 0;
11172 kvm_rip_write(vcpu, ctxt->eip);
11173 kvm_set_rflags(vcpu, ctxt->eflags);
11176 EXPORT_SYMBOL_GPL(kvm_task_switch);
11178 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11180 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
11182 * When EFER.LME and CR0.PG are set, the processor is in
11183 * 64-bit mode (though maybe in a 32-bit code segment).
11184 * CR4.PAE and EFER.LMA must be set.
11186 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
11188 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
11192 * Not in 64-bit mode: EFER.LMA is clear and the code
11193 * segment cannot be 64-bit.
11195 if (sregs->efer & EFER_LMA || sregs->cs.l)
11199 return kvm_is_valid_cr4(vcpu, sregs->cr4);
11202 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
11203 int *mmu_reset_needed, bool update_pdptrs)
11205 struct msr_data apic_base_msr;
11207 struct desc_ptr dt;
11209 if (!kvm_is_valid_sregs(vcpu, sregs))
11212 apic_base_msr.data = sregs->apic_base;
11213 apic_base_msr.host_initiated = true;
11214 if (kvm_set_apic_base(vcpu, &apic_base_msr))
11217 if (vcpu->arch.guest_state_protected)
11220 dt.size = sregs->idt.limit;
11221 dt.address = sregs->idt.base;
11222 static_call(kvm_x86_set_idt)(vcpu, &dt);
11223 dt.size = sregs->gdt.limit;
11224 dt.address = sregs->gdt.base;
11225 static_call(kvm_x86_set_gdt)(vcpu, &dt);
11227 vcpu->arch.cr2 = sregs->cr2;
11228 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
11229 vcpu->arch.cr3 = sregs->cr3;
11230 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11231 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
11233 kvm_set_cr8(vcpu, sregs->cr8);
11235 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
11236 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
11238 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
11239 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
11240 vcpu->arch.cr0 = sregs->cr0;
11242 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
11243 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
11245 if (update_pdptrs) {
11246 idx = srcu_read_lock(&vcpu->kvm->srcu);
11247 if (is_pae_paging(vcpu)) {
11248 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
11249 *mmu_reset_needed = 1;
11251 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11254 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11255 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11256 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11257 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11258 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11259 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11261 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11262 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11264 update_cr8_intercept(vcpu);
11266 /* Older userspace won't unhalt the vcpu on reset. */
11267 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
11268 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
11269 !is_protmode(vcpu))
11270 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11275 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11277 int pending_vec, max_bits;
11278 int mmu_reset_needed = 0;
11279 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
11284 if (mmu_reset_needed)
11285 kvm_mmu_reset_context(vcpu);
11287 max_bits = KVM_NR_INTERRUPTS;
11288 pending_vec = find_first_bit(
11289 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
11291 if (pending_vec < max_bits) {
11292 kvm_queue_interrupt(vcpu, pending_vec, false);
11293 pr_debug("Set back pending irq %d\n", pending_vec);
11294 kvm_make_request(KVM_REQ_EVENT, vcpu);
11299 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11301 int mmu_reset_needed = 0;
11302 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
11303 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
11304 !(sregs2->efer & EFER_LMA);
11307 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11310 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11313 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11314 &mmu_reset_needed, !valid_pdptrs);
11318 if (valid_pdptrs) {
11319 for (i = 0; i < 4 ; i++)
11320 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11322 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11323 mmu_reset_needed = 1;
11324 vcpu->arch.pdptrs_from_userspace = true;
11326 if (mmu_reset_needed)
11327 kvm_mmu_reset_context(vcpu);
11331 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11332 struct kvm_sregs *sregs)
11337 ret = __set_sregs(vcpu, sregs);
11342 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11345 struct kvm_vcpu *vcpu;
11351 down_write(&kvm->arch.apicv_update_lock);
11353 kvm_for_each_vcpu(i, vcpu, kvm) {
11354 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11359 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11360 up_write(&kvm->arch.apicv_update_lock);
11363 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11364 struct kvm_guest_debug *dbg)
11366 unsigned long rflags;
11369 if (vcpu->arch.guest_state_protected)
11374 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11376 if (kvm_is_exception_pending(vcpu))
11378 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11379 kvm_queue_exception(vcpu, DB_VECTOR);
11381 kvm_queue_exception(vcpu, BP_VECTOR);
11385 * Read rflags as long as potentially injected trace flags are still
11388 rflags = kvm_get_rflags(vcpu);
11390 vcpu->guest_debug = dbg->control;
11391 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11392 vcpu->guest_debug = 0;
11394 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11395 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11396 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11397 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11399 for (i = 0; i < KVM_NR_DB_REGS; i++)
11400 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11402 kvm_update_dr7(vcpu);
11404 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11405 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11408 * Trigger an rflags update that will inject or remove the trace
11411 kvm_set_rflags(vcpu, rflags);
11413 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11415 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11425 * Translate a guest virtual address to a guest physical address.
11427 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11428 struct kvm_translation *tr)
11430 unsigned long vaddr = tr->linear_address;
11436 idx = srcu_read_lock(&vcpu->kvm->srcu);
11437 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11438 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11439 tr->physical_address = gpa;
11440 tr->valid = gpa != INVALID_GPA;
11448 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11450 struct fxregs_state *fxsave;
11452 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11457 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11458 memcpy(fpu->fpr, fxsave->st_space, 128);
11459 fpu->fcw = fxsave->cwd;
11460 fpu->fsw = fxsave->swd;
11461 fpu->ftwx = fxsave->twd;
11462 fpu->last_opcode = fxsave->fop;
11463 fpu->last_ip = fxsave->rip;
11464 fpu->last_dp = fxsave->rdp;
11465 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11471 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11473 struct fxregs_state *fxsave;
11475 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11480 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11482 memcpy(fxsave->st_space, fpu->fpr, 128);
11483 fxsave->cwd = fpu->fcw;
11484 fxsave->swd = fpu->fsw;
11485 fxsave->twd = fpu->ftwx;
11486 fxsave->fop = fpu->last_opcode;
11487 fxsave->rip = fpu->last_ip;
11488 fxsave->rdp = fpu->last_dp;
11489 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11495 static void store_regs(struct kvm_vcpu *vcpu)
11497 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11499 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11500 __get_regs(vcpu, &vcpu->run->s.regs.regs);
11502 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11503 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11505 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11506 kvm_vcpu_ioctl_x86_get_vcpu_events(
11507 vcpu, &vcpu->run->s.regs.events);
11510 static int sync_regs(struct kvm_vcpu *vcpu)
11512 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11513 __set_regs(vcpu, &vcpu->run->s.regs.regs);
11514 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11516 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11517 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
11519 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11521 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11522 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
11523 vcpu, &vcpu->run->s.regs.events))
11525 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11531 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11533 if (kvm_check_tsc_unstable() && kvm->created_vcpus)
11534 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
11535 "guest TSC will not be reliable\n");
11537 if (!kvm->arch.max_vcpu_ids)
11538 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
11540 if (id >= kvm->arch.max_vcpu_ids)
11543 return static_call(kvm_x86_vcpu_precreate)(kvm);
11546 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11551 vcpu->arch.last_vmentry_cpu = -1;
11552 vcpu->arch.regs_avail = ~0;
11553 vcpu->arch.regs_dirty = ~0;
11555 kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm, vcpu, KVM_HOST_USES_PFN);
11557 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11558 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11560 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11562 r = kvm_mmu_create(vcpu);
11566 if (irqchip_in_kernel(vcpu->kvm)) {
11567 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11569 goto fail_mmu_destroy;
11572 * Defer evaluating inhibits until the vCPU is first run, as
11573 * this vCPU will not get notified of any changes until this
11574 * vCPU is visible to other vCPUs (marked online and added to
11575 * the set of vCPUs). Opportunistically mark APICv active as
11576 * VMX in particularly is highly unlikely to have inhibits.
11577 * Ignore the current per-VM APICv state so that vCPU creation
11578 * is guaranteed to run with a deterministic value, the request
11579 * will ensure the vCPU gets the correct state before VM-Entry.
11581 if (enable_apicv) {
11582 vcpu->arch.apic->apicv_active = true;
11583 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
11586 static_branch_inc(&kvm_has_noapic_vcpu);
11590 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11592 goto fail_free_lapic;
11593 vcpu->arch.pio_data = page_address(page);
11595 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
11596 GFP_KERNEL_ACCOUNT);
11597 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
11598 GFP_KERNEL_ACCOUNT);
11599 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
11600 goto fail_free_mce_banks;
11601 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11603 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11604 GFP_KERNEL_ACCOUNT))
11605 goto fail_free_mce_banks;
11607 if (!alloc_emulate_ctxt(vcpu))
11608 goto free_wbinvd_dirty_mask;
11610 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11611 pr_err("kvm: failed to allocate vcpu's fpu\n");
11612 goto free_emulate_ctxt;
11615 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11616 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11618 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11620 kvm_async_pf_hash_reset(vcpu);
11622 vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap;
11623 kvm_pmu_init(vcpu);
11625 vcpu->arch.pending_external_vector = -1;
11626 vcpu->arch.preempted_in_kernel = false;
11628 #if IS_ENABLED(CONFIG_HYPERV)
11629 vcpu->arch.hv_root_tdp = INVALID_PAGE;
11632 r = static_call(kvm_x86_vcpu_create)(vcpu);
11634 goto free_guest_fpu;
11636 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11637 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11638 kvm_xen_init_vcpu(vcpu);
11639 kvm_vcpu_mtrr_init(vcpu);
11641 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
11642 kvm_vcpu_reset(vcpu, false);
11643 kvm_init_mmu(vcpu);
11648 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11650 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11651 free_wbinvd_dirty_mask:
11652 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11653 fail_free_mce_banks:
11654 kfree(vcpu->arch.mce_banks);
11655 kfree(vcpu->arch.mci_ctl2_banks);
11656 free_page((unsigned long)vcpu->arch.pio_data);
11658 kvm_free_lapic(vcpu);
11660 kvm_mmu_destroy(vcpu);
11664 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11666 struct kvm *kvm = vcpu->kvm;
11668 if (mutex_lock_killable(&vcpu->mutex))
11671 kvm_synchronize_tsc(vcpu, 0);
11674 /* poll control enabled by default */
11675 vcpu->arch.msr_kvm_poll_control = 1;
11677 mutex_unlock(&vcpu->mutex);
11679 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11680 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
11681 KVMCLOCK_SYNC_PERIOD);
11684 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
11688 kvmclock_reset(vcpu);
11690 static_call(kvm_x86_vcpu_free)(vcpu);
11692 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11693 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11694 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11696 kvm_xen_destroy_vcpu(vcpu);
11697 kvm_hv_vcpu_uninit(vcpu);
11698 kvm_pmu_destroy(vcpu);
11699 kfree(vcpu->arch.mce_banks);
11700 kfree(vcpu->arch.mci_ctl2_banks);
11701 kvm_free_lapic(vcpu);
11702 idx = srcu_read_lock(&vcpu->kvm->srcu);
11703 kvm_mmu_destroy(vcpu);
11704 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11705 free_page((unsigned long)vcpu->arch.pio_data);
11706 kvfree(vcpu->arch.cpuid_entries);
11707 if (!lapic_in_kernel(vcpu))
11708 static_branch_dec(&kvm_has_noapic_vcpu);
11711 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
11713 struct kvm_cpuid_entry2 *cpuid_0x1;
11714 unsigned long old_cr0 = kvm_read_cr0(vcpu);
11715 unsigned long new_cr0;
11718 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
11719 * to handle side effects. RESET emulation hits those flows and relies
11720 * on emulated/virtualized registers, including those that are loaded
11721 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
11722 * to detect improper or missing initialization.
11724 WARN_ON_ONCE(!init_event &&
11725 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
11728 * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's
11729 * possible to INIT the vCPU while L2 is active. Force the vCPU back
11730 * into L1 as EFER.SVME is cleared on INIT (along with all other EFER
11731 * bits), i.e. virtualization is disabled.
11733 if (is_guest_mode(vcpu))
11734 kvm_leave_nested(vcpu);
11736 kvm_lapic_reset(vcpu, init_event);
11738 WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu));
11739 vcpu->arch.hflags = 0;
11741 vcpu->arch.smi_pending = 0;
11742 vcpu->arch.smi_count = 0;
11743 atomic_set(&vcpu->arch.nmi_queued, 0);
11744 vcpu->arch.nmi_pending = 0;
11745 vcpu->arch.nmi_injected = false;
11746 kvm_clear_interrupt_queue(vcpu);
11747 kvm_clear_exception_queue(vcpu);
11749 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
11750 kvm_update_dr0123(vcpu);
11751 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
11752 vcpu->arch.dr7 = DR7_FIXED_1;
11753 kvm_update_dr7(vcpu);
11755 vcpu->arch.cr2 = 0;
11757 kvm_make_request(KVM_REQ_EVENT, vcpu);
11758 vcpu->arch.apf.msr_en_val = 0;
11759 vcpu->arch.apf.msr_int_val = 0;
11760 vcpu->arch.st.msr_val = 0;
11762 kvmclock_reset(vcpu);
11764 kvm_clear_async_pf_completion_queue(vcpu);
11765 kvm_async_pf_hash_reset(vcpu);
11766 vcpu->arch.apf.halted = false;
11768 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
11769 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
11772 * All paths that lead to INIT are required to load the guest's
11773 * FPU state (because most paths are buried in KVM_RUN).
11776 kvm_put_guest_fpu(vcpu);
11778 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
11779 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
11782 kvm_load_guest_fpu(vcpu);
11786 kvm_pmu_reset(vcpu);
11787 vcpu->arch.smbase = 0x30000;
11789 vcpu->arch.msr_misc_features_enables = 0;
11790 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
11791 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
11793 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
11794 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
11797 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
11798 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
11799 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
11802 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
11803 * if no CPUID match is found. Note, it's impossible to get a match at
11804 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
11805 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
11806 * on RESET. But, go through the motions in case that's ever remedied.
11808 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1);
11809 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
11811 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
11813 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
11814 kvm_rip_write(vcpu, 0xfff0);
11816 vcpu->arch.cr3 = 0;
11817 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11820 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
11821 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
11822 * (or qualify) that with a footnote stating that CD/NW are preserved.
11824 new_cr0 = X86_CR0_ET;
11826 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
11828 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
11830 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
11831 static_call(kvm_x86_set_cr4)(vcpu, 0);
11832 static_call(kvm_x86_set_efer)(vcpu, 0);
11833 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11836 * On the standard CR0/CR4/EFER modification paths, there are several
11837 * complex conditions determining whether the MMU has to be reset and/or
11838 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
11839 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
11840 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
11841 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
11843 if (old_cr0 & X86_CR0_PG) {
11844 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11845 kvm_mmu_reset_context(vcpu);
11849 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
11850 * APM states the TLBs are untouched by INIT, but it also states that
11851 * the TLBs are flushed on "External initialization of the processor."
11852 * Flush the guest TLB regardless of vendor, there is no meaningful
11853 * benefit in relying on the guest to flush the TLB immediately after
11854 * INIT. A spurious TLB flush is benign and likely negligible from a
11855 * performance perspective.
11858 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11860 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
11862 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
11864 struct kvm_segment cs;
11866 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
11867 cs.selector = vector << 8;
11868 cs.base = vector << 12;
11869 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
11870 kvm_rip_write(vcpu, 0);
11872 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
11874 int kvm_arch_hardware_enable(void)
11877 struct kvm_vcpu *vcpu;
11882 bool stable, backwards_tsc = false;
11884 kvm_user_return_msr_cpu_online();
11885 ret = static_call(kvm_x86_hardware_enable)();
11889 local_tsc = rdtsc();
11890 stable = !kvm_check_tsc_unstable();
11891 list_for_each_entry(kvm, &vm_list, vm_list) {
11892 kvm_for_each_vcpu(i, vcpu, kvm) {
11893 if (!stable && vcpu->cpu == smp_processor_id())
11894 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
11895 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
11896 backwards_tsc = true;
11897 if (vcpu->arch.last_host_tsc > max_tsc)
11898 max_tsc = vcpu->arch.last_host_tsc;
11904 * Sometimes, even reliable TSCs go backwards. This happens on
11905 * platforms that reset TSC during suspend or hibernate actions, but
11906 * maintain synchronization. We must compensate. Fortunately, we can
11907 * detect that condition here, which happens early in CPU bringup,
11908 * before any KVM threads can be running. Unfortunately, we can't
11909 * bring the TSCs fully up to date with real time, as we aren't yet far
11910 * enough into CPU bringup that we know how much real time has actually
11911 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
11912 * variables that haven't been updated yet.
11914 * So we simply find the maximum observed TSC above, then record the
11915 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
11916 * the adjustment will be applied. Note that we accumulate
11917 * adjustments, in case multiple suspend cycles happen before some VCPU
11918 * gets a chance to run again. In the event that no KVM threads get a
11919 * chance to run, we will miss the entire elapsed period, as we'll have
11920 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
11921 * loose cycle time. This isn't too big a deal, since the loss will be
11922 * uniform across all VCPUs (not to mention the scenario is extremely
11923 * unlikely). It is possible that a second hibernate recovery happens
11924 * much faster than a first, causing the observed TSC here to be
11925 * smaller; this would require additional padding adjustment, which is
11926 * why we set last_host_tsc to the local tsc observed here.
11928 * N.B. - this code below runs only on platforms with reliable TSC,
11929 * as that is the only way backwards_tsc is set above. Also note
11930 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
11931 * have the same delta_cyc adjustment applied if backwards_tsc
11932 * is detected. Note further, this adjustment is only done once,
11933 * as we reset last_host_tsc on all VCPUs to stop this from being
11934 * called multiple times (one for each physical CPU bringup).
11936 * Platforms with unreliable TSCs don't have to deal with this, they
11937 * will be compensated by the logic in vcpu_load, which sets the TSC to
11938 * catchup mode. This will catchup all VCPUs to real time, but cannot
11939 * guarantee that they stay in perfect synchronization.
11941 if (backwards_tsc) {
11942 u64 delta_cyc = max_tsc - local_tsc;
11943 list_for_each_entry(kvm, &vm_list, vm_list) {
11944 kvm->arch.backwards_tsc_observed = true;
11945 kvm_for_each_vcpu(i, vcpu, kvm) {
11946 vcpu->arch.tsc_offset_adjustment += delta_cyc;
11947 vcpu->arch.last_host_tsc = local_tsc;
11948 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
11952 * We have to disable TSC offset matching.. if you were
11953 * booting a VM while issuing an S4 host suspend....
11954 * you may have some problem. Solving this issue is
11955 * left as an exercise to the reader.
11957 kvm->arch.last_tsc_nsec = 0;
11958 kvm->arch.last_tsc_write = 0;
11965 void kvm_arch_hardware_disable(void)
11967 static_call(kvm_x86_hardware_disable)();
11968 drop_user_return_notifiers();
11971 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
11973 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
11975 #define __KVM_X86_OP(func) \
11976 static_call_update(kvm_x86_##func, kvm_x86_ops.func);
11977 #define KVM_X86_OP(func) \
11978 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func)
11979 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP
11980 #define KVM_X86_OP_OPTIONAL_RET0(func) \
11981 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \
11982 (void *)__static_call_return0);
11983 #include <asm/kvm-x86-ops.h>
11984 #undef __KVM_X86_OP
11986 kvm_pmu_ops_update(ops->pmu_ops);
11989 int kvm_arch_hardware_setup(void *opaque)
11991 struct kvm_x86_init_ops *ops = opaque;
11994 rdmsrl_safe(MSR_EFER, &host_efer);
11996 if (boot_cpu_has(X86_FEATURE_XSAVES))
11997 rdmsrl(MSR_IA32_XSS, host_xss);
11999 kvm_init_pmu_capability();
12001 r = ops->hardware_setup();
12005 kvm_ops_update(ops);
12007 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
12009 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
12010 kvm_caps.supported_xss = 0;
12012 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
12013 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
12014 #undef __kvm_cpu_cap_has
12016 if (kvm_caps.has_tsc_control) {
12018 * Make sure the user can only configure tsc_khz values that
12019 * fit into a signed integer.
12020 * A min value is not calculated because it will always
12021 * be 1 on all machines.
12023 u64 max = min(0x7fffffffULL,
12024 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
12025 kvm_caps.max_guest_tsc_khz = max;
12027 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
12028 kvm_init_msr_list();
12032 void kvm_arch_hardware_unsetup(void)
12034 kvm_unregister_perf_callbacks();
12036 static_call(kvm_x86_hardware_unsetup)();
12039 int kvm_arch_check_processor_compat(void *opaque)
12041 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
12042 struct kvm_x86_init_ops *ops = opaque;
12044 WARN_ON(!irqs_disabled());
12046 if (__cr4_reserved_bits(cpu_has, c) !=
12047 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
12050 return ops->check_processor_compatibility();
12053 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
12055 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
12058 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
12060 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
12063 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
12064 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
12066 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
12068 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
12070 vcpu->arch.l1tf_flush_l1d = true;
12071 if (pmu->version && unlikely(pmu->event_count)) {
12072 pmu->need_cleanup = true;
12073 kvm_make_request(KVM_REQ_PMU, vcpu);
12075 static_call(kvm_x86_sched_in)(vcpu, cpu);
12078 void kvm_arch_free_vm(struct kvm *kvm)
12080 kfree(to_kvm_hv(kvm)->hv_pa_pg);
12081 __kvm_arch_free_vm(kvm);
12085 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
12088 unsigned long flags;
12093 ret = kvm_page_track_init(kvm);
12097 ret = kvm_mmu_init_vm(kvm);
12099 goto out_page_track;
12101 ret = static_call(kvm_x86_vm_init)(kvm);
12103 goto out_uninit_mmu;
12105 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
12106 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
12107 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
12109 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
12110 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
12111 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
12112 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
12113 &kvm->arch.irq_sources_bitmap);
12115 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
12116 mutex_init(&kvm->arch.apic_map_lock);
12117 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
12118 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
12120 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
12121 pvclock_update_vm_gtod_copy(kvm);
12122 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
12124 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
12125 kvm->arch.guest_can_read_msr_platform_info = true;
12126 kvm->arch.enable_pmu = enable_pmu;
12128 #if IS_ENABLED(CONFIG_HYPERV)
12129 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
12130 kvm->arch.hv_root_tdp = INVALID_PAGE;
12133 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
12134 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
12136 kvm_apicv_init(kvm);
12137 kvm_hv_init_vm(kvm);
12138 kvm_xen_init_vm(kvm);
12143 kvm_mmu_uninit_vm(kvm);
12145 kvm_page_track_cleanup(kvm);
12150 int kvm_arch_post_init_vm(struct kvm *kvm)
12152 return kvm_mmu_post_init_vm(kvm);
12155 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
12158 kvm_mmu_unload(vcpu);
12162 static void kvm_unload_vcpu_mmus(struct kvm *kvm)
12165 struct kvm_vcpu *vcpu;
12167 kvm_for_each_vcpu(i, vcpu, kvm) {
12168 kvm_clear_async_pf_completion_queue(vcpu);
12169 kvm_unload_vcpu_mmu(vcpu);
12173 void kvm_arch_sync_events(struct kvm *kvm)
12175 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
12176 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
12181 * __x86_set_memory_region: Setup KVM internal memory slot
12183 * @kvm: the kvm pointer to the VM.
12184 * @id: the slot ID to setup.
12185 * @gpa: the GPA to install the slot (unused when @size == 0).
12186 * @size: the size of the slot. Set to zero to uninstall a slot.
12188 * This function helps to setup a KVM internal memory slot. Specify
12189 * @size > 0 to install a new slot, while @size == 0 to uninstall a
12190 * slot. The return code can be one of the following:
12192 * HVA: on success (uninstall will return a bogus HVA)
12195 * The caller should always use IS_ERR() to check the return value
12196 * before use. Note, the KVM internal memory slots are guaranteed to
12197 * remain valid and unchanged until the VM is destroyed, i.e., the
12198 * GPA->HVA translation will not change. However, the HVA is a user
12199 * address, i.e. its accessibility is not guaranteed, and must be
12200 * accessed via __copy_{to,from}_user().
12202 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
12206 unsigned long hva, old_npages;
12207 struct kvm_memslots *slots = kvm_memslots(kvm);
12208 struct kvm_memory_slot *slot;
12210 /* Called with kvm->slots_lock held. */
12211 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
12212 return ERR_PTR_USR(-EINVAL);
12214 slot = id_to_memslot(slots, id);
12216 if (slot && slot->npages)
12217 return ERR_PTR_USR(-EEXIST);
12220 * MAP_SHARED to prevent internal slot pages from being moved
12223 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
12224 MAP_SHARED | MAP_ANONYMOUS, 0);
12225 if (IS_ERR((void *)hva))
12226 return (void __user *)hva;
12228 if (!slot || !slot->npages)
12231 old_npages = slot->npages;
12232 hva = slot->userspace_addr;
12235 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
12236 struct kvm_userspace_memory_region m;
12238 m.slot = id | (i << 16);
12240 m.guest_phys_addr = gpa;
12241 m.userspace_addr = hva;
12242 m.memory_size = size;
12243 r = __kvm_set_memory_region(kvm, &m);
12245 return ERR_PTR_USR(r);
12249 vm_munmap(hva, old_npages * PAGE_SIZE);
12251 return (void __user *)hva;
12253 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
12255 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
12257 kvm_mmu_pre_destroy_vm(kvm);
12260 void kvm_arch_destroy_vm(struct kvm *kvm)
12262 if (current->mm == kvm->mm) {
12264 * Free memory regions allocated on behalf of userspace,
12265 * unless the memory map has changed due to process exit
12268 mutex_lock(&kvm->slots_lock);
12269 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
12271 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
12273 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
12274 mutex_unlock(&kvm->slots_lock);
12276 kvm_unload_vcpu_mmus(kvm);
12277 static_call_cond(kvm_x86_vm_destroy)(kvm);
12278 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
12279 kvm_pic_destroy(kvm);
12280 kvm_ioapic_destroy(kvm);
12281 kvm_destroy_vcpus(kvm);
12282 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
12283 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
12284 kvm_mmu_uninit_vm(kvm);
12285 kvm_page_track_cleanup(kvm);
12286 kvm_xen_destroy_vm(kvm);
12287 kvm_hv_destroy_vm(kvm);
12290 static void memslot_rmap_free(struct kvm_memory_slot *slot)
12294 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12295 kvfree(slot->arch.rmap[i]);
12296 slot->arch.rmap[i] = NULL;
12300 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
12304 memslot_rmap_free(slot);
12306 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12307 kvfree(slot->arch.lpage_info[i - 1]);
12308 slot->arch.lpage_info[i - 1] = NULL;
12311 kvm_page_track_free_memslot(slot);
12314 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
12316 const int sz = sizeof(*slot->arch.rmap[0]);
12319 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12321 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12323 if (slot->arch.rmap[i])
12326 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
12327 if (!slot->arch.rmap[i]) {
12328 memslot_rmap_free(slot);
12336 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
12337 struct kvm_memory_slot *slot)
12339 unsigned long npages = slot->npages;
12343 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
12344 * old arrays will be freed by __kvm_set_memory_region() if installing
12345 * the new memslot is successful.
12347 memset(&slot->arch, 0, sizeof(slot->arch));
12349 if (kvm_memslots_have_rmaps(kvm)) {
12350 r = memslot_rmap_alloc(slot, npages);
12355 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12356 struct kvm_lpage_info *linfo;
12357 unsigned long ugfn;
12361 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12363 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
12367 slot->arch.lpage_info[i - 1] = linfo;
12369 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12370 linfo[0].disallow_lpage = 1;
12371 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12372 linfo[lpages - 1].disallow_lpage = 1;
12373 ugfn = slot->userspace_addr >> PAGE_SHIFT;
12375 * If the gfn and userspace address are not aligned wrt each
12376 * other, disable large page support for this slot.
12378 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12381 for (j = 0; j < lpages; ++j)
12382 linfo[j].disallow_lpage = 1;
12386 if (kvm_page_track_create_memslot(kvm, slot, npages))
12392 memslot_rmap_free(slot);
12394 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12395 kvfree(slot->arch.lpage_info[i - 1]);
12396 slot->arch.lpage_info[i - 1] = NULL;
12401 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12403 struct kvm_vcpu *vcpu;
12407 * memslots->generation has been incremented.
12408 * mmio generation may have reached its maximum value.
12410 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12412 /* Force re-initialization of steal_time cache */
12413 kvm_for_each_vcpu(i, vcpu, kvm)
12414 kvm_vcpu_kick(vcpu);
12417 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12418 const struct kvm_memory_slot *old,
12419 struct kvm_memory_slot *new,
12420 enum kvm_mr_change change)
12422 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
12423 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
12426 return kvm_alloc_memslot_metadata(kvm, new);
12429 if (change == KVM_MR_FLAGS_ONLY)
12430 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12431 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12438 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12440 struct kvm_arch *ka = &kvm->arch;
12442 if (!kvm_x86_ops.cpu_dirty_log_size)
12445 if ((enable && ++ka->cpu_dirty_logging_count == 1) ||
12446 (!enable && --ka->cpu_dirty_logging_count == 0))
12447 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12449 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0);
12452 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12453 struct kvm_memory_slot *old,
12454 const struct kvm_memory_slot *new,
12455 enum kvm_mr_change change)
12457 u32 old_flags = old ? old->flags : 0;
12458 u32 new_flags = new ? new->flags : 0;
12459 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12462 * Update CPU dirty logging if dirty logging is being toggled. This
12463 * applies to all operations.
12465 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12466 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12469 * Nothing more to do for RO slots (which can't be dirtied and can't be
12470 * made writable) or CREATE/MOVE/DELETE of a slot.
12472 * For a memslot with dirty logging disabled:
12473 * CREATE: No dirty mappings will already exist.
12474 * MOVE/DELETE: The old mappings will already have been cleaned up by
12475 * kvm_arch_flush_shadow_memslot()
12477 * For a memslot with dirty logging enabled:
12478 * CREATE: No shadow pages exist, thus nothing to write-protect
12479 * and no dirty bits to clear.
12480 * MOVE/DELETE: The old mappings will already have been cleaned up by
12481 * kvm_arch_flush_shadow_memslot().
12483 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12487 * READONLY and non-flags changes were filtered out above, and the only
12488 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12489 * logging isn't being toggled on or off.
12491 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12494 if (!log_dirty_pages) {
12496 * Dirty logging tracks sptes in 4k granularity, meaning that
12497 * large sptes have to be split. If live migration succeeds,
12498 * the guest in the source machine will be destroyed and large
12499 * sptes will be created in the destination. However, if the
12500 * guest continues to run in the source machine (for example if
12501 * live migration fails), small sptes will remain around and
12502 * cause bad performance.
12504 * Scan sptes if dirty logging has been stopped, dropping those
12505 * which can be collapsed into a single large-page spte. Later
12506 * page faults will create the large-page sptes.
12508 kvm_mmu_zap_collapsible_sptes(kvm, new);
12511 * Initially-all-set does not require write protecting any page,
12512 * because they're all assumed to be dirty.
12514 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12517 if (READ_ONCE(eager_page_split))
12518 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12520 if (kvm_x86_ops.cpu_dirty_log_size) {
12521 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12522 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12524 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12528 * Unconditionally flush the TLBs after enabling dirty logging.
12529 * A flush is almost always going to be necessary (see below),
12530 * and unconditionally flushing allows the helpers to omit
12531 * the subtly complex checks when removing write access.
12533 * Do the flush outside of mmu_lock to reduce the amount of
12534 * time mmu_lock is held. Flushing after dropping mmu_lock is
12535 * safe as KVM only needs to guarantee the slot is fully
12536 * write-protected before returning to userspace, i.e. before
12537 * userspace can consume the dirty status.
12539 * Flushing outside of mmu_lock requires KVM to be careful when
12540 * making decisions based on writable status of an SPTE, e.g. a
12541 * !writable SPTE doesn't guarantee a CPU can't perform writes.
12543 * Specifically, KVM also write-protects guest page tables to
12544 * monitor changes when using shadow paging, and must guarantee
12545 * no CPUs can write to those page before mmu_lock is dropped.
12546 * Because CPUs may have stale TLB entries at this point, a
12547 * !writable SPTE doesn't guarantee CPUs can't perform writes.
12549 * KVM also allows making SPTES writable outside of mmu_lock,
12550 * e.g. to allow dirty logging without taking mmu_lock.
12552 * To handle these scenarios, KVM uses a separate software-only
12553 * bit (MMU-writable) to track if a SPTE is !writable due to
12554 * a guest page table being write-protected (KVM clears the
12555 * MMU-writable flag when write-protecting for shadow paging).
12557 * The use of MMU-writable is also the primary motivation for
12558 * the unconditional flush. Because KVM must guarantee that a
12559 * CPU doesn't contain stale, writable TLB entries for a
12560 * !MMU-writable SPTE, KVM must flush if it encounters any
12561 * MMU-writable SPTE regardless of whether the actual hardware
12562 * writable bit was set. I.e. KVM is almost guaranteed to need
12563 * to flush, while unconditionally flushing allows the "remove
12564 * write access" helpers to ignore MMU-writable entirely.
12566 * See is_writable_pte() for more details (the case involving
12567 * access-tracked SPTEs is particularly relevant).
12569 kvm_arch_flush_remote_tlbs_memslot(kvm, new);
12573 void kvm_arch_commit_memory_region(struct kvm *kvm,
12574 struct kvm_memory_slot *old,
12575 const struct kvm_memory_slot *new,
12576 enum kvm_mr_change change)
12578 if (!kvm->arch.n_requested_mmu_pages &&
12579 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12580 unsigned long nr_mmu_pages;
12582 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12583 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12584 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12587 kvm_mmu_slot_apply_flags(kvm, old, new, change);
12589 /* Free the arrays associated with the old memslot. */
12590 if (change == KVM_MR_MOVE)
12591 kvm_arch_free_memslot(kvm, old);
12594 void kvm_arch_flush_shadow_all(struct kvm *kvm)
12596 kvm_mmu_zap_all(kvm);
12599 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
12600 struct kvm_memory_slot *slot)
12602 kvm_page_track_flush_slot(kvm, slot);
12605 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12607 return (is_guest_mode(vcpu) &&
12608 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12611 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12613 if (!list_empty_careful(&vcpu->async_pf.done))
12616 if (kvm_apic_has_pending_init_or_sipi(vcpu) &&
12617 kvm_apic_init_sipi_allowed(vcpu))
12620 if (vcpu->arch.pv.pv_unhalted)
12623 if (kvm_is_exception_pending(vcpu))
12626 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12627 (vcpu->arch.nmi_pending &&
12628 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12631 #ifdef CONFIG_KVM_SMM
12632 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12633 (vcpu->arch.smi_pending &&
12634 static_call(kvm_x86_smi_allowed)(vcpu, false)))
12638 if (kvm_arch_interrupt_allowed(vcpu) &&
12639 (kvm_cpu_has_interrupt(vcpu) ||
12640 kvm_guest_apic_has_interrupt(vcpu)))
12643 if (kvm_hv_has_stimer_pending(vcpu))
12646 if (is_guest_mode(vcpu) &&
12647 kvm_x86_ops.nested_ops->has_events &&
12648 kvm_x86_ops.nested_ops->has_events(vcpu))
12651 if (kvm_xen_has_pending_events(vcpu))
12657 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12659 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12662 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12664 if (kvm_vcpu_apicv_active(vcpu) &&
12665 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12671 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12673 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12676 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12677 #ifdef CONFIG_KVM_SMM
12678 kvm_test_request(KVM_REQ_SMI, vcpu) ||
12680 kvm_test_request(KVM_REQ_EVENT, vcpu))
12683 return kvm_arch_dy_has_pending_interrupt(vcpu);
12686 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
12688 if (vcpu->arch.guest_state_protected)
12691 return vcpu->arch.preempted_in_kernel;
12694 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
12696 return kvm_rip_read(vcpu);
12699 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
12701 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
12704 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
12706 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
12709 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
12711 /* Can't read the RIP when guest state is protected, just return 0 */
12712 if (vcpu->arch.guest_state_protected)
12715 if (is_64_bit_mode(vcpu))
12716 return kvm_rip_read(vcpu);
12717 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
12718 kvm_rip_read(vcpu));
12720 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
12722 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
12724 return kvm_get_linear_rip(vcpu) == linear_rip;
12726 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
12728 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
12730 unsigned long rflags;
12732 rflags = static_call(kvm_x86_get_rflags)(vcpu);
12733 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12734 rflags &= ~X86_EFLAGS_TF;
12737 EXPORT_SYMBOL_GPL(kvm_get_rflags);
12739 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12741 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
12742 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
12743 rflags |= X86_EFLAGS_TF;
12744 static_call(kvm_x86_set_rflags)(vcpu, rflags);
12747 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12749 __kvm_set_rflags(vcpu, rflags);
12750 kvm_make_request(KVM_REQ_EVENT, vcpu);
12752 EXPORT_SYMBOL_GPL(kvm_set_rflags);
12754 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
12756 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
12758 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
12761 static inline u32 kvm_async_pf_next_probe(u32 key)
12763 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
12766 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12768 u32 key = kvm_async_pf_hash_fn(gfn);
12770 while (vcpu->arch.apf.gfns[key] != ~0)
12771 key = kvm_async_pf_next_probe(key);
12773 vcpu->arch.apf.gfns[key] = gfn;
12776 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
12779 u32 key = kvm_async_pf_hash_fn(gfn);
12781 for (i = 0; i < ASYNC_PF_PER_VCPU &&
12782 (vcpu->arch.apf.gfns[key] != gfn &&
12783 vcpu->arch.apf.gfns[key] != ~0); i++)
12784 key = kvm_async_pf_next_probe(key);
12789 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12791 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
12794 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12798 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
12800 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
12804 vcpu->arch.apf.gfns[i] = ~0;
12806 j = kvm_async_pf_next_probe(j);
12807 if (vcpu->arch.apf.gfns[j] == ~0)
12809 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
12811 * k lies cyclically in ]i,j]
12813 * |....j i.k.| or |.k..j i...|
12815 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
12816 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
12821 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
12823 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
12825 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
12829 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
12831 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12833 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12834 &token, offset, sizeof(token));
12837 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
12839 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12842 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12843 &val, offset, sizeof(val)))
12849 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
12852 if (!kvm_pv_async_pf_enabled(vcpu))
12855 if (vcpu->arch.apf.send_user_only &&
12856 static_call(kvm_x86_get_cpl)(vcpu) == 0)
12859 if (is_guest_mode(vcpu)) {
12861 * L1 needs to opt into the special #PF vmexits that are
12862 * used to deliver async page faults.
12864 return vcpu->arch.apf.delivery_as_pf_vmexit;
12867 * Play it safe in case the guest temporarily disables paging.
12868 * The real mode IDT in particular is unlikely to have a #PF
12871 return is_paging(vcpu);
12875 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
12877 if (unlikely(!lapic_in_kernel(vcpu) ||
12878 kvm_event_needs_reinjection(vcpu) ||
12879 kvm_is_exception_pending(vcpu)))
12882 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
12886 * If interrupts are off we cannot even use an artificial
12889 return kvm_arch_interrupt_allowed(vcpu);
12892 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
12893 struct kvm_async_pf *work)
12895 struct x86_exception fault;
12897 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
12898 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
12900 if (kvm_can_deliver_async_pf(vcpu) &&
12901 !apf_put_user_notpresent(vcpu)) {
12902 fault.vector = PF_VECTOR;
12903 fault.error_code_valid = true;
12904 fault.error_code = 0;
12905 fault.nested_page_fault = false;
12906 fault.address = work->arch.token;
12907 fault.async_page_fault = true;
12908 kvm_inject_page_fault(vcpu, &fault);
12912 * It is not possible to deliver a paravirtualized asynchronous
12913 * page fault, but putting the guest in an artificial halt state
12914 * can be beneficial nevertheless: if an interrupt arrives, we
12915 * can deliver it timely and perhaps the guest will schedule
12916 * another process. When the instruction that triggered a page
12917 * fault is retried, hopefully the page will be ready in the host.
12919 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
12924 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
12925 struct kvm_async_pf *work)
12927 struct kvm_lapic_irq irq = {
12928 .delivery_mode = APIC_DM_FIXED,
12929 .vector = vcpu->arch.apf.vec
12932 if (work->wakeup_all)
12933 work->arch.token = ~0; /* broadcast wakeup */
12935 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
12936 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
12938 if ((work->wakeup_all || work->notpresent_injected) &&
12939 kvm_pv_async_pf_enabled(vcpu) &&
12940 !apf_put_user_ready(vcpu, work->arch.token)) {
12941 vcpu->arch.apf.pageready_pending = true;
12942 kvm_apic_set_irq(vcpu, &irq, NULL);
12945 vcpu->arch.apf.halted = false;
12946 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12949 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
12951 kvm_make_request(KVM_REQ_APF_READY, vcpu);
12952 if (!vcpu->arch.apf.pageready_pending)
12953 kvm_vcpu_kick(vcpu);
12956 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
12958 if (!kvm_pv_async_pf_enabled(vcpu))
12961 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
12964 void kvm_arch_start_assignment(struct kvm *kvm)
12966 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
12967 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
12969 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
12971 void kvm_arch_end_assignment(struct kvm *kvm)
12973 atomic_dec(&kvm->arch.assigned_device_count);
12975 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
12977 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm)
12979 return arch_atomic_read(&kvm->arch.assigned_device_count);
12981 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
12983 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
12985 atomic_inc(&kvm->arch.noncoherent_dma_count);
12987 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
12989 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
12991 atomic_dec(&kvm->arch.noncoherent_dma_count);
12993 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
12995 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
12997 return atomic_read(&kvm->arch.noncoherent_dma_count);
12999 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
13001 bool kvm_arch_has_irq_bypass(void)
13006 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
13007 struct irq_bypass_producer *prod)
13009 struct kvm_kernel_irqfd *irqfd =
13010 container_of(cons, struct kvm_kernel_irqfd, consumer);
13013 irqfd->producer = prod;
13014 kvm_arch_start_assignment(irqfd->kvm);
13015 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
13016 prod->irq, irqfd->gsi, 1);
13019 kvm_arch_end_assignment(irqfd->kvm);
13024 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
13025 struct irq_bypass_producer *prod)
13028 struct kvm_kernel_irqfd *irqfd =
13029 container_of(cons, struct kvm_kernel_irqfd, consumer);
13031 WARN_ON(irqfd->producer != prod);
13032 irqfd->producer = NULL;
13035 * When producer of consumer is unregistered, we change back to
13036 * remapped mode, so we can re-use the current implementation
13037 * when the irq is masked/disabled or the consumer side (KVM
13038 * int this case doesn't want to receive the interrupts.
13040 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
13042 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
13043 " fails: %d\n", irqfd->consumer.token, ret);
13045 kvm_arch_end_assignment(irqfd->kvm);
13048 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
13049 uint32_t guest_irq, bool set)
13051 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
13054 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
13055 struct kvm_kernel_irq_routing_entry *new)
13057 if (new->type != KVM_IRQ_ROUTING_MSI)
13060 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
13063 bool kvm_vector_hashing_enabled(void)
13065 return vector_hashing;
13068 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
13070 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
13072 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
13075 int kvm_spec_ctrl_test_value(u64 value)
13078 * test that setting IA32_SPEC_CTRL to given value
13079 * is allowed by the host processor
13083 unsigned long flags;
13086 local_irq_save(flags);
13088 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
13090 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
13093 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
13095 local_irq_restore(flags);
13099 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
13101 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
13103 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
13104 struct x86_exception fault;
13105 u64 access = error_code &
13106 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
13108 if (!(error_code & PFERR_PRESENT_MASK) ||
13109 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) {
13111 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
13112 * tables probably do not match the TLB. Just proceed
13113 * with the error code that the processor gave.
13115 fault.vector = PF_VECTOR;
13116 fault.error_code_valid = true;
13117 fault.error_code = error_code;
13118 fault.nested_page_fault = false;
13119 fault.address = gva;
13120 fault.async_page_fault = false;
13122 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
13124 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
13127 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
13128 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
13129 * indicates whether exit to userspace is needed.
13131 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
13132 struct x86_exception *e)
13134 if (r == X86EMUL_PROPAGATE_FAULT) {
13135 if (KVM_BUG_ON(!e, vcpu->kvm))
13138 kvm_inject_emulated_page_fault(vcpu, e);
13143 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
13144 * while handling a VMX instruction KVM could've handled the request
13145 * correctly by exiting to userspace and performing I/O but there
13146 * doesn't seem to be a real use-case behind such requests, just return
13147 * KVM_EXIT_INTERNAL_ERROR for now.
13149 kvm_prepare_emulation_failure_exit(vcpu);
13153 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
13155 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
13158 struct x86_exception e;
13165 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
13166 if (r != X86EMUL_CONTINUE)
13167 return kvm_handle_memory_failure(vcpu, r, &e);
13169 if (operand.pcid >> 12 != 0) {
13170 kvm_inject_gp(vcpu, 0);
13174 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
13177 case INVPCID_TYPE_INDIV_ADDR:
13178 if ((!pcid_enabled && (operand.pcid != 0)) ||
13179 is_noncanonical_address(operand.gla, vcpu)) {
13180 kvm_inject_gp(vcpu, 0);
13183 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
13184 return kvm_skip_emulated_instruction(vcpu);
13186 case INVPCID_TYPE_SINGLE_CTXT:
13187 if (!pcid_enabled && (operand.pcid != 0)) {
13188 kvm_inject_gp(vcpu, 0);
13192 kvm_invalidate_pcid(vcpu, operand.pcid);
13193 return kvm_skip_emulated_instruction(vcpu);
13195 case INVPCID_TYPE_ALL_NON_GLOBAL:
13197 * Currently, KVM doesn't mark global entries in the shadow
13198 * page tables, so a non-global flush just degenerates to a
13199 * global flush. If needed, we could optimize this later by
13200 * keeping track of global entries in shadow page tables.
13204 case INVPCID_TYPE_ALL_INCL_GLOBAL:
13205 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
13206 return kvm_skip_emulated_instruction(vcpu);
13209 kvm_inject_gp(vcpu, 0);
13213 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
13215 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
13217 struct kvm_run *run = vcpu->run;
13218 struct kvm_mmio_fragment *frag;
13221 BUG_ON(!vcpu->mmio_needed);
13223 /* Complete previous fragment */
13224 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
13225 len = min(8u, frag->len);
13226 if (!vcpu->mmio_is_write)
13227 memcpy(frag->data, run->mmio.data, len);
13229 if (frag->len <= 8) {
13230 /* Switch to the next fragment. */
13232 vcpu->mmio_cur_fragment++;
13234 /* Go forward to the next mmio piece. */
13240 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
13241 vcpu->mmio_needed = 0;
13243 // VMG change, at this point, we're always done
13244 // RIP has already been advanced
13248 // More MMIO is needed
13249 run->mmio.phys_addr = frag->gpa;
13250 run->mmio.len = min(8u, frag->len);
13251 run->mmio.is_write = vcpu->mmio_is_write;
13252 if (run->mmio.is_write)
13253 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
13254 run->exit_reason = KVM_EXIT_MMIO;
13256 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13261 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13265 struct kvm_mmio_fragment *frag;
13270 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13271 if (handled == bytes)
13278 /*TODO: Check if need to increment number of frags */
13279 frag = vcpu->mmio_fragments;
13280 vcpu->mmio_nr_fragments = 1;
13285 vcpu->mmio_needed = 1;
13286 vcpu->mmio_cur_fragment = 0;
13288 vcpu->run->mmio.phys_addr = gpa;
13289 vcpu->run->mmio.len = min(8u, frag->len);
13290 vcpu->run->mmio.is_write = 1;
13291 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
13292 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13294 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13298 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
13300 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13304 struct kvm_mmio_fragment *frag;
13309 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13310 if (handled == bytes)
13317 /*TODO: Check if need to increment number of frags */
13318 frag = vcpu->mmio_fragments;
13319 vcpu->mmio_nr_fragments = 1;
13324 vcpu->mmio_needed = 1;
13325 vcpu->mmio_cur_fragment = 0;
13327 vcpu->run->mmio.phys_addr = gpa;
13328 vcpu->run->mmio.len = min(8u, frag->len);
13329 vcpu->run->mmio.is_write = 0;
13330 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13332 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13336 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
13338 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size)
13340 vcpu->arch.sev_pio_count -= count;
13341 vcpu->arch.sev_pio_data += count * size;
13344 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13345 unsigned int port);
13347 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
13349 int size = vcpu->arch.pio.size;
13350 int port = vcpu->arch.pio.port;
13352 vcpu->arch.pio.count = 0;
13353 if (vcpu->arch.sev_pio_count)
13354 return kvm_sev_es_outs(vcpu, size, port);
13358 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13362 unsigned int count =
13363 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13364 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
13366 /* memcpy done already by emulator_pio_out. */
13367 advance_sev_es_emulated_pio(vcpu, count, size);
13371 /* Emulation done by the kernel. */
13372 if (!vcpu->arch.sev_pio_count)
13376 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
13380 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13381 unsigned int port);
13383 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
13385 unsigned count = vcpu->arch.pio.count;
13386 int size = vcpu->arch.pio.size;
13387 int port = vcpu->arch.pio.port;
13389 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
13390 advance_sev_es_emulated_pio(vcpu, count, size);
13391 if (vcpu->arch.sev_pio_count)
13392 return kvm_sev_es_ins(vcpu, size, port);
13396 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13400 unsigned int count =
13401 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13402 if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count))
13405 /* Emulation done by the kernel. */
13406 advance_sev_es_emulated_pio(vcpu, count, size);
13407 if (!vcpu->arch.sev_pio_count)
13411 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13415 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13416 unsigned int port, void *data, unsigned int count,
13419 vcpu->arch.sev_pio_data = data;
13420 vcpu->arch.sev_pio_count = count;
13421 return in ? kvm_sev_es_ins(vcpu, size, port)
13422 : kvm_sev_es_outs(vcpu, size, port);
13424 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13426 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13427 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13428 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13429 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13430 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13431 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13432 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13433 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter);
13434 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13435 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13436 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13437 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13438 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13439 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13440 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13441 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13442 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13443 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13444 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13445 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13446 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13447 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13448 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath);
13449 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell);
13450 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13451 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13452 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13453 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13454 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13456 static int __init kvm_x86_init(void)
13458 kvm_mmu_x86_module_init();
13461 module_init(kvm_x86_init);
13463 static void __exit kvm_x86_exit(void)
13466 * If module_init() is implemented, module_exit() must also be
13467 * implemented to allow module unload.
13470 module_exit(kvm_x86_exit);