1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
30 #include <linux/clocksource.h>
31 #include <linux/interrupt.h>
32 #include <linux/kvm.h>
34 #include <linux/vmalloc.h>
35 #include <linux/export.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <linux/kvm_irqfd.h>
52 #include <linux/irqbypass.h>
53 #include <linux/sched/stat.h>
54 #include <linux/sched/isolation.h>
55 #include <linux/mem_encrypt.h>
57 #include <trace/events/kvm.h>
59 #include <asm/debugreg.h>
63 #include <linux/kernel_stat.h>
64 #include <asm/fpu/internal.h> /* Ugh! */
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67 #include <asm/irq_remapping.h>
68 #include <asm/mshyperv.h>
69 #include <asm/hypervisor.h>
70 #include <asm/intel_pt.h>
71 #include <clocksource/hyperv_timer.h>
73 #define CREATE_TRACE_POINTS
76 #define MAX_IO_MSRS 256
77 #define KVM_MAX_MCE_BANKS 32
78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
81 #define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
95 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
101 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
102 static void process_nmi(struct kvm_vcpu *vcpu);
103 static void enter_smm(struct kvm_vcpu *vcpu);
104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
105 static void store_regs(struct kvm_vcpu *vcpu);
106 static int sync_regs(struct kvm_vcpu *vcpu);
108 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
109 EXPORT_SYMBOL_GPL(kvm_x86_ops);
111 static bool __read_mostly ignore_msrs = 0;
112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
114 static bool __read_mostly report_ignored_msrs = true;
115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117 unsigned int min_timer_period_us = 200;
118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120 static bool __read_mostly kvmclock_periodic_sync = true;
121 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123 bool __read_mostly kvm_has_tsc_control;
124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
125 u32 __read_mostly kvm_max_guest_tsc_khz;
126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
127 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129 u64 __read_mostly kvm_max_tsc_scaling_ratio;
130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
131 u64 __read_mostly kvm_default_tsc_scaling_ratio;
132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
135 static u32 __read_mostly tsc_tolerance_ppm = 250;
136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
144 static int __read_mostly lapic_timer_advance_ns = -1;
145 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
147 static bool __read_mostly vector_hashing = true;
148 module_param(vector_hashing, bool, S_IRUGO);
150 bool __read_mostly enable_vmware_backdoor = false;
151 module_param(enable_vmware_backdoor, bool, S_IRUGO);
152 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
154 static bool __read_mostly force_emulation_prefix = false;
155 module_param(force_emulation_prefix, bool, S_IRUGO);
157 int __read_mostly pi_inject_timer = -1;
158 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
160 #define KVM_NR_SHARED_MSRS 16
162 struct kvm_shared_msrs_global {
164 u32 msrs[KVM_NR_SHARED_MSRS];
167 struct kvm_shared_msrs {
168 struct user_return_notifier urn;
170 struct kvm_shared_msr_values {
173 } values[KVM_NR_SHARED_MSRS];
176 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
177 static struct kvm_shared_msrs __percpu *shared_msrs;
179 struct kvm_stats_debugfs_item debugfs_entries[] = {
180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
190 { "halt_exits", VCPU_STAT(halt_exits) },
191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
195 { "hypercalls", VCPU_STAT(hypercalls) },
196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
202 { "irq_injections", VCPU_STAT(irq_injections) },
203 { "nmi_injections", VCPU_STAT(nmi_injections) },
204 { "req_event", VCPU_STAT(req_event) },
205 { "l1d_flush", VCPU_STAT(l1d_flush) },
206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
213 { "mmu_unsync", VM_STAT(mmu_unsync) },
214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
215 { "largepages", VM_STAT(lpages) },
216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
221 u64 __read_mostly host_xcr0;
223 struct kmem_cache *x86_fpu_cache;
224 EXPORT_SYMBOL_GPL(x86_fpu_cache);
226 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
228 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
235 static void kvm_on_user_return(struct user_return_notifier *urn)
238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
240 struct kvm_shared_msr_values *values;
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
252 local_irq_restore(flags);
253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
262 static void shared_msr_update(unsigned slot, u32 msr)
265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
279 void kvm_define_shared_msr(unsigned slot, u32 msr)
281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
282 shared_msrs_global.msrs[slot] = msr;
283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
286 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
288 static void kvm_shared_msr_cpu_online(void)
292 for (i = 0; i < shared_msrs_global.nr; ++i)
293 shared_msr_update(i, shared_msrs_global.msrs[i]);
296 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
304 smsr->values[slot].curr = value;
305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
316 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
318 static void drop_user_return_notifiers(void)
320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
327 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
329 return vcpu->arch.apic_base;
331 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
333 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
337 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
339 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
355 kvm_lapic_set_base(vcpu, msr_info->data);
358 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
360 asmlinkage __visible void kvm_spurious_fault(void)
362 /* Fault while not rebooting. We want the trace. */
365 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
367 #define EXCPT_BENIGN 0
368 #define EXCPT_CONTRIBUTORY 1
371 static int exception_class(int vector)
381 return EXCPT_CONTRIBUTORY;
388 #define EXCPT_FAULT 0
390 #define EXCPT_ABORT 2
391 #define EXCPT_INTERRUPT 3
393 static int exception_type(int vector)
397 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
398 return EXCPT_INTERRUPT;
402 /* #DB is trap, as instruction watchpoints are handled elsewhere */
403 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
406 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
409 /* Reserved exceptions will result in fault */
413 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
415 unsigned nr = vcpu->arch.exception.nr;
416 bool has_payload = vcpu->arch.exception.has_payload;
417 unsigned long payload = vcpu->arch.exception.payload;
425 * "Certain debug exceptions may clear bit 0-3. The
426 * remaining contents of the DR6 register are never
427 * cleared by the processor".
429 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
431 * DR6.RTM is set by all #DB exceptions that don't clear it.
433 vcpu->arch.dr6 |= DR6_RTM;
434 vcpu->arch.dr6 |= payload;
436 * Bit 16 should be set in the payload whenever the #DB
437 * exception should clear DR6.RTM. This makes the payload
438 * compatible with the pending debug exceptions under VMX.
439 * Though not currently documented in the SDM, this also
440 * makes the payload compatible with the exit qualification
441 * for #DB exceptions under VMX.
443 vcpu->arch.dr6 ^= payload & DR6_RTM;
446 vcpu->arch.cr2 = payload;
450 vcpu->arch.exception.has_payload = false;
451 vcpu->arch.exception.payload = 0;
453 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
455 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
456 unsigned nr, bool has_error, u32 error_code,
457 bool has_payload, unsigned long payload, bool reinject)
462 kvm_make_request(KVM_REQ_EVENT, vcpu);
464 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
466 if (has_error && !is_protmode(vcpu))
470 * On vmentry, vcpu->arch.exception.pending is only
471 * true if an event injection was blocked by
472 * nested_run_pending. In that case, however,
473 * vcpu_enter_guest requests an immediate exit,
474 * and the guest shouldn't proceed far enough to
477 WARN_ON_ONCE(vcpu->arch.exception.pending);
478 vcpu->arch.exception.injected = true;
479 if (WARN_ON_ONCE(has_payload)) {
481 * A reinjected event has already
482 * delivered its payload.
488 vcpu->arch.exception.pending = true;
489 vcpu->arch.exception.injected = false;
491 vcpu->arch.exception.has_error_code = has_error;
492 vcpu->arch.exception.nr = nr;
493 vcpu->arch.exception.error_code = error_code;
494 vcpu->arch.exception.has_payload = has_payload;
495 vcpu->arch.exception.payload = payload;
497 * In guest mode, payload delivery should be deferred,
498 * so that the L1 hypervisor can intercept #PF before
499 * CR2 is modified (or intercept #DB before DR6 is
500 * modified under nVMX). However, for ABI
501 * compatibility with KVM_GET_VCPU_EVENTS and
502 * KVM_SET_VCPU_EVENTS, we can't delay payload
503 * delivery unless userspace has enabled this
504 * functionality via the per-VM capability,
505 * KVM_CAP_EXCEPTION_PAYLOAD.
507 if (!vcpu->kvm->arch.exception_payload_enabled ||
508 !is_guest_mode(vcpu))
509 kvm_deliver_exception_payload(vcpu);
513 /* to check exception */
514 prev_nr = vcpu->arch.exception.nr;
515 if (prev_nr == DF_VECTOR) {
516 /* triple fault -> shutdown */
517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
520 class1 = exception_class(prev_nr);
521 class2 = exception_class(nr);
522 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
523 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
525 * Generate double fault per SDM Table 5-5. Set
526 * exception.pending = true so that the double fault
527 * can trigger a nested vmexit.
529 vcpu->arch.exception.pending = true;
530 vcpu->arch.exception.injected = false;
531 vcpu->arch.exception.has_error_code = true;
532 vcpu->arch.exception.nr = DF_VECTOR;
533 vcpu->arch.exception.error_code = 0;
534 vcpu->arch.exception.has_payload = false;
535 vcpu->arch.exception.payload = 0;
537 /* replace previous exception with a new one in a hope
538 that instruction re-execution will regenerate lost
543 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
547 EXPORT_SYMBOL_GPL(kvm_queue_exception);
549 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
551 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
553 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
555 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
556 unsigned long payload)
558 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
561 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
562 u32 error_code, unsigned long payload)
564 kvm_multiple_exception(vcpu, nr, true, error_code,
565 true, payload, false);
568 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
571 kvm_inject_gp(vcpu, 0);
573 return kvm_skip_emulated_instruction(vcpu);
577 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
579 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
581 ++vcpu->stat.pf_guest;
582 vcpu->arch.exception.nested_apf =
583 is_guest_mode(vcpu) && fault->async_page_fault;
584 if (vcpu->arch.exception.nested_apf) {
585 vcpu->arch.apf.nested_apf_token = fault->address;
586 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
588 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
592 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
594 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
596 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
597 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
599 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
601 return fault->nested_page_fault;
604 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
606 atomic_inc(&vcpu->arch.nmi_queued);
607 kvm_make_request(KVM_REQ_NMI, vcpu);
609 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
611 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
615 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
617 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
619 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
621 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
624 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
625 * a #GP and return false.
627 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
629 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
634 EXPORT_SYMBOL_GPL(kvm_require_cpl);
636 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
638 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
641 kvm_queue_exception(vcpu, UD_VECTOR);
644 EXPORT_SYMBOL_GPL(kvm_require_dr);
647 * This function will be used to read from the physical memory of the currently
648 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
649 * can read from guest physical or from the guest's guest physical memory.
651 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
652 gfn_t ngfn, void *data, int offset, int len,
655 struct x86_exception exception;
659 ngpa = gfn_to_gpa(ngfn);
660 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
661 if (real_gfn == UNMAPPED_GVA)
664 real_gfn = gpa_to_gfn(real_gfn);
666 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
668 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
670 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
671 void *data, int offset, int len, u32 access)
673 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
674 data, offset, len, access);
677 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
679 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
684 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
686 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
688 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
689 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
692 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
694 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
695 offset * sizeof(u64), sizeof(pdpte),
696 PFERR_USER_MASK|PFERR_WRITE_MASK);
701 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
702 if ((pdpte[i] & PT_PRESENT_MASK) &&
703 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
710 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
711 __set_bit(VCPU_EXREG_PDPTR,
712 (unsigned long *)&vcpu->arch.regs_avail);
713 __set_bit(VCPU_EXREG_PDPTR,
714 (unsigned long *)&vcpu->arch.regs_dirty);
719 EXPORT_SYMBOL_GPL(load_pdptrs);
721 bool pdptrs_changed(struct kvm_vcpu *vcpu)
723 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
729 if (!is_pae_paging(vcpu))
732 if (!test_bit(VCPU_EXREG_PDPTR,
733 (unsigned long *)&vcpu->arch.regs_avail))
736 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
737 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
738 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
739 PFERR_USER_MASK | PFERR_WRITE_MASK);
742 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
747 EXPORT_SYMBOL_GPL(pdptrs_changed);
749 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
751 unsigned long old_cr0 = kvm_read_cr0(vcpu);
752 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
757 if (cr0 & 0xffffffff00000000UL)
761 cr0 &= ~CR0_RESERVED_BITS;
763 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
766 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
769 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
771 if ((vcpu->arch.efer & EFER_LME)) {
776 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
781 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
786 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
789 kvm_x86_ops->set_cr0(vcpu, cr0);
791 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
792 kvm_clear_async_pf_completion_queue(vcpu);
793 kvm_async_pf_hash_reset(vcpu);
796 if ((cr0 ^ old_cr0) & update_bits)
797 kvm_mmu_reset_context(vcpu);
799 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
800 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
801 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
802 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
806 EXPORT_SYMBOL_GPL(kvm_set_cr0);
808 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
810 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
812 EXPORT_SYMBOL_GPL(kvm_lmsw);
814 void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
816 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
817 !vcpu->guest_xcr0_loaded) {
818 /* kvm_set_xcr() also depends on this */
819 if (vcpu->arch.xcr0 != host_xcr0)
820 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
821 vcpu->guest_xcr0_loaded = 1;
824 EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
826 void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
828 if (vcpu->guest_xcr0_loaded) {
829 if (vcpu->arch.xcr0 != host_xcr0)
830 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
831 vcpu->guest_xcr0_loaded = 0;
834 EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
836 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
839 u64 old_xcr0 = vcpu->arch.xcr0;
842 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
843 if (index != XCR_XFEATURE_ENABLED_MASK)
845 if (!(xcr0 & XFEATURE_MASK_FP))
847 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
851 * Do not allow the guest to set bits that we do not support
852 * saving. However, xcr0 bit 0 is always set, even if the
853 * emulated CPU does not support XSAVE (see fx_init).
855 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
856 if (xcr0 & ~valid_bits)
859 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
860 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
863 if (xcr0 & XFEATURE_MASK_AVX512) {
864 if (!(xcr0 & XFEATURE_MASK_YMM))
866 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
869 vcpu->arch.xcr0 = xcr0;
871 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
872 kvm_update_cpuid(vcpu);
876 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
878 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
879 __kvm_set_xcr(vcpu, index, xcr)) {
880 kvm_inject_gp(vcpu, 0);
885 EXPORT_SYMBOL_GPL(kvm_set_xcr);
887 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
889 unsigned long old_cr4 = kvm_read_cr4(vcpu);
890 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
891 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
893 if (cr4 & CR4_RESERVED_BITS)
896 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
899 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
902 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
905 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
908 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
911 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
914 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
917 if (is_long_mode(vcpu)) {
918 if (!(cr4 & X86_CR4_PAE))
920 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
921 && ((cr4 ^ old_cr4) & pdptr_bits)
922 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
926 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
927 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
930 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
931 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
935 if (kvm_x86_ops->set_cr4(vcpu, cr4))
938 if (((cr4 ^ old_cr4) & pdptr_bits) ||
939 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
940 kvm_mmu_reset_context(vcpu);
942 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
943 kvm_update_cpuid(vcpu);
947 EXPORT_SYMBOL_GPL(kvm_set_cr4);
949 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
951 bool skip_tlb_flush = false;
953 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
956 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
957 cr3 &= ~X86_CR3_PCID_NOFLUSH;
961 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
962 if (!skip_tlb_flush) {
963 kvm_mmu_sync_roots(vcpu);
964 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
969 if (is_long_mode(vcpu) &&
970 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
972 else if (is_pae_paging(vcpu) &&
973 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
976 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
977 vcpu->arch.cr3 = cr3;
978 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
982 EXPORT_SYMBOL_GPL(kvm_set_cr3);
984 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
986 if (cr8 & CR8_RESERVED_BITS)
988 if (lapic_in_kernel(vcpu))
989 kvm_lapic_set_tpr(vcpu, cr8);
991 vcpu->arch.cr8 = cr8;
994 EXPORT_SYMBOL_GPL(kvm_set_cr8);
996 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
998 if (lapic_in_kernel(vcpu))
999 return kvm_lapic_get_cr8(vcpu);
1001 return vcpu->arch.cr8;
1003 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1005 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1009 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1010 for (i = 0; i < KVM_NR_DB_REGS; i++)
1011 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1012 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1016 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1018 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1019 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1022 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1026 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1027 dr7 = vcpu->arch.guest_debug_dr7;
1029 dr7 = vcpu->arch.dr7;
1030 kvm_x86_ops->set_dr7(vcpu, dr7);
1031 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1032 if (dr7 & DR7_BP_EN_MASK)
1033 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1036 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1038 u64 fixed = DR6_FIXED_1;
1040 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1045 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1049 vcpu->arch.db[dr] = val;
1050 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1051 vcpu->arch.eff_db[dr] = val;
1056 if (val & 0xffffffff00000000ULL)
1057 return -1; /* #GP */
1058 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1059 kvm_update_dr6(vcpu);
1064 if (val & 0xffffffff00000000ULL)
1065 return -1; /* #GP */
1066 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1067 kvm_update_dr7(vcpu);
1074 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1076 if (__kvm_set_dr(vcpu, dr, val)) {
1077 kvm_inject_gp(vcpu, 0);
1082 EXPORT_SYMBOL_GPL(kvm_set_dr);
1084 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1088 *val = vcpu->arch.db[dr];
1093 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1094 *val = vcpu->arch.dr6;
1096 *val = kvm_x86_ops->get_dr6(vcpu);
1101 *val = vcpu->arch.dr7;
1106 EXPORT_SYMBOL_GPL(kvm_get_dr);
1108 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1110 u32 ecx = kvm_rcx_read(vcpu);
1114 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1117 kvm_rax_write(vcpu, (u32)data);
1118 kvm_rdx_write(vcpu, data >> 32);
1121 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1124 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1125 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1127 * This list is modified at module load time to reflect the
1128 * capabilities of the host cpu. This capabilities test skips MSRs that are
1129 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1130 * may depend on host virtualization features rather than host cpu features.
1133 static u32 msrs_to_save[] = {
1134 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1136 #ifdef CONFIG_X86_64
1137 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1139 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1140 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1142 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1143 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1144 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1145 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1146 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1147 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1148 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1149 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1150 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1151 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1152 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1153 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1154 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1155 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1156 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1157 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1158 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1159 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1160 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1161 MSR_ARCH_PERFMON_PERFCTR0 + 18, MSR_ARCH_PERFMON_PERFCTR0 + 19,
1162 MSR_ARCH_PERFMON_PERFCTR0 + 20, MSR_ARCH_PERFMON_PERFCTR0 + 21,
1163 MSR_ARCH_PERFMON_PERFCTR0 + 22, MSR_ARCH_PERFMON_PERFCTR0 + 23,
1164 MSR_ARCH_PERFMON_PERFCTR0 + 24, MSR_ARCH_PERFMON_PERFCTR0 + 25,
1165 MSR_ARCH_PERFMON_PERFCTR0 + 26, MSR_ARCH_PERFMON_PERFCTR0 + 27,
1166 MSR_ARCH_PERFMON_PERFCTR0 + 28, MSR_ARCH_PERFMON_PERFCTR0 + 29,
1167 MSR_ARCH_PERFMON_PERFCTR0 + 30, MSR_ARCH_PERFMON_PERFCTR0 + 31,
1168 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1169 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1170 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1171 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1172 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1173 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1174 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1175 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1176 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1177 MSR_ARCH_PERFMON_EVENTSEL0 + 18, MSR_ARCH_PERFMON_EVENTSEL0 + 19,
1178 MSR_ARCH_PERFMON_EVENTSEL0 + 20, MSR_ARCH_PERFMON_EVENTSEL0 + 21,
1179 MSR_ARCH_PERFMON_EVENTSEL0 + 22, MSR_ARCH_PERFMON_EVENTSEL0 + 23,
1180 MSR_ARCH_PERFMON_EVENTSEL0 + 24, MSR_ARCH_PERFMON_EVENTSEL0 + 25,
1181 MSR_ARCH_PERFMON_EVENTSEL0 + 26, MSR_ARCH_PERFMON_EVENTSEL0 + 27,
1182 MSR_ARCH_PERFMON_EVENTSEL0 + 28, MSR_ARCH_PERFMON_EVENTSEL0 + 29,
1183 MSR_ARCH_PERFMON_EVENTSEL0 + 30, MSR_ARCH_PERFMON_EVENTSEL0 + 31,
1186 static unsigned num_msrs_to_save;
1188 static u32 emulated_msrs[] = {
1189 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1190 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1191 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1192 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1193 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1194 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1195 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1197 HV_X64_MSR_VP_INDEX,
1198 HV_X64_MSR_VP_RUNTIME,
1199 HV_X64_MSR_SCONTROL,
1200 HV_X64_MSR_STIMER0_CONFIG,
1201 HV_X64_MSR_VP_ASSIST_PAGE,
1202 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1203 HV_X64_MSR_TSC_EMULATION_STATUS,
1205 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1208 MSR_IA32_TSC_ADJUST,
1209 MSR_IA32_TSCDEADLINE,
1210 MSR_IA32_ARCH_CAPABILITIES,
1211 MSR_IA32_MISC_ENABLE,
1212 MSR_IA32_MCG_STATUS,
1214 MSR_IA32_MCG_EXT_CTL,
1218 MSR_MISC_FEATURES_ENABLES,
1219 MSR_AMD64_VIRT_SPEC_CTRL,
1223 * The following list leaves out MSRs whose values are determined
1224 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1225 * We always support the "true" VMX control MSRs, even if the host
1226 * processor does not, so I am putting these registers here rather
1227 * than in msrs_to_save.
1230 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1231 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1232 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1233 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1235 MSR_IA32_VMX_CR0_FIXED0,
1236 MSR_IA32_VMX_CR4_FIXED0,
1237 MSR_IA32_VMX_VMCS_ENUM,
1238 MSR_IA32_VMX_PROCBASED_CTLS2,
1239 MSR_IA32_VMX_EPT_VPID_CAP,
1240 MSR_IA32_VMX_VMFUNC,
1243 MSR_KVM_POLL_CONTROL,
1246 static unsigned num_emulated_msrs;
1249 * List of msr numbers which are used to expose MSR-based features that
1250 * can be used by a hypervisor to validate requested CPU features.
1252 static u32 msr_based_features[] = {
1254 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1255 MSR_IA32_VMX_PINBASED_CTLS,
1256 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1257 MSR_IA32_VMX_PROCBASED_CTLS,
1258 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1259 MSR_IA32_VMX_EXIT_CTLS,
1260 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1261 MSR_IA32_VMX_ENTRY_CTLS,
1263 MSR_IA32_VMX_CR0_FIXED0,
1264 MSR_IA32_VMX_CR0_FIXED1,
1265 MSR_IA32_VMX_CR4_FIXED0,
1266 MSR_IA32_VMX_CR4_FIXED1,
1267 MSR_IA32_VMX_VMCS_ENUM,
1268 MSR_IA32_VMX_PROCBASED_CTLS2,
1269 MSR_IA32_VMX_EPT_VPID_CAP,
1270 MSR_IA32_VMX_VMFUNC,
1274 MSR_IA32_ARCH_CAPABILITIES,
1277 static unsigned int num_msr_based_features;
1279 static u64 kvm_get_arch_capabilities(void)
1283 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1284 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1287 * If we're doing cache flushes (either "always" or "cond")
1288 * we will do one whenever the guest does a vmlaunch/vmresume.
1289 * If an outer hypervisor is doing the cache flush for us
1290 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1291 * capability to the guest too, and if EPT is disabled we're not
1292 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1293 * require a nested hypervisor to do a flush of its own.
1295 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1296 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1298 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1299 data |= ARCH_CAP_RDCL_NO;
1300 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1301 data |= ARCH_CAP_SSB_NO;
1302 if (!boot_cpu_has_bug(X86_BUG_MDS))
1303 data |= ARCH_CAP_MDS_NO;
1308 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1310 switch (msr->index) {
1311 case MSR_IA32_ARCH_CAPABILITIES:
1312 msr->data = kvm_get_arch_capabilities();
1314 case MSR_IA32_UCODE_REV:
1315 rdmsrl_safe(msr->index, &msr->data);
1318 if (kvm_x86_ops->get_msr_feature(msr))
1324 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1326 struct kvm_msr_entry msr;
1330 r = kvm_get_msr_feature(&msr);
1339 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1341 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1344 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1347 if (efer & (EFER_LME | EFER_LMA) &&
1348 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1351 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1357 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1359 if (efer & efer_reserved_bits)
1362 return __kvm_valid_efer(vcpu, efer);
1364 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1366 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1368 u64 old_efer = vcpu->arch.efer;
1369 u64 efer = msr_info->data;
1371 if (efer & efer_reserved_bits)
1374 if (!msr_info->host_initiated) {
1375 if (!__kvm_valid_efer(vcpu, efer))
1378 if (is_paging(vcpu) &&
1379 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1384 efer |= vcpu->arch.efer & EFER_LMA;
1386 kvm_x86_ops->set_efer(vcpu, efer);
1388 /* Update reserved bits */
1389 if ((efer ^ old_efer) & EFER_NX)
1390 kvm_mmu_reset_context(vcpu);
1395 void kvm_enable_efer_bits(u64 mask)
1397 efer_reserved_bits &= ~mask;
1399 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1402 * Write @data into the MSR specified by @index. Select MSR specific fault
1403 * checks are bypassed if @host_initiated is %true.
1404 * Returns 0 on success, non-0 otherwise.
1405 * Assumes vcpu_load() was already called.
1407 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1408 bool host_initiated)
1410 struct msr_data msr;
1415 case MSR_KERNEL_GS_BASE:
1418 if (is_noncanonical_address(data, vcpu))
1421 case MSR_IA32_SYSENTER_EIP:
1422 case MSR_IA32_SYSENTER_ESP:
1424 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1425 * non-canonical address is written on Intel but not on
1426 * AMD (which ignores the top 32-bits, because it does
1427 * not implement 64-bit SYSENTER).
1429 * 64-bit code should hence be able to write a non-canonical
1430 * value on AMD. Making the address canonical ensures that
1431 * vmentry does not fail on Intel after writing a non-canonical
1432 * value, and that something deterministic happens if the guest
1433 * invokes 64-bit SYSENTER.
1435 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1440 msr.host_initiated = host_initiated;
1442 return kvm_x86_ops->set_msr(vcpu, &msr);
1446 * Read the MSR specified by @index into @data. Select MSR specific fault
1447 * checks are bypassed if @host_initiated is %true.
1448 * Returns 0 on success, non-0 otherwise.
1449 * Assumes vcpu_load() was already called.
1451 static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1452 bool host_initiated)
1454 struct msr_data msr;
1458 msr.host_initiated = host_initiated;
1460 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1466 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1468 return __kvm_get_msr(vcpu, index, data, false);
1470 EXPORT_SYMBOL_GPL(kvm_get_msr);
1472 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1474 return __kvm_set_msr(vcpu, index, data, false);
1476 EXPORT_SYMBOL_GPL(kvm_set_msr);
1478 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1480 u32 ecx = kvm_rcx_read(vcpu);
1483 if (kvm_get_msr(vcpu, ecx, &data)) {
1484 trace_kvm_msr_read_ex(ecx);
1485 kvm_inject_gp(vcpu, 0);
1489 trace_kvm_msr_read(ecx, data);
1491 kvm_rax_write(vcpu, data & -1u);
1492 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1493 return kvm_skip_emulated_instruction(vcpu);
1495 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1497 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1499 u32 ecx = kvm_rcx_read(vcpu);
1500 u64 data = kvm_read_edx_eax(vcpu);
1502 if (kvm_set_msr(vcpu, ecx, data)) {
1503 trace_kvm_msr_write_ex(ecx, data);
1504 kvm_inject_gp(vcpu, 0);
1508 trace_kvm_msr_write(ecx, data);
1509 return kvm_skip_emulated_instruction(vcpu);
1511 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1514 * Adapt set_msr() to msr_io()'s calling convention
1516 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1518 return __kvm_get_msr(vcpu, index, data, true);
1521 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1523 return __kvm_set_msr(vcpu, index, *data, true);
1526 #ifdef CONFIG_X86_64
1527 struct pvclock_gtod_data {
1530 struct { /* extract of a clocksource struct */
1543 static struct pvclock_gtod_data pvclock_gtod_data;
1545 static void update_pvclock_gtod(struct timekeeper *tk)
1547 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1550 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1552 write_seqcount_begin(&vdata->seq);
1554 /* copy pvclock gtod data */
1555 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1556 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1557 vdata->clock.mask = tk->tkr_mono.mask;
1558 vdata->clock.mult = tk->tkr_mono.mult;
1559 vdata->clock.shift = tk->tkr_mono.shift;
1561 vdata->boot_ns = boot_ns;
1562 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1564 vdata->wall_time_sec = tk->xtime_sec;
1566 write_seqcount_end(&vdata->seq);
1570 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1572 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1573 kvm_vcpu_kick(vcpu);
1576 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1580 struct pvclock_wall_clock wc;
1581 struct timespec64 boot;
1586 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1591 ++version; /* first time write, random junk */
1595 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1599 * The guest calculates current wall clock time by adding
1600 * system time (updated by kvm_guest_time_update below) to the
1601 * wall clock specified here. guest system time equals host
1602 * system time for us, thus we must fill in host boot time here.
1604 getboottime64(&boot);
1606 if (kvm->arch.kvmclock_offset) {
1607 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1608 boot = timespec64_sub(boot, ts);
1610 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1611 wc.nsec = boot.tv_nsec;
1612 wc.version = version;
1614 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1617 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1620 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1622 do_shl32_div32(dividend, divisor);
1626 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1627 s8 *pshift, u32 *pmultiplier)
1635 scaled64 = scaled_hz;
1636 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1641 tps32 = (uint32_t)tps64;
1642 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1643 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1651 *pmultiplier = div_frac(scaled64, tps32);
1654 #ifdef CONFIG_X86_64
1655 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1658 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1659 static unsigned long max_tsc_khz;
1661 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1663 u64 v = (u64)khz * (1000000 + ppm);
1668 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1672 /* Guest TSC same frequency as host TSC? */
1674 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1678 /* TSC scaling supported? */
1679 if (!kvm_has_tsc_control) {
1680 if (user_tsc_khz > tsc_khz) {
1681 vcpu->arch.tsc_catchup = 1;
1682 vcpu->arch.tsc_always_catchup = 1;
1685 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1690 /* TSC scaling required - calculate ratio */
1691 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1692 user_tsc_khz, tsc_khz);
1694 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1695 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1700 vcpu->arch.tsc_scaling_ratio = ratio;
1704 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1706 u32 thresh_lo, thresh_hi;
1707 int use_scaling = 0;
1709 /* tsc_khz can be zero if TSC calibration fails */
1710 if (user_tsc_khz == 0) {
1711 /* set tsc_scaling_ratio to a safe value */
1712 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1716 /* Compute a scale to convert nanoseconds in TSC cycles */
1717 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1718 &vcpu->arch.virtual_tsc_shift,
1719 &vcpu->arch.virtual_tsc_mult);
1720 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1723 * Compute the variation in TSC rate which is acceptable
1724 * within the range of tolerance and decide if the
1725 * rate being applied is within that bounds of the hardware
1726 * rate. If so, no scaling or compensation need be done.
1728 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1729 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1730 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1731 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1734 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1737 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1739 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1740 vcpu->arch.virtual_tsc_mult,
1741 vcpu->arch.virtual_tsc_shift);
1742 tsc += vcpu->arch.this_tsc_write;
1746 static inline int gtod_is_based_on_tsc(int mode)
1748 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1751 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1753 #ifdef CONFIG_X86_64
1755 struct kvm_arch *ka = &vcpu->kvm->arch;
1756 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1758 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1759 atomic_read(&vcpu->kvm->online_vcpus));
1762 * Once the masterclock is enabled, always perform request in
1763 * order to update it.
1765 * In order to enable masterclock, the host clocksource must be TSC
1766 * and the vcpus need to have matched TSCs. When that happens,
1767 * perform request to enable masterclock.
1769 if (ka->use_master_clock ||
1770 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1771 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1773 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1774 atomic_read(&vcpu->kvm->online_vcpus),
1775 ka->use_master_clock, gtod->clock.vclock_mode);
1779 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1781 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1782 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1786 * Multiply tsc by a fixed point number represented by ratio.
1788 * The most significant 64-N bits (mult) of ratio represent the
1789 * integral part of the fixed point number; the remaining N bits
1790 * (frac) represent the fractional part, ie. ratio represents a fixed
1791 * point number (mult + frac * 2^(-N)).
1793 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1795 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1797 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1800 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1803 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1805 if (ratio != kvm_default_tsc_scaling_ratio)
1806 _tsc = __scale_tsc(ratio, tsc);
1810 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1812 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1816 tsc = kvm_scale_tsc(vcpu, rdtsc());
1818 return target_tsc - tsc;
1821 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1823 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1825 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1827 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1829 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1831 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1834 static inline bool kvm_check_tsc_unstable(void)
1836 #ifdef CONFIG_X86_64
1838 * TSC is marked unstable when we're running on Hyper-V,
1839 * 'TSC page' clocksource is good.
1841 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1844 return check_tsc_unstable();
1847 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1849 struct kvm *kvm = vcpu->kvm;
1850 u64 offset, ns, elapsed;
1851 unsigned long flags;
1853 bool already_matched;
1854 u64 data = msr->data;
1855 bool synchronizing = false;
1857 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1858 offset = kvm_compute_tsc_offset(vcpu, data);
1859 ns = ktime_get_boottime_ns();
1860 elapsed = ns - kvm->arch.last_tsc_nsec;
1862 if (vcpu->arch.virtual_tsc_khz) {
1863 if (data == 0 && msr->host_initiated) {
1865 * detection of vcpu initialization -- need to sync
1866 * with other vCPUs. This particularly helps to keep
1867 * kvm_clock stable after CPU hotplug
1869 synchronizing = true;
1871 u64 tsc_exp = kvm->arch.last_tsc_write +
1872 nsec_to_cycles(vcpu, elapsed);
1873 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1875 * Special case: TSC write with a small delta (1 second)
1876 * of virtual cycle time against real time is
1877 * interpreted as an attempt to synchronize the CPU.
1879 synchronizing = data < tsc_exp + tsc_hz &&
1880 data + tsc_hz > tsc_exp;
1885 * For a reliable TSC, we can match TSC offsets, and for an unstable
1886 * TSC, we add elapsed time in this computation. We could let the
1887 * compensation code attempt to catch up if we fall behind, but
1888 * it's better to try to match offsets from the beginning.
1890 if (synchronizing &&
1891 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1892 if (!kvm_check_tsc_unstable()) {
1893 offset = kvm->arch.cur_tsc_offset;
1895 u64 delta = nsec_to_cycles(vcpu, elapsed);
1897 offset = kvm_compute_tsc_offset(vcpu, data);
1900 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1903 * We split periods of matched TSC writes into generations.
1904 * For each generation, we track the original measured
1905 * nanosecond time, offset, and write, so if TSCs are in
1906 * sync, we can match exact offset, and if not, we can match
1907 * exact software computation in compute_guest_tsc()
1909 * These values are tracked in kvm->arch.cur_xxx variables.
1911 kvm->arch.cur_tsc_generation++;
1912 kvm->arch.cur_tsc_nsec = ns;
1913 kvm->arch.cur_tsc_write = data;
1914 kvm->arch.cur_tsc_offset = offset;
1919 * We also track th most recent recorded KHZ, write and time to
1920 * allow the matching interval to be extended at each write.
1922 kvm->arch.last_tsc_nsec = ns;
1923 kvm->arch.last_tsc_write = data;
1924 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1926 vcpu->arch.last_guest_tsc = data;
1928 /* Keep track of which generation this VCPU has synchronized to */
1929 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1930 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1931 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1933 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1934 update_ia32_tsc_adjust_msr(vcpu, offset);
1936 kvm_vcpu_write_tsc_offset(vcpu, offset);
1937 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1939 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1941 kvm->arch.nr_vcpus_matched_tsc = 0;
1942 } else if (!already_matched) {
1943 kvm->arch.nr_vcpus_matched_tsc++;
1946 kvm_track_tsc_matching(vcpu);
1947 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1950 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1952 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1955 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1956 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
1959 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1961 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1962 WARN_ON(adjustment < 0);
1963 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1964 adjust_tsc_offset_guest(vcpu, adjustment);
1967 #ifdef CONFIG_X86_64
1969 static u64 read_tsc(void)
1971 u64 ret = (u64)rdtsc_ordered();
1972 u64 last = pvclock_gtod_data.clock.cycle_last;
1974 if (likely(ret >= last))
1978 * GCC likes to generate cmov here, but this branch is extremely
1979 * predictable (it's just a function of time and the likely is
1980 * very likely) and there's a data dependence, so force GCC
1981 * to generate a branch instead. I don't barrier() because
1982 * we don't actually need a barrier, and if this function
1983 * ever gets inlined it will generate worse code.
1989 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1992 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1995 switch (gtod->clock.vclock_mode) {
1996 case VCLOCK_HVCLOCK:
1997 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1999 if (tsc_pg_val != U64_MAX) {
2000 /* TSC page valid */
2001 *mode = VCLOCK_HVCLOCK;
2002 v = (tsc_pg_val - gtod->clock.cycle_last) &
2005 /* TSC page invalid */
2006 *mode = VCLOCK_NONE;
2011 *tsc_timestamp = read_tsc();
2012 v = (*tsc_timestamp - gtod->clock.cycle_last) &
2016 *mode = VCLOCK_NONE;
2019 if (*mode == VCLOCK_NONE)
2020 *tsc_timestamp = v = 0;
2022 return v * gtod->clock.mult;
2025 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
2027 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2033 seq = read_seqcount_begin(>od->seq);
2034 ns = gtod->nsec_base;
2035 ns += vgettsc(tsc_timestamp, &mode);
2036 ns >>= gtod->clock.shift;
2037 ns += gtod->boot_ns;
2038 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2044 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2046 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2052 seq = read_seqcount_begin(>od->seq);
2053 ts->tv_sec = gtod->wall_time_sec;
2054 ns = gtod->nsec_base;
2055 ns += vgettsc(tsc_timestamp, &mode);
2056 ns >>= gtod->clock.shift;
2057 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2059 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2065 /* returns true if host is using TSC based clocksource */
2066 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2068 /* checked again under seqlock below */
2069 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2072 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
2076 /* returns true if host is using TSC based clocksource */
2077 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2080 /* checked again under seqlock below */
2081 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2084 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2090 * Assuming a stable TSC across physical CPUS, and a stable TSC
2091 * across virtual CPUs, the following condition is possible.
2092 * Each numbered line represents an event visible to both
2093 * CPUs at the next numbered event.
2095 * "timespecX" represents host monotonic time. "tscX" represents
2098 * VCPU0 on CPU0 | VCPU1 on CPU1
2100 * 1. read timespec0,tsc0
2101 * 2. | timespec1 = timespec0 + N
2103 * 3. transition to guest | transition to guest
2104 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2105 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2106 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2108 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2111 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2113 * - 0 < N - M => M < N
2115 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2116 * always the case (the difference between two distinct xtime instances
2117 * might be smaller then the difference between corresponding TSC reads,
2118 * when updating guest vcpus pvclock areas).
2120 * To avoid that problem, do not allow visibility of distinct
2121 * system_timestamp/tsc_timestamp values simultaneously: use a master
2122 * copy of host monotonic time values. Update that master copy
2125 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2129 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2131 #ifdef CONFIG_X86_64
2132 struct kvm_arch *ka = &kvm->arch;
2134 bool host_tsc_clocksource, vcpus_matched;
2136 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2137 atomic_read(&kvm->online_vcpus));
2140 * If the host uses TSC clock, then passthrough TSC as stable
2143 host_tsc_clocksource = kvm_get_time_and_clockread(
2144 &ka->master_kernel_ns,
2145 &ka->master_cycle_now);
2147 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2148 && !ka->backwards_tsc_observed
2149 && !ka->boot_vcpu_runs_old_kvmclock;
2151 if (ka->use_master_clock)
2152 atomic_set(&kvm_guest_has_master_clock, 1);
2154 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2155 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2160 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2162 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2165 static void kvm_gen_update_masterclock(struct kvm *kvm)
2167 #ifdef CONFIG_X86_64
2169 struct kvm_vcpu *vcpu;
2170 struct kvm_arch *ka = &kvm->arch;
2172 spin_lock(&ka->pvclock_gtod_sync_lock);
2173 kvm_make_mclock_inprogress_request(kvm);
2174 /* no guest entries from this point */
2175 pvclock_update_vm_gtod_copy(kvm);
2177 kvm_for_each_vcpu(i, vcpu, kvm)
2178 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2180 /* guest entries allowed */
2181 kvm_for_each_vcpu(i, vcpu, kvm)
2182 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2184 spin_unlock(&ka->pvclock_gtod_sync_lock);
2188 u64 get_kvmclock_ns(struct kvm *kvm)
2190 struct kvm_arch *ka = &kvm->arch;
2191 struct pvclock_vcpu_time_info hv_clock;
2194 spin_lock(&ka->pvclock_gtod_sync_lock);
2195 if (!ka->use_master_clock) {
2196 spin_unlock(&ka->pvclock_gtod_sync_lock);
2197 return ktime_get_boottime_ns() + ka->kvmclock_offset;
2200 hv_clock.tsc_timestamp = ka->master_cycle_now;
2201 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2202 spin_unlock(&ka->pvclock_gtod_sync_lock);
2204 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2207 if (__this_cpu_read(cpu_tsc_khz)) {
2208 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2209 &hv_clock.tsc_shift,
2210 &hv_clock.tsc_to_system_mul);
2211 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2213 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
2220 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2222 struct kvm_vcpu_arch *vcpu = &v->arch;
2223 struct pvclock_vcpu_time_info guest_hv_clock;
2225 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2226 &guest_hv_clock, sizeof(guest_hv_clock))))
2229 /* This VCPU is paused, but it's legal for a guest to read another
2230 * VCPU's kvmclock, so we really have to follow the specification where
2231 * it says that version is odd if data is being modified, and even after
2234 * Version field updates must be kept separate. This is because
2235 * kvm_write_guest_cached might use a "rep movs" instruction, and
2236 * writes within a string instruction are weakly ordered. So there
2237 * are three writes overall.
2239 * As a small optimization, only write the version field in the first
2240 * and third write. The vcpu->pv_time cache is still valid, because the
2241 * version field is the first in the struct.
2243 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2245 if (guest_hv_clock.version & 1)
2246 ++guest_hv_clock.version; /* first time write, random junk */
2248 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2249 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2251 sizeof(vcpu->hv_clock.version));
2255 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2256 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2258 if (vcpu->pvclock_set_guest_stopped_request) {
2259 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2260 vcpu->pvclock_set_guest_stopped_request = false;
2263 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2265 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2267 sizeof(vcpu->hv_clock));
2271 vcpu->hv_clock.version++;
2272 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2274 sizeof(vcpu->hv_clock.version));
2277 static int kvm_guest_time_update(struct kvm_vcpu *v)
2279 unsigned long flags, tgt_tsc_khz;
2280 struct kvm_vcpu_arch *vcpu = &v->arch;
2281 struct kvm_arch *ka = &v->kvm->arch;
2283 u64 tsc_timestamp, host_tsc;
2285 bool use_master_clock;
2291 * If the host uses TSC clock, then passthrough TSC as stable
2294 spin_lock(&ka->pvclock_gtod_sync_lock);
2295 use_master_clock = ka->use_master_clock;
2296 if (use_master_clock) {
2297 host_tsc = ka->master_cycle_now;
2298 kernel_ns = ka->master_kernel_ns;
2300 spin_unlock(&ka->pvclock_gtod_sync_lock);
2302 /* Keep irq disabled to prevent changes to the clock */
2303 local_irq_save(flags);
2304 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2305 if (unlikely(tgt_tsc_khz == 0)) {
2306 local_irq_restore(flags);
2307 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2310 if (!use_master_clock) {
2312 kernel_ns = ktime_get_boottime_ns();
2315 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2318 * We may have to catch up the TSC to match elapsed wall clock
2319 * time for two reasons, even if kvmclock is used.
2320 * 1) CPU could have been running below the maximum TSC rate
2321 * 2) Broken TSC compensation resets the base at each VCPU
2322 * entry to avoid unknown leaps of TSC even when running
2323 * again on the same CPU. This may cause apparent elapsed
2324 * time to disappear, and the guest to stand still or run
2327 if (vcpu->tsc_catchup) {
2328 u64 tsc = compute_guest_tsc(v, kernel_ns);
2329 if (tsc > tsc_timestamp) {
2330 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2331 tsc_timestamp = tsc;
2335 local_irq_restore(flags);
2337 /* With all the info we got, fill in the values */
2339 if (kvm_has_tsc_control)
2340 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2342 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2343 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2344 &vcpu->hv_clock.tsc_shift,
2345 &vcpu->hv_clock.tsc_to_system_mul);
2346 vcpu->hw_tsc_khz = tgt_tsc_khz;
2349 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2350 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2351 vcpu->last_guest_tsc = tsc_timestamp;
2353 /* If the host uses TSC clocksource, then it is stable */
2355 if (use_master_clock)
2356 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2358 vcpu->hv_clock.flags = pvclock_flags;
2360 if (vcpu->pv_time_enabled)
2361 kvm_setup_pvclock_page(v);
2362 if (v == kvm_get_vcpu(v->kvm, 0))
2363 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2368 * kvmclock updates which are isolated to a given vcpu, such as
2369 * vcpu->cpu migration, should not allow system_timestamp from
2370 * the rest of the vcpus to remain static. Otherwise ntp frequency
2371 * correction applies to one vcpu's system_timestamp but not
2374 * So in those cases, request a kvmclock update for all vcpus.
2375 * We need to rate-limit these requests though, as they can
2376 * considerably slow guests that have a large number of vcpus.
2377 * The time for a remote vcpu to update its kvmclock is bound
2378 * by the delay we use to rate-limit the updates.
2381 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2383 static void kvmclock_update_fn(struct work_struct *work)
2386 struct delayed_work *dwork = to_delayed_work(work);
2387 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2388 kvmclock_update_work);
2389 struct kvm *kvm = container_of(ka, struct kvm, arch);
2390 struct kvm_vcpu *vcpu;
2392 kvm_for_each_vcpu(i, vcpu, kvm) {
2393 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2394 kvm_vcpu_kick(vcpu);
2398 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2400 struct kvm *kvm = v->kvm;
2402 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2403 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2404 KVMCLOCK_UPDATE_DELAY);
2407 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2409 static void kvmclock_sync_fn(struct work_struct *work)
2411 struct delayed_work *dwork = to_delayed_work(work);
2412 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2413 kvmclock_sync_work);
2414 struct kvm *kvm = container_of(ka, struct kvm, arch);
2416 if (!kvmclock_periodic_sync)
2419 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2420 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2421 KVMCLOCK_SYNC_PERIOD);
2425 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2427 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2429 /* McStatusWrEn enabled? */
2430 if (guest_cpuid_is_amd(vcpu))
2431 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2436 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2438 u64 mcg_cap = vcpu->arch.mcg_cap;
2439 unsigned bank_num = mcg_cap & 0xff;
2440 u32 msr = msr_info->index;
2441 u64 data = msr_info->data;
2444 case MSR_IA32_MCG_STATUS:
2445 vcpu->arch.mcg_status = data;
2447 case MSR_IA32_MCG_CTL:
2448 if (!(mcg_cap & MCG_CTL_P) &&
2449 (data || !msr_info->host_initiated))
2451 if (data != 0 && data != ~(u64)0)
2453 vcpu->arch.mcg_ctl = data;
2456 if (msr >= MSR_IA32_MC0_CTL &&
2457 msr < MSR_IA32_MCx_CTL(bank_num)) {
2458 u32 offset = msr - MSR_IA32_MC0_CTL;
2459 /* only 0 or all 1s can be written to IA32_MCi_CTL
2460 * some Linux kernels though clear bit 10 in bank 4 to
2461 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2462 * this to avoid an uncatched #GP in the guest
2464 if ((offset & 0x3) == 0 &&
2465 data != 0 && (data | (1 << 10)) != ~(u64)0)
2469 if (!msr_info->host_initiated &&
2470 (offset & 0x3) == 1 && data != 0) {
2471 if (!can_set_mci_status(vcpu))
2475 vcpu->arch.mce_banks[offset] = data;
2483 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2485 struct kvm *kvm = vcpu->kvm;
2486 int lm = is_long_mode(vcpu);
2487 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2488 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2489 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2490 : kvm->arch.xen_hvm_config.blob_size_32;
2491 u32 page_num = data & ~PAGE_MASK;
2492 u64 page_addr = data & PAGE_MASK;
2497 if (page_num >= blob_size)
2500 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2505 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2514 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2516 gpa_t gpa = data & ~0x3f;
2518 /* Bits 3:5 are reserved, Should be zero */
2522 vcpu->arch.apf.msr_val = data;
2524 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2525 kvm_clear_async_pf_completion_queue(vcpu);
2526 kvm_async_pf_hash_reset(vcpu);
2530 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2534 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2535 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2536 kvm_async_pf_wakeup_all(vcpu);
2540 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2542 vcpu->arch.pv_time_enabled = false;
2545 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2547 ++vcpu->stat.tlb_flush;
2548 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2551 static void record_steal_time(struct kvm_vcpu *vcpu)
2553 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2556 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2557 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2561 * Doing a TLB flush here, on the guest's behalf, can avoid
2564 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2565 vcpu->arch.st.steal.preempted & KVM_VCPU_FLUSH_TLB);
2566 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2567 kvm_vcpu_flush_tlb(vcpu, false);
2569 if (vcpu->arch.st.steal.version & 1)
2570 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2572 vcpu->arch.st.steal.version += 1;
2574 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2575 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2579 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2580 vcpu->arch.st.last_steal;
2581 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2583 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2584 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2588 vcpu->arch.st.steal.version += 1;
2590 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2591 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2594 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2597 u32 msr = msr_info->index;
2598 u64 data = msr_info->data;
2601 case MSR_AMD64_NB_CFG:
2602 case MSR_IA32_UCODE_WRITE:
2603 case MSR_VM_HSAVE_PA:
2604 case MSR_AMD64_PATCH_LOADER:
2605 case MSR_AMD64_BU_CFG2:
2606 case MSR_AMD64_DC_CFG:
2607 case MSR_F15H_EX_CFG:
2610 case MSR_IA32_UCODE_REV:
2611 if (msr_info->host_initiated)
2612 vcpu->arch.microcode_version = data;
2614 case MSR_IA32_ARCH_CAPABILITIES:
2615 if (!msr_info->host_initiated)
2617 vcpu->arch.arch_capabilities = data;
2620 return set_efer(vcpu, msr_info);
2622 data &= ~(u64)0x40; /* ignore flush filter disable */
2623 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2624 data &= ~(u64)0x8; /* ignore TLB cache disable */
2626 /* Handle McStatusWrEn */
2627 if (data == BIT_ULL(18)) {
2628 vcpu->arch.msr_hwcr = data;
2629 } else if (data != 0) {
2630 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2635 case MSR_FAM10H_MMIO_CONF_BASE:
2637 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2642 case MSR_IA32_DEBUGCTLMSR:
2644 /* We support the non-activated case already */
2646 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2647 /* Values other than LBR and BTF are vendor-specific,
2648 thus reserved and should throw a #GP */
2651 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2654 case 0x200 ... 0x2ff:
2655 return kvm_mtrr_set_msr(vcpu, msr, data);
2656 case MSR_IA32_APICBASE:
2657 return kvm_set_apic_base(vcpu, msr_info);
2658 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2659 return kvm_x2apic_msr_write(vcpu, msr, data);
2660 case MSR_IA32_TSCDEADLINE:
2661 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2663 case MSR_IA32_TSC_ADJUST:
2664 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2665 if (!msr_info->host_initiated) {
2666 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2667 adjust_tsc_offset_guest(vcpu, adj);
2669 vcpu->arch.ia32_tsc_adjust_msr = data;
2672 case MSR_IA32_MISC_ENABLE:
2673 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2674 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2675 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2677 vcpu->arch.ia32_misc_enable_msr = data;
2678 kvm_update_cpuid(vcpu);
2680 vcpu->arch.ia32_misc_enable_msr = data;
2683 case MSR_IA32_SMBASE:
2684 if (!msr_info->host_initiated)
2686 vcpu->arch.smbase = data;
2688 case MSR_IA32_POWER_CTL:
2689 vcpu->arch.msr_ia32_power_ctl = data;
2692 kvm_write_tsc(vcpu, msr_info);
2695 if (!msr_info->host_initiated)
2697 vcpu->arch.smi_count = data;
2699 case MSR_KVM_WALL_CLOCK_NEW:
2700 case MSR_KVM_WALL_CLOCK:
2701 vcpu->kvm->arch.wall_clock = data;
2702 kvm_write_wall_clock(vcpu->kvm, data);
2704 case MSR_KVM_SYSTEM_TIME_NEW:
2705 case MSR_KVM_SYSTEM_TIME: {
2706 struct kvm_arch *ka = &vcpu->kvm->arch;
2708 kvmclock_reset(vcpu);
2710 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2711 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2713 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2714 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2716 ka->boot_vcpu_runs_old_kvmclock = tmp;
2719 vcpu->arch.time = data;
2720 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2722 /* we verify if the enable bit is set... */
2726 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2727 &vcpu->arch.pv_time, data & ~1ULL,
2728 sizeof(struct pvclock_vcpu_time_info)))
2729 vcpu->arch.pv_time_enabled = false;
2731 vcpu->arch.pv_time_enabled = true;
2735 case MSR_KVM_ASYNC_PF_EN:
2736 if (kvm_pv_enable_async_pf(vcpu, data))
2739 case MSR_KVM_STEAL_TIME:
2741 if (unlikely(!sched_info_on()))
2744 if (data & KVM_STEAL_RESERVED_MASK)
2747 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2748 data & KVM_STEAL_VALID_BITS,
2749 sizeof(struct kvm_steal_time)))
2752 vcpu->arch.st.msr_val = data;
2754 if (!(data & KVM_MSR_ENABLED))
2757 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2760 case MSR_KVM_PV_EOI_EN:
2761 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2765 case MSR_KVM_POLL_CONTROL:
2766 /* only enable bit supported */
2767 if (data & (-1ULL << 1))
2770 vcpu->arch.msr_kvm_poll_control = data;
2773 case MSR_IA32_MCG_CTL:
2774 case MSR_IA32_MCG_STATUS:
2775 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2776 return set_msr_mce(vcpu, msr_info);
2778 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2779 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2780 pr = true; /* fall through */
2781 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2782 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2783 if (kvm_pmu_is_valid_msr(vcpu, msr))
2784 return kvm_pmu_set_msr(vcpu, msr_info);
2786 if (pr || data != 0)
2787 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2788 "0x%x data 0x%llx\n", msr, data);
2790 case MSR_K7_CLK_CTL:
2792 * Ignore all writes to this no longer documented MSR.
2793 * Writes are only relevant for old K7 processors,
2794 * all pre-dating SVM, but a recommended workaround from
2795 * AMD for these chips. It is possible to specify the
2796 * affected processor models on the command line, hence
2797 * the need to ignore the workaround.
2800 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2801 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2802 case HV_X64_MSR_CRASH_CTL:
2803 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2804 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2805 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2806 case HV_X64_MSR_TSC_EMULATION_STATUS:
2807 return kvm_hv_set_msr_common(vcpu, msr, data,
2808 msr_info->host_initiated);
2809 case MSR_IA32_BBL_CR_CTL3:
2810 /* Drop writes to this legacy MSR -- see rdmsr
2811 * counterpart for further detail.
2813 if (report_ignored_msrs)
2814 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2817 case MSR_AMD64_OSVW_ID_LENGTH:
2818 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2820 vcpu->arch.osvw.length = data;
2822 case MSR_AMD64_OSVW_STATUS:
2823 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2825 vcpu->arch.osvw.status = data;
2827 case MSR_PLATFORM_INFO:
2828 if (!msr_info->host_initiated ||
2829 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2830 cpuid_fault_enabled(vcpu)))
2832 vcpu->arch.msr_platform_info = data;
2834 case MSR_MISC_FEATURES_ENABLES:
2835 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2836 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2837 !supports_cpuid_fault(vcpu)))
2839 vcpu->arch.msr_misc_features_enables = data;
2842 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2843 return xen_hvm_config(vcpu, data);
2844 if (kvm_pmu_is_valid_msr(vcpu, msr))
2845 return kvm_pmu_set_msr(vcpu, msr_info);
2847 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2851 if (report_ignored_msrs)
2853 "ignored wrmsr: 0x%x data 0x%llx\n",
2860 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2862 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2865 u64 mcg_cap = vcpu->arch.mcg_cap;
2866 unsigned bank_num = mcg_cap & 0xff;
2869 case MSR_IA32_P5_MC_ADDR:
2870 case MSR_IA32_P5_MC_TYPE:
2873 case MSR_IA32_MCG_CAP:
2874 data = vcpu->arch.mcg_cap;
2876 case MSR_IA32_MCG_CTL:
2877 if (!(mcg_cap & MCG_CTL_P) && !host)
2879 data = vcpu->arch.mcg_ctl;
2881 case MSR_IA32_MCG_STATUS:
2882 data = vcpu->arch.mcg_status;
2885 if (msr >= MSR_IA32_MC0_CTL &&
2886 msr < MSR_IA32_MCx_CTL(bank_num)) {
2887 u32 offset = msr - MSR_IA32_MC0_CTL;
2888 data = vcpu->arch.mce_banks[offset];
2897 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2899 switch (msr_info->index) {
2900 case MSR_IA32_PLATFORM_ID:
2901 case MSR_IA32_EBL_CR_POWERON:
2902 case MSR_IA32_DEBUGCTLMSR:
2903 case MSR_IA32_LASTBRANCHFROMIP:
2904 case MSR_IA32_LASTBRANCHTOIP:
2905 case MSR_IA32_LASTINTFROMIP:
2906 case MSR_IA32_LASTINTTOIP:
2908 case MSR_K8_TSEG_ADDR:
2909 case MSR_K8_TSEG_MASK:
2910 case MSR_VM_HSAVE_PA:
2911 case MSR_K8_INT_PENDING_MSG:
2912 case MSR_AMD64_NB_CFG:
2913 case MSR_FAM10H_MMIO_CONF_BASE:
2914 case MSR_AMD64_BU_CFG2:
2915 case MSR_IA32_PERF_CTL:
2916 case MSR_AMD64_DC_CFG:
2917 case MSR_F15H_EX_CFG:
2920 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2921 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2922 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2923 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2924 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2925 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2926 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2929 case MSR_IA32_UCODE_REV:
2930 msr_info->data = vcpu->arch.microcode_version;
2932 case MSR_IA32_ARCH_CAPABILITIES:
2933 if (!msr_info->host_initiated &&
2934 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2936 msr_info->data = vcpu->arch.arch_capabilities;
2938 case MSR_IA32_POWER_CTL:
2939 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2942 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2945 case 0x200 ... 0x2ff:
2946 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2947 case 0xcd: /* fsb frequency */
2951 * MSR_EBC_FREQUENCY_ID
2952 * Conservative value valid for even the basic CPU models.
2953 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2954 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2955 * and 266MHz for model 3, or 4. Set Core Clock
2956 * Frequency to System Bus Frequency Ratio to 1 (bits
2957 * 31:24) even though these are only valid for CPU
2958 * models > 2, however guests may end up dividing or
2959 * multiplying by zero otherwise.
2961 case MSR_EBC_FREQUENCY_ID:
2962 msr_info->data = 1 << 24;
2964 case MSR_IA32_APICBASE:
2965 msr_info->data = kvm_get_apic_base(vcpu);
2967 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2968 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2970 case MSR_IA32_TSCDEADLINE:
2971 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2973 case MSR_IA32_TSC_ADJUST:
2974 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2976 case MSR_IA32_MISC_ENABLE:
2977 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2979 case MSR_IA32_SMBASE:
2980 if (!msr_info->host_initiated)
2982 msr_info->data = vcpu->arch.smbase;
2985 msr_info->data = vcpu->arch.smi_count;
2987 case MSR_IA32_PERF_STATUS:
2988 /* TSC increment by tick */
2989 msr_info->data = 1000ULL;
2990 /* CPU multiplier */
2991 msr_info->data |= (((uint64_t)4ULL) << 40);
2994 msr_info->data = vcpu->arch.efer;
2996 case MSR_KVM_WALL_CLOCK:
2997 case MSR_KVM_WALL_CLOCK_NEW:
2998 msr_info->data = vcpu->kvm->arch.wall_clock;
3000 case MSR_KVM_SYSTEM_TIME:
3001 case MSR_KVM_SYSTEM_TIME_NEW:
3002 msr_info->data = vcpu->arch.time;
3004 case MSR_KVM_ASYNC_PF_EN:
3005 msr_info->data = vcpu->arch.apf.msr_val;
3007 case MSR_KVM_STEAL_TIME:
3008 msr_info->data = vcpu->arch.st.msr_val;
3010 case MSR_KVM_PV_EOI_EN:
3011 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3013 case MSR_KVM_POLL_CONTROL:
3014 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3016 case MSR_IA32_P5_MC_ADDR:
3017 case MSR_IA32_P5_MC_TYPE:
3018 case MSR_IA32_MCG_CAP:
3019 case MSR_IA32_MCG_CTL:
3020 case MSR_IA32_MCG_STATUS:
3021 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3022 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3023 msr_info->host_initiated);
3024 case MSR_K7_CLK_CTL:
3026 * Provide expected ramp-up count for K7. All other
3027 * are set to zero, indicating minimum divisors for
3030 * This prevents guest kernels on AMD host with CPU
3031 * type 6, model 8 and higher from exploding due to
3032 * the rdmsr failing.
3034 msr_info->data = 0x20000000;
3036 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3037 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3038 case HV_X64_MSR_CRASH_CTL:
3039 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3040 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3041 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3042 case HV_X64_MSR_TSC_EMULATION_STATUS:
3043 return kvm_hv_get_msr_common(vcpu,
3044 msr_info->index, &msr_info->data,
3045 msr_info->host_initiated);
3047 case MSR_IA32_BBL_CR_CTL3:
3048 /* This legacy MSR exists but isn't fully documented in current
3049 * silicon. It is however accessed by winxp in very narrow
3050 * scenarios where it sets bit #19, itself documented as
3051 * a "reserved" bit. Best effort attempt to source coherent
3052 * read data here should the balance of the register be
3053 * interpreted by the guest:
3055 * L2 cache control register 3: 64GB range, 256KB size,
3056 * enabled, latency 0x1, configured
3058 msr_info->data = 0xbe702111;
3060 case MSR_AMD64_OSVW_ID_LENGTH:
3061 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3063 msr_info->data = vcpu->arch.osvw.length;
3065 case MSR_AMD64_OSVW_STATUS:
3066 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3068 msr_info->data = vcpu->arch.osvw.status;
3070 case MSR_PLATFORM_INFO:
3071 if (!msr_info->host_initiated &&
3072 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3074 msr_info->data = vcpu->arch.msr_platform_info;
3076 case MSR_MISC_FEATURES_ENABLES:
3077 msr_info->data = vcpu->arch.msr_misc_features_enables;
3080 msr_info->data = vcpu->arch.msr_hwcr;
3083 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3084 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3086 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3090 if (report_ignored_msrs)
3091 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3099 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3102 * Read or write a bunch of msrs. All parameters are kernel addresses.
3104 * @return number of msrs set successfully.
3106 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3107 struct kvm_msr_entry *entries,
3108 int (*do_msr)(struct kvm_vcpu *vcpu,
3109 unsigned index, u64 *data))
3113 for (i = 0; i < msrs->nmsrs; ++i)
3114 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3121 * Read or write a bunch of msrs. Parameters are user addresses.
3123 * @return number of msrs set successfully.
3125 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3126 int (*do_msr)(struct kvm_vcpu *vcpu,
3127 unsigned index, u64 *data),
3130 struct kvm_msrs msrs;
3131 struct kvm_msr_entry *entries;
3136 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3140 if (msrs.nmsrs >= MAX_IO_MSRS)
3143 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3144 entries = memdup_user(user_msrs->entries, size);
3145 if (IS_ERR(entries)) {
3146 r = PTR_ERR(entries);
3150 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3155 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3166 static inline bool kvm_can_mwait_in_guest(void)
3168 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3169 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3170 boot_cpu_has(X86_FEATURE_ARAT);
3173 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3178 case KVM_CAP_IRQCHIP:
3180 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3181 case KVM_CAP_SET_TSS_ADDR:
3182 case KVM_CAP_EXT_CPUID:
3183 case KVM_CAP_EXT_EMUL_CPUID:
3184 case KVM_CAP_CLOCKSOURCE:
3186 case KVM_CAP_NOP_IO_DELAY:
3187 case KVM_CAP_MP_STATE:
3188 case KVM_CAP_SYNC_MMU:
3189 case KVM_CAP_USER_NMI:
3190 case KVM_CAP_REINJECT_CONTROL:
3191 case KVM_CAP_IRQ_INJECT_STATUS:
3192 case KVM_CAP_IOEVENTFD:
3193 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3195 case KVM_CAP_PIT_STATE2:
3196 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3197 case KVM_CAP_XEN_HVM:
3198 case KVM_CAP_VCPU_EVENTS:
3199 case KVM_CAP_HYPERV:
3200 case KVM_CAP_HYPERV_VAPIC:
3201 case KVM_CAP_HYPERV_SPIN:
3202 case KVM_CAP_HYPERV_SYNIC:
3203 case KVM_CAP_HYPERV_SYNIC2:
3204 case KVM_CAP_HYPERV_VP_INDEX:
3205 case KVM_CAP_HYPERV_EVENTFD:
3206 case KVM_CAP_HYPERV_TLBFLUSH:
3207 case KVM_CAP_HYPERV_SEND_IPI:
3208 case KVM_CAP_HYPERV_CPUID:
3209 case KVM_CAP_PCI_SEGMENT:
3210 case KVM_CAP_DEBUGREGS:
3211 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3213 case KVM_CAP_ASYNC_PF:
3214 case KVM_CAP_GET_TSC_KHZ:
3215 case KVM_CAP_KVMCLOCK_CTRL:
3216 case KVM_CAP_READONLY_MEM:
3217 case KVM_CAP_HYPERV_TIME:
3218 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3219 case KVM_CAP_TSC_DEADLINE_TIMER:
3220 case KVM_CAP_DISABLE_QUIRKS:
3221 case KVM_CAP_SET_BOOT_CPU_ID:
3222 case KVM_CAP_SPLIT_IRQCHIP:
3223 case KVM_CAP_IMMEDIATE_EXIT:
3224 case KVM_CAP_PMU_EVENT_FILTER:
3225 case KVM_CAP_GET_MSR_FEATURES:
3226 case KVM_CAP_MSR_PLATFORM_INFO:
3227 case KVM_CAP_EXCEPTION_PAYLOAD:
3230 case KVM_CAP_SYNC_REGS:
3231 r = KVM_SYNC_X86_VALID_FIELDS;
3233 case KVM_CAP_ADJUST_CLOCK:
3234 r = KVM_CLOCK_TSC_STABLE;
3236 case KVM_CAP_X86_DISABLE_EXITS:
3237 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3238 KVM_X86_DISABLE_EXITS_CSTATE;
3239 if(kvm_can_mwait_in_guest())
3240 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3242 case KVM_CAP_X86_SMM:
3243 /* SMBASE is usually relocated above 1M on modern chipsets,
3244 * and SMM handlers might indeed rely on 4G segment limits,
3245 * so do not report SMM to be available if real mode is
3246 * emulated via vm86 mode. Still, do not go to great lengths
3247 * to avoid userspace's usage of the feature, because it is a
3248 * fringe case that is not enabled except via specific settings
3249 * of the module parameters.
3251 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3254 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3256 case KVM_CAP_NR_VCPUS:
3257 r = KVM_SOFT_MAX_VCPUS;
3259 case KVM_CAP_MAX_VCPUS:
3262 case KVM_CAP_MAX_VCPU_ID:
3263 r = KVM_MAX_VCPU_ID;
3265 case KVM_CAP_PV_MMU: /* obsolete */
3269 r = KVM_MAX_MCE_BANKS;
3272 r = boot_cpu_has(X86_FEATURE_XSAVE);
3274 case KVM_CAP_TSC_CONTROL:
3275 r = kvm_has_tsc_control;
3277 case KVM_CAP_X2APIC_API:
3278 r = KVM_X2APIC_API_VALID_FLAGS;
3280 case KVM_CAP_NESTED_STATE:
3281 r = kvm_x86_ops->get_nested_state ?
3282 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3284 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3285 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3287 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3288 r = kvm_x86_ops->nested_enable_evmcs != NULL;
3297 long kvm_arch_dev_ioctl(struct file *filp,
3298 unsigned int ioctl, unsigned long arg)
3300 void __user *argp = (void __user *)arg;
3304 case KVM_GET_MSR_INDEX_LIST: {
3305 struct kvm_msr_list __user *user_msr_list = argp;
3306 struct kvm_msr_list msr_list;
3310 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3313 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3314 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3317 if (n < msr_list.nmsrs)
3320 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3321 num_msrs_to_save * sizeof(u32)))
3323 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3325 num_emulated_msrs * sizeof(u32)))
3330 case KVM_GET_SUPPORTED_CPUID:
3331 case KVM_GET_EMULATED_CPUID: {
3332 struct kvm_cpuid2 __user *cpuid_arg = argp;
3333 struct kvm_cpuid2 cpuid;
3336 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3339 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3345 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3350 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3352 if (copy_to_user(argp, &kvm_mce_cap_supported,
3353 sizeof(kvm_mce_cap_supported)))
3357 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3358 struct kvm_msr_list __user *user_msr_list = argp;
3359 struct kvm_msr_list msr_list;
3363 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3366 msr_list.nmsrs = num_msr_based_features;
3367 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3370 if (n < msr_list.nmsrs)
3373 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3374 num_msr_based_features * sizeof(u32)))
3380 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3390 static void wbinvd_ipi(void *garbage)
3395 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3397 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3400 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3402 /* Address WBINVD may be executed by guest */
3403 if (need_emulate_wbinvd(vcpu)) {
3404 if (kvm_x86_ops->has_wbinvd_exit())
3405 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3406 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3407 smp_call_function_single(vcpu->cpu,
3408 wbinvd_ipi, NULL, 1);
3411 kvm_x86_ops->vcpu_load(vcpu, cpu);
3413 fpregs_assert_state_consistent();
3414 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3415 switch_fpu_return();
3417 /* Apply any externally detected TSC adjustments (due to suspend) */
3418 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3419 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3420 vcpu->arch.tsc_offset_adjustment = 0;
3421 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3424 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3425 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3426 rdtsc() - vcpu->arch.last_host_tsc;
3428 mark_tsc_unstable("KVM discovered backwards TSC");
3430 if (kvm_check_tsc_unstable()) {
3431 u64 offset = kvm_compute_tsc_offset(vcpu,
3432 vcpu->arch.last_guest_tsc);
3433 kvm_vcpu_write_tsc_offset(vcpu, offset);
3434 vcpu->arch.tsc_catchup = 1;
3437 if (kvm_lapic_hv_timer_in_use(vcpu))
3438 kvm_lapic_restart_hv_timer(vcpu);
3441 * On a host with synchronized TSC, there is no need to update
3442 * kvmclock on vcpu->cpu migration
3444 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3445 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3446 if (vcpu->cpu != cpu)
3447 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3451 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3454 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3456 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3459 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3461 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3462 &vcpu->arch.st.steal.preempted,
3463 offsetof(struct kvm_steal_time, preempted),
3464 sizeof(vcpu->arch.st.steal.preempted));
3467 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3471 if (vcpu->preempted)
3472 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3475 * Disable page faults because we're in atomic context here.
3476 * kvm_write_guest_offset_cached() would call might_fault()
3477 * that relies on pagefault_disable() to tell if there's a
3478 * bug. NOTE: the write to guest memory may not go through if
3479 * during postcopy live migration or if there's heavy guest
3482 pagefault_disable();
3484 * kvm_memslots() will be called by
3485 * kvm_write_guest_offset_cached() so take the srcu lock.
3487 idx = srcu_read_lock(&vcpu->kvm->srcu);
3488 kvm_steal_time_set_preempted(vcpu);
3489 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3491 kvm_x86_ops->vcpu_put(vcpu);
3492 vcpu->arch.last_host_tsc = rdtsc();
3494 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3495 * on every vmexit, but if not, we might have a stale dr6 from the
3496 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3501 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3502 struct kvm_lapic_state *s)
3504 if (vcpu->arch.apicv_active)
3505 kvm_x86_ops->sync_pir_to_irr(vcpu);
3507 return kvm_apic_get_state(vcpu, s);
3510 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3511 struct kvm_lapic_state *s)
3515 r = kvm_apic_set_state(vcpu, s);
3518 update_cr8_intercept(vcpu);
3523 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3525 return (!lapic_in_kernel(vcpu) ||
3526 kvm_apic_accept_pic_intr(vcpu));
3530 * if userspace requested an interrupt window, check that the
3531 * interrupt window is open.
3533 * No need to exit to userspace if we already have an interrupt queued.
3535 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3537 return kvm_arch_interrupt_allowed(vcpu) &&
3538 !kvm_cpu_has_interrupt(vcpu) &&
3539 !kvm_event_needs_reinjection(vcpu) &&
3540 kvm_cpu_accept_dm_intr(vcpu);
3543 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3544 struct kvm_interrupt *irq)
3546 if (irq->irq >= KVM_NR_INTERRUPTS)
3549 if (!irqchip_in_kernel(vcpu->kvm)) {
3550 kvm_queue_interrupt(vcpu, irq->irq, false);
3551 kvm_make_request(KVM_REQ_EVENT, vcpu);
3556 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3557 * fail for in-kernel 8259.
3559 if (pic_in_kernel(vcpu->kvm))
3562 if (vcpu->arch.pending_external_vector != -1)
3565 vcpu->arch.pending_external_vector = irq->irq;
3566 kvm_make_request(KVM_REQ_EVENT, vcpu);
3570 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3572 kvm_inject_nmi(vcpu);
3577 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3579 kvm_make_request(KVM_REQ_SMI, vcpu);
3584 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3585 struct kvm_tpr_access_ctl *tac)
3589 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3593 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3597 unsigned bank_num = mcg_cap & 0xff, bank;
3600 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3602 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3605 vcpu->arch.mcg_cap = mcg_cap;
3606 /* Init IA32_MCG_CTL to all 1s */
3607 if (mcg_cap & MCG_CTL_P)
3608 vcpu->arch.mcg_ctl = ~(u64)0;
3609 /* Init IA32_MCi_CTL to all 1s */
3610 for (bank = 0; bank < bank_num; bank++)
3611 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3613 kvm_x86_ops->setup_mce(vcpu);
3618 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3619 struct kvm_x86_mce *mce)
3621 u64 mcg_cap = vcpu->arch.mcg_cap;
3622 unsigned bank_num = mcg_cap & 0xff;
3623 u64 *banks = vcpu->arch.mce_banks;
3625 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3628 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3629 * reporting is disabled
3631 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3632 vcpu->arch.mcg_ctl != ~(u64)0)
3634 banks += 4 * mce->bank;
3636 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3637 * reporting is disabled for the bank
3639 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3641 if (mce->status & MCI_STATUS_UC) {
3642 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3643 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3644 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3647 if (banks[1] & MCI_STATUS_VAL)
3648 mce->status |= MCI_STATUS_OVER;
3649 banks[2] = mce->addr;
3650 banks[3] = mce->misc;
3651 vcpu->arch.mcg_status = mce->mcg_status;
3652 banks[1] = mce->status;
3653 kvm_queue_exception(vcpu, MC_VECTOR);
3654 } else if (!(banks[1] & MCI_STATUS_VAL)
3655 || !(banks[1] & MCI_STATUS_UC)) {
3656 if (banks[1] & MCI_STATUS_VAL)
3657 mce->status |= MCI_STATUS_OVER;
3658 banks[2] = mce->addr;
3659 banks[3] = mce->misc;
3660 banks[1] = mce->status;
3662 banks[1] |= MCI_STATUS_OVER;
3666 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3667 struct kvm_vcpu_events *events)
3672 * The API doesn't provide the instruction length for software
3673 * exceptions, so don't report them. As long as the guest RIP
3674 * isn't advanced, we should expect to encounter the exception
3677 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3678 events->exception.injected = 0;
3679 events->exception.pending = 0;
3681 events->exception.injected = vcpu->arch.exception.injected;
3682 events->exception.pending = vcpu->arch.exception.pending;
3684 * For ABI compatibility, deliberately conflate
3685 * pending and injected exceptions when
3686 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3688 if (!vcpu->kvm->arch.exception_payload_enabled)
3689 events->exception.injected |=
3690 vcpu->arch.exception.pending;
3692 events->exception.nr = vcpu->arch.exception.nr;
3693 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3694 events->exception.error_code = vcpu->arch.exception.error_code;
3695 events->exception_has_payload = vcpu->arch.exception.has_payload;
3696 events->exception_payload = vcpu->arch.exception.payload;
3698 events->interrupt.injected =
3699 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3700 events->interrupt.nr = vcpu->arch.interrupt.nr;
3701 events->interrupt.soft = 0;
3702 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3704 events->nmi.injected = vcpu->arch.nmi_injected;
3705 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3706 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3707 events->nmi.pad = 0;
3709 events->sipi_vector = 0; /* never valid when reporting to user space */
3711 events->smi.smm = is_smm(vcpu);
3712 events->smi.pending = vcpu->arch.smi_pending;
3713 events->smi.smm_inside_nmi =
3714 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3715 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3717 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3718 | KVM_VCPUEVENT_VALID_SHADOW
3719 | KVM_VCPUEVENT_VALID_SMM);
3720 if (vcpu->kvm->arch.exception_payload_enabled)
3721 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3723 memset(&events->reserved, 0, sizeof(events->reserved));
3726 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3728 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3729 struct kvm_vcpu_events *events)
3731 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3732 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3733 | KVM_VCPUEVENT_VALID_SHADOW
3734 | KVM_VCPUEVENT_VALID_SMM
3735 | KVM_VCPUEVENT_VALID_PAYLOAD))
3738 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3739 if (!vcpu->kvm->arch.exception_payload_enabled)
3741 if (events->exception.pending)
3742 events->exception.injected = 0;
3744 events->exception_has_payload = 0;
3746 events->exception.pending = 0;
3747 events->exception_has_payload = 0;
3750 if ((events->exception.injected || events->exception.pending) &&
3751 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3754 /* INITs are latched while in SMM */
3755 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3756 (events->smi.smm || events->smi.pending) &&
3757 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3761 vcpu->arch.exception.injected = events->exception.injected;
3762 vcpu->arch.exception.pending = events->exception.pending;
3763 vcpu->arch.exception.nr = events->exception.nr;
3764 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3765 vcpu->arch.exception.error_code = events->exception.error_code;
3766 vcpu->arch.exception.has_payload = events->exception_has_payload;
3767 vcpu->arch.exception.payload = events->exception_payload;
3769 vcpu->arch.interrupt.injected = events->interrupt.injected;
3770 vcpu->arch.interrupt.nr = events->interrupt.nr;
3771 vcpu->arch.interrupt.soft = events->interrupt.soft;
3772 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3773 kvm_x86_ops->set_interrupt_shadow(vcpu,
3774 events->interrupt.shadow);
3776 vcpu->arch.nmi_injected = events->nmi.injected;
3777 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3778 vcpu->arch.nmi_pending = events->nmi.pending;
3779 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3781 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3782 lapic_in_kernel(vcpu))
3783 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3785 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3786 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3787 if (events->smi.smm)
3788 vcpu->arch.hflags |= HF_SMM_MASK;
3790 vcpu->arch.hflags &= ~HF_SMM_MASK;
3791 kvm_smm_changed(vcpu);
3794 vcpu->arch.smi_pending = events->smi.pending;
3796 if (events->smi.smm) {
3797 if (events->smi.smm_inside_nmi)
3798 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3800 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3801 if (lapic_in_kernel(vcpu)) {
3802 if (events->smi.latched_init)
3803 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3805 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3810 kvm_make_request(KVM_REQ_EVENT, vcpu);
3815 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3816 struct kvm_debugregs *dbgregs)
3820 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3821 kvm_get_dr(vcpu, 6, &val);
3823 dbgregs->dr7 = vcpu->arch.dr7;
3825 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3828 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3829 struct kvm_debugregs *dbgregs)
3834 if (dbgregs->dr6 & ~0xffffffffull)
3836 if (dbgregs->dr7 & ~0xffffffffull)
3839 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3840 kvm_update_dr0123(vcpu);
3841 vcpu->arch.dr6 = dbgregs->dr6;
3842 kvm_update_dr6(vcpu);
3843 vcpu->arch.dr7 = dbgregs->dr7;
3844 kvm_update_dr7(vcpu);
3849 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3851 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3853 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3854 u64 xstate_bv = xsave->header.xfeatures;
3858 * Copy legacy XSAVE area, to avoid complications with CPUID
3859 * leaves 0 and 1 in the loop below.
3861 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3864 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
3865 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3868 * Copy each region from the possibly compacted offset to the
3869 * non-compacted offset.
3871 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3873 u64 xfeature_mask = valid & -valid;
3874 int xfeature_nr = fls64(xfeature_mask) - 1;
3875 void *src = get_xsave_addr(xsave, xfeature_nr);
3878 u32 size, offset, ecx, edx;
3879 cpuid_count(XSTATE_CPUID, xfeature_nr,
3880 &size, &offset, &ecx, &edx);
3881 if (xfeature_nr == XFEATURE_PKRU)
3882 memcpy(dest + offset, &vcpu->arch.pkru,
3883 sizeof(vcpu->arch.pkru));
3885 memcpy(dest + offset, src, size);
3889 valid -= xfeature_mask;
3893 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3895 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
3896 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3900 * Copy legacy XSAVE area, to avoid complications with CPUID
3901 * leaves 0 and 1 in the loop below.
3903 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3905 /* Set XSTATE_BV and possibly XCOMP_BV. */
3906 xsave->header.xfeatures = xstate_bv;
3907 if (boot_cpu_has(X86_FEATURE_XSAVES))
3908 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3911 * Copy each region from the non-compacted offset to the
3912 * possibly compacted offset.
3914 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3916 u64 xfeature_mask = valid & -valid;
3917 int xfeature_nr = fls64(xfeature_mask) - 1;
3918 void *dest = get_xsave_addr(xsave, xfeature_nr);
3921 u32 size, offset, ecx, edx;
3922 cpuid_count(XSTATE_CPUID, xfeature_nr,
3923 &size, &offset, &ecx, &edx);
3924 if (xfeature_nr == XFEATURE_PKRU)
3925 memcpy(&vcpu->arch.pkru, src + offset,
3926 sizeof(vcpu->arch.pkru));
3928 memcpy(dest, src + offset, size);
3931 valid -= xfeature_mask;
3935 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3936 struct kvm_xsave *guest_xsave)
3938 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3939 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3940 fill_xsave((u8 *) guest_xsave->region, vcpu);
3942 memcpy(guest_xsave->region,
3943 &vcpu->arch.guest_fpu->state.fxsave,
3944 sizeof(struct fxregs_state));
3945 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3946 XFEATURE_MASK_FPSSE;
3950 #define XSAVE_MXCSR_OFFSET 24
3952 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3953 struct kvm_xsave *guest_xsave)
3956 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3957 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
3959 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
3961 * Here we allow setting states that are not present in
3962 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3963 * with old userspace.
3965 if (xstate_bv & ~kvm_supported_xcr0() ||
3966 mxcsr & ~mxcsr_feature_mask)
3968 load_xsave(vcpu, (u8 *)guest_xsave->region);
3970 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3971 mxcsr & ~mxcsr_feature_mask)
3973 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
3974 guest_xsave->region, sizeof(struct fxregs_state));
3979 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3980 struct kvm_xcrs *guest_xcrs)
3982 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
3983 guest_xcrs->nr_xcrs = 0;
3987 guest_xcrs->nr_xcrs = 1;
3988 guest_xcrs->flags = 0;
3989 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3990 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3993 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3994 struct kvm_xcrs *guest_xcrs)
3998 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4001 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4004 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4005 /* Only support XCR0 currently */
4006 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4007 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4008 guest_xcrs->xcrs[i].value);
4017 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4018 * stopped by the hypervisor. This function will be called from the host only.
4019 * EINVAL is returned when the host attempts to set the flag for a guest that
4020 * does not support pv clocks.
4022 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4024 if (!vcpu->arch.pv_time_enabled)
4026 vcpu->arch.pvclock_set_guest_stopped_request = true;
4027 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4031 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4032 struct kvm_enable_cap *cap)
4035 uint16_t vmcs_version;
4036 void __user *user_ptr;
4042 case KVM_CAP_HYPERV_SYNIC2:
4047 case KVM_CAP_HYPERV_SYNIC:
4048 if (!irqchip_in_kernel(vcpu->kvm))
4050 return kvm_hv_activate_synic(vcpu, cap->cap ==
4051 KVM_CAP_HYPERV_SYNIC2);
4052 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4053 if (!kvm_x86_ops->nested_enable_evmcs)
4055 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4057 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4058 if (copy_to_user(user_ptr, &vmcs_version,
4059 sizeof(vmcs_version)))
4063 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4064 if (!kvm_x86_ops->enable_direct_tlbflush)
4067 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
4074 long kvm_arch_vcpu_ioctl(struct file *filp,
4075 unsigned int ioctl, unsigned long arg)
4077 struct kvm_vcpu *vcpu = filp->private_data;
4078 void __user *argp = (void __user *)arg;
4081 struct kvm_lapic_state *lapic;
4082 struct kvm_xsave *xsave;
4083 struct kvm_xcrs *xcrs;
4091 case KVM_GET_LAPIC: {
4093 if (!lapic_in_kernel(vcpu))
4095 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4096 GFP_KERNEL_ACCOUNT);
4101 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4105 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4110 case KVM_SET_LAPIC: {
4112 if (!lapic_in_kernel(vcpu))
4114 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4115 if (IS_ERR(u.lapic)) {
4116 r = PTR_ERR(u.lapic);
4120 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4123 case KVM_INTERRUPT: {
4124 struct kvm_interrupt irq;
4127 if (copy_from_user(&irq, argp, sizeof(irq)))
4129 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4133 r = kvm_vcpu_ioctl_nmi(vcpu);
4137 r = kvm_vcpu_ioctl_smi(vcpu);
4140 case KVM_SET_CPUID: {
4141 struct kvm_cpuid __user *cpuid_arg = argp;
4142 struct kvm_cpuid cpuid;
4145 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4147 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4150 case KVM_SET_CPUID2: {
4151 struct kvm_cpuid2 __user *cpuid_arg = argp;
4152 struct kvm_cpuid2 cpuid;
4155 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4157 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4158 cpuid_arg->entries);
4161 case KVM_GET_CPUID2: {
4162 struct kvm_cpuid2 __user *cpuid_arg = argp;
4163 struct kvm_cpuid2 cpuid;
4166 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4168 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4169 cpuid_arg->entries);
4173 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4178 case KVM_GET_MSRS: {
4179 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4180 r = msr_io(vcpu, argp, do_get_msr, 1);
4181 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4184 case KVM_SET_MSRS: {
4185 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4186 r = msr_io(vcpu, argp, do_set_msr, 0);
4187 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4190 case KVM_TPR_ACCESS_REPORTING: {
4191 struct kvm_tpr_access_ctl tac;
4194 if (copy_from_user(&tac, argp, sizeof(tac)))
4196 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4200 if (copy_to_user(argp, &tac, sizeof(tac)))
4205 case KVM_SET_VAPIC_ADDR: {
4206 struct kvm_vapic_addr va;
4210 if (!lapic_in_kernel(vcpu))
4213 if (copy_from_user(&va, argp, sizeof(va)))
4215 idx = srcu_read_lock(&vcpu->kvm->srcu);
4216 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4217 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4220 case KVM_X86_SETUP_MCE: {
4224 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4226 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4229 case KVM_X86_SET_MCE: {
4230 struct kvm_x86_mce mce;
4233 if (copy_from_user(&mce, argp, sizeof(mce)))
4235 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4238 case KVM_GET_VCPU_EVENTS: {
4239 struct kvm_vcpu_events events;
4241 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4244 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4249 case KVM_SET_VCPU_EVENTS: {
4250 struct kvm_vcpu_events events;
4253 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4256 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4259 case KVM_GET_DEBUGREGS: {
4260 struct kvm_debugregs dbgregs;
4262 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4265 if (copy_to_user(argp, &dbgregs,
4266 sizeof(struct kvm_debugregs)))
4271 case KVM_SET_DEBUGREGS: {
4272 struct kvm_debugregs dbgregs;
4275 if (copy_from_user(&dbgregs, argp,
4276 sizeof(struct kvm_debugregs)))
4279 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4282 case KVM_GET_XSAVE: {
4283 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4288 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4291 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4296 case KVM_SET_XSAVE: {
4297 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4298 if (IS_ERR(u.xsave)) {
4299 r = PTR_ERR(u.xsave);
4303 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4306 case KVM_GET_XCRS: {
4307 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4312 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4315 if (copy_to_user(argp, u.xcrs,
4316 sizeof(struct kvm_xcrs)))
4321 case KVM_SET_XCRS: {
4322 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4323 if (IS_ERR(u.xcrs)) {
4324 r = PTR_ERR(u.xcrs);
4328 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4331 case KVM_SET_TSC_KHZ: {
4335 user_tsc_khz = (u32)arg;
4337 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4340 if (user_tsc_khz == 0)
4341 user_tsc_khz = tsc_khz;
4343 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4348 case KVM_GET_TSC_KHZ: {
4349 r = vcpu->arch.virtual_tsc_khz;
4352 case KVM_KVMCLOCK_CTRL: {
4353 r = kvm_set_guest_paused(vcpu);
4356 case KVM_ENABLE_CAP: {
4357 struct kvm_enable_cap cap;
4360 if (copy_from_user(&cap, argp, sizeof(cap)))
4362 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4365 case KVM_GET_NESTED_STATE: {
4366 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4370 if (!kvm_x86_ops->get_nested_state)
4373 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4375 if (get_user(user_data_size, &user_kvm_nested_state->size))
4378 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4383 if (r > user_data_size) {
4384 if (put_user(r, &user_kvm_nested_state->size))
4394 case KVM_SET_NESTED_STATE: {
4395 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4396 struct kvm_nested_state kvm_state;
4399 if (!kvm_x86_ops->set_nested_state)
4403 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4407 if (kvm_state.size < sizeof(kvm_state))
4410 if (kvm_state.flags &
4411 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4412 | KVM_STATE_NESTED_EVMCS))
4415 /* nested_run_pending implies guest_mode. */
4416 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4417 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4420 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4423 case KVM_GET_SUPPORTED_HV_CPUID: {
4424 struct kvm_cpuid2 __user *cpuid_arg = argp;
4425 struct kvm_cpuid2 cpuid;
4428 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4431 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4432 cpuid_arg->entries);
4437 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4452 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4454 return VM_FAULT_SIGBUS;
4457 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4461 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4463 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4467 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4470 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4473 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4474 unsigned long kvm_nr_mmu_pages)
4476 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4479 mutex_lock(&kvm->slots_lock);
4481 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4482 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4484 mutex_unlock(&kvm->slots_lock);
4488 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4490 return kvm->arch.n_max_mmu_pages;
4493 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4495 struct kvm_pic *pic = kvm->arch.vpic;
4499 switch (chip->chip_id) {
4500 case KVM_IRQCHIP_PIC_MASTER:
4501 memcpy(&chip->chip.pic, &pic->pics[0],
4502 sizeof(struct kvm_pic_state));
4504 case KVM_IRQCHIP_PIC_SLAVE:
4505 memcpy(&chip->chip.pic, &pic->pics[1],
4506 sizeof(struct kvm_pic_state));
4508 case KVM_IRQCHIP_IOAPIC:
4509 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4518 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4520 struct kvm_pic *pic = kvm->arch.vpic;
4524 switch (chip->chip_id) {
4525 case KVM_IRQCHIP_PIC_MASTER:
4526 spin_lock(&pic->lock);
4527 memcpy(&pic->pics[0], &chip->chip.pic,
4528 sizeof(struct kvm_pic_state));
4529 spin_unlock(&pic->lock);
4531 case KVM_IRQCHIP_PIC_SLAVE:
4532 spin_lock(&pic->lock);
4533 memcpy(&pic->pics[1], &chip->chip.pic,
4534 sizeof(struct kvm_pic_state));
4535 spin_unlock(&pic->lock);
4537 case KVM_IRQCHIP_IOAPIC:
4538 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4544 kvm_pic_update_irq(pic);
4548 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4550 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4552 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4554 mutex_lock(&kps->lock);
4555 memcpy(ps, &kps->channels, sizeof(*ps));
4556 mutex_unlock(&kps->lock);
4560 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4563 struct kvm_pit *pit = kvm->arch.vpit;
4565 mutex_lock(&pit->pit_state.lock);
4566 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4567 for (i = 0; i < 3; i++)
4568 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4569 mutex_unlock(&pit->pit_state.lock);
4573 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4575 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4576 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4577 sizeof(ps->channels));
4578 ps->flags = kvm->arch.vpit->pit_state.flags;
4579 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4580 memset(&ps->reserved, 0, sizeof(ps->reserved));
4584 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4588 u32 prev_legacy, cur_legacy;
4589 struct kvm_pit *pit = kvm->arch.vpit;
4591 mutex_lock(&pit->pit_state.lock);
4592 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4593 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4594 if (!prev_legacy && cur_legacy)
4596 memcpy(&pit->pit_state.channels, &ps->channels,
4597 sizeof(pit->pit_state.channels));
4598 pit->pit_state.flags = ps->flags;
4599 for (i = 0; i < 3; i++)
4600 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4602 mutex_unlock(&pit->pit_state.lock);
4606 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4607 struct kvm_reinject_control *control)
4609 struct kvm_pit *pit = kvm->arch.vpit;
4614 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4615 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4616 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4618 mutex_lock(&pit->pit_state.lock);
4619 kvm_pit_set_reinject(pit, control->pit_reinject);
4620 mutex_unlock(&pit->pit_state.lock);
4626 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4627 * @kvm: kvm instance
4628 * @log: slot id and address to which we copy the log
4630 * Steps 1-4 below provide general overview of dirty page logging. See
4631 * kvm_get_dirty_log_protect() function description for additional details.
4633 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4634 * always flush the TLB (step 4) even if previous step failed and the dirty
4635 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4636 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4637 * writes will be marked dirty for next log read.
4639 * 1. Take a snapshot of the bit and clear it if needed.
4640 * 2. Write protect the corresponding page.
4641 * 3. Copy the snapshot to the userspace.
4642 * 4. Flush TLB's if needed.
4644 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
4649 mutex_lock(&kvm->slots_lock);
4652 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4654 if (kvm_x86_ops->flush_log_dirty)
4655 kvm_x86_ops->flush_log_dirty(kvm);
4657 r = kvm_get_dirty_log_protect(kvm, log, &flush);
4660 * All the TLBs can be flushed out of mmu lock, see the comments in
4661 * kvm_mmu_slot_remove_write_access().
4663 lockdep_assert_held(&kvm->slots_lock);
4665 kvm_flush_remote_tlbs(kvm);
4667 mutex_unlock(&kvm->slots_lock);
4671 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4676 mutex_lock(&kvm->slots_lock);
4679 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4681 if (kvm_x86_ops->flush_log_dirty)
4682 kvm_x86_ops->flush_log_dirty(kvm);
4684 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4687 * All the TLBs can be flushed out of mmu lock, see the comments in
4688 * kvm_mmu_slot_remove_write_access().
4690 lockdep_assert_held(&kvm->slots_lock);
4692 kvm_flush_remote_tlbs(kvm);
4694 mutex_unlock(&kvm->slots_lock);
4698 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4701 if (!irqchip_in_kernel(kvm))
4704 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4705 irq_event->irq, irq_event->level,
4710 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4711 struct kvm_enable_cap *cap)
4719 case KVM_CAP_DISABLE_QUIRKS:
4720 kvm->arch.disabled_quirks = cap->args[0];
4723 case KVM_CAP_SPLIT_IRQCHIP: {
4724 mutex_lock(&kvm->lock);
4726 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4727 goto split_irqchip_unlock;
4729 if (irqchip_in_kernel(kvm))
4730 goto split_irqchip_unlock;
4731 if (kvm->created_vcpus)
4732 goto split_irqchip_unlock;
4733 r = kvm_setup_empty_irq_routing(kvm);
4735 goto split_irqchip_unlock;
4736 /* Pairs with irqchip_in_kernel. */
4738 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4739 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4741 split_irqchip_unlock:
4742 mutex_unlock(&kvm->lock);
4745 case KVM_CAP_X2APIC_API:
4747 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4750 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4751 kvm->arch.x2apic_format = true;
4752 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4753 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4757 case KVM_CAP_X86_DISABLE_EXITS:
4759 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4762 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4763 kvm_can_mwait_in_guest())
4764 kvm->arch.mwait_in_guest = true;
4765 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4766 kvm->arch.hlt_in_guest = true;
4767 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4768 kvm->arch.pause_in_guest = true;
4769 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4770 kvm->arch.cstate_in_guest = true;
4773 case KVM_CAP_MSR_PLATFORM_INFO:
4774 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4777 case KVM_CAP_EXCEPTION_PAYLOAD:
4778 kvm->arch.exception_payload_enabled = cap->args[0];
4788 long kvm_arch_vm_ioctl(struct file *filp,
4789 unsigned int ioctl, unsigned long arg)
4791 struct kvm *kvm = filp->private_data;
4792 void __user *argp = (void __user *)arg;
4795 * This union makes it completely explicit to gcc-3.x
4796 * that these two variables' stack usage should be
4797 * combined, not added together.
4800 struct kvm_pit_state ps;
4801 struct kvm_pit_state2 ps2;
4802 struct kvm_pit_config pit_config;
4806 case KVM_SET_TSS_ADDR:
4807 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4809 case KVM_SET_IDENTITY_MAP_ADDR: {
4812 mutex_lock(&kvm->lock);
4814 if (kvm->created_vcpus)
4815 goto set_identity_unlock;
4817 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4818 goto set_identity_unlock;
4819 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4820 set_identity_unlock:
4821 mutex_unlock(&kvm->lock);
4824 case KVM_SET_NR_MMU_PAGES:
4825 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4827 case KVM_GET_NR_MMU_PAGES:
4828 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4830 case KVM_CREATE_IRQCHIP: {
4831 mutex_lock(&kvm->lock);
4834 if (irqchip_in_kernel(kvm))
4835 goto create_irqchip_unlock;
4838 if (kvm->created_vcpus)
4839 goto create_irqchip_unlock;
4841 r = kvm_pic_init(kvm);
4843 goto create_irqchip_unlock;
4845 r = kvm_ioapic_init(kvm);
4847 kvm_pic_destroy(kvm);
4848 goto create_irqchip_unlock;
4851 r = kvm_setup_default_irq_routing(kvm);
4853 kvm_ioapic_destroy(kvm);
4854 kvm_pic_destroy(kvm);
4855 goto create_irqchip_unlock;
4857 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4859 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4860 create_irqchip_unlock:
4861 mutex_unlock(&kvm->lock);
4864 case KVM_CREATE_PIT:
4865 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4867 case KVM_CREATE_PIT2:
4869 if (copy_from_user(&u.pit_config, argp,
4870 sizeof(struct kvm_pit_config)))
4873 mutex_lock(&kvm->lock);
4876 goto create_pit_unlock;
4878 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4882 mutex_unlock(&kvm->lock);
4884 case KVM_GET_IRQCHIP: {
4885 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4886 struct kvm_irqchip *chip;
4888 chip = memdup_user(argp, sizeof(*chip));
4895 if (!irqchip_kernel(kvm))
4896 goto get_irqchip_out;
4897 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4899 goto get_irqchip_out;
4901 if (copy_to_user(argp, chip, sizeof(*chip)))
4902 goto get_irqchip_out;
4908 case KVM_SET_IRQCHIP: {
4909 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4910 struct kvm_irqchip *chip;
4912 chip = memdup_user(argp, sizeof(*chip));
4919 if (!irqchip_kernel(kvm))
4920 goto set_irqchip_out;
4921 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
4923 goto set_irqchip_out;
4931 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
4934 if (!kvm->arch.vpit)
4936 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
4940 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
4947 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
4950 if (!kvm->arch.vpit)
4952 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
4955 case KVM_GET_PIT2: {
4957 if (!kvm->arch.vpit)
4959 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4963 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4968 case KVM_SET_PIT2: {
4970 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4973 if (!kvm->arch.vpit)
4975 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4978 case KVM_REINJECT_CONTROL: {
4979 struct kvm_reinject_control control;
4981 if (copy_from_user(&control, argp, sizeof(control)))
4983 r = kvm_vm_ioctl_reinject(kvm, &control);
4986 case KVM_SET_BOOT_CPU_ID:
4988 mutex_lock(&kvm->lock);
4989 if (kvm->created_vcpus)
4992 kvm->arch.bsp_vcpu_id = arg;
4993 mutex_unlock(&kvm->lock);
4995 case KVM_XEN_HVM_CONFIG: {
4996 struct kvm_xen_hvm_config xhc;
4998 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5003 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5007 case KVM_SET_CLOCK: {
5008 struct kvm_clock_data user_ns;
5012 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5021 * TODO: userspace has to take care of races with VCPU_RUN, so
5022 * kvm_gen_update_masterclock() can be cut down to locked
5023 * pvclock_update_vm_gtod_copy().
5025 kvm_gen_update_masterclock(kvm);
5026 now_ns = get_kvmclock_ns(kvm);
5027 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5028 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5031 case KVM_GET_CLOCK: {
5032 struct kvm_clock_data user_ns;
5035 now_ns = get_kvmclock_ns(kvm);
5036 user_ns.clock = now_ns;
5037 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5038 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5041 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5046 case KVM_MEMORY_ENCRYPT_OP: {
5048 if (kvm_x86_ops->mem_enc_op)
5049 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5052 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5053 struct kvm_enc_region region;
5056 if (copy_from_user(®ion, argp, sizeof(region)))
5060 if (kvm_x86_ops->mem_enc_reg_region)
5061 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion);
5064 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5065 struct kvm_enc_region region;
5068 if (copy_from_user(®ion, argp, sizeof(region)))
5072 if (kvm_x86_ops->mem_enc_unreg_region)
5073 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion);
5076 case KVM_HYPERV_EVENTFD: {
5077 struct kvm_hyperv_eventfd hvevfd;
5080 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5082 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5085 case KVM_SET_PMU_EVENT_FILTER:
5086 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5095 static void kvm_init_msr_list(void)
5100 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5101 "Please update the fixed PMCs in msrs_to_save[]");
5102 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_GENERIC != 32,
5103 "Please update the generic perfctr/eventsel MSRs in msrs_to_save[]");
5105 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
5106 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
5110 * Even MSRs that are valid in the host may not be exposed
5111 * to the guests in some cases.
5113 switch (msrs_to_save[i]) {
5114 case MSR_IA32_BNDCFGS:
5115 if (!kvm_mpx_supported())
5119 if (!kvm_x86_ops->rdtscp_supported())
5122 case MSR_IA32_RTIT_CTL:
5123 case MSR_IA32_RTIT_STATUS:
5124 if (!kvm_x86_ops->pt_supported())
5127 case MSR_IA32_RTIT_CR3_MATCH:
5128 if (!kvm_x86_ops->pt_supported() ||
5129 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5132 case MSR_IA32_RTIT_OUTPUT_BASE:
5133 case MSR_IA32_RTIT_OUTPUT_MASK:
5134 if (!kvm_x86_ops->pt_supported() ||
5135 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5136 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5139 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5140 if (!kvm_x86_ops->pt_supported() ||
5141 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5142 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5151 msrs_to_save[j] = msrs_to_save[i];
5154 num_msrs_to_save = j;
5156 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
5157 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5161 emulated_msrs[j] = emulated_msrs[i];
5164 num_emulated_msrs = j;
5166 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5167 struct kvm_msr_entry msr;
5169 msr.index = msr_based_features[i];
5170 if (kvm_get_msr_feature(&msr))
5174 msr_based_features[j] = msr_based_features[i];
5177 num_msr_based_features = j;
5180 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5188 if (!(lapic_in_kernel(vcpu) &&
5189 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5190 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5201 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5208 if (!(lapic_in_kernel(vcpu) &&
5209 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5211 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5213 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5223 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5224 struct kvm_segment *var, int seg)
5226 kvm_x86_ops->set_segment(vcpu, var, seg);
5229 void kvm_get_segment(struct kvm_vcpu *vcpu,
5230 struct kvm_segment *var, int seg)
5232 kvm_x86_ops->get_segment(vcpu, var, seg);
5235 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5236 struct x86_exception *exception)
5240 BUG_ON(!mmu_is_nested(vcpu));
5242 /* NPT walks are always user-walks */
5243 access |= PFERR_USER_MASK;
5244 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5249 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5250 struct x86_exception *exception)
5252 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5253 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5256 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5257 struct x86_exception *exception)
5259 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5260 access |= PFERR_FETCH_MASK;
5261 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5264 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5265 struct x86_exception *exception)
5267 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5268 access |= PFERR_WRITE_MASK;
5269 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5272 /* uses this to access any guest's mapped memory without checking CPL */
5273 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5274 struct x86_exception *exception)
5276 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5279 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5280 struct kvm_vcpu *vcpu, u32 access,
5281 struct x86_exception *exception)
5284 int r = X86EMUL_CONTINUE;
5287 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5289 unsigned offset = addr & (PAGE_SIZE-1);
5290 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5293 if (gpa == UNMAPPED_GVA)
5294 return X86EMUL_PROPAGATE_FAULT;
5295 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5298 r = X86EMUL_IO_NEEDED;
5310 /* used for instruction fetching */
5311 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5312 gva_t addr, void *val, unsigned int bytes,
5313 struct x86_exception *exception)
5315 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5316 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5320 /* Inline kvm_read_guest_virt_helper for speed. */
5321 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5323 if (unlikely(gpa == UNMAPPED_GVA))
5324 return X86EMUL_PROPAGATE_FAULT;
5326 offset = addr & (PAGE_SIZE-1);
5327 if (WARN_ON(offset + bytes > PAGE_SIZE))
5328 bytes = (unsigned)PAGE_SIZE - offset;
5329 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5331 if (unlikely(ret < 0))
5332 return X86EMUL_IO_NEEDED;
5334 return X86EMUL_CONTINUE;
5337 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5338 gva_t addr, void *val, unsigned int bytes,
5339 struct x86_exception *exception)
5341 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5344 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5345 * is returned, but our callers are not ready for that and they blindly
5346 * call kvm_inject_page_fault. Ensure that they at least do not leak
5347 * uninitialized kernel stack memory into cr2 and error code.
5349 memset(exception, 0, sizeof(*exception));
5350 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5353 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5355 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5356 gva_t addr, void *val, unsigned int bytes,
5357 struct x86_exception *exception, bool system)
5359 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5362 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5363 access |= PFERR_USER_MASK;
5365 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5368 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5369 unsigned long addr, void *val, unsigned int bytes)
5371 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5372 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5374 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5377 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5378 struct kvm_vcpu *vcpu, u32 access,
5379 struct x86_exception *exception)
5382 int r = X86EMUL_CONTINUE;
5385 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5388 unsigned offset = addr & (PAGE_SIZE-1);
5389 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5392 if (gpa == UNMAPPED_GVA)
5393 return X86EMUL_PROPAGATE_FAULT;
5394 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5396 r = X86EMUL_IO_NEEDED;
5408 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5409 unsigned int bytes, struct x86_exception *exception,
5412 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5413 u32 access = PFERR_WRITE_MASK;
5415 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5416 access |= PFERR_USER_MASK;
5418 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5422 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5423 unsigned int bytes, struct x86_exception *exception)
5425 /* kvm_write_guest_virt_system can pull in tons of pages. */
5426 vcpu->arch.l1tf_flush_l1d = true;
5429 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5430 * is returned, but our callers are not ready for that and they blindly
5431 * call kvm_inject_page_fault. Ensure that they at least do not leak
5432 * uninitialized kernel stack memory into cr2 and error code.
5434 memset(exception, 0, sizeof(*exception));
5435 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5436 PFERR_WRITE_MASK, exception);
5438 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5440 int handle_ud(struct kvm_vcpu *vcpu)
5442 int emul_type = EMULTYPE_TRAP_UD;
5443 char sig[5]; /* ud2; .ascii "kvm" */
5444 struct x86_exception e;
5446 if (force_emulation_prefix &&
5447 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5448 sig, sizeof(sig), &e) == 0 &&
5449 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5450 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5451 emul_type = EMULTYPE_TRAP_UD_FORCED;
5454 return kvm_emulate_instruction(vcpu, emul_type) != EMULATE_USER_EXIT;
5456 EXPORT_SYMBOL_GPL(handle_ud);
5458 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5459 gpa_t gpa, bool write)
5461 /* For APIC access vmexit */
5462 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5465 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5466 trace_vcpu_match_mmio(gva, gpa, write, true);
5473 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5474 gpa_t *gpa, struct x86_exception *exception,
5477 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5478 | (write ? PFERR_WRITE_MASK : 0);
5481 * currently PKRU is only applied to ept enabled guest so
5482 * there is no pkey in EPT page table for L1 guest or EPT
5483 * shadow page table for L2 guest.
5485 if (vcpu_match_mmio_gva(vcpu, gva)
5486 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5487 vcpu->arch.mmio_access, 0, access)) {
5488 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5489 (gva & (PAGE_SIZE - 1));
5490 trace_vcpu_match_mmio(gva, *gpa, write, false);
5494 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5496 if (*gpa == UNMAPPED_GVA)
5499 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5502 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5503 const void *val, int bytes)
5507 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5510 kvm_page_track_write(vcpu, gpa, val, bytes);
5514 struct read_write_emulator_ops {
5515 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5517 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5518 void *val, int bytes);
5519 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5520 int bytes, void *val);
5521 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5522 void *val, int bytes);
5526 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5528 if (vcpu->mmio_read_completed) {
5529 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5530 vcpu->mmio_fragments[0].gpa, val);
5531 vcpu->mmio_read_completed = 0;
5538 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5539 void *val, int bytes)
5541 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5544 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5545 void *val, int bytes)
5547 return emulator_write_phys(vcpu, gpa, val, bytes);
5550 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5552 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5553 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5556 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5557 void *val, int bytes)
5559 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5560 return X86EMUL_IO_NEEDED;
5563 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5564 void *val, int bytes)
5566 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5568 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5569 return X86EMUL_CONTINUE;
5572 static const struct read_write_emulator_ops read_emultor = {
5573 .read_write_prepare = read_prepare,
5574 .read_write_emulate = read_emulate,
5575 .read_write_mmio = vcpu_mmio_read,
5576 .read_write_exit_mmio = read_exit_mmio,
5579 static const struct read_write_emulator_ops write_emultor = {
5580 .read_write_emulate = write_emulate,
5581 .read_write_mmio = write_mmio,
5582 .read_write_exit_mmio = write_exit_mmio,
5586 static int emulator_read_write_onepage(unsigned long addr, void *val,
5588 struct x86_exception *exception,
5589 struct kvm_vcpu *vcpu,
5590 const struct read_write_emulator_ops *ops)
5594 bool write = ops->write;
5595 struct kvm_mmio_fragment *frag;
5596 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5599 * If the exit was due to a NPF we may already have a GPA.
5600 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5601 * Note, this cannot be used on string operations since string
5602 * operation using rep will only have the initial GPA from the NPF
5605 if (vcpu->arch.gpa_available &&
5606 emulator_can_use_gpa(ctxt) &&
5607 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5608 gpa = vcpu->arch.gpa_val;
5609 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5611 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5613 return X86EMUL_PROPAGATE_FAULT;
5616 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5617 return X86EMUL_CONTINUE;
5620 * Is this MMIO handled locally?
5622 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5623 if (handled == bytes)
5624 return X86EMUL_CONTINUE;
5630 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5631 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5635 return X86EMUL_CONTINUE;
5638 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5640 void *val, unsigned int bytes,
5641 struct x86_exception *exception,
5642 const struct read_write_emulator_ops *ops)
5644 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5648 if (ops->read_write_prepare &&
5649 ops->read_write_prepare(vcpu, val, bytes))
5650 return X86EMUL_CONTINUE;
5652 vcpu->mmio_nr_fragments = 0;
5654 /* Crossing a page boundary? */
5655 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5658 now = -addr & ~PAGE_MASK;
5659 rc = emulator_read_write_onepage(addr, val, now, exception,
5662 if (rc != X86EMUL_CONTINUE)
5665 if (ctxt->mode != X86EMUL_MODE_PROT64)
5671 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5673 if (rc != X86EMUL_CONTINUE)
5676 if (!vcpu->mmio_nr_fragments)
5679 gpa = vcpu->mmio_fragments[0].gpa;
5681 vcpu->mmio_needed = 1;
5682 vcpu->mmio_cur_fragment = 0;
5684 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5685 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5686 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5687 vcpu->run->mmio.phys_addr = gpa;
5689 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5692 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5696 struct x86_exception *exception)
5698 return emulator_read_write(ctxt, addr, val, bytes,
5699 exception, &read_emultor);
5702 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5706 struct x86_exception *exception)
5708 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5709 exception, &write_emultor);
5712 #define CMPXCHG_TYPE(t, ptr, old, new) \
5713 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5715 #ifdef CONFIG_X86_64
5716 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5718 # define CMPXCHG64(ptr, old, new) \
5719 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5722 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5727 struct x86_exception *exception)
5729 struct kvm_host_map map;
5730 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5735 /* guests cmpxchg8b have to be emulated atomically */
5736 if (bytes > 8 || (bytes & (bytes - 1)))
5739 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5741 if (gpa == UNMAPPED_GVA ||
5742 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5745 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5748 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5751 kaddr = map.hva + offset_in_page(gpa);
5755 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5758 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5761 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5764 exchanged = CMPXCHG64(kaddr, old, new);
5770 kvm_vcpu_unmap(vcpu, &map, true);
5773 return X86EMUL_CMPXCHG_FAILED;
5775 kvm_page_track_write(vcpu, gpa, new, bytes);
5777 return X86EMUL_CONTINUE;
5780 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5782 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5785 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5789 for (i = 0; i < vcpu->arch.pio.count; i++) {
5790 if (vcpu->arch.pio.in)
5791 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5792 vcpu->arch.pio.size, pd);
5794 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5795 vcpu->arch.pio.port, vcpu->arch.pio.size,
5799 pd += vcpu->arch.pio.size;
5804 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5805 unsigned short port, void *val,
5806 unsigned int count, bool in)
5808 vcpu->arch.pio.port = port;
5809 vcpu->arch.pio.in = in;
5810 vcpu->arch.pio.count = count;
5811 vcpu->arch.pio.size = size;
5813 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5814 vcpu->arch.pio.count = 0;
5818 vcpu->run->exit_reason = KVM_EXIT_IO;
5819 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5820 vcpu->run->io.size = size;
5821 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5822 vcpu->run->io.count = count;
5823 vcpu->run->io.port = port;
5828 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5829 int size, unsigned short port, void *val,
5832 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5835 if (vcpu->arch.pio.count)
5838 memset(vcpu->arch.pio_data, 0, size * count);
5840 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5843 memcpy(val, vcpu->arch.pio_data, size * count);
5844 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5845 vcpu->arch.pio.count = 0;
5852 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5853 int size, unsigned short port,
5854 const void *val, unsigned int count)
5856 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5858 memcpy(vcpu->arch.pio_data, val, size * count);
5859 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5860 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5863 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5865 return kvm_x86_ops->get_segment_base(vcpu, seg);
5868 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5870 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5873 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5875 if (!need_emulate_wbinvd(vcpu))
5876 return X86EMUL_CONTINUE;
5878 if (kvm_x86_ops->has_wbinvd_exit()) {
5879 int cpu = get_cpu();
5881 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
5882 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5883 wbinvd_ipi, NULL, 1);
5885 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
5888 return X86EMUL_CONTINUE;
5891 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5893 kvm_emulate_wbinvd_noskip(vcpu);
5894 return kvm_skip_emulated_instruction(vcpu);
5896 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5900 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5902 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
5905 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5906 unsigned long *dest)
5908 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
5911 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5912 unsigned long value)
5915 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
5918 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5920 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5923 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
5925 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5926 unsigned long value;
5930 value = kvm_read_cr0(vcpu);
5933 value = vcpu->arch.cr2;
5936 value = kvm_read_cr3(vcpu);
5939 value = kvm_read_cr4(vcpu);
5942 value = kvm_get_cr8(vcpu);
5945 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5952 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
5954 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5959 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
5962 vcpu->arch.cr2 = val;
5965 res = kvm_set_cr3(vcpu, val);
5968 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
5971 res = kvm_set_cr8(vcpu, val);
5974 kvm_err("%s: unexpected cr %u\n", __func__, cr);
5981 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
5983 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
5986 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5988 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
5991 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5993 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
5996 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5998 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6001 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6003 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6006 static unsigned long emulator_get_cached_segment_base(
6007 struct x86_emulate_ctxt *ctxt, int seg)
6009 return get_segment_base(emul_to_vcpu(ctxt), seg);
6012 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6013 struct desc_struct *desc, u32 *base3,
6016 struct kvm_segment var;
6018 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6019 *selector = var.selector;
6022 memset(desc, 0, sizeof(*desc));
6030 set_desc_limit(desc, var.limit);
6031 set_desc_base(desc, (unsigned long)var.base);
6032 #ifdef CONFIG_X86_64
6034 *base3 = var.base >> 32;
6036 desc->type = var.type;
6038 desc->dpl = var.dpl;
6039 desc->p = var.present;
6040 desc->avl = var.avl;
6048 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6049 struct desc_struct *desc, u32 base3,
6052 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6053 struct kvm_segment var;
6055 var.selector = selector;
6056 var.base = get_desc_base(desc);
6057 #ifdef CONFIG_X86_64
6058 var.base |= ((u64)base3) << 32;
6060 var.limit = get_desc_limit(desc);
6062 var.limit = (var.limit << 12) | 0xfff;
6063 var.type = desc->type;
6064 var.dpl = desc->dpl;
6069 var.avl = desc->avl;
6070 var.present = desc->p;
6071 var.unusable = !var.present;
6074 kvm_set_segment(vcpu, &var, seg);
6078 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6079 u32 msr_index, u64 *pdata)
6081 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6084 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6085 u32 msr_index, u64 data)
6087 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6090 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6092 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6094 return vcpu->arch.smbase;
6097 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6099 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6101 vcpu->arch.smbase = smbase;
6104 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6107 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
6110 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6111 u32 pmc, u64 *pdata)
6113 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6116 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6118 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6121 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6122 struct x86_instruction_info *info,
6123 enum x86_intercept_stage stage)
6125 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
6128 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6129 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
6131 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
6134 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6136 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6139 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6141 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6144 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6146 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6149 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6151 return emul_to_vcpu(ctxt)->arch.hflags;
6154 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6156 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6159 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6160 const char *smstate)
6162 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6165 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6167 kvm_smm_changed(emul_to_vcpu(ctxt));
6170 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6172 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6175 static const struct x86_emulate_ops emulate_ops = {
6176 .read_gpr = emulator_read_gpr,
6177 .write_gpr = emulator_write_gpr,
6178 .read_std = emulator_read_std,
6179 .write_std = emulator_write_std,
6180 .read_phys = kvm_read_guest_phys_system,
6181 .fetch = kvm_fetch_guest_virt,
6182 .read_emulated = emulator_read_emulated,
6183 .write_emulated = emulator_write_emulated,
6184 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6185 .invlpg = emulator_invlpg,
6186 .pio_in_emulated = emulator_pio_in_emulated,
6187 .pio_out_emulated = emulator_pio_out_emulated,
6188 .get_segment = emulator_get_segment,
6189 .set_segment = emulator_set_segment,
6190 .get_cached_segment_base = emulator_get_cached_segment_base,
6191 .get_gdt = emulator_get_gdt,
6192 .get_idt = emulator_get_idt,
6193 .set_gdt = emulator_set_gdt,
6194 .set_idt = emulator_set_idt,
6195 .get_cr = emulator_get_cr,
6196 .set_cr = emulator_set_cr,
6197 .cpl = emulator_get_cpl,
6198 .get_dr = emulator_get_dr,
6199 .set_dr = emulator_set_dr,
6200 .get_smbase = emulator_get_smbase,
6201 .set_smbase = emulator_set_smbase,
6202 .set_msr = emulator_set_msr,
6203 .get_msr = emulator_get_msr,
6204 .check_pmc = emulator_check_pmc,
6205 .read_pmc = emulator_read_pmc,
6206 .halt = emulator_halt,
6207 .wbinvd = emulator_wbinvd,
6208 .fix_hypercall = emulator_fix_hypercall,
6209 .intercept = emulator_intercept,
6210 .get_cpuid = emulator_get_cpuid,
6211 .set_nmi_mask = emulator_set_nmi_mask,
6212 .get_hflags = emulator_get_hflags,
6213 .set_hflags = emulator_set_hflags,
6214 .pre_leave_smm = emulator_pre_leave_smm,
6215 .post_leave_smm = emulator_post_leave_smm,
6216 .set_xcr = emulator_set_xcr,
6219 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6221 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6223 * an sti; sti; sequence only disable interrupts for the first
6224 * instruction. So, if the last instruction, be it emulated or
6225 * not, left the system with the INT_STI flag enabled, it
6226 * means that the last instruction is an sti. We should not
6227 * leave the flag on in this case. The same goes for mov ss
6229 if (int_shadow & mask)
6231 if (unlikely(int_shadow || mask)) {
6232 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6234 kvm_make_request(KVM_REQ_EVENT, vcpu);
6238 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6240 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6241 if (ctxt->exception.vector == PF_VECTOR)
6242 return kvm_propagate_fault(vcpu, &ctxt->exception);
6244 if (ctxt->exception.error_code_valid)
6245 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6246 ctxt->exception.error_code);
6248 kvm_queue_exception(vcpu, ctxt->exception.vector);
6252 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6254 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6257 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6259 ctxt->eflags = kvm_get_rflags(vcpu);
6260 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6262 ctxt->eip = kvm_rip_read(vcpu);
6263 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6264 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6265 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6266 cs_db ? X86EMUL_MODE_PROT32 :
6267 X86EMUL_MODE_PROT16;
6268 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6269 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6270 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6272 init_decode_cache(ctxt);
6273 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6276 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6278 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6281 init_emulate_ctxt(vcpu);
6285 ctxt->_eip = ctxt->eip + inc_eip;
6286 ret = emulate_int_real(ctxt, irq);
6288 if (ret != X86EMUL_CONTINUE)
6289 return EMULATE_FAIL;
6291 ctxt->eip = ctxt->_eip;
6292 kvm_rip_write(vcpu, ctxt->eip);
6293 kvm_set_rflags(vcpu, ctxt->eflags);
6295 return EMULATE_DONE;
6297 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6299 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6301 ++vcpu->stat.insn_emulation_fail;
6302 trace_kvm_emulate_insn_failed(vcpu);
6304 if (emulation_type & EMULTYPE_VMWARE_GP) {
6305 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6306 return EMULATE_DONE;
6309 if (emulation_type & EMULTYPE_SKIP) {
6310 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6311 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6312 vcpu->run->internal.ndata = 0;
6313 return EMULATE_USER_EXIT;
6316 kvm_queue_exception(vcpu, UD_VECTOR);
6318 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6319 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6320 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6321 vcpu->run->internal.ndata = 0;
6322 return EMULATE_USER_EXIT;
6325 return EMULATE_DONE;
6328 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
6329 bool write_fault_to_shadow_pgtable,
6335 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6338 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6341 if (!vcpu->arch.mmu->direct_map) {
6343 * Write permission should be allowed since only
6344 * write access need to be emulated.
6346 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6349 * If the mapping is invalid in guest, let cpu retry
6350 * it to generate fault.
6352 if (gpa == UNMAPPED_GVA)
6357 * Do not retry the unhandleable instruction if it faults on the
6358 * readonly host memory, otherwise it will goto a infinite loop:
6359 * retry instruction -> write #PF -> emulation fail -> retry
6360 * instruction -> ...
6362 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6365 * If the instruction failed on the error pfn, it can not be fixed,
6366 * report the error to userspace.
6368 if (is_error_noslot_pfn(pfn))
6371 kvm_release_pfn_clean(pfn);
6373 /* The instructions are well-emulated on direct mmu. */
6374 if (vcpu->arch.mmu->direct_map) {
6375 unsigned int indirect_shadow_pages;
6377 spin_lock(&vcpu->kvm->mmu_lock);
6378 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6379 spin_unlock(&vcpu->kvm->mmu_lock);
6381 if (indirect_shadow_pages)
6382 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6388 * if emulation was due to access to shadowed page table
6389 * and it failed try to unshadow page and re-enter the
6390 * guest to let CPU execute the instruction.
6392 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6395 * If the access faults on its page table, it can not
6396 * be fixed by unprotecting shadow page and it should
6397 * be reported to userspace.
6399 return !write_fault_to_shadow_pgtable;
6402 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6403 unsigned long cr2, int emulation_type)
6405 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6406 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6408 last_retry_eip = vcpu->arch.last_retry_eip;
6409 last_retry_addr = vcpu->arch.last_retry_addr;
6412 * If the emulation is caused by #PF and it is non-page_table
6413 * writing instruction, it means the VM-EXIT is caused by shadow
6414 * page protected, we can zap the shadow page and retry this
6415 * instruction directly.
6417 * Note: if the guest uses a non-page-table modifying instruction
6418 * on the PDE that points to the instruction, then we will unmap
6419 * the instruction and go to an infinite loop. So, we cache the
6420 * last retried eip and the last fault address, if we meet the eip
6421 * and the address again, we can break out of the potential infinite
6424 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6426 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
6429 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6432 if (x86_page_table_writing_insn(ctxt))
6435 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6438 vcpu->arch.last_retry_eip = ctxt->eip;
6439 vcpu->arch.last_retry_addr = cr2;
6441 if (!vcpu->arch.mmu->direct_map)
6442 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6444 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6449 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6450 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6452 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6454 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6455 /* This is a good place to trace that we are exiting SMM. */
6456 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6458 /* Process a latched INIT or SMI, if any. */
6459 kvm_make_request(KVM_REQ_EVENT, vcpu);
6462 kvm_mmu_reset_context(vcpu);
6465 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6474 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6475 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6480 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6482 struct kvm_run *kvm_run = vcpu->run;
6484 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6485 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6486 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6487 kvm_run->debug.arch.exception = DB_VECTOR;
6488 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6489 return EMULATE_USER_EXIT;
6491 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6492 return EMULATE_DONE;
6495 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6497 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6500 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6501 if (unlikely(r != EMULATE_DONE))
6505 * rflags is the old, "raw" value of the flags. The new value has
6506 * not been saved yet.
6508 * This is correct even for TF set by the guest, because "the
6509 * processor will not generate this exception after the instruction
6510 * that sets the TF flag".
6512 if (unlikely(rflags & X86_EFLAGS_TF))
6513 r = kvm_vcpu_do_singlestep(vcpu);
6514 return r == EMULATE_DONE;
6516 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6518 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6520 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6521 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6522 struct kvm_run *kvm_run = vcpu->run;
6523 unsigned long eip = kvm_get_linear_rip(vcpu);
6524 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6525 vcpu->arch.guest_debug_dr7,
6529 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6530 kvm_run->debug.arch.pc = eip;
6531 kvm_run->debug.arch.exception = DB_VECTOR;
6532 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6533 *r = EMULATE_USER_EXIT;
6538 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6539 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6540 unsigned long eip = kvm_get_linear_rip(vcpu);
6541 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6546 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6547 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6548 kvm_queue_exception(vcpu, DB_VECTOR);
6557 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6559 switch (ctxt->opcode_len) {
6566 case 0xe6: /* OUT */
6570 case 0x6c: /* INS */
6572 case 0x6e: /* OUTS */
6579 case 0x33: /* RDPMC */
6588 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6595 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6596 bool writeback = true;
6597 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6599 vcpu->arch.l1tf_flush_l1d = true;
6602 * Clear write_fault_to_shadow_pgtable here to ensure it is
6605 vcpu->arch.write_fault_to_shadow_pgtable = false;
6606 kvm_clear_exception_queue(vcpu);
6608 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6609 init_emulate_ctxt(vcpu);
6612 * We will reenter on the same instruction since
6613 * we do not set complete_userspace_io. This does not
6614 * handle watchpoints yet, those would be handled in
6617 if (!(emulation_type & EMULTYPE_SKIP) &&
6618 kvm_vcpu_check_breakpoint(vcpu, &r))
6621 ctxt->interruptibility = 0;
6622 ctxt->have_exception = false;
6623 ctxt->exception.vector = -1;
6624 ctxt->perm_ok = false;
6626 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6628 r = x86_decode_insn(ctxt, insn, insn_len);
6630 trace_kvm_emulate_insn_start(vcpu);
6631 ++vcpu->stat.insn_emulation;
6632 if (r != EMULATION_OK) {
6633 if ((emulation_type & EMULTYPE_TRAP_UD) ||
6634 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6635 kvm_queue_exception(vcpu, UD_VECTOR);
6636 return EMULATE_DONE;
6638 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6640 return EMULATE_DONE;
6641 if (ctxt->have_exception) {
6643 * #UD should result in just EMULATION_FAILED, and trap-like
6644 * exception should not be encountered during decode.
6646 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6647 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6648 inject_emulated_exception(vcpu);
6649 return EMULATE_DONE;
6651 return handle_emulation_failure(vcpu, emulation_type);
6655 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6656 !is_vmware_backdoor_opcode(ctxt)) {
6657 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6658 return EMULATE_DONE;
6661 if (emulation_type & EMULTYPE_SKIP) {
6662 kvm_rip_write(vcpu, ctxt->_eip);
6663 if (ctxt->eflags & X86_EFLAGS_RF)
6664 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6665 kvm_x86_ops->set_interrupt_shadow(vcpu, 0);
6666 return EMULATE_DONE;
6669 if (retry_instruction(ctxt, cr2, emulation_type))
6670 return EMULATE_DONE;
6672 /* this is needed for vmware backdoor interface to work since it
6673 changes registers values during IO operation */
6674 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6675 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6676 emulator_invalidate_register_cache(ctxt);
6680 /* Save the faulting GPA (cr2) in the address field */
6681 ctxt->exception.address = cr2;
6683 r = x86_emulate_insn(ctxt);
6685 if (r == EMULATION_INTERCEPTED)
6686 return EMULATE_DONE;
6688 if (r == EMULATION_FAILED) {
6689 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6691 return EMULATE_DONE;
6693 return handle_emulation_failure(vcpu, emulation_type);
6696 if (ctxt->have_exception) {
6698 if (inject_emulated_exception(vcpu))
6700 } else if (vcpu->arch.pio.count) {
6701 if (!vcpu->arch.pio.in) {
6702 /* FIXME: return into emulator if single-stepping. */
6703 vcpu->arch.pio.count = 0;
6706 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6708 r = EMULATE_USER_EXIT;
6709 } else if (vcpu->mmio_needed) {
6710 ++vcpu->stat.mmio_exits;
6712 if (!vcpu->mmio_is_write)
6714 r = EMULATE_USER_EXIT;
6715 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6716 } else if (r == EMULATION_RESTART)
6722 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6723 toggle_interruptibility(vcpu, ctxt->interruptibility);
6724 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6725 if (!ctxt->have_exception ||
6726 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6727 kvm_rip_write(vcpu, ctxt->eip);
6728 if (r == EMULATE_DONE && ctxt->tf)
6729 r = kvm_vcpu_do_singlestep(vcpu);
6730 __kvm_set_rflags(vcpu, ctxt->eflags);
6734 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6735 * do nothing, and it will be requested again as soon as
6736 * the shadow expires. But we still need to check here,
6737 * because POPF has no interrupt shadow.
6739 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6740 kvm_make_request(KVM_REQ_EVENT, vcpu);
6742 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6747 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6749 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6751 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6753 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6754 void *insn, int insn_len)
6756 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6758 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6760 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6762 vcpu->arch.pio.count = 0;
6766 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6768 vcpu->arch.pio.count = 0;
6770 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6773 return kvm_skip_emulated_instruction(vcpu);
6776 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6777 unsigned short port)
6779 unsigned long val = kvm_rax_read(vcpu);
6780 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6781 size, port, &val, 1);
6786 * Workaround userspace that relies on old KVM behavior of %rip being
6787 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6790 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6791 vcpu->arch.complete_userspace_io =
6792 complete_fast_pio_out_port_0x7e;
6793 kvm_skip_emulated_instruction(vcpu);
6795 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6796 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6801 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6805 /* We should only ever be called with arch.pio.count equal to 1 */
6806 BUG_ON(vcpu->arch.pio.count != 1);
6808 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6809 vcpu->arch.pio.count = 0;
6813 /* For size less than 4 we merge, else we zero extend */
6814 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6817 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6818 * the copy and tracing
6820 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6821 vcpu->arch.pio.port, &val, 1);
6822 kvm_rax_write(vcpu, val);
6824 return kvm_skip_emulated_instruction(vcpu);
6827 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6828 unsigned short port)
6833 /* For size less than 4 we merge, else we zero extend */
6834 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
6836 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6839 kvm_rax_write(vcpu, val);
6843 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6844 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6849 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6854 ret = kvm_fast_pio_in(vcpu, size, port);
6856 ret = kvm_fast_pio_out(vcpu, size, port);
6857 return ret && kvm_skip_emulated_instruction(vcpu);
6859 EXPORT_SYMBOL_GPL(kvm_fast_pio);
6861 static int kvmclock_cpu_down_prep(unsigned int cpu)
6863 __this_cpu_write(cpu_tsc_khz, 0);
6867 static void tsc_khz_changed(void *data)
6869 struct cpufreq_freqs *freq = data;
6870 unsigned long khz = 0;
6874 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6875 khz = cpufreq_quick_get(raw_smp_processor_id());
6878 __this_cpu_write(cpu_tsc_khz, khz);
6881 #ifdef CONFIG_X86_64
6882 static void kvm_hyperv_tsc_notifier(void)
6885 struct kvm_vcpu *vcpu;
6888 mutex_lock(&kvm_lock);
6889 list_for_each_entry(kvm, &vm_list, vm_list)
6890 kvm_make_mclock_inprogress_request(kvm);
6892 hyperv_stop_tsc_emulation();
6894 /* TSC frequency always matches when on Hyper-V */
6895 for_each_present_cpu(cpu)
6896 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6897 kvm_max_guest_tsc_khz = tsc_khz;
6899 list_for_each_entry(kvm, &vm_list, vm_list) {
6900 struct kvm_arch *ka = &kvm->arch;
6902 spin_lock(&ka->pvclock_gtod_sync_lock);
6904 pvclock_update_vm_gtod_copy(kvm);
6906 kvm_for_each_vcpu(cpu, vcpu, kvm)
6907 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6909 kvm_for_each_vcpu(cpu, vcpu, kvm)
6910 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6912 spin_unlock(&ka->pvclock_gtod_sync_lock);
6914 mutex_unlock(&kvm_lock);
6918 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
6921 struct kvm_vcpu *vcpu;
6922 int i, send_ipi = 0;
6925 * We allow guests to temporarily run on slowing clocks,
6926 * provided we notify them after, or to run on accelerating
6927 * clocks, provided we notify them before. Thus time never
6930 * However, we have a problem. We can't atomically update
6931 * the frequency of a given CPU from this function; it is
6932 * merely a notifier, which can be called from any CPU.
6933 * Changing the TSC frequency at arbitrary points in time
6934 * requires a recomputation of local variables related to
6935 * the TSC for each VCPU. We must flag these local variables
6936 * to be updated and be sure the update takes place with the
6937 * new frequency before any guests proceed.
6939 * Unfortunately, the combination of hotplug CPU and frequency
6940 * change creates an intractable locking scenario; the order
6941 * of when these callouts happen is undefined with respect to
6942 * CPU hotplug, and they can race with each other. As such,
6943 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6944 * undefined; you can actually have a CPU frequency change take
6945 * place in between the computation of X and the setting of the
6946 * variable. To protect against this problem, all updates of
6947 * the per_cpu tsc_khz variable are done in an interrupt
6948 * protected IPI, and all callers wishing to update the value
6949 * must wait for a synchronous IPI to complete (which is trivial
6950 * if the caller is on the CPU already). This establishes the
6951 * necessary total order on variable updates.
6953 * Note that because a guest time update may take place
6954 * anytime after the setting of the VCPU's request bit, the
6955 * correct TSC value must be set before the request. However,
6956 * to ensure the update actually makes it to any guest which
6957 * starts running in hardware virtualization between the set
6958 * and the acquisition of the spinlock, we must also ping the
6959 * CPU after setting the request bit.
6963 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6965 mutex_lock(&kvm_lock);
6966 list_for_each_entry(kvm, &vm_list, vm_list) {
6967 kvm_for_each_vcpu(i, vcpu, kvm) {
6968 if (vcpu->cpu != cpu)
6970 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6971 if (vcpu->cpu != raw_smp_processor_id())
6975 mutex_unlock(&kvm_lock);
6977 if (freq->old < freq->new && send_ipi) {
6979 * We upscale the frequency. Must make the guest
6980 * doesn't see old kvmclock values while running with
6981 * the new frequency, otherwise we risk the guest sees
6982 * time go backwards.
6984 * In case we update the frequency for another cpu
6985 * (which might be in guest context) send an interrupt
6986 * to kick the cpu out of guest context. Next time
6987 * guest context is entered kvmclock will be updated,
6988 * so the guest will not see stale values.
6990 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
6994 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6997 struct cpufreq_freqs *freq = data;
7000 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7002 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7005 for_each_cpu(cpu, freq->policy->cpus)
7006 __kvmclock_cpufreq_notifier(freq, cpu);
7011 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7012 .notifier_call = kvmclock_cpufreq_notifier
7015 static int kvmclock_cpu_online(unsigned int cpu)
7017 tsc_khz_changed(NULL);
7021 static void kvm_timer_init(void)
7023 max_tsc_khz = tsc_khz;
7025 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7026 #ifdef CONFIG_CPU_FREQ
7027 struct cpufreq_policy policy;
7030 memset(&policy, 0, sizeof(policy));
7032 cpufreq_get_policy(&policy, cpu);
7033 if (policy.cpuinfo.max_freq)
7034 max_tsc_khz = policy.cpuinfo.max_freq;
7037 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7038 CPUFREQ_TRANSITION_NOTIFIER);
7041 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7042 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7045 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7046 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7048 int kvm_is_in_guest(void)
7050 return __this_cpu_read(current_vcpu) != NULL;
7053 static int kvm_is_user_mode(void)
7057 if (__this_cpu_read(current_vcpu))
7058 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
7060 return user_mode != 0;
7063 static unsigned long kvm_get_guest_ip(void)
7065 unsigned long ip = 0;
7067 if (__this_cpu_read(current_vcpu))
7068 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7073 static void kvm_handle_intel_pt_intr(void)
7075 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7077 kvm_make_request(KVM_REQ_PMI, vcpu);
7078 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7079 (unsigned long *)&vcpu->arch.pmu.global_status);
7082 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7083 .is_in_guest = kvm_is_in_guest,
7084 .is_user_mode = kvm_is_user_mode,
7085 .get_guest_ip = kvm_get_guest_ip,
7086 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7089 #ifdef CONFIG_X86_64
7090 static void pvclock_gtod_update_fn(struct work_struct *work)
7094 struct kvm_vcpu *vcpu;
7097 mutex_lock(&kvm_lock);
7098 list_for_each_entry(kvm, &vm_list, vm_list)
7099 kvm_for_each_vcpu(i, vcpu, kvm)
7100 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7101 atomic_set(&kvm_guest_has_master_clock, 0);
7102 mutex_unlock(&kvm_lock);
7105 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7108 * Notification about pvclock gtod data update.
7110 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7113 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7114 struct timekeeper *tk = priv;
7116 update_pvclock_gtod(tk);
7118 /* disable master clock if host does not trust, or does not
7119 * use, TSC based clocksource.
7121 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7122 atomic_read(&kvm_guest_has_master_clock) != 0)
7123 queue_work(system_long_wq, &pvclock_gtod_work);
7128 static struct notifier_block pvclock_gtod_notifier = {
7129 .notifier_call = pvclock_gtod_notify,
7133 int kvm_arch_init(void *opaque)
7136 struct kvm_x86_ops *ops = opaque;
7139 printk(KERN_ERR "kvm: already loaded the other module\n");
7144 if (!ops->cpu_has_kvm_support()) {
7145 printk(KERN_ERR "kvm: no hardware support\n");
7149 if (ops->disabled_by_bios()) {
7150 printk(KERN_ERR "kvm: disabled by bios\n");
7156 * KVM explicitly assumes that the guest has an FPU and
7157 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7158 * vCPU's FPU state as a fxregs_state struct.
7160 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7161 printk(KERN_ERR "kvm: inadequate fpu\n");
7167 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7168 __alignof__(struct fpu), SLAB_ACCOUNT,
7170 if (!x86_fpu_cache) {
7171 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7175 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7177 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7178 goto out_free_x86_fpu_cache;
7181 r = kvm_mmu_module_init();
7183 goto out_free_percpu;
7187 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7188 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7189 PT_PRESENT_MASK, 0, sme_me_mask);
7192 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7194 if (boot_cpu_has(X86_FEATURE_XSAVE))
7195 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7198 if (pi_inject_timer == -1)
7199 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7200 #ifdef CONFIG_X86_64
7201 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7203 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7204 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7210 free_percpu(shared_msrs);
7211 out_free_x86_fpu_cache:
7212 kmem_cache_destroy(x86_fpu_cache);
7217 void kvm_arch_exit(void)
7219 #ifdef CONFIG_X86_64
7220 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7221 clear_hv_tscchange_cb();
7224 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7226 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7227 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7228 CPUFREQ_TRANSITION_NOTIFIER);
7229 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7230 #ifdef CONFIG_X86_64
7231 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7234 kvm_mmu_module_exit();
7235 free_percpu(shared_msrs);
7236 kmem_cache_destroy(x86_fpu_cache);
7239 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7241 ++vcpu->stat.halt_exits;
7242 if (lapic_in_kernel(vcpu)) {
7243 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7246 vcpu->run->exit_reason = KVM_EXIT_HLT;
7250 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7252 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7254 int ret = kvm_skip_emulated_instruction(vcpu);
7256 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7257 * KVM_EXIT_DEBUG here.
7259 return kvm_vcpu_halt(vcpu) && ret;
7261 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7263 #ifdef CONFIG_X86_64
7264 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7265 unsigned long clock_type)
7267 struct kvm_clock_pairing clock_pairing;
7268 struct timespec64 ts;
7272 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7273 return -KVM_EOPNOTSUPP;
7275 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7276 return -KVM_EOPNOTSUPP;
7278 clock_pairing.sec = ts.tv_sec;
7279 clock_pairing.nsec = ts.tv_nsec;
7280 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7281 clock_pairing.flags = 0;
7282 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7285 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7286 sizeof(struct kvm_clock_pairing)))
7294 * kvm_pv_kick_cpu_op: Kick a vcpu.
7296 * @apicid - apicid of vcpu to be kicked.
7298 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7300 struct kvm_lapic_irq lapic_irq;
7302 lapic_irq.shorthand = 0;
7303 lapic_irq.dest_mode = 0;
7304 lapic_irq.level = 0;
7305 lapic_irq.dest_id = apicid;
7306 lapic_irq.msi_redir_hint = false;
7308 lapic_irq.delivery_mode = APIC_DM_REMRD;
7309 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7312 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7314 if (!lapic_in_kernel(vcpu)) {
7315 WARN_ON_ONCE(vcpu->arch.apicv_active);
7318 if (!vcpu->arch.apicv_active)
7321 vcpu->arch.apicv_active = false;
7322 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7325 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7327 struct kvm_vcpu *target = NULL;
7328 struct kvm_apic_map *map;
7331 map = rcu_dereference(kvm->arch.apic_map);
7333 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7334 target = map->phys_map[dest_id]->vcpu;
7338 if (target && READ_ONCE(target->ready))
7339 kvm_vcpu_yield_to(target);
7342 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7344 unsigned long nr, a0, a1, a2, a3, ret;
7347 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7348 return kvm_hv_hypercall(vcpu);
7350 nr = kvm_rax_read(vcpu);
7351 a0 = kvm_rbx_read(vcpu);
7352 a1 = kvm_rcx_read(vcpu);
7353 a2 = kvm_rdx_read(vcpu);
7354 a3 = kvm_rsi_read(vcpu);
7356 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7358 op_64_bit = is_64_bit_mode(vcpu);
7367 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7373 case KVM_HC_VAPIC_POLL_IRQ:
7376 case KVM_HC_KICK_CPU:
7377 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7378 kvm_sched_yield(vcpu->kvm, a1);
7381 #ifdef CONFIG_X86_64
7382 case KVM_HC_CLOCK_PAIRING:
7383 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7386 case KVM_HC_SEND_IPI:
7387 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7389 case KVM_HC_SCHED_YIELD:
7390 kvm_sched_yield(vcpu->kvm, a0);
7400 kvm_rax_write(vcpu, ret);
7402 ++vcpu->stat.hypercalls;
7403 return kvm_skip_emulated_instruction(vcpu);
7405 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7407 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7409 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7410 char instruction[3];
7411 unsigned long rip = kvm_rip_read(vcpu);
7413 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7415 return emulator_write_emulated(ctxt, rip, instruction, 3,
7419 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7421 return vcpu->run->request_interrupt_window &&
7422 likely(!pic_in_kernel(vcpu->kvm));
7425 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7427 struct kvm_run *kvm_run = vcpu->run;
7429 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7430 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7431 kvm_run->cr8 = kvm_get_cr8(vcpu);
7432 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7433 kvm_run->ready_for_interrupt_injection =
7434 pic_in_kernel(vcpu->kvm) ||
7435 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7438 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7442 if (!kvm_x86_ops->update_cr8_intercept)
7445 if (!lapic_in_kernel(vcpu))
7448 if (vcpu->arch.apicv_active)
7451 if (!vcpu->arch.apic->vapic_addr)
7452 max_irr = kvm_lapic_find_highest_irr(vcpu);
7459 tpr = kvm_lapic_get_cr8(vcpu);
7461 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7464 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
7468 /* try to reinject previous events if any */
7470 if (vcpu->arch.exception.injected)
7471 kvm_x86_ops->queue_exception(vcpu);
7473 * Do not inject an NMI or interrupt if there is a pending
7474 * exception. Exceptions and interrupts are recognized at
7475 * instruction boundaries, i.e. the start of an instruction.
7476 * Trap-like exceptions, e.g. #DB, have higher priority than
7477 * NMIs and interrupts, i.e. traps are recognized before an
7478 * NMI/interrupt that's pending on the same instruction.
7479 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7480 * priority, but are only generated (pended) during instruction
7481 * execution, i.e. a pending fault-like exception means the
7482 * fault occurred on the *previous* instruction and must be
7483 * serviced prior to recognizing any new events in order to
7484 * fully complete the previous instruction.
7486 else if (!vcpu->arch.exception.pending) {
7487 if (vcpu->arch.nmi_injected)
7488 kvm_x86_ops->set_nmi(vcpu);
7489 else if (vcpu->arch.interrupt.injected)
7490 kvm_x86_ops->set_irq(vcpu);
7494 * Call check_nested_events() even if we reinjected a previous event
7495 * in order for caller to determine if it should require immediate-exit
7496 * from L2 to L1 due to pending L1 events which require exit
7499 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7500 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7505 /* try to inject new event if pending */
7506 if (vcpu->arch.exception.pending) {
7507 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7508 vcpu->arch.exception.has_error_code,
7509 vcpu->arch.exception.error_code);
7511 WARN_ON_ONCE(vcpu->arch.exception.injected);
7512 vcpu->arch.exception.pending = false;
7513 vcpu->arch.exception.injected = true;
7515 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7516 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7519 if (vcpu->arch.exception.nr == DB_VECTOR) {
7521 * This code assumes that nSVM doesn't use
7522 * check_nested_events(). If it does, the
7523 * DR6/DR7 changes should happen before L1
7524 * gets a #VMEXIT for an intercepted #DB in
7525 * L2. (Under VMX, on the other hand, the
7526 * DR6/DR7 changes should not happen in the
7527 * event of a VM-exit to L1 for an intercepted
7530 kvm_deliver_exception_payload(vcpu);
7531 if (vcpu->arch.dr7 & DR7_GD) {
7532 vcpu->arch.dr7 &= ~DR7_GD;
7533 kvm_update_dr7(vcpu);
7537 kvm_x86_ops->queue_exception(vcpu);
7540 /* Don't consider new event if we re-injected an event */
7541 if (kvm_event_needs_reinjection(vcpu))
7544 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7545 kvm_x86_ops->smi_allowed(vcpu)) {
7546 vcpu->arch.smi_pending = false;
7547 ++vcpu->arch.smi_count;
7549 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7550 --vcpu->arch.nmi_pending;
7551 vcpu->arch.nmi_injected = true;
7552 kvm_x86_ops->set_nmi(vcpu);
7553 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7555 * Because interrupts can be injected asynchronously, we are
7556 * calling check_nested_events again here to avoid a race condition.
7557 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7558 * proposal and current concerns. Perhaps we should be setting
7559 * KVM_REQ_EVENT only on certain events and not unconditionally?
7561 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7562 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7566 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7567 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7569 kvm_x86_ops->set_irq(vcpu);
7576 static void process_nmi(struct kvm_vcpu *vcpu)
7581 * x86 is limited to one NMI running, and one NMI pending after it.
7582 * If an NMI is already in progress, limit further NMIs to just one.
7583 * Otherwise, allow two (and we'll inject the first one immediately).
7585 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7588 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7589 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7590 kvm_make_request(KVM_REQ_EVENT, vcpu);
7593 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7596 flags |= seg->g << 23;
7597 flags |= seg->db << 22;
7598 flags |= seg->l << 21;
7599 flags |= seg->avl << 20;
7600 flags |= seg->present << 15;
7601 flags |= seg->dpl << 13;
7602 flags |= seg->s << 12;
7603 flags |= seg->type << 8;
7607 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7609 struct kvm_segment seg;
7612 kvm_get_segment(vcpu, &seg, n);
7613 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7616 offset = 0x7f84 + n * 12;
7618 offset = 0x7f2c + (n - 3) * 12;
7620 put_smstate(u32, buf, offset + 8, seg.base);
7621 put_smstate(u32, buf, offset + 4, seg.limit);
7622 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7625 #ifdef CONFIG_X86_64
7626 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7628 struct kvm_segment seg;
7632 kvm_get_segment(vcpu, &seg, n);
7633 offset = 0x7e00 + n * 16;
7635 flags = enter_smm_get_segment_flags(&seg) >> 8;
7636 put_smstate(u16, buf, offset, seg.selector);
7637 put_smstate(u16, buf, offset + 2, flags);
7638 put_smstate(u32, buf, offset + 4, seg.limit);
7639 put_smstate(u64, buf, offset + 8, seg.base);
7643 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7646 struct kvm_segment seg;
7650 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7651 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7652 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7653 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7655 for (i = 0; i < 8; i++)
7656 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7658 kvm_get_dr(vcpu, 6, &val);
7659 put_smstate(u32, buf, 0x7fcc, (u32)val);
7660 kvm_get_dr(vcpu, 7, &val);
7661 put_smstate(u32, buf, 0x7fc8, (u32)val);
7663 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7664 put_smstate(u32, buf, 0x7fc4, seg.selector);
7665 put_smstate(u32, buf, 0x7f64, seg.base);
7666 put_smstate(u32, buf, 0x7f60, seg.limit);
7667 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7669 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7670 put_smstate(u32, buf, 0x7fc0, seg.selector);
7671 put_smstate(u32, buf, 0x7f80, seg.base);
7672 put_smstate(u32, buf, 0x7f7c, seg.limit);
7673 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7675 kvm_x86_ops->get_gdt(vcpu, &dt);
7676 put_smstate(u32, buf, 0x7f74, dt.address);
7677 put_smstate(u32, buf, 0x7f70, dt.size);
7679 kvm_x86_ops->get_idt(vcpu, &dt);
7680 put_smstate(u32, buf, 0x7f58, dt.address);
7681 put_smstate(u32, buf, 0x7f54, dt.size);
7683 for (i = 0; i < 6; i++)
7684 enter_smm_save_seg_32(vcpu, buf, i);
7686 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7689 put_smstate(u32, buf, 0x7efc, 0x00020000);
7690 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7693 #ifdef CONFIG_X86_64
7694 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7697 struct kvm_segment seg;
7701 for (i = 0; i < 16; i++)
7702 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7704 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7705 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7707 kvm_get_dr(vcpu, 6, &val);
7708 put_smstate(u64, buf, 0x7f68, val);
7709 kvm_get_dr(vcpu, 7, &val);
7710 put_smstate(u64, buf, 0x7f60, val);
7712 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7713 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7714 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7716 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7719 put_smstate(u32, buf, 0x7efc, 0x00020064);
7721 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7723 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7724 put_smstate(u16, buf, 0x7e90, seg.selector);
7725 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7726 put_smstate(u32, buf, 0x7e94, seg.limit);
7727 put_smstate(u64, buf, 0x7e98, seg.base);
7729 kvm_x86_ops->get_idt(vcpu, &dt);
7730 put_smstate(u32, buf, 0x7e84, dt.size);
7731 put_smstate(u64, buf, 0x7e88, dt.address);
7733 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7734 put_smstate(u16, buf, 0x7e70, seg.selector);
7735 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7736 put_smstate(u32, buf, 0x7e74, seg.limit);
7737 put_smstate(u64, buf, 0x7e78, seg.base);
7739 kvm_x86_ops->get_gdt(vcpu, &dt);
7740 put_smstate(u32, buf, 0x7e64, dt.size);
7741 put_smstate(u64, buf, 0x7e68, dt.address);
7743 for (i = 0; i < 6; i++)
7744 enter_smm_save_seg_64(vcpu, buf, i);
7748 static void enter_smm(struct kvm_vcpu *vcpu)
7750 struct kvm_segment cs, ds;
7755 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7756 memset(buf, 0, 512);
7757 #ifdef CONFIG_X86_64
7758 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7759 enter_smm_save_state_64(vcpu, buf);
7762 enter_smm_save_state_32(vcpu, buf);
7765 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7766 * vCPU state (e.g. leave guest mode) after we've saved the state into
7767 * the SMM state-save area.
7769 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7771 vcpu->arch.hflags |= HF_SMM_MASK;
7772 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7774 if (kvm_x86_ops->get_nmi_mask(vcpu))
7775 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7777 kvm_x86_ops->set_nmi_mask(vcpu, true);
7779 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7780 kvm_rip_write(vcpu, 0x8000);
7782 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7783 kvm_x86_ops->set_cr0(vcpu, cr0);
7784 vcpu->arch.cr0 = cr0;
7786 kvm_x86_ops->set_cr4(vcpu, 0);
7788 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7789 dt.address = dt.size = 0;
7790 kvm_x86_ops->set_idt(vcpu, &dt);
7792 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7794 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7795 cs.base = vcpu->arch.smbase;
7800 cs.limit = ds.limit = 0xffffffff;
7801 cs.type = ds.type = 0x3;
7802 cs.dpl = ds.dpl = 0;
7807 cs.avl = ds.avl = 0;
7808 cs.present = ds.present = 1;
7809 cs.unusable = ds.unusable = 0;
7810 cs.padding = ds.padding = 0;
7812 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7813 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7814 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7815 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7816 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7817 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7819 #ifdef CONFIG_X86_64
7820 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7821 kvm_x86_ops->set_efer(vcpu, 0);
7824 kvm_update_cpuid(vcpu);
7825 kvm_mmu_reset_context(vcpu);
7828 static void process_smi(struct kvm_vcpu *vcpu)
7830 vcpu->arch.smi_pending = true;
7831 kvm_make_request(KVM_REQ_EVENT, vcpu);
7834 void kvm_make_scan_ioapic_request(struct kvm *kvm)
7836 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7839 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
7841 if (!kvm_apic_present(vcpu))
7844 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
7846 if (irqchip_split(vcpu->kvm))
7847 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
7849 if (vcpu->arch.apicv_active)
7850 kvm_x86_ops->sync_pir_to_irr(vcpu);
7851 if (ioapic_in_kernel(vcpu->kvm))
7852 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
7855 if (is_guest_mode(vcpu))
7856 vcpu->arch.load_eoi_exitmap_pending = true;
7858 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7861 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7863 u64 eoi_exit_bitmap[4];
7865 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7868 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7869 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7870 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
7873 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7874 unsigned long start, unsigned long end,
7877 unsigned long apic_address;
7880 * The physical address of apic access page is stored in the VMCS.
7881 * Update it when it becomes invalid.
7883 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7884 if (start <= apic_address && apic_address < end)
7885 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7890 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7892 struct page *page = NULL;
7894 if (!lapic_in_kernel(vcpu))
7897 if (!kvm_x86_ops->set_apic_access_page_addr)
7900 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7901 if (is_error_page(page))
7903 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7906 * Do not pin apic access page in memory, the MMU notifier
7907 * will call us again if it is migrated or swapped out.
7911 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7913 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7915 smp_send_reschedule(vcpu->cpu);
7917 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7920 * Returns 1 to let vcpu_run() continue the guest execution loop without
7921 * exiting to the userspace. Otherwise, the value will be returned to the
7924 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
7928 dm_request_for_irq_injection(vcpu) &&
7929 kvm_cpu_accept_dm_intr(vcpu);
7931 bool req_immediate_exit = false;
7933 if (kvm_request_pending(vcpu)) {
7934 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7935 kvm_x86_ops->get_vmcs12_pages(vcpu);
7936 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
7937 kvm_mmu_unload(vcpu);
7938 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
7939 __kvm_migrate_timers(vcpu);
7940 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7941 kvm_gen_update_masterclock(vcpu->kvm);
7942 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7943 kvm_gen_kvmclock_update(vcpu);
7944 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7945 r = kvm_guest_time_update(vcpu);
7949 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
7950 kvm_mmu_sync_roots(vcpu);
7951 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7952 kvm_mmu_load_cr3(vcpu);
7953 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
7954 kvm_vcpu_flush_tlb(vcpu, true);
7955 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
7956 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
7960 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
7961 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
7962 vcpu->mmio_needed = 0;
7966 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7967 /* Page is swapped out. Do synthetic halt */
7968 vcpu->arch.apf.halted = true;
7972 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7973 record_steal_time(vcpu);
7974 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7976 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7978 if (kvm_check_request(KVM_REQ_PMU, vcpu))
7979 kvm_pmu_handle_event(vcpu);
7980 if (kvm_check_request(KVM_REQ_PMI, vcpu))
7981 kvm_pmu_deliver_pmi(vcpu);
7982 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7983 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7984 if (test_bit(vcpu->arch.pending_ioapic_eoi,
7985 vcpu->arch.ioapic_handled_vectors)) {
7986 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7987 vcpu->run->eoi.vector =
7988 vcpu->arch.pending_ioapic_eoi;
7993 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7994 vcpu_scan_ioapic(vcpu);
7995 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7996 vcpu_load_eoi_exitmap(vcpu);
7997 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7998 kvm_vcpu_reload_apic_access_page(vcpu);
7999 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8000 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8001 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8005 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8006 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8007 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8011 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8012 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8013 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8019 * KVM_REQ_HV_STIMER has to be processed after
8020 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8021 * depend on the guest clock being up-to-date
8023 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8024 kvm_hv_process_stimers(vcpu);
8027 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8028 ++vcpu->stat.req_event;
8029 kvm_apic_accept_events(vcpu);
8030 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8035 if (inject_pending_event(vcpu, req_int_win) != 0)
8036 req_immediate_exit = true;
8038 /* Enable SMI/NMI/IRQ window open exits if needed.
8040 * SMIs have three cases:
8041 * 1) They can be nested, and then there is nothing to
8042 * do here because RSM will cause a vmexit anyway.
8043 * 2) There is an ISA-specific reason why SMI cannot be
8044 * injected, and the moment when this changes can be
8046 * 3) Or the SMI can be pending because
8047 * inject_pending_event has completed the injection
8048 * of an IRQ or NMI from the previous vmexit, and
8049 * then we request an immediate exit to inject the
8052 if (vcpu->arch.smi_pending && !is_smm(vcpu))
8053 if (!kvm_x86_ops->enable_smi_window(vcpu))
8054 req_immediate_exit = true;
8055 if (vcpu->arch.nmi_pending)
8056 kvm_x86_ops->enable_nmi_window(vcpu);
8057 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8058 kvm_x86_ops->enable_irq_window(vcpu);
8059 WARN_ON(vcpu->arch.exception.pending);
8062 if (kvm_lapic_enabled(vcpu)) {
8063 update_cr8_intercept(vcpu);
8064 kvm_lapic_sync_to_vapic(vcpu);
8068 r = kvm_mmu_reload(vcpu);
8070 goto cancel_injection;
8075 kvm_x86_ops->prepare_guest_switch(vcpu);
8078 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8079 * IPI are then delayed after guest entry, which ensures that they
8080 * result in virtual interrupt delivery.
8082 local_irq_disable();
8083 vcpu->mode = IN_GUEST_MODE;
8085 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8088 * 1) We should set ->mode before checking ->requests. Please see
8089 * the comment in kvm_vcpu_exiting_guest_mode().
8091 * 2) For APICv, we should set ->mode before checking PID.ON. This
8092 * pairs with the memory barrier implicit in pi_test_and_set_on
8093 * (see vmx_deliver_posted_interrupt).
8095 * 3) This also orders the write to mode from any reads to the page
8096 * tables done while the VCPU is running. Please see the comment
8097 * in kvm_flush_remote_tlbs.
8099 smp_mb__after_srcu_read_unlock();
8102 * This handles the case where a posted interrupt was
8103 * notified with kvm_vcpu_kick.
8105 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8106 kvm_x86_ops->sync_pir_to_irr(vcpu);
8108 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8109 || need_resched() || signal_pending(current)) {
8110 vcpu->mode = OUTSIDE_GUEST_MODE;
8114 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8116 goto cancel_injection;
8119 if (req_immediate_exit) {
8120 kvm_make_request(KVM_REQ_EVENT, vcpu);
8121 kvm_x86_ops->request_immediate_exit(vcpu);
8124 trace_kvm_entry(vcpu->vcpu_id);
8125 guest_enter_irqoff();
8127 /* The preempt notifier should have taken care of the FPU already. */
8128 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
8130 if (unlikely(vcpu->arch.switch_db_regs)) {
8132 set_debugreg(vcpu->arch.eff_db[0], 0);
8133 set_debugreg(vcpu->arch.eff_db[1], 1);
8134 set_debugreg(vcpu->arch.eff_db[2], 2);
8135 set_debugreg(vcpu->arch.eff_db[3], 3);
8136 set_debugreg(vcpu->arch.dr6, 6);
8137 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8140 kvm_x86_ops->run(vcpu);
8143 * Do this here before restoring debug registers on the host. And
8144 * since we do this before handling the vmexit, a DR access vmexit
8145 * can (a) read the correct value of the debug registers, (b) set
8146 * KVM_DEBUGREG_WONT_EXIT again.
8148 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8149 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8150 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8151 kvm_update_dr0123(vcpu);
8152 kvm_update_dr6(vcpu);
8153 kvm_update_dr7(vcpu);
8154 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8158 * If the guest has used debug registers, at least dr7
8159 * will be disabled while returning to the host.
8160 * If we don't have active breakpoints in the host, we don't
8161 * care about the messed up debug address registers. But if
8162 * we have some of them active, restore the old state.
8164 if (hw_breakpoint_active())
8165 hw_breakpoint_restore();
8167 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8169 vcpu->mode = OUTSIDE_GUEST_MODE;
8172 kvm_x86_ops->handle_exit_irqoff(vcpu);
8175 * Consume any pending interrupts, including the possible source of
8176 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8177 * An instruction is required after local_irq_enable() to fully unblock
8178 * interrupts on processors that implement an interrupt shadow, the
8179 * stat.exits increment will do nicely.
8181 kvm_before_interrupt(vcpu);
8184 local_irq_disable();
8185 kvm_after_interrupt(vcpu);
8187 guest_exit_irqoff();
8188 if (lapic_in_kernel(vcpu)) {
8189 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8190 if (delta != S64_MIN) {
8191 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8192 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8199 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8202 * Profile KVM exit RIPs:
8204 if (unlikely(prof_on == KVM_PROFILING)) {
8205 unsigned long rip = kvm_rip_read(vcpu);
8206 profile_hit(KVM_PROFILING, (void *)rip);
8209 if (unlikely(vcpu->arch.tsc_always_catchup))
8210 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8212 if (vcpu->arch.apic_attention)
8213 kvm_lapic_sync_from_vapic(vcpu);
8215 vcpu->arch.gpa_available = false;
8216 r = kvm_x86_ops->handle_exit(vcpu);
8220 kvm_x86_ops->cancel_injection(vcpu);
8221 if (unlikely(vcpu->arch.apic_attention))
8222 kvm_lapic_sync_from_vapic(vcpu);
8227 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8229 if (!kvm_arch_vcpu_runnable(vcpu) &&
8230 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8231 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8232 kvm_vcpu_block(vcpu);
8233 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8235 if (kvm_x86_ops->post_block)
8236 kvm_x86_ops->post_block(vcpu);
8238 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8242 kvm_apic_accept_events(vcpu);
8243 switch(vcpu->arch.mp_state) {
8244 case KVM_MP_STATE_HALTED:
8245 vcpu->arch.pv.pv_unhalted = false;
8246 vcpu->arch.mp_state =
8247 KVM_MP_STATE_RUNNABLE;
8249 case KVM_MP_STATE_RUNNABLE:
8250 vcpu->arch.apf.halted = false;
8252 case KVM_MP_STATE_INIT_RECEIVED:
8261 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8263 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8264 kvm_x86_ops->check_nested_events(vcpu, false);
8266 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8267 !vcpu->arch.apf.halted);
8270 static int vcpu_run(struct kvm_vcpu *vcpu)
8273 struct kvm *kvm = vcpu->kvm;
8275 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8276 vcpu->arch.l1tf_flush_l1d = true;
8279 if (kvm_vcpu_running(vcpu)) {
8280 r = vcpu_enter_guest(vcpu);
8282 r = vcpu_block(kvm, vcpu);
8288 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8289 if (kvm_cpu_has_pending_timer(vcpu))
8290 kvm_inject_pending_timer_irqs(vcpu);
8292 if (dm_request_for_irq_injection(vcpu) &&
8293 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8295 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8296 ++vcpu->stat.request_irq_exits;
8300 kvm_check_async_pf_completion(vcpu);
8302 if (signal_pending(current)) {
8304 vcpu->run->exit_reason = KVM_EXIT_INTR;
8305 ++vcpu->stat.signal_exits;
8308 if (need_resched()) {
8309 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8311 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8315 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8320 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8323 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8324 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8325 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8326 if (r != EMULATE_DONE)
8331 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8333 BUG_ON(!vcpu->arch.pio.count);
8335 return complete_emulated_io(vcpu);
8339 * Implements the following, as a state machine:
8343 * for each mmio piece in the fragment
8351 * for each mmio piece in the fragment
8356 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8358 struct kvm_run *run = vcpu->run;
8359 struct kvm_mmio_fragment *frag;
8362 BUG_ON(!vcpu->mmio_needed);
8364 /* Complete previous fragment */
8365 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8366 len = min(8u, frag->len);
8367 if (!vcpu->mmio_is_write)
8368 memcpy(frag->data, run->mmio.data, len);
8370 if (frag->len <= 8) {
8371 /* Switch to the next fragment. */
8373 vcpu->mmio_cur_fragment++;
8375 /* Go forward to the next mmio piece. */
8381 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8382 vcpu->mmio_needed = 0;
8384 /* FIXME: return into emulator if single-stepping. */
8385 if (vcpu->mmio_is_write)
8387 vcpu->mmio_read_completed = 1;
8388 return complete_emulated_io(vcpu);
8391 run->exit_reason = KVM_EXIT_MMIO;
8392 run->mmio.phys_addr = frag->gpa;
8393 if (vcpu->mmio_is_write)
8394 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8395 run->mmio.len = min(8u, frag->len);
8396 run->mmio.is_write = vcpu->mmio_is_write;
8397 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8401 /* Swap (qemu) user FPU context for the guest FPU context. */
8402 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8406 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
8407 /* PKRU is separately restored in kvm_x86_ops->run. */
8408 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8409 ~XFEATURE_MASK_PKRU);
8411 fpregs_mark_activate();
8417 /* When vcpu_run ends, restore user space FPU context. */
8418 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8422 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
8423 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8425 fpregs_mark_activate();
8428 ++vcpu->stat.fpu_reload;
8432 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8437 kvm_sigset_activate(vcpu);
8438 kvm_load_guest_fpu(vcpu);
8440 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8441 if (kvm_run->immediate_exit) {
8445 kvm_vcpu_block(vcpu);
8446 kvm_apic_accept_events(vcpu);
8447 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8449 if (signal_pending(current)) {
8451 vcpu->run->exit_reason = KVM_EXIT_INTR;
8452 ++vcpu->stat.signal_exits;
8457 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8462 if (vcpu->run->kvm_dirty_regs) {
8463 r = sync_regs(vcpu);
8468 /* re-sync apic's tpr */
8469 if (!lapic_in_kernel(vcpu)) {
8470 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8476 if (unlikely(vcpu->arch.complete_userspace_io)) {
8477 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8478 vcpu->arch.complete_userspace_io = NULL;
8483 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8485 if (kvm_run->immediate_exit)
8491 kvm_put_guest_fpu(vcpu);
8492 if (vcpu->run->kvm_valid_regs)
8494 post_kvm_run_save(vcpu);
8495 kvm_sigset_deactivate(vcpu);
8501 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8503 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8505 * We are here if userspace calls get_regs() in the middle of
8506 * instruction emulation. Registers state needs to be copied
8507 * back from emulation context to vcpu. Userspace shouldn't do
8508 * that usually, but some bad designed PV devices (vmware
8509 * backdoor interface) need this to work
8511 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
8512 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8514 regs->rax = kvm_rax_read(vcpu);
8515 regs->rbx = kvm_rbx_read(vcpu);
8516 regs->rcx = kvm_rcx_read(vcpu);
8517 regs->rdx = kvm_rdx_read(vcpu);
8518 regs->rsi = kvm_rsi_read(vcpu);
8519 regs->rdi = kvm_rdi_read(vcpu);
8520 regs->rsp = kvm_rsp_read(vcpu);
8521 regs->rbp = kvm_rbp_read(vcpu);
8522 #ifdef CONFIG_X86_64
8523 regs->r8 = kvm_r8_read(vcpu);
8524 regs->r9 = kvm_r9_read(vcpu);
8525 regs->r10 = kvm_r10_read(vcpu);
8526 regs->r11 = kvm_r11_read(vcpu);
8527 regs->r12 = kvm_r12_read(vcpu);
8528 regs->r13 = kvm_r13_read(vcpu);
8529 regs->r14 = kvm_r14_read(vcpu);
8530 regs->r15 = kvm_r15_read(vcpu);
8533 regs->rip = kvm_rip_read(vcpu);
8534 regs->rflags = kvm_get_rflags(vcpu);
8537 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8540 __get_regs(vcpu, regs);
8545 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8547 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8548 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8550 kvm_rax_write(vcpu, regs->rax);
8551 kvm_rbx_write(vcpu, regs->rbx);
8552 kvm_rcx_write(vcpu, regs->rcx);
8553 kvm_rdx_write(vcpu, regs->rdx);
8554 kvm_rsi_write(vcpu, regs->rsi);
8555 kvm_rdi_write(vcpu, regs->rdi);
8556 kvm_rsp_write(vcpu, regs->rsp);
8557 kvm_rbp_write(vcpu, regs->rbp);
8558 #ifdef CONFIG_X86_64
8559 kvm_r8_write(vcpu, regs->r8);
8560 kvm_r9_write(vcpu, regs->r9);
8561 kvm_r10_write(vcpu, regs->r10);
8562 kvm_r11_write(vcpu, regs->r11);
8563 kvm_r12_write(vcpu, regs->r12);
8564 kvm_r13_write(vcpu, regs->r13);
8565 kvm_r14_write(vcpu, regs->r14);
8566 kvm_r15_write(vcpu, regs->r15);
8569 kvm_rip_write(vcpu, regs->rip);
8570 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8572 vcpu->arch.exception.pending = false;
8574 kvm_make_request(KVM_REQ_EVENT, vcpu);
8577 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8580 __set_regs(vcpu, regs);
8585 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8587 struct kvm_segment cs;
8589 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8593 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8595 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8599 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8600 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8601 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8602 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8603 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8604 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8606 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8607 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8609 kvm_x86_ops->get_idt(vcpu, &dt);
8610 sregs->idt.limit = dt.size;
8611 sregs->idt.base = dt.address;
8612 kvm_x86_ops->get_gdt(vcpu, &dt);
8613 sregs->gdt.limit = dt.size;
8614 sregs->gdt.base = dt.address;
8616 sregs->cr0 = kvm_read_cr0(vcpu);
8617 sregs->cr2 = vcpu->arch.cr2;
8618 sregs->cr3 = kvm_read_cr3(vcpu);
8619 sregs->cr4 = kvm_read_cr4(vcpu);
8620 sregs->cr8 = kvm_get_cr8(vcpu);
8621 sregs->efer = vcpu->arch.efer;
8622 sregs->apic_base = kvm_get_apic_base(vcpu);
8624 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8626 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8627 set_bit(vcpu->arch.interrupt.nr,
8628 (unsigned long *)sregs->interrupt_bitmap);
8631 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8632 struct kvm_sregs *sregs)
8635 __get_sregs(vcpu, sregs);
8640 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8641 struct kvm_mp_state *mp_state)
8645 kvm_apic_accept_events(vcpu);
8646 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8647 vcpu->arch.pv.pv_unhalted)
8648 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8650 mp_state->mp_state = vcpu->arch.mp_state;
8656 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8657 struct kvm_mp_state *mp_state)
8663 if (!lapic_in_kernel(vcpu) &&
8664 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8667 /* INITs are latched while in SMM */
8668 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8669 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8670 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8673 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8674 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8675 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8677 vcpu->arch.mp_state = mp_state->mp_state;
8678 kvm_make_request(KVM_REQ_EVENT, vcpu);
8686 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8687 int reason, bool has_error_code, u32 error_code)
8689 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8692 init_emulate_ctxt(vcpu);
8694 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8695 has_error_code, error_code);
8697 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8698 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8699 vcpu->run->internal.ndata = 0;
8700 return EMULATE_USER_EXIT;
8703 kvm_rip_write(vcpu, ctxt->eip);
8704 kvm_set_rflags(vcpu, ctxt->eflags);
8705 kvm_make_request(KVM_REQ_EVENT, vcpu);
8706 return EMULATE_DONE;
8708 EXPORT_SYMBOL_GPL(kvm_task_switch);
8710 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8712 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8713 (sregs->cr4 & X86_CR4_OSXSAVE))
8716 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8718 * When EFER.LME and CR0.PG are set, the processor is in
8719 * 64-bit mode (though maybe in a 32-bit code segment).
8720 * CR4.PAE and EFER.LMA must be set.
8722 if (!(sregs->cr4 & X86_CR4_PAE)
8723 || !(sregs->efer & EFER_LMA))
8727 * Not in 64-bit mode: EFER.LMA is clear and the code
8728 * segment cannot be 64-bit.
8730 if (sregs->efer & EFER_LMA || sregs->cs.l)
8737 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8739 struct msr_data apic_base_msr;
8740 int mmu_reset_needed = 0;
8741 int cpuid_update_needed = 0;
8742 int pending_vec, max_bits, idx;
8746 if (kvm_valid_sregs(vcpu, sregs))
8749 apic_base_msr.data = sregs->apic_base;
8750 apic_base_msr.host_initiated = true;
8751 if (kvm_set_apic_base(vcpu, &apic_base_msr))
8754 dt.size = sregs->idt.limit;
8755 dt.address = sregs->idt.base;
8756 kvm_x86_ops->set_idt(vcpu, &dt);
8757 dt.size = sregs->gdt.limit;
8758 dt.address = sregs->gdt.base;
8759 kvm_x86_ops->set_gdt(vcpu, &dt);
8761 vcpu->arch.cr2 = sregs->cr2;
8762 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
8763 vcpu->arch.cr3 = sregs->cr3;
8764 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
8766 kvm_set_cr8(vcpu, sregs->cr8);
8768 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
8769 kvm_x86_ops->set_efer(vcpu, sregs->efer);
8771 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
8772 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
8773 vcpu->arch.cr0 = sregs->cr0;
8775 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
8776 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8777 (X86_CR4_OSXSAVE | X86_CR4_PKE));
8778 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
8779 if (cpuid_update_needed)
8780 kvm_update_cpuid(vcpu);
8782 idx = srcu_read_lock(&vcpu->kvm->srcu);
8783 if (is_pae_paging(vcpu)) {
8784 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
8785 mmu_reset_needed = 1;
8787 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8789 if (mmu_reset_needed)
8790 kvm_mmu_reset_context(vcpu);
8792 max_bits = KVM_NR_INTERRUPTS;
8793 pending_vec = find_first_bit(
8794 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8795 if (pending_vec < max_bits) {
8796 kvm_queue_interrupt(vcpu, pending_vec, false);
8797 pr_debug("Set back pending irq %d\n", pending_vec);
8800 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8801 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8802 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8803 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8804 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8805 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8807 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8808 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8810 update_cr8_intercept(vcpu);
8812 /* Older userspace won't unhalt the vcpu on reset. */
8813 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
8814 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
8816 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8818 kvm_make_request(KVM_REQ_EVENT, vcpu);
8825 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8826 struct kvm_sregs *sregs)
8831 ret = __set_sregs(vcpu, sregs);
8836 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8837 struct kvm_guest_debug *dbg)
8839 unsigned long rflags;
8844 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8846 if (vcpu->arch.exception.pending)
8848 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8849 kvm_queue_exception(vcpu, DB_VECTOR);
8851 kvm_queue_exception(vcpu, BP_VECTOR);
8855 * Read rflags as long as potentially injected trace flags are still
8858 rflags = kvm_get_rflags(vcpu);
8860 vcpu->guest_debug = dbg->control;
8861 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8862 vcpu->guest_debug = 0;
8864 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
8865 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8866 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
8867 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
8869 for (i = 0; i < KVM_NR_DB_REGS; i++)
8870 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
8872 kvm_update_dr7(vcpu);
8874 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8875 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8876 get_segment_base(vcpu, VCPU_SREG_CS);
8879 * Trigger an rflags update that will inject or remove the trace
8882 kvm_set_rflags(vcpu, rflags);
8884 kvm_x86_ops->update_bp_intercept(vcpu);
8894 * Translate a guest virtual address to a guest physical address.
8896 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8897 struct kvm_translation *tr)
8899 unsigned long vaddr = tr->linear_address;
8905 idx = srcu_read_lock(&vcpu->kvm->srcu);
8906 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
8907 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8908 tr->physical_address = gpa;
8909 tr->valid = gpa != UNMAPPED_GVA;
8917 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8919 struct fxregs_state *fxsave;
8923 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8924 memcpy(fpu->fpr, fxsave->st_space, 128);
8925 fpu->fcw = fxsave->cwd;
8926 fpu->fsw = fxsave->swd;
8927 fpu->ftwx = fxsave->twd;
8928 fpu->last_opcode = fxsave->fop;
8929 fpu->last_ip = fxsave->rip;
8930 fpu->last_dp = fxsave->rdp;
8931 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
8937 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8939 struct fxregs_state *fxsave;
8943 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
8945 memcpy(fxsave->st_space, fpu->fpr, 128);
8946 fxsave->cwd = fpu->fcw;
8947 fxsave->swd = fpu->fsw;
8948 fxsave->twd = fpu->ftwx;
8949 fxsave->fop = fpu->last_opcode;
8950 fxsave->rip = fpu->last_ip;
8951 fxsave->rdp = fpu->last_dp;
8952 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
8958 static void store_regs(struct kvm_vcpu *vcpu)
8960 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8962 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8963 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8965 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8966 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8968 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8969 kvm_vcpu_ioctl_x86_get_vcpu_events(
8970 vcpu, &vcpu->run->s.regs.events);
8973 static int sync_regs(struct kvm_vcpu *vcpu)
8975 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8978 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8979 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8980 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8982 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8983 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8985 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8987 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8988 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8989 vcpu, &vcpu->run->s.regs.events))
8991 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8997 static void fx_init(struct kvm_vcpu *vcpu)
8999 fpstate_init(&vcpu->arch.guest_fpu->state);
9000 if (boot_cpu_has(X86_FEATURE_XSAVES))
9001 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9002 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9005 * Ensure guest xcr0 is valid for loading
9007 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9009 vcpu->arch.cr0 |= X86_CR0_ET;
9012 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
9014 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
9016 kvmclock_reset(vcpu);
9018 kvm_x86_ops->vcpu_free(vcpu);
9019 free_cpumask_var(wbinvd_dirty_mask);
9022 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
9025 struct kvm_vcpu *vcpu;
9027 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9028 printk_once(KERN_WARNING
9029 "kvm: SMP vm created on host with unstable TSC; "
9030 "guest TSC will not be reliable\n");
9032 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
9037 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
9039 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9040 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9041 kvm_vcpu_mtrr_init(vcpu);
9043 kvm_vcpu_reset(vcpu, false);
9044 kvm_init_mmu(vcpu, false);
9049 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9051 struct msr_data msr;
9052 struct kvm *kvm = vcpu->kvm;
9054 kvm_hv_vcpu_postcreate(vcpu);
9056 if (mutex_lock_killable(&vcpu->mutex))
9060 msr.index = MSR_IA32_TSC;
9061 msr.host_initiated = true;
9062 kvm_write_tsc(vcpu, &msr);
9065 /* poll control enabled by default */
9066 vcpu->arch.msr_kvm_poll_control = 1;
9068 mutex_unlock(&vcpu->mutex);
9070 if (!kvmclock_periodic_sync)
9073 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9074 KVMCLOCK_SYNC_PERIOD);
9077 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9079 vcpu->arch.apf.msr_val = 0;
9082 kvm_mmu_unload(vcpu);
9085 kvm_x86_ops->vcpu_free(vcpu);
9088 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9090 kvm_lapic_reset(vcpu, init_event);
9092 vcpu->arch.hflags = 0;
9094 vcpu->arch.smi_pending = 0;
9095 vcpu->arch.smi_count = 0;
9096 atomic_set(&vcpu->arch.nmi_queued, 0);
9097 vcpu->arch.nmi_pending = 0;
9098 vcpu->arch.nmi_injected = false;
9099 kvm_clear_interrupt_queue(vcpu);
9100 kvm_clear_exception_queue(vcpu);
9101 vcpu->arch.exception.pending = false;
9103 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9104 kvm_update_dr0123(vcpu);
9105 vcpu->arch.dr6 = DR6_INIT;
9106 kvm_update_dr6(vcpu);
9107 vcpu->arch.dr7 = DR7_FIXED_1;
9108 kvm_update_dr7(vcpu);
9112 kvm_make_request(KVM_REQ_EVENT, vcpu);
9113 vcpu->arch.apf.msr_val = 0;
9114 vcpu->arch.st.msr_val = 0;
9116 kvmclock_reset(vcpu);
9118 kvm_clear_async_pf_completion_queue(vcpu);
9119 kvm_async_pf_hash_reset(vcpu);
9120 vcpu->arch.apf.halted = false;
9122 if (kvm_mpx_supported()) {
9123 void *mpx_state_buffer;
9126 * To avoid have the INIT path from kvm_apic_has_events() that be
9127 * called with loaded FPU and does not let userspace fix the state.
9130 kvm_put_guest_fpu(vcpu);
9131 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9133 if (mpx_state_buffer)
9134 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9135 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9137 if (mpx_state_buffer)
9138 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9140 kvm_load_guest_fpu(vcpu);
9144 kvm_pmu_reset(vcpu);
9145 vcpu->arch.smbase = 0x30000;
9147 vcpu->arch.msr_misc_features_enables = 0;
9149 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9152 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9153 vcpu->arch.regs_avail = ~0;
9154 vcpu->arch.regs_dirty = ~0;
9156 vcpu->arch.ia32_xss = 0;
9158 kvm_x86_ops->vcpu_reset(vcpu, init_event);
9161 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9163 struct kvm_segment cs;
9165 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9166 cs.selector = vector << 8;
9167 cs.base = vector << 12;
9168 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9169 kvm_rip_write(vcpu, 0);
9172 int kvm_arch_hardware_enable(void)
9175 struct kvm_vcpu *vcpu;
9180 bool stable, backwards_tsc = false;
9182 kvm_shared_msr_cpu_online();
9183 ret = kvm_x86_ops->hardware_enable();
9187 local_tsc = rdtsc();
9188 stable = !kvm_check_tsc_unstable();
9189 list_for_each_entry(kvm, &vm_list, vm_list) {
9190 kvm_for_each_vcpu(i, vcpu, kvm) {
9191 if (!stable && vcpu->cpu == smp_processor_id())
9192 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9193 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9194 backwards_tsc = true;
9195 if (vcpu->arch.last_host_tsc > max_tsc)
9196 max_tsc = vcpu->arch.last_host_tsc;
9202 * Sometimes, even reliable TSCs go backwards. This happens on
9203 * platforms that reset TSC during suspend or hibernate actions, but
9204 * maintain synchronization. We must compensate. Fortunately, we can
9205 * detect that condition here, which happens early in CPU bringup,
9206 * before any KVM threads can be running. Unfortunately, we can't
9207 * bring the TSCs fully up to date with real time, as we aren't yet far
9208 * enough into CPU bringup that we know how much real time has actually
9209 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9210 * variables that haven't been updated yet.
9212 * So we simply find the maximum observed TSC above, then record the
9213 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9214 * the adjustment will be applied. Note that we accumulate
9215 * adjustments, in case multiple suspend cycles happen before some VCPU
9216 * gets a chance to run again. In the event that no KVM threads get a
9217 * chance to run, we will miss the entire elapsed period, as we'll have
9218 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9219 * loose cycle time. This isn't too big a deal, since the loss will be
9220 * uniform across all VCPUs (not to mention the scenario is extremely
9221 * unlikely). It is possible that a second hibernate recovery happens
9222 * much faster than a first, causing the observed TSC here to be
9223 * smaller; this would require additional padding adjustment, which is
9224 * why we set last_host_tsc to the local tsc observed here.
9226 * N.B. - this code below runs only on platforms with reliable TSC,
9227 * as that is the only way backwards_tsc is set above. Also note
9228 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9229 * have the same delta_cyc adjustment applied if backwards_tsc
9230 * is detected. Note further, this adjustment is only done once,
9231 * as we reset last_host_tsc on all VCPUs to stop this from being
9232 * called multiple times (one for each physical CPU bringup).
9234 * Platforms with unreliable TSCs don't have to deal with this, they
9235 * will be compensated by the logic in vcpu_load, which sets the TSC to
9236 * catchup mode. This will catchup all VCPUs to real time, but cannot
9237 * guarantee that they stay in perfect synchronization.
9239 if (backwards_tsc) {
9240 u64 delta_cyc = max_tsc - local_tsc;
9241 list_for_each_entry(kvm, &vm_list, vm_list) {
9242 kvm->arch.backwards_tsc_observed = true;
9243 kvm_for_each_vcpu(i, vcpu, kvm) {
9244 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9245 vcpu->arch.last_host_tsc = local_tsc;
9246 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9250 * We have to disable TSC offset matching.. if you were
9251 * booting a VM while issuing an S4 host suspend....
9252 * you may have some problem. Solving this issue is
9253 * left as an exercise to the reader.
9255 kvm->arch.last_tsc_nsec = 0;
9256 kvm->arch.last_tsc_write = 0;
9263 void kvm_arch_hardware_disable(void)
9265 kvm_x86_ops->hardware_disable();
9266 drop_user_return_notifiers();
9269 int kvm_arch_hardware_setup(void)
9273 r = kvm_x86_ops->hardware_setup();
9277 if (kvm_has_tsc_control) {
9279 * Make sure the user can only configure tsc_khz values that
9280 * fit into a signed integer.
9281 * A min value is not calculated because it will always
9282 * be 1 on all machines.
9284 u64 max = min(0x7fffffffULL,
9285 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9286 kvm_max_guest_tsc_khz = max;
9288 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9291 kvm_init_msr_list();
9295 void kvm_arch_hardware_unsetup(void)
9297 kvm_x86_ops->hardware_unsetup();
9300 int kvm_arch_check_processor_compat(void)
9302 return kvm_x86_ops->check_processor_compatibility();
9305 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9307 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9309 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9311 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9313 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9316 struct static_key kvm_no_apic_vcpu __read_mostly;
9317 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9319 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9324 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9325 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9326 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9328 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9330 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9335 vcpu->arch.pio_data = page_address(page);
9337 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9339 r = kvm_mmu_create(vcpu);
9341 goto fail_free_pio_data;
9343 if (irqchip_in_kernel(vcpu->kvm)) {
9344 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9345 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9347 goto fail_mmu_destroy;
9349 static_key_slow_inc(&kvm_no_apic_vcpu);
9351 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9352 GFP_KERNEL_ACCOUNT);
9353 if (!vcpu->arch.mce_banks) {
9355 goto fail_free_lapic;
9357 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9359 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9360 GFP_KERNEL_ACCOUNT)) {
9362 goto fail_free_mce_banks;
9367 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9369 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9371 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9373 kvm_async_pf_hash_reset(vcpu);
9376 vcpu->arch.pending_external_vector = -1;
9377 vcpu->arch.preempted_in_kernel = false;
9379 kvm_hv_vcpu_init(vcpu);
9383 fail_free_mce_banks:
9384 kfree(vcpu->arch.mce_banks);
9386 kvm_free_lapic(vcpu);
9388 kvm_mmu_destroy(vcpu);
9390 free_page((unsigned long)vcpu->arch.pio_data);
9395 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9399 kvm_hv_vcpu_uninit(vcpu);
9400 kvm_pmu_destroy(vcpu);
9401 kfree(vcpu->arch.mce_banks);
9402 kvm_free_lapic(vcpu);
9403 idx = srcu_read_lock(&vcpu->kvm->srcu);
9404 kvm_mmu_destroy(vcpu);
9405 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9406 free_page((unsigned long)vcpu->arch.pio_data);
9407 if (!lapic_in_kernel(vcpu))
9408 static_key_slow_dec(&kvm_no_apic_vcpu);
9411 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9413 vcpu->arch.l1tf_flush_l1d = true;
9414 kvm_x86_ops->sched_in(vcpu, cpu);
9417 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9422 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9423 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9424 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9425 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9427 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9428 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9429 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9430 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9431 &kvm->arch.irq_sources_bitmap);
9433 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9434 mutex_init(&kvm->arch.apic_map_lock);
9435 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9437 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
9438 pvclock_update_vm_gtod_copy(kvm);
9440 kvm->arch.guest_can_read_msr_platform_info = true;
9442 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9443 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9445 kvm_hv_init_vm(kvm);
9446 kvm_page_track_init(kvm);
9447 kvm_mmu_init_vm(kvm);
9449 return kvm_x86_ops->vm_init(kvm);
9452 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9455 kvm_mmu_unload(vcpu);
9459 static void kvm_free_vcpus(struct kvm *kvm)
9462 struct kvm_vcpu *vcpu;
9465 * Unpin any mmu pages first.
9467 kvm_for_each_vcpu(i, vcpu, kvm) {
9468 kvm_clear_async_pf_completion_queue(vcpu);
9469 kvm_unload_vcpu_mmu(vcpu);
9471 kvm_for_each_vcpu(i, vcpu, kvm)
9472 kvm_arch_vcpu_free(vcpu);
9474 mutex_lock(&kvm->lock);
9475 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9476 kvm->vcpus[i] = NULL;
9478 atomic_set(&kvm->online_vcpus, 0);
9479 mutex_unlock(&kvm->lock);
9482 void kvm_arch_sync_events(struct kvm *kvm)
9484 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9485 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9489 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9493 struct kvm_memslots *slots = kvm_memslots(kvm);
9494 struct kvm_memory_slot *slot, old;
9496 /* Called with kvm->slots_lock held. */
9497 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9500 slot = id_to_memslot(slots, id);
9506 * MAP_SHARED to prevent internal slot pages from being moved
9509 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9510 MAP_SHARED | MAP_ANONYMOUS, 0);
9511 if (IS_ERR((void *)hva))
9512 return PTR_ERR((void *)hva);
9521 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9522 struct kvm_userspace_memory_region m;
9524 m.slot = id | (i << 16);
9526 m.guest_phys_addr = gpa;
9527 m.userspace_addr = hva;
9528 m.memory_size = size;
9529 r = __kvm_set_memory_region(kvm, &m);
9535 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
9539 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9541 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9545 mutex_lock(&kvm->slots_lock);
9546 r = __x86_set_memory_region(kvm, id, gpa, size);
9547 mutex_unlock(&kvm->slots_lock);
9551 EXPORT_SYMBOL_GPL(x86_set_memory_region);
9553 void kvm_arch_destroy_vm(struct kvm *kvm)
9555 if (current->mm == kvm->mm) {
9557 * Free memory regions allocated on behalf of userspace,
9558 * unless the the memory map has changed due to process exit
9561 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9562 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9563 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9565 if (kvm_x86_ops->vm_destroy)
9566 kvm_x86_ops->vm_destroy(kvm);
9567 kvm_pic_destroy(kvm);
9568 kvm_ioapic_destroy(kvm);
9569 kvm_free_vcpus(kvm);
9570 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9571 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9572 kvm_mmu_uninit_vm(kvm);
9573 kvm_page_track_cleanup(kvm);
9574 kvm_hv_destroy_vm(kvm);
9577 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
9578 struct kvm_memory_slot *dont)
9582 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9583 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
9584 kvfree(free->arch.rmap[i]);
9585 free->arch.rmap[i] = NULL;
9590 if (!dont || free->arch.lpage_info[i - 1] !=
9591 dont->arch.lpage_info[i - 1]) {
9592 kvfree(free->arch.lpage_info[i - 1]);
9593 free->arch.lpage_info[i - 1] = NULL;
9597 kvm_page_track_free_memslot(free, dont);
9600 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9601 unsigned long npages)
9605 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9606 struct kvm_lpage_info *linfo;
9611 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9612 slot->base_gfn, level) + 1;
9614 slot->arch.rmap[i] =
9615 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9616 GFP_KERNEL_ACCOUNT);
9617 if (!slot->arch.rmap[i])
9622 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9626 slot->arch.lpage_info[i - 1] = linfo;
9628 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9629 linfo[0].disallow_lpage = 1;
9630 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9631 linfo[lpages - 1].disallow_lpage = 1;
9632 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9634 * If the gfn and userspace address are not aligned wrt each
9635 * other, or if explicitly asked to, disable large page
9636 * support for this slot
9638 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9639 !kvm_largepages_enabled()) {
9642 for (j = 0; j < lpages; ++j)
9643 linfo[j].disallow_lpage = 1;
9647 if (kvm_page_track_create_memslot(slot, npages))
9653 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9654 kvfree(slot->arch.rmap[i]);
9655 slot->arch.rmap[i] = NULL;
9659 kvfree(slot->arch.lpage_info[i - 1]);
9660 slot->arch.lpage_info[i - 1] = NULL;
9665 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9668 * memslots->generation has been incremented.
9669 * mmio generation may have reached its maximum value.
9671 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9674 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9675 struct kvm_memory_slot *memslot,
9676 const struct kvm_userspace_memory_region *mem,
9677 enum kvm_mr_change change)
9682 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9683 struct kvm_memory_slot *new)
9685 /* Still write protect RO slot */
9686 if (new->flags & KVM_MEM_READONLY) {
9687 kvm_mmu_slot_remove_write_access(kvm, new);
9692 * Call kvm_x86_ops dirty logging hooks when they are valid.
9694 * kvm_x86_ops->slot_disable_log_dirty is called when:
9696 * - KVM_MR_CREATE with dirty logging is disabled
9697 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9699 * The reason is, in case of PML, we need to set D-bit for any slots
9700 * with dirty logging disabled in order to eliminate unnecessary GPA
9701 * logging in PML buffer (and potential PML buffer full VMEXT). This
9702 * guarantees leaving PML enabled during guest's lifetime won't have
9703 * any additional overhead from PML when guest is running with dirty
9704 * logging disabled for memory slots.
9706 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9707 * to dirty logging mode.
9709 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9711 * In case of write protect:
9713 * Write protect all pages for dirty logging.
9715 * All the sptes including the large sptes which point to this
9716 * slot are set to readonly. We can not create any new large
9717 * spte on this slot until the end of the logging.
9719 * See the comments in fast_page_fault().
9721 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9722 if (kvm_x86_ops->slot_enable_log_dirty)
9723 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9725 kvm_mmu_slot_remove_write_access(kvm, new);
9727 if (kvm_x86_ops->slot_disable_log_dirty)
9728 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9732 void kvm_arch_commit_memory_region(struct kvm *kvm,
9733 const struct kvm_userspace_memory_region *mem,
9734 const struct kvm_memory_slot *old,
9735 const struct kvm_memory_slot *new,
9736 enum kvm_mr_change change)
9738 if (!kvm->arch.n_requested_mmu_pages)
9739 kvm_mmu_change_mmu_pages(kvm,
9740 kvm_mmu_calculate_default_mmu_pages(kvm));
9743 * Dirty logging tracks sptes in 4k granularity, meaning that large
9744 * sptes have to be split. If live migration is successful, the guest
9745 * in the source machine will be destroyed and large sptes will be
9746 * created in the destination. However, if the guest continues to run
9747 * in the source machine (for example if live migration fails), small
9748 * sptes will remain around and cause bad performance.
9750 * Scan sptes if dirty logging has been stopped, dropping those
9751 * which can be collapsed into a single large-page spte. Later
9752 * page faults will create the large-page sptes.
9754 * There is no need to do this in any of the following cases:
9755 * CREATE: No dirty mappings will already exist.
9756 * MOVE/DELETE: The old mappings will already have been cleaned up by
9757 * kvm_arch_flush_shadow_memslot()
9759 if (change == KVM_MR_FLAGS_ONLY &&
9760 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9761 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9762 kvm_mmu_zap_collapsible_sptes(kvm, new);
9765 * Set up write protection and/or dirty logging for the new slot.
9767 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9768 * been zapped so no dirty logging staff is needed for old slot. For
9769 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9770 * new and it's also covered when dealing with the new slot.
9772 * FIXME: const-ify all uses of struct kvm_memory_slot.
9774 if (change != KVM_MR_DELETE)
9775 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
9778 void kvm_arch_flush_shadow_all(struct kvm *kvm)
9780 kvm_mmu_zap_all(kvm);
9783 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9784 struct kvm_memory_slot *slot)
9786 kvm_page_track_flush_slot(kvm, slot);
9789 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9791 return (is_guest_mode(vcpu) &&
9792 kvm_x86_ops->guest_apic_has_interrupt &&
9793 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9796 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9798 if (!list_empty_careful(&vcpu->async_pf.done))
9801 if (kvm_apic_has_events(vcpu))
9804 if (vcpu->arch.pv.pv_unhalted)
9807 if (vcpu->arch.exception.pending)
9810 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9811 (vcpu->arch.nmi_pending &&
9812 kvm_x86_ops->nmi_allowed(vcpu)))
9815 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9816 (vcpu->arch.smi_pending && !is_smm(vcpu)))
9819 if (kvm_arch_interrupt_allowed(vcpu) &&
9820 (kvm_cpu_has_interrupt(vcpu) ||
9821 kvm_guest_apic_has_interrupt(vcpu)))
9824 if (kvm_hv_has_stimer_pending(vcpu))
9830 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9832 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
9835 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9837 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9840 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9841 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9842 kvm_test_request(KVM_REQ_EVENT, vcpu))
9845 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9851 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9853 return vcpu->arch.preempted_in_kernel;
9856 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
9858 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
9861 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9863 return kvm_x86_ops->interrupt_allowed(vcpu);
9866 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
9868 if (is_64_bit_mode(vcpu))
9869 return kvm_rip_read(vcpu);
9870 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9871 kvm_rip_read(vcpu));
9873 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
9875 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9877 return kvm_get_linear_rip(vcpu) == linear_rip;
9879 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9881 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9883 unsigned long rflags;
9885 rflags = kvm_x86_ops->get_rflags(vcpu);
9886 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9887 rflags &= ~X86_EFLAGS_TF;
9890 EXPORT_SYMBOL_GPL(kvm_get_rflags);
9892 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9894 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
9895 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
9896 rflags |= X86_EFLAGS_TF;
9897 kvm_x86_ops->set_rflags(vcpu, rflags);
9900 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9902 __kvm_set_rflags(vcpu, rflags);
9903 kvm_make_request(KVM_REQ_EVENT, vcpu);
9905 EXPORT_SYMBOL_GPL(kvm_set_rflags);
9907 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9911 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
9915 r = kvm_mmu_reload(vcpu);
9919 if (!vcpu->arch.mmu->direct_map &&
9920 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
9923 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
9926 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9928 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9931 static inline u32 kvm_async_pf_next_probe(u32 key)
9933 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9936 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9938 u32 key = kvm_async_pf_hash_fn(gfn);
9940 while (vcpu->arch.apf.gfns[key] != ~0)
9941 key = kvm_async_pf_next_probe(key);
9943 vcpu->arch.apf.gfns[key] = gfn;
9946 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9949 u32 key = kvm_async_pf_hash_fn(gfn);
9951 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
9952 (vcpu->arch.apf.gfns[key] != gfn &&
9953 vcpu->arch.apf.gfns[key] != ~0); i++)
9954 key = kvm_async_pf_next_probe(key);
9959 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9961 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9964 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9968 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9970 vcpu->arch.apf.gfns[i] = ~0;
9972 j = kvm_async_pf_next_probe(j);
9973 if (vcpu->arch.apf.gfns[j] == ~0)
9975 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9977 * k lies cyclically in ]i,j]
9979 * |....j i.k.| or |.k..j i...|
9981 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9982 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9987 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9990 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9994 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9997 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10001 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10003 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10006 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10007 (vcpu->arch.apf.send_user_only &&
10008 kvm_x86_ops->get_cpl(vcpu) == 0))
10014 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10016 if (unlikely(!lapic_in_kernel(vcpu) ||
10017 kvm_event_needs_reinjection(vcpu) ||
10018 vcpu->arch.exception.pending))
10021 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10025 * If interrupts are off we cannot even use an artificial
10028 return kvm_x86_ops->interrupt_allowed(vcpu);
10031 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10032 struct kvm_async_pf *work)
10034 struct x86_exception fault;
10036 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
10037 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10039 if (kvm_can_deliver_async_pf(vcpu) &&
10040 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10041 fault.vector = PF_VECTOR;
10042 fault.error_code_valid = true;
10043 fault.error_code = 0;
10044 fault.nested_page_fault = false;
10045 fault.address = work->arch.token;
10046 fault.async_page_fault = true;
10047 kvm_inject_page_fault(vcpu, &fault);
10050 * It is not possible to deliver a paravirtualized asynchronous
10051 * page fault, but putting the guest in an artificial halt state
10052 * can be beneficial nevertheless: if an interrupt arrives, we
10053 * can deliver it timely and perhaps the guest will schedule
10054 * another process. When the instruction that triggered a page
10055 * fault is retried, hopefully the page will be ready in the host.
10057 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10061 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10062 struct kvm_async_pf *work)
10064 struct x86_exception fault;
10067 if (work->wakeup_all)
10068 work->arch.token = ~0; /* broadcast wakeup */
10070 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10071 trace_kvm_async_pf_ready(work->arch.token, work->gva);
10073 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10074 !apf_get_user(vcpu, &val)) {
10075 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10076 vcpu->arch.exception.pending &&
10077 vcpu->arch.exception.nr == PF_VECTOR &&
10078 !apf_put_user(vcpu, 0)) {
10079 vcpu->arch.exception.injected = false;
10080 vcpu->arch.exception.pending = false;
10081 vcpu->arch.exception.nr = 0;
10082 vcpu->arch.exception.has_error_code = false;
10083 vcpu->arch.exception.error_code = 0;
10084 vcpu->arch.exception.has_payload = false;
10085 vcpu->arch.exception.payload = 0;
10086 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10087 fault.vector = PF_VECTOR;
10088 fault.error_code_valid = true;
10089 fault.error_code = 0;
10090 fault.nested_page_fault = false;
10091 fault.address = work->arch.token;
10092 fault.async_page_fault = true;
10093 kvm_inject_page_fault(vcpu, &fault);
10096 vcpu->arch.apf.halted = false;
10097 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10100 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10102 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10105 return kvm_can_do_async_pf(vcpu);
10108 void kvm_arch_start_assignment(struct kvm *kvm)
10110 atomic_inc(&kvm->arch.assigned_device_count);
10112 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10114 void kvm_arch_end_assignment(struct kvm *kvm)
10116 atomic_dec(&kvm->arch.assigned_device_count);
10118 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10120 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10122 return atomic_read(&kvm->arch.assigned_device_count);
10124 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10126 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10128 atomic_inc(&kvm->arch.noncoherent_dma_count);
10130 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10132 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10134 atomic_dec(&kvm->arch.noncoherent_dma_count);
10136 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10138 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10140 return atomic_read(&kvm->arch.noncoherent_dma_count);
10142 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10144 bool kvm_arch_has_irq_bypass(void)
10149 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10150 struct irq_bypass_producer *prod)
10152 struct kvm_kernel_irqfd *irqfd =
10153 container_of(cons, struct kvm_kernel_irqfd, consumer);
10155 irqfd->producer = prod;
10157 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10158 prod->irq, irqfd->gsi, 1);
10161 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10162 struct irq_bypass_producer *prod)
10165 struct kvm_kernel_irqfd *irqfd =
10166 container_of(cons, struct kvm_kernel_irqfd, consumer);
10168 WARN_ON(irqfd->producer != prod);
10169 irqfd->producer = NULL;
10172 * When producer of consumer is unregistered, we change back to
10173 * remapped mode, so we can re-use the current implementation
10174 * when the irq is masked/disabled or the consumer side (KVM
10175 * int this case doesn't want to receive the interrupts.
10177 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10179 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10180 " fails: %d\n", irqfd->consumer.token, ret);
10183 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10184 uint32_t guest_irq, bool set)
10186 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10189 bool kvm_vector_hashing_enabled(void)
10191 return vector_hashing;
10193 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10195 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10197 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10199 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10202 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10203 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10204 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10205 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10206 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10207 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10208 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10209 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10210 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10211 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10212 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10213 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10214 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10215 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10216 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10217 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10218 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10219 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10220 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10221 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);