1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/kvm_host.h>
26 #include "kvm_cache_regs.h"
27 #include "kvm_emulate.h"
36 #include <linux/clocksource.h>
37 #include <linux/interrupt.h>
38 #include <linux/kvm.h>
40 #include <linux/vmalloc.h>
41 #include <linux/export.h>
42 #include <linux/moduleparam.h>
43 #include <linux/mman.h>
44 #include <linux/highmem.h>
45 #include <linux/iommu.h>
46 #include <linux/cpufreq.h>
47 #include <linux/user-return-notifier.h>
48 #include <linux/srcu.h>
49 #include <linux/slab.h>
50 #include <linux/perf_event.h>
51 #include <linux/uaccess.h>
52 #include <linux/hash.h>
53 #include <linux/pci.h>
54 #include <linux/timekeeper_internal.h>
55 #include <linux/pvclock_gtod.h>
56 #include <linux/kvm_irqfd.h>
57 #include <linux/irqbypass.h>
58 #include <linux/sched/stat.h>
59 #include <linux/sched/isolation.h>
60 #include <linux/mem_encrypt.h>
61 #include <linux/entry-kvm.h>
62 #include <linux/suspend.h>
63 #include <linux/smp.h>
65 #include <trace/events/ipi.h>
66 #include <trace/events/kvm.h>
68 #include <asm/debugreg.h>
73 #include <linux/kernel_stat.h>
74 #include <asm/fpu/api.h>
75 #include <asm/fpu/xcr.h>
76 #include <asm/fpu/xstate.h>
77 #include <asm/pvclock.h>
78 #include <asm/div64.h>
79 #include <asm/irq_remapping.h>
80 #include <asm/mshyperv.h>
81 #include <asm/hypervisor.h>
82 #include <asm/tlbflush.h>
83 #include <asm/intel_pt.h>
84 #include <asm/emulate_prefix.h>
86 #include <clocksource/hyperv_timer.h>
88 #define CREATE_TRACE_POINTS
91 #define MAX_IO_MSRS 256
92 #define KVM_MAX_MCE_BANKS 32
94 struct kvm_caps kvm_caps __read_mostly = {
95 .supported_mce_cap = MCG_CTL_P | MCG_SER_P,
97 EXPORT_SYMBOL_GPL(kvm_caps);
99 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
101 #define emul_to_vcpu(ctxt) \
102 ((struct kvm_vcpu *)(ctxt)->vcpu)
105 * - enable syscall per default because its emulated by KVM
106 * - enable LME and LMA per default on 64 bit KVM
110 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
112 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
115 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
117 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
119 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
121 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
122 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
124 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
125 static void process_nmi(struct kvm_vcpu *vcpu);
126 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
127 static void store_regs(struct kvm_vcpu *vcpu);
128 static int sync_regs(struct kvm_vcpu *vcpu);
129 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
131 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
132 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
134 static DEFINE_MUTEX(vendor_module_lock);
135 struct kvm_x86_ops kvm_x86_ops __read_mostly;
137 #define KVM_X86_OP(func) \
138 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
139 *(((struct kvm_x86_ops *)0)->func));
140 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
141 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
142 #include <asm/kvm-x86-ops.h>
143 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
144 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
146 static bool __read_mostly ignore_msrs = 0;
147 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
149 bool __read_mostly report_ignored_msrs = true;
150 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
151 EXPORT_SYMBOL_GPL(report_ignored_msrs);
153 unsigned int min_timer_period_us = 200;
154 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
156 static bool __read_mostly kvmclock_periodic_sync = true;
157 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
159 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
160 static u32 __read_mostly tsc_tolerance_ppm = 250;
161 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
164 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
165 * adaptive tuning starting from default advancement of 1000ns. '0' disables
166 * advancement entirely. Any other value is used as-is and disables adaptive
167 * tuning, i.e. allows privileged userspace to set an exact advancement time.
169 static int __read_mostly lapic_timer_advance_ns = -1;
170 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
172 static bool __read_mostly vector_hashing = true;
173 module_param(vector_hashing, bool, S_IRUGO);
175 bool __read_mostly enable_vmware_backdoor = false;
176 module_param(enable_vmware_backdoor, bool, S_IRUGO);
177 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
180 * Flags to manipulate forced emulation behavior (any non-zero value will
181 * enable forced emulation).
183 #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1)
184 static int __read_mostly force_emulation_prefix;
185 module_param(force_emulation_prefix, int, 0644);
187 int __read_mostly pi_inject_timer = -1;
188 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
190 /* Enable/disable PMU virtualization */
191 bool __read_mostly enable_pmu = true;
192 EXPORT_SYMBOL_GPL(enable_pmu);
193 module_param(enable_pmu, bool, 0444);
195 bool __read_mostly eager_page_split = true;
196 module_param(eager_page_split, bool, 0644);
198 /* Enable/disable SMT_RSB bug mitigation */
199 static bool __read_mostly mitigate_smt_rsb;
200 module_param(mitigate_smt_rsb, bool, 0444);
203 * Restoring the host value for MSRs that are only consumed when running in
204 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
205 * returns to userspace, i.e. the kernel can run with the guest's value.
207 #define KVM_MAX_NR_USER_RETURN_MSRS 16
209 struct kvm_user_return_msrs {
210 struct user_return_notifier urn;
212 struct kvm_user_return_msr_values {
215 } values[KVM_MAX_NR_USER_RETURN_MSRS];
218 u32 __read_mostly kvm_nr_uret_msrs;
219 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
220 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
221 static struct kvm_user_return_msrs __percpu *user_return_msrs;
223 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
224 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
225 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
226 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
228 u64 __read_mostly host_efer;
229 EXPORT_SYMBOL_GPL(host_efer);
231 bool __read_mostly allow_smaller_maxphyaddr = 0;
232 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
234 bool __read_mostly enable_apicv = true;
235 EXPORT_SYMBOL_GPL(enable_apicv);
237 u64 __read_mostly host_xss;
238 EXPORT_SYMBOL_GPL(host_xss);
240 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
241 KVM_GENERIC_VM_STATS(),
242 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
243 STATS_DESC_COUNTER(VM, mmu_pte_write),
244 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
245 STATS_DESC_COUNTER(VM, mmu_flooded),
246 STATS_DESC_COUNTER(VM, mmu_recycled),
247 STATS_DESC_COUNTER(VM, mmu_cache_miss),
248 STATS_DESC_ICOUNTER(VM, mmu_unsync),
249 STATS_DESC_ICOUNTER(VM, pages_4k),
250 STATS_DESC_ICOUNTER(VM, pages_2m),
251 STATS_DESC_ICOUNTER(VM, pages_1g),
252 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
253 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
254 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
257 const struct kvm_stats_header kvm_vm_stats_header = {
258 .name_size = KVM_STATS_NAME_SIZE,
259 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
260 .id_offset = sizeof(struct kvm_stats_header),
261 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
262 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
263 sizeof(kvm_vm_stats_desc),
266 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
267 KVM_GENERIC_VCPU_STATS(),
268 STATS_DESC_COUNTER(VCPU, pf_taken),
269 STATS_DESC_COUNTER(VCPU, pf_fixed),
270 STATS_DESC_COUNTER(VCPU, pf_emulate),
271 STATS_DESC_COUNTER(VCPU, pf_spurious),
272 STATS_DESC_COUNTER(VCPU, pf_fast),
273 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created),
274 STATS_DESC_COUNTER(VCPU, pf_guest),
275 STATS_DESC_COUNTER(VCPU, tlb_flush),
276 STATS_DESC_COUNTER(VCPU, invlpg),
277 STATS_DESC_COUNTER(VCPU, exits),
278 STATS_DESC_COUNTER(VCPU, io_exits),
279 STATS_DESC_COUNTER(VCPU, mmio_exits),
280 STATS_DESC_COUNTER(VCPU, signal_exits),
281 STATS_DESC_COUNTER(VCPU, irq_window_exits),
282 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
283 STATS_DESC_COUNTER(VCPU, l1d_flush),
284 STATS_DESC_COUNTER(VCPU, halt_exits),
285 STATS_DESC_COUNTER(VCPU, request_irq_exits),
286 STATS_DESC_COUNTER(VCPU, irq_exits),
287 STATS_DESC_COUNTER(VCPU, host_state_reload),
288 STATS_DESC_COUNTER(VCPU, fpu_reload),
289 STATS_DESC_COUNTER(VCPU, insn_emulation),
290 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
291 STATS_DESC_COUNTER(VCPU, hypercalls),
292 STATS_DESC_COUNTER(VCPU, irq_injections),
293 STATS_DESC_COUNTER(VCPU, nmi_injections),
294 STATS_DESC_COUNTER(VCPU, req_event),
295 STATS_DESC_COUNTER(VCPU, nested_run),
296 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
297 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
298 STATS_DESC_COUNTER(VCPU, preemption_reported),
299 STATS_DESC_COUNTER(VCPU, preemption_other),
300 STATS_DESC_IBOOLEAN(VCPU, guest_mode),
301 STATS_DESC_COUNTER(VCPU, notify_window_exits),
304 const struct kvm_stats_header kvm_vcpu_stats_header = {
305 .name_size = KVM_STATS_NAME_SIZE,
306 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
307 .id_offset = sizeof(struct kvm_stats_header),
308 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
309 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
310 sizeof(kvm_vcpu_stats_desc),
313 u64 __read_mostly host_xcr0;
315 static struct kmem_cache *x86_emulator_cache;
318 * When called, it means the previous get/set msr reached an invalid msr.
319 * Return true if we want to ignore/silent this failed msr access.
321 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
323 const char *op = write ? "wrmsr" : "rdmsr";
326 if (report_ignored_msrs)
327 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
332 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
338 static struct kmem_cache *kvm_alloc_emulator_cache(void)
340 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
341 unsigned int size = sizeof(struct x86_emulate_ctxt);
343 return kmem_cache_create_usercopy("x86_emulator", size,
344 __alignof__(struct x86_emulate_ctxt),
345 SLAB_ACCOUNT, useroffset,
346 size - useroffset, NULL);
349 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
351 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
354 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
355 vcpu->arch.apf.gfns[i] = ~0;
358 static void kvm_on_user_return(struct user_return_notifier *urn)
361 struct kvm_user_return_msrs *msrs
362 = container_of(urn, struct kvm_user_return_msrs, urn);
363 struct kvm_user_return_msr_values *values;
367 * Disabling irqs at this point since the following code could be
368 * interrupted and executed through kvm_arch_hardware_disable()
370 local_irq_save(flags);
371 if (msrs->registered) {
372 msrs->registered = false;
373 user_return_notifier_unregister(urn);
375 local_irq_restore(flags);
376 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
377 values = &msrs->values[slot];
378 if (values->host != values->curr) {
379 wrmsrl(kvm_uret_msrs_list[slot], values->host);
380 values->curr = values->host;
385 static int kvm_probe_user_return_msr(u32 msr)
391 ret = rdmsrl_safe(msr, &val);
394 ret = wrmsrl_safe(msr, val);
400 int kvm_add_user_return_msr(u32 msr)
402 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
404 if (kvm_probe_user_return_msr(msr))
407 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
408 return kvm_nr_uret_msrs++;
410 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
412 int kvm_find_user_return_msr(u32 msr)
416 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
417 if (kvm_uret_msrs_list[i] == msr)
422 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
424 static void kvm_user_return_msr_cpu_online(void)
426 unsigned int cpu = smp_processor_id();
427 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
431 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
432 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
433 msrs->values[i].host = value;
434 msrs->values[i].curr = value;
438 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
440 unsigned int cpu = smp_processor_id();
441 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
444 value = (value & mask) | (msrs->values[slot].host & ~mask);
445 if (value == msrs->values[slot].curr)
447 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
451 msrs->values[slot].curr = value;
452 if (!msrs->registered) {
453 msrs->urn.on_user_return = kvm_on_user_return;
454 user_return_notifier_register(&msrs->urn);
455 msrs->registered = true;
459 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
461 static void drop_user_return_notifiers(void)
463 unsigned int cpu = smp_processor_id();
464 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
466 if (msrs->registered)
467 kvm_on_user_return(&msrs->urn);
470 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
472 return vcpu->arch.apic_base;
475 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
477 return kvm_apic_mode(kvm_get_apic_base(vcpu));
479 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
481 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
483 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
484 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
485 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
486 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
488 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
490 if (!msr_info->host_initiated) {
491 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
493 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
497 kvm_lapic_set_base(vcpu, msr_info->data);
498 kvm_recalculate_apic_map(vcpu->kvm);
503 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
505 * Hardware virtualization extension instructions may fault if a reboot turns
506 * off virtualization while processes are running. Usually after catching the
507 * fault we just panic; during reboot instead the instruction is ignored.
509 noinstr void kvm_spurious_fault(void)
511 /* Fault while not rebooting. We want the trace. */
512 BUG_ON(!kvm_rebooting);
514 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
516 #define EXCPT_BENIGN 0
517 #define EXCPT_CONTRIBUTORY 1
520 static int exception_class(int vector)
530 return EXCPT_CONTRIBUTORY;
537 #define EXCPT_FAULT 0
539 #define EXCPT_ABORT 2
540 #define EXCPT_INTERRUPT 3
543 static int exception_type(int vector)
547 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
548 return EXCPT_INTERRUPT;
553 * #DBs can be trap-like or fault-like, the caller must check other CPU
554 * state, e.g. DR6, to determine whether a #DB is a trap or fault.
556 if (mask & (1 << DB_VECTOR))
559 if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR)))
562 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
565 /* Reserved exceptions will result in fault */
569 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
570 struct kvm_queued_exception *ex)
572 if (!ex->has_payload)
575 switch (ex->vector) {
578 * "Certain debug exceptions may clear bit 0-3. The
579 * remaining contents of the DR6 register are never
580 * cleared by the processor".
582 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
584 * In order to reflect the #DB exception payload in guest
585 * dr6, three components need to be considered: active low
586 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
588 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
589 * In the target guest dr6:
590 * FIXED_1 bits should always be set.
591 * Active low bits should be cleared if 1-setting in payload.
592 * Active high bits should be set if 1-setting in payload.
594 * Note, the payload is compatible with the pending debug
595 * exceptions/exit qualification under VMX, that active_low bits
596 * are active high in payload.
597 * So they need to be flipped for DR6.
599 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
600 vcpu->arch.dr6 |= ex->payload;
601 vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW;
604 * The #DB payload is defined as compatible with the 'pending
605 * debug exceptions' field under VMX, not DR6. While bit 12 is
606 * defined in the 'pending debug exceptions' field (enabled
607 * breakpoint), it is reserved and must be zero in DR6.
609 vcpu->arch.dr6 &= ~BIT(12);
612 vcpu->arch.cr2 = ex->payload;
616 ex->has_payload = false;
619 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
621 static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector,
622 bool has_error_code, u32 error_code,
623 bool has_payload, unsigned long payload)
625 struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit;
628 ex->injected = false;
630 ex->has_error_code = has_error_code;
631 ex->error_code = error_code;
632 ex->has_payload = has_payload;
633 ex->payload = payload;
636 /* Forcibly leave the nested mode in cases like a vCPU reset */
637 static void kvm_leave_nested(struct kvm_vcpu *vcpu)
639 kvm_x86_ops.nested_ops->leave_nested(vcpu);
642 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
643 unsigned nr, bool has_error, u32 error_code,
644 bool has_payload, unsigned long payload, bool reinject)
649 kvm_make_request(KVM_REQ_EVENT, vcpu);
652 * If the exception is destined for L2 and isn't being reinjected,
653 * morph it to a VM-Exit if L1 wants to intercept the exception. A
654 * previously injected exception is not checked because it was checked
655 * when it was original queued, and re-checking is incorrect if _L1_
656 * injected the exception, in which case it's exempt from interception.
658 if (!reinject && is_guest_mode(vcpu) &&
659 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) {
660 kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code,
661 has_payload, payload);
665 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
669 * On VM-Entry, an exception can be pending if and only
670 * if event injection was blocked by nested_run_pending.
671 * In that case, however, vcpu_enter_guest() requests an
672 * immediate exit, and the guest shouldn't proceed far
673 * enough to need reinjection.
675 WARN_ON_ONCE(kvm_is_exception_pending(vcpu));
676 vcpu->arch.exception.injected = true;
677 if (WARN_ON_ONCE(has_payload)) {
679 * A reinjected event has already
680 * delivered its payload.
686 vcpu->arch.exception.pending = true;
687 vcpu->arch.exception.injected = false;
689 vcpu->arch.exception.has_error_code = has_error;
690 vcpu->arch.exception.vector = nr;
691 vcpu->arch.exception.error_code = error_code;
692 vcpu->arch.exception.has_payload = has_payload;
693 vcpu->arch.exception.payload = payload;
694 if (!is_guest_mode(vcpu))
695 kvm_deliver_exception_payload(vcpu,
696 &vcpu->arch.exception);
700 /* to check exception */
701 prev_nr = vcpu->arch.exception.vector;
702 if (prev_nr == DF_VECTOR) {
703 /* triple fault -> shutdown */
704 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
707 class1 = exception_class(prev_nr);
708 class2 = exception_class(nr);
709 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) ||
710 (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
712 * Synthesize #DF. Clear the previously injected or pending
713 * exception so as not to incorrectly trigger shutdown.
715 vcpu->arch.exception.injected = false;
716 vcpu->arch.exception.pending = false;
718 kvm_queue_exception_e(vcpu, DF_VECTOR, 0);
720 /* replace previous exception with a new one in a hope
721 that instruction re-execution will regenerate lost
727 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
729 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
731 EXPORT_SYMBOL_GPL(kvm_queue_exception);
733 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
735 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
737 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
739 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
740 unsigned long payload)
742 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
744 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
746 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
747 u32 error_code, unsigned long payload)
749 kvm_multiple_exception(vcpu, nr, true, error_code,
750 true, payload, false);
753 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
756 kvm_inject_gp(vcpu, 0);
758 return kvm_skip_emulated_instruction(vcpu);
762 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
764 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
767 kvm_inject_gp(vcpu, 0);
771 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
772 EMULTYPE_COMPLETE_USER_EXIT);
775 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
777 ++vcpu->stat.pf_guest;
780 * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of
781 * whether or not L1 wants to intercept "regular" #PF.
783 if (is_guest_mode(vcpu) && fault->async_page_fault)
784 kvm_queue_exception_vmexit(vcpu, PF_VECTOR,
785 true, fault->error_code,
786 true, fault->address);
788 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
792 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
793 struct x86_exception *fault)
795 struct kvm_mmu *fault_mmu;
796 WARN_ON_ONCE(fault->vector != PF_VECTOR);
798 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
802 * Invalidate the TLB entry for the faulting address, if it exists,
803 * else the access will fault indefinitely (and to emulate hardware).
805 if ((fault->error_code & PFERR_PRESENT_MASK) &&
806 !(fault->error_code & PFERR_RSVD_MASK))
807 kvm_mmu_invalidate_addr(vcpu, fault_mmu, fault->address,
808 KVM_MMU_ROOT_CURRENT);
810 fault_mmu->inject_page_fault(vcpu, fault);
812 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
814 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
816 atomic_inc(&vcpu->arch.nmi_queued);
817 kvm_make_request(KVM_REQ_NMI, vcpu);
820 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
822 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
824 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
826 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
828 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
830 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
833 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
834 * a #GP and return false.
836 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
838 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
840 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
844 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
846 if ((dr != 4 && dr != 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE))
849 kvm_queue_exception(vcpu, UD_VECTOR);
852 EXPORT_SYMBOL_GPL(kvm_require_dr);
854 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
856 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
860 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
862 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
864 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
865 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
869 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
872 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
875 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
876 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
877 if (real_gpa == INVALID_GPA)
880 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
881 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
882 cr3 & GENMASK(11, 5), sizeof(pdpte));
886 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
887 if ((pdpte[i] & PT_PRESENT_MASK) &&
888 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
894 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
895 * Shadow page roots need to be reconstructed instead.
897 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
898 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
900 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
901 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
902 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
903 vcpu->arch.pdptrs_from_userspace = false;
907 EXPORT_SYMBOL_GPL(load_pdptrs);
909 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
912 * CR0.WP is incorporated into the MMU role, but only for non-nested,
913 * indirect shadow MMUs. If paging is disabled, no updates are needed
914 * as there are no permission bits to emulate. If TDP is enabled, the
915 * MMU's metadata needs to be updated, e.g. so that emulating guest
916 * translations does the right thing, but there's no need to unload the
917 * root as CR0.WP doesn't affect SPTEs.
919 if ((cr0 ^ old_cr0) == X86_CR0_WP) {
920 if (!(cr0 & X86_CR0_PG))
929 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
930 kvm_clear_async_pf_completion_queue(vcpu);
931 kvm_async_pf_hash_reset(vcpu);
934 * Clearing CR0.PG is defined to flush the TLB from the guest's
937 if (!(cr0 & X86_CR0_PG))
938 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
941 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
942 kvm_mmu_reset_context(vcpu);
944 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
945 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
946 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
947 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
949 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
951 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
953 unsigned long old_cr0 = kvm_read_cr0(vcpu);
958 if (cr0 & 0xffffffff00000000UL)
962 cr0 &= ~CR0_RESERVED_BITS;
964 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
967 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
971 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
972 (cr0 & X86_CR0_PG)) {
977 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
982 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
983 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
984 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
987 if (!(cr0 & X86_CR0_PG) &&
988 (is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)))
991 static_call(kvm_x86_set_cr0)(vcpu, cr0);
993 kvm_post_set_cr0(vcpu, old_cr0, cr0);
997 EXPORT_SYMBOL_GPL(kvm_set_cr0);
999 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
1001 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
1003 EXPORT_SYMBOL_GPL(kvm_lmsw);
1005 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
1007 if (vcpu->arch.guest_state_protected)
1010 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1012 if (vcpu->arch.xcr0 != host_xcr0)
1013 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
1015 if (vcpu->arch.xsaves_enabled &&
1016 vcpu->arch.ia32_xss != host_xss)
1017 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
1020 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
1021 if (static_cpu_has(X86_FEATURE_PKU) &&
1022 vcpu->arch.pkru != vcpu->arch.host_pkru &&
1023 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1024 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)))
1025 write_pkru(vcpu->arch.pkru);
1026 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
1028 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
1030 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
1032 if (vcpu->arch.guest_state_protected)
1035 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
1036 if (static_cpu_has(X86_FEATURE_PKU) &&
1037 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1038 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) {
1039 vcpu->arch.pkru = rdpkru();
1040 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
1041 write_pkru(vcpu->arch.host_pkru);
1043 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
1045 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1047 if (vcpu->arch.xcr0 != host_xcr0)
1048 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
1050 if (vcpu->arch.xsaves_enabled &&
1051 vcpu->arch.ia32_xss != host_xss)
1052 wrmsrl(MSR_IA32_XSS, host_xss);
1056 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1058 #ifdef CONFIG_X86_64
1059 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1061 return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC;
1065 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1068 u64 old_xcr0 = vcpu->arch.xcr0;
1071 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1072 if (index != XCR_XFEATURE_ENABLED_MASK)
1074 if (!(xcr0 & XFEATURE_MASK_FP))
1076 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1080 * Do not allow the guest to set bits that we do not support
1081 * saving. However, xcr0 bit 0 is always set, even if the
1082 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1084 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
1085 if (xcr0 & ~valid_bits)
1088 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1089 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1092 if (xcr0 & XFEATURE_MASK_AVX512) {
1093 if (!(xcr0 & XFEATURE_MASK_YMM))
1095 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1099 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1100 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1103 vcpu->arch.xcr0 = xcr0;
1105 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1106 kvm_update_cpuid_runtime(vcpu);
1110 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1112 /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
1113 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1114 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1115 kvm_inject_gp(vcpu, 0);
1119 return kvm_skip_emulated_instruction(vcpu);
1121 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1123 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1125 if (cr4 & cr4_reserved_bits)
1128 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1133 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4);
1135 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1137 return __kvm_is_valid_cr4(vcpu, cr4) &&
1138 static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1141 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1143 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1144 kvm_mmu_reset_context(vcpu);
1147 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1148 * according to the SDM; however, stale prev_roots could be reused
1149 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1150 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1151 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1155 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1156 kvm_mmu_unload(vcpu);
1159 * The TLB has to be flushed for all PCIDs if any of the following
1160 * (architecturally required) changes happen:
1161 * - CR4.PCIDE is changed from 1 to 0
1162 * - CR4.PGE is toggled
1164 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1166 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1167 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1168 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1171 * The TLB has to be flushed for the current PCID if any of the
1172 * following (architecturally required) changes happen:
1173 * - CR4.SMEP is changed from 0 to 1
1174 * - CR4.PAE is toggled
1176 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1177 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1178 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1181 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1183 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1185 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1187 if (!kvm_is_valid_cr4(vcpu, cr4))
1190 if (is_long_mode(vcpu)) {
1191 if (!(cr4 & X86_CR4_PAE))
1193 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1195 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1196 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1197 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1200 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1201 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1202 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1206 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1208 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1212 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1214 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1216 struct kvm_mmu *mmu = vcpu->arch.mmu;
1217 unsigned long roots_to_free = 0;
1221 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1222 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1223 * also via the emulator. KVM's TDP page tables are not in the scope of
1224 * the invalidation, but the guest's TLB entries need to be flushed as
1225 * the CPU may have cached entries in its TLB for the target PCID.
1227 if (unlikely(tdp_enabled)) {
1228 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1233 * If neither the current CR3 nor any of the prev_roots use the given
1234 * PCID, then nothing needs to be done here because a resync will
1235 * happen anyway before switching to any other CR3.
1237 if (kvm_get_active_pcid(vcpu) == pcid) {
1238 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1239 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1243 * If PCID is disabled, there is no need to free prev_roots even if the
1244 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1247 if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))
1250 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1251 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1252 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1254 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1257 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1259 bool skip_tlb_flush = false;
1260 unsigned long pcid = 0;
1261 #ifdef CONFIG_X86_64
1262 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) {
1263 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1264 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1265 pcid = cr3 & X86_CR3_PCID_MASK;
1269 /* PDPTRs are always reloaded for PAE paging. */
1270 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1271 goto handle_tlb_flush;
1274 * Do not condition the GPA check on long mode, this helper is used to
1275 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1276 * the current vCPU mode is accurate.
1278 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1281 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1284 if (cr3 != kvm_read_cr3(vcpu))
1285 kvm_mmu_new_pgd(vcpu, cr3);
1287 vcpu->arch.cr3 = cr3;
1288 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1289 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1293 * A load of CR3 that flushes the TLB flushes only the current PCID,
1294 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1295 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1296 * and it's impossible to use a non-zero PCID when PCID is disabled,
1297 * i.e. only PCID=0 can be relevant.
1299 if (!skip_tlb_flush)
1300 kvm_invalidate_pcid(vcpu, pcid);
1304 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1306 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1308 if (cr8 & CR8_RESERVED_BITS)
1310 if (lapic_in_kernel(vcpu))
1311 kvm_lapic_set_tpr(vcpu, cr8);
1313 vcpu->arch.cr8 = cr8;
1316 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1318 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1320 if (lapic_in_kernel(vcpu))
1321 return kvm_lapic_get_cr8(vcpu);
1323 return vcpu->arch.cr8;
1325 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1327 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1331 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1332 for (i = 0; i < KVM_NR_DB_REGS; i++)
1333 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1337 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1341 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1342 dr7 = vcpu->arch.guest_debug_dr7;
1344 dr7 = vcpu->arch.dr7;
1345 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1346 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1347 if (dr7 & DR7_BP_EN_MASK)
1348 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1350 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1352 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1354 u64 fixed = DR6_FIXED_1;
1356 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1359 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1360 fixed |= DR6_BUS_LOCK;
1364 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1366 size_t size = ARRAY_SIZE(vcpu->arch.db);
1370 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1371 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1372 vcpu->arch.eff_db[dr] = val;
1376 if (!kvm_dr6_valid(val))
1378 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1382 if (!kvm_dr7_valid(val))
1384 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1385 kvm_update_dr7(vcpu);
1391 EXPORT_SYMBOL_GPL(kvm_set_dr);
1393 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1395 size_t size = ARRAY_SIZE(vcpu->arch.db);
1399 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1403 *val = vcpu->arch.dr6;
1407 *val = vcpu->arch.dr7;
1411 EXPORT_SYMBOL_GPL(kvm_get_dr);
1413 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1415 u32 ecx = kvm_rcx_read(vcpu);
1418 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1419 kvm_inject_gp(vcpu, 0);
1423 kvm_rax_write(vcpu, (u32)data);
1424 kvm_rdx_write(vcpu, data >> 32);
1425 return kvm_skip_emulated_instruction(vcpu);
1427 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1430 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1431 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1433 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1434 * extract the supported MSRs from the related const lists.
1435 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1436 * capabilities of the host cpu. This capabilities test skips MSRs that are
1437 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1438 * may depend on host virtualization features rather than host cpu features.
1441 static const u32 msrs_to_save_base[] = {
1442 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1444 #ifdef CONFIG_X86_64
1445 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1447 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1448 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1449 MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL,
1450 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1451 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1452 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1453 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1454 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1455 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1456 MSR_IA32_UMWAIT_CONTROL,
1458 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1461 static const u32 msrs_to_save_pmu[] = {
1462 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1463 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1464 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1465 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1466 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1468 /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
1469 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1470 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1471 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1472 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1473 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1474 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1475 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1476 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1478 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1479 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1481 /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
1482 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1483 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1484 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1485 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1488 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) +
1489 ARRAY_SIZE(msrs_to_save_pmu)];
1490 static unsigned num_msrs_to_save;
1492 static const u32 emulated_msrs_all[] = {
1493 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1494 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1495 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1496 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1497 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1498 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1499 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1501 HV_X64_MSR_VP_INDEX,
1502 HV_X64_MSR_VP_RUNTIME,
1503 HV_X64_MSR_SCONTROL,
1504 HV_X64_MSR_STIMER0_CONFIG,
1505 HV_X64_MSR_VP_ASSIST_PAGE,
1506 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1507 HV_X64_MSR_TSC_EMULATION_STATUS, HV_X64_MSR_TSC_INVARIANT_CONTROL,
1508 HV_X64_MSR_SYNDBG_OPTIONS,
1509 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1510 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1511 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1513 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1514 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1516 MSR_IA32_TSC_ADJUST,
1517 MSR_IA32_TSC_DEADLINE,
1518 MSR_IA32_ARCH_CAPABILITIES,
1519 MSR_IA32_PERF_CAPABILITIES,
1520 MSR_IA32_MISC_ENABLE,
1521 MSR_IA32_MCG_STATUS,
1523 MSR_IA32_MCG_EXT_CTL,
1527 MSR_MISC_FEATURES_ENABLES,
1528 MSR_AMD64_VIRT_SPEC_CTRL,
1529 MSR_AMD64_TSC_RATIO,
1534 * The following list leaves out MSRs whose values are determined
1535 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1536 * We always support the "true" VMX control MSRs, even if the host
1537 * processor does not, so I am putting these registers here rather
1538 * than in msrs_to_save_all.
1541 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1542 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1543 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1544 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1546 MSR_IA32_VMX_CR0_FIXED0,
1547 MSR_IA32_VMX_CR4_FIXED0,
1548 MSR_IA32_VMX_VMCS_ENUM,
1549 MSR_IA32_VMX_PROCBASED_CTLS2,
1550 MSR_IA32_VMX_EPT_VPID_CAP,
1551 MSR_IA32_VMX_VMFUNC,
1554 MSR_KVM_POLL_CONTROL,
1557 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1558 static unsigned num_emulated_msrs;
1561 * List of MSRs that control the existence of MSR-based features, i.e. MSRs
1562 * that are effectively CPUID leafs. VMX MSRs are also included in the set of
1563 * feature MSRs, but are handled separately to allow expedited lookups.
1565 static const u32 msr_based_features_all_except_vmx[] = {
1568 MSR_IA32_ARCH_CAPABILITIES,
1569 MSR_IA32_PERF_CAPABILITIES,
1572 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all_except_vmx) +
1573 (KVM_LAST_EMULATED_VMX_MSR - KVM_FIRST_EMULATED_VMX_MSR + 1)];
1574 static unsigned int num_msr_based_features;
1577 * All feature MSRs except uCode revID, which tracks the currently loaded uCode
1578 * patch, are immutable once the vCPU model is defined.
1580 static bool kvm_is_immutable_feature_msr(u32 msr)
1584 if (msr >= KVM_FIRST_EMULATED_VMX_MSR && msr <= KVM_LAST_EMULATED_VMX_MSR)
1587 for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) {
1588 if (msr == msr_based_features_all_except_vmx[i])
1589 return msr != MSR_IA32_UCODE_REV;
1596 * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM
1597 * does not yet virtualize. These include:
1598 * 10 - MISC_PACKAGE_CTRLS
1599 * 11 - ENERGY_FILTERING_CTL
1601 * 18 - FB_CLEAR_CTRL
1602 * 21 - XAPIC_DISABLE_STATUS
1603 * 23 - OVERCLOCKING_STATUS
1606 #define KVM_SUPPORTED_ARCH_CAP \
1607 (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \
1608 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \
1609 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \
1610 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \
1611 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO)
1613 static u64 kvm_get_arch_capabilities(void)
1617 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
1618 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1619 data &= KVM_SUPPORTED_ARCH_CAP;
1623 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1624 * the nested hypervisor runs with NX huge pages. If it is not,
1625 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1626 * L1 guests, so it need not worry about its own (L2) guests.
1628 data |= ARCH_CAP_PSCHANGE_MC_NO;
1631 * If we're doing cache flushes (either "always" or "cond")
1632 * we will do one whenever the guest does a vmlaunch/vmresume.
1633 * If an outer hypervisor is doing the cache flush for us
1634 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1635 * capability to the guest too, and if EPT is disabled we're not
1636 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1637 * require a nested hypervisor to do a flush of its own.
1639 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1640 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1642 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1643 data |= ARCH_CAP_RDCL_NO;
1644 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1645 data |= ARCH_CAP_SSB_NO;
1646 if (!boot_cpu_has_bug(X86_BUG_MDS))
1647 data |= ARCH_CAP_MDS_NO;
1649 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1651 * If RTM=0 because the kernel has disabled TSX, the host might
1652 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1653 * and therefore knows that there cannot be TAA) but keep
1654 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1655 * and we want to allow migrating those guests to tsx=off hosts.
1657 data &= ~ARCH_CAP_TAA_NO;
1658 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1659 data |= ARCH_CAP_TAA_NO;
1662 * Nothing to do here; we emulate TSX_CTRL if present on the
1663 * host so the guest can choose between disabling TSX or
1664 * using VERW to clear CPU buffers.
1671 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1673 switch (msr->index) {
1674 case MSR_IA32_ARCH_CAPABILITIES:
1675 msr->data = kvm_get_arch_capabilities();
1677 case MSR_IA32_PERF_CAPABILITIES:
1678 msr->data = kvm_caps.supported_perf_cap;
1680 case MSR_IA32_UCODE_REV:
1681 rdmsrl_safe(msr->index, &msr->data);
1684 return static_call(kvm_x86_get_msr_feature)(msr);
1689 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1691 struct kvm_msr_entry msr;
1695 r = kvm_get_msr_feature(&msr);
1697 if (r == KVM_MSR_RET_INVALID) {
1698 /* Unconditionally clear the output for simplicity */
1700 if (kvm_msr_ignored_check(index, 0, false))
1712 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1714 if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS))
1717 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1720 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1723 if (efer & (EFER_LME | EFER_LMA) &&
1724 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1727 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1733 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1735 if (efer & efer_reserved_bits)
1738 return __kvm_valid_efer(vcpu, efer);
1740 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1742 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1744 u64 old_efer = vcpu->arch.efer;
1745 u64 efer = msr_info->data;
1748 if (efer & efer_reserved_bits)
1751 if (!msr_info->host_initiated) {
1752 if (!__kvm_valid_efer(vcpu, efer))
1755 if (is_paging(vcpu) &&
1756 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1761 efer |= vcpu->arch.efer & EFER_LMA;
1763 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1769 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1770 kvm_mmu_reset_context(vcpu);
1775 void kvm_enable_efer_bits(u64 mask)
1777 efer_reserved_bits &= ~mask;
1779 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1781 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1783 struct kvm_x86_msr_filter *msr_filter;
1784 struct msr_bitmap_range *ranges;
1785 struct kvm *kvm = vcpu->kvm;
1790 /* x2APIC MSRs do not support filtering. */
1791 if (index >= 0x800 && index <= 0x8ff)
1794 idx = srcu_read_lock(&kvm->srcu);
1796 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1802 allowed = msr_filter->default_allow;
1803 ranges = msr_filter->ranges;
1805 for (i = 0; i < msr_filter->count; i++) {
1806 u32 start = ranges[i].base;
1807 u32 end = start + ranges[i].nmsrs;
1808 u32 flags = ranges[i].flags;
1809 unsigned long *bitmap = ranges[i].bitmap;
1811 if ((index >= start) && (index < end) && (flags & type)) {
1812 allowed = !!test_bit(index - start, bitmap);
1818 srcu_read_unlock(&kvm->srcu, idx);
1822 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1825 * Write @data into the MSR specified by @index. Select MSR specific fault
1826 * checks are bypassed if @host_initiated is %true.
1827 * Returns 0 on success, non-0 otherwise.
1828 * Assumes vcpu_load() was already called.
1830 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1831 bool host_initiated)
1833 struct msr_data msr;
1838 case MSR_KERNEL_GS_BASE:
1841 if (is_noncanonical_address(data, vcpu))
1844 case MSR_IA32_SYSENTER_EIP:
1845 case MSR_IA32_SYSENTER_ESP:
1847 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1848 * non-canonical address is written on Intel but not on
1849 * AMD (which ignores the top 32-bits, because it does
1850 * not implement 64-bit SYSENTER).
1852 * 64-bit code should hence be able to write a non-canonical
1853 * value on AMD. Making the address canonical ensures that
1854 * vmentry does not fail on Intel after writing a non-canonical
1855 * value, and that something deterministic happens if the guest
1856 * invokes 64-bit SYSENTER.
1858 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1861 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1864 if (!host_initiated &&
1865 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1866 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1870 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1871 * incomplete and conflicting architectural behavior. Current
1872 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1873 * reserved and always read as zeros. Enforce Intel's reserved
1874 * bits check if and only if the guest CPU is Intel, and clear
1875 * the bits in all other cases. This ensures cross-vendor
1876 * migration will provide consistent behavior for the guest.
1878 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1887 msr.host_initiated = host_initiated;
1889 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1892 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1893 u32 index, u64 data, bool host_initiated)
1895 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1897 if (ret == KVM_MSR_RET_INVALID)
1898 if (kvm_msr_ignored_check(index, data, true))
1905 * Read the MSR specified by @index into @data. Select MSR specific fault
1906 * checks are bypassed if @host_initiated is %true.
1907 * Returns 0 on success, non-0 otherwise.
1908 * Assumes vcpu_load() was already called.
1910 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1911 bool host_initiated)
1913 struct msr_data msr;
1918 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1921 if (!host_initiated &&
1922 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1923 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1929 msr.host_initiated = host_initiated;
1931 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1937 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1938 u32 index, u64 *data, bool host_initiated)
1940 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1942 if (ret == KVM_MSR_RET_INVALID) {
1943 /* Unconditionally clear *data for simplicity */
1945 if (kvm_msr_ignored_check(index, 0, false))
1952 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1954 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1955 return KVM_MSR_RET_FILTERED;
1956 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1959 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1961 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1962 return KVM_MSR_RET_FILTERED;
1963 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1966 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1968 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1970 EXPORT_SYMBOL_GPL(kvm_get_msr);
1972 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1974 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1976 EXPORT_SYMBOL_GPL(kvm_set_msr);
1978 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1980 if (!vcpu->run->msr.error) {
1981 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1982 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1986 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1988 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
1991 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1993 complete_userspace_rdmsr(vcpu);
1994 return complete_emulated_msr_access(vcpu);
1997 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
1999 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
2002 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
2004 complete_userspace_rdmsr(vcpu);
2005 return complete_fast_msr_access(vcpu);
2008 static u64 kvm_msr_reason(int r)
2011 case KVM_MSR_RET_INVALID:
2012 return KVM_MSR_EXIT_REASON_UNKNOWN;
2013 case KVM_MSR_RET_FILTERED:
2014 return KVM_MSR_EXIT_REASON_FILTER;
2016 return KVM_MSR_EXIT_REASON_INVAL;
2020 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
2021 u32 exit_reason, u64 data,
2022 int (*completion)(struct kvm_vcpu *vcpu),
2025 u64 msr_reason = kvm_msr_reason(r);
2027 /* Check if the user wanted to know about this MSR fault */
2028 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
2031 vcpu->run->exit_reason = exit_reason;
2032 vcpu->run->msr.error = 0;
2033 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
2034 vcpu->run->msr.reason = msr_reason;
2035 vcpu->run->msr.index = index;
2036 vcpu->run->msr.data = data;
2037 vcpu->arch.complete_userspace_io = completion;
2042 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
2044 u32 ecx = kvm_rcx_read(vcpu);
2048 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
2051 trace_kvm_msr_read(ecx, data);
2053 kvm_rax_write(vcpu, data & -1u);
2054 kvm_rdx_write(vcpu, (data >> 32) & -1u);
2056 /* MSR read failed? See if we should ask user space */
2057 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
2058 complete_fast_rdmsr, r))
2060 trace_kvm_msr_read_ex(ecx);
2063 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2065 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
2067 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
2069 u32 ecx = kvm_rcx_read(vcpu);
2070 u64 data = kvm_read_edx_eax(vcpu);
2073 r = kvm_set_msr_with_filter(vcpu, ecx, data);
2076 trace_kvm_msr_write(ecx, data);
2078 /* MSR write failed? See if we should ask user space */
2079 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2080 complete_fast_msr_access, r))
2082 /* Signal all other negative errors to userspace */
2085 trace_kvm_msr_write_ex(ecx, data);
2088 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2090 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2092 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2094 return kvm_skip_emulated_instruction(vcpu);
2097 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2099 /* Treat an INVD instruction as a NOP and just skip it. */
2100 return kvm_emulate_as_nop(vcpu);
2102 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2104 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2106 kvm_queue_exception(vcpu, UD_VECTOR);
2109 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2112 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
2114 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) &&
2115 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT))
2116 return kvm_handle_invalid_op(vcpu);
2118 pr_warn_once("%s instruction emulated as NOP!\n", insn);
2119 return kvm_emulate_as_nop(vcpu);
2121 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2123 return kvm_emulate_monitor_mwait(vcpu, "MWAIT");
2125 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2127 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2129 return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
2131 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2133 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2135 xfer_to_guest_mode_prepare();
2136 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2137 xfer_to_guest_mode_work_pending();
2141 * The fast path for frequent and performance sensitive wrmsr emulation,
2142 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2143 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2144 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2145 * other cases which must be called after interrupts are enabled on the host.
2147 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2149 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2152 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2153 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2154 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2155 ((u32)(data >> 32) != X2APIC_BROADCAST))
2156 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2161 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2163 if (!kvm_can_use_hv_timer(vcpu))
2166 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2170 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2172 u32 msr = kvm_rcx_read(vcpu);
2174 fastpath_t ret = EXIT_FASTPATH_NONE;
2177 case APIC_BASE_MSR + (APIC_ICR >> 4):
2178 data = kvm_read_edx_eax(vcpu);
2179 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2180 kvm_skip_emulated_instruction(vcpu);
2181 ret = EXIT_FASTPATH_EXIT_HANDLED;
2184 case MSR_IA32_TSC_DEADLINE:
2185 data = kvm_read_edx_eax(vcpu);
2186 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2187 kvm_skip_emulated_instruction(vcpu);
2188 ret = EXIT_FASTPATH_REENTER_GUEST;
2195 if (ret != EXIT_FASTPATH_NONE)
2196 trace_kvm_msr_write(msr, data);
2200 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2203 * Adapt set_msr() to msr_io()'s calling convention
2205 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2207 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2210 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2215 * Disallow writes to immutable feature MSRs after KVM_RUN. KVM does
2216 * not support modifying the guest vCPU model on the fly, e.g. changing
2217 * the nVMX capabilities while L2 is running is nonsensical. Ignore
2218 * writes of the same value, e.g. to allow userspace to blindly stuff
2219 * all MSRs when emulating RESET.
2221 if (kvm_vcpu_has_run(vcpu) && kvm_is_immutable_feature_msr(index)) {
2222 if (do_get_msr(vcpu, index, &val) || *data != val)
2228 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2231 #ifdef CONFIG_X86_64
2232 struct pvclock_clock {
2242 struct pvclock_gtod_data {
2245 struct pvclock_clock clock; /* extract of a clocksource struct */
2246 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2252 static struct pvclock_gtod_data pvclock_gtod_data;
2254 static void update_pvclock_gtod(struct timekeeper *tk)
2256 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2258 write_seqcount_begin(&vdata->seq);
2260 /* copy pvclock gtod data */
2261 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2262 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2263 vdata->clock.mask = tk->tkr_mono.mask;
2264 vdata->clock.mult = tk->tkr_mono.mult;
2265 vdata->clock.shift = tk->tkr_mono.shift;
2266 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2267 vdata->clock.offset = tk->tkr_mono.base;
2269 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2270 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2271 vdata->raw_clock.mask = tk->tkr_raw.mask;
2272 vdata->raw_clock.mult = tk->tkr_raw.mult;
2273 vdata->raw_clock.shift = tk->tkr_raw.shift;
2274 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2275 vdata->raw_clock.offset = tk->tkr_raw.base;
2277 vdata->wall_time_sec = tk->xtime_sec;
2279 vdata->offs_boot = tk->offs_boot;
2281 write_seqcount_end(&vdata->seq);
2284 static s64 get_kvmclock_base_ns(void)
2286 /* Count up from boot time, but with the frequency of the raw clock. */
2287 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2290 static s64 get_kvmclock_base_ns(void)
2292 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2293 return ktime_get_boottime_ns();
2297 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2301 struct pvclock_wall_clock wc;
2308 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2313 ++version; /* first time write, random junk */
2317 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2321 * The guest calculates current wall clock time by adding
2322 * system time (updated by kvm_guest_time_update below) to the
2323 * wall clock specified here. We do the reverse here.
2325 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2327 wc.nsec = do_div(wall_nsec, 1000000000);
2328 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2329 wc.version = version;
2331 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2334 wc_sec_hi = wall_nsec >> 32;
2335 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2336 &wc_sec_hi, sizeof(wc_sec_hi));
2340 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2343 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2344 bool old_msr, bool host_initiated)
2346 struct kvm_arch *ka = &vcpu->kvm->arch;
2348 if (vcpu->vcpu_id == 0 && !host_initiated) {
2349 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2350 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2352 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2355 vcpu->arch.time = system_time;
2356 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2358 /* we verify if the enable bit is set... */
2359 if (system_time & 1)
2360 kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL,
2361 sizeof(struct pvclock_vcpu_time_info));
2363 kvm_gpc_deactivate(&vcpu->arch.pv_time);
2368 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2370 do_shl32_div32(dividend, divisor);
2374 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2375 s8 *pshift, u32 *pmultiplier)
2383 scaled64 = scaled_hz;
2384 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2389 tps32 = (uint32_t)tps64;
2390 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2391 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2399 *pmultiplier = div_frac(scaled64, tps32);
2402 #ifdef CONFIG_X86_64
2403 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2406 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2407 static unsigned long max_tsc_khz;
2409 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2411 u64 v = (u64)khz * (1000000 + ppm);
2416 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2418 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2422 /* Guest TSC same frequency as host TSC? */
2424 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2428 /* TSC scaling supported? */
2429 if (!kvm_caps.has_tsc_control) {
2430 if (user_tsc_khz > tsc_khz) {
2431 vcpu->arch.tsc_catchup = 1;
2432 vcpu->arch.tsc_always_catchup = 1;
2435 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2440 /* TSC scaling required - calculate ratio */
2441 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
2442 user_tsc_khz, tsc_khz);
2444 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
2445 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2450 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2454 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2456 u32 thresh_lo, thresh_hi;
2457 int use_scaling = 0;
2459 /* tsc_khz can be zero if TSC calibration fails */
2460 if (user_tsc_khz == 0) {
2461 /* set tsc_scaling_ratio to a safe value */
2462 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2466 /* Compute a scale to convert nanoseconds in TSC cycles */
2467 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2468 &vcpu->arch.virtual_tsc_shift,
2469 &vcpu->arch.virtual_tsc_mult);
2470 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2473 * Compute the variation in TSC rate which is acceptable
2474 * within the range of tolerance and decide if the
2475 * rate being applied is within that bounds of the hardware
2476 * rate. If so, no scaling or compensation need be done.
2478 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2479 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2480 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2481 pr_debug("requested TSC rate %u falls outside tolerance [%u,%u]\n",
2482 user_tsc_khz, thresh_lo, thresh_hi);
2485 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2488 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2490 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2491 vcpu->arch.virtual_tsc_mult,
2492 vcpu->arch.virtual_tsc_shift);
2493 tsc += vcpu->arch.this_tsc_write;
2497 #ifdef CONFIG_X86_64
2498 static inline int gtod_is_based_on_tsc(int mode)
2500 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2504 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2506 #ifdef CONFIG_X86_64
2508 struct kvm_arch *ka = &vcpu->kvm->arch;
2509 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2511 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2512 atomic_read(&vcpu->kvm->online_vcpus));
2515 * Once the masterclock is enabled, always perform request in
2516 * order to update it.
2518 * In order to enable masterclock, the host clocksource must be TSC
2519 * and the vcpus need to have matched TSCs. When that happens,
2520 * perform request to enable masterclock.
2522 if (ka->use_master_clock ||
2523 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2524 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2526 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2527 atomic_read(&vcpu->kvm->online_vcpus),
2528 ka->use_master_clock, gtod->clock.vclock_mode);
2533 * Multiply tsc by a fixed point number represented by ratio.
2535 * The most significant 64-N bits (mult) of ratio represent the
2536 * integral part of the fixed point number; the remaining N bits
2537 * (frac) represent the fractional part, ie. ratio represents a fixed
2538 * point number (mult + frac * 2^(-N)).
2540 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
2542 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2544 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
2547 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2551 if (ratio != kvm_caps.default_tsc_scaling_ratio)
2552 _tsc = __scale_tsc(ratio, tsc);
2557 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2561 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2563 return target_tsc - tsc;
2566 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2568 return vcpu->arch.l1_tsc_offset +
2569 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2571 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2573 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2577 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
2578 nested_offset = l1_offset;
2580 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2581 kvm_caps.tsc_scaling_ratio_frac_bits);
2583 nested_offset += l2_offset;
2584 return nested_offset;
2586 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2588 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2590 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
2591 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2592 kvm_caps.tsc_scaling_ratio_frac_bits);
2594 return l1_multiplier;
2596 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2598 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2600 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2601 vcpu->arch.l1_tsc_offset,
2604 vcpu->arch.l1_tsc_offset = l1_offset;
2607 * If we are here because L1 chose not to trap WRMSR to TSC then
2608 * according to the spec this should set L1's TSC (as opposed to
2609 * setting L1's offset for L2).
2611 if (is_guest_mode(vcpu))
2612 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2614 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2615 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2617 vcpu->arch.tsc_offset = l1_offset;
2619 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset);
2622 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2624 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2626 /* Userspace is changing the multiplier while L2 is active */
2627 if (is_guest_mode(vcpu))
2628 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2630 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2632 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2634 if (kvm_caps.has_tsc_control)
2635 static_call(kvm_x86_write_tsc_multiplier)(
2636 vcpu, vcpu->arch.tsc_scaling_ratio);
2639 static inline bool kvm_check_tsc_unstable(void)
2641 #ifdef CONFIG_X86_64
2643 * TSC is marked unstable when we're running on Hyper-V,
2644 * 'TSC page' clocksource is good.
2646 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2649 return check_tsc_unstable();
2653 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2654 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2657 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2658 u64 ns, bool matched)
2660 struct kvm *kvm = vcpu->kvm;
2662 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2665 * We also track th most recent recorded KHZ, write and time to
2666 * allow the matching interval to be extended at each write.
2668 kvm->arch.last_tsc_nsec = ns;
2669 kvm->arch.last_tsc_write = tsc;
2670 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2671 kvm->arch.last_tsc_offset = offset;
2673 vcpu->arch.last_guest_tsc = tsc;
2675 kvm_vcpu_write_tsc_offset(vcpu, offset);
2679 * We split periods of matched TSC writes into generations.
2680 * For each generation, we track the original measured
2681 * nanosecond time, offset, and write, so if TSCs are in
2682 * sync, we can match exact offset, and if not, we can match
2683 * exact software computation in compute_guest_tsc()
2685 * These values are tracked in kvm->arch.cur_xxx variables.
2687 kvm->arch.cur_tsc_generation++;
2688 kvm->arch.cur_tsc_nsec = ns;
2689 kvm->arch.cur_tsc_write = tsc;
2690 kvm->arch.cur_tsc_offset = offset;
2691 kvm->arch.nr_vcpus_matched_tsc = 0;
2692 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2693 kvm->arch.nr_vcpus_matched_tsc++;
2696 /* Keep track of which generation this VCPU has synchronized to */
2697 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2698 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2699 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2701 kvm_track_tsc_matching(vcpu);
2704 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2706 struct kvm *kvm = vcpu->kvm;
2707 u64 offset, ns, elapsed;
2708 unsigned long flags;
2709 bool matched = false;
2710 bool synchronizing = false;
2712 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2713 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2714 ns = get_kvmclock_base_ns();
2715 elapsed = ns - kvm->arch.last_tsc_nsec;
2717 if (vcpu->arch.virtual_tsc_khz) {
2720 * detection of vcpu initialization -- need to sync
2721 * with other vCPUs. This particularly helps to keep
2722 * kvm_clock stable after CPU hotplug
2724 synchronizing = true;
2726 u64 tsc_exp = kvm->arch.last_tsc_write +
2727 nsec_to_cycles(vcpu, elapsed);
2728 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2730 * Special case: TSC write with a small delta (1 second)
2731 * of virtual cycle time against real time is
2732 * interpreted as an attempt to synchronize the CPU.
2734 synchronizing = data < tsc_exp + tsc_hz &&
2735 data + tsc_hz > tsc_exp;
2740 * For a reliable TSC, we can match TSC offsets, and for an unstable
2741 * TSC, we add elapsed time in this computation. We could let the
2742 * compensation code attempt to catch up if we fall behind, but
2743 * it's better to try to match offsets from the beginning.
2745 if (synchronizing &&
2746 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2747 if (!kvm_check_tsc_unstable()) {
2748 offset = kvm->arch.cur_tsc_offset;
2750 u64 delta = nsec_to_cycles(vcpu, elapsed);
2752 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2757 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2758 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2761 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2764 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2765 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2768 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2770 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
2771 WARN_ON(adjustment < 0);
2772 adjustment = kvm_scale_tsc((u64) adjustment,
2773 vcpu->arch.l1_tsc_scaling_ratio);
2774 adjust_tsc_offset_guest(vcpu, adjustment);
2777 #ifdef CONFIG_X86_64
2779 static u64 read_tsc(void)
2781 u64 ret = (u64)rdtsc_ordered();
2782 u64 last = pvclock_gtod_data.clock.cycle_last;
2784 if (likely(ret >= last))
2788 * GCC likes to generate cmov here, but this branch is extremely
2789 * predictable (it's just a function of time and the likely is
2790 * very likely) and there's a data dependence, so force GCC
2791 * to generate a branch instead. I don't barrier() because
2792 * we don't actually need a barrier, and if this function
2793 * ever gets inlined it will generate worse code.
2799 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2805 switch (clock->vclock_mode) {
2806 case VDSO_CLOCKMODE_HVCLOCK:
2807 if (hv_read_tsc_page_tsc(hv_get_tsc_page(),
2808 tsc_timestamp, &tsc_pg_val)) {
2809 /* TSC page valid */
2810 *mode = VDSO_CLOCKMODE_HVCLOCK;
2811 v = (tsc_pg_val - clock->cycle_last) &
2814 /* TSC page invalid */
2815 *mode = VDSO_CLOCKMODE_NONE;
2818 case VDSO_CLOCKMODE_TSC:
2819 *mode = VDSO_CLOCKMODE_TSC;
2820 *tsc_timestamp = read_tsc();
2821 v = (*tsc_timestamp - clock->cycle_last) &
2825 *mode = VDSO_CLOCKMODE_NONE;
2828 if (*mode == VDSO_CLOCKMODE_NONE)
2829 *tsc_timestamp = v = 0;
2831 return v * clock->mult;
2834 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2836 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2842 seq = read_seqcount_begin(>od->seq);
2843 ns = gtod->raw_clock.base_cycles;
2844 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2845 ns >>= gtod->raw_clock.shift;
2846 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2847 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2853 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2855 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2861 seq = read_seqcount_begin(>od->seq);
2862 ts->tv_sec = gtod->wall_time_sec;
2863 ns = gtod->clock.base_cycles;
2864 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2865 ns >>= gtod->clock.shift;
2866 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2868 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2874 /* returns true if host is using TSC based clocksource */
2875 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2877 /* checked again under seqlock below */
2878 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2881 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2885 /* returns true if host is using TSC based clocksource */
2886 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2889 /* checked again under seqlock below */
2890 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2893 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2899 * Assuming a stable TSC across physical CPUS, and a stable TSC
2900 * across virtual CPUs, the following condition is possible.
2901 * Each numbered line represents an event visible to both
2902 * CPUs at the next numbered event.
2904 * "timespecX" represents host monotonic time. "tscX" represents
2907 * VCPU0 on CPU0 | VCPU1 on CPU1
2909 * 1. read timespec0,tsc0
2910 * 2. | timespec1 = timespec0 + N
2912 * 3. transition to guest | transition to guest
2913 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2914 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2915 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2917 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2920 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2922 * - 0 < N - M => M < N
2924 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2925 * always the case (the difference between two distinct xtime instances
2926 * might be smaller then the difference between corresponding TSC reads,
2927 * when updating guest vcpus pvclock areas).
2929 * To avoid that problem, do not allow visibility of distinct
2930 * system_timestamp/tsc_timestamp values simultaneously: use a master
2931 * copy of host monotonic time values. Update that master copy
2934 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2938 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2940 #ifdef CONFIG_X86_64
2941 struct kvm_arch *ka = &kvm->arch;
2943 bool host_tsc_clocksource, vcpus_matched;
2945 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2946 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2947 atomic_read(&kvm->online_vcpus));
2950 * If the host uses TSC clock, then passthrough TSC as stable
2953 host_tsc_clocksource = kvm_get_time_and_clockread(
2954 &ka->master_kernel_ns,
2955 &ka->master_cycle_now);
2957 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2958 && !ka->backwards_tsc_observed
2959 && !ka->boot_vcpu_runs_old_kvmclock;
2961 if (ka->use_master_clock)
2962 atomic_set(&kvm_guest_has_master_clock, 1);
2964 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2965 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2970 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2972 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2975 static void __kvm_start_pvclock_update(struct kvm *kvm)
2977 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2978 write_seqcount_begin(&kvm->arch.pvclock_sc);
2981 static void kvm_start_pvclock_update(struct kvm *kvm)
2983 kvm_make_mclock_inprogress_request(kvm);
2985 /* no guest entries from this point */
2986 __kvm_start_pvclock_update(kvm);
2989 static void kvm_end_pvclock_update(struct kvm *kvm)
2991 struct kvm_arch *ka = &kvm->arch;
2992 struct kvm_vcpu *vcpu;
2995 write_seqcount_end(&ka->pvclock_sc);
2996 raw_spin_unlock_irq(&ka->tsc_write_lock);
2997 kvm_for_each_vcpu(i, vcpu, kvm)
2998 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3000 /* guest entries allowed */
3001 kvm_for_each_vcpu(i, vcpu, kvm)
3002 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
3005 static void kvm_update_masterclock(struct kvm *kvm)
3007 kvm_hv_request_tsc_page_update(kvm);
3008 kvm_start_pvclock_update(kvm);
3009 pvclock_update_vm_gtod_copy(kvm);
3010 kvm_end_pvclock_update(kvm);
3014 * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's
3015 * per-CPU value (which may be zero if a CPU is going offline). Note, tsc_khz
3016 * can change during boot even if the TSC is constant, as it's possible for KVM
3017 * to be loaded before TSC calibration completes. Ideally, KVM would get a
3018 * notification when calibration completes, but practically speaking calibration
3019 * will complete before userspace is alive enough to create VMs.
3021 static unsigned long get_cpu_tsc_khz(void)
3023 if (static_cpu_has(X86_FEATURE_CONSTANT_TSC))
3026 return __this_cpu_read(cpu_tsc_khz);
3029 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
3030 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3032 struct kvm_arch *ka = &kvm->arch;
3033 struct pvclock_vcpu_time_info hv_clock;
3035 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
3039 if (ka->use_master_clock &&
3040 (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) {
3041 #ifdef CONFIG_X86_64
3042 struct timespec64 ts;
3044 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
3045 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
3046 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
3049 data->host_tsc = rdtsc();
3051 data->flags |= KVM_CLOCK_TSC_STABLE;
3052 hv_clock.tsc_timestamp = ka->master_cycle_now;
3053 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3054 kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL,
3055 &hv_clock.tsc_shift,
3056 &hv_clock.tsc_to_system_mul);
3057 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
3059 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
3065 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3067 struct kvm_arch *ka = &kvm->arch;
3071 seq = read_seqcount_begin(&ka->pvclock_sc);
3072 __get_kvmclock(kvm, data);
3073 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3076 u64 get_kvmclock_ns(struct kvm *kvm)
3078 struct kvm_clock_data data;
3080 get_kvmclock(kvm, &data);
3084 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
3085 struct gfn_to_pfn_cache *gpc,
3086 unsigned int offset)
3088 struct kvm_vcpu_arch *vcpu = &v->arch;
3089 struct pvclock_vcpu_time_info *guest_hv_clock;
3090 unsigned long flags;
3092 read_lock_irqsave(&gpc->lock, flags);
3093 while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) {
3094 read_unlock_irqrestore(&gpc->lock, flags);
3096 if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock)))
3099 read_lock_irqsave(&gpc->lock, flags);
3102 guest_hv_clock = (void *)(gpc->khva + offset);
3105 * This VCPU is paused, but it's legal for a guest to read another
3106 * VCPU's kvmclock, so we really have to follow the specification where
3107 * it says that version is odd if data is being modified, and even after
3111 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
3114 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3115 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3117 if (vcpu->pvclock_set_guest_stopped_request) {
3118 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3119 vcpu->pvclock_set_guest_stopped_request = false;
3122 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3125 guest_hv_clock->version = ++vcpu->hv_clock.version;
3127 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT);
3128 read_unlock_irqrestore(&gpc->lock, flags);
3130 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3133 static int kvm_guest_time_update(struct kvm_vcpu *v)
3135 unsigned long flags, tgt_tsc_khz;
3137 struct kvm_vcpu_arch *vcpu = &v->arch;
3138 struct kvm_arch *ka = &v->kvm->arch;
3140 u64 tsc_timestamp, host_tsc;
3142 bool use_master_clock;
3148 * If the host uses TSC clock, then passthrough TSC as stable
3152 seq = read_seqcount_begin(&ka->pvclock_sc);
3153 use_master_clock = ka->use_master_clock;
3154 if (use_master_clock) {
3155 host_tsc = ka->master_cycle_now;
3156 kernel_ns = ka->master_kernel_ns;
3158 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3160 /* Keep irq disabled to prevent changes to the clock */
3161 local_irq_save(flags);
3162 tgt_tsc_khz = get_cpu_tsc_khz();
3163 if (unlikely(tgt_tsc_khz == 0)) {
3164 local_irq_restore(flags);
3165 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3168 if (!use_master_clock) {
3170 kernel_ns = get_kvmclock_base_ns();
3173 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3176 * We may have to catch up the TSC to match elapsed wall clock
3177 * time for two reasons, even if kvmclock is used.
3178 * 1) CPU could have been running below the maximum TSC rate
3179 * 2) Broken TSC compensation resets the base at each VCPU
3180 * entry to avoid unknown leaps of TSC even when running
3181 * again on the same CPU. This may cause apparent elapsed
3182 * time to disappear, and the guest to stand still or run
3185 if (vcpu->tsc_catchup) {
3186 u64 tsc = compute_guest_tsc(v, kernel_ns);
3187 if (tsc > tsc_timestamp) {
3188 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3189 tsc_timestamp = tsc;
3193 local_irq_restore(flags);
3195 /* With all the info we got, fill in the values */
3197 if (kvm_caps.has_tsc_control)
3198 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3199 v->arch.l1_tsc_scaling_ratio);
3201 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3202 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3203 &vcpu->hv_clock.tsc_shift,
3204 &vcpu->hv_clock.tsc_to_system_mul);
3205 vcpu->hw_tsc_khz = tgt_tsc_khz;
3206 kvm_xen_update_tsc_info(v);
3209 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3210 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3211 vcpu->last_guest_tsc = tsc_timestamp;
3213 /* If the host uses TSC clocksource, then it is stable */
3215 if (use_master_clock)
3216 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3218 vcpu->hv_clock.flags = pvclock_flags;
3220 if (vcpu->pv_time.active)
3221 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0);
3222 if (vcpu->xen.vcpu_info_cache.active)
3223 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3224 offsetof(struct compat_vcpu_info, time));
3225 if (vcpu->xen.vcpu_time_info_cache.active)
3226 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0);
3227 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3232 * kvmclock updates which are isolated to a given vcpu, such as
3233 * vcpu->cpu migration, should not allow system_timestamp from
3234 * the rest of the vcpus to remain static. Otherwise ntp frequency
3235 * correction applies to one vcpu's system_timestamp but not
3238 * So in those cases, request a kvmclock update for all vcpus.
3239 * We need to rate-limit these requests though, as they can
3240 * considerably slow guests that have a large number of vcpus.
3241 * The time for a remote vcpu to update its kvmclock is bound
3242 * by the delay we use to rate-limit the updates.
3245 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3247 static void kvmclock_update_fn(struct work_struct *work)
3250 struct delayed_work *dwork = to_delayed_work(work);
3251 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3252 kvmclock_update_work);
3253 struct kvm *kvm = container_of(ka, struct kvm, arch);
3254 struct kvm_vcpu *vcpu;
3256 kvm_for_each_vcpu(i, vcpu, kvm) {
3257 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3258 kvm_vcpu_kick(vcpu);
3262 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3264 struct kvm *kvm = v->kvm;
3266 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3267 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3268 KVMCLOCK_UPDATE_DELAY);
3271 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3273 static void kvmclock_sync_fn(struct work_struct *work)
3275 struct delayed_work *dwork = to_delayed_work(work);
3276 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3277 kvmclock_sync_work);
3278 struct kvm *kvm = container_of(ka, struct kvm, arch);
3280 if (!kvmclock_periodic_sync)
3283 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3284 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3285 KVMCLOCK_SYNC_PERIOD);
3288 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
3289 static bool is_mci_control_msr(u32 msr)
3291 return (msr & 3) == 0;
3293 static bool is_mci_status_msr(u32 msr)
3295 return (msr & 3) == 1;
3299 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3301 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3303 /* McStatusWrEn enabled? */
3304 if (guest_cpuid_is_amd_or_hygon(vcpu))
3305 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3310 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3312 u64 mcg_cap = vcpu->arch.mcg_cap;
3313 unsigned bank_num = mcg_cap & 0xff;
3314 u32 msr = msr_info->index;
3315 u64 data = msr_info->data;
3316 u32 offset, last_msr;
3319 case MSR_IA32_MCG_STATUS:
3320 vcpu->arch.mcg_status = data;
3322 case MSR_IA32_MCG_CTL:
3323 if (!(mcg_cap & MCG_CTL_P) &&
3324 (data || !msr_info->host_initiated))
3326 if (data != 0 && data != ~(u64)0)
3328 vcpu->arch.mcg_ctl = data;
3330 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3331 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3335 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
3337 /* An attempt to write a 1 to a reserved bit raises #GP */
3338 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
3340 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3341 last_msr + 1 - MSR_IA32_MC0_CTL2);
3342 vcpu->arch.mci_ctl2_banks[offset] = data;
3344 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3345 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3350 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other
3351 * values are architecturally undefined. But, some Linux
3352 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
3353 * issue on AMD K8s, allow bit 10 to be clear when setting all
3354 * other bits in order to avoid an uncaught #GP in the guest.
3356 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable,
3357 * single-bit ECC data errors.
3359 if (is_mci_control_msr(msr) &&
3360 data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
3364 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
3365 * AMD-based CPUs allow non-zero values, but if and only if
3366 * HWCR[McStatusWrEn] is set.
3368 if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
3369 data != 0 && !can_set_mci_status(vcpu))
3372 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3373 last_msr + 1 - MSR_IA32_MC0_CTL);
3374 vcpu->arch.mce_banks[offset] = data;
3382 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3384 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3386 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3389 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3391 gpa_t gpa = data & ~0x3f;
3393 /* Bits 4:5 are reserved, Should be zero */
3397 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3398 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3401 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3402 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3405 if (!lapic_in_kernel(vcpu))
3406 return data ? 1 : 0;
3408 vcpu->arch.apf.msr_en_val = data;
3410 if (!kvm_pv_async_pf_enabled(vcpu)) {
3411 kvm_clear_async_pf_completion_queue(vcpu);
3412 kvm_async_pf_hash_reset(vcpu);
3416 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3420 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3421 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3423 kvm_async_pf_wakeup_all(vcpu);
3428 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3430 /* Bits 8-63 are reserved */
3434 if (!lapic_in_kernel(vcpu))
3437 vcpu->arch.apf.msr_int_val = data;
3439 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3444 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3446 kvm_gpc_deactivate(&vcpu->arch.pv_time);
3447 vcpu->arch.time = 0;
3450 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3452 ++vcpu->stat.tlb_flush;
3453 static_call(kvm_x86_flush_tlb_all)(vcpu);
3455 /* Flushing all ASIDs flushes the current ASID... */
3456 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3459 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3461 ++vcpu->stat.tlb_flush;
3465 * A TLB flush on behalf of the guest is equivalent to
3466 * INVPCID(all), toggling CR4.PGE, etc., which requires
3467 * a forced sync of the shadow page tables. Ensure all the
3468 * roots are synced and the guest TLB in hardware is clean.
3470 kvm_mmu_sync_roots(vcpu);
3471 kvm_mmu_sync_prev_roots(vcpu);
3474 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3477 * Flushing all "guest" TLB is always a superset of Hyper-V's fine
3480 kvm_hv_vcpu_purge_flush_tlb(vcpu);
3484 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3486 ++vcpu->stat.tlb_flush;
3487 static_call(kvm_x86_flush_tlb_current)(vcpu);
3491 * Service "local" TLB flush requests, which are specific to the current MMU
3492 * context. In addition to the generic event handling in vcpu_enter_guest(),
3493 * TLB flushes that are targeted at an MMU context also need to be serviced
3494 * prior before nested VM-Enter/VM-Exit.
3496 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3498 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3499 kvm_vcpu_flush_tlb_current(vcpu);
3501 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3502 kvm_vcpu_flush_tlb_guest(vcpu);
3504 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3506 static void record_steal_time(struct kvm_vcpu *vcpu)
3508 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3509 struct kvm_steal_time __user *st;
3510 struct kvm_memslots *slots;
3511 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3515 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3516 kvm_xen_runstate_set_running(vcpu);
3520 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3523 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3526 slots = kvm_memslots(vcpu->kvm);
3528 if (unlikely(slots->generation != ghc->generation ||
3530 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3531 /* We rely on the fact that it fits in a single page. */
3532 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3534 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) ||
3535 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3539 st = (struct kvm_steal_time __user *)ghc->hva;
3541 * Doing a TLB flush here, on the guest's behalf, can avoid
3544 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3545 u8 st_preempted = 0;
3548 if (!user_access_begin(st, sizeof(*st)))
3551 asm volatile("1: xchgb %0, %2\n"
3554 _ASM_EXTABLE_UA(1b, 2b)
3555 : "+q" (st_preempted),
3557 "+m" (st->preempted));
3563 vcpu->arch.st.preempted = 0;
3565 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3566 st_preempted & KVM_VCPU_FLUSH_TLB);
3567 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3568 kvm_vcpu_flush_tlb_guest(vcpu);
3570 if (!user_access_begin(st, sizeof(*st)))
3573 if (!user_access_begin(st, sizeof(*st)))
3576 unsafe_put_user(0, &st->preempted, out);
3577 vcpu->arch.st.preempted = 0;
3580 unsafe_get_user(version, &st->version, out);
3582 version += 1; /* first time write, random junk */
3585 unsafe_put_user(version, &st->version, out);
3589 unsafe_get_user(steal, &st->steal, out);
3590 steal += current->sched_info.run_delay -
3591 vcpu->arch.st.last_steal;
3592 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3593 unsafe_put_user(steal, &st->steal, out);
3596 unsafe_put_user(version, &st->version, out);
3601 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3604 static bool kvm_is_msr_to_save(u32 msr_index)
3608 for (i = 0; i < num_msrs_to_save; i++) {
3609 if (msrs_to_save[i] == msr_index)
3616 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3618 u32 msr = msr_info->index;
3619 u64 data = msr_info->data;
3621 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3622 return kvm_xen_write_hypercall_page(vcpu, data);
3625 case MSR_AMD64_NB_CFG:
3626 case MSR_IA32_UCODE_WRITE:
3627 case MSR_VM_HSAVE_PA:
3628 case MSR_AMD64_PATCH_LOADER:
3629 case MSR_AMD64_BU_CFG2:
3630 case MSR_AMD64_DC_CFG:
3631 case MSR_F15H_EX_CFG:
3634 case MSR_IA32_UCODE_REV:
3635 if (msr_info->host_initiated)
3636 vcpu->arch.microcode_version = data;
3638 case MSR_IA32_ARCH_CAPABILITIES:
3639 if (!msr_info->host_initiated)
3641 vcpu->arch.arch_capabilities = data;
3643 case MSR_IA32_PERF_CAPABILITIES:
3644 if (!msr_info->host_initiated)
3646 if (data & ~kvm_caps.supported_perf_cap)
3650 * Note, this is not just a performance optimization! KVM
3651 * disallows changing feature MSRs after the vCPU has run; PMU
3652 * refresh will bug the VM if called after the vCPU has run.
3654 if (vcpu->arch.perf_capabilities == data)
3657 vcpu->arch.perf_capabilities = data;
3658 kvm_pmu_refresh(vcpu);
3660 case MSR_IA32_PRED_CMD:
3661 if (!msr_info->host_initiated && !guest_has_pred_cmd_msr(vcpu))
3664 if (!boot_cpu_has(X86_FEATURE_IBPB) || (data & ~PRED_CMD_IBPB))
3669 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3671 case MSR_IA32_FLUSH_CMD:
3672 if (!msr_info->host_initiated &&
3673 !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D))
3676 if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH))
3681 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
3684 return set_efer(vcpu, msr_info);
3686 data &= ~(u64)0x40; /* ignore flush filter disable */
3687 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3688 data &= ~(u64)0x8; /* ignore TLB cache disable */
3690 /* Handle McStatusWrEn */
3691 if (data == BIT_ULL(18)) {
3692 vcpu->arch.msr_hwcr = data;
3693 } else if (data != 0) {
3694 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3698 case MSR_FAM10H_MMIO_CONF_BASE:
3700 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3704 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
3705 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
3706 return kvm_mtrr_set_msr(vcpu, msr, data);
3707 case MSR_IA32_APICBASE:
3708 return kvm_set_apic_base(vcpu, msr_info);
3709 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3710 return kvm_x2apic_msr_write(vcpu, msr, data);
3711 case MSR_IA32_TSC_DEADLINE:
3712 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3714 case MSR_IA32_TSC_ADJUST:
3715 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3716 if (!msr_info->host_initiated) {
3717 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3718 adjust_tsc_offset_guest(vcpu, adj);
3719 /* Before back to guest, tsc_timestamp must be adjusted
3720 * as well, otherwise guest's percpu pvclock time could jump.
3722 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3724 vcpu->arch.ia32_tsc_adjust_msr = data;
3727 case MSR_IA32_MISC_ENABLE: {
3728 u64 old_val = vcpu->arch.ia32_misc_enable_msr;
3730 if (!msr_info->host_initiated) {
3732 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)
3735 /* R bits, i.e. writes are ignored, but don't fault. */
3736 data = data & ~MSR_IA32_MISC_ENABLE_EMON;
3737 data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
3740 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3741 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3742 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3744 vcpu->arch.ia32_misc_enable_msr = data;
3745 kvm_update_cpuid_runtime(vcpu);
3747 vcpu->arch.ia32_misc_enable_msr = data;
3751 case MSR_IA32_SMBASE:
3752 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
3754 vcpu->arch.smbase = data;
3756 case MSR_IA32_POWER_CTL:
3757 vcpu->arch.msr_ia32_power_ctl = data;
3760 if (msr_info->host_initiated) {
3761 kvm_synchronize_tsc(vcpu, data);
3763 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3764 adjust_tsc_offset_guest(vcpu, adj);
3765 vcpu->arch.ia32_tsc_adjust_msr += adj;
3769 if (!msr_info->host_initiated &&
3770 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3773 * KVM supports exposing PT to the guest, but does not support
3774 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3775 * XSAVES/XRSTORS to save/restore PT MSRs.
3777 if (data & ~kvm_caps.supported_xss)
3779 vcpu->arch.ia32_xss = data;
3780 kvm_update_cpuid_runtime(vcpu);
3783 if (!msr_info->host_initiated)
3785 vcpu->arch.smi_count = data;
3787 case MSR_KVM_WALL_CLOCK_NEW:
3788 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3791 vcpu->kvm->arch.wall_clock = data;
3792 kvm_write_wall_clock(vcpu->kvm, data, 0);
3794 case MSR_KVM_WALL_CLOCK:
3795 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3798 vcpu->kvm->arch.wall_clock = data;
3799 kvm_write_wall_clock(vcpu->kvm, data, 0);
3801 case MSR_KVM_SYSTEM_TIME_NEW:
3802 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3805 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3807 case MSR_KVM_SYSTEM_TIME:
3808 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3811 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3813 case MSR_KVM_ASYNC_PF_EN:
3814 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3817 if (kvm_pv_enable_async_pf(vcpu, data))
3820 case MSR_KVM_ASYNC_PF_INT:
3821 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3824 if (kvm_pv_enable_async_pf_int(vcpu, data))
3827 case MSR_KVM_ASYNC_PF_ACK:
3828 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3831 vcpu->arch.apf.pageready_pending = false;
3832 kvm_check_async_pf_completion(vcpu);
3835 case MSR_KVM_STEAL_TIME:
3836 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3839 if (unlikely(!sched_info_on()))
3842 if (data & KVM_STEAL_RESERVED_MASK)
3845 vcpu->arch.st.msr_val = data;
3847 if (!(data & KVM_MSR_ENABLED))
3850 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3853 case MSR_KVM_PV_EOI_EN:
3854 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3857 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3861 case MSR_KVM_POLL_CONTROL:
3862 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3865 /* only enable bit supported */
3866 if (data & (-1ULL << 1))
3869 vcpu->arch.msr_kvm_poll_control = data;
3872 case MSR_IA32_MCG_CTL:
3873 case MSR_IA32_MCG_STATUS:
3874 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3875 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3876 return set_msr_mce(vcpu, msr_info);
3878 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3879 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3880 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3881 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3882 if (kvm_pmu_is_valid_msr(vcpu, msr))
3883 return kvm_pmu_set_msr(vcpu, msr_info);
3886 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3888 case MSR_K7_CLK_CTL:
3890 * Ignore all writes to this no longer documented MSR.
3891 * Writes are only relevant for old K7 processors,
3892 * all pre-dating SVM, but a recommended workaround from
3893 * AMD for these chips. It is possible to specify the
3894 * affected processor models on the command line, hence
3895 * the need to ignore the workaround.
3898 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3899 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3900 case HV_X64_MSR_SYNDBG_OPTIONS:
3901 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3902 case HV_X64_MSR_CRASH_CTL:
3903 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3904 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3905 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3906 case HV_X64_MSR_TSC_EMULATION_STATUS:
3907 case HV_X64_MSR_TSC_INVARIANT_CONTROL:
3908 return kvm_hv_set_msr_common(vcpu, msr, data,
3909 msr_info->host_initiated);
3910 case MSR_IA32_BBL_CR_CTL3:
3911 /* Drop writes to this legacy MSR -- see rdmsr
3912 * counterpart for further detail.
3914 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3916 case MSR_AMD64_OSVW_ID_LENGTH:
3917 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3919 vcpu->arch.osvw.length = data;
3921 case MSR_AMD64_OSVW_STATUS:
3922 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3924 vcpu->arch.osvw.status = data;
3926 case MSR_PLATFORM_INFO:
3927 if (!msr_info->host_initiated ||
3928 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3929 cpuid_fault_enabled(vcpu)))
3931 vcpu->arch.msr_platform_info = data;
3933 case MSR_MISC_FEATURES_ENABLES:
3934 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3935 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3936 !supports_cpuid_fault(vcpu)))
3938 vcpu->arch.msr_misc_features_enables = data;
3940 #ifdef CONFIG_X86_64
3942 if (!msr_info->host_initiated &&
3943 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3946 if (data & ~kvm_guest_supported_xfd(vcpu))
3949 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3951 case MSR_IA32_XFD_ERR:
3952 if (!msr_info->host_initiated &&
3953 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3956 if (data & ~kvm_guest_supported_xfd(vcpu))
3959 vcpu->arch.guest_fpu.xfd_err = data;
3963 if (kvm_pmu_is_valid_msr(vcpu, msr))
3964 return kvm_pmu_set_msr(vcpu, msr_info);
3967 * Userspace is allowed to write '0' to MSRs that KVM reports
3968 * as to-be-saved, even if an MSRs isn't fully supported.
3970 if (msr_info->host_initiated && !data &&
3971 kvm_is_msr_to_save(msr))
3974 return KVM_MSR_RET_INVALID;
3978 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3980 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3983 u64 mcg_cap = vcpu->arch.mcg_cap;
3984 unsigned bank_num = mcg_cap & 0xff;
3985 u32 offset, last_msr;
3988 case MSR_IA32_P5_MC_ADDR:
3989 case MSR_IA32_P5_MC_TYPE:
3992 case MSR_IA32_MCG_CAP:
3993 data = vcpu->arch.mcg_cap;
3995 case MSR_IA32_MCG_CTL:
3996 if (!(mcg_cap & MCG_CTL_P) && !host)
3998 data = vcpu->arch.mcg_ctl;
4000 case MSR_IA32_MCG_STATUS:
4001 data = vcpu->arch.mcg_status;
4003 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4004 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
4008 if (!(mcg_cap & MCG_CMCI_P) && !host)
4010 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
4011 last_msr + 1 - MSR_IA32_MC0_CTL2);
4012 data = vcpu->arch.mci_ctl2_banks[offset];
4014 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4015 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
4019 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
4020 last_msr + 1 - MSR_IA32_MC0_CTL);
4021 data = vcpu->arch.mce_banks[offset];
4030 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4032 switch (msr_info->index) {
4033 case MSR_IA32_PLATFORM_ID:
4034 case MSR_IA32_EBL_CR_POWERON:
4035 case MSR_IA32_LASTBRANCHFROMIP:
4036 case MSR_IA32_LASTBRANCHTOIP:
4037 case MSR_IA32_LASTINTFROMIP:
4038 case MSR_IA32_LASTINTTOIP:
4039 case MSR_AMD64_SYSCFG:
4040 case MSR_K8_TSEG_ADDR:
4041 case MSR_K8_TSEG_MASK:
4042 case MSR_VM_HSAVE_PA:
4043 case MSR_K8_INT_PENDING_MSG:
4044 case MSR_AMD64_NB_CFG:
4045 case MSR_FAM10H_MMIO_CONF_BASE:
4046 case MSR_AMD64_BU_CFG2:
4047 case MSR_IA32_PERF_CTL:
4048 case MSR_AMD64_DC_CFG:
4049 case MSR_F15H_EX_CFG:
4051 * Intel Sandy Bridge CPUs must support the RAPL (running average power
4052 * limit) MSRs. Just return 0, as we do not want to expose the host
4053 * data here. Do not conditionalize this on CPUID, as KVM does not do
4054 * so for existing CPU-specific MSRs.
4056 case MSR_RAPL_POWER_UNIT:
4057 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
4058 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
4059 case MSR_PKG_ENERGY_STATUS: /* Total package */
4060 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
4063 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
4064 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
4065 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
4066 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
4067 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4068 return kvm_pmu_get_msr(vcpu, msr_info);
4071 case MSR_IA32_UCODE_REV:
4072 msr_info->data = vcpu->arch.microcode_version;
4074 case MSR_IA32_ARCH_CAPABILITIES:
4075 if (!msr_info->host_initiated &&
4076 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4078 msr_info->data = vcpu->arch.arch_capabilities;
4080 case MSR_IA32_PERF_CAPABILITIES:
4081 if (!msr_info->host_initiated &&
4082 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
4084 msr_info->data = vcpu->arch.perf_capabilities;
4086 case MSR_IA32_POWER_CTL:
4087 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
4089 case MSR_IA32_TSC: {
4091 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
4092 * even when not intercepted. AMD manual doesn't explicitly
4093 * state this but appears to behave the same.
4095 * On userspace reads and writes, however, we unconditionally
4096 * return L1's TSC value to ensure backwards-compatible
4097 * behavior for migration.
4101 if (msr_info->host_initiated) {
4102 offset = vcpu->arch.l1_tsc_offset;
4103 ratio = vcpu->arch.l1_tsc_scaling_ratio;
4105 offset = vcpu->arch.tsc_offset;
4106 ratio = vcpu->arch.tsc_scaling_ratio;
4109 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
4113 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
4114 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
4115 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
4116 case 0xcd: /* fsb frequency */
4120 * MSR_EBC_FREQUENCY_ID
4121 * Conservative value valid for even the basic CPU models.
4122 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
4123 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
4124 * and 266MHz for model 3, or 4. Set Core Clock
4125 * Frequency to System Bus Frequency Ratio to 1 (bits
4126 * 31:24) even though these are only valid for CPU
4127 * models > 2, however guests may end up dividing or
4128 * multiplying by zero otherwise.
4130 case MSR_EBC_FREQUENCY_ID:
4131 msr_info->data = 1 << 24;
4133 case MSR_IA32_APICBASE:
4134 msr_info->data = kvm_get_apic_base(vcpu);
4136 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
4137 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
4138 case MSR_IA32_TSC_DEADLINE:
4139 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
4141 case MSR_IA32_TSC_ADJUST:
4142 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
4144 case MSR_IA32_MISC_ENABLE:
4145 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
4147 case MSR_IA32_SMBASE:
4148 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
4150 msr_info->data = vcpu->arch.smbase;
4153 msr_info->data = vcpu->arch.smi_count;
4155 case MSR_IA32_PERF_STATUS:
4156 /* TSC increment by tick */
4157 msr_info->data = 1000ULL;
4158 /* CPU multiplier */
4159 msr_info->data |= (((uint64_t)4ULL) << 40);
4162 msr_info->data = vcpu->arch.efer;
4164 case MSR_KVM_WALL_CLOCK:
4165 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4168 msr_info->data = vcpu->kvm->arch.wall_clock;
4170 case MSR_KVM_WALL_CLOCK_NEW:
4171 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4174 msr_info->data = vcpu->kvm->arch.wall_clock;
4176 case MSR_KVM_SYSTEM_TIME:
4177 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4180 msr_info->data = vcpu->arch.time;
4182 case MSR_KVM_SYSTEM_TIME_NEW:
4183 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4186 msr_info->data = vcpu->arch.time;
4188 case MSR_KVM_ASYNC_PF_EN:
4189 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4192 msr_info->data = vcpu->arch.apf.msr_en_val;
4194 case MSR_KVM_ASYNC_PF_INT:
4195 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4198 msr_info->data = vcpu->arch.apf.msr_int_val;
4200 case MSR_KVM_ASYNC_PF_ACK:
4201 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4206 case MSR_KVM_STEAL_TIME:
4207 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4210 msr_info->data = vcpu->arch.st.msr_val;
4212 case MSR_KVM_PV_EOI_EN:
4213 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4216 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4218 case MSR_KVM_POLL_CONTROL:
4219 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4222 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4224 case MSR_IA32_P5_MC_ADDR:
4225 case MSR_IA32_P5_MC_TYPE:
4226 case MSR_IA32_MCG_CAP:
4227 case MSR_IA32_MCG_CTL:
4228 case MSR_IA32_MCG_STATUS:
4229 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4230 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4231 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4232 msr_info->host_initiated);
4234 if (!msr_info->host_initiated &&
4235 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4237 msr_info->data = vcpu->arch.ia32_xss;
4239 case MSR_K7_CLK_CTL:
4241 * Provide expected ramp-up count for K7. All other
4242 * are set to zero, indicating minimum divisors for
4245 * This prevents guest kernels on AMD host with CPU
4246 * type 6, model 8 and higher from exploding due to
4247 * the rdmsr failing.
4249 msr_info->data = 0x20000000;
4251 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4252 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4253 case HV_X64_MSR_SYNDBG_OPTIONS:
4254 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4255 case HV_X64_MSR_CRASH_CTL:
4256 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4257 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4258 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4259 case HV_X64_MSR_TSC_EMULATION_STATUS:
4260 case HV_X64_MSR_TSC_INVARIANT_CONTROL:
4261 return kvm_hv_get_msr_common(vcpu,
4262 msr_info->index, &msr_info->data,
4263 msr_info->host_initiated);
4264 case MSR_IA32_BBL_CR_CTL3:
4265 /* This legacy MSR exists but isn't fully documented in current
4266 * silicon. It is however accessed by winxp in very narrow
4267 * scenarios where it sets bit #19, itself documented as
4268 * a "reserved" bit. Best effort attempt to source coherent
4269 * read data here should the balance of the register be
4270 * interpreted by the guest:
4272 * L2 cache control register 3: 64GB range, 256KB size,
4273 * enabled, latency 0x1, configured
4275 msr_info->data = 0xbe702111;
4277 case MSR_AMD64_OSVW_ID_LENGTH:
4278 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4280 msr_info->data = vcpu->arch.osvw.length;
4282 case MSR_AMD64_OSVW_STATUS:
4283 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4285 msr_info->data = vcpu->arch.osvw.status;
4287 case MSR_PLATFORM_INFO:
4288 if (!msr_info->host_initiated &&
4289 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4291 msr_info->data = vcpu->arch.msr_platform_info;
4293 case MSR_MISC_FEATURES_ENABLES:
4294 msr_info->data = vcpu->arch.msr_misc_features_enables;
4297 msr_info->data = vcpu->arch.msr_hwcr;
4299 #ifdef CONFIG_X86_64
4301 if (!msr_info->host_initiated &&
4302 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4305 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4307 case MSR_IA32_XFD_ERR:
4308 if (!msr_info->host_initiated &&
4309 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4312 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4316 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4317 return kvm_pmu_get_msr(vcpu, msr_info);
4320 * Userspace is allowed to read MSRs that KVM reports as
4321 * to-be-saved, even if an MSR isn't fully supported.
4323 if (msr_info->host_initiated &&
4324 kvm_is_msr_to_save(msr_info->index)) {
4329 return KVM_MSR_RET_INVALID;
4333 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4336 * Read or write a bunch of msrs. All parameters are kernel addresses.
4338 * @return number of msrs set successfully.
4340 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4341 struct kvm_msr_entry *entries,
4342 int (*do_msr)(struct kvm_vcpu *vcpu,
4343 unsigned index, u64 *data))
4347 for (i = 0; i < msrs->nmsrs; ++i)
4348 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4355 * Read or write a bunch of msrs. Parameters are user addresses.
4357 * @return number of msrs set successfully.
4359 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4360 int (*do_msr)(struct kvm_vcpu *vcpu,
4361 unsigned index, u64 *data),
4364 struct kvm_msrs msrs;
4365 struct kvm_msr_entry *entries;
4370 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4374 if (msrs.nmsrs >= MAX_IO_MSRS)
4377 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4378 entries = memdup_user(user_msrs->entries, size);
4379 if (IS_ERR(entries)) {
4380 r = PTR_ERR(entries);
4384 r = __msr_io(vcpu, &msrs, entries, do_msr);
4386 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4394 static inline bool kvm_can_mwait_in_guest(void)
4396 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4397 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4398 boot_cpu_has(X86_FEATURE_ARAT);
4401 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4402 struct kvm_cpuid2 __user *cpuid_arg)
4404 struct kvm_cpuid2 cpuid;
4408 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4411 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4416 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4422 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4427 case KVM_CAP_IRQCHIP:
4429 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4430 case KVM_CAP_SET_TSS_ADDR:
4431 case KVM_CAP_EXT_CPUID:
4432 case KVM_CAP_EXT_EMUL_CPUID:
4433 case KVM_CAP_CLOCKSOURCE:
4435 case KVM_CAP_NOP_IO_DELAY:
4436 case KVM_CAP_MP_STATE:
4437 case KVM_CAP_SYNC_MMU:
4438 case KVM_CAP_USER_NMI:
4439 case KVM_CAP_REINJECT_CONTROL:
4440 case KVM_CAP_IRQ_INJECT_STATUS:
4441 case KVM_CAP_IOEVENTFD:
4442 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4444 case KVM_CAP_PIT_STATE2:
4445 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4446 case KVM_CAP_VCPU_EVENTS:
4447 case KVM_CAP_HYPERV:
4448 case KVM_CAP_HYPERV_VAPIC:
4449 case KVM_CAP_HYPERV_SPIN:
4450 case KVM_CAP_HYPERV_SYNIC:
4451 case KVM_CAP_HYPERV_SYNIC2:
4452 case KVM_CAP_HYPERV_VP_INDEX:
4453 case KVM_CAP_HYPERV_EVENTFD:
4454 case KVM_CAP_HYPERV_TLBFLUSH:
4455 case KVM_CAP_HYPERV_SEND_IPI:
4456 case KVM_CAP_HYPERV_CPUID:
4457 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4458 case KVM_CAP_SYS_HYPERV_CPUID:
4459 case KVM_CAP_PCI_SEGMENT:
4460 case KVM_CAP_DEBUGREGS:
4461 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4463 case KVM_CAP_ASYNC_PF:
4464 case KVM_CAP_ASYNC_PF_INT:
4465 case KVM_CAP_GET_TSC_KHZ:
4466 case KVM_CAP_KVMCLOCK_CTRL:
4467 case KVM_CAP_READONLY_MEM:
4468 case KVM_CAP_HYPERV_TIME:
4469 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4470 case KVM_CAP_TSC_DEADLINE_TIMER:
4471 case KVM_CAP_DISABLE_QUIRKS:
4472 case KVM_CAP_SET_BOOT_CPU_ID:
4473 case KVM_CAP_SPLIT_IRQCHIP:
4474 case KVM_CAP_IMMEDIATE_EXIT:
4475 case KVM_CAP_PMU_EVENT_FILTER:
4476 case KVM_CAP_PMU_EVENT_MASKED_EVENTS:
4477 case KVM_CAP_GET_MSR_FEATURES:
4478 case KVM_CAP_MSR_PLATFORM_INFO:
4479 case KVM_CAP_EXCEPTION_PAYLOAD:
4480 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
4481 case KVM_CAP_SET_GUEST_DEBUG:
4482 case KVM_CAP_LAST_CPU:
4483 case KVM_CAP_X86_USER_SPACE_MSR:
4484 case KVM_CAP_X86_MSR_FILTER:
4485 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4486 #ifdef CONFIG_X86_SGX_KVM
4487 case KVM_CAP_SGX_ATTRIBUTE:
4489 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4490 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4491 case KVM_CAP_SREGS2:
4492 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4493 case KVM_CAP_VCPU_ATTRIBUTES:
4494 case KVM_CAP_SYS_ATTRIBUTES:
4496 case KVM_CAP_ENABLE_CAP:
4497 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
4498 case KVM_CAP_IRQFD_RESAMPLE:
4501 case KVM_CAP_EXIT_HYPERCALL:
4502 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4504 case KVM_CAP_SET_GUEST_DEBUG2:
4505 return KVM_GUESTDBG_VALID_MASK;
4506 #ifdef CONFIG_KVM_XEN
4507 case KVM_CAP_XEN_HVM:
4508 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4509 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4510 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4511 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4512 KVM_XEN_HVM_CONFIG_EVTCHN_SEND;
4513 if (sched_info_on())
4514 r |= KVM_XEN_HVM_CONFIG_RUNSTATE |
4515 KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG;
4518 case KVM_CAP_SYNC_REGS:
4519 r = KVM_SYNC_X86_VALID_FIELDS;
4521 case KVM_CAP_ADJUST_CLOCK:
4522 r = KVM_CLOCK_VALID_FLAGS;
4524 case KVM_CAP_X86_DISABLE_EXITS:
4525 r = KVM_X86_DISABLE_EXITS_PAUSE;
4527 if (!mitigate_smt_rsb) {
4528 r |= KVM_X86_DISABLE_EXITS_HLT |
4529 KVM_X86_DISABLE_EXITS_CSTATE;
4531 if (kvm_can_mwait_in_guest())
4532 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4535 case KVM_CAP_X86_SMM:
4536 if (!IS_ENABLED(CONFIG_KVM_SMM))
4539 /* SMBASE is usually relocated above 1M on modern chipsets,
4540 * and SMM handlers might indeed rely on 4G segment limits,
4541 * so do not report SMM to be available if real mode is
4542 * emulated via vm86 mode. Still, do not go to great lengths
4543 * to avoid userspace's usage of the feature, because it is a
4544 * fringe case that is not enabled except via specific settings
4545 * of the module parameters.
4547 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4549 case KVM_CAP_NR_VCPUS:
4550 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4552 case KVM_CAP_MAX_VCPUS:
4555 case KVM_CAP_MAX_VCPU_ID:
4556 r = KVM_MAX_VCPU_IDS;
4558 case KVM_CAP_PV_MMU: /* obsolete */
4562 r = KVM_MAX_MCE_BANKS;
4565 r = boot_cpu_has(X86_FEATURE_XSAVE);
4567 case KVM_CAP_TSC_CONTROL:
4568 case KVM_CAP_VM_TSC_CONTROL:
4569 r = kvm_caps.has_tsc_control;
4571 case KVM_CAP_X2APIC_API:
4572 r = KVM_X2APIC_API_VALID_FLAGS;
4574 case KVM_CAP_NESTED_STATE:
4575 r = kvm_x86_ops.nested_ops->get_state ?
4576 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4578 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4579 r = kvm_x86_ops.enable_l2_tlb_flush != NULL;
4581 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4582 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4584 case KVM_CAP_SMALLER_MAXPHYADDR:
4585 r = (int) allow_smaller_maxphyaddr;
4587 case KVM_CAP_STEAL_TIME:
4588 r = sched_info_on();
4590 case KVM_CAP_X86_BUS_LOCK_EXIT:
4591 if (kvm_caps.has_bus_lock_exit)
4592 r = KVM_BUS_LOCK_DETECTION_OFF |
4593 KVM_BUS_LOCK_DETECTION_EXIT;
4597 case KVM_CAP_XSAVE2: {
4598 r = xstate_required_size(kvm_get_filtered_xcr0(), false);
4599 if (r < sizeof(struct kvm_xsave))
4600 r = sizeof(struct kvm_xsave);
4603 case KVM_CAP_PMU_CAPABILITY:
4604 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4606 case KVM_CAP_DISABLE_QUIRKS2:
4607 r = KVM_X86_VALID_QUIRKS;
4609 case KVM_CAP_X86_NOTIFY_VMEXIT:
4610 r = kvm_caps.has_notify_vmexit;
4618 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4620 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4622 if ((u64)(unsigned long)uaddr != attr->addr)
4623 return ERR_PTR_USR(-EFAULT);
4627 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4629 u64 __user *uaddr = kvm_get_attr_addr(attr);
4635 return PTR_ERR(uaddr);
4637 switch (attr->attr) {
4638 case KVM_X86_XCOMP_GUEST_SUPP:
4639 if (put_user(kvm_caps.supported_xcr0, uaddr))
4648 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4653 switch (attr->attr) {
4654 case KVM_X86_XCOMP_GUEST_SUPP:
4661 long kvm_arch_dev_ioctl(struct file *filp,
4662 unsigned int ioctl, unsigned long arg)
4664 void __user *argp = (void __user *)arg;
4668 case KVM_GET_MSR_INDEX_LIST: {
4669 struct kvm_msr_list __user *user_msr_list = argp;
4670 struct kvm_msr_list msr_list;
4674 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4677 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4678 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4681 if (n < msr_list.nmsrs)
4684 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4685 num_msrs_to_save * sizeof(u32)))
4687 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4689 num_emulated_msrs * sizeof(u32)))
4694 case KVM_GET_SUPPORTED_CPUID:
4695 case KVM_GET_EMULATED_CPUID: {
4696 struct kvm_cpuid2 __user *cpuid_arg = argp;
4697 struct kvm_cpuid2 cpuid;
4700 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4703 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4709 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4714 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4716 if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
4717 sizeof(kvm_caps.supported_mce_cap)))
4721 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4722 struct kvm_msr_list __user *user_msr_list = argp;
4723 struct kvm_msr_list msr_list;
4727 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4730 msr_list.nmsrs = num_msr_based_features;
4731 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4734 if (n < msr_list.nmsrs)
4737 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4738 num_msr_based_features * sizeof(u32)))
4744 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4746 case KVM_GET_SUPPORTED_HV_CPUID:
4747 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4749 case KVM_GET_DEVICE_ATTR: {
4750 struct kvm_device_attr attr;
4752 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4754 r = kvm_x86_dev_get_attr(&attr);
4757 case KVM_HAS_DEVICE_ATTR: {
4758 struct kvm_device_attr attr;
4760 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4762 r = kvm_x86_dev_has_attr(&attr);
4773 static void wbinvd_ipi(void *garbage)
4778 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4780 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4783 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4785 /* Address WBINVD may be executed by guest */
4786 if (need_emulate_wbinvd(vcpu)) {
4787 if (static_call(kvm_x86_has_wbinvd_exit)())
4788 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4789 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4790 smp_call_function_single(vcpu->cpu,
4791 wbinvd_ipi, NULL, 1);
4794 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4796 /* Save host pkru register if supported */
4797 vcpu->arch.host_pkru = read_pkru();
4799 /* Apply any externally detected TSC adjustments (due to suspend) */
4800 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4801 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4802 vcpu->arch.tsc_offset_adjustment = 0;
4803 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4806 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4807 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4808 rdtsc() - vcpu->arch.last_host_tsc;
4810 mark_tsc_unstable("KVM discovered backwards TSC");
4812 if (kvm_check_tsc_unstable()) {
4813 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4814 vcpu->arch.last_guest_tsc);
4815 kvm_vcpu_write_tsc_offset(vcpu, offset);
4816 vcpu->arch.tsc_catchup = 1;
4819 if (kvm_lapic_hv_timer_in_use(vcpu))
4820 kvm_lapic_restart_hv_timer(vcpu);
4823 * On a host with synchronized TSC, there is no need to update
4824 * kvmclock on vcpu->cpu migration
4826 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4827 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4828 if (vcpu->cpu != cpu)
4829 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4833 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4836 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4838 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4839 struct kvm_steal_time __user *st;
4840 struct kvm_memslots *slots;
4841 static const u8 preempted = KVM_VCPU_PREEMPTED;
4842 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
4845 * The vCPU can be marked preempted if and only if the VM-Exit was on
4846 * an instruction boundary and will not trigger guest emulation of any
4847 * kind (see vcpu_run). Vendor specific code controls (conservatively)
4848 * when this is true, for example allowing the vCPU to be marked
4849 * preempted if and only if the VM-Exit was due to a host interrupt.
4851 if (!vcpu->arch.at_instruction_boundary) {
4852 vcpu->stat.preemption_other++;
4856 vcpu->stat.preemption_reported++;
4857 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4860 if (vcpu->arch.st.preempted)
4863 /* This happens on process exit */
4864 if (unlikely(current->mm != vcpu->kvm->mm))
4867 slots = kvm_memslots(vcpu->kvm);
4869 if (unlikely(slots->generation != ghc->generation ||
4871 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4874 st = (struct kvm_steal_time __user *)ghc->hva;
4875 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4877 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4878 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4880 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4883 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4887 if (vcpu->preempted) {
4888 if (!vcpu->arch.guest_state_protected)
4889 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4892 * Take the srcu lock as memslots will be accessed to check the gfn
4893 * cache generation against the memslots generation.
4895 idx = srcu_read_lock(&vcpu->kvm->srcu);
4896 if (kvm_xen_msr_enabled(vcpu->kvm))
4897 kvm_xen_runstate_set_preempted(vcpu);
4899 kvm_steal_time_set_preempted(vcpu);
4900 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4903 static_call(kvm_x86_vcpu_put)(vcpu);
4904 vcpu->arch.last_host_tsc = rdtsc();
4907 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4908 struct kvm_lapic_state *s)
4910 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4912 return kvm_apic_get_state(vcpu, s);
4915 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4916 struct kvm_lapic_state *s)
4920 r = kvm_apic_set_state(vcpu, s);
4923 update_cr8_intercept(vcpu);
4928 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4931 * We can accept userspace's request for interrupt injection
4932 * as long as we have a place to store the interrupt number.
4933 * The actual injection will happen when the CPU is able to
4934 * deliver the interrupt.
4936 if (kvm_cpu_has_extint(vcpu))
4939 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4940 return (!lapic_in_kernel(vcpu) ||
4941 kvm_apic_accept_pic_intr(vcpu));
4944 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4947 * Do not cause an interrupt window exit if an exception
4948 * is pending or an event needs reinjection; userspace
4949 * might want to inject the interrupt manually using KVM_SET_REGS
4950 * or KVM_SET_SREGS. For that to work, we must be at an
4951 * instruction boundary and with no events half-injected.
4953 return (kvm_arch_interrupt_allowed(vcpu) &&
4954 kvm_cpu_accept_dm_intr(vcpu) &&
4955 !kvm_event_needs_reinjection(vcpu) &&
4956 !kvm_is_exception_pending(vcpu));
4959 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4960 struct kvm_interrupt *irq)
4962 if (irq->irq >= KVM_NR_INTERRUPTS)
4965 if (!irqchip_in_kernel(vcpu->kvm)) {
4966 kvm_queue_interrupt(vcpu, irq->irq, false);
4967 kvm_make_request(KVM_REQ_EVENT, vcpu);
4972 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4973 * fail for in-kernel 8259.
4975 if (pic_in_kernel(vcpu->kvm))
4978 if (vcpu->arch.pending_external_vector != -1)
4981 vcpu->arch.pending_external_vector = irq->irq;
4982 kvm_make_request(KVM_REQ_EVENT, vcpu);
4986 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4988 kvm_inject_nmi(vcpu);
4993 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4994 struct kvm_tpr_access_ctl *tac)
4998 vcpu->arch.tpr_access_reporting = !!tac->enabled;
5002 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
5006 unsigned bank_num = mcg_cap & 0xff, bank;
5009 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
5011 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
5014 vcpu->arch.mcg_cap = mcg_cap;
5015 /* Init IA32_MCG_CTL to all 1s */
5016 if (mcg_cap & MCG_CTL_P)
5017 vcpu->arch.mcg_ctl = ~(u64)0;
5018 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
5019 for (bank = 0; bank < bank_num; bank++) {
5020 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
5021 if (mcg_cap & MCG_CMCI_P)
5022 vcpu->arch.mci_ctl2_banks[bank] = 0;
5025 kvm_apic_after_set_mcg_cap(vcpu);
5027 static_call(kvm_x86_setup_mce)(vcpu);
5033 * Validate this is an UCNA (uncorrectable no action) error by checking the
5034 * MCG_STATUS and MCi_STATUS registers:
5035 * - none of the bits for Machine Check Exceptions are set
5036 * - both the VAL (valid) and UC (uncorrectable) bits are set
5037 * MCI_STATUS_PCC - Processor Context Corrupted
5038 * MCI_STATUS_S - Signaled as a Machine Check Exception
5039 * MCI_STATUS_AR - Software recoverable Action Required
5041 static bool is_ucna(struct kvm_x86_mce *mce)
5043 return !mce->mcg_status &&
5044 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) &&
5045 (mce->status & MCI_STATUS_VAL) &&
5046 (mce->status & MCI_STATUS_UC);
5049 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks)
5051 u64 mcg_cap = vcpu->arch.mcg_cap;
5053 banks[1] = mce->status;
5054 banks[2] = mce->addr;
5055 banks[3] = mce->misc;
5056 vcpu->arch.mcg_status = mce->mcg_status;
5058 if (!(mcg_cap & MCG_CMCI_P) ||
5059 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
5062 if (lapic_in_kernel(vcpu))
5063 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);
5068 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
5069 struct kvm_x86_mce *mce)
5071 u64 mcg_cap = vcpu->arch.mcg_cap;
5072 unsigned bank_num = mcg_cap & 0xff;
5073 u64 *banks = vcpu->arch.mce_banks;
5075 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
5078 banks += array_index_nospec(4 * mce->bank, 4 * bank_num);
5081 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks);
5084 * if IA32_MCG_CTL is not all 1s, the uncorrected error
5085 * reporting is disabled
5087 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
5088 vcpu->arch.mcg_ctl != ~(u64)0)
5091 * if IA32_MCi_CTL is not all 1s, the uncorrected error
5092 * reporting is disabled for the bank
5094 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
5096 if (mce->status & MCI_STATUS_UC) {
5097 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
5098 !kvm_is_cr4_bit_set(vcpu, X86_CR4_MCE)) {
5099 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5102 if (banks[1] & MCI_STATUS_VAL)
5103 mce->status |= MCI_STATUS_OVER;
5104 banks[2] = mce->addr;
5105 banks[3] = mce->misc;
5106 vcpu->arch.mcg_status = mce->mcg_status;
5107 banks[1] = mce->status;
5108 kvm_queue_exception(vcpu, MC_VECTOR);
5109 } else if (!(banks[1] & MCI_STATUS_VAL)
5110 || !(banks[1] & MCI_STATUS_UC)) {
5111 if (banks[1] & MCI_STATUS_VAL)
5112 mce->status |= MCI_STATUS_OVER;
5113 banks[2] = mce->addr;
5114 banks[3] = mce->misc;
5115 banks[1] = mce->status;
5117 banks[1] |= MCI_STATUS_OVER;
5121 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
5122 struct kvm_vcpu_events *events)
5124 struct kvm_queued_exception *ex;
5128 #ifdef CONFIG_KVM_SMM
5129 if (kvm_check_request(KVM_REQ_SMI, vcpu))
5134 * KVM's ABI only allows for one exception to be migrated. Luckily,
5135 * the only time there can be two queued exceptions is if there's a
5136 * non-exiting _injected_ exception, and a pending exiting exception.
5137 * In that case, ignore the VM-Exiting exception as it's an extension
5138 * of the injected exception.
5140 if (vcpu->arch.exception_vmexit.pending &&
5141 !vcpu->arch.exception.pending &&
5142 !vcpu->arch.exception.injected)
5143 ex = &vcpu->arch.exception_vmexit;
5145 ex = &vcpu->arch.exception;
5148 * In guest mode, payload delivery should be deferred if the exception
5149 * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1
5150 * intercepts #PF, ditto for DR6 and #DBs. If the per-VM capability,
5151 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not
5152 * propagate the payload and so it cannot be safely deferred. Deliver
5153 * the payload if the capability hasn't been requested.
5155 if (!vcpu->kvm->arch.exception_payload_enabled &&
5156 ex->pending && ex->has_payload)
5157 kvm_deliver_exception_payload(vcpu, ex);
5159 memset(events, 0, sizeof(*events));
5162 * The API doesn't provide the instruction length for software
5163 * exceptions, so don't report them. As long as the guest RIP
5164 * isn't advanced, we should expect to encounter the exception
5167 if (!kvm_exception_is_soft(ex->vector)) {
5168 events->exception.injected = ex->injected;
5169 events->exception.pending = ex->pending;
5171 * For ABI compatibility, deliberately conflate
5172 * pending and injected exceptions when
5173 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
5175 if (!vcpu->kvm->arch.exception_payload_enabled)
5176 events->exception.injected |= ex->pending;
5178 events->exception.nr = ex->vector;
5179 events->exception.has_error_code = ex->has_error_code;
5180 events->exception.error_code = ex->error_code;
5181 events->exception_has_payload = ex->has_payload;
5182 events->exception_payload = ex->payload;
5184 events->interrupt.injected =
5185 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
5186 events->interrupt.nr = vcpu->arch.interrupt.nr;
5187 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
5189 events->nmi.injected = vcpu->arch.nmi_injected;
5190 events->nmi.pending = kvm_get_nr_pending_nmis(vcpu);
5191 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
5193 /* events->sipi_vector is never valid when reporting to user space */
5195 #ifdef CONFIG_KVM_SMM
5196 events->smi.smm = is_smm(vcpu);
5197 events->smi.pending = vcpu->arch.smi_pending;
5198 events->smi.smm_inside_nmi =
5199 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
5201 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
5203 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
5204 | KVM_VCPUEVENT_VALID_SHADOW
5205 | KVM_VCPUEVENT_VALID_SMM);
5206 if (vcpu->kvm->arch.exception_payload_enabled)
5207 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5208 if (vcpu->kvm->arch.triple_fault_event) {
5209 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5210 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5214 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
5215 struct kvm_vcpu_events *events)
5217 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
5218 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
5219 | KVM_VCPUEVENT_VALID_SHADOW
5220 | KVM_VCPUEVENT_VALID_SMM
5221 | KVM_VCPUEVENT_VALID_PAYLOAD
5222 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
5225 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5226 if (!vcpu->kvm->arch.exception_payload_enabled)
5228 if (events->exception.pending)
5229 events->exception.injected = 0;
5231 events->exception_has_payload = 0;
5233 events->exception.pending = 0;
5234 events->exception_has_payload = 0;
5237 if ((events->exception.injected || events->exception.pending) &&
5238 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
5241 /* INITs are latched while in SMM */
5242 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
5243 (events->smi.smm || events->smi.pending) &&
5244 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
5250 * Flag that userspace is stuffing an exception, the next KVM_RUN will
5251 * morph the exception to a VM-Exit if appropriate. Do this only for
5252 * pending exceptions, already-injected exceptions are not subject to
5253 * intercpetion. Note, userspace that conflates pending and injected
5254 * is hosed, and will incorrectly convert an injected exception into a
5255 * pending exception, which in turn may cause a spurious VM-Exit.
5257 vcpu->arch.exception_from_userspace = events->exception.pending;
5259 vcpu->arch.exception_vmexit.pending = false;
5261 vcpu->arch.exception.injected = events->exception.injected;
5262 vcpu->arch.exception.pending = events->exception.pending;
5263 vcpu->arch.exception.vector = events->exception.nr;
5264 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
5265 vcpu->arch.exception.error_code = events->exception.error_code;
5266 vcpu->arch.exception.has_payload = events->exception_has_payload;
5267 vcpu->arch.exception.payload = events->exception_payload;
5269 vcpu->arch.interrupt.injected = events->interrupt.injected;
5270 vcpu->arch.interrupt.nr = events->interrupt.nr;
5271 vcpu->arch.interrupt.soft = events->interrupt.soft;
5272 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
5273 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
5274 events->interrupt.shadow);
5276 vcpu->arch.nmi_injected = events->nmi.injected;
5277 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) {
5278 vcpu->arch.nmi_pending = 0;
5279 atomic_set(&vcpu->arch.nmi_queued, events->nmi.pending);
5280 kvm_make_request(KVM_REQ_NMI, vcpu);
5282 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
5284 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
5285 lapic_in_kernel(vcpu))
5286 vcpu->arch.apic->sipi_vector = events->sipi_vector;
5288 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
5289 #ifdef CONFIG_KVM_SMM
5290 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
5291 kvm_leave_nested(vcpu);
5292 kvm_smm_changed(vcpu, events->smi.smm);
5295 vcpu->arch.smi_pending = events->smi.pending;
5297 if (events->smi.smm) {
5298 if (events->smi.smm_inside_nmi)
5299 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
5301 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
5305 if (events->smi.smm || events->smi.pending ||
5306 events->smi.smm_inside_nmi)
5310 if (lapic_in_kernel(vcpu)) {
5311 if (events->smi.latched_init)
5312 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5314 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5318 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5319 if (!vcpu->kvm->arch.triple_fault_event)
5321 if (events->triple_fault.pending)
5322 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5324 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5327 kvm_make_request(KVM_REQ_EVENT, vcpu);
5332 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
5333 struct kvm_debugregs *dbgregs)
5337 memset(dbgregs, 0, sizeof(*dbgregs));
5338 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5339 kvm_get_dr(vcpu, 6, &val);
5341 dbgregs->dr7 = vcpu->arch.dr7;
5344 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5345 struct kvm_debugregs *dbgregs)
5350 if (!kvm_dr6_valid(dbgregs->dr6))
5352 if (!kvm_dr7_valid(dbgregs->dr7))
5355 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5356 kvm_update_dr0123(vcpu);
5357 vcpu->arch.dr6 = dbgregs->dr6;
5358 vcpu->arch.dr7 = dbgregs->dr7;
5359 kvm_update_dr7(vcpu);
5364 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5365 struct kvm_xsave *guest_xsave)
5367 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5370 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5371 guest_xsave->region,
5372 sizeof(guest_xsave->region),
5376 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5377 u8 *state, unsigned int size)
5379 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5382 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5383 state, size, vcpu->arch.pkru);
5386 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5387 struct kvm_xsave *guest_xsave)
5389 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5392 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5393 guest_xsave->region,
5394 kvm_caps.supported_xcr0,
5398 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5399 struct kvm_xcrs *guest_xcrs)
5401 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5402 guest_xcrs->nr_xcrs = 0;
5406 guest_xcrs->nr_xcrs = 1;
5407 guest_xcrs->flags = 0;
5408 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5409 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5412 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5413 struct kvm_xcrs *guest_xcrs)
5417 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5420 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5423 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5424 /* Only support XCR0 currently */
5425 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5426 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5427 guest_xcrs->xcrs[i].value);
5436 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5437 * stopped by the hypervisor. This function will be called from the host only.
5438 * EINVAL is returned when the host attempts to set the flag for a guest that
5439 * does not support pv clocks.
5441 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5443 if (!vcpu->arch.pv_time.active)
5445 vcpu->arch.pvclock_set_guest_stopped_request = true;
5446 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5450 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5451 struct kvm_device_attr *attr)
5455 switch (attr->attr) {
5456 case KVM_VCPU_TSC_OFFSET:
5466 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5467 struct kvm_device_attr *attr)
5469 u64 __user *uaddr = kvm_get_attr_addr(attr);
5473 return PTR_ERR(uaddr);
5475 switch (attr->attr) {
5476 case KVM_VCPU_TSC_OFFSET:
5478 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5489 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5490 struct kvm_device_attr *attr)
5492 u64 __user *uaddr = kvm_get_attr_addr(attr);
5493 struct kvm *kvm = vcpu->kvm;
5497 return PTR_ERR(uaddr);
5499 switch (attr->attr) {
5500 case KVM_VCPU_TSC_OFFSET: {
5501 u64 offset, tsc, ns;
5502 unsigned long flags;
5506 if (get_user(offset, uaddr))
5509 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5511 matched = (vcpu->arch.virtual_tsc_khz &&
5512 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5513 kvm->arch.last_tsc_offset == offset);
5515 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5516 ns = get_kvmclock_base_ns();
5518 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5519 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5531 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5535 struct kvm_device_attr attr;
5538 if (copy_from_user(&attr, argp, sizeof(attr)))
5541 if (attr.group != KVM_VCPU_TSC_CTRL)
5545 case KVM_HAS_DEVICE_ATTR:
5546 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5548 case KVM_GET_DEVICE_ATTR:
5549 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5551 case KVM_SET_DEVICE_ATTR:
5552 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5559 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5560 struct kvm_enable_cap *cap)
5563 uint16_t vmcs_version;
5564 void __user *user_ptr;
5570 case KVM_CAP_HYPERV_SYNIC2:
5575 case KVM_CAP_HYPERV_SYNIC:
5576 if (!irqchip_in_kernel(vcpu->kvm))
5578 return kvm_hv_activate_synic(vcpu, cap->cap ==
5579 KVM_CAP_HYPERV_SYNIC2);
5580 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5581 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5583 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5585 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5586 if (copy_to_user(user_ptr, &vmcs_version,
5587 sizeof(vmcs_version)))
5591 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5592 if (!kvm_x86_ops.enable_l2_tlb_flush)
5595 return static_call(kvm_x86_enable_l2_tlb_flush)(vcpu);
5597 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5598 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5600 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5601 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5602 if (vcpu->arch.pv_cpuid.enforce)
5603 kvm_update_pv_runtime(vcpu);
5611 long kvm_arch_vcpu_ioctl(struct file *filp,
5612 unsigned int ioctl, unsigned long arg)
5614 struct kvm_vcpu *vcpu = filp->private_data;
5615 void __user *argp = (void __user *)arg;
5618 struct kvm_sregs2 *sregs2;
5619 struct kvm_lapic_state *lapic;
5620 struct kvm_xsave *xsave;
5621 struct kvm_xcrs *xcrs;
5629 case KVM_GET_LAPIC: {
5631 if (!lapic_in_kernel(vcpu))
5633 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5634 GFP_KERNEL_ACCOUNT);
5639 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5643 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5648 case KVM_SET_LAPIC: {
5650 if (!lapic_in_kernel(vcpu))
5652 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5653 if (IS_ERR(u.lapic)) {
5654 r = PTR_ERR(u.lapic);
5658 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5661 case KVM_INTERRUPT: {
5662 struct kvm_interrupt irq;
5665 if (copy_from_user(&irq, argp, sizeof(irq)))
5667 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5671 r = kvm_vcpu_ioctl_nmi(vcpu);
5675 r = kvm_inject_smi(vcpu);
5678 case KVM_SET_CPUID: {
5679 struct kvm_cpuid __user *cpuid_arg = argp;
5680 struct kvm_cpuid cpuid;
5683 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5685 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5688 case KVM_SET_CPUID2: {
5689 struct kvm_cpuid2 __user *cpuid_arg = argp;
5690 struct kvm_cpuid2 cpuid;
5693 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5695 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5696 cpuid_arg->entries);
5699 case KVM_GET_CPUID2: {
5700 struct kvm_cpuid2 __user *cpuid_arg = argp;
5701 struct kvm_cpuid2 cpuid;
5704 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5706 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5707 cpuid_arg->entries);
5711 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5716 case KVM_GET_MSRS: {
5717 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5718 r = msr_io(vcpu, argp, do_get_msr, 1);
5719 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5722 case KVM_SET_MSRS: {
5723 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5724 r = msr_io(vcpu, argp, do_set_msr, 0);
5725 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5728 case KVM_TPR_ACCESS_REPORTING: {
5729 struct kvm_tpr_access_ctl tac;
5732 if (copy_from_user(&tac, argp, sizeof(tac)))
5734 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5738 if (copy_to_user(argp, &tac, sizeof(tac)))
5743 case KVM_SET_VAPIC_ADDR: {
5744 struct kvm_vapic_addr va;
5748 if (!lapic_in_kernel(vcpu))
5751 if (copy_from_user(&va, argp, sizeof(va)))
5753 idx = srcu_read_lock(&vcpu->kvm->srcu);
5754 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5755 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5758 case KVM_X86_SETUP_MCE: {
5762 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5764 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5767 case KVM_X86_SET_MCE: {
5768 struct kvm_x86_mce mce;
5771 if (copy_from_user(&mce, argp, sizeof(mce)))
5773 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5776 case KVM_GET_VCPU_EVENTS: {
5777 struct kvm_vcpu_events events;
5779 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5782 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5787 case KVM_SET_VCPU_EVENTS: {
5788 struct kvm_vcpu_events events;
5791 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5794 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5797 case KVM_GET_DEBUGREGS: {
5798 struct kvm_debugregs dbgregs;
5800 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5803 if (copy_to_user(argp, &dbgregs,
5804 sizeof(struct kvm_debugregs)))
5809 case KVM_SET_DEBUGREGS: {
5810 struct kvm_debugregs dbgregs;
5813 if (copy_from_user(&dbgregs, argp,
5814 sizeof(struct kvm_debugregs)))
5817 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5820 case KVM_GET_XSAVE: {
5822 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5825 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5830 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5833 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5838 case KVM_SET_XSAVE: {
5839 int size = vcpu->arch.guest_fpu.uabi_size;
5841 u.xsave = memdup_user(argp, size);
5842 if (IS_ERR(u.xsave)) {
5843 r = PTR_ERR(u.xsave);
5847 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5851 case KVM_GET_XSAVE2: {
5852 int size = vcpu->arch.guest_fpu.uabi_size;
5854 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5859 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5862 if (copy_to_user(argp, u.xsave, size))
5869 case KVM_GET_XCRS: {
5870 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5875 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5878 if (copy_to_user(argp, u.xcrs,
5879 sizeof(struct kvm_xcrs)))
5884 case KVM_SET_XCRS: {
5885 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5886 if (IS_ERR(u.xcrs)) {
5887 r = PTR_ERR(u.xcrs);
5891 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5894 case KVM_SET_TSC_KHZ: {
5898 user_tsc_khz = (u32)arg;
5900 if (kvm_caps.has_tsc_control &&
5901 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
5904 if (user_tsc_khz == 0)
5905 user_tsc_khz = tsc_khz;
5907 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5912 case KVM_GET_TSC_KHZ: {
5913 r = vcpu->arch.virtual_tsc_khz;
5916 case KVM_KVMCLOCK_CTRL: {
5917 r = kvm_set_guest_paused(vcpu);
5920 case KVM_ENABLE_CAP: {
5921 struct kvm_enable_cap cap;
5924 if (copy_from_user(&cap, argp, sizeof(cap)))
5926 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5929 case KVM_GET_NESTED_STATE: {
5930 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5934 if (!kvm_x86_ops.nested_ops->get_state)
5937 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5939 if (get_user(user_data_size, &user_kvm_nested_state->size))
5942 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5947 if (r > user_data_size) {
5948 if (put_user(r, &user_kvm_nested_state->size))
5958 case KVM_SET_NESTED_STATE: {
5959 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5960 struct kvm_nested_state kvm_state;
5964 if (!kvm_x86_ops.nested_ops->set_state)
5968 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5972 if (kvm_state.size < sizeof(kvm_state))
5975 if (kvm_state.flags &
5976 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5977 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5978 | KVM_STATE_NESTED_GIF_SET))
5981 /* nested_run_pending implies guest_mode. */
5982 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5983 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5986 idx = srcu_read_lock(&vcpu->kvm->srcu);
5987 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5988 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5991 case KVM_GET_SUPPORTED_HV_CPUID:
5992 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5994 #ifdef CONFIG_KVM_XEN
5995 case KVM_XEN_VCPU_GET_ATTR: {
5996 struct kvm_xen_vcpu_attr xva;
5999 if (copy_from_user(&xva, argp, sizeof(xva)))
6001 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
6002 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
6006 case KVM_XEN_VCPU_SET_ATTR: {
6007 struct kvm_xen_vcpu_attr xva;
6010 if (copy_from_user(&xva, argp, sizeof(xva)))
6012 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
6016 case KVM_GET_SREGS2: {
6017 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
6021 __get_sregs2(vcpu, u.sregs2);
6023 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
6028 case KVM_SET_SREGS2: {
6029 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
6030 if (IS_ERR(u.sregs2)) {
6031 r = PTR_ERR(u.sregs2);
6035 r = __set_sregs2(vcpu, u.sregs2);
6038 case KVM_HAS_DEVICE_ATTR:
6039 case KVM_GET_DEVICE_ATTR:
6040 case KVM_SET_DEVICE_ATTR:
6041 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
6053 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
6055 return VM_FAULT_SIGBUS;
6058 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
6062 if (addr > (unsigned int)(-3 * PAGE_SIZE))
6064 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
6068 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
6071 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
6074 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
6075 unsigned long kvm_nr_mmu_pages)
6077 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
6080 mutex_lock(&kvm->slots_lock);
6082 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
6083 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
6085 mutex_unlock(&kvm->slots_lock);
6089 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6091 struct kvm_pic *pic = kvm->arch.vpic;
6095 switch (chip->chip_id) {
6096 case KVM_IRQCHIP_PIC_MASTER:
6097 memcpy(&chip->chip.pic, &pic->pics[0],
6098 sizeof(struct kvm_pic_state));
6100 case KVM_IRQCHIP_PIC_SLAVE:
6101 memcpy(&chip->chip.pic, &pic->pics[1],
6102 sizeof(struct kvm_pic_state));
6104 case KVM_IRQCHIP_IOAPIC:
6105 kvm_get_ioapic(kvm, &chip->chip.ioapic);
6114 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6116 struct kvm_pic *pic = kvm->arch.vpic;
6120 switch (chip->chip_id) {
6121 case KVM_IRQCHIP_PIC_MASTER:
6122 spin_lock(&pic->lock);
6123 memcpy(&pic->pics[0], &chip->chip.pic,
6124 sizeof(struct kvm_pic_state));
6125 spin_unlock(&pic->lock);
6127 case KVM_IRQCHIP_PIC_SLAVE:
6128 spin_lock(&pic->lock);
6129 memcpy(&pic->pics[1], &chip->chip.pic,
6130 sizeof(struct kvm_pic_state));
6131 spin_unlock(&pic->lock);
6133 case KVM_IRQCHIP_IOAPIC:
6134 kvm_set_ioapic(kvm, &chip->chip.ioapic);
6140 kvm_pic_update_irq(pic);
6144 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6146 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
6148 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
6150 mutex_lock(&kps->lock);
6151 memcpy(ps, &kps->channels, sizeof(*ps));
6152 mutex_unlock(&kps->lock);
6156 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6159 struct kvm_pit *pit = kvm->arch.vpit;
6161 mutex_lock(&pit->pit_state.lock);
6162 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
6163 for (i = 0; i < 3; i++)
6164 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
6165 mutex_unlock(&pit->pit_state.lock);
6169 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6171 mutex_lock(&kvm->arch.vpit->pit_state.lock);
6172 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
6173 sizeof(ps->channels));
6174 ps->flags = kvm->arch.vpit->pit_state.flags;
6175 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
6176 memset(&ps->reserved, 0, sizeof(ps->reserved));
6180 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6184 u32 prev_legacy, cur_legacy;
6185 struct kvm_pit *pit = kvm->arch.vpit;
6187 mutex_lock(&pit->pit_state.lock);
6188 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
6189 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
6190 if (!prev_legacy && cur_legacy)
6192 memcpy(&pit->pit_state.channels, &ps->channels,
6193 sizeof(pit->pit_state.channels));
6194 pit->pit_state.flags = ps->flags;
6195 for (i = 0; i < 3; i++)
6196 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
6198 mutex_unlock(&pit->pit_state.lock);
6202 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
6203 struct kvm_reinject_control *control)
6205 struct kvm_pit *pit = kvm->arch.vpit;
6207 /* pit->pit_state.lock was overloaded to prevent userspace from getting
6208 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
6209 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
6211 mutex_lock(&pit->pit_state.lock);
6212 kvm_pit_set_reinject(pit, control->pit_reinject);
6213 mutex_unlock(&pit->pit_state.lock);
6218 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
6222 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
6223 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
6224 * on all VM-Exits, thus we only need to kick running vCPUs to force a
6227 struct kvm_vcpu *vcpu;
6230 kvm_for_each_vcpu(i, vcpu, kvm)
6231 kvm_vcpu_kick(vcpu);
6234 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
6237 if (!irqchip_in_kernel(kvm))
6240 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
6241 irq_event->irq, irq_event->level,
6246 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
6247 struct kvm_enable_cap *cap)
6255 case KVM_CAP_DISABLE_QUIRKS2:
6257 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
6260 case KVM_CAP_DISABLE_QUIRKS:
6261 kvm->arch.disabled_quirks = cap->args[0];
6264 case KVM_CAP_SPLIT_IRQCHIP: {
6265 mutex_lock(&kvm->lock);
6267 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
6268 goto split_irqchip_unlock;
6270 if (irqchip_in_kernel(kvm))
6271 goto split_irqchip_unlock;
6272 if (kvm->created_vcpus)
6273 goto split_irqchip_unlock;
6274 r = kvm_setup_empty_irq_routing(kvm);
6276 goto split_irqchip_unlock;
6277 /* Pairs with irqchip_in_kernel. */
6279 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
6280 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
6281 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6283 split_irqchip_unlock:
6284 mutex_unlock(&kvm->lock);
6287 case KVM_CAP_X2APIC_API:
6289 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
6292 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
6293 kvm->arch.x2apic_format = true;
6294 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
6295 kvm->arch.x2apic_broadcast_quirk_disabled = true;
6299 case KVM_CAP_X86_DISABLE_EXITS:
6301 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
6304 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
6305 kvm->arch.pause_in_guest = true;
6307 #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \
6308 "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests."
6310 if (!mitigate_smt_rsb) {
6311 if (boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible() &&
6312 (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE))
6313 pr_warn_once(SMT_RSB_MSG);
6315 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
6316 kvm_can_mwait_in_guest())
6317 kvm->arch.mwait_in_guest = true;
6318 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
6319 kvm->arch.hlt_in_guest = true;
6320 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
6321 kvm->arch.cstate_in_guest = true;
6326 case KVM_CAP_MSR_PLATFORM_INFO:
6327 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
6330 case KVM_CAP_EXCEPTION_PAYLOAD:
6331 kvm->arch.exception_payload_enabled = cap->args[0];
6334 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
6335 kvm->arch.triple_fault_event = cap->args[0];
6338 case KVM_CAP_X86_USER_SPACE_MSR:
6340 if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK)
6342 kvm->arch.user_space_msr_mask = cap->args[0];
6345 case KVM_CAP_X86_BUS_LOCK_EXIT:
6347 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6350 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6351 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6354 if (kvm_caps.has_bus_lock_exit &&
6355 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6356 kvm->arch.bus_lock_detection_enabled = true;
6359 #ifdef CONFIG_X86_SGX_KVM
6360 case KVM_CAP_SGX_ATTRIBUTE: {
6361 unsigned long allowed_attributes = 0;
6363 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6367 /* KVM only supports the PROVISIONKEY privileged attribute. */
6368 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6369 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6370 kvm->arch.sgx_provisioning_allowed = true;
6376 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6378 if (!kvm_x86_ops.vm_copy_enc_context_from)
6381 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6383 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6385 if (!kvm_x86_ops.vm_move_enc_context_from)
6388 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6390 case KVM_CAP_EXIT_HYPERCALL:
6391 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6395 kvm->arch.hypercall_exit_enabled = cap->args[0];
6398 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6400 if (cap->args[0] & ~1)
6402 kvm->arch.exit_on_emulation_error = cap->args[0];
6405 case KVM_CAP_PMU_CAPABILITY:
6407 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6410 mutex_lock(&kvm->lock);
6411 if (!kvm->created_vcpus) {
6412 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6415 mutex_unlock(&kvm->lock);
6417 case KVM_CAP_MAX_VCPU_ID:
6419 if (cap->args[0] > KVM_MAX_VCPU_IDS)
6422 mutex_lock(&kvm->lock);
6423 if (kvm->arch.max_vcpu_ids == cap->args[0]) {
6425 } else if (!kvm->arch.max_vcpu_ids) {
6426 kvm->arch.max_vcpu_ids = cap->args[0];
6429 mutex_unlock(&kvm->lock);
6431 case KVM_CAP_X86_NOTIFY_VMEXIT:
6433 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
6435 if (!kvm_caps.has_notify_vmexit)
6437 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
6439 mutex_lock(&kvm->lock);
6440 if (!kvm->created_vcpus) {
6441 kvm->arch.notify_window = cap->args[0] >> 32;
6442 kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
6445 mutex_unlock(&kvm->lock);
6447 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
6451 * Since the risk of disabling NX hugepages is a guest crashing
6452 * the system, ensure the userspace process has permission to
6453 * reboot the system.
6455 * Note that unlike the reboot() syscall, the process must have
6456 * this capability in the root namespace because exposing
6457 * /dev/kvm into a container does not limit the scope of the
6458 * iTLB multihit bug to that container. In other words,
6459 * this must use capable(), not ns_capable().
6461 if (!capable(CAP_SYS_BOOT)) {
6469 mutex_lock(&kvm->lock);
6470 if (!kvm->created_vcpus) {
6471 kvm->arch.disable_nx_huge_pages = true;
6474 mutex_unlock(&kvm->lock);
6483 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6485 struct kvm_x86_msr_filter *msr_filter;
6487 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6491 msr_filter->default_allow = default_allow;
6495 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6502 for (i = 0; i < msr_filter->count; i++)
6503 kfree(msr_filter->ranges[i].bitmap);
6508 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6509 struct kvm_msr_filter_range *user_range)
6511 unsigned long *bitmap = NULL;
6514 if (!user_range->nmsrs)
6517 if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK)
6520 if (!user_range->flags)
6523 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6524 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6527 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6529 return PTR_ERR(bitmap);
6531 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6532 .flags = user_range->flags,
6533 .base = user_range->base,
6534 .nmsrs = user_range->nmsrs,
6538 msr_filter->count++;
6542 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm,
6543 struct kvm_msr_filter *filter)
6545 struct kvm_x86_msr_filter *new_filter, *old_filter;
6551 if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK)
6554 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++)
6555 empty &= !filter->ranges[i].nmsrs;
6557 default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY);
6558 if (empty && !default_allow)
6561 new_filter = kvm_alloc_msr_filter(default_allow);
6565 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) {
6566 r = kvm_add_msr_filter(new_filter, &filter->ranges[i]);
6568 kvm_free_msr_filter(new_filter);
6573 mutex_lock(&kvm->lock);
6574 old_filter = rcu_replace_pointer(kvm->arch.msr_filter, new_filter,
6575 mutex_is_locked(&kvm->lock));
6576 mutex_unlock(&kvm->lock);
6577 synchronize_srcu(&kvm->srcu);
6579 kvm_free_msr_filter(old_filter);
6581 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6586 #ifdef CONFIG_KVM_COMPAT
6587 /* for KVM_X86_SET_MSR_FILTER */
6588 struct kvm_msr_filter_range_compat {
6595 struct kvm_msr_filter_compat {
6597 struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES];
6600 #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat)
6602 long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl,
6605 void __user *argp = (void __user *)arg;
6606 struct kvm *kvm = filp->private_data;
6610 case KVM_X86_SET_MSR_FILTER_COMPAT: {
6611 struct kvm_msr_filter __user *user_msr_filter = argp;
6612 struct kvm_msr_filter_compat filter_compat;
6613 struct kvm_msr_filter filter;
6616 if (copy_from_user(&filter_compat, user_msr_filter,
6617 sizeof(filter_compat)))
6620 filter.flags = filter_compat.flags;
6621 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6622 struct kvm_msr_filter_range_compat *cr;
6624 cr = &filter_compat.ranges[i];
6625 filter.ranges[i] = (struct kvm_msr_filter_range) {
6629 .bitmap = (__u8 *)(ulong)cr->bitmap,
6633 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
6642 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6643 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6645 struct kvm_vcpu *vcpu;
6649 mutex_lock(&kvm->lock);
6650 kvm_for_each_vcpu(i, vcpu, kvm) {
6651 if (!vcpu->arch.pv_time.active)
6654 ret = kvm_set_guest_paused(vcpu);
6656 kvm_err("Failed to pause guest VCPU%d: %d\n",
6657 vcpu->vcpu_id, ret);
6661 mutex_unlock(&kvm->lock);
6663 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6666 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6669 case PM_HIBERNATION_PREPARE:
6670 case PM_SUSPEND_PREPARE:
6671 return kvm_arch_suspend_notifier(kvm);
6676 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6678 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6680 struct kvm_clock_data data = { 0 };
6682 get_kvmclock(kvm, &data);
6683 if (copy_to_user(argp, &data, sizeof(data)))
6689 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6691 struct kvm_arch *ka = &kvm->arch;
6692 struct kvm_clock_data data;
6695 if (copy_from_user(&data, argp, sizeof(data)))
6699 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6700 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6702 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6705 kvm_hv_request_tsc_page_update(kvm);
6706 kvm_start_pvclock_update(kvm);
6707 pvclock_update_vm_gtod_copy(kvm);
6710 * This pairs with kvm_guest_time_update(): when masterclock is
6711 * in use, we use master_kernel_ns + kvmclock_offset to set
6712 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6713 * is slightly ahead) here we risk going negative on unsigned
6714 * 'system_time' when 'data.clock' is very small.
6716 if (data.flags & KVM_CLOCK_REALTIME) {
6717 u64 now_real_ns = ktime_get_real_ns();
6720 * Avoid stepping the kvmclock backwards.
6722 if (now_real_ns > data.realtime)
6723 data.clock += now_real_ns - data.realtime;
6726 if (ka->use_master_clock)
6727 now_raw_ns = ka->master_kernel_ns;
6729 now_raw_ns = get_kvmclock_base_ns();
6730 ka->kvmclock_offset = data.clock - now_raw_ns;
6731 kvm_end_pvclock_update(kvm);
6735 int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
6737 struct kvm *kvm = filp->private_data;
6738 void __user *argp = (void __user *)arg;
6741 * This union makes it completely explicit to gcc-3.x
6742 * that these two variables' stack usage should be
6743 * combined, not added together.
6746 struct kvm_pit_state ps;
6747 struct kvm_pit_state2 ps2;
6748 struct kvm_pit_config pit_config;
6752 case KVM_SET_TSS_ADDR:
6753 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6755 case KVM_SET_IDENTITY_MAP_ADDR: {
6758 mutex_lock(&kvm->lock);
6760 if (kvm->created_vcpus)
6761 goto set_identity_unlock;
6763 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6764 goto set_identity_unlock;
6765 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6766 set_identity_unlock:
6767 mutex_unlock(&kvm->lock);
6770 case KVM_SET_NR_MMU_PAGES:
6771 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6773 case KVM_CREATE_IRQCHIP: {
6774 mutex_lock(&kvm->lock);
6777 if (irqchip_in_kernel(kvm))
6778 goto create_irqchip_unlock;
6781 if (kvm->created_vcpus)
6782 goto create_irqchip_unlock;
6784 r = kvm_pic_init(kvm);
6786 goto create_irqchip_unlock;
6788 r = kvm_ioapic_init(kvm);
6790 kvm_pic_destroy(kvm);
6791 goto create_irqchip_unlock;
6794 r = kvm_setup_default_irq_routing(kvm);
6796 kvm_ioapic_destroy(kvm);
6797 kvm_pic_destroy(kvm);
6798 goto create_irqchip_unlock;
6800 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6802 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6803 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6804 create_irqchip_unlock:
6805 mutex_unlock(&kvm->lock);
6808 case KVM_CREATE_PIT:
6809 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6811 case KVM_CREATE_PIT2:
6813 if (copy_from_user(&u.pit_config, argp,
6814 sizeof(struct kvm_pit_config)))
6817 mutex_lock(&kvm->lock);
6820 goto create_pit_unlock;
6822 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6826 mutex_unlock(&kvm->lock);
6828 case KVM_GET_IRQCHIP: {
6829 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6830 struct kvm_irqchip *chip;
6832 chip = memdup_user(argp, sizeof(*chip));
6839 if (!irqchip_kernel(kvm))
6840 goto get_irqchip_out;
6841 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6843 goto get_irqchip_out;
6845 if (copy_to_user(argp, chip, sizeof(*chip)))
6846 goto get_irqchip_out;
6852 case KVM_SET_IRQCHIP: {
6853 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6854 struct kvm_irqchip *chip;
6856 chip = memdup_user(argp, sizeof(*chip));
6863 if (!irqchip_kernel(kvm))
6864 goto set_irqchip_out;
6865 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6872 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6875 if (!kvm->arch.vpit)
6877 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6881 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6888 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6890 mutex_lock(&kvm->lock);
6892 if (!kvm->arch.vpit)
6894 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6896 mutex_unlock(&kvm->lock);
6899 case KVM_GET_PIT2: {
6901 if (!kvm->arch.vpit)
6903 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6907 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6912 case KVM_SET_PIT2: {
6914 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6916 mutex_lock(&kvm->lock);
6918 if (!kvm->arch.vpit)
6920 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6922 mutex_unlock(&kvm->lock);
6925 case KVM_REINJECT_CONTROL: {
6926 struct kvm_reinject_control control;
6928 if (copy_from_user(&control, argp, sizeof(control)))
6931 if (!kvm->arch.vpit)
6933 r = kvm_vm_ioctl_reinject(kvm, &control);
6936 case KVM_SET_BOOT_CPU_ID:
6938 mutex_lock(&kvm->lock);
6939 if (kvm->created_vcpus)
6942 kvm->arch.bsp_vcpu_id = arg;
6943 mutex_unlock(&kvm->lock);
6945 #ifdef CONFIG_KVM_XEN
6946 case KVM_XEN_HVM_CONFIG: {
6947 struct kvm_xen_hvm_config xhc;
6949 if (copy_from_user(&xhc, argp, sizeof(xhc)))
6951 r = kvm_xen_hvm_config(kvm, &xhc);
6954 case KVM_XEN_HVM_GET_ATTR: {
6955 struct kvm_xen_hvm_attr xha;
6958 if (copy_from_user(&xha, argp, sizeof(xha)))
6960 r = kvm_xen_hvm_get_attr(kvm, &xha);
6961 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
6965 case KVM_XEN_HVM_SET_ATTR: {
6966 struct kvm_xen_hvm_attr xha;
6969 if (copy_from_user(&xha, argp, sizeof(xha)))
6971 r = kvm_xen_hvm_set_attr(kvm, &xha);
6974 case KVM_XEN_HVM_EVTCHN_SEND: {
6975 struct kvm_irq_routing_xen_evtchn uxe;
6978 if (copy_from_user(&uxe, argp, sizeof(uxe)))
6980 r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
6985 r = kvm_vm_ioctl_set_clock(kvm, argp);
6988 r = kvm_vm_ioctl_get_clock(kvm, argp);
6990 case KVM_SET_TSC_KHZ: {
6994 user_tsc_khz = (u32)arg;
6996 if (kvm_caps.has_tsc_control &&
6997 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
7000 if (user_tsc_khz == 0)
7001 user_tsc_khz = tsc_khz;
7003 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
7008 case KVM_GET_TSC_KHZ: {
7009 r = READ_ONCE(kvm->arch.default_tsc_khz);
7012 case KVM_MEMORY_ENCRYPT_OP: {
7014 if (!kvm_x86_ops.mem_enc_ioctl)
7017 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
7020 case KVM_MEMORY_ENCRYPT_REG_REGION: {
7021 struct kvm_enc_region region;
7024 if (copy_from_user(®ion, argp, sizeof(region)))
7028 if (!kvm_x86_ops.mem_enc_register_region)
7031 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
7034 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
7035 struct kvm_enc_region region;
7038 if (copy_from_user(®ion, argp, sizeof(region)))
7042 if (!kvm_x86_ops.mem_enc_unregister_region)
7045 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
7048 case KVM_HYPERV_EVENTFD: {
7049 struct kvm_hyperv_eventfd hvevfd;
7052 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
7054 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
7057 case KVM_SET_PMU_EVENT_FILTER:
7058 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
7060 case KVM_X86_SET_MSR_FILTER: {
7061 struct kvm_msr_filter __user *user_msr_filter = argp;
7062 struct kvm_msr_filter filter;
7064 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
7067 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
7077 static void kvm_probe_feature_msr(u32 msr_index)
7079 struct kvm_msr_entry msr = {
7083 if (kvm_get_msr_feature(&msr))
7086 msr_based_features[num_msr_based_features++] = msr_index;
7089 static void kvm_probe_msr_to_save(u32 msr_index)
7093 if (rdmsr_safe(msr_index, &dummy[0], &dummy[1]))
7097 * Even MSRs that are valid in the host may not be exposed to guests in
7100 switch (msr_index) {
7101 case MSR_IA32_BNDCFGS:
7102 if (!kvm_mpx_supported())
7106 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
7107 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
7110 case MSR_IA32_UMWAIT_CONTROL:
7111 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
7114 case MSR_IA32_RTIT_CTL:
7115 case MSR_IA32_RTIT_STATUS:
7116 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
7119 case MSR_IA32_RTIT_CR3_MATCH:
7120 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7121 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
7124 case MSR_IA32_RTIT_OUTPUT_BASE:
7125 case MSR_IA32_RTIT_OUTPUT_MASK:
7126 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7127 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
7128 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
7131 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
7132 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7133 (msr_index - MSR_IA32_RTIT_ADDR0_A >=
7134 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2))
7137 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
7138 if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >=
7139 kvm_pmu_cap.num_counters_gp)
7142 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
7143 if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >=
7144 kvm_pmu_cap.num_counters_gp)
7147 case MSR_ARCH_PERFMON_FIXED_CTR0 ... MSR_ARCH_PERFMON_FIXED_CTR_MAX:
7148 if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >=
7149 kvm_pmu_cap.num_counters_fixed)
7153 case MSR_IA32_XFD_ERR:
7154 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
7157 case MSR_IA32_TSX_CTRL:
7158 if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR))
7165 msrs_to_save[num_msrs_to_save++] = msr_index;
7168 static void kvm_init_msr_lists(void)
7172 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
7173 "Please update the fixed PMCs in msrs_to_save_pmu[]");
7175 num_msrs_to_save = 0;
7176 num_emulated_msrs = 0;
7177 num_msr_based_features = 0;
7179 for (i = 0; i < ARRAY_SIZE(msrs_to_save_base); i++)
7180 kvm_probe_msr_to_save(msrs_to_save_base[i]);
7183 for (i = 0; i < ARRAY_SIZE(msrs_to_save_pmu); i++)
7184 kvm_probe_msr_to_save(msrs_to_save_pmu[i]);
7187 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
7188 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
7191 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
7194 for (i = KVM_FIRST_EMULATED_VMX_MSR; i <= KVM_LAST_EMULATED_VMX_MSR; i++)
7195 kvm_probe_feature_msr(i);
7197 for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++)
7198 kvm_probe_feature_msr(msr_based_features_all_except_vmx[i]);
7201 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
7209 if (!(lapic_in_kernel(vcpu) &&
7210 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
7211 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
7222 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
7229 if (!(lapic_in_kernel(vcpu) &&
7230 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
7232 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
7234 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
7244 void kvm_set_segment(struct kvm_vcpu *vcpu,
7245 struct kvm_segment *var, int seg)
7247 static_call(kvm_x86_set_segment)(vcpu, var, seg);
7250 void kvm_get_segment(struct kvm_vcpu *vcpu,
7251 struct kvm_segment *var, int seg)
7253 static_call(kvm_x86_get_segment)(vcpu, var, seg);
7256 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
7257 struct x86_exception *exception)
7259 struct kvm_mmu *mmu = vcpu->arch.mmu;
7262 BUG_ON(!mmu_is_nested(vcpu));
7264 /* NPT walks are always user-walks */
7265 access |= PFERR_USER_MASK;
7266 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
7271 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
7272 struct x86_exception *exception)
7274 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7276 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7277 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7279 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
7281 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
7282 struct x86_exception *exception)
7284 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7286 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7287 access |= PFERR_WRITE_MASK;
7288 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7290 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
7292 /* uses this to access any guest's mapped memory without checking CPL */
7293 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
7294 struct x86_exception *exception)
7296 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7298 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
7301 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7302 struct kvm_vcpu *vcpu, u64 access,
7303 struct x86_exception *exception)
7305 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7307 int r = X86EMUL_CONTINUE;
7310 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7311 unsigned offset = addr & (PAGE_SIZE-1);
7312 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
7315 if (gpa == INVALID_GPA)
7316 return X86EMUL_PROPAGATE_FAULT;
7317 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
7320 r = X86EMUL_IO_NEEDED;
7332 /* used for instruction fetching */
7333 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
7334 gva_t addr, void *val, unsigned int bytes,
7335 struct x86_exception *exception)
7337 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7338 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7339 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7343 /* Inline kvm_read_guest_virt_helper for speed. */
7344 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
7346 if (unlikely(gpa == INVALID_GPA))
7347 return X86EMUL_PROPAGATE_FAULT;
7349 offset = addr & (PAGE_SIZE-1);
7350 if (WARN_ON(offset + bytes > PAGE_SIZE))
7351 bytes = (unsigned)PAGE_SIZE - offset;
7352 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
7354 if (unlikely(ret < 0))
7355 return X86EMUL_IO_NEEDED;
7357 return X86EMUL_CONTINUE;
7360 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
7361 gva_t addr, void *val, unsigned int bytes,
7362 struct x86_exception *exception)
7364 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7367 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
7368 * is returned, but our callers are not ready for that and they blindly
7369 * call kvm_inject_page_fault. Ensure that they at least do not leak
7370 * uninitialized kernel stack memory into cr2 and error code.
7372 memset(exception, 0, sizeof(*exception));
7373 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
7376 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
7378 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
7379 gva_t addr, void *val, unsigned int bytes,
7380 struct x86_exception *exception, bool system)
7382 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7386 access |= PFERR_IMPLICIT_ACCESS;
7387 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7388 access |= PFERR_USER_MASK;
7390 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
7393 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7394 struct kvm_vcpu *vcpu, u64 access,
7395 struct x86_exception *exception)
7397 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7399 int r = X86EMUL_CONTINUE;
7402 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7403 unsigned offset = addr & (PAGE_SIZE-1);
7404 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
7407 if (gpa == INVALID_GPA)
7408 return X86EMUL_PROPAGATE_FAULT;
7409 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
7411 r = X86EMUL_IO_NEEDED;
7423 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
7424 unsigned int bytes, struct x86_exception *exception,
7427 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7428 u64 access = PFERR_WRITE_MASK;
7431 access |= PFERR_IMPLICIT_ACCESS;
7432 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7433 access |= PFERR_USER_MASK;
7435 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7439 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
7440 unsigned int bytes, struct x86_exception *exception)
7442 /* kvm_write_guest_virt_system can pull in tons of pages. */
7443 vcpu->arch.l1tf_flush_l1d = true;
7445 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7446 PFERR_WRITE_MASK, exception);
7448 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
7450 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
7451 void *insn, int insn_len)
7453 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
7457 int handle_ud(struct kvm_vcpu *vcpu)
7459 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
7460 int fep_flags = READ_ONCE(force_emulation_prefix);
7461 int emul_type = EMULTYPE_TRAP_UD;
7462 char sig[5]; /* ud2; .ascii "kvm" */
7463 struct x86_exception e;
7465 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
7469 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
7470 sig, sizeof(sig), &e) == 0 &&
7471 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
7472 if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF)
7473 kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF);
7474 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
7475 emul_type = EMULTYPE_TRAP_UD_FORCED;
7478 return kvm_emulate_instruction(vcpu, emul_type);
7480 EXPORT_SYMBOL_GPL(handle_ud);
7482 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7483 gpa_t gpa, bool write)
7485 /* For APIC access vmexit */
7486 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7489 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7490 trace_vcpu_match_mmio(gva, gpa, write, true);
7497 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7498 gpa_t *gpa, struct x86_exception *exception,
7501 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7502 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7503 | (write ? PFERR_WRITE_MASK : 0);
7506 * currently PKRU is only applied to ept enabled guest so
7507 * there is no pkey in EPT page table for L1 guest or EPT
7508 * shadow page table for L2 guest.
7510 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7511 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7512 vcpu->arch.mmio_access, 0, access))) {
7513 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7514 (gva & (PAGE_SIZE - 1));
7515 trace_vcpu_match_mmio(gva, *gpa, write, false);
7519 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7521 if (*gpa == INVALID_GPA)
7524 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7527 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7528 const void *val, int bytes)
7532 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7535 kvm_page_track_write(vcpu, gpa, val, bytes);
7539 struct read_write_emulator_ops {
7540 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7542 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7543 void *val, int bytes);
7544 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7545 int bytes, void *val);
7546 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7547 void *val, int bytes);
7551 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7553 if (vcpu->mmio_read_completed) {
7554 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7555 vcpu->mmio_fragments[0].gpa, val);
7556 vcpu->mmio_read_completed = 0;
7563 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7564 void *val, int bytes)
7566 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7569 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7570 void *val, int bytes)
7572 return emulator_write_phys(vcpu, gpa, val, bytes);
7575 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7577 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7578 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7581 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7582 void *val, int bytes)
7584 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7585 return X86EMUL_IO_NEEDED;
7588 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7589 void *val, int bytes)
7591 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7593 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7594 return X86EMUL_CONTINUE;
7597 static const struct read_write_emulator_ops read_emultor = {
7598 .read_write_prepare = read_prepare,
7599 .read_write_emulate = read_emulate,
7600 .read_write_mmio = vcpu_mmio_read,
7601 .read_write_exit_mmio = read_exit_mmio,
7604 static const struct read_write_emulator_ops write_emultor = {
7605 .read_write_emulate = write_emulate,
7606 .read_write_mmio = write_mmio,
7607 .read_write_exit_mmio = write_exit_mmio,
7611 static int emulator_read_write_onepage(unsigned long addr, void *val,
7613 struct x86_exception *exception,
7614 struct kvm_vcpu *vcpu,
7615 const struct read_write_emulator_ops *ops)
7619 bool write = ops->write;
7620 struct kvm_mmio_fragment *frag;
7621 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7624 * If the exit was due to a NPF we may already have a GPA.
7625 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7626 * Note, this cannot be used on string operations since string
7627 * operation using rep will only have the initial GPA from the NPF
7630 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7631 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7632 gpa = ctxt->gpa_val;
7633 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7635 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7637 return X86EMUL_PROPAGATE_FAULT;
7640 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7641 return X86EMUL_CONTINUE;
7644 * Is this MMIO handled locally?
7646 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7647 if (handled == bytes)
7648 return X86EMUL_CONTINUE;
7654 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7655 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7659 return X86EMUL_CONTINUE;
7662 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7664 void *val, unsigned int bytes,
7665 struct x86_exception *exception,
7666 const struct read_write_emulator_ops *ops)
7668 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7672 if (ops->read_write_prepare &&
7673 ops->read_write_prepare(vcpu, val, bytes))
7674 return X86EMUL_CONTINUE;
7676 vcpu->mmio_nr_fragments = 0;
7678 /* Crossing a page boundary? */
7679 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7682 now = -addr & ~PAGE_MASK;
7683 rc = emulator_read_write_onepage(addr, val, now, exception,
7686 if (rc != X86EMUL_CONTINUE)
7689 if (ctxt->mode != X86EMUL_MODE_PROT64)
7695 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7697 if (rc != X86EMUL_CONTINUE)
7700 if (!vcpu->mmio_nr_fragments)
7703 gpa = vcpu->mmio_fragments[0].gpa;
7705 vcpu->mmio_needed = 1;
7706 vcpu->mmio_cur_fragment = 0;
7708 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7709 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7710 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7711 vcpu->run->mmio.phys_addr = gpa;
7713 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7716 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7720 struct x86_exception *exception)
7722 return emulator_read_write(ctxt, addr, val, bytes,
7723 exception, &read_emultor);
7726 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7730 struct x86_exception *exception)
7732 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7733 exception, &write_emultor);
7736 #define emulator_try_cmpxchg_user(t, ptr, old, new) \
7737 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t))
7739 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7744 struct x86_exception *exception)
7746 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7752 /* guests cmpxchg8b have to be emulated atomically */
7753 if (bytes > 8 || (bytes & (bytes - 1)))
7756 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7758 if (gpa == INVALID_GPA ||
7759 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7763 * Emulate the atomic as a straight write to avoid #AC if SLD is
7764 * enabled in the host and the access splits a cache line.
7766 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7767 page_line_mask = ~(cache_line_size() - 1);
7769 page_line_mask = PAGE_MASK;
7771 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7774 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa));
7775 if (kvm_is_error_hva(hva))
7778 hva += offset_in_page(gpa);
7782 r = emulator_try_cmpxchg_user(u8, hva, old, new);
7785 r = emulator_try_cmpxchg_user(u16, hva, old, new);
7788 r = emulator_try_cmpxchg_user(u32, hva, old, new);
7791 r = emulator_try_cmpxchg_user(u64, hva, old, new);
7798 return X86EMUL_UNHANDLEABLE;
7800 return X86EMUL_CMPXCHG_FAILED;
7802 kvm_page_track_write(vcpu, gpa, new, bytes);
7804 return X86EMUL_CONTINUE;
7807 pr_warn_once("emulating exchange as write\n");
7809 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7812 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7813 unsigned short port, void *data,
7814 unsigned int count, bool in)
7819 WARN_ON_ONCE(vcpu->arch.pio.count);
7820 for (i = 0; i < count; i++) {
7822 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data);
7824 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data);
7831 * Userspace must have unregistered the device while PIO
7832 * was running. Drop writes / read as 0.
7835 memset(data, 0, size * (count - i));
7844 vcpu->arch.pio.port = port;
7845 vcpu->arch.pio.in = in;
7846 vcpu->arch.pio.count = count;
7847 vcpu->arch.pio.size = size;
7850 memset(vcpu->arch.pio_data, 0, size * count);
7852 memcpy(vcpu->arch.pio_data, data, size * count);
7854 vcpu->run->exit_reason = KVM_EXIT_IO;
7855 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7856 vcpu->run->io.size = size;
7857 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7858 vcpu->run->io.count = count;
7859 vcpu->run->io.port = port;
7863 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7864 unsigned short port, void *val, unsigned int count)
7866 int r = emulator_pio_in_out(vcpu, size, port, val, count, true);
7868 trace_kvm_pio(KVM_PIO_IN, port, size, count, val);
7873 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7875 int size = vcpu->arch.pio.size;
7876 unsigned int count = vcpu->arch.pio.count;
7877 memcpy(val, vcpu->arch.pio_data, size * count);
7878 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7879 vcpu->arch.pio.count = 0;
7882 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7883 int size, unsigned short port, void *val,
7886 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7887 if (vcpu->arch.pio.count) {
7889 * Complete a previous iteration that required userspace I/O.
7890 * Note, @count isn't guaranteed to match pio.count as userspace
7891 * can modify ECX before rerunning the vCPU. Ignore any such
7892 * shenanigans as KVM doesn't support modifying the rep count,
7893 * and the emulator ensures @count doesn't overflow the buffer.
7895 complete_emulator_pio_in(vcpu, val);
7899 return emulator_pio_in(vcpu, size, port, val, count);
7902 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7903 unsigned short port, const void *val,
7906 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val);
7907 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
7910 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7911 int size, unsigned short port,
7912 const void *val, unsigned int count)
7914 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7917 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7919 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7922 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7924 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7927 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7929 if (!need_emulate_wbinvd(vcpu))
7930 return X86EMUL_CONTINUE;
7932 if (static_call(kvm_x86_has_wbinvd_exit)()) {
7933 int cpu = get_cpu();
7935 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7936 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7937 wbinvd_ipi, NULL, 1);
7939 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7942 return X86EMUL_CONTINUE;
7945 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
7947 kvm_emulate_wbinvd_noskip(vcpu);
7948 return kvm_skip_emulated_instruction(vcpu);
7950 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
7954 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
7956 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
7959 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
7960 unsigned long *dest)
7962 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
7965 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
7966 unsigned long value)
7969 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
7972 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
7974 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
7977 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
7979 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7980 unsigned long value;
7984 value = kvm_read_cr0(vcpu);
7987 value = vcpu->arch.cr2;
7990 value = kvm_read_cr3(vcpu);
7993 value = kvm_read_cr4(vcpu);
7996 value = kvm_get_cr8(vcpu);
7999 kvm_err("%s: unexpected cr %u\n", __func__, cr);
8006 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
8008 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8013 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
8016 vcpu->arch.cr2 = val;
8019 res = kvm_set_cr3(vcpu, val);
8022 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8025 res = kvm_set_cr8(vcpu, val);
8028 kvm_err("%s: unexpected cr %u\n", __func__, cr);
8035 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
8037 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
8040 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8042 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
8045 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8047 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
8050 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8052 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
8055 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8057 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
8060 static unsigned long emulator_get_cached_segment_base(
8061 struct x86_emulate_ctxt *ctxt, int seg)
8063 return get_segment_base(emul_to_vcpu(ctxt), seg);
8066 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
8067 struct desc_struct *desc, u32 *base3,
8070 struct kvm_segment var;
8072 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
8073 *selector = var.selector;
8076 memset(desc, 0, sizeof(*desc));
8084 set_desc_limit(desc, var.limit);
8085 set_desc_base(desc, (unsigned long)var.base);
8086 #ifdef CONFIG_X86_64
8088 *base3 = var.base >> 32;
8090 desc->type = var.type;
8092 desc->dpl = var.dpl;
8093 desc->p = var.present;
8094 desc->avl = var.avl;
8102 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
8103 struct desc_struct *desc, u32 base3,
8106 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8107 struct kvm_segment var;
8109 var.selector = selector;
8110 var.base = get_desc_base(desc);
8111 #ifdef CONFIG_X86_64
8112 var.base |= ((u64)base3) << 32;
8114 var.limit = get_desc_limit(desc);
8116 var.limit = (var.limit << 12) | 0xfff;
8117 var.type = desc->type;
8118 var.dpl = desc->dpl;
8123 var.avl = desc->avl;
8124 var.present = desc->p;
8125 var.unusable = !var.present;
8128 kvm_set_segment(vcpu, &var, seg);
8132 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8133 u32 msr_index, u64 *pdata)
8135 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8138 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
8140 return X86EMUL_UNHANDLEABLE;
8143 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
8144 complete_emulated_rdmsr, r))
8145 return X86EMUL_IO_NEEDED;
8147 trace_kvm_msr_read_ex(msr_index);
8148 return X86EMUL_PROPAGATE_FAULT;
8151 trace_kvm_msr_read(msr_index, *pdata);
8152 return X86EMUL_CONTINUE;
8155 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8156 u32 msr_index, u64 data)
8158 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8161 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
8163 return X86EMUL_UNHANDLEABLE;
8166 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
8167 complete_emulated_msr_access, r))
8168 return X86EMUL_IO_NEEDED;
8170 trace_kvm_msr_write_ex(msr_index, data);
8171 return X86EMUL_PROPAGATE_FAULT;
8174 trace_kvm_msr_write(msr_index, data);
8175 return X86EMUL_CONTINUE;
8178 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
8179 u32 msr_index, u64 *pdata)
8181 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
8184 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
8187 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
8192 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
8193 u32 pmc, u64 *pdata)
8195 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
8198 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
8200 emul_to_vcpu(ctxt)->arch.halt_request = 1;
8203 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8204 struct x86_instruction_info *info,
8205 enum x86_intercept_stage stage)
8207 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
8211 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
8212 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
8215 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
8218 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
8220 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
8223 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
8225 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
8228 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
8230 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
8233 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
8235 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
8238 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
8240 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
8243 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
8245 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
8248 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
8250 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
8253 static bool emulator_is_smm(struct x86_emulate_ctxt *ctxt)
8255 return is_smm(emul_to_vcpu(ctxt));
8258 static bool emulator_is_guest_mode(struct x86_emulate_ctxt *ctxt)
8260 return is_guest_mode(emul_to_vcpu(ctxt));
8263 #ifndef CONFIG_KVM_SMM
8264 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt)
8267 return X86EMUL_UNHANDLEABLE;
8271 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
8273 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
8276 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
8278 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
8281 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
8283 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
8285 if (!kvm->vm_bugged)
8289 static const struct x86_emulate_ops emulate_ops = {
8290 .vm_bugged = emulator_vm_bugged,
8291 .read_gpr = emulator_read_gpr,
8292 .write_gpr = emulator_write_gpr,
8293 .read_std = emulator_read_std,
8294 .write_std = emulator_write_std,
8295 .fetch = kvm_fetch_guest_virt,
8296 .read_emulated = emulator_read_emulated,
8297 .write_emulated = emulator_write_emulated,
8298 .cmpxchg_emulated = emulator_cmpxchg_emulated,
8299 .invlpg = emulator_invlpg,
8300 .pio_in_emulated = emulator_pio_in_emulated,
8301 .pio_out_emulated = emulator_pio_out_emulated,
8302 .get_segment = emulator_get_segment,
8303 .set_segment = emulator_set_segment,
8304 .get_cached_segment_base = emulator_get_cached_segment_base,
8305 .get_gdt = emulator_get_gdt,
8306 .get_idt = emulator_get_idt,
8307 .set_gdt = emulator_set_gdt,
8308 .set_idt = emulator_set_idt,
8309 .get_cr = emulator_get_cr,
8310 .set_cr = emulator_set_cr,
8311 .cpl = emulator_get_cpl,
8312 .get_dr = emulator_get_dr,
8313 .set_dr = emulator_set_dr,
8314 .set_msr_with_filter = emulator_set_msr_with_filter,
8315 .get_msr_with_filter = emulator_get_msr_with_filter,
8316 .get_msr = emulator_get_msr,
8317 .check_pmc = emulator_check_pmc,
8318 .read_pmc = emulator_read_pmc,
8319 .halt = emulator_halt,
8320 .wbinvd = emulator_wbinvd,
8321 .fix_hypercall = emulator_fix_hypercall,
8322 .intercept = emulator_intercept,
8323 .get_cpuid = emulator_get_cpuid,
8324 .guest_has_long_mode = emulator_guest_has_long_mode,
8325 .guest_has_movbe = emulator_guest_has_movbe,
8326 .guest_has_fxsr = emulator_guest_has_fxsr,
8327 .guest_has_rdpid = emulator_guest_has_rdpid,
8328 .set_nmi_mask = emulator_set_nmi_mask,
8329 .is_smm = emulator_is_smm,
8330 .is_guest_mode = emulator_is_guest_mode,
8331 .leave_smm = emulator_leave_smm,
8332 .triple_fault = emulator_triple_fault,
8333 .set_xcr = emulator_set_xcr,
8336 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
8338 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8340 * an sti; sti; sequence only disable interrupts for the first
8341 * instruction. So, if the last instruction, be it emulated or
8342 * not, left the system with the INT_STI flag enabled, it
8343 * means that the last instruction is an sti. We should not
8344 * leave the flag on in this case. The same goes for mov ss
8346 if (int_shadow & mask)
8348 if (unlikely(int_shadow || mask)) {
8349 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
8351 kvm_make_request(KVM_REQ_EVENT, vcpu);
8355 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
8357 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8359 if (ctxt->exception.vector == PF_VECTOR)
8360 kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
8361 else if (ctxt->exception.error_code_valid)
8362 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
8363 ctxt->exception.error_code);
8365 kvm_queue_exception(vcpu, ctxt->exception.vector);
8368 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
8370 struct x86_emulate_ctxt *ctxt;
8372 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
8374 pr_err("failed to allocate vcpu's emulator\n");
8379 ctxt->ops = &emulate_ops;
8380 vcpu->arch.emulate_ctxt = ctxt;
8385 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
8387 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8390 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
8392 ctxt->gpa_available = false;
8393 ctxt->eflags = kvm_get_rflags(vcpu);
8394 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
8396 ctxt->eip = kvm_rip_read(vcpu);
8397 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
8398 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
8399 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
8400 cs_db ? X86EMUL_MODE_PROT32 :
8401 X86EMUL_MODE_PROT16;
8402 ctxt->interruptibility = 0;
8403 ctxt->have_exception = false;
8404 ctxt->exception.vector = -1;
8405 ctxt->perm_ok = false;
8407 init_decode_cache(ctxt);
8408 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8411 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
8413 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8416 init_emulate_ctxt(vcpu);
8420 ctxt->_eip = ctxt->eip + inc_eip;
8421 ret = emulate_int_real(ctxt, irq);
8423 if (ret != X86EMUL_CONTINUE) {
8424 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8426 ctxt->eip = ctxt->_eip;
8427 kvm_rip_write(vcpu, ctxt->eip);
8428 kvm_set_rflags(vcpu, ctxt->eflags);
8431 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
8433 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8434 u8 ndata, u8 *insn_bytes, u8 insn_size)
8436 struct kvm_run *run = vcpu->run;
8441 * Zero the whole array used to retrieve the exit info, as casting to
8442 * u32 for select entries will leave some chunks uninitialized.
8444 memset(&info, 0, sizeof(info));
8446 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
8447 &info[2], (u32 *)&info[3],
8450 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8451 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
8454 * There's currently space for 13 entries, but 5 are used for the exit
8455 * reason and info. Restrict to 4 to reduce the maintenance burden
8456 * when expanding kvm_run.emulation_failure in the future.
8458 if (WARN_ON_ONCE(ndata > 4))
8461 /* Always include the flags as a 'data' entry. */
8463 run->emulation_failure.flags = 0;
8466 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8467 sizeof(run->emulation_failure.insn_bytes) != 16));
8469 run->emulation_failure.flags |=
8470 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8471 run->emulation_failure.insn_size = insn_size;
8472 memset(run->emulation_failure.insn_bytes, 0x90,
8473 sizeof(run->emulation_failure.insn_bytes));
8474 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8477 memcpy(&run->internal.data[info_start], info, sizeof(info));
8478 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8479 ndata * sizeof(data[0]));
8481 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8484 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8486 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8488 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8489 ctxt->fetch.end - ctxt->fetch.data);
8492 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8495 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8497 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8499 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8501 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8503 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8505 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8507 struct kvm *kvm = vcpu->kvm;
8509 ++vcpu->stat.insn_emulation_fail;
8510 trace_kvm_emulate_insn_failed(vcpu);
8512 if (emulation_type & EMULTYPE_VMWARE_GP) {
8513 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8517 if (kvm->arch.exit_on_emulation_error ||
8518 (emulation_type & EMULTYPE_SKIP)) {
8519 prepare_emulation_ctxt_failure_exit(vcpu);
8523 kvm_queue_exception(vcpu, UD_VECTOR);
8525 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8526 prepare_emulation_ctxt_failure_exit(vcpu);
8533 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8536 gpa_t gpa = cr2_or_gpa;
8539 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8542 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8543 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8546 if (!vcpu->arch.mmu->root_role.direct) {
8548 * Write permission should be allowed since only
8549 * write access need to be emulated.
8551 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8554 * If the mapping is invalid in guest, let cpu retry
8555 * it to generate fault.
8557 if (gpa == INVALID_GPA)
8562 * Do not retry the unhandleable instruction if it faults on the
8563 * readonly host memory, otherwise it will goto a infinite loop:
8564 * retry instruction -> write #PF -> emulation fail -> retry
8565 * instruction -> ...
8567 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8570 * If the instruction failed on the error pfn, it can not be fixed,
8571 * report the error to userspace.
8573 if (is_error_noslot_pfn(pfn))
8576 kvm_release_pfn_clean(pfn);
8578 /* The instructions are well-emulated on direct mmu. */
8579 if (vcpu->arch.mmu->root_role.direct) {
8580 unsigned int indirect_shadow_pages;
8582 write_lock(&vcpu->kvm->mmu_lock);
8583 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8584 write_unlock(&vcpu->kvm->mmu_lock);
8586 if (indirect_shadow_pages)
8587 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8593 * if emulation was due to access to shadowed page table
8594 * and it failed try to unshadow page and re-enter the
8595 * guest to let CPU execute the instruction.
8597 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8600 * If the access faults on its page table, it can not
8601 * be fixed by unprotecting shadow page and it should
8602 * be reported to userspace.
8604 return !(emulation_type & EMULTYPE_WRITE_PF_TO_SP);
8607 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8608 gpa_t cr2_or_gpa, int emulation_type)
8610 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8611 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8613 last_retry_eip = vcpu->arch.last_retry_eip;
8614 last_retry_addr = vcpu->arch.last_retry_addr;
8617 * If the emulation is caused by #PF and it is non-page_table
8618 * writing instruction, it means the VM-EXIT is caused by shadow
8619 * page protected, we can zap the shadow page and retry this
8620 * instruction directly.
8622 * Note: if the guest uses a non-page-table modifying instruction
8623 * on the PDE that points to the instruction, then we will unmap
8624 * the instruction and go to an infinite loop. So, we cache the
8625 * last retried eip and the last fault address, if we meet the eip
8626 * and the address again, we can break out of the potential infinite
8629 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8631 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8634 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8635 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8638 if (x86_page_table_writing_insn(ctxt))
8641 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8644 vcpu->arch.last_retry_eip = ctxt->eip;
8645 vcpu->arch.last_retry_addr = cr2_or_gpa;
8647 if (!vcpu->arch.mmu->root_role.direct)
8648 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8650 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8655 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8656 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8658 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8667 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8668 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8673 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8675 struct kvm_run *kvm_run = vcpu->run;
8677 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8678 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8679 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8680 kvm_run->debug.arch.exception = DB_VECTOR;
8681 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8684 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8688 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8690 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8693 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8697 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8700 * rflags is the old, "raw" value of the flags. The new value has
8701 * not been saved yet.
8703 * This is correct even for TF set by the guest, because "the
8704 * processor will not generate this exception after the instruction
8705 * that sets the TF flag".
8707 if (unlikely(rflags & X86_EFLAGS_TF))
8708 r = kvm_vcpu_do_singlestep(vcpu);
8711 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8713 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
8717 if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
8721 * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
8722 * but AMD CPUs do not. MOV/POP SS blocking is rare, check that first
8723 * to avoid the relatively expensive CPUID lookup.
8725 shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8726 return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
8727 guest_cpuid_is_intel(vcpu);
8730 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,
8731 int emulation_type, int *r)
8733 WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE);
8736 * Do not check for code breakpoints if hardware has already done the
8737 * checks, as inferred from the emulation type. On NO_DECODE and SKIP,
8738 * the instruction has passed all exception checks, and all intercepted
8739 * exceptions that trigger emulation have lower priority than code
8740 * breakpoints, i.e. the fact that the intercepted exception occurred
8741 * means any code breakpoints have already been serviced.
8743 * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as
8744 * hardware has checked the RIP of the magic prefix, but not the RIP of
8745 * the instruction being emulated. The intent of forced emulation is
8746 * to behave as if KVM intercepted the instruction without an exception
8747 * and without a prefix.
8749 if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
8750 EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF))
8753 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8754 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8755 struct kvm_run *kvm_run = vcpu->run;
8756 unsigned long eip = kvm_get_linear_rip(vcpu);
8757 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8758 vcpu->arch.guest_debug_dr7,
8762 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8763 kvm_run->debug.arch.pc = eip;
8764 kvm_run->debug.arch.exception = DB_VECTOR;
8765 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8771 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8772 !kvm_is_code_breakpoint_inhibited(vcpu)) {
8773 unsigned long eip = kvm_get_linear_rip(vcpu);
8774 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8779 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8788 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8790 switch (ctxt->opcode_len) {
8797 case 0xe6: /* OUT */
8801 case 0x6c: /* INS */
8803 case 0x6e: /* OUTS */
8810 case 0x33: /* RDPMC */
8820 * Decode an instruction for emulation. The caller is responsible for handling
8821 * code breakpoints. Note, manually detecting code breakpoints is unnecessary
8822 * (and wrong) when emulating on an intercepted fault-like exception[*], as
8823 * code breakpoints have higher priority and thus have already been done by
8826 * [*] Except #MC, which is higher priority, but KVM should never emulate in
8827 * response to a machine check.
8829 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8830 void *insn, int insn_len)
8832 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8835 init_emulate_ctxt(vcpu);
8837 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8839 trace_kvm_emulate_insn_start(vcpu);
8840 ++vcpu->stat.insn_emulation;
8844 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8846 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8847 int emulation_type, void *insn, int insn_len)
8850 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8851 bool writeback = true;
8853 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8856 vcpu->arch.l1tf_flush_l1d = true;
8858 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8859 kvm_clear_exception_queue(vcpu);
8862 * Return immediately if RIP hits a code breakpoint, such #DBs
8863 * are fault-like and are higher priority than any faults on
8864 * the code fetch itself.
8866 if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r))
8869 r = x86_decode_emulated_instruction(vcpu, emulation_type,
8871 if (r != EMULATION_OK) {
8872 if ((emulation_type & EMULTYPE_TRAP_UD) ||
8873 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8874 kvm_queue_exception(vcpu, UD_VECTOR);
8877 if (reexecute_instruction(vcpu, cr2_or_gpa,
8881 if (ctxt->have_exception &&
8882 !(emulation_type & EMULTYPE_SKIP)) {
8884 * #UD should result in just EMULATION_FAILED, and trap-like
8885 * exception should not be encountered during decode.
8887 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8888 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8889 inject_emulated_exception(vcpu);
8892 return handle_emulation_failure(vcpu, emulation_type);
8896 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8897 !is_vmware_backdoor_opcode(ctxt)) {
8898 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8903 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8904 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8905 * The caller is responsible for updating interruptibility state and
8906 * injecting single-step #DBs.
8908 if (emulation_type & EMULTYPE_SKIP) {
8909 if (ctxt->mode != X86EMUL_MODE_PROT64)
8910 ctxt->eip = (u32)ctxt->_eip;
8912 ctxt->eip = ctxt->_eip;
8914 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8919 kvm_rip_write(vcpu, ctxt->eip);
8920 if (ctxt->eflags & X86_EFLAGS_RF)
8921 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8925 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8928 /* this is needed for vmware backdoor interface to work since it
8929 changes registers values during IO operation */
8930 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8931 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8932 emulator_invalidate_register_cache(ctxt);
8936 if (emulation_type & EMULTYPE_PF) {
8937 /* Save the faulting GPA (cr2) in the address field */
8938 ctxt->exception.address = cr2_or_gpa;
8940 /* With shadow page tables, cr2 contains a GVA or nGPA. */
8941 if (vcpu->arch.mmu->root_role.direct) {
8942 ctxt->gpa_available = true;
8943 ctxt->gpa_val = cr2_or_gpa;
8946 /* Sanitize the address out of an abundance of paranoia. */
8947 ctxt->exception.address = 0;
8950 r = x86_emulate_insn(ctxt);
8952 if (r == EMULATION_INTERCEPTED)
8955 if (r == EMULATION_FAILED) {
8956 if (reexecute_instruction(vcpu, cr2_or_gpa, emulation_type))
8959 return handle_emulation_failure(vcpu, emulation_type);
8962 if (ctxt->have_exception) {
8963 WARN_ON_ONCE(vcpu->mmio_needed && !vcpu->mmio_is_write);
8964 vcpu->mmio_needed = false;
8966 inject_emulated_exception(vcpu);
8967 } else if (vcpu->arch.pio.count) {
8968 if (!vcpu->arch.pio.in) {
8969 /* FIXME: return into emulator if single-stepping. */
8970 vcpu->arch.pio.count = 0;
8973 vcpu->arch.complete_userspace_io = complete_emulated_pio;
8976 } else if (vcpu->mmio_needed) {
8977 ++vcpu->stat.mmio_exits;
8979 if (!vcpu->mmio_is_write)
8982 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8983 } else if (vcpu->arch.complete_userspace_io) {
8986 } else if (r == EMULATION_RESTART)
8993 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8994 toggle_interruptibility(vcpu, ctxt->interruptibility);
8995 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8998 * Note, EXCPT_DB is assumed to be fault-like as the emulator
8999 * only supports code breakpoints and general detect #DB, both
9000 * of which are fault-like.
9002 if (!ctxt->have_exception ||
9003 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
9004 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
9005 if (ctxt->is_branch)
9006 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
9007 kvm_rip_write(vcpu, ctxt->eip);
9008 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
9009 r = kvm_vcpu_do_singlestep(vcpu);
9010 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
9011 __kvm_set_rflags(vcpu, ctxt->eflags);
9015 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
9016 * do nothing, and it will be requested again as soon as
9017 * the shadow expires. But we still need to check here,
9018 * because POPF has no interrupt shadow.
9020 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
9021 kvm_make_request(KVM_REQ_EVENT, vcpu);
9023 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
9028 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
9030 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
9032 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
9034 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
9035 void *insn, int insn_len)
9037 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
9039 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
9041 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
9043 vcpu->arch.pio.count = 0;
9047 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
9049 vcpu->arch.pio.count = 0;
9051 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
9054 return kvm_skip_emulated_instruction(vcpu);
9057 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
9058 unsigned short port)
9060 unsigned long val = kvm_rax_read(vcpu);
9061 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
9067 * Workaround userspace that relies on old KVM behavior of %rip being
9068 * incremented prior to exiting to userspace to handle "OUT 0x7e".
9071 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
9072 vcpu->arch.complete_userspace_io =
9073 complete_fast_pio_out_port_0x7e;
9074 kvm_skip_emulated_instruction(vcpu);
9076 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9077 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
9082 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
9086 /* We should only ever be called with arch.pio.count equal to 1 */
9087 BUG_ON(vcpu->arch.pio.count != 1);
9089 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
9090 vcpu->arch.pio.count = 0;
9094 /* For size less than 4 we merge, else we zero extend */
9095 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
9097 complete_emulator_pio_in(vcpu, &val);
9098 kvm_rax_write(vcpu, val);
9100 return kvm_skip_emulated_instruction(vcpu);
9103 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
9104 unsigned short port)
9109 /* For size less than 4 we merge, else we zero extend */
9110 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
9112 ret = emulator_pio_in(vcpu, size, port, &val, 1);
9114 kvm_rax_write(vcpu, val);
9118 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9119 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
9124 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
9129 ret = kvm_fast_pio_in(vcpu, size, port);
9131 ret = kvm_fast_pio_out(vcpu, size, port);
9132 return ret && kvm_skip_emulated_instruction(vcpu);
9134 EXPORT_SYMBOL_GPL(kvm_fast_pio);
9136 static int kvmclock_cpu_down_prep(unsigned int cpu)
9138 __this_cpu_write(cpu_tsc_khz, 0);
9142 static void tsc_khz_changed(void *data)
9144 struct cpufreq_freqs *freq = data;
9145 unsigned long khz = 0;
9147 WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC));
9152 khz = cpufreq_quick_get(raw_smp_processor_id());
9155 __this_cpu_write(cpu_tsc_khz, khz);
9158 #ifdef CONFIG_X86_64
9159 static void kvm_hyperv_tsc_notifier(void)
9164 mutex_lock(&kvm_lock);
9165 list_for_each_entry(kvm, &vm_list, vm_list)
9166 kvm_make_mclock_inprogress_request(kvm);
9168 /* no guest entries from this point */
9169 hyperv_stop_tsc_emulation();
9171 /* TSC frequency always matches when on Hyper-V */
9172 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9173 for_each_present_cpu(cpu)
9174 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
9176 kvm_caps.max_guest_tsc_khz = tsc_khz;
9178 list_for_each_entry(kvm, &vm_list, vm_list) {
9179 __kvm_start_pvclock_update(kvm);
9180 pvclock_update_vm_gtod_copy(kvm);
9181 kvm_end_pvclock_update(kvm);
9184 mutex_unlock(&kvm_lock);
9188 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
9191 struct kvm_vcpu *vcpu;
9196 * We allow guests to temporarily run on slowing clocks,
9197 * provided we notify them after, or to run on accelerating
9198 * clocks, provided we notify them before. Thus time never
9201 * However, we have a problem. We can't atomically update
9202 * the frequency of a given CPU from this function; it is
9203 * merely a notifier, which can be called from any CPU.
9204 * Changing the TSC frequency at arbitrary points in time
9205 * requires a recomputation of local variables related to
9206 * the TSC for each VCPU. We must flag these local variables
9207 * to be updated and be sure the update takes place with the
9208 * new frequency before any guests proceed.
9210 * Unfortunately, the combination of hotplug CPU and frequency
9211 * change creates an intractable locking scenario; the order
9212 * of when these callouts happen is undefined with respect to
9213 * CPU hotplug, and they can race with each other. As such,
9214 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
9215 * undefined; you can actually have a CPU frequency change take
9216 * place in between the computation of X and the setting of the
9217 * variable. To protect against this problem, all updates of
9218 * the per_cpu tsc_khz variable are done in an interrupt
9219 * protected IPI, and all callers wishing to update the value
9220 * must wait for a synchronous IPI to complete (which is trivial
9221 * if the caller is on the CPU already). This establishes the
9222 * necessary total order on variable updates.
9224 * Note that because a guest time update may take place
9225 * anytime after the setting of the VCPU's request bit, the
9226 * correct TSC value must be set before the request. However,
9227 * to ensure the update actually makes it to any guest which
9228 * starts running in hardware virtualization between the set
9229 * and the acquisition of the spinlock, we must also ping the
9230 * CPU after setting the request bit.
9234 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9236 mutex_lock(&kvm_lock);
9237 list_for_each_entry(kvm, &vm_list, vm_list) {
9238 kvm_for_each_vcpu(i, vcpu, kvm) {
9239 if (vcpu->cpu != cpu)
9241 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9242 if (vcpu->cpu != raw_smp_processor_id())
9246 mutex_unlock(&kvm_lock);
9248 if (freq->old < freq->new && send_ipi) {
9250 * We upscale the frequency. Must make the guest
9251 * doesn't see old kvmclock values while running with
9252 * the new frequency, otherwise we risk the guest sees
9253 * time go backwards.
9255 * In case we update the frequency for another cpu
9256 * (which might be in guest context) send an interrupt
9257 * to kick the cpu out of guest context. Next time
9258 * guest context is entered kvmclock will be updated,
9259 * so the guest will not see stale values.
9261 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9265 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
9268 struct cpufreq_freqs *freq = data;
9271 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
9273 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
9276 for_each_cpu(cpu, freq->policy->cpus)
9277 __kvmclock_cpufreq_notifier(freq, cpu);
9282 static struct notifier_block kvmclock_cpufreq_notifier_block = {
9283 .notifier_call = kvmclock_cpufreq_notifier
9286 static int kvmclock_cpu_online(unsigned int cpu)
9288 tsc_khz_changed(NULL);
9292 static void kvm_timer_init(void)
9294 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9295 max_tsc_khz = tsc_khz;
9297 if (IS_ENABLED(CONFIG_CPU_FREQ)) {
9298 struct cpufreq_policy *policy;
9302 policy = cpufreq_cpu_get(cpu);
9304 if (policy->cpuinfo.max_freq)
9305 max_tsc_khz = policy->cpuinfo.max_freq;
9306 cpufreq_cpu_put(policy);
9310 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
9311 CPUFREQ_TRANSITION_NOTIFIER);
9313 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
9314 kvmclock_cpu_online, kvmclock_cpu_down_prep);
9318 #ifdef CONFIG_X86_64
9319 static void pvclock_gtod_update_fn(struct work_struct *work)
9322 struct kvm_vcpu *vcpu;
9325 mutex_lock(&kvm_lock);
9326 list_for_each_entry(kvm, &vm_list, vm_list)
9327 kvm_for_each_vcpu(i, vcpu, kvm)
9328 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9329 atomic_set(&kvm_guest_has_master_clock, 0);
9330 mutex_unlock(&kvm_lock);
9333 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
9336 * Indirection to move queue_work() out of the tk_core.seq write held
9337 * region to prevent possible deadlocks against time accessors which
9338 * are invoked with work related locks held.
9340 static void pvclock_irq_work_fn(struct irq_work *w)
9342 queue_work(system_long_wq, &pvclock_gtod_work);
9345 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
9348 * Notification about pvclock gtod data update.
9350 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
9353 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
9354 struct timekeeper *tk = priv;
9356 update_pvclock_gtod(tk);
9359 * Disable master clock if host does not trust, or does not use,
9360 * TSC based clocksource. Delegate queue_work() to irq_work as
9361 * this is invoked with tk_core.seq write held.
9363 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
9364 atomic_read(&kvm_guest_has_master_clock) != 0)
9365 irq_work_queue(&pvclock_irq_work);
9369 static struct notifier_block pvclock_gtod_notifier = {
9370 .notifier_call = pvclock_gtod_notify,
9374 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
9376 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9378 #define __KVM_X86_OP(func) \
9379 static_call_update(kvm_x86_##func, kvm_x86_ops.func);
9380 #define KVM_X86_OP(func) \
9381 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func)
9382 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP
9383 #define KVM_X86_OP_OPTIONAL_RET0(func) \
9384 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \
9385 (void *)__static_call_return0);
9386 #include <asm/kvm-x86-ops.h>
9389 kvm_pmu_ops_update(ops->pmu_ops);
9392 static int kvm_x86_check_processor_compatibility(void)
9394 int cpu = smp_processor_id();
9395 struct cpuinfo_x86 *c = &cpu_data(cpu);
9398 * Compatibility checks are done when loading KVM and when enabling
9399 * hardware, e.g. during CPU hotplug, to ensure all online CPUs are
9400 * compatible, i.e. KVM should never perform a compatibility check on
9403 WARN_ON(!cpu_online(cpu));
9405 if (__cr4_reserved_bits(cpu_has, c) !=
9406 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9409 return static_call(kvm_x86_check_processor_compatibility)();
9412 static void kvm_x86_check_cpu_compat(void *ret)
9414 *(int *)ret = kvm_x86_check_processor_compatibility();
9417 static int __kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9422 if (kvm_x86_ops.hardware_enable) {
9423 pr_err("already loaded vendor module '%s'\n", kvm_x86_ops.name);
9428 * KVM explicitly assumes that the guest has an FPU and
9429 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
9430 * vCPU's FPU state as a fxregs_state struct.
9432 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
9433 pr_err("inadequate fpu\n");
9437 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9438 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
9443 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes
9444 * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something
9445 * other than WB. Note, EPT doesn't utilize the PAT, but don't bother
9446 * with an exception. PAT[0] is set to WB on RESET and also by the
9447 * kernel, i.e. failure indicates a kernel bug or broken firmware.
9449 if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) ||
9450 (host_pat & GENMASK(2, 0)) != 6) {
9451 pr_err("host PAT[0] is not WB\n");
9455 x86_emulator_cache = kvm_alloc_emulator_cache();
9456 if (!x86_emulator_cache) {
9457 pr_err("failed to allocate cache for x86 emulator\n");
9461 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
9462 if (!user_return_msrs) {
9463 pr_err("failed to allocate percpu kvm_user_return_msrs\n");
9465 goto out_free_x86_emulator_cache;
9467 kvm_nr_uret_msrs = 0;
9469 r = kvm_mmu_vendor_module_init();
9471 goto out_free_percpu;
9473 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
9474 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
9475 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
9478 rdmsrl_safe(MSR_EFER, &host_efer);
9480 if (boot_cpu_has(X86_FEATURE_XSAVES))
9481 rdmsrl(MSR_IA32_XSS, host_xss);
9483 kvm_init_pmu_capability(ops->pmu_ops);
9485 r = ops->hardware_setup();
9489 kvm_ops_update(ops);
9491 for_each_online_cpu(cpu) {
9492 smp_call_function_single(cpu, kvm_x86_check_cpu_compat, &r, 1);
9494 goto out_unwind_ops;
9498 * Point of no return! DO NOT add error paths below this point unless
9499 * absolutely necessary, as most operations from this point forward
9500 * require unwinding.
9504 if (pi_inject_timer == -1)
9505 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
9506 #ifdef CONFIG_X86_64
9507 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
9509 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9510 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
9513 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
9515 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9516 kvm_caps.supported_xss = 0;
9518 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9519 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9520 #undef __kvm_cpu_cap_has
9522 if (kvm_caps.has_tsc_control) {
9524 * Make sure the user can only configure tsc_khz values that
9525 * fit into a signed integer.
9526 * A min value is not calculated because it will always
9527 * be 1 on all machines.
9529 u64 max = min(0x7fffffffULL,
9530 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
9531 kvm_caps.max_guest_tsc_khz = max;
9533 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
9534 kvm_init_msr_lists();
9538 kvm_x86_ops.hardware_enable = NULL;
9539 static_call(kvm_x86_hardware_unsetup)();
9541 kvm_mmu_vendor_module_exit();
9543 free_percpu(user_return_msrs);
9544 out_free_x86_emulator_cache:
9545 kmem_cache_destroy(x86_emulator_cache);
9549 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9553 mutex_lock(&vendor_module_lock);
9554 r = __kvm_x86_vendor_init(ops);
9555 mutex_unlock(&vendor_module_lock);
9559 EXPORT_SYMBOL_GPL(kvm_x86_vendor_init);
9561 void kvm_x86_vendor_exit(void)
9563 kvm_unregister_perf_callbacks();
9565 #ifdef CONFIG_X86_64
9566 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9567 clear_hv_tscchange_cb();
9571 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9572 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
9573 CPUFREQ_TRANSITION_NOTIFIER);
9574 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
9576 #ifdef CONFIG_X86_64
9577 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9578 irq_work_sync(&pvclock_irq_work);
9579 cancel_work_sync(&pvclock_gtod_work);
9581 static_call(kvm_x86_hardware_unsetup)();
9582 kvm_mmu_vendor_module_exit();
9583 free_percpu(user_return_msrs);
9584 kmem_cache_destroy(x86_emulator_cache);
9585 #ifdef CONFIG_KVM_XEN
9586 static_key_deferred_flush(&kvm_xen_enabled);
9587 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9589 mutex_lock(&vendor_module_lock);
9590 kvm_x86_ops.hardware_enable = NULL;
9591 mutex_unlock(&vendor_module_lock);
9593 EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit);
9595 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9598 * The vCPU has halted, e.g. executed HLT. Update the run state if the
9599 * local APIC is in-kernel, the run loop will detect the non-runnable
9600 * state and halt the vCPU. Exit to userspace if the local APIC is
9601 * managed by userspace, in which case userspace is responsible for
9602 * handling wake events.
9604 ++vcpu->stat.halt_exits;
9605 if (lapic_in_kernel(vcpu)) {
9606 vcpu->arch.mp_state = state;
9609 vcpu->run->exit_reason = reason;
9614 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9616 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9618 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9620 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9622 int ret = kvm_skip_emulated_instruction(vcpu);
9624 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9625 * KVM_EXIT_DEBUG here.
9627 return kvm_emulate_halt_noskip(vcpu) && ret;
9629 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9631 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9633 int ret = kvm_skip_emulated_instruction(vcpu);
9635 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9636 KVM_EXIT_AP_RESET_HOLD) && ret;
9638 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9640 #ifdef CONFIG_X86_64
9641 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9642 unsigned long clock_type)
9644 struct kvm_clock_pairing clock_pairing;
9645 struct timespec64 ts;
9649 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9650 return -KVM_EOPNOTSUPP;
9653 * When tsc is in permanent catchup mode guests won't be able to use
9654 * pvclock_read_retry loop to get consistent view of pvclock
9656 if (vcpu->arch.tsc_always_catchup)
9657 return -KVM_EOPNOTSUPP;
9659 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9660 return -KVM_EOPNOTSUPP;
9662 clock_pairing.sec = ts.tv_sec;
9663 clock_pairing.nsec = ts.tv_nsec;
9664 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9665 clock_pairing.flags = 0;
9666 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9669 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9670 sizeof(struct kvm_clock_pairing)))
9678 * kvm_pv_kick_cpu_op: Kick a vcpu.
9680 * @apicid - apicid of vcpu to be kicked.
9682 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9685 * All other fields are unused for APIC_DM_REMRD, but may be consumed by
9686 * common code, e.g. for tracing. Defer initialization to the compiler.
9688 struct kvm_lapic_irq lapic_irq = {
9689 .delivery_mode = APIC_DM_REMRD,
9690 .dest_mode = APIC_DEST_PHYSICAL,
9691 .shorthand = APIC_DEST_NOSHORT,
9695 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9698 bool kvm_apicv_activated(struct kvm *kvm)
9700 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9702 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9704 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
9706 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
9707 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
9709 return (vm_reasons | vcpu_reasons) == 0;
9711 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
9713 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9714 enum kvm_apicv_inhibit reason, bool set)
9717 __set_bit(reason, inhibits);
9719 __clear_bit(reason, inhibits);
9721 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9724 static void kvm_apicv_init(struct kvm *kvm)
9726 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9728 init_rwsem(&kvm->arch.apicv_update_lock);
9730 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9733 set_or_clear_apicv_inhibit(inhibits,
9734 APICV_INHIBIT_REASON_DISABLE, true);
9737 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9739 struct kvm_vcpu *target = NULL;
9740 struct kvm_apic_map *map;
9742 vcpu->stat.directed_yield_attempted++;
9744 if (single_task_running())
9748 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9750 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9751 target = map->phys_map[dest_id]->vcpu;
9755 if (!target || !READ_ONCE(target->ready))
9758 /* Ignore requests to yield to self */
9762 if (kvm_vcpu_yield_to(target) <= 0)
9765 vcpu->stat.directed_yield_successful++;
9771 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9773 u64 ret = vcpu->run->hypercall.ret;
9775 if (!is_64_bit_mode(vcpu))
9777 kvm_rax_write(vcpu, ret);
9778 ++vcpu->stat.hypercalls;
9779 return kvm_skip_emulated_instruction(vcpu);
9782 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9784 unsigned long nr, a0, a1, a2, a3, ret;
9787 if (kvm_xen_hypercall_enabled(vcpu->kvm))
9788 return kvm_xen_hypercall(vcpu);
9790 if (kvm_hv_hypercall_enabled(vcpu))
9791 return kvm_hv_hypercall(vcpu);
9793 nr = kvm_rax_read(vcpu);
9794 a0 = kvm_rbx_read(vcpu);
9795 a1 = kvm_rcx_read(vcpu);
9796 a2 = kvm_rdx_read(vcpu);
9797 a3 = kvm_rsi_read(vcpu);
9799 trace_kvm_hypercall(nr, a0, a1, a2, a3);
9801 op_64_bit = is_64_bit_hypercall(vcpu);
9810 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9818 case KVM_HC_VAPIC_POLL_IRQ:
9821 case KVM_HC_KICK_CPU:
9822 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9825 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9826 kvm_sched_yield(vcpu, a1);
9829 #ifdef CONFIG_X86_64
9830 case KVM_HC_CLOCK_PAIRING:
9831 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9834 case KVM_HC_SEND_IPI:
9835 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9838 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9840 case KVM_HC_SCHED_YIELD:
9841 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9844 kvm_sched_yield(vcpu, a0);
9847 case KVM_HC_MAP_GPA_RANGE: {
9848 u64 gpa = a0, npages = a1, attrs = a2;
9851 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9854 if (!PAGE_ALIGNED(gpa) || !npages ||
9855 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9860 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
9861 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
9862 vcpu->run->hypercall.args[0] = gpa;
9863 vcpu->run->hypercall.args[1] = npages;
9864 vcpu->run->hypercall.args[2] = attrs;
9865 vcpu->run->hypercall.flags = 0;
9867 vcpu->run->hypercall.flags |= KVM_EXIT_HYPERCALL_LONG_MODE;
9869 WARN_ON_ONCE(vcpu->run->hypercall.flags & KVM_EXIT_HYPERCALL_MBZ);
9870 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9880 kvm_rax_write(vcpu, ret);
9882 ++vcpu->stat.hypercalls;
9883 return kvm_skip_emulated_instruction(vcpu);
9885 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9887 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9889 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9890 char instruction[3];
9891 unsigned long rip = kvm_rip_read(vcpu);
9894 * If the quirk is disabled, synthesize a #UD and let the guest pick up
9897 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
9898 ctxt->exception.error_code_valid = false;
9899 ctxt->exception.vector = UD_VECTOR;
9900 ctxt->have_exception = true;
9901 return X86EMUL_PROPAGATE_FAULT;
9904 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9906 return emulator_write_emulated(ctxt, rip, instruction, 3,
9910 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9912 return vcpu->run->request_interrupt_window &&
9913 likely(!pic_in_kernel(vcpu->kvm));
9916 /* Called within kvm->srcu read side. */
9917 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9919 struct kvm_run *kvm_run = vcpu->run;
9921 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9922 kvm_run->cr8 = kvm_get_cr8(vcpu);
9923 kvm_run->apic_base = kvm_get_apic_base(vcpu);
9925 kvm_run->ready_for_interrupt_injection =
9926 pic_in_kernel(vcpu->kvm) ||
9927 kvm_vcpu_ready_for_interrupt_injection(vcpu);
9930 kvm_run->flags |= KVM_RUN_X86_SMM;
9933 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9937 if (!kvm_x86_ops.update_cr8_intercept)
9940 if (!lapic_in_kernel(vcpu))
9943 if (vcpu->arch.apic->apicv_active)
9946 if (!vcpu->arch.apic->vapic_addr)
9947 max_irr = kvm_lapic_find_highest_irr(vcpu);
9954 tpr = kvm_lapic_get_cr8(vcpu);
9956 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
9960 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
9962 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9963 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9967 return kvm_x86_ops.nested_ops->check_events(vcpu);
9970 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
9973 * Suppress the error code if the vCPU is in Real Mode, as Real Mode
9974 * exceptions don't report error codes. The presence of an error code
9975 * is carried with the exception and only stripped when the exception
9976 * is injected as intercepted #PF VM-Exits for AMD's Paged Real Mode do
9977 * report an error code despite the CPU being in Real Mode.
9979 vcpu->arch.exception.has_error_code &= is_protmode(vcpu);
9981 trace_kvm_inj_exception(vcpu->arch.exception.vector,
9982 vcpu->arch.exception.has_error_code,
9983 vcpu->arch.exception.error_code,
9984 vcpu->arch.exception.injected);
9986 static_call(kvm_x86_inject_exception)(vcpu);
9990 * Check for any event (interrupt or exception) that is ready to be injected,
9991 * and if there is at least one event, inject the event with the highest
9992 * priority. This handles both "pending" events, i.e. events that have never
9993 * been injected into the guest, and "injected" events, i.e. events that were
9994 * injected as part of a previous VM-Enter, but weren't successfully delivered
9995 * and need to be re-injected.
9997 * Note, this is not guaranteed to be invoked on a guest instruction boundary,
9998 * i.e. doesn't guarantee that there's an event window in the guest. KVM must
9999 * be able to inject exceptions in the "middle" of an instruction, and so must
10000 * also be able to re-inject NMIs and IRQs in the middle of an instruction.
10001 * I.e. for exceptions and re-injected events, NOT invoking this on instruction
10002 * boundaries is necessary and correct.
10004 * For simplicity, KVM uses a single path to inject all events (except events
10005 * that are injected directly from L1 to L2) and doesn't explicitly track
10006 * instruction boundaries for asynchronous events. However, because VM-Exits
10007 * that can occur during instruction execution typically result in KVM skipping
10008 * the instruction or injecting an exception, e.g. instruction and exception
10009 * intercepts, and because pending exceptions have higher priority than pending
10010 * interrupts, KVM still honors instruction boundaries in most scenarios.
10012 * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip
10013 * the instruction or inject an exception, then KVM can incorrecty inject a new
10014 * asynchrounous event if the event became pending after the CPU fetched the
10015 * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation)
10016 * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be
10017 * injected on the restarted instruction instead of being deferred until the
10018 * instruction completes.
10020 * In practice, this virtualization hole is unlikely to be observed by the
10021 * guest, and even less likely to cause functional problems. To detect the
10022 * hole, the guest would have to trigger an event on a side effect of an early
10023 * phase of instruction execution, e.g. on the instruction fetch from memory.
10024 * And for it to be a functional problem, the guest would need to depend on the
10025 * ordering between that side effect, the instruction completing, _and_ the
10026 * delivery of the asynchronous event.
10028 static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu,
10029 bool *req_immediate_exit)
10035 * Process nested events first, as nested VM-Exit supercedes event
10036 * re-injection. If there's an event queued for re-injection, it will
10037 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit.
10039 if (is_guest_mode(vcpu))
10040 r = kvm_check_nested_events(vcpu);
10045 * Re-inject exceptions and events *especially* if immediate entry+exit
10046 * to/from L2 is needed, as any event that has already been injected
10047 * into L2 needs to complete its lifecycle before injecting a new event.
10049 * Don't re-inject an NMI or interrupt if there is a pending exception.
10050 * This collision arises if an exception occurred while vectoring the
10051 * injected event, KVM intercepted said exception, and KVM ultimately
10052 * determined the fault belongs to the guest and queues the exception
10053 * for injection back into the guest.
10055 * "Injected" interrupts can also collide with pending exceptions if
10056 * userspace ignores the "ready for injection" flag and blindly queues
10057 * an interrupt. In that case, prioritizing the exception is correct,
10058 * as the exception "occurred" before the exit to userspace. Trap-like
10059 * exceptions, e.g. most #DBs, have higher priority than interrupts.
10060 * And while fault-like exceptions, e.g. #GP and #PF, are the lowest
10061 * priority, they're only generated (pended) during instruction
10062 * execution, and interrupts are recognized at instruction boundaries.
10063 * Thus a pending fault-like exception means the fault occurred on the
10064 * *previous* instruction and must be serviced prior to recognizing any
10065 * new events in order to fully complete the previous instruction.
10067 if (vcpu->arch.exception.injected)
10068 kvm_inject_exception(vcpu);
10069 else if (kvm_is_exception_pending(vcpu))
10071 else if (vcpu->arch.nmi_injected)
10072 static_call(kvm_x86_inject_nmi)(vcpu);
10073 else if (vcpu->arch.interrupt.injected)
10074 static_call(kvm_x86_inject_irq)(vcpu, true);
10077 * Exceptions that morph to VM-Exits are handled above, and pending
10078 * exceptions on top of injected exceptions that do not VM-Exit should
10079 * either morph to #DF or, sadly, override the injected exception.
10081 WARN_ON_ONCE(vcpu->arch.exception.injected &&
10082 vcpu->arch.exception.pending);
10085 * Bail if immediate entry+exit to/from the guest is needed to complete
10086 * nested VM-Enter or event re-injection so that a different pending
10087 * event can be serviced (or if KVM needs to exit to userspace).
10089 * Otherwise, continue processing events even if VM-Exit occurred. The
10090 * VM-Exit will have cleared exceptions that were meant for L2, but
10091 * there may now be events that can be injected into L1.
10097 * A pending exception VM-Exit should either result in nested VM-Exit
10098 * or force an immediate re-entry and exit to/from L2, and exception
10099 * VM-Exits cannot be injected (flag should _never_ be set).
10101 WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected ||
10102 vcpu->arch.exception_vmexit.pending);
10105 * New events, other than exceptions, cannot be injected if KVM needs
10106 * to re-inject a previous event. See above comments on re-injecting
10107 * for why pending exceptions get priority.
10109 can_inject = !kvm_event_needs_reinjection(vcpu);
10111 if (vcpu->arch.exception.pending) {
10113 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS
10114 * value pushed on the stack. Trap-like exception and all #DBs
10115 * leave RF as-is (KVM follows Intel's behavior in this regard;
10116 * AMD states that code breakpoint #DBs excplitly clear RF=0).
10118 * Note, most versions of Intel's SDM and AMD's APM incorrectly
10119 * describe the behavior of General Detect #DBs, which are
10120 * fault-like. They do _not_ set RF, a la code breakpoints.
10122 if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT)
10123 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
10126 if (vcpu->arch.exception.vector == DB_VECTOR) {
10127 kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception);
10128 if (vcpu->arch.dr7 & DR7_GD) {
10129 vcpu->arch.dr7 &= ~DR7_GD;
10130 kvm_update_dr7(vcpu);
10134 kvm_inject_exception(vcpu);
10136 vcpu->arch.exception.pending = false;
10137 vcpu->arch.exception.injected = true;
10139 can_inject = false;
10142 /* Don't inject interrupts if the user asked to avoid doing so */
10143 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
10147 * Finally, inject interrupt events. If an event cannot be injected
10148 * due to architectural conditions (e.g. IF=0) a window-open exit
10149 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
10150 * and can architecturally be injected, but we cannot do it right now:
10151 * an interrupt could have arrived just now and we have to inject it
10152 * as a vmexit, or there could already an event in the queue, which is
10153 * indicated by can_inject. In that case we request an immediate exit
10154 * in order to make progress and get back here for another iteration.
10155 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
10157 #ifdef CONFIG_KVM_SMM
10158 if (vcpu->arch.smi_pending) {
10159 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
10163 vcpu->arch.smi_pending = false;
10164 ++vcpu->arch.smi_count;
10166 can_inject = false;
10168 static_call(kvm_x86_enable_smi_window)(vcpu);
10172 if (vcpu->arch.nmi_pending) {
10173 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
10177 --vcpu->arch.nmi_pending;
10178 vcpu->arch.nmi_injected = true;
10179 static_call(kvm_x86_inject_nmi)(vcpu);
10180 can_inject = false;
10181 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
10183 if (vcpu->arch.nmi_pending)
10184 static_call(kvm_x86_enable_nmi_window)(vcpu);
10187 if (kvm_cpu_has_injectable_intr(vcpu)) {
10188 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
10192 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
10193 static_call(kvm_x86_inject_irq)(vcpu, false);
10194 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
10196 if (kvm_cpu_has_injectable_intr(vcpu))
10197 static_call(kvm_x86_enable_irq_window)(vcpu);
10200 if (is_guest_mode(vcpu) &&
10201 kvm_x86_ops.nested_ops->has_events &&
10202 kvm_x86_ops.nested_ops->has_events(vcpu))
10203 *req_immediate_exit = true;
10206 * KVM must never queue a new exception while injecting an event; KVM
10207 * is done emulating and should only propagate the to-be-injected event
10208 * to the VMCS/VMCB. Queueing a new exception can put the vCPU into an
10209 * infinite loop as KVM will bail from VM-Enter to inject the pending
10210 * exception and start the cycle all over.
10212 * Exempt triple faults as they have special handling and won't put the
10213 * vCPU into an infinite loop. Triple fault can be queued when running
10214 * VMX without unrestricted guest, as that requires KVM to emulate Real
10215 * Mode events (see kvm_inject_realmode_interrupt()).
10217 WARN_ON_ONCE(vcpu->arch.exception.pending ||
10218 vcpu->arch.exception_vmexit.pending);
10223 *req_immediate_exit = true;
10229 static void process_nmi(struct kvm_vcpu *vcpu)
10231 unsigned int limit;
10234 * x86 is limited to one NMI pending, but because KVM can't react to
10235 * incoming NMIs as quickly as bare metal, e.g. if the vCPU is
10236 * scheduled out, KVM needs to play nice with two queued NMIs showing
10237 * up at the same time. To handle this scenario, allow two NMIs to be
10238 * (temporarily) pending so long as NMIs are not blocked and KVM is not
10239 * waiting for a previous NMI injection to complete (which effectively
10240 * blocks NMIs). KVM will immediately inject one of the two NMIs, and
10241 * will request an NMI window to handle the second NMI.
10243 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
10249 * Adjust the limit to account for pending virtual NMIs, which aren't
10250 * tracked in vcpu->arch.nmi_pending.
10252 if (static_call(kvm_x86_is_vnmi_pending)(vcpu))
10255 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
10256 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
10258 if (vcpu->arch.nmi_pending &&
10259 (static_call(kvm_x86_set_vnmi_pending)(vcpu)))
10260 vcpu->arch.nmi_pending--;
10262 if (vcpu->arch.nmi_pending)
10263 kvm_make_request(KVM_REQ_EVENT, vcpu);
10266 /* Return total number of NMIs pending injection to the VM */
10267 int kvm_get_nr_pending_nmis(struct kvm_vcpu *vcpu)
10269 return vcpu->arch.nmi_pending +
10270 static_call(kvm_x86_is_vnmi_pending)(vcpu);
10273 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
10274 unsigned long *vcpu_bitmap)
10276 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
10279 void kvm_make_scan_ioapic_request(struct kvm *kvm)
10281 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
10284 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10286 struct kvm_lapic *apic = vcpu->arch.apic;
10289 if (!lapic_in_kernel(vcpu))
10292 down_read(&vcpu->kvm->arch.apicv_update_lock);
10295 /* Do not activate APICV when APIC is disabled */
10296 activate = kvm_vcpu_apicv_activated(vcpu) &&
10297 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED);
10299 if (apic->apicv_active == activate)
10302 apic->apicv_active = activate;
10303 kvm_apic_update_apicv(vcpu);
10304 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
10307 * When APICv gets disabled, we may still have injected interrupts
10308 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10309 * still active when the interrupt got accepted. Make sure
10310 * kvm_check_and_inject_events() is called to check for that.
10312 if (!apic->apicv_active)
10313 kvm_make_request(KVM_REQ_EVENT, vcpu);
10317 up_read(&vcpu->kvm->arch.apicv_update_lock);
10319 EXPORT_SYMBOL_GPL(__kvm_vcpu_update_apicv);
10321 static void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10323 if (!lapic_in_kernel(vcpu))
10327 * Due to sharing page tables across vCPUs, the xAPIC memslot must be
10328 * deleted if any vCPU has xAPIC virtualization and x2APIC enabled, but
10329 * and hardware doesn't support x2APIC virtualization. E.g. some AMD
10330 * CPUs support AVIC but not x2APIC. KVM still allows enabling AVIC in
10331 * this case so that KVM can the AVIC doorbell to inject interrupts to
10332 * running vCPUs, but KVM must not create SPTEs for the APIC base as
10333 * the vCPU would incorrectly be able to access the vAPIC page via MMIO
10334 * despite being in x2APIC mode. For simplicity, inhibiting the APIC
10335 * access page is sticky.
10337 if (apic_x2apic_mode(vcpu->arch.apic) &&
10338 kvm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization)
10339 kvm_inhibit_apic_access_page(vcpu);
10341 __kvm_vcpu_update_apicv(vcpu);
10344 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10345 enum kvm_apicv_inhibit reason, bool set)
10347 unsigned long old, new;
10349 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
10351 if (!(kvm_x86_ops.required_apicv_inhibits & BIT(reason)))
10354 old = new = kvm->arch.apicv_inhibit_reasons;
10356 set_or_clear_apicv_inhibit(&new, reason, set);
10358 if (!!old != !!new) {
10360 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
10361 * false positives in the sanity check WARN in svm_vcpu_run().
10362 * This task will wait for all vCPUs to ack the kick IRQ before
10363 * updating apicv_inhibit_reasons, and all other vCPUs will
10364 * block on acquiring apicv_update_lock so that vCPUs can't
10365 * redo svm_vcpu_run() without seeing the new inhibit state.
10367 * Note, holding apicv_update_lock and taking it in the read
10368 * side (handling the request) also prevents other vCPUs from
10369 * servicing the request with a stale apicv_inhibit_reasons.
10371 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
10372 kvm->arch.apicv_inhibit_reasons = new;
10374 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
10375 int idx = srcu_read_lock(&kvm->srcu);
10377 kvm_zap_gfn_range(kvm, gfn, gfn+1);
10378 srcu_read_unlock(&kvm->srcu, idx);
10381 kvm->arch.apicv_inhibit_reasons = new;
10385 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10386 enum kvm_apicv_inhibit reason, bool set)
10391 down_write(&kvm->arch.apicv_update_lock);
10392 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10393 up_write(&kvm->arch.apicv_update_lock);
10395 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
10397 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
10399 if (!kvm_apic_present(vcpu))
10402 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
10404 if (irqchip_split(vcpu->kvm))
10405 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
10407 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10408 if (ioapic_in_kernel(vcpu->kvm))
10409 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
10412 if (is_guest_mode(vcpu))
10413 vcpu->arch.load_eoi_exitmap_pending = true;
10415 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
10418 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
10420 u64 eoi_exit_bitmap[4];
10422 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
10425 if (to_hv_vcpu(vcpu)) {
10426 bitmap_or((ulong *)eoi_exit_bitmap,
10427 vcpu->arch.ioapic_handled_vectors,
10428 to_hv_synic(vcpu)->vec_bitmap, 256);
10429 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
10433 static_call_cond(kvm_x86_load_eoi_exitmap)(
10434 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
10437 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
10438 unsigned long start, unsigned long end)
10440 unsigned long apic_address;
10443 * The physical address of apic access page is stored in the VMCS.
10444 * Update it when it becomes invalid.
10446 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
10447 if (start <= apic_address && apic_address < end)
10448 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
10451 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
10453 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
10456 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
10458 if (!lapic_in_kernel(vcpu))
10461 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
10464 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
10466 smp_send_reschedule(vcpu->cpu);
10468 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
10471 * Called within kvm->srcu read side.
10472 * Returns 1 to let vcpu_run() continue the guest execution loop without
10473 * exiting to the userspace. Otherwise, the value will be returned to the
10476 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
10480 dm_request_for_irq_injection(vcpu) &&
10481 kvm_cpu_accept_dm_intr(vcpu);
10482 fastpath_t exit_fastpath;
10484 bool req_immediate_exit = false;
10486 if (kvm_request_pending(vcpu)) {
10487 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
10492 if (kvm_dirty_ring_check_request(vcpu)) {
10497 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
10498 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
10503 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
10504 kvm_mmu_free_obsolete_roots(vcpu);
10505 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
10506 __kvm_migrate_timers(vcpu);
10507 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
10508 kvm_update_masterclock(vcpu->kvm);
10509 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
10510 kvm_gen_kvmclock_update(vcpu);
10511 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
10512 r = kvm_guest_time_update(vcpu);
10516 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10517 kvm_mmu_sync_roots(vcpu);
10518 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10519 kvm_mmu_load_pgd(vcpu);
10522 * Note, the order matters here, as flushing "all" TLB entries
10523 * also flushes the "current" TLB entries, i.e. servicing the
10524 * flush "all" will clear any request to flush "current".
10526 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
10527 kvm_vcpu_flush_tlb_all(vcpu);
10529 kvm_service_local_tlb_flush_requests(vcpu);
10532 * Fall back to a "full" guest flush if Hyper-V's precise
10533 * flushing fails. Note, Hyper-V's flushing is per-vCPU, but
10534 * the flushes are considered "remote" and not "local" because
10535 * the requests can be initiated from other vCPUs.
10537 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) &&
10538 kvm_hv_vcpu_flush_tlb(vcpu))
10539 kvm_vcpu_flush_tlb_guest(vcpu);
10541 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10542 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10546 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10547 if (is_guest_mode(vcpu))
10548 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10550 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10551 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10552 vcpu->mmio_needed = 0;
10557 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10558 /* Page is swapped out. Do synthetic halt */
10559 vcpu->arch.apf.halted = true;
10563 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10564 record_steal_time(vcpu);
10565 #ifdef CONFIG_KVM_SMM
10566 if (kvm_check_request(KVM_REQ_SMI, vcpu))
10569 if (kvm_check_request(KVM_REQ_NMI, vcpu))
10571 if (kvm_check_request(KVM_REQ_PMU, vcpu))
10572 kvm_pmu_handle_event(vcpu);
10573 if (kvm_check_request(KVM_REQ_PMI, vcpu))
10574 kvm_pmu_deliver_pmi(vcpu);
10575 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10576 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10577 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10578 vcpu->arch.ioapic_handled_vectors)) {
10579 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10580 vcpu->run->eoi.vector =
10581 vcpu->arch.pending_ioapic_eoi;
10586 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10587 vcpu_scan_ioapic(vcpu);
10588 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10589 vcpu_load_eoi_exitmap(vcpu);
10590 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10591 kvm_vcpu_reload_apic_access_page(vcpu);
10592 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10593 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10594 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10595 vcpu->run->system_event.ndata = 0;
10599 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10600 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10601 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10602 vcpu->run->system_event.ndata = 0;
10606 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10607 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10609 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10610 vcpu->run->hyperv = hv_vcpu->exit;
10616 * KVM_REQ_HV_STIMER has to be processed after
10617 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10618 * depend on the guest clock being up-to-date
10620 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10621 kvm_hv_process_stimers(vcpu);
10622 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10623 kvm_vcpu_update_apicv(vcpu);
10624 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10625 kvm_check_async_pf_completion(vcpu);
10626 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10627 static_call(kvm_x86_msr_filter_changed)(vcpu);
10629 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10630 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10633 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10634 kvm_xen_has_interrupt(vcpu)) {
10635 ++vcpu->stat.req_event;
10636 r = kvm_apic_accept_events(vcpu);
10641 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10646 r = kvm_check_and_inject_events(vcpu, &req_immediate_exit);
10652 static_call(kvm_x86_enable_irq_window)(vcpu);
10654 if (kvm_lapic_enabled(vcpu)) {
10655 update_cr8_intercept(vcpu);
10656 kvm_lapic_sync_to_vapic(vcpu);
10660 r = kvm_mmu_reload(vcpu);
10662 goto cancel_injection;
10667 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10670 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10671 * IPI are then delayed after guest entry, which ensures that they
10672 * result in virtual interrupt delivery.
10674 local_irq_disable();
10676 /* Store vcpu->apicv_active before vcpu->mode. */
10677 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10679 kvm_vcpu_srcu_read_unlock(vcpu);
10682 * 1) We should set ->mode before checking ->requests. Please see
10683 * the comment in kvm_vcpu_exiting_guest_mode().
10685 * 2) For APICv, we should set ->mode before checking PID.ON. This
10686 * pairs with the memory barrier implicit in pi_test_and_set_on
10687 * (see vmx_deliver_posted_interrupt).
10689 * 3) This also orders the write to mode from any reads to the page
10690 * tables done while the VCPU is running. Please see the comment
10691 * in kvm_flush_remote_tlbs.
10693 smp_mb__after_srcu_read_unlock();
10696 * Process pending posted interrupts to handle the case where the
10697 * notification IRQ arrived in the host, or was never sent (because the
10698 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10699 * status, KVM doesn't update assigned devices when APICv is inhibited,
10700 * i.e. they can post interrupts even if APICv is temporarily disabled.
10702 if (kvm_lapic_enabled(vcpu))
10703 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10705 if (kvm_vcpu_exit_request(vcpu)) {
10706 vcpu->mode = OUTSIDE_GUEST_MODE;
10708 local_irq_enable();
10710 kvm_vcpu_srcu_read_lock(vcpu);
10712 goto cancel_injection;
10715 if (req_immediate_exit) {
10716 kvm_make_request(KVM_REQ_EVENT, vcpu);
10717 static_call(kvm_x86_request_immediate_exit)(vcpu);
10720 fpregs_assert_state_consistent();
10721 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10722 switch_fpu_return();
10724 if (vcpu->arch.guest_fpu.xfd_err)
10725 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10727 if (unlikely(vcpu->arch.switch_db_regs)) {
10728 set_debugreg(0, 7);
10729 set_debugreg(vcpu->arch.eff_db[0], 0);
10730 set_debugreg(vcpu->arch.eff_db[1], 1);
10731 set_debugreg(vcpu->arch.eff_db[2], 2);
10732 set_debugreg(vcpu->arch.eff_db[3], 3);
10733 } else if (unlikely(hw_breakpoint_active())) {
10734 set_debugreg(0, 7);
10737 guest_timing_enter_irqoff();
10741 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10742 * update must kick and wait for all vCPUs before toggling the
10743 * per-VM state, and responsing vCPUs must wait for the update
10744 * to complete before servicing KVM_REQ_APICV_UPDATE.
10746 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&
10747 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED));
10749 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10750 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10753 if (kvm_lapic_enabled(vcpu))
10754 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10756 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10757 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10761 /* Note, VM-Exits that go down the "slow" path are accounted below. */
10762 ++vcpu->stat.exits;
10766 * Do this here before restoring debug registers on the host. And
10767 * since we do this before handling the vmexit, a DR access vmexit
10768 * can (a) read the correct value of the debug registers, (b) set
10769 * KVM_DEBUGREG_WONT_EXIT again.
10771 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10772 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10773 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10774 kvm_update_dr0123(vcpu);
10775 kvm_update_dr7(vcpu);
10779 * If the guest has used debug registers, at least dr7
10780 * will be disabled while returning to the host.
10781 * If we don't have active breakpoints in the host, we don't
10782 * care about the messed up debug address registers. But if
10783 * we have some of them active, restore the old state.
10785 if (hw_breakpoint_active())
10786 hw_breakpoint_restore();
10788 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10789 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10791 vcpu->mode = OUTSIDE_GUEST_MODE;
10795 * Sync xfd before calling handle_exit_irqoff() which may
10796 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10797 * in #NM irqoff handler).
10799 if (vcpu->arch.xfd_no_write_intercept)
10800 fpu_sync_guest_vmexit_xfd_state();
10802 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10804 if (vcpu->arch.guest_fpu.xfd_err)
10805 wrmsrl(MSR_IA32_XFD_ERR, 0);
10808 * Consume any pending interrupts, including the possible source of
10809 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10810 * An instruction is required after local_irq_enable() to fully unblock
10811 * interrupts on processors that implement an interrupt shadow, the
10812 * stat.exits increment will do nicely.
10814 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10815 local_irq_enable();
10816 ++vcpu->stat.exits;
10817 local_irq_disable();
10818 kvm_after_interrupt(vcpu);
10821 * Wait until after servicing IRQs to account guest time so that any
10822 * ticks that occurred while running the guest are properly accounted
10823 * to the guest. Waiting until IRQs are enabled degrades the accuracy
10824 * of accounting via context tracking, but the loss of accuracy is
10825 * acceptable for all known use cases.
10827 guest_timing_exit_irqoff();
10829 local_irq_enable();
10832 kvm_vcpu_srcu_read_lock(vcpu);
10835 * Profile KVM exit RIPs:
10837 if (unlikely(prof_on == KVM_PROFILING)) {
10838 unsigned long rip = kvm_rip_read(vcpu);
10839 profile_hit(KVM_PROFILING, (void *)rip);
10842 if (unlikely(vcpu->arch.tsc_always_catchup))
10843 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10845 if (vcpu->arch.apic_attention)
10846 kvm_lapic_sync_from_vapic(vcpu);
10848 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10852 if (req_immediate_exit)
10853 kvm_make_request(KVM_REQ_EVENT, vcpu);
10854 static_call(kvm_x86_cancel_injection)(vcpu);
10855 if (unlikely(vcpu->arch.apic_attention))
10856 kvm_lapic_sync_from_vapic(vcpu);
10861 /* Called within kvm->srcu read side. */
10862 static inline int vcpu_block(struct kvm_vcpu *vcpu)
10866 if (!kvm_arch_vcpu_runnable(vcpu)) {
10868 * Switch to the software timer before halt-polling/blocking as
10869 * the guest's timer may be a break event for the vCPU, and the
10870 * hypervisor timer runs only when the CPU is in guest mode.
10871 * Switch before halt-polling so that KVM recognizes an expired
10872 * timer before blocking.
10874 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10876 kvm_lapic_switch_to_sw_timer(vcpu);
10878 kvm_vcpu_srcu_read_unlock(vcpu);
10879 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10880 kvm_vcpu_halt(vcpu);
10882 kvm_vcpu_block(vcpu);
10883 kvm_vcpu_srcu_read_lock(vcpu);
10886 kvm_lapic_switch_to_hv_timer(vcpu);
10889 * If the vCPU is not runnable, a signal or another host event
10890 * of some kind is pending; service it without changing the
10891 * vCPU's activity state.
10893 if (!kvm_arch_vcpu_runnable(vcpu))
10898 * Evaluate nested events before exiting the halted state. This allows
10899 * the halt state to be recorded properly in the VMCS12's activity
10900 * state field (AMD does not have a similar field and a VM-Exit always
10901 * causes a spurious wakeup from HLT).
10903 if (is_guest_mode(vcpu)) {
10904 if (kvm_check_nested_events(vcpu) < 0)
10908 if (kvm_apic_accept_events(vcpu) < 0)
10910 switch(vcpu->arch.mp_state) {
10911 case KVM_MP_STATE_HALTED:
10912 case KVM_MP_STATE_AP_RESET_HOLD:
10913 vcpu->arch.pv.pv_unhalted = false;
10914 vcpu->arch.mp_state =
10915 KVM_MP_STATE_RUNNABLE;
10917 case KVM_MP_STATE_RUNNABLE:
10918 vcpu->arch.apf.halted = false;
10920 case KVM_MP_STATE_INIT_RECEIVED:
10929 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10931 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10932 !vcpu->arch.apf.halted);
10935 /* Called within kvm->srcu read side. */
10936 static int vcpu_run(struct kvm_vcpu *vcpu)
10940 vcpu->arch.l1tf_flush_l1d = true;
10944 * If another guest vCPU requests a PV TLB flush in the middle
10945 * of instruction emulation, the rest of the emulation could
10946 * use a stale page translation. Assume that any code after
10947 * this point can start executing an instruction.
10949 vcpu->arch.at_instruction_boundary = false;
10950 if (kvm_vcpu_running(vcpu)) {
10951 r = vcpu_enter_guest(vcpu);
10953 r = vcpu_block(vcpu);
10959 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
10960 if (kvm_xen_has_pending_events(vcpu))
10961 kvm_xen_inject_pending_events(vcpu);
10963 if (kvm_cpu_has_pending_timer(vcpu))
10964 kvm_inject_pending_timer_irqs(vcpu);
10966 if (dm_request_for_irq_injection(vcpu) &&
10967 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
10969 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
10970 ++vcpu->stat.request_irq_exits;
10974 if (__xfer_to_guest_mode_work_pending()) {
10975 kvm_vcpu_srcu_read_unlock(vcpu);
10976 r = xfer_to_guest_mode_handle_work(vcpu);
10977 kvm_vcpu_srcu_read_lock(vcpu);
10986 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
10988 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
10991 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
10993 BUG_ON(!vcpu->arch.pio.count);
10995 return complete_emulated_io(vcpu);
10999 * Implements the following, as a state machine:
11002 * for each fragment
11003 * for each mmio piece in the fragment
11010 * for each fragment
11011 * for each mmio piece in the fragment
11016 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
11018 struct kvm_run *run = vcpu->run;
11019 struct kvm_mmio_fragment *frag;
11022 BUG_ON(!vcpu->mmio_needed);
11024 /* Complete previous fragment */
11025 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11026 len = min(8u, frag->len);
11027 if (!vcpu->mmio_is_write)
11028 memcpy(frag->data, run->mmio.data, len);
11030 if (frag->len <= 8) {
11031 /* Switch to the next fragment. */
11033 vcpu->mmio_cur_fragment++;
11035 /* Go forward to the next mmio piece. */
11041 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11042 vcpu->mmio_needed = 0;
11044 /* FIXME: return into emulator if single-stepping. */
11045 if (vcpu->mmio_is_write)
11047 vcpu->mmio_read_completed = 1;
11048 return complete_emulated_io(vcpu);
11051 run->exit_reason = KVM_EXIT_MMIO;
11052 run->mmio.phys_addr = frag->gpa;
11053 if (vcpu->mmio_is_write)
11054 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11055 run->mmio.len = min(8u, frag->len);
11056 run->mmio.is_write = vcpu->mmio_is_write;
11057 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
11061 /* Swap (qemu) user FPU context for the guest FPU context. */
11062 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
11064 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
11065 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
11069 /* When vcpu_run ends, restore user space FPU context. */
11070 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
11072 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
11073 ++vcpu->stat.fpu_reload;
11077 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
11079 struct kvm_queued_exception *ex = &vcpu->arch.exception;
11080 struct kvm_run *kvm_run = vcpu->run;
11084 kvm_sigset_activate(vcpu);
11085 kvm_run->flags = 0;
11086 kvm_load_guest_fpu(vcpu);
11088 kvm_vcpu_srcu_read_lock(vcpu);
11089 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
11090 if (kvm_run->immediate_exit) {
11095 * It should be impossible for the hypervisor timer to be in
11096 * use before KVM has ever run the vCPU.
11098 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu));
11100 kvm_vcpu_srcu_read_unlock(vcpu);
11101 kvm_vcpu_block(vcpu);
11102 kvm_vcpu_srcu_read_lock(vcpu);
11104 if (kvm_apic_accept_events(vcpu) < 0) {
11109 if (signal_pending(current)) {
11111 kvm_run->exit_reason = KVM_EXIT_INTR;
11112 ++vcpu->stat.signal_exits;
11117 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
11118 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
11123 if (kvm_run->kvm_dirty_regs) {
11124 r = sync_regs(vcpu);
11129 /* re-sync apic's tpr */
11130 if (!lapic_in_kernel(vcpu)) {
11131 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
11138 * If userspace set a pending exception and L2 is active, convert it to
11139 * a pending VM-Exit if L1 wants to intercept the exception.
11141 if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) &&
11142 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector,
11144 kvm_queue_exception_vmexit(vcpu, ex->vector,
11145 ex->has_error_code, ex->error_code,
11146 ex->has_payload, ex->payload);
11147 ex->injected = false;
11148 ex->pending = false;
11150 vcpu->arch.exception_from_userspace = false;
11152 if (unlikely(vcpu->arch.complete_userspace_io)) {
11153 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
11154 vcpu->arch.complete_userspace_io = NULL;
11159 WARN_ON_ONCE(vcpu->arch.pio.count);
11160 WARN_ON_ONCE(vcpu->mmio_needed);
11163 if (kvm_run->immediate_exit) {
11168 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
11172 r = vcpu_run(vcpu);
11175 kvm_put_guest_fpu(vcpu);
11176 if (kvm_run->kvm_valid_regs)
11178 post_kvm_run_save(vcpu);
11179 kvm_vcpu_srcu_read_unlock(vcpu);
11181 kvm_sigset_deactivate(vcpu);
11186 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11188 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
11190 * We are here if userspace calls get_regs() in the middle of
11191 * instruction emulation. Registers state needs to be copied
11192 * back from emulation context to vcpu. Userspace shouldn't do
11193 * that usually, but some bad designed PV devices (vmware
11194 * backdoor interface) need this to work
11196 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
11197 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11199 regs->rax = kvm_rax_read(vcpu);
11200 regs->rbx = kvm_rbx_read(vcpu);
11201 regs->rcx = kvm_rcx_read(vcpu);
11202 regs->rdx = kvm_rdx_read(vcpu);
11203 regs->rsi = kvm_rsi_read(vcpu);
11204 regs->rdi = kvm_rdi_read(vcpu);
11205 regs->rsp = kvm_rsp_read(vcpu);
11206 regs->rbp = kvm_rbp_read(vcpu);
11207 #ifdef CONFIG_X86_64
11208 regs->r8 = kvm_r8_read(vcpu);
11209 regs->r9 = kvm_r9_read(vcpu);
11210 regs->r10 = kvm_r10_read(vcpu);
11211 regs->r11 = kvm_r11_read(vcpu);
11212 regs->r12 = kvm_r12_read(vcpu);
11213 regs->r13 = kvm_r13_read(vcpu);
11214 regs->r14 = kvm_r14_read(vcpu);
11215 regs->r15 = kvm_r15_read(vcpu);
11218 regs->rip = kvm_rip_read(vcpu);
11219 regs->rflags = kvm_get_rflags(vcpu);
11222 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11225 __get_regs(vcpu, regs);
11230 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11232 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
11233 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11235 kvm_rax_write(vcpu, regs->rax);
11236 kvm_rbx_write(vcpu, regs->rbx);
11237 kvm_rcx_write(vcpu, regs->rcx);
11238 kvm_rdx_write(vcpu, regs->rdx);
11239 kvm_rsi_write(vcpu, regs->rsi);
11240 kvm_rdi_write(vcpu, regs->rdi);
11241 kvm_rsp_write(vcpu, regs->rsp);
11242 kvm_rbp_write(vcpu, regs->rbp);
11243 #ifdef CONFIG_X86_64
11244 kvm_r8_write(vcpu, regs->r8);
11245 kvm_r9_write(vcpu, regs->r9);
11246 kvm_r10_write(vcpu, regs->r10);
11247 kvm_r11_write(vcpu, regs->r11);
11248 kvm_r12_write(vcpu, regs->r12);
11249 kvm_r13_write(vcpu, regs->r13);
11250 kvm_r14_write(vcpu, regs->r14);
11251 kvm_r15_write(vcpu, regs->r15);
11254 kvm_rip_write(vcpu, regs->rip);
11255 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
11257 vcpu->arch.exception.pending = false;
11258 vcpu->arch.exception_vmexit.pending = false;
11260 kvm_make_request(KVM_REQ_EVENT, vcpu);
11263 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11266 __set_regs(vcpu, regs);
11271 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11273 struct desc_ptr dt;
11275 if (vcpu->arch.guest_state_protected)
11276 goto skip_protected_regs;
11278 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11279 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11280 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11281 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11282 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11283 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11285 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11286 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11288 static_call(kvm_x86_get_idt)(vcpu, &dt);
11289 sregs->idt.limit = dt.size;
11290 sregs->idt.base = dt.address;
11291 static_call(kvm_x86_get_gdt)(vcpu, &dt);
11292 sregs->gdt.limit = dt.size;
11293 sregs->gdt.base = dt.address;
11295 sregs->cr2 = vcpu->arch.cr2;
11296 sregs->cr3 = kvm_read_cr3(vcpu);
11298 skip_protected_regs:
11299 sregs->cr0 = kvm_read_cr0(vcpu);
11300 sregs->cr4 = kvm_read_cr4(vcpu);
11301 sregs->cr8 = kvm_get_cr8(vcpu);
11302 sregs->efer = vcpu->arch.efer;
11303 sregs->apic_base = kvm_get_apic_base(vcpu);
11306 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11308 __get_sregs_common(vcpu, sregs);
11310 if (vcpu->arch.guest_state_protected)
11313 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
11314 set_bit(vcpu->arch.interrupt.nr,
11315 (unsigned long *)sregs->interrupt_bitmap);
11318 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11322 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
11324 if (vcpu->arch.guest_state_protected)
11327 if (is_pae_paging(vcpu)) {
11328 for (i = 0 ; i < 4 ; i++)
11329 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
11330 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
11334 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
11335 struct kvm_sregs *sregs)
11338 __get_sregs(vcpu, sregs);
11343 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
11344 struct kvm_mp_state *mp_state)
11349 if (kvm_mpx_supported())
11350 kvm_load_guest_fpu(vcpu);
11352 r = kvm_apic_accept_events(vcpu);
11357 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
11358 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
11359 vcpu->arch.pv.pv_unhalted)
11360 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
11362 mp_state->mp_state = vcpu->arch.mp_state;
11365 if (kvm_mpx_supported())
11366 kvm_put_guest_fpu(vcpu);
11371 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
11372 struct kvm_mp_state *mp_state)
11378 switch (mp_state->mp_state) {
11379 case KVM_MP_STATE_UNINITIALIZED:
11380 case KVM_MP_STATE_HALTED:
11381 case KVM_MP_STATE_AP_RESET_HOLD:
11382 case KVM_MP_STATE_INIT_RECEIVED:
11383 case KVM_MP_STATE_SIPI_RECEIVED:
11384 if (!lapic_in_kernel(vcpu))
11388 case KVM_MP_STATE_RUNNABLE:
11396 * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow
11397 * forcing the guest into INIT/SIPI if those events are supposed to be
11398 * blocked. KVM prioritizes SMI over INIT, so reject INIT/SIPI state
11399 * if an SMI is pending as well.
11401 if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) &&
11402 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
11403 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
11406 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
11407 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
11408 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
11410 vcpu->arch.mp_state = mp_state->mp_state;
11411 kvm_make_request(KVM_REQ_EVENT, vcpu);
11419 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
11420 int reason, bool has_error_code, u32 error_code)
11422 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
11425 init_emulate_ctxt(vcpu);
11427 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
11428 has_error_code, error_code);
11430 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11431 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11432 vcpu->run->internal.ndata = 0;
11436 kvm_rip_write(vcpu, ctxt->eip);
11437 kvm_set_rflags(vcpu, ctxt->eflags);
11440 EXPORT_SYMBOL_GPL(kvm_task_switch);
11442 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11444 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
11446 * When EFER.LME and CR0.PG are set, the processor is in
11447 * 64-bit mode (though maybe in a 32-bit code segment).
11448 * CR4.PAE and EFER.LMA must be set.
11450 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
11452 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
11456 * Not in 64-bit mode: EFER.LMA is clear and the code
11457 * segment cannot be 64-bit.
11459 if (sregs->efer & EFER_LMA || sregs->cs.l)
11463 return kvm_is_valid_cr4(vcpu, sregs->cr4);
11466 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
11467 int *mmu_reset_needed, bool update_pdptrs)
11469 struct msr_data apic_base_msr;
11471 struct desc_ptr dt;
11473 if (!kvm_is_valid_sregs(vcpu, sregs))
11476 apic_base_msr.data = sregs->apic_base;
11477 apic_base_msr.host_initiated = true;
11478 if (kvm_set_apic_base(vcpu, &apic_base_msr))
11481 if (vcpu->arch.guest_state_protected)
11484 dt.size = sregs->idt.limit;
11485 dt.address = sregs->idt.base;
11486 static_call(kvm_x86_set_idt)(vcpu, &dt);
11487 dt.size = sregs->gdt.limit;
11488 dt.address = sregs->gdt.base;
11489 static_call(kvm_x86_set_gdt)(vcpu, &dt);
11491 vcpu->arch.cr2 = sregs->cr2;
11492 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
11493 vcpu->arch.cr3 = sregs->cr3;
11494 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11495 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
11497 kvm_set_cr8(vcpu, sregs->cr8);
11499 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
11500 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
11502 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
11503 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
11504 vcpu->arch.cr0 = sregs->cr0;
11506 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
11507 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
11509 if (update_pdptrs) {
11510 idx = srcu_read_lock(&vcpu->kvm->srcu);
11511 if (is_pae_paging(vcpu)) {
11512 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
11513 *mmu_reset_needed = 1;
11515 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11518 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11519 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11520 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11521 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11522 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11523 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11525 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11526 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11528 update_cr8_intercept(vcpu);
11530 /* Older userspace won't unhalt the vcpu on reset. */
11531 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
11532 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
11533 !is_protmode(vcpu))
11534 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11539 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11541 int pending_vec, max_bits;
11542 int mmu_reset_needed = 0;
11543 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
11548 if (mmu_reset_needed)
11549 kvm_mmu_reset_context(vcpu);
11551 max_bits = KVM_NR_INTERRUPTS;
11552 pending_vec = find_first_bit(
11553 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
11555 if (pending_vec < max_bits) {
11556 kvm_queue_interrupt(vcpu, pending_vec, false);
11557 pr_debug("Set back pending irq %d\n", pending_vec);
11558 kvm_make_request(KVM_REQ_EVENT, vcpu);
11563 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11565 int mmu_reset_needed = 0;
11566 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
11567 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
11568 !(sregs2->efer & EFER_LMA);
11571 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11574 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11577 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11578 &mmu_reset_needed, !valid_pdptrs);
11582 if (valid_pdptrs) {
11583 for (i = 0; i < 4 ; i++)
11584 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11586 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11587 mmu_reset_needed = 1;
11588 vcpu->arch.pdptrs_from_userspace = true;
11590 if (mmu_reset_needed)
11591 kvm_mmu_reset_context(vcpu);
11595 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11596 struct kvm_sregs *sregs)
11601 ret = __set_sregs(vcpu, sregs);
11606 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11609 struct kvm_vcpu *vcpu;
11615 down_write(&kvm->arch.apicv_update_lock);
11617 kvm_for_each_vcpu(i, vcpu, kvm) {
11618 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11623 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11624 up_write(&kvm->arch.apicv_update_lock);
11627 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11628 struct kvm_guest_debug *dbg)
11630 unsigned long rflags;
11633 if (vcpu->arch.guest_state_protected)
11638 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11640 if (kvm_is_exception_pending(vcpu))
11642 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11643 kvm_queue_exception(vcpu, DB_VECTOR);
11645 kvm_queue_exception(vcpu, BP_VECTOR);
11649 * Read rflags as long as potentially injected trace flags are still
11652 rflags = kvm_get_rflags(vcpu);
11654 vcpu->guest_debug = dbg->control;
11655 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11656 vcpu->guest_debug = 0;
11658 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11659 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11660 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11661 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11663 for (i = 0; i < KVM_NR_DB_REGS; i++)
11664 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11666 kvm_update_dr7(vcpu);
11668 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11669 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11672 * Trigger an rflags update that will inject or remove the trace
11675 kvm_set_rflags(vcpu, rflags);
11677 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11679 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11689 * Translate a guest virtual address to a guest physical address.
11691 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11692 struct kvm_translation *tr)
11694 unsigned long vaddr = tr->linear_address;
11700 idx = srcu_read_lock(&vcpu->kvm->srcu);
11701 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11702 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11703 tr->physical_address = gpa;
11704 tr->valid = gpa != INVALID_GPA;
11712 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11714 struct fxregs_state *fxsave;
11716 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11721 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11722 memcpy(fpu->fpr, fxsave->st_space, 128);
11723 fpu->fcw = fxsave->cwd;
11724 fpu->fsw = fxsave->swd;
11725 fpu->ftwx = fxsave->twd;
11726 fpu->last_opcode = fxsave->fop;
11727 fpu->last_ip = fxsave->rip;
11728 fpu->last_dp = fxsave->rdp;
11729 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11735 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11737 struct fxregs_state *fxsave;
11739 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11744 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11746 memcpy(fxsave->st_space, fpu->fpr, 128);
11747 fxsave->cwd = fpu->fcw;
11748 fxsave->swd = fpu->fsw;
11749 fxsave->twd = fpu->ftwx;
11750 fxsave->fop = fpu->last_opcode;
11751 fxsave->rip = fpu->last_ip;
11752 fxsave->rdp = fpu->last_dp;
11753 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11759 static void store_regs(struct kvm_vcpu *vcpu)
11761 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11763 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11764 __get_regs(vcpu, &vcpu->run->s.regs.regs);
11766 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11767 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11769 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11770 kvm_vcpu_ioctl_x86_get_vcpu_events(
11771 vcpu, &vcpu->run->s.regs.events);
11774 static int sync_regs(struct kvm_vcpu *vcpu)
11776 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11777 __set_regs(vcpu, &vcpu->run->s.regs.regs);
11778 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11780 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11781 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
11783 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11785 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11786 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
11787 vcpu, &vcpu->run->s.regs.events))
11789 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11795 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11797 if (kvm_check_tsc_unstable() && kvm->created_vcpus)
11798 pr_warn_once("SMP vm created on host with unstable TSC; "
11799 "guest TSC will not be reliable\n");
11801 if (!kvm->arch.max_vcpu_ids)
11802 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
11804 if (id >= kvm->arch.max_vcpu_ids)
11807 return static_call(kvm_x86_vcpu_precreate)(kvm);
11810 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11815 vcpu->arch.last_vmentry_cpu = -1;
11816 vcpu->arch.regs_avail = ~0;
11817 vcpu->arch.regs_dirty = ~0;
11819 kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm, vcpu, KVM_HOST_USES_PFN);
11821 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11822 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11824 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11826 r = kvm_mmu_create(vcpu);
11830 if (irqchip_in_kernel(vcpu->kvm)) {
11831 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11833 goto fail_mmu_destroy;
11836 * Defer evaluating inhibits until the vCPU is first run, as
11837 * this vCPU will not get notified of any changes until this
11838 * vCPU is visible to other vCPUs (marked online and added to
11839 * the set of vCPUs). Opportunistically mark APICv active as
11840 * VMX in particularly is highly unlikely to have inhibits.
11841 * Ignore the current per-VM APICv state so that vCPU creation
11842 * is guaranteed to run with a deterministic value, the request
11843 * will ensure the vCPU gets the correct state before VM-Entry.
11845 if (enable_apicv) {
11846 vcpu->arch.apic->apicv_active = true;
11847 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
11850 static_branch_inc(&kvm_has_noapic_vcpu);
11854 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11856 goto fail_free_lapic;
11857 vcpu->arch.pio_data = page_address(page);
11859 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
11860 GFP_KERNEL_ACCOUNT);
11861 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
11862 GFP_KERNEL_ACCOUNT);
11863 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
11864 goto fail_free_mce_banks;
11865 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11867 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11868 GFP_KERNEL_ACCOUNT))
11869 goto fail_free_mce_banks;
11871 if (!alloc_emulate_ctxt(vcpu))
11872 goto free_wbinvd_dirty_mask;
11874 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11875 pr_err("failed to allocate vcpu's fpu\n");
11876 goto free_emulate_ctxt;
11879 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11880 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11882 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11884 kvm_async_pf_hash_reset(vcpu);
11886 vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap;
11887 kvm_pmu_init(vcpu);
11889 vcpu->arch.pending_external_vector = -1;
11890 vcpu->arch.preempted_in_kernel = false;
11892 #if IS_ENABLED(CONFIG_HYPERV)
11893 vcpu->arch.hv_root_tdp = INVALID_PAGE;
11896 r = static_call(kvm_x86_vcpu_create)(vcpu);
11898 goto free_guest_fpu;
11900 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11901 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11902 kvm_xen_init_vcpu(vcpu);
11903 kvm_vcpu_mtrr_init(vcpu);
11905 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
11906 kvm_vcpu_reset(vcpu, false);
11907 kvm_init_mmu(vcpu);
11912 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11914 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11915 free_wbinvd_dirty_mask:
11916 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11917 fail_free_mce_banks:
11918 kfree(vcpu->arch.mce_banks);
11919 kfree(vcpu->arch.mci_ctl2_banks);
11920 free_page((unsigned long)vcpu->arch.pio_data);
11922 kvm_free_lapic(vcpu);
11924 kvm_mmu_destroy(vcpu);
11928 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11930 struct kvm *kvm = vcpu->kvm;
11932 if (mutex_lock_killable(&vcpu->mutex))
11935 kvm_synchronize_tsc(vcpu, 0);
11938 /* poll control enabled by default */
11939 vcpu->arch.msr_kvm_poll_control = 1;
11941 mutex_unlock(&vcpu->mutex);
11943 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11944 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
11945 KVMCLOCK_SYNC_PERIOD);
11948 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
11952 kvmclock_reset(vcpu);
11954 static_call(kvm_x86_vcpu_free)(vcpu);
11956 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11957 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11958 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11960 kvm_xen_destroy_vcpu(vcpu);
11961 kvm_hv_vcpu_uninit(vcpu);
11962 kvm_pmu_destroy(vcpu);
11963 kfree(vcpu->arch.mce_banks);
11964 kfree(vcpu->arch.mci_ctl2_banks);
11965 kvm_free_lapic(vcpu);
11966 idx = srcu_read_lock(&vcpu->kvm->srcu);
11967 kvm_mmu_destroy(vcpu);
11968 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11969 free_page((unsigned long)vcpu->arch.pio_data);
11970 kvfree(vcpu->arch.cpuid_entries);
11971 if (!lapic_in_kernel(vcpu))
11972 static_branch_dec(&kvm_has_noapic_vcpu);
11975 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
11977 struct kvm_cpuid_entry2 *cpuid_0x1;
11978 unsigned long old_cr0 = kvm_read_cr0(vcpu);
11979 unsigned long new_cr0;
11982 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
11983 * to handle side effects. RESET emulation hits those flows and relies
11984 * on emulated/virtualized registers, including those that are loaded
11985 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
11986 * to detect improper or missing initialization.
11988 WARN_ON_ONCE(!init_event &&
11989 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
11992 * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's
11993 * possible to INIT the vCPU while L2 is active. Force the vCPU back
11994 * into L1 as EFER.SVME is cleared on INIT (along with all other EFER
11995 * bits), i.e. virtualization is disabled.
11997 if (is_guest_mode(vcpu))
11998 kvm_leave_nested(vcpu);
12000 kvm_lapic_reset(vcpu, init_event);
12002 WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu));
12003 vcpu->arch.hflags = 0;
12005 vcpu->arch.smi_pending = 0;
12006 vcpu->arch.smi_count = 0;
12007 atomic_set(&vcpu->arch.nmi_queued, 0);
12008 vcpu->arch.nmi_pending = 0;
12009 vcpu->arch.nmi_injected = false;
12010 kvm_clear_interrupt_queue(vcpu);
12011 kvm_clear_exception_queue(vcpu);
12013 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
12014 kvm_update_dr0123(vcpu);
12015 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
12016 vcpu->arch.dr7 = DR7_FIXED_1;
12017 kvm_update_dr7(vcpu);
12019 vcpu->arch.cr2 = 0;
12021 kvm_make_request(KVM_REQ_EVENT, vcpu);
12022 vcpu->arch.apf.msr_en_val = 0;
12023 vcpu->arch.apf.msr_int_val = 0;
12024 vcpu->arch.st.msr_val = 0;
12026 kvmclock_reset(vcpu);
12028 kvm_clear_async_pf_completion_queue(vcpu);
12029 kvm_async_pf_hash_reset(vcpu);
12030 vcpu->arch.apf.halted = false;
12032 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
12033 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
12036 * All paths that lead to INIT are required to load the guest's
12037 * FPU state (because most paths are buried in KVM_RUN).
12040 kvm_put_guest_fpu(vcpu);
12042 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
12043 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
12046 kvm_load_guest_fpu(vcpu);
12050 kvm_pmu_reset(vcpu);
12051 vcpu->arch.smbase = 0x30000;
12053 vcpu->arch.msr_misc_features_enables = 0;
12054 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
12055 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
12057 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
12058 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
12061 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
12062 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
12063 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
12066 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
12067 * if no CPUID match is found. Note, it's impossible to get a match at
12068 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
12069 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
12070 * on RESET. But, go through the motions in case that's ever remedied.
12072 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1);
12073 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
12075 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
12077 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
12078 kvm_rip_write(vcpu, 0xfff0);
12080 vcpu->arch.cr3 = 0;
12081 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
12084 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
12085 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
12086 * (or qualify) that with a footnote stating that CD/NW are preserved.
12088 new_cr0 = X86_CR0_ET;
12090 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
12092 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
12094 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
12095 static_call(kvm_x86_set_cr4)(vcpu, 0);
12096 static_call(kvm_x86_set_efer)(vcpu, 0);
12097 static_call(kvm_x86_update_exception_bitmap)(vcpu);
12100 * On the standard CR0/CR4/EFER modification paths, there are several
12101 * complex conditions determining whether the MMU has to be reset and/or
12102 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
12103 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
12104 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
12105 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
12107 if (old_cr0 & X86_CR0_PG) {
12108 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12109 kvm_mmu_reset_context(vcpu);
12113 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
12114 * APM states the TLBs are untouched by INIT, but it also states that
12115 * the TLBs are flushed on "External initialization of the processor."
12116 * Flush the guest TLB regardless of vendor, there is no meaningful
12117 * benefit in relying on the guest to flush the TLB immediately after
12118 * INIT. A spurious TLB flush is benign and likely negligible from a
12119 * performance perspective.
12122 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12124 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
12126 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
12128 struct kvm_segment cs;
12130 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
12131 cs.selector = vector << 8;
12132 cs.base = vector << 12;
12133 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
12134 kvm_rip_write(vcpu, 0);
12136 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
12138 int kvm_arch_hardware_enable(void)
12141 struct kvm_vcpu *vcpu;
12146 bool stable, backwards_tsc = false;
12148 kvm_user_return_msr_cpu_online();
12150 ret = kvm_x86_check_processor_compatibility();
12154 ret = static_call(kvm_x86_hardware_enable)();
12158 local_tsc = rdtsc();
12159 stable = !kvm_check_tsc_unstable();
12160 list_for_each_entry(kvm, &vm_list, vm_list) {
12161 kvm_for_each_vcpu(i, vcpu, kvm) {
12162 if (!stable && vcpu->cpu == smp_processor_id())
12163 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
12164 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
12165 backwards_tsc = true;
12166 if (vcpu->arch.last_host_tsc > max_tsc)
12167 max_tsc = vcpu->arch.last_host_tsc;
12173 * Sometimes, even reliable TSCs go backwards. This happens on
12174 * platforms that reset TSC during suspend or hibernate actions, but
12175 * maintain synchronization. We must compensate. Fortunately, we can
12176 * detect that condition here, which happens early in CPU bringup,
12177 * before any KVM threads can be running. Unfortunately, we can't
12178 * bring the TSCs fully up to date with real time, as we aren't yet far
12179 * enough into CPU bringup that we know how much real time has actually
12180 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
12181 * variables that haven't been updated yet.
12183 * So we simply find the maximum observed TSC above, then record the
12184 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
12185 * the adjustment will be applied. Note that we accumulate
12186 * adjustments, in case multiple suspend cycles happen before some VCPU
12187 * gets a chance to run again. In the event that no KVM threads get a
12188 * chance to run, we will miss the entire elapsed period, as we'll have
12189 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
12190 * loose cycle time. This isn't too big a deal, since the loss will be
12191 * uniform across all VCPUs (not to mention the scenario is extremely
12192 * unlikely). It is possible that a second hibernate recovery happens
12193 * much faster than a first, causing the observed TSC here to be
12194 * smaller; this would require additional padding adjustment, which is
12195 * why we set last_host_tsc to the local tsc observed here.
12197 * N.B. - this code below runs only on platforms with reliable TSC,
12198 * as that is the only way backwards_tsc is set above. Also note
12199 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
12200 * have the same delta_cyc adjustment applied if backwards_tsc
12201 * is detected. Note further, this adjustment is only done once,
12202 * as we reset last_host_tsc on all VCPUs to stop this from being
12203 * called multiple times (one for each physical CPU bringup).
12205 * Platforms with unreliable TSCs don't have to deal with this, they
12206 * will be compensated by the logic in vcpu_load, which sets the TSC to
12207 * catchup mode. This will catchup all VCPUs to real time, but cannot
12208 * guarantee that they stay in perfect synchronization.
12210 if (backwards_tsc) {
12211 u64 delta_cyc = max_tsc - local_tsc;
12212 list_for_each_entry(kvm, &vm_list, vm_list) {
12213 kvm->arch.backwards_tsc_observed = true;
12214 kvm_for_each_vcpu(i, vcpu, kvm) {
12215 vcpu->arch.tsc_offset_adjustment += delta_cyc;
12216 vcpu->arch.last_host_tsc = local_tsc;
12217 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
12221 * We have to disable TSC offset matching.. if you were
12222 * booting a VM while issuing an S4 host suspend....
12223 * you may have some problem. Solving this issue is
12224 * left as an exercise to the reader.
12226 kvm->arch.last_tsc_nsec = 0;
12227 kvm->arch.last_tsc_write = 0;
12234 void kvm_arch_hardware_disable(void)
12236 static_call(kvm_x86_hardware_disable)();
12237 drop_user_return_notifiers();
12240 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
12242 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
12245 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
12247 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
12250 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
12251 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
12253 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
12255 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
12257 vcpu->arch.l1tf_flush_l1d = true;
12258 if (pmu->version && unlikely(pmu->event_count)) {
12259 pmu->need_cleanup = true;
12260 kvm_make_request(KVM_REQ_PMU, vcpu);
12262 static_call(kvm_x86_sched_in)(vcpu, cpu);
12265 void kvm_arch_free_vm(struct kvm *kvm)
12267 kfree(to_kvm_hv(kvm)->hv_pa_pg);
12268 __kvm_arch_free_vm(kvm);
12272 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
12275 unsigned long flags;
12280 ret = kvm_page_track_init(kvm);
12284 ret = kvm_mmu_init_vm(kvm);
12286 goto out_page_track;
12288 ret = static_call(kvm_x86_vm_init)(kvm);
12290 goto out_uninit_mmu;
12292 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
12293 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
12294 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
12296 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
12297 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
12298 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
12299 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
12300 &kvm->arch.irq_sources_bitmap);
12302 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
12303 mutex_init(&kvm->arch.apic_map_lock);
12304 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
12305 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
12307 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
12308 pvclock_update_vm_gtod_copy(kvm);
12309 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
12311 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
12312 kvm->arch.guest_can_read_msr_platform_info = true;
12313 kvm->arch.enable_pmu = enable_pmu;
12315 #if IS_ENABLED(CONFIG_HYPERV)
12316 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
12317 kvm->arch.hv_root_tdp = INVALID_PAGE;
12320 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
12321 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
12323 kvm_apicv_init(kvm);
12324 kvm_hv_init_vm(kvm);
12325 kvm_xen_init_vm(kvm);
12330 kvm_mmu_uninit_vm(kvm);
12332 kvm_page_track_cleanup(kvm);
12337 int kvm_arch_post_init_vm(struct kvm *kvm)
12339 return kvm_mmu_post_init_vm(kvm);
12342 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
12345 kvm_mmu_unload(vcpu);
12349 static void kvm_unload_vcpu_mmus(struct kvm *kvm)
12352 struct kvm_vcpu *vcpu;
12354 kvm_for_each_vcpu(i, vcpu, kvm) {
12355 kvm_clear_async_pf_completion_queue(vcpu);
12356 kvm_unload_vcpu_mmu(vcpu);
12360 void kvm_arch_sync_events(struct kvm *kvm)
12362 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
12363 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
12368 * __x86_set_memory_region: Setup KVM internal memory slot
12370 * @kvm: the kvm pointer to the VM.
12371 * @id: the slot ID to setup.
12372 * @gpa: the GPA to install the slot (unused when @size == 0).
12373 * @size: the size of the slot. Set to zero to uninstall a slot.
12375 * This function helps to setup a KVM internal memory slot. Specify
12376 * @size > 0 to install a new slot, while @size == 0 to uninstall a
12377 * slot. The return code can be one of the following:
12379 * HVA: on success (uninstall will return a bogus HVA)
12382 * The caller should always use IS_ERR() to check the return value
12383 * before use. Note, the KVM internal memory slots are guaranteed to
12384 * remain valid and unchanged until the VM is destroyed, i.e., the
12385 * GPA->HVA translation will not change. However, the HVA is a user
12386 * address, i.e. its accessibility is not guaranteed, and must be
12387 * accessed via __copy_{to,from}_user().
12389 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
12393 unsigned long hva, old_npages;
12394 struct kvm_memslots *slots = kvm_memslots(kvm);
12395 struct kvm_memory_slot *slot;
12397 /* Called with kvm->slots_lock held. */
12398 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
12399 return ERR_PTR_USR(-EINVAL);
12401 slot = id_to_memslot(slots, id);
12403 if (slot && slot->npages)
12404 return ERR_PTR_USR(-EEXIST);
12407 * MAP_SHARED to prevent internal slot pages from being moved
12410 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
12411 MAP_SHARED | MAP_ANONYMOUS, 0);
12412 if (IS_ERR_VALUE(hva))
12413 return (void __user *)hva;
12415 if (!slot || !slot->npages)
12418 old_npages = slot->npages;
12419 hva = slot->userspace_addr;
12422 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
12423 struct kvm_userspace_memory_region m;
12425 m.slot = id | (i << 16);
12427 m.guest_phys_addr = gpa;
12428 m.userspace_addr = hva;
12429 m.memory_size = size;
12430 r = __kvm_set_memory_region(kvm, &m);
12432 return ERR_PTR_USR(r);
12436 vm_munmap(hva, old_npages * PAGE_SIZE);
12438 return (void __user *)hva;
12440 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
12442 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
12444 kvm_mmu_pre_destroy_vm(kvm);
12447 void kvm_arch_destroy_vm(struct kvm *kvm)
12449 if (current->mm == kvm->mm) {
12451 * Free memory regions allocated on behalf of userspace,
12452 * unless the memory map has changed due to process exit
12455 mutex_lock(&kvm->slots_lock);
12456 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
12458 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
12460 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
12461 mutex_unlock(&kvm->slots_lock);
12463 kvm_unload_vcpu_mmus(kvm);
12464 static_call_cond(kvm_x86_vm_destroy)(kvm);
12465 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
12466 kvm_pic_destroy(kvm);
12467 kvm_ioapic_destroy(kvm);
12468 kvm_destroy_vcpus(kvm);
12469 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
12470 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
12471 kvm_mmu_uninit_vm(kvm);
12472 kvm_page_track_cleanup(kvm);
12473 kvm_xen_destroy_vm(kvm);
12474 kvm_hv_destroy_vm(kvm);
12477 static void memslot_rmap_free(struct kvm_memory_slot *slot)
12481 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12482 kvfree(slot->arch.rmap[i]);
12483 slot->arch.rmap[i] = NULL;
12487 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
12491 memslot_rmap_free(slot);
12493 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12494 kvfree(slot->arch.lpage_info[i - 1]);
12495 slot->arch.lpage_info[i - 1] = NULL;
12498 kvm_page_track_free_memslot(slot);
12501 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
12503 const int sz = sizeof(*slot->arch.rmap[0]);
12506 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12508 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12510 if (slot->arch.rmap[i])
12513 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
12514 if (!slot->arch.rmap[i]) {
12515 memslot_rmap_free(slot);
12523 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
12524 struct kvm_memory_slot *slot)
12526 unsigned long npages = slot->npages;
12530 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
12531 * old arrays will be freed by __kvm_set_memory_region() if installing
12532 * the new memslot is successful.
12534 memset(&slot->arch, 0, sizeof(slot->arch));
12536 if (kvm_memslots_have_rmaps(kvm)) {
12537 r = memslot_rmap_alloc(slot, npages);
12542 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12543 struct kvm_lpage_info *linfo;
12544 unsigned long ugfn;
12548 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12550 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
12554 slot->arch.lpage_info[i - 1] = linfo;
12556 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12557 linfo[0].disallow_lpage = 1;
12558 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12559 linfo[lpages - 1].disallow_lpage = 1;
12560 ugfn = slot->userspace_addr >> PAGE_SHIFT;
12562 * If the gfn and userspace address are not aligned wrt each
12563 * other, disable large page support for this slot.
12565 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12568 for (j = 0; j < lpages; ++j)
12569 linfo[j].disallow_lpage = 1;
12573 if (kvm_page_track_create_memslot(kvm, slot, npages))
12579 memslot_rmap_free(slot);
12581 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12582 kvfree(slot->arch.lpage_info[i - 1]);
12583 slot->arch.lpage_info[i - 1] = NULL;
12588 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12590 struct kvm_vcpu *vcpu;
12594 * memslots->generation has been incremented.
12595 * mmio generation may have reached its maximum value.
12597 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12599 /* Force re-initialization of steal_time cache */
12600 kvm_for_each_vcpu(i, vcpu, kvm)
12601 kvm_vcpu_kick(vcpu);
12604 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12605 const struct kvm_memory_slot *old,
12606 struct kvm_memory_slot *new,
12607 enum kvm_mr_change change)
12609 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
12610 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
12613 return kvm_alloc_memslot_metadata(kvm, new);
12616 if (change == KVM_MR_FLAGS_ONLY)
12617 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12618 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12625 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12629 if (!kvm_x86_ops.cpu_dirty_log_size)
12632 nr_slots = atomic_read(&kvm->nr_memslots_dirty_logging);
12633 if ((enable && nr_slots == 1) || !nr_slots)
12634 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12637 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12638 struct kvm_memory_slot *old,
12639 const struct kvm_memory_slot *new,
12640 enum kvm_mr_change change)
12642 u32 old_flags = old ? old->flags : 0;
12643 u32 new_flags = new ? new->flags : 0;
12644 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12647 * Update CPU dirty logging if dirty logging is being toggled. This
12648 * applies to all operations.
12650 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12651 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12654 * Nothing more to do for RO slots (which can't be dirtied and can't be
12655 * made writable) or CREATE/MOVE/DELETE of a slot.
12657 * For a memslot with dirty logging disabled:
12658 * CREATE: No dirty mappings will already exist.
12659 * MOVE/DELETE: The old mappings will already have been cleaned up by
12660 * kvm_arch_flush_shadow_memslot()
12662 * For a memslot with dirty logging enabled:
12663 * CREATE: No shadow pages exist, thus nothing to write-protect
12664 * and no dirty bits to clear.
12665 * MOVE/DELETE: The old mappings will already have been cleaned up by
12666 * kvm_arch_flush_shadow_memslot().
12668 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12672 * READONLY and non-flags changes were filtered out above, and the only
12673 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12674 * logging isn't being toggled on or off.
12676 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12679 if (!log_dirty_pages) {
12681 * Dirty logging tracks sptes in 4k granularity, meaning that
12682 * large sptes have to be split. If live migration succeeds,
12683 * the guest in the source machine will be destroyed and large
12684 * sptes will be created in the destination. However, if the
12685 * guest continues to run in the source machine (for example if
12686 * live migration fails), small sptes will remain around and
12687 * cause bad performance.
12689 * Scan sptes if dirty logging has been stopped, dropping those
12690 * which can be collapsed into a single large-page spte. Later
12691 * page faults will create the large-page sptes.
12693 kvm_mmu_zap_collapsible_sptes(kvm, new);
12696 * Initially-all-set does not require write protecting any page,
12697 * because they're all assumed to be dirty.
12699 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12702 if (READ_ONCE(eager_page_split))
12703 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12705 if (kvm_x86_ops.cpu_dirty_log_size) {
12706 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12707 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12709 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12713 * Unconditionally flush the TLBs after enabling dirty logging.
12714 * A flush is almost always going to be necessary (see below),
12715 * and unconditionally flushing allows the helpers to omit
12716 * the subtly complex checks when removing write access.
12718 * Do the flush outside of mmu_lock to reduce the amount of
12719 * time mmu_lock is held. Flushing after dropping mmu_lock is
12720 * safe as KVM only needs to guarantee the slot is fully
12721 * write-protected before returning to userspace, i.e. before
12722 * userspace can consume the dirty status.
12724 * Flushing outside of mmu_lock requires KVM to be careful when
12725 * making decisions based on writable status of an SPTE, e.g. a
12726 * !writable SPTE doesn't guarantee a CPU can't perform writes.
12728 * Specifically, KVM also write-protects guest page tables to
12729 * monitor changes when using shadow paging, and must guarantee
12730 * no CPUs can write to those page before mmu_lock is dropped.
12731 * Because CPUs may have stale TLB entries at this point, a
12732 * !writable SPTE doesn't guarantee CPUs can't perform writes.
12734 * KVM also allows making SPTES writable outside of mmu_lock,
12735 * e.g. to allow dirty logging without taking mmu_lock.
12737 * To handle these scenarios, KVM uses a separate software-only
12738 * bit (MMU-writable) to track if a SPTE is !writable due to
12739 * a guest page table being write-protected (KVM clears the
12740 * MMU-writable flag when write-protecting for shadow paging).
12742 * The use of MMU-writable is also the primary motivation for
12743 * the unconditional flush. Because KVM must guarantee that a
12744 * CPU doesn't contain stale, writable TLB entries for a
12745 * !MMU-writable SPTE, KVM must flush if it encounters any
12746 * MMU-writable SPTE regardless of whether the actual hardware
12747 * writable bit was set. I.e. KVM is almost guaranteed to need
12748 * to flush, while unconditionally flushing allows the "remove
12749 * write access" helpers to ignore MMU-writable entirely.
12751 * See is_writable_pte() for more details (the case involving
12752 * access-tracked SPTEs is particularly relevant).
12754 kvm_arch_flush_remote_tlbs_memslot(kvm, new);
12758 void kvm_arch_commit_memory_region(struct kvm *kvm,
12759 struct kvm_memory_slot *old,
12760 const struct kvm_memory_slot *new,
12761 enum kvm_mr_change change)
12763 if (!kvm->arch.n_requested_mmu_pages &&
12764 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12765 unsigned long nr_mmu_pages;
12767 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12768 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12769 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12772 kvm_mmu_slot_apply_flags(kvm, old, new, change);
12774 /* Free the arrays associated with the old memslot. */
12775 if (change == KVM_MR_MOVE)
12776 kvm_arch_free_memslot(kvm, old);
12779 void kvm_arch_flush_shadow_all(struct kvm *kvm)
12781 kvm_mmu_zap_all(kvm);
12784 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
12785 struct kvm_memory_slot *slot)
12787 kvm_page_track_flush_slot(kvm, slot);
12790 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12792 return (is_guest_mode(vcpu) &&
12793 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12796 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12798 if (!list_empty_careful(&vcpu->async_pf.done))
12801 if (kvm_apic_has_pending_init_or_sipi(vcpu) &&
12802 kvm_apic_init_sipi_allowed(vcpu))
12805 if (vcpu->arch.pv.pv_unhalted)
12808 if (kvm_is_exception_pending(vcpu))
12811 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12812 (vcpu->arch.nmi_pending &&
12813 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12816 #ifdef CONFIG_KVM_SMM
12817 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12818 (vcpu->arch.smi_pending &&
12819 static_call(kvm_x86_smi_allowed)(vcpu, false)))
12823 if (kvm_arch_interrupt_allowed(vcpu) &&
12824 (kvm_cpu_has_interrupt(vcpu) ||
12825 kvm_guest_apic_has_interrupt(vcpu)))
12828 if (kvm_hv_has_stimer_pending(vcpu))
12831 if (is_guest_mode(vcpu) &&
12832 kvm_x86_ops.nested_ops->has_events &&
12833 kvm_x86_ops.nested_ops->has_events(vcpu))
12836 if (kvm_xen_has_pending_events(vcpu))
12842 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12844 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12847 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12849 if (kvm_vcpu_apicv_active(vcpu) &&
12850 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12856 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12858 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12861 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12862 #ifdef CONFIG_KVM_SMM
12863 kvm_test_request(KVM_REQ_SMI, vcpu) ||
12865 kvm_test_request(KVM_REQ_EVENT, vcpu))
12868 return kvm_arch_dy_has_pending_interrupt(vcpu);
12871 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
12873 if (vcpu->arch.guest_state_protected)
12876 return vcpu->arch.preempted_in_kernel;
12879 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
12881 return kvm_rip_read(vcpu);
12884 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
12886 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
12889 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
12891 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
12894 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
12896 /* Can't read the RIP when guest state is protected, just return 0 */
12897 if (vcpu->arch.guest_state_protected)
12900 if (is_64_bit_mode(vcpu))
12901 return kvm_rip_read(vcpu);
12902 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
12903 kvm_rip_read(vcpu));
12905 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
12907 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
12909 return kvm_get_linear_rip(vcpu) == linear_rip;
12911 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
12913 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
12915 unsigned long rflags;
12917 rflags = static_call(kvm_x86_get_rflags)(vcpu);
12918 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12919 rflags &= ~X86_EFLAGS_TF;
12922 EXPORT_SYMBOL_GPL(kvm_get_rflags);
12924 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12926 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
12927 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
12928 rflags |= X86_EFLAGS_TF;
12929 static_call(kvm_x86_set_rflags)(vcpu, rflags);
12932 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12934 __kvm_set_rflags(vcpu, rflags);
12935 kvm_make_request(KVM_REQ_EVENT, vcpu);
12937 EXPORT_SYMBOL_GPL(kvm_set_rflags);
12939 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
12941 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
12943 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
12946 static inline u32 kvm_async_pf_next_probe(u32 key)
12948 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
12951 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12953 u32 key = kvm_async_pf_hash_fn(gfn);
12955 while (vcpu->arch.apf.gfns[key] != ~0)
12956 key = kvm_async_pf_next_probe(key);
12958 vcpu->arch.apf.gfns[key] = gfn;
12961 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
12964 u32 key = kvm_async_pf_hash_fn(gfn);
12966 for (i = 0; i < ASYNC_PF_PER_VCPU &&
12967 (vcpu->arch.apf.gfns[key] != gfn &&
12968 vcpu->arch.apf.gfns[key] != ~0); i++)
12969 key = kvm_async_pf_next_probe(key);
12974 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12976 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
12979 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12983 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
12985 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
12989 vcpu->arch.apf.gfns[i] = ~0;
12991 j = kvm_async_pf_next_probe(j);
12992 if (vcpu->arch.apf.gfns[j] == ~0)
12994 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
12996 * k lies cyclically in ]i,j]
12998 * |....j i.k.| or |.k..j i...|
13000 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
13001 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
13006 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
13008 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
13010 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
13014 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
13016 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13018 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13019 &token, offset, sizeof(token));
13022 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
13024 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13027 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13028 &val, offset, sizeof(val)))
13034 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
13037 if (!kvm_pv_async_pf_enabled(vcpu))
13040 if (vcpu->arch.apf.send_user_only &&
13041 static_call(kvm_x86_get_cpl)(vcpu) == 0)
13044 if (is_guest_mode(vcpu)) {
13046 * L1 needs to opt into the special #PF vmexits that are
13047 * used to deliver async page faults.
13049 return vcpu->arch.apf.delivery_as_pf_vmexit;
13052 * Play it safe in case the guest temporarily disables paging.
13053 * The real mode IDT in particular is unlikely to have a #PF
13056 return is_paging(vcpu);
13060 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
13062 if (unlikely(!lapic_in_kernel(vcpu) ||
13063 kvm_event_needs_reinjection(vcpu) ||
13064 kvm_is_exception_pending(vcpu)))
13067 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
13071 * If interrupts are off we cannot even use an artificial
13074 return kvm_arch_interrupt_allowed(vcpu);
13077 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
13078 struct kvm_async_pf *work)
13080 struct x86_exception fault;
13082 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
13083 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
13085 if (kvm_can_deliver_async_pf(vcpu) &&
13086 !apf_put_user_notpresent(vcpu)) {
13087 fault.vector = PF_VECTOR;
13088 fault.error_code_valid = true;
13089 fault.error_code = 0;
13090 fault.nested_page_fault = false;
13091 fault.address = work->arch.token;
13092 fault.async_page_fault = true;
13093 kvm_inject_page_fault(vcpu, &fault);
13097 * It is not possible to deliver a paravirtualized asynchronous
13098 * page fault, but putting the guest in an artificial halt state
13099 * can be beneficial nevertheless: if an interrupt arrives, we
13100 * can deliver it timely and perhaps the guest will schedule
13101 * another process. When the instruction that triggered a page
13102 * fault is retried, hopefully the page will be ready in the host.
13104 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
13109 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
13110 struct kvm_async_pf *work)
13112 struct kvm_lapic_irq irq = {
13113 .delivery_mode = APIC_DM_FIXED,
13114 .vector = vcpu->arch.apf.vec
13117 if (work->wakeup_all)
13118 work->arch.token = ~0; /* broadcast wakeup */
13120 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
13121 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
13123 if ((work->wakeup_all || work->notpresent_injected) &&
13124 kvm_pv_async_pf_enabled(vcpu) &&
13125 !apf_put_user_ready(vcpu, work->arch.token)) {
13126 vcpu->arch.apf.pageready_pending = true;
13127 kvm_apic_set_irq(vcpu, &irq, NULL);
13130 vcpu->arch.apf.halted = false;
13131 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13134 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
13136 kvm_make_request(KVM_REQ_APF_READY, vcpu);
13137 if (!vcpu->arch.apf.pageready_pending)
13138 kvm_vcpu_kick(vcpu);
13141 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
13143 if (!kvm_pv_async_pf_enabled(vcpu))
13146 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
13149 void kvm_arch_start_assignment(struct kvm *kvm)
13151 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
13152 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
13154 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
13156 void kvm_arch_end_assignment(struct kvm *kvm)
13158 atomic_dec(&kvm->arch.assigned_device_count);
13160 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
13162 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm)
13164 return arch_atomic_read(&kvm->arch.assigned_device_count);
13166 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
13168 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
13170 atomic_inc(&kvm->arch.noncoherent_dma_count);
13172 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
13174 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
13176 atomic_dec(&kvm->arch.noncoherent_dma_count);
13178 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
13180 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
13182 return atomic_read(&kvm->arch.noncoherent_dma_count);
13184 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
13186 bool kvm_arch_has_irq_bypass(void)
13191 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
13192 struct irq_bypass_producer *prod)
13194 struct kvm_kernel_irqfd *irqfd =
13195 container_of(cons, struct kvm_kernel_irqfd, consumer);
13198 irqfd->producer = prod;
13199 kvm_arch_start_assignment(irqfd->kvm);
13200 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
13201 prod->irq, irqfd->gsi, 1);
13204 kvm_arch_end_assignment(irqfd->kvm);
13209 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
13210 struct irq_bypass_producer *prod)
13213 struct kvm_kernel_irqfd *irqfd =
13214 container_of(cons, struct kvm_kernel_irqfd, consumer);
13216 WARN_ON(irqfd->producer != prod);
13217 irqfd->producer = NULL;
13220 * When producer of consumer is unregistered, we change back to
13221 * remapped mode, so we can re-use the current implementation
13222 * when the irq is masked/disabled or the consumer side (KVM
13223 * int this case doesn't want to receive the interrupts.
13225 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
13227 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
13228 " fails: %d\n", irqfd->consumer.token, ret);
13230 kvm_arch_end_assignment(irqfd->kvm);
13233 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
13234 uint32_t guest_irq, bool set)
13236 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
13239 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
13240 struct kvm_kernel_irq_routing_entry *new)
13242 if (new->type != KVM_IRQ_ROUTING_MSI)
13245 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
13248 bool kvm_vector_hashing_enabled(void)
13250 return vector_hashing;
13253 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
13255 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
13257 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
13260 int kvm_spec_ctrl_test_value(u64 value)
13263 * test that setting IA32_SPEC_CTRL to given value
13264 * is allowed by the host processor
13268 unsigned long flags;
13271 local_irq_save(flags);
13273 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
13275 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
13278 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
13280 local_irq_restore(flags);
13284 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
13286 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
13288 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
13289 struct x86_exception fault;
13290 u64 access = error_code &
13291 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
13293 if (!(error_code & PFERR_PRESENT_MASK) ||
13294 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) {
13296 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
13297 * tables probably do not match the TLB. Just proceed
13298 * with the error code that the processor gave.
13300 fault.vector = PF_VECTOR;
13301 fault.error_code_valid = true;
13302 fault.error_code = error_code;
13303 fault.nested_page_fault = false;
13304 fault.address = gva;
13305 fault.async_page_fault = false;
13307 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
13309 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
13312 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
13313 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
13314 * indicates whether exit to userspace is needed.
13316 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
13317 struct x86_exception *e)
13319 if (r == X86EMUL_PROPAGATE_FAULT) {
13320 if (KVM_BUG_ON(!e, vcpu->kvm))
13323 kvm_inject_emulated_page_fault(vcpu, e);
13328 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
13329 * while handling a VMX instruction KVM could've handled the request
13330 * correctly by exiting to userspace and performing I/O but there
13331 * doesn't seem to be a real use-case behind such requests, just return
13332 * KVM_EXIT_INTERNAL_ERROR for now.
13334 kvm_prepare_emulation_failure_exit(vcpu);
13338 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
13340 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
13343 struct x86_exception e;
13350 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
13351 if (r != X86EMUL_CONTINUE)
13352 return kvm_handle_memory_failure(vcpu, r, &e);
13354 if (operand.pcid >> 12 != 0) {
13355 kvm_inject_gp(vcpu, 0);
13359 pcid_enabled = kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE);
13362 case INVPCID_TYPE_INDIV_ADDR:
13363 if ((!pcid_enabled && (operand.pcid != 0)) ||
13364 is_noncanonical_address(operand.gla, vcpu)) {
13365 kvm_inject_gp(vcpu, 0);
13368 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
13369 return kvm_skip_emulated_instruction(vcpu);
13371 case INVPCID_TYPE_SINGLE_CTXT:
13372 if (!pcid_enabled && (operand.pcid != 0)) {
13373 kvm_inject_gp(vcpu, 0);
13377 kvm_invalidate_pcid(vcpu, operand.pcid);
13378 return kvm_skip_emulated_instruction(vcpu);
13380 case INVPCID_TYPE_ALL_NON_GLOBAL:
13382 * Currently, KVM doesn't mark global entries in the shadow
13383 * page tables, so a non-global flush just degenerates to a
13384 * global flush. If needed, we could optimize this later by
13385 * keeping track of global entries in shadow page tables.
13389 case INVPCID_TYPE_ALL_INCL_GLOBAL:
13390 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
13391 return kvm_skip_emulated_instruction(vcpu);
13394 kvm_inject_gp(vcpu, 0);
13398 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
13400 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
13402 struct kvm_run *run = vcpu->run;
13403 struct kvm_mmio_fragment *frag;
13406 BUG_ON(!vcpu->mmio_needed);
13408 /* Complete previous fragment */
13409 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
13410 len = min(8u, frag->len);
13411 if (!vcpu->mmio_is_write)
13412 memcpy(frag->data, run->mmio.data, len);
13414 if (frag->len <= 8) {
13415 /* Switch to the next fragment. */
13417 vcpu->mmio_cur_fragment++;
13419 /* Go forward to the next mmio piece. */
13425 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
13426 vcpu->mmio_needed = 0;
13428 // VMG change, at this point, we're always done
13429 // RIP has already been advanced
13433 // More MMIO is needed
13434 run->mmio.phys_addr = frag->gpa;
13435 run->mmio.len = min(8u, frag->len);
13436 run->mmio.is_write = vcpu->mmio_is_write;
13437 if (run->mmio.is_write)
13438 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
13439 run->exit_reason = KVM_EXIT_MMIO;
13441 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13446 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13450 struct kvm_mmio_fragment *frag;
13455 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13456 if (handled == bytes)
13463 /*TODO: Check if need to increment number of frags */
13464 frag = vcpu->mmio_fragments;
13465 vcpu->mmio_nr_fragments = 1;
13470 vcpu->mmio_needed = 1;
13471 vcpu->mmio_cur_fragment = 0;
13473 vcpu->run->mmio.phys_addr = gpa;
13474 vcpu->run->mmio.len = min(8u, frag->len);
13475 vcpu->run->mmio.is_write = 1;
13476 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
13477 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13479 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13483 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
13485 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13489 struct kvm_mmio_fragment *frag;
13494 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13495 if (handled == bytes)
13502 /*TODO: Check if need to increment number of frags */
13503 frag = vcpu->mmio_fragments;
13504 vcpu->mmio_nr_fragments = 1;
13509 vcpu->mmio_needed = 1;
13510 vcpu->mmio_cur_fragment = 0;
13512 vcpu->run->mmio.phys_addr = gpa;
13513 vcpu->run->mmio.len = min(8u, frag->len);
13514 vcpu->run->mmio.is_write = 0;
13515 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13517 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13521 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
13523 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size)
13525 vcpu->arch.sev_pio_count -= count;
13526 vcpu->arch.sev_pio_data += count * size;
13529 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13530 unsigned int port);
13532 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
13534 int size = vcpu->arch.pio.size;
13535 int port = vcpu->arch.pio.port;
13537 vcpu->arch.pio.count = 0;
13538 if (vcpu->arch.sev_pio_count)
13539 return kvm_sev_es_outs(vcpu, size, port);
13543 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13547 unsigned int count =
13548 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13549 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
13551 /* memcpy done already by emulator_pio_out. */
13552 advance_sev_es_emulated_pio(vcpu, count, size);
13556 /* Emulation done by the kernel. */
13557 if (!vcpu->arch.sev_pio_count)
13561 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
13565 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13566 unsigned int port);
13568 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
13570 unsigned count = vcpu->arch.pio.count;
13571 int size = vcpu->arch.pio.size;
13572 int port = vcpu->arch.pio.port;
13574 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
13575 advance_sev_es_emulated_pio(vcpu, count, size);
13576 if (vcpu->arch.sev_pio_count)
13577 return kvm_sev_es_ins(vcpu, size, port);
13581 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13585 unsigned int count =
13586 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13587 if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count))
13590 /* Emulation done by the kernel. */
13591 advance_sev_es_emulated_pio(vcpu, count, size);
13592 if (!vcpu->arch.sev_pio_count)
13596 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13600 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13601 unsigned int port, void *data, unsigned int count,
13604 vcpu->arch.sev_pio_data = data;
13605 vcpu->arch.sev_pio_count = count;
13606 return in ? kvm_sev_es_ins(vcpu, size, port)
13607 : kvm_sev_es_outs(vcpu, size, port);
13609 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13611 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13612 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13613 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13614 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13615 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13616 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13617 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13618 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter);
13619 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13620 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13621 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13622 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13623 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13624 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13625 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13626 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13627 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13628 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13629 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13630 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13631 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13632 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13633 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath);
13634 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell);
13635 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13636 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13637 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13638 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13639 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13641 static int __init kvm_x86_init(void)
13643 kvm_mmu_x86_module_init();
13644 mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible();
13647 module_init(kvm_x86_init);
13649 static void __exit kvm_x86_exit(void)
13652 * If module_init() is implemented, module_exit() must also be
13653 * implemented to allow module unload.
13656 module_exit(kvm_x86_exit);