1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/kvm_host.h>
26 #include "kvm_cache_regs.h"
27 #include "kvm_emulate.h"
36 #include <linux/clocksource.h>
37 #include <linux/interrupt.h>
38 #include <linux/kvm.h>
40 #include <linux/vmalloc.h>
41 #include <linux/export.h>
42 #include <linux/moduleparam.h>
43 #include <linux/mman.h>
44 #include <linux/highmem.h>
45 #include <linux/iommu.h>
46 #include <linux/cpufreq.h>
47 #include <linux/user-return-notifier.h>
48 #include <linux/srcu.h>
49 #include <linux/slab.h>
50 #include <linux/perf_event.h>
51 #include <linux/uaccess.h>
52 #include <linux/hash.h>
53 #include <linux/pci.h>
54 #include <linux/timekeeper_internal.h>
55 #include <linux/pvclock_gtod.h>
56 #include <linux/kvm_irqfd.h>
57 #include <linux/irqbypass.h>
58 #include <linux/sched/stat.h>
59 #include <linux/sched/isolation.h>
60 #include <linux/mem_encrypt.h>
61 #include <linux/entry-kvm.h>
62 #include <linux/suspend.h>
64 #include <trace/events/kvm.h>
66 #include <asm/debugreg.h>
71 #include <linux/kernel_stat.h>
72 #include <asm/fpu/api.h>
73 #include <asm/fpu/xcr.h>
74 #include <asm/fpu/xstate.h>
75 #include <asm/pvclock.h>
76 #include <asm/div64.h>
77 #include <asm/irq_remapping.h>
78 #include <asm/mshyperv.h>
79 #include <asm/hypervisor.h>
80 #include <asm/tlbflush.h>
81 #include <asm/intel_pt.h>
82 #include <asm/emulate_prefix.h>
84 #include <clocksource/hyperv_timer.h>
86 #define CREATE_TRACE_POINTS
89 #define MAX_IO_MSRS 256
90 #define KVM_MAX_MCE_BANKS 32
92 struct kvm_caps kvm_caps __read_mostly = {
93 .supported_mce_cap = MCG_CTL_P | MCG_SER_P,
95 EXPORT_SYMBOL_GPL(kvm_caps);
97 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
99 #define emul_to_vcpu(ctxt) \
100 ((struct kvm_vcpu *)(ctxt)->vcpu)
103 * - enable syscall per default because its emulated by KVM
104 * - enable LME and LMA per default on 64 bit KVM
108 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
110 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
113 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
115 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
117 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
119 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
120 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
122 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
123 static void process_nmi(struct kvm_vcpu *vcpu);
124 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
125 static void store_regs(struct kvm_vcpu *vcpu);
126 static int sync_regs(struct kvm_vcpu *vcpu);
127 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
129 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
130 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
132 static DEFINE_MUTEX(vendor_module_lock);
133 struct kvm_x86_ops kvm_x86_ops __read_mostly;
135 #define KVM_X86_OP(func) \
136 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
137 *(((struct kvm_x86_ops *)0)->func));
138 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
139 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
140 #include <asm/kvm-x86-ops.h>
141 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
142 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
144 static bool __read_mostly ignore_msrs = 0;
145 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
147 bool __read_mostly report_ignored_msrs = true;
148 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
149 EXPORT_SYMBOL_GPL(report_ignored_msrs);
151 unsigned int min_timer_period_us = 200;
152 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
154 static bool __read_mostly kvmclock_periodic_sync = true;
155 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
157 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
158 static u32 __read_mostly tsc_tolerance_ppm = 250;
159 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
162 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
163 * adaptive tuning starting from default advancement of 1000ns. '0' disables
164 * advancement entirely. Any other value is used as-is and disables adaptive
165 * tuning, i.e. allows privileged userspace to set an exact advancement time.
167 static int __read_mostly lapic_timer_advance_ns = -1;
168 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
170 static bool __read_mostly vector_hashing = true;
171 module_param(vector_hashing, bool, S_IRUGO);
173 bool __read_mostly enable_vmware_backdoor = false;
174 module_param(enable_vmware_backdoor, bool, S_IRUGO);
175 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
178 * Flags to manipulate forced emulation behavior (any non-zero value will
179 * enable forced emulation).
181 #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1)
182 static int __read_mostly force_emulation_prefix;
183 module_param(force_emulation_prefix, int, 0644);
185 int __read_mostly pi_inject_timer = -1;
186 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
188 /* Enable/disable PMU virtualization */
189 bool __read_mostly enable_pmu = true;
190 EXPORT_SYMBOL_GPL(enable_pmu);
191 module_param(enable_pmu, bool, 0444);
193 bool __read_mostly eager_page_split = true;
194 module_param(eager_page_split, bool, 0644);
196 /* Enable/disable SMT_RSB bug mitigation */
197 static bool __read_mostly mitigate_smt_rsb;
198 module_param(mitigate_smt_rsb, bool, 0444);
201 * Restoring the host value for MSRs that are only consumed when running in
202 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
203 * returns to userspace, i.e. the kernel can run with the guest's value.
205 #define KVM_MAX_NR_USER_RETURN_MSRS 16
207 struct kvm_user_return_msrs {
208 struct user_return_notifier urn;
210 struct kvm_user_return_msr_values {
213 } values[KVM_MAX_NR_USER_RETURN_MSRS];
216 u32 __read_mostly kvm_nr_uret_msrs;
217 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
218 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
219 static struct kvm_user_return_msrs __percpu *user_return_msrs;
221 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
222 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
223 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
224 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
226 u64 __read_mostly host_efer;
227 EXPORT_SYMBOL_GPL(host_efer);
229 bool __read_mostly allow_smaller_maxphyaddr = 0;
230 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
232 bool __read_mostly enable_apicv = true;
233 EXPORT_SYMBOL_GPL(enable_apicv);
235 u64 __read_mostly host_xss;
236 EXPORT_SYMBOL_GPL(host_xss);
238 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
239 KVM_GENERIC_VM_STATS(),
240 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
241 STATS_DESC_COUNTER(VM, mmu_pte_write),
242 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
243 STATS_DESC_COUNTER(VM, mmu_flooded),
244 STATS_DESC_COUNTER(VM, mmu_recycled),
245 STATS_DESC_COUNTER(VM, mmu_cache_miss),
246 STATS_DESC_ICOUNTER(VM, mmu_unsync),
247 STATS_DESC_ICOUNTER(VM, pages_4k),
248 STATS_DESC_ICOUNTER(VM, pages_2m),
249 STATS_DESC_ICOUNTER(VM, pages_1g),
250 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
251 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
252 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
255 const struct kvm_stats_header kvm_vm_stats_header = {
256 .name_size = KVM_STATS_NAME_SIZE,
257 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
258 .id_offset = sizeof(struct kvm_stats_header),
259 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
260 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
261 sizeof(kvm_vm_stats_desc),
264 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
265 KVM_GENERIC_VCPU_STATS(),
266 STATS_DESC_COUNTER(VCPU, pf_taken),
267 STATS_DESC_COUNTER(VCPU, pf_fixed),
268 STATS_DESC_COUNTER(VCPU, pf_emulate),
269 STATS_DESC_COUNTER(VCPU, pf_spurious),
270 STATS_DESC_COUNTER(VCPU, pf_fast),
271 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created),
272 STATS_DESC_COUNTER(VCPU, pf_guest),
273 STATS_DESC_COUNTER(VCPU, tlb_flush),
274 STATS_DESC_COUNTER(VCPU, invlpg),
275 STATS_DESC_COUNTER(VCPU, exits),
276 STATS_DESC_COUNTER(VCPU, io_exits),
277 STATS_DESC_COUNTER(VCPU, mmio_exits),
278 STATS_DESC_COUNTER(VCPU, signal_exits),
279 STATS_DESC_COUNTER(VCPU, irq_window_exits),
280 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
281 STATS_DESC_COUNTER(VCPU, l1d_flush),
282 STATS_DESC_COUNTER(VCPU, halt_exits),
283 STATS_DESC_COUNTER(VCPU, request_irq_exits),
284 STATS_DESC_COUNTER(VCPU, irq_exits),
285 STATS_DESC_COUNTER(VCPU, host_state_reload),
286 STATS_DESC_COUNTER(VCPU, fpu_reload),
287 STATS_DESC_COUNTER(VCPU, insn_emulation),
288 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
289 STATS_DESC_COUNTER(VCPU, hypercalls),
290 STATS_DESC_COUNTER(VCPU, irq_injections),
291 STATS_DESC_COUNTER(VCPU, nmi_injections),
292 STATS_DESC_COUNTER(VCPU, req_event),
293 STATS_DESC_COUNTER(VCPU, nested_run),
294 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
295 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
296 STATS_DESC_COUNTER(VCPU, preemption_reported),
297 STATS_DESC_COUNTER(VCPU, preemption_other),
298 STATS_DESC_IBOOLEAN(VCPU, guest_mode),
299 STATS_DESC_COUNTER(VCPU, notify_window_exits),
302 const struct kvm_stats_header kvm_vcpu_stats_header = {
303 .name_size = KVM_STATS_NAME_SIZE,
304 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
305 .id_offset = sizeof(struct kvm_stats_header),
306 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
307 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
308 sizeof(kvm_vcpu_stats_desc),
311 u64 __read_mostly host_xcr0;
313 static struct kmem_cache *x86_emulator_cache;
316 * When called, it means the previous get/set msr reached an invalid msr.
317 * Return true if we want to ignore/silent this failed msr access.
319 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
321 const char *op = write ? "wrmsr" : "rdmsr";
324 if (report_ignored_msrs)
325 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
330 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
336 static struct kmem_cache *kvm_alloc_emulator_cache(void)
338 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
339 unsigned int size = sizeof(struct x86_emulate_ctxt);
341 return kmem_cache_create_usercopy("x86_emulator", size,
342 __alignof__(struct x86_emulate_ctxt),
343 SLAB_ACCOUNT, useroffset,
344 size - useroffset, NULL);
347 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
349 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
352 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
353 vcpu->arch.apf.gfns[i] = ~0;
356 static void kvm_on_user_return(struct user_return_notifier *urn)
359 struct kvm_user_return_msrs *msrs
360 = container_of(urn, struct kvm_user_return_msrs, urn);
361 struct kvm_user_return_msr_values *values;
365 * Disabling irqs at this point since the following code could be
366 * interrupted and executed through kvm_arch_hardware_disable()
368 local_irq_save(flags);
369 if (msrs->registered) {
370 msrs->registered = false;
371 user_return_notifier_unregister(urn);
373 local_irq_restore(flags);
374 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
375 values = &msrs->values[slot];
376 if (values->host != values->curr) {
377 wrmsrl(kvm_uret_msrs_list[slot], values->host);
378 values->curr = values->host;
383 static int kvm_probe_user_return_msr(u32 msr)
389 ret = rdmsrl_safe(msr, &val);
392 ret = wrmsrl_safe(msr, val);
398 int kvm_add_user_return_msr(u32 msr)
400 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
402 if (kvm_probe_user_return_msr(msr))
405 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
406 return kvm_nr_uret_msrs++;
408 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
410 int kvm_find_user_return_msr(u32 msr)
414 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
415 if (kvm_uret_msrs_list[i] == msr)
420 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
422 static void kvm_user_return_msr_cpu_online(void)
424 unsigned int cpu = smp_processor_id();
425 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
429 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
430 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
431 msrs->values[i].host = value;
432 msrs->values[i].curr = value;
436 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
438 unsigned int cpu = smp_processor_id();
439 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
442 value = (value & mask) | (msrs->values[slot].host & ~mask);
443 if (value == msrs->values[slot].curr)
445 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
449 msrs->values[slot].curr = value;
450 if (!msrs->registered) {
451 msrs->urn.on_user_return = kvm_on_user_return;
452 user_return_notifier_register(&msrs->urn);
453 msrs->registered = true;
457 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
459 static void drop_user_return_notifiers(void)
461 unsigned int cpu = smp_processor_id();
462 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
464 if (msrs->registered)
465 kvm_on_user_return(&msrs->urn);
468 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
470 return vcpu->arch.apic_base;
473 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
475 return kvm_apic_mode(kvm_get_apic_base(vcpu));
477 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
479 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
481 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
482 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
483 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
484 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
486 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
488 if (!msr_info->host_initiated) {
489 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
491 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
495 kvm_lapic_set_base(vcpu, msr_info->data);
496 kvm_recalculate_apic_map(vcpu->kvm);
501 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
503 * Hardware virtualization extension instructions may fault if a reboot turns
504 * off virtualization while processes are running. Usually after catching the
505 * fault we just panic; during reboot instead the instruction is ignored.
507 noinstr void kvm_spurious_fault(void)
509 /* Fault while not rebooting. We want the trace. */
510 BUG_ON(!kvm_rebooting);
512 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
514 #define EXCPT_BENIGN 0
515 #define EXCPT_CONTRIBUTORY 1
518 static int exception_class(int vector)
528 return EXCPT_CONTRIBUTORY;
535 #define EXCPT_FAULT 0
537 #define EXCPT_ABORT 2
538 #define EXCPT_INTERRUPT 3
541 static int exception_type(int vector)
545 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
546 return EXCPT_INTERRUPT;
551 * #DBs can be trap-like or fault-like, the caller must check other CPU
552 * state, e.g. DR6, to determine whether a #DB is a trap or fault.
554 if (mask & (1 << DB_VECTOR))
557 if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR)))
560 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
563 /* Reserved exceptions will result in fault */
567 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
568 struct kvm_queued_exception *ex)
570 if (!ex->has_payload)
573 switch (ex->vector) {
576 * "Certain debug exceptions may clear bit 0-3. The
577 * remaining contents of the DR6 register are never
578 * cleared by the processor".
580 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
582 * In order to reflect the #DB exception payload in guest
583 * dr6, three components need to be considered: active low
584 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
586 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
587 * In the target guest dr6:
588 * FIXED_1 bits should always be set.
589 * Active low bits should be cleared if 1-setting in payload.
590 * Active high bits should be set if 1-setting in payload.
592 * Note, the payload is compatible with the pending debug
593 * exceptions/exit qualification under VMX, that active_low bits
594 * are active high in payload.
595 * So they need to be flipped for DR6.
597 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
598 vcpu->arch.dr6 |= ex->payload;
599 vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW;
602 * The #DB payload is defined as compatible with the 'pending
603 * debug exceptions' field under VMX, not DR6. While bit 12 is
604 * defined in the 'pending debug exceptions' field (enabled
605 * breakpoint), it is reserved and must be zero in DR6.
607 vcpu->arch.dr6 &= ~BIT(12);
610 vcpu->arch.cr2 = ex->payload;
614 ex->has_payload = false;
617 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
619 static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector,
620 bool has_error_code, u32 error_code,
621 bool has_payload, unsigned long payload)
623 struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit;
626 ex->injected = false;
628 ex->has_error_code = has_error_code;
629 ex->error_code = error_code;
630 ex->has_payload = has_payload;
631 ex->payload = payload;
634 /* Forcibly leave the nested mode in cases like a vCPU reset */
635 static void kvm_leave_nested(struct kvm_vcpu *vcpu)
637 kvm_x86_ops.nested_ops->leave_nested(vcpu);
640 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
641 unsigned nr, bool has_error, u32 error_code,
642 bool has_payload, unsigned long payload, bool reinject)
647 kvm_make_request(KVM_REQ_EVENT, vcpu);
650 * If the exception is destined for L2 and isn't being reinjected,
651 * morph it to a VM-Exit if L1 wants to intercept the exception. A
652 * previously injected exception is not checked because it was checked
653 * when it was original queued, and re-checking is incorrect if _L1_
654 * injected the exception, in which case it's exempt from interception.
656 if (!reinject && is_guest_mode(vcpu) &&
657 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) {
658 kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code,
659 has_payload, payload);
663 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
667 * On VM-Entry, an exception can be pending if and only
668 * if event injection was blocked by nested_run_pending.
669 * In that case, however, vcpu_enter_guest() requests an
670 * immediate exit, and the guest shouldn't proceed far
671 * enough to need reinjection.
673 WARN_ON_ONCE(kvm_is_exception_pending(vcpu));
674 vcpu->arch.exception.injected = true;
675 if (WARN_ON_ONCE(has_payload)) {
677 * A reinjected event has already
678 * delivered its payload.
684 vcpu->arch.exception.pending = true;
685 vcpu->arch.exception.injected = false;
687 vcpu->arch.exception.has_error_code = has_error;
688 vcpu->arch.exception.vector = nr;
689 vcpu->arch.exception.error_code = error_code;
690 vcpu->arch.exception.has_payload = has_payload;
691 vcpu->arch.exception.payload = payload;
692 if (!is_guest_mode(vcpu))
693 kvm_deliver_exception_payload(vcpu,
694 &vcpu->arch.exception);
698 /* to check exception */
699 prev_nr = vcpu->arch.exception.vector;
700 if (prev_nr == DF_VECTOR) {
701 /* triple fault -> shutdown */
702 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
705 class1 = exception_class(prev_nr);
706 class2 = exception_class(nr);
707 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) ||
708 (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
710 * Synthesize #DF. Clear the previously injected or pending
711 * exception so as not to incorrectly trigger shutdown.
713 vcpu->arch.exception.injected = false;
714 vcpu->arch.exception.pending = false;
716 kvm_queue_exception_e(vcpu, DF_VECTOR, 0);
718 /* replace previous exception with a new one in a hope
719 that instruction re-execution will regenerate lost
725 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
727 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
729 EXPORT_SYMBOL_GPL(kvm_queue_exception);
731 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
733 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
735 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
737 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
738 unsigned long payload)
740 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
742 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
744 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
745 u32 error_code, unsigned long payload)
747 kvm_multiple_exception(vcpu, nr, true, error_code,
748 true, payload, false);
751 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
754 kvm_inject_gp(vcpu, 0);
756 return kvm_skip_emulated_instruction(vcpu);
760 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
762 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
765 kvm_inject_gp(vcpu, 0);
769 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
770 EMULTYPE_COMPLETE_USER_EXIT);
773 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
775 ++vcpu->stat.pf_guest;
778 * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of
779 * whether or not L1 wants to intercept "regular" #PF.
781 if (is_guest_mode(vcpu) && fault->async_page_fault)
782 kvm_queue_exception_vmexit(vcpu, PF_VECTOR,
783 true, fault->error_code,
784 true, fault->address);
786 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
790 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
791 struct x86_exception *fault)
793 struct kvm_mmu *fault_mmu;
794 WARN_ON_ONCE(fault->vector != PF_VECTOR);
796 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
800 * Invalidate the TLB entry for the faulting address, if it exists,
801 * else the access will fault indefinitely (and to emulate hardware).
803 if ((fault->error_code & PFERR_PRESENT_MASK) &&
804 !(fault->error_code & PFERR_RSVD_MASK))
805 kvm_mmu_invalidate_addr(vcpu, fault_mmu, fault->address,
806 KVM_MMU_ROOT_CURRENT);
808 fault_mmu->inject_page_fault(vcpu, fault);
810 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
812 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
814 atomic_inc(&vcpu->arch.nmi_queued);
815 kvm_make_request(KVM_REQ_NMI, vcpu);
818 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
820 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
822 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
824 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
826 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
828 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
831 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
832 * a #GP and return false.
834 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
836 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
838 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
842 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
844 if ((dr != 4 && dr != 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE))
847 kvm_queue_exception(vcpu, UD_VECTOR);
850 EXPORT_SYMBOL_GPL(kvm_require_dr);
852 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
854 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
858 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
860 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
862 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
863 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
867 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
870 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
873 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
874 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
875 if (real_gpa == INVALID_GPA)
878 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
879 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
880 cr3 & GENMASK(11, 5), sizeof(pdpte));
884 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
885 if ((pdpte[i] & PT_PRESENT_MASK) &&
886 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
892 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
893 * Shadow page roots need to be reconstructed instead.
895 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
896 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
898 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
899 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
900 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
901 vcpu->arch.pdptrs_from_userspace = false;
905 EXPORT_SYMBOL_GPL(load_pdptrs);
907 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
910 * CR0.WP is incorporated into the MMU role, but only for non-nested,
911 * indirect shadow MMUs. If paging is disabled, no updates are needed
912 * as there are no permission bits to emulate. If TDP is enabled, the
913 * MMU's metadata needs to be updated, e.g. so that emulating guest
914 * translations does the right thing, but there's no need to unload the
915 * root as CR0.WP doesn't affect SPTEs.
917 if ((cr0 ^ old_cr0) == X86_CR0_WP) {
918 if (!(cr0 & X86_CR0_PG))
927 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
928 kvm_clear_async_pf_completion_queue(vcpu);
929 kvm_async_pf_hash_reset(vcpu);
932 * Clearing CR0.PG is defined to flush the TLB from the guest's
935 if (!(cr0 & X86_CR0_PG))
936 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
939 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
940 kvm_mmu_reset_context(vcpu);
942 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
943 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
944 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
945 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
947 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
949 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
951 unsigned long old_cr0 = kvm_read_cr0(vcpu);
956 if (cr0 & 0xffffffff00000000UL)
960 cr0 &= ~CR0_RESERVED_BITS;
962 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
965 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
969 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
970 (cr0 & X86_CR0_PG)) {
975 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
980 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
981 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
982 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
985 if (!(cr0 & X86_CR0_PG) &&
986 (is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)))
989 static_call(kvm_x86_set_cr0)(vcpu, cr0);
991 kvm_post_set_cr0(vcpu, old_cr0, cr0);
995 EXPORT_SYMBOL_GPL(kvm_set_cr0);
997 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
999 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
1001 EXPORT_SYMBOL_GPL(kvm_lmsw);
1003 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
1005 if (vcpu->arch.guest_state_protected)
1008 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1010 if (vcpu->arch.xcr0 != host_xcr0)
1011 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
1013 if (vcpu->arch.xsaves_enabled &&
1014 vcpu->arch.ia32_xss != host_xss)
1015 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
1018 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
1019 if (static_cpu_has(X86_FEATURE_PKU) &&
1020 vcpu->arch.pkru != vcpu->arch.host_pkru &&
1021 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1022 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)))
1023 write_pkru(vcpu->arch.pkru);
1024 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
1026 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
1028 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
1030 if (vcpu->arch.guest_state_protected)
1033 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
1034 if (static_cpu_has(X86_FEATURE_PKU) &&
1035 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1036 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) {
1037 vcpu->arch.pkru = rdpkru();
1038 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
1039 write_pkru(vcpu->arch.host_pkru);
1041 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
1043 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1045 if (vcpu->arch.xcr0 != host_xcr0)
1046 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
1048 if (vcpu->arch.xsaves_enabled &&
1049 vcpu->arch.ia32_xss != host_xss)
1050 wrmsrl(MSR_IA32_XSS, host_xss);
1054 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1056 #ifdef CONFIG_X86_64
1057 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1059 return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC;
1063 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1066 u64 old_xcr0 = vcpu->arch.xcr0;
1069 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1070 if (index != XCR_XFEATURE_ENABLED_MASK)
1072 if (!(xcr0 & XFEATURE_MASK_FP))
1074 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1078 * Do not allow the guest to set bits that we do not support
1079 * saving. However, xcr0 bit 0 is always set, even if the
1080 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1082 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
1083 if (xcr0 & ~valid_bits)
1086 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1087 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1090 if (xcr0 & XFEATURE_MASK_AVX512) {
1091 if (!(xcr0 & XFEATURE_MASK_YMM))
1093 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1097 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1098 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1101 vcpu->arch.xcr0 = xcr0;
1103 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1104 kvm_update_cpuid_runtime(vcpu);
1108 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1110 /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
1111 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1112 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1113 kvm_inject_gp(vcpu, 0);
1117 return kvm_skip_emulated_instruction(vcpu);
1119 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1121 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1123 if (cr4 & cr4_reserved_bits)
1126 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1131 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4);
1133 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1135 return __kvm_is_valid_cr4(vcpu, cr4) &&
1136 static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1139 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1141 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1142 kvm_mmu_reset_context(vcpu);
1145 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1146 * according to the SDM; however, stale prev_roots could be reused
1147 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1148 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1149 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1153 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1154 kvm_mmu_unload(vcpu);
1157 * The TLB has to be flushed for all PCIDs if any of the following
1158 * (architecturally required) changes happen:
1159 * - CR4.PCIDE is changed from 1 to 0
1160 * - CR4.PGE is toggled
1162 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1164 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1165 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1166 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1169 * The TLB has to be flushed for the current PCID if any of the
1170 * following (architecturally required) changes happen:
1171 * - CR4.SMEP is changed from 0 to 1
1172 * - CR4.PAE is toggled
1174 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1175 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1176 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1179 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1181 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1183 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1185 if (!kvm_is_valid_cr4(vcpu, cr4))
1188 if (is_long_mode(vcpu)) {
1189 if (!(cr4 & X86_CR4_PAE))
1191 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1193 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1194 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1195 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1198 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1199 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1200 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1204 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1206 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1210 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1212 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1214 struct kvm_mmu *mmu = vcpu->arch.mmu;
1215 unsigned long roots_to_free = 0;
1219 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1220 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1221 * also via the emulator. KVM's TDP page tables are not in the scope of
1222 * the invalidation, but the guest's TLB entries need to be flushed as
1223 * the CPU may have cached entries in its TLB for the target PCID.
1225 if (unlikely(tdp_enabled)) {
1226 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1231 * If neither the current CR3 nor any of the prev_roots use the given
1232 * PCID, then nothing needs to be done here because a resync will
1233 * happen anyway before switching to any other CR3.
1235 if (kvm_get_active_pcid(vcpu) == pcid) {
1236 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1237 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1241 * If PCID is disabled, there is no need to free prev_roots even if the
1242 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1245 if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))
1248 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1249 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1250 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1252 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1255 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1257 bool skip_tlb_flush = false;
1258 unsigned long pcid = 0;
1259 #ifdef CONFIG_X86_64
1260 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) {
1261 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1262 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1263 pcid = cr3 & X86_CR3_PCID_MASK;
1267 /* PDPTRs are always reloaded for PAE paging. */
1268 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1269 goto handle_tlb_flush;
1272 * Do not condition the GPA check on long mode, this helper is used to
1273 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1274 * the current vCPU mode is accurate.
1276 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1279 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1282 if (cr3 != kvm_read_cr3(vcpu))
1283 kvm_mmu_new_pgd(vcpu, cr3);
1285 vcpu->arch.cr3 = cr3;
1286 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1287 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1291 * A load of CR3 that flushes the TLB flushes only the current PCID,
1292 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1293 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1294 * and it's impossible to use a non-zero PCID when PCID is disabled,
1295 * i.e. only PCID=0 can be relevant.
1297 if (!skip_tlb_flush)
1298 kvm_invalidate_pcid(vcpu, pcid);
1302 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1304 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1306 if (cr8 & CR8_RESERVED_BITS)
1308 if (lapic_in_kernel(vcpu))
1309 kvm_lapic_set_tpr(vcpu, cr8);
1311 vcpu->arch.cr8 = cr8;
1314 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1316 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1318 if (lapic_in_kernel(vcpu))
1319 return kvm_lapic_get_cr8(vcpu);
1321 return vcpu->arch.cr8;
1323 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1325 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1329 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1330 for (i = 0; i < KVM_NR_DB_REGS; i++)
1331 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1335 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1339 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1340 dr7 = vcpu->arch.guest_debug_dr7;
1342 dr7 = vcpu->arch.dr7;
1343 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1344 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1345 if (dr7 & DR7_BP_EN_MASK)
1346 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1348 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1350 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1352 u64 fixed = DR6_FIXED_1;
1354 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1357 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1358 fixed |= DR6_BUS_LOCK;
1362 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1364 size_t size = ARRAY_SIZE(vcpu->arch.db);
1368 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1369 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1370 vcpu->arch.eff_db[dr] = val;
1374 if (!kvm_dr6_valid(val))
1376 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1380 if (!kvm_dr7_valid(val))
1382 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1383 kvm_update_dr7(vcpu);
1389 EXPORT_SYMBOL_GPL(kvm_set_dr);
1391 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1393 size_t size = ARRAY_SIZE(vcpu->arch.db);
1397 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1401 *val = vcpu->arch.dr6;
1405 *val = vcpu->arch.dr7;
1409 EXPORT_SYMBOL_GPL(kvm_get_dr);
1411 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1413 u32 ecx = kvm_rcx_read(vcpu);
1416 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1417 kvm_inject_gp(vcpu, 0);
1421 kvm_rax_write(vcpu, (u32)data);
1422 kvm_rdx_write(vcpu, data >> 32);
1423 return kvm_skip_emulated_instruction(vcpu);
1425 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1428 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1429 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1431 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1432 * extract the supported MSRs from the related const lists.
1433 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1434 * capabilities of the host cpu. This capabilities test skips MSRs that are
1435 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1436 * may depend on host virtualization features rather than host cpu features.
1439 static const u32 msrs_to_save_base[] = {
1440 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1442 #ifdef CONFIG_X86_64
1443 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1445 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1446 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1448 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1449 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1450 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1451 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1452 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1453 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1454 MSR_IA32_UMWAIT_CONTROL,
1456 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1459 static const u32 msrs_to_save_pmu[] = {
1460 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1461 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1462 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1463 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1464 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1466 /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
1467 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1468 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1469 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1470 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1471 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1472 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1473 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1474 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1476 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1477 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1479 /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
1480 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1481 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1482 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1483 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1486 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) +
1487 ARRAY_SIZE(msrs_to_save_pmu)];
1488 static unsigned num_msrs_to_save;
1490 static const u32 emulated_msrs_all[] = {
1491 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1492 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1493 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1494 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1495 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1496 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1497 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1499 HV_X64_MSR_VP_INDEX,
1500 HV_X64_MSR_VP_RUNTIME,
1501 HV_X64_MSR_SCONTROL,
1502 HV_X64_MSR_STIMER0_CONFIG,
1503 HV_X64_MSR_VP_ASSIST_PAGE,
1504 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1505 HV_X64_MSR_TSC_EMULATION_STATUS, HV_X64_MSR_TSC_INVARIANT_CONTROL,
1506 HV_X64_MSR_SYNDBG_OPTIONS,
1507 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1508 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1509 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1511 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1512 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1514 MSR_IA32_TSC_ADJUST,
1515 MSR_IA32_TSC_DEADLINE,
1516 MSR_IA32_ARCH_CAPABILITIES,
1517 MSR_IA32_PERF_CAPABILITIES,
1518 MSR_IA32_MISC_ENABLE,
1519 MSR_IA32_MCG_STATUS,
1521 MSR_IA32_MCG_EXT_CTL,
1525 MSR_MISC_FEATURES_ENABLES,
1526 MSR_AMD64_VIRT_SPEC_CTRL,
1527 MSR_AMD64_TSC_RATIO,
1532 * The following list leaves out MSRs whose values are determined
1533 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1534 * We always support the "true" VMX control MSRs, even if the host
1535 * processor does not, so I am putting these registers here rather
1536 * than in msrs_to_save_all.
1539 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1540 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1541 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1542 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1544 MSR_IA32_VMX_CR0_FIXED0,
1545 MSR_IA32_VMX_CR4_FIXED0,
1546 MSR_IA32_VMX_VMCS_ENUM,
1547 MSR_IA32_VMX_PROCBASED_CTLS2,
1548 MSR_IA32_VMX_EPT_VPID_CAP,
1549 MSR_IA32_VMX_VMFUNC,
1552 MSR_KVM_POLL_CONTROL,
1555 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1556 static unsigned num_emulated_msrs;
1559 * List of msr numbers which are used to expose MSR-based features that
1560 * can be used by a hypervisor to validate requested CPU features.
1562 static const u32 msr_based_features_all[] = {
1564 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1565 MSR_IA32_VMX_PINBASED_CTLS,
1566 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1567 MSR_IA32_VMX_PROCBASED_CTLS,
1568 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1569 MSR_IA32_VMX_EXIT_CTLS,
1570 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1571 MSR_IA32_VMX_ENTRY_CTLS,
1573 MSR_IA32_VMX_CR0_FIXED0,
1574 MSR_IA32_VMX_CR0_FIXED1,
1575 MSR_IA32_VMX_CR4_FIXED0,
1576 MSR_IA32_VMX_CR4_FIXED1,
1577 MSR_IA32_VMX_VMCS_ENUM,
1578 MSR_IA32_VMX_PROCBASED_CTLS2,
1579 MSR_IA32_VMX_EPT_VPID_CAP,
1580 MSR_IA32_VMX_VMFUNC,
1584 MSR_IA32_ARCH_CAPABILITIES,
1585 MSR_IA32_PERF_CAPABILITIES,
1588 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1589 static unsigned int num_msr_based_features;
1592 * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM
1593 * does not yet virtualize. These include:
1594 * 10 - MISC_PACKAGE_CTRLS
1595 * 11 - ENERGY_FILTERING_CTL
1597 * 18 - FB_CLEAR_CTRL
1598 * 21 - XAPIC_DISABLE_STATUS
1599 * 23 - OVERCLOCKING_STATUS
1602 #define KVM_SUPPORTED_ARCH_CAP \
1603 (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \
1604 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \
1605 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \
1606 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \
1607 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO)
1609 static u64 kvm_get_arch_capabilities(void)
1613 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
1614 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1615 data &= KVM_SUPPORTED_ARCH_CAP;
1619 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1620 * the nested hypervisor runs with NX huge pages. If it is not,
1621 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1622 * L1 guests, so it need not worry about its own (L2) guests.
1624 data |= ARCH_CAP_PSCHANGE_MC_NO;
1627 * If we're doing cache flushes (either "always" or "cond")
1628 * we will do one whenever the guest does a vmlaunch/vmresume.
1629 * If an outer hypervisor is doing the cache flush for us
1630 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1631 * capability to the guest too, and if EPT is disabled we're not
1632 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1633 * require a nested hypervisor to do a flush of its own.
1635 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1636 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1638 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1639 data |= ARCH_CAP_RDCL_NO;
1640 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1641 data |= ARCH_CAP_SSB_NO;
1642 if (!boot_cpu_has_bug(X86_BUG_MDS))
1643 data |= ARCH_CAP_MDS_NO;
1645 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1647 * If RTM=0 because the kernel has disabled TSX, the host might
1648 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1649 * and therefore knows that there cannot be TAA) but keep
1650 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1651 * and we want to allow migrating those guests to tsx=off hosts.
1653 data &= ~ARCH_CAP_TAA_NO;
1654 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1655 data |= ARCH_CAP_TAA_NO;
1658 * Nothing to do here; we emulate TSX_CTRL if present on the
1659 * host so the guest can choose between disabling TSX or
1660 * using VERW to clear CPU buffers.
1667 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1669 switch (msr->index) {
1670 case MSR_IA32_ARCH_CAPABILITIES:
1671 msr->data = kvm_get_arch_capabilities();
1673 case MSR_IA32_PERF_CAPABILITIES:
1674 msr->data = kvm_caps.supported_perf_cap;
1676 case MSR_IA32_UCODE_REV:
1677 rdmsrl_safe(msr->index, &msr->data);
1680 return static_call(kvm_x86_get_msr_feature)(msr);
1685 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1687 struct kvm_msr_entry msr;
1691 r = kvm_get_msr_feature(&msr);
1693 if (r == KVM_MSR_RET_INVALID) {
1694 /* Unconditionally clear the output for simplicity */
1696 if (kvm_msr_ignored_check(index, 0, false))
1708 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1710 if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS))
1713 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1716 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1719 if (efer & (EFER_LME | EFER_LMA) &&
1720 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1723 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1729 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1731 if (efer & efer_reserved_bits)
1734 return __kvm_valid_efer(vcpu, efer);
1736 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1738 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1740 u64 old_efer = vcpu->arch.efer;
1741 u64 efer = msr_info->data;
1744 if (efer & efer_reserved_bits)
1747 if (!msr_info->host_initiated) {
1748 if (!__kvm_valid_efer(vcpu, efer))
1751 if (is_paging(vcpu) &&
1752 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1757 efer |= vcpu->arch.efer & EFER_LMA;
1759 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1765 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1766 kvm_mmu_reset_context(vcpu);
1771 void kvm_enable_efer_bits(u64 mask)
1773 efer_reserved_bits &= ~mask;
1775 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1777 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1779 struct kvm_x86_msr_filter *msr_filter;
1780 struct msr_bitmap_range *ranges;
1781 struct kvm *kvm = vcpu->kvm;
1786 /* x2APIC MSRs do not support filtering. */
1787 if (index >= 0x800 && index <= 0x8ff)
1790 idx = srcu_read_lock(&kvm->srcu);
1792 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1798 allowed = msr_filter->default_allow;
1799 ranges = msr_filter->ranges;
1801 for (i = 0; i < msr_filter->count; i++) {
1802 u32 start = ranges[i].base;
1803 u32 end = start + ranges[i].nmsrs;
1804 u32 flags = ranges[i].flags;
1805 unsigned long *bitmap = ranges[i].bitmap;
1807 if ((index >= start) && (index < end) && (flags & type)) {
1808 allowed = !!test_bit(index - start, bitmap);
1814 srcu_read_unlock(&kvm->srcu, idx);
1818 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1821 * Write @data into the MSR specified by @index. Select MSR specific fault
1822 * checks are bypassed if @host_initiated is %true.
1823 * Returns 0 on success, non-0 otherwise.
1824 * Assumes vcpu_load() was already called.
1826 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1827 bool host_initiated)
1829 struct msr_data msr;
1834 case MSR_KERNEL_GS_BASE:
1837 if (is_noncanonical_address(data, vcpu))
1840 case MSR_IA32_SYSENTER_EIP:
1841 case MSR_IA32_SYSENTER_ESP:
1843 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1844 * non-canonical address is written on Intel but not on
1845 * AMD (which ignores the top 32-bits, because it does
1846 * not implement 64-bit SYSENTER).
1848 * 64-bit code should hence be able to write a non-canonical
1849 * value on AMD. Making the address canonical ensures that
1850 * vmentry does not fail on Intel after writing a non-canonical
1851 * value, and that something deterministic happens if the guest
1852 * invokes 64-bit SYSENTER.
1854 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1857 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1860 if (!host_initiated &&
1861 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1862 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1866 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1867 * incomplete and conflicting architectural behavior. Current
1868 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1869 * reserved and always read as zeros. Enforce Intel's reserved
1870 * bits check if and only if the guest CPU is Intel, and clear
1871 * the bits in all other cases. This ensures cross-vendor
1872 * migration will provide consistent behavior for the guest.
1874 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1883 msr.host_initiated = host_initiated;
1885 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1888 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1889 u32 index, u64 data, bool host_initiated)
1891 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1893 if (ret == KVM_MSR_RET_INVALID)
1894 if (kvm_msr_ignored_check(index, data, true))
1901 * Read the MSR specified by @index into @data. Select MSR specific fault
1902 * checks are bypassed if @host_initiated is %true.
1903 * Returns 0 on success, non-0 otherwise.
1904 * Assumes vcpu_load() was already called.
1906 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1907 bool host_initiated)
1909 struct msr_data msr;
1914 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1917 if (!host_initiated &&
1918 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1919 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1925 msr.host_initiated = host_initiated;
1927 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1933 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1934 u32 index, u64 *data, bool host_initiated)
1936 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1938 if (ret == KVM_MSR_RET_INVALID) {
1939 /* Unconditionally clear *data for simplicity */
1941 if (kvm_msr_ignored_check(index, 0, false))
1948 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1950 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1951 return KVM_MSR_RET_FILTERED;
1952 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1955 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1957 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1958 return KVM_MSR_RET_FILTERED;
1959 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1962 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1964 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1966 EXPORT_SYMBOL_GPL(kvm_get_msr);
1968 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1970 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1972 EXPORT_SYMBOL_GPL(kvm_set_msr);
1974 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1976 if (!vcpu->run->msr.error) {
1977 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1978 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1982 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1984 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
1987 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1989 complete_userspace_rdmsr(vcpu);
1990 return complete_emulated_msr_access(vcpu);
1993 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
1995 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
1998 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
2000 complete_userspace_rdmsr(vcpu);
2001 return complete_fast_msr_access(vcpu);
2004 static u64 kvm_msr_reason(int r)
2007 case KVM_MSR_RET_INVALID:
2008 return KVM_MSR_EXIT_REASON_UNKNOWN;
2009 case KVM_MSR_RET_FILTERED:
2010 return KVM_MSR_EXIT_REASON_FILTER;
2012 return KVM_MSR_EXIT_REASON_INVAL;
2016 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
2017 u32 exit_reason, u64 data,
2018 int (*completion)(struct kvm_vcpu *vcpu),
2021 u64 msr_reason = kvm_msr_reason(r);
2023 /* Check if the user wanted to know about this MSR fault */
2024 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
2027 vcpu->run->exit_reason = exit_reason;
2028 vcpu->run->msr.error = 0;
2029 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
2030 vcpu->run->msr.reason = msr_reason;
2031 vcpu->run->msr.index = index;
2032 vcpu->run->msr.data = data;
2033 vcpu->arch.complete_userspace_io = completion;
2038 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
2040 u32 ecx = kvm_rcx_read(vcpu);
2044 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
2047 trace_kvm_msr_read(ecx, data);
2049 kvm_rax_write(vcpu, data & -1u);
2050 kvm_rdx_write(vcpu, (data >> 32) & -1u);
2052 /* MSR read failed? See if we should ask user space */
2053 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
2054 complete_fast_rdmsr, r))
2056 trace_kvm_msr_read_ex(ecx);
2059 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2061 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
2063 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
2065 u32 ecx = kvm_rcx_read(vcpu);
2066 u64 data = kvm_read_edx_eax(vcpu);
2069 r = kvm_set_msr_with_filter(vcpu, ecx, data);
2072 trace_kvm_msr_write(ecx, data);
2074 /* MSR write failed? See if we should ask user space */
2075 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2076 complete_fast_msr_access, r))
2078 /* Signal all other negative errors to userspace */
2081 trace_kvm_msr_write_ex(ecx, data);
2084 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2086 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2088 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2090 return kvm_skip_emulated_instruction(vcpu);
2093 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2095 /* Treat an INVD instruction as a NOP and just skip it. */
2096 return kvm_emulate_as_nop(vcpu);
2098 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2100 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2102 kvm_queue_exception(vcpu, UD_VECTOR);
2105 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2108 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
2110 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) &&
2111 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT))
2112 return kvm_handle_invalid_op(vcpu);
2114 pr_warn_once("%s instruction emulated as NOP!\n", insn);
2115 return kvm_emulate_as_nop(vcpu);
2117 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2119 return kvm_emulate_monitor_mwait(vcpu, "MWAIT");
2121 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2123 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2125 return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
2127 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2129 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2131 xfer_to_guest_mode_prepare();
2132 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2133 xfer_to_guest_mode_work_pending();
2137 * The fast path for frequent and performance sensitive wrmsr emulation,
2138 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2139 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2140 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2141 * other cases which must be called after interrupts are enabled on the host.
2143 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2145 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2148 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2149 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2150 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2151 ((u32)(data >> 32) != X2APIC_BROADCAST))
2152 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2157 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2159 if (!kvm_can_use_hv_timer(vcpu))
2162 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2166 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2168 u32 msr = kvm_rcx_read(vcpu);
2170 fastpath_t ret = EXIT_FASTPATH_NONE;
2173 case APIC_BASE_MSR + (APIC_ICR >> 4):
2174 data = kvm_read_edx_eax(vcpu);
2175 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2176 kvm_skip_emulated_instruction(vcpu);
2177 ret = EXIT_FASTPATH_EXIT_HANDLED;
2180 case MSR_IA32_TSC_DEADLINE:
2181 data = kvm_read_edx_eax(vcpu);
2182 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2183 kvm_skip_emulated_instruction(vcpu);
2184 ret = EXIT_FASTPATH_REENTER_GUEST;
2191 if (ret != EXIT_FASTPATH_NONE)
2192 trace_kvm_msr_write(msr, data);
2196 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2199 * Adapt set_msr() to msr_io()'s calling convention
2201 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2203 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2206 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2208 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2211 #ifdef CONFIG_X86_64
2212 struct pvclock_clock {
2222 struct pvclock_gtod_data {
2225 struct pvclock_clock clock; /* extract of a clocksource struct */
2226 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2232 static struct pvclock_gtod_data pvclock_gtod_data;
2234 static void update_pvclock_gtod(struct timekeeper *tk)
2236 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2238 write_seqcount_begin(&vdata->seq);
2240 /* copy pvclock gtod data */
2241 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2242 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2243 vdata->clock.mask = tk->tkr_mono.mask;
2244 vdata->clock.mult = tk->tkr_mono.mult;
2245 vdata->clock.shift = tk->tkr_mono.shift;
2246 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2247 vdata->clock.offset = tk->tkr_mono.base;
2249 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2250 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2251 vdata->raw_clock.mask = tk->tkr_raw.mask;
2252 vdata->raw_clock.mult = tk->tkr_raw.mult;
2253 vdata->raw_clock.shift = tk->tkr_raw.shift;
2254 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2255 vdata->raw_clock.offset = tk->tkr_raw.base;
2257 vdata->wall_time_sec = tk->xtime_sec;
2259 vdata->offs_boot = tk->offs_boot;
2261 write_seqcount_end(&vdata->seq);
2264 static s64 get_kvmclock_base_ns(void)
2266 /* Count up from boot time, but with the frequency of the raw clock. */
2267 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2270 static s64 get_kvmclock_base_ns(void)
2272 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2273 return ktime_get_boottime_ns();
2277 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2281 struct pvclock_wall_clock wc;
2288 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2293 ++version; /* first time write, random junk */
2297 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2301 * The guest calculates current wall clock time by adding
2302 * system time (updated by kvm_guest_time_update below) to the
2303 * wall clock specified here. We do the reverse here.
2305 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2307 wc.nsec = do_div(wall_nsec, 1000000000);
2308 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2309 wc.version = version;
2311 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2314 wc_sec_hi = wall_nsec >> 32;
2315 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2316 &wc_sec_hi, sizeof(wc_sec_hi));
2320 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2323 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2324 bool old_msr, bool host_initiated)
2326 struct kvm_arch *ka = &vcpu->kvm->arch;
2328 if (vcpu->vcpu_id == 0 && !host_initiated) {
2329 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2330 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2332 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2335 vcpu->arch.time = system_time;
2336 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2338 /* we verify if the enable bit is set... */
2339 if (system_time & 1)
2340 kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL,
2341 sizeof(struct pvclock_vcpu_time_info));
2343 kvm_gpc_deactivate(&vcpu->arch.pv_time);
2348 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2350 do_shl32_div32(dividend, divisor);
2354 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2355 s8 *pshift, u32 *pmultiplier)
2363 scaled64 = scaled_hz;
2364 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2369 tps32 = (uint32_t)tps64;
2370 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2371 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2379 *pmultiplier = div_frac(scaled64, tps32);
2382 #ifdef CONFIG_X86_64
2383 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2386 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2387 static unsigned long max_tsc_khz;
2389 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2391 u64 v = (u64)khz * (1000000 + ppm);
2396 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2398 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2402 /* Guest TSC same frequency as host TSC? */
2404 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2408 /* TSC scaling supported? */
2409 if (!kvm_caps.has_tsc_control) {
2410 if (user_tsc_khz > tsc_khz) {
2411 vcpu->arch.tsc_catchup = 1;
2412 vcpu->arch.tsc_always_catchup = 1;
2415 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2420 /* TSC scaling required - calculate ratio */
2421 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
2422 user_tsc_khz, tsc_khz);
2424 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
2425 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2430 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2434 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2436 u32 thresh_lo, thresh_hi;
2437 int use_scaling = 0;
2439 /* tsc_khz can be zero if TSC calibration fails */
2440 if (user_tsc_khz == 0) {
2441 /* set tsc_scaling_ratio to a safe value */
2442 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2446 /* Compute a scale to convert nanoseconds in TSC cycles */
2447 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2448 &vcpu->arch.virtual_tsc_shift,
2449 &vcpu->arch.virtual_tsc_mult);
2450 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2453 * Compute the variation in TSC rate which is acceptable
2454 * within the range of tolerance and decide if the
2455 * rate being applied is within that bounds of the hardware
2456 * rate. If so, no scaling or compensation need be done.
2458 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2459 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2460 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2461 pr_debug("requested TSC rate %u falls outside tolerance [%u,%u]\n",
2462 user_tsc_khz, thresh_lo, thresh_hi);
2465 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2468 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2470 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2471 vcpu->arch.virtual_tsc_mult,
2472 vcpu->arch.virtual_tsc_shift);
2473 tsc += vcpu->arch.this_tsc_write;
2477 #ifdef CONFIG_X86_64
2478 static inline int gtod_is_based_on_tsc(int mode)
2480 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2484 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2486 #ifdef CONFIG_X86_64
2488 struct kvm_arch *ka = &vcpu->kvm->arch;
2489 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2491 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2492 atomic_read(&vcpu->kvm->online_vcpus));
2495 * Once the masterclock is enabled, always perform request in
2496 * order to update it.
2498 * In order to enable masterclock, the host clocksource must be TSC
2499 * and the vcpus need to have matched TSCs. When that happens,
2500 * perform request to enable masterclock.
2502 if (ka->use_master_clock ||
2503 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2504 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2506 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2507 atomic_read(&vcpu->kvm->online_vcpus),
2508 ka->use_master_clock, gtod->clock.vclock_mode);
2513 * Multiply tsc by a fixed point number represented by ratio.
2515 * The most significant 64-N bits (mult) of ratio represent the
2516 * integral part of the fixed point number; the remaining N bits
2517 * (frac) represent the fractional part, ie. ratio represents a fixed
2518 * point number (mult + frac * 2^(-N)).
2520 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
2522 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2524 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
2527 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2531 if (ratio != kvm_caps.default_tsc_scaling_ratio)
2532 _tsc = __scale_tsc(ratio, tsc);
2537 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2541 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2543 return target_tsc - tsc;
2546 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2548 return vcpu->arch.l1_tsc_offset +
2549 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2551 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2553 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2557 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
2558 nested_offset = l1_offset;
2560 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2561 kvm_caps.tsc_scaling_ratio_frac_bits);
2563 nested_offset += l2_offset;
2564 return nested_offset;
2566 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2568 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2570 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
2571 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2572 kvm_caps.tsc_scaling_ratio_frac_bits);
2574 return l1_multiplier;
2576 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2578 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2580 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2581 vcpu->arch.l1_tsc_offset,
2584 vcpu->arch.l1_tsc_offset = l1_offset;
2587 * If we are here because L1 chose not to trap WRMSR to TSC then
2588 * according to the spec this should set L1's TSC (as opposed to
2589 * setting L1's offset for L2).
2591 if (is_guest_mode(vcpu))
2592 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2594 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2595 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2597 vcpu->arch.tsc_offset = l1_offset;
2599 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset);
2602 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2604 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2606 /* Userspace is changing the multiplier while L2 is active */
2607 if (is_guest_mode(vcpu))
2608 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2610 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2612 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2614 if (kvm_caps.has_tsc_control)
2615 static_call(kvm_x86_write_tsc_multiplier)(
2616 vcpu, vcpu->arch.tsc_scaling_ratio);
2619 static inline bool kvm_check_tsc_unstable(void)
2621 #ifdef CONFIG_X86_64
2623 * TSC is marked unstable when we're running on Hyper-V,
2624 * 'TSC page' clocksource is good.
2626 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2629 return check_tsc_unstable();
2633 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2634 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2637 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2638 u64 ns, bool matched)
2640 struct kvm *kvm = vcpu->kvm;
2642 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2645 * We also track th most recent recorded KHZ, write and time to
2646 * allow the matching interval to be extended at each write.
2648 kvm->arch.last_tsc_nsec = ns;
2649 kvm->arch.last_tsc_write = tsc;
2650 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2651 kvm->arch.last_tsc_offset = offset;
2653 vcpu->arch.last_guest_tsc = tsc;
2655 kvm_vcpu_write_tsc_offset(vcpu, offset);
2659 * We split periods of matched TSC writes into generations.
2660 * For each generation, we track the original measured
2661 * nanosecond time, offset, and write, so if TSCs are in
2662 * sync, we can match exact offset, and if not, we can match
2663 * exact software computation in compute_guest_tsc()
2665 * These values are tracked in kvm->arch.cur_xxx variables.
2667 kvm->arch.cur_tsc_generation++;
2668 kvm->arch.cur_tsc_nsec = ns;
2669 kvm->arch.cur_tsc_write = tsc;
2670 kvm->arch.cur_tsc_offset = offset;
2671 kvm->arch.nr_vcpus_matched_tsc = 0;
2672 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2673 kvm->arch.nr_vcpus_matched_tsc++;
2676 /* Keep track of which generation this VCPU has synchronized to */
2677 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2678 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2679 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2681 kvm_track_tsc_matching(vcpu);
2684 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2686 struct kvm *kvm = vcpu->kvm;
2687 u64 offset, ns, elapsed;
2688 unsigned long flags;
2689 bool matched = false;
2690 bool synchronizing = false;
2692 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2693 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2694 ns = get_kvmclock_base_ns();
2695 elapsed = ns - kvm->arch.last_tsc_nsec;
2697 if (vcpu->arch.virtual_tsc_khz) {
2700 * detection of vcpu initialization -- need to sync
2701 * with other vCPUs. This particularly helps to keep
2702 * kvm_clock stable after CPU hotplug
2704 synchronizing = true;
2706 u64 tsc_exp = kvm->arch.last_tsc_write +
2707 nsec_to_cycles(vcpu, elapsed);
2708 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2710 * Special case: TSC write with a small delta (1 second)
2711 * of virtual cycle time against real time is
2712 * interpreted as an attempt to synchronize the CPU.
2714 synchronizing = data < tsc_exp + tsc_hz &&
2715 data + tsc_hz > tsc_exp;
2720 * For a reliable TSC, we can match TSC offsets, and for an unstable
2721 * TSC, we add elapsed time in this computation. We could let the
2722 * compensation code attempt to catch up if we fall behind, but
2723 * it's better to try to match offsets from the beginning.
2725 if (synchronizing &&
2726 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2727 if (!kvm_check_tsc_unstable()) {
2728 offset = kvm->arch.cur_tsc_offset;
2730 u64 delta = nsec_to_cycles(vcpu, elapsed);
2732 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2737 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2738 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2741 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2744 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2745 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2748 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2750 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
2751 WARN_ON(adjustment < 0);
2752 adjustment = kvm_scale_tsc((u64) adjustment,
2753 vcpu->arch.l1_tsc_scaling_ratio);
2754 adjust_tsc_offset_guest(vcpu, adjustment);
2757 #ifdef CONFIG_X86_64
2759 static u64 read_tsc(void)
2761 u64 ret = (u64)rdtsc_ordered();
2762 u64 last = pvclock_gtod_data.clock.cycle_last;
2764 if (likely(ret >= last))
2768 * GCC likes to generate cmov here, but this branch is extremely
2769 * predictable (it's just a function of time and the likely is
2770 * very likely) and there's a data dependence, so force GCC
2771 * to generate a branch instead. I don't barrier() because
2772 * we don't actually need a barrier, and if this function
2773 * ever gets inlined it will generate worse code.
2779 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2785 switch (clock->vclock_mode) {
2786 case VDSO_CLOCKMODE_HVCLOCK:
2787 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2789 if (tsc_pg_val != U64_MAX) {
2790 /* TSC page valid */
2791 *mode = VDSO_CLOCKMODE_HVCLOCK;
2792 v = (tsc_pg_val - clock->cycle_last) &
2795 /* TSC page invalid */
2796 *mode = VDSO_CLOCKMODE_NONE;
2799 case VDSO_CLOCKMODE_TSC:
2800 *mode = VDSO_CLOCKMODE_TSC;
2801 *tsc_timestamp = read_tsc();
2802 v = (*tsc_timestamp - clock->cycle_last) &
2806 *mode = VDSO_CLOCKMODE_NONE;
2809 if (*mode == VDSO_CLOCKMODE_NONE)
2810 *tsc_timestamp = v = 0;
2812 return v * clock->mult;
2815 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2817 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2823 seq = read_seqcount_begin(>od->seq);
2824 ns = gtod->raw_clock.base_cycles;
2825 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2826 ns >>= gtod->raw_clock.shift;
2827 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2828 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2834 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2836 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2842 seq = read_seqcount_begin(>od->seq);
2843 ts->tv_sec = gtod->wall_time_sec;
2844 ns = gtod->clock.base_cycles;
2845 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2846 ns >>= gtod->clock.shift;
2847 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2849 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2855 /* returns true if host is using TSC based clocksource */
2856 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2858 /* checked again under seqlock below */
2859 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2862 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2866 /* returns true if host is using TSC based clocksource */
2867 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2870 /* checked again under seqlock below */
2871 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2874 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2880 * Assuming a stable TSC across physical CPUS, and a stable TSC
2881 * across virtual CPUs, the following condition is possible.
2882 * Each numbered line represents an event visible to both
2883 * CPUs at the next numbered event.
2885 * "timespecX" represents host monotonic time. "tscX" represents
2888 * VCPU0 on CPU0 | VCPU1 on CPU1
2890 * 1. read timespec0,tsc0
2891 * 2. | timespec1 = timespec0 + N
2893 * 3. transition to guest | transition to guest
2894 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2895 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2896 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2898 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2901 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2903 * - 0 < N - M => M < N
2905 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2906 * always the case (the difference between two distinct xtime instances
2907 * might be smaller then the difference between corresponding TSC reads,
2908 * when updating guest vcpus pvclock areas).
2910 * To avoid that problem, do not allow visibility of distinct
2911 * system_timestamp/tsc_timestamp values simultaneously: use a master
2912 * copy of host monotonic time values. Update that master copy
2915 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2919 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2921 #ifdef CONFIG_X86_64
2922 struct kvm_arch *ka = &kvm->arch;
2924 bool host_tsc_clocksource, vcpus_matched;
2926 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2927 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2928 atomic_read(&kvm->online_vcpus));
2931 * If the host uses TSC clock, then passthrough TSC as stable
2934 host_tsc_clocksource = kvm_get_time_and_clockread(
2935 &ka->master_kernel_ns,
2936 &ka->master_cycle_now);
2938 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2939 && !ka->backwards_tsc_observed
2940 && !ka->boot_vcpu_runs_old_kvmclock;
2942 if (ka->use_master_clock)
2943 atomic_set(&kvm_guest_has_master_clock, 1);
2945 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2946 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2951 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2953 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2956 static void __kvm_start_pvclock_update(struct kvm *kvm)
2958 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2959 write_seqcount_begin(&kvm->arch.pvclock_sc);
2962 static void kvm_start_pvclock_update(struct kvm *kvm)
2964 kvm_make_mclock_inprogress_request(kvm);
2966 /* no guest entries from this point */
2967 __kvm_start_pvclock_update(kvm);
2970 static void kvm_end_pvclock_update(struct kvm *kvm)
2972 struct kvm_arch *ka = &kvm->arch;
2973 struct kvm_vcpu *vcpu;
2976 write_seqcount_end(&ka->pvclock_sc);
2977 raw_spin_unlock_irq(&ka->tsc_write_lock);
2978 kvm_for_each_vcpu(i, vcpu, kvm)
2979 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2981 /* guest entries allowed */
2982 kvm_for_each_vcpu(i, vcpu, kvm)
2983 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2986 static void kvm_update_masterclock(struct kvm *kvm)
2988 kvm_hv_request_tsc_page_update(kvm);
2989 kvm_start_pvclock_update(kvm);
2990 pvclock_update_vm_gtod_copy(kvm);
2991 kvm_end_pvclock_update(kvm);
2995 * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's
2996 * per-CPU value (which may be zero if a CPU is going offline). Note, tsc_khz
2997 * can change during boot even if the TSC is constant, as it's possible for KVM
2998 * to be loaded before TSC calibration completes. Ideally, KVM would get a
2999 * notification when calibration completes, but practically speaking calibration
3000 * will complete before userspace is alive enough to create VMs.
3002 static unsigned long get_cpu_tsc_khz(void)
3004 if (static_cpu_has(X86_FEATURE_CONSTANT_TSC))
3007 return __this_cpu_read(cpu_tsc_khz);
3010 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
3011 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3013 struct kvm_arch *ka = &kvm->arch;
3014 struct pvclock_vcpu_time_info hv_clock;
3016 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
3020 if (ka->use_master_clock &&
3021 (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) {
3022 #ifdef CONFIG_X86_64
3023 struct timespec64 ts;
3025 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
3026 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
3027 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
3030 data->host_tsc = rdtsc();
3032 data->flags |= KVM_CLOCK_TSC_STABLE;
3033 hv_clock.tsc_timestamp = ka->master_cycle_now;
3034 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3035 kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL,
3036 &hv_clock.tsc_shift,
3037 &hv_clock.tsc_to_system_mul);
3038 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
3040 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
3046 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3048 struct kvm_arch *ka = &kvm->arch;
3052 seq = read_seqcount_begin(&ka->pvclock_sc);
3053 __get_kvmclock(kvm, data);
3054 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3057 u64 get_kvmclock_ns(struct kvm *kvm)
3059 struct kvm_clock_data data;
3061 get_kvmclock(kvm, &data);
3065 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
3066 struct gfn_to_pfn_cache *gpc,
3067 unsigned int offset)
3069 struct kvm_vcpu_arch *vcpu = &v->arch;
3070 struct pvclock_vcpu_time_info *guest_hv_clock;
3071 unsigned long flags;
3073 read_lock_irqsave(&gpc->lock, flags);
3074 while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) {
3075 read_unlock_irqrestore(&gpc->lock, flags);
3077 if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock)))
3080 read_lock_irqsave(&gpc->lock, flags);
3083 guest_hv_clock = (void *)(gpc->khva + offset);
3086 * This VCPU is paused, but it's legal for a guest to read another
3087 * VCPU's kvmclock, so we really have to follow the specification where
3088 * it says that version is odd if data is being modified, and even after
3092 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
3095 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3096 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3098 if (vcpu->pvclock_set_guest_stopped_request) {
3099 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3100 vcpu->pvclock_set_guest_stopped_request = false;
3103 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3106 guest_hv_clock->version = ++vcpu->hv_clock.version;
3108 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT);
3109 read_unlock_irqrestore(&gpc->lock, flags);
3111 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3114 static int kvm_guest_time_update(struct kvm_vcpu *v)
3116 unsigned long flags, tgt_tsc_khz;
3118 struct kvm_vcpu_arch *vcpu = &v->arch;
3119 struct kvm_arch *ka = &v->kvm->arch;
3121 u64 tsc_timestamp, host_tsc;
3123 bool use_master_clock;
3129 * If the host uses TSC clock, then passthrough TSC as stable
3133 seq = read_seqcount_begin(&ka->pvclock_sc);
3134 use_master_clock = ka->use_master_clock;
3135 if (use_master_clock) {
3136 host_tsc = ka->master_cycle_now;
3137 kernel_ns = ka->master_kernel_ns;
3139 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3141 /* Keep irq disabled to prevent changes to the clock */
3142 local_irq_save(flags);
3143 tgt_tsc_khz = get_cpu_tsc_khz();
3144 if (unlikely(tgt_tsc_khz == 0)) {
3145 local_irq_restore(flags);
3146 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3149 if (!use_master_clock) {
3151 kernel_ns = get_kvmclock_base_ns();
3154 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3157 * We may have to catch up the TSC to match elapsed wall clock
3158 * time for two reasons, even if kvmclock is used.
3159 * 1) CPU could have been running below the maximum TSC rate
3160 * 2) Broken TSC compensation resets the base at each VCPU
3161 * entry to avoid unknown leaps of TSC even when running
3162 * again on the same CPU. This may cause apparent elapsed
3163 * time to disappear, and the guest to stand still or run
3166 if (vcpu->tsc_catchup) {
3167 u64 tsc = compute_guest_tsc(v, kernel_ns);
3168 if (tsc > tsc_timestamp) {
3169 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3170 tsc_timestamp = tsc;
3174 local_irq_restore(flags);
3176 /* With all the info we got, fill in the values */
3178 if (kvm_caps.has_tsc_control)
3179 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3180 v->arch.l1_tsc_scaling_ratio);
3182 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3183 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3184 &vcpu->hv_clock.tsc_shift,
3185 &vcpu->hv_clock.tsc_to_system_mul);
3186 vcpu->hw_tsc_khz = tgt_tsc_khz;
3187 kvm_xen_update_tsc_info(v);
3190 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3191 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3192 vcpu->last_guest_tsc = tsc_timestamp;
3194 /* If the host uses TSC clocksource, then it is stable */
3196 if (use_master_clock)
3197 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3199 vcpu->hv_clock.flags = pvclock_flags;
3201 if (vcpu->pv_time.active)
3202 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0);
3203 if (vcpu->xen.vcpu_info_cache.active)
3204 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3205 offsetof(struct compat_vcpu_info, time));
3206 if (vcpu->xen.vcpu_time_info_cache.active)
3207 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0);
3208 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3213 * kvmclock updates which are isolated to a given vcpu, such as
3214 * vcpu->cpu migration, should not allow system_timestamp from
3215 * the rest of the vcpus to remain static. Otherwise ntp frequency
3216 * correction applies to one vcpu's system_timestamp but not
3219 * So in those cases, request a kvmclock update for all vcpus.
3220 * We need to rate-limit these requests though, as they can
3221 * considerably slow guests that have a large number of vcpus.
3222 * The time for a remote vcpu to update its kvmclock is bound
3223 * by the delay we use to rate-limit the updates.
3226 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3228 static void kvmclock_update_fn(struct work_struct *work)
3231 struct delayed_work *dwork = to_delayed_work(work);
3232 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3233 kvmclock_update_work);
3234 struct kvm *kvm = container_of(ka, struct kvm, arch);
3235 struct kvm_vcpu *vcpu;
3237 kvm_for_each_vcpu(i, vcpu, kvm) {
3238 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3239 kvm_vcpu_kick(vcpu);
3243 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3245 struct kvm *kvm = v->kvm;
3247 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3248 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3249 KVMCLOCK_UPDATE_DELAY);
3252 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3254 static void kvmclock_sync_fn(struct work_struct *work)
3256 struct delayed_work *dwork = to_delayed_work(work);
3257 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3258 kvmclock_sync_work);
3259 struct kvm *kvm = container_of(ka, struct kvm, arch);
3261 if (!kvmclock_periodic_sync)
3264 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3265 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3266 KVMCLOCK_SYNC_PERIOD);
3269 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
3270 static bool is_mci_control_msr(u32 msr)
3272 return (msr & 3) == 0;
3274 static bool is_mci_status_msr(u32 msr)
3276 return (msr & 3) == 1;
3280 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3282 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3284 /* McStatusWrEn enabled? */
3285 if (guest_cpuid_is_amd_or_hygon(vcpu))
3286 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3291 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3293 u64 mcg_cap = vcpu->arch.mcg_cap;
3294 unsigned bank_num = mcg_cap & 0xff;
3295 u32 msr = msr_info->index;
3296 u64 data = msr_info->data;
3297 u32 offset, last_msr;
3300 case MSR_IA32_MCG_STATUS:
3301 vcpu->arch.mcg_status = data;
3303 case MSR_IA32_MCG_CTL:
3304 if (!(mcg_cap & MCG_CTL_P) &&
3305 (data || !msr_info->host_initiated))
3307 if (data != 0 && data != ~(u64)0)
3309 vcpu->arch.mcg_ctl = data;
3311 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3312 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3316 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
3318 /* An attempt to write a 1 to a reserved bit raises #GP */
3319 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
3321 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3322 last_msr + 1 - MSR_IA32_MC0_CTL2);
3323 vcpu->arch.mci_ctl2_banks[offset] = data;
3325 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3326 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3331 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other
3332 * values are architecturally undefined. But, some Linux
3333 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
3334 * issue on AMD K8s, allow bit 10 to be clear when setting all
3335 * other bits in order to avoid an uncaught #GP in the guest.
3337 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable,
3338 * single-bit ECC data errors.
3340 if (is_mci_control_msr(msr) &&
3341 data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
3345 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
3346 * AMD-based CPUs allow non-zero values, but if and only if
3347 * HWCR[McStatusWrEn] is set.
3349 if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
3350 data != 0 && !can_set_mci_status(vcpu))
3353 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3354 last_msr + 1 - MSR_IA32_MC0_CTL);
3355 vcpu->arch.mce_banks[offset] = data;
3363 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3365 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3367 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3370 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3372 gpa_t gpa = data & ~0x3f;
3374 /* Bits 4:5 are reserved, Should be zero */
3378 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3379 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3382 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3383 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3386 if (!lapic_in_kernel(vcpu))
3387 return data ? 1 : 0;
3389 vcpu->arch.apf.msr_en_val = data;
3391 if (!kvm_pv_async_pf_enabled(vcpu)) {
3392 kvm_clear_async_pf_completion_queue(vcpu);
3393 kvm_async_pf_hash_reset(vcpu);
3397 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3401 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3402 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3404 kvm_async_pf_wakeup_all(vcpu);
3409 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3411 /* Bits 8-63 are reserved */
3415 if (!lapic_in_kernel(vcpu))
3418 vcpu->arch.apf.msr_int_val = data;
3420 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3425 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3427 kvm_gpc_deactivate(&vcpu->arch.pv_time);
3428 vcpu->arch.time = 0;
3431 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3433 ++vcpu->stat.tlb_flush;
3434 static_call(kvm_x86_flush_tlb_all)(vcpu);
3436 /* Flushing all ASIDs flushes the current ASID... */
3437 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3440 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3442 ++vcpu->stat.tlb_flush;
3446 * A TLB flush on behalf of the guest is equivalent to
3447 * INVPCID(all), toggling CR4.PGE, etc., which requires
3448 * a forced sync of the shadow page tables. Ensure all the
3449 * roots are synced and the guest TLB in hardware is clean.
3451 kvm_mmu_sync_roots(vcpu);
3452 kvm_mmu_sync_prev_roots(vcpu);
3455 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3458 * Flushing all "guest" TLB is always a superset of Hyper-V's fine
3461 kvm_hv_vcpu_purge_flush_tlb(vcpu);
3465 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3467 ++vcpu->stat.tlb_flush;
3468 static_call(kvm_x86_flush_tlb_current)(vcpu);
3472 * Service "local" TLB flush requests, which are specific to the current MMU
3473 * context. In addition to the generic event handling in vcpu_enter_guest(),
3474 * TLB flushes that are targeted at an MMU context also need to be serviced
3475 * prior before nested VM-Enter/VM-Exit.
3477 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3479 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3480 kvm_vcpu_flush_tlb_current(vcpu);
3482 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3483 kvm_vcpu_flush_tlb_guest(vcpu);
3485 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3487 static void record_steal_time(struct kvm_vcpu *vcpu)
3489 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3490 struct kvm_steal_time __user *st;
3491 struct kvm_memslots *slots;
3492 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3496 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3497 kvm_xen_runstate_set_running(vcpu);
3501 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3504 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3507 slots = kvm_memslots(vcpu->kvm);
3509 if (unlikely(slots->generation != ghc->generation ||
3511 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3512 /* We rely on the fact that it fits in a single page. */
3513 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3515 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) ||
3516 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3520 st = (struct kvm_steal_time __user *)ghc->hva;
3522 * Doing a TLB flush here, on the guest's behalf, can avoid
3525 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3526 u8 st_preempted = 0;
3529 if (!user_access_begin(st, sizeof(*st)))
3532 asm volatile("1: xchgb %0, %2\n"
3535 _ASM_EXTABLE_UA(1b, 2b)
3536 : "+q" (st_preempted),
3538 "+m" (st->preempted));
3544 vcpu->arch.st.preempted = 0;
3546 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3547 st_preempted & KVM_VCPU_FLUSH_TLB);
3548 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3549 kvm_vcpu_flush_tlb_guest(vcpu);
3551 if (!user_access_begin(st, sizeof(*st)))
3554 if (!user_access_begin(st, sizeof(*st)))
3557 unsafe_put_user(0, &st->preempted, out);
3558 vcpu->arch.st.preempted = 0;
3561 unsafe_get_user(version, &st->version, out);
3563 version += 1; /* first time write, random junk */
3566 unsafe_put_user(version, &st->version, out);
3570 unsafe_get_user(steal, &st->steal, out);
3571 steal += current->sched_info.run_delay -
3572 vcpu->arch.st.last_steal;
3573 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3574 unsafe_put_user(steal, &st->steal, out);
3577 unsafe_put_user(version, &st->version, out);
3582 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3585 static bool kvm_is_msr_to_save(u32 msr_index)
3589 for (i = 0; i < num_msrs_to_save; i++) {
3590 if (msrs_to_save[i] == msr_index)
3597 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3599 u32 msr = msr_info->index;
3600 u64 data = msr_info->data;
3602 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3603 return kvm_xen_write_hypercall_page(vcpu, data);
3606 case MSR_AMD64_NB_CFG:
3607 case MSR_IA32_UCODE_WRITE:
3608 case MSR_VM_HSAVE_PA:
3609 case MSR_AMD64_PATCH_LOADER:
3610 case MSR_AMD64_BU_CFG2:
3611 case MSR_AMD64_DC_CFG:
3612 case MSR_F15H_EX_CFG:
3615 case MSR_IA32_UCODE_REV:
3616 if (msr_info->host_initiated)
3617 vcpu->arch.microcode_version = data;
3619 case MSR_IA32_ARCH_CAPABILITIES:
3620 if (!msr_info->host_initiated)
3622 vcpu->arch.arch_capabilities = data;
3624 case MSR_IA32_PERF_CAPABILITIES:
3625 if (!msr_info->host_initiated)
3627 if (data & ~kvm_caps.supported_perf_cap)
3630 vcpu->arch.perf_capabilities = data;
3631 kvm_pmu_refresh(vcpu);
3633 case MSR_IA32_PRED_CMD:
3634 if (!msr_info->host_initiated && !guest_has_pred_cmd_msr(vcpu))
3637 if (!boot_cpu_has(X86_FEATURE_IBPB) || (data & ~PRED_CMD_IBPB))
3642 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3644 case MSR_IA32_FLUSH_CMD:
3645 if (!msr_info->host_initiated &&
3646 !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D))
3649 if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH))
3654 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
3657 return set_efer(vcpu, msr_info);
3659 data &= ~(u64)0x40; /* ignore flush filter disable */
3660 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3661 data &= ~(u64)0x8; /* ignore TLB cache disable */
3663 /* Handle McStatusWrEn */
3664 if (data == BIT_ULL(18)) {
3665 vcpu->arch.msr_hwcr = data;
3666 } else if (data != 0) {
3667 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3671 case MSR_FAM10H_MMIO_CONF_BASE:
3673 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3677 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
3678 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
3679 return kvm_mtrr_set_msr(vcpu, msr, data);
3680 case MSR_IA32_APICBASE:
3681 return kvm_set_apic_base(vcpu, msr_info);
3682 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3683 return kvm_x2apic_msr_write(vcpu, msr, data);
3684 case MSR_IA32_TSC_DEADLINE:
3685 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3687 case MSR_IA32_TSC_ADJUST:
3688 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3689 if (!msr_info->host_initiated) {
3690 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3691 adjust_tsc_offset_guest(vcpu, adj);
3692 /* Before back to guest, tsc_timestamp must be adjusted
3693 * as well, otherwise guest's percpu pvclock time could jump.
3695 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3697 vcpu->arch.ia32_tsc_adjust_msr = data;
3700 case MSR_IA32_MISC_ENABLE: {
3701 u64 old_val = vcpu->arch.ia32_misc_enable_msr;
3703 if (!msr_info->host_initiated) {
3705 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)
3708 /* R bits, i.e. writes are ignored, but don't fault. */
3709 data = data & ~MSR_IA32_MISC_ENABLE_EMON;
3710 data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
3713 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3714 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3715 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3717 vcpu->arch.ia32_misc_enable_msr = data;
3718 kvm_update_cpuid_runtime(vcpu);
3720 vcpu->arch.ia32_misc_enable_msr = data;
3724 case MSR_IA32_SMBASE:
3725 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
3727 vcpu->arch.smbase = data;
3729 case MSR_IA32_POWER_CTL:
3730 vcpu->arch.msr_ia32_power_ctl = data;
3733 if (msr_info->host_initiated) {
3734 kvm_synchronize_tsc(vcpu, data);
3736 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3737 adjust_tsc_offset_guest(vcpu, adj);
3738 vcpu->arch.ia32_tsc_adjust_msr += adj;
3742 if (!msr_info->host_initiated &&
3743 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3746 * KVM supports exposing PT to the guest, but does not support
3747 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3748 * XSAVES/XRSTORS to save/restore PT MSRs.
3750 if (data & ~kvm_caps.supported_xss)
3752 vcpu->arch.ia32_xss = data;
3753 kvm_update_cpuid_runtime(vcpu);
3756 if (!msr_info->host_initiated)
3758 vcpu->arch.smi_count = data;
3760 case MSR_KVM_WALL_CLOCK_NEW:
3761 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3764 vcpu->kvm->arch.wall_clock = data;
3765 kvm_write_wall_clock(vcpu->kvm, data, 0);
3767 case MSR_KVM_WALL_CLOCK:
3768 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3771 vcpu->kvm->arch.wall_clock = data;
3772 kvm_write_wall_clock(vcpu->kvm, data, 0);
3774 case MSR_KVM_SYSTEM_TIME_NEW:
3775 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3778 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3780 case MSR_KVM_SYSTEM_TIME:
3781 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3784 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3786 case MSR_KVM_ASYNC_PF_EN:
3787 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3790 if (kvm_pv_enable_async_pf(vcpu, data))
3793 case MSR_KVM_ASYNC_PF_INT:
3794 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3797 if (kvm_pv_enable_async_pf_int(vcpu, data))
3800 case MSR_KVM_ASYNC_PF_ACK:
3801 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3804 vcpu->arch.apf.pageready_pending = false;
3805 kvm_check_async_pf_completion(vcpu);
3808 case MSR_KVM_STEAL_TIME:
3809 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3812 if (unlikely(!sched_info_on()))
3815 if (data & KVM_STEAL_RESERVED_MASK)
3818 vcpu->arch.st.msr_val = data;
3820 if (!(data & KVM_MSR_ENABLED))
3823 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3826 case MSR_KVM_PV_EOI_EN:
3827 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3830 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3834 case MSR_KVM_POLL_CONTROL:
3835 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3838 /* only enable bit supported */
3839 if (data & (-1ULL << 1))
3842 vcpu->arch.msr_kvm_poll_control = data;
3845 case MSR_IA32_MCG_CTL:
3846 case MSR_IA32_MCG_STATUS:
3847 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3848 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3849 return set_msr_mce(vcpu, msr_info);
3851 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3852 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3853 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3854 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3855 if (kvm_pmu_is_valid_msr(vcpu, msr))
3856 return kvm_pmu_set_msr(vcpu, msr_info);
3859 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3861 case MSR_K7_CLK_CTL:
3863 * Ignore all writes to this no longer documented MSR.
3864 * Writes are only relevant for old K7 processors,
3865 * all pre-dating SVM, but a recommended workaround from
3866 * AMD for these chips. It is possible to specify the
3867 * affected processor models on the command line, hence
3868 * the need to ignore the workaround.
3871 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3872 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3873 case HV_X64_MSR_SYNDBG_OPTIONS:
3874 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3875 case HV_X64_MSR_CRASH_CTL:
3876 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3877 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3878 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3879 case HV_X64_MSR_TSC_EMULATION_STATUS:
3880 case HV_X64_MSR_TSC_INVARIANT_CONTROL:
3881 return kvm_hv_set_msr_common(vcpu, msr, data,
3882 msr_info->host_initiated);
3883 case MSR_IA32_BBL_CR_CTL3:
3884 /* Drop writes to this legacy MSR -- see rdmsr
3885 * counterpart for further detail.
3887 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3889 case MSR_AMD64_OSVW_ID_LENGTH:
3890 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3892 vcpu->arch.osvw.length = data;
3894 case MSR_AMD64_OSVW_STATUS:
3895 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3897 vcpu->arch.osvw.status = data;
3899 case MSR_PLATFORM_INFO:
3900 if (!msr_info->host_initiated ||
3901 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3902 cpuid_fault_enabled(vcpu)))
3904 vcpu->arch.msr_platform_info = data;
3906 case MSR_MISC_FEATURES_ENABLES:
3907 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3908 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3909 !supports_cpuid_fault(vcpu)))
3911 vcpu->arch.msr_misc_features_enables = data;
3913 #ifdef CONFIG_X86_64
3915 if (!msr_info->host_initiated &&
3916 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3919 if (data & ~kvm_guest_supported_xfd(vcpu))
3922 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3924 case MSR_IA32_XFD_ERR:
3925 if (!msr_info->host_initiated &&
3926 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3929 if (data & ~kvm_guest_supported_xfd(vcpu))
3932 vcpu->arch.guest_fpu.xfd_err = data;
3936 if (kvm_pmu_is_valid_msr(vcpu, msr))
3937 return kvm_pmu_set_msr(vcpu, msr_info);
3940 * Userspace is allowed to write '0' to MSRs that KVM reports
3941 * as to-be-saved, even if an MSRs isn't fully supported.
3943 if (msr_info->host_initiated && !data &&
3944 kvm_is_msr_to_save(msr))
3947 return KVM_MSR_RET_INVALID;
3951 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3953 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3956 u64 mcg_cap = vcpu->arch.mcg_cap;
3957 unsigned bank_num = mcg_cap & 0xff;
3958 u32 offset, last_msr;
3961 case MSR_IA32_P5_MC_ADDR:
3962 case MSR_IA32_P5_MC_TYPE:
3965 case MSR_IA32_MCG_CAP:
3966 data = vcpu->arch.mcg_cap;
3968 case MSR_IA32_MCG_CTL:
3969 if (!(mcg_cap & MCG_CTL_P) && !host)
3971 data = vcpu->arch.mcg_ctl;
3973 case MSR_IA32_MCG_STATUS:
3974 data = vcpu->arch.mcg_status;
3976 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3977 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3981 if (!(mcg_cap & MCG_CMCI_P) && !host)
3983 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3984 last_msr + 1 - MSR_IA32_MC0_CTL2);
3985 data = vcpu->arch.mci_ctl2_banks[offset];
3987 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3988 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3992 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3993 last_msr + 1 - MSR_IA32_MC0_CTL);
3994 data = vcpu->arch.mce_banks[offset];
4003 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4005 switch (msr_info->index) {
4006 case MSR_IA32_PLATFORM_ID:
4007 case MSR_IA32_EBL_CR_POWERON:
4008 case MSR_IA32_LASTBRANCHFROMIP:
4009 case MSR_IA32_LASTBRANCHTOIP:
4010 case MSR_IA32_LASTINTFROMIP:
4011 case MSR_IA32_LASTINTTOIP:
4012 case MSR_AMD64_SYSCFG:
4013 case MSR_K8_TSEG_ADDR:
4014 case MSR_K8_TSEG_MASK:
4015 case MSR_VM_HSAVE_PA:
4016 case MSR_K8_INT_PENDING_MSG:
4017 case MSR_AMD64_NB_CFG:
4018 case MSR_FAM10H_MMIO_CONF_BASE:
4019 case MSR_AMD64_BU_CFG2:
4020 case MSR_IA32_PERF_CTL:
4021 case MSR_AMD64_DC_CFG:
4022 case MSR_F15H_EX_CFG:
4024 * Intel Sandy Bridge CPUs must support the RAPL (running average power
4025 * limit) MSRs. Just return 0, as we do not want to expose the host
4026 * data here. Do not conditionalize this on CPUID, as KVM does not do
4027 * so for existing CPU-specific MSRs.
4029 case MSR_RAPL_POWER_UNIT:
4030 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
4031 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
4032 case MSR_PKG_ENERGY_STATUS: /* Total package */
4033 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
4036 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
4037 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
4038 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
4039 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
4040 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4041 return kvm_pmu_get_msr(vcpu, msr_info);
4044 case MSR_IA32_UCODE_REV:
4045 msr_info->data = vcpu->arch.microcode_version;
4047 case MSR_IA32_ARCH_CAPABILITIES:
4048 if (!msr_info->host_initiated &&
4049 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4051 msr_info->data = vcpu->arch.arch_capabilities;
4053 case MSR_IA32_PERF_CAPABILITIES:
4054 if (!msr_info->host_initiated &&
4055 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
4057 msr_info->data = vcpu->arch.perf_capabilities;
4059 case MSR_IA32_POWER_CTL:
4060 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
4062 case MSR_IA32_TSC: {
4064 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
4065 * even when not intercepted. AMD manual doesn't explicitly
4066 * state this but appears to behave the same.
4068 * On userspace reads and writes, however, we unconditionally
4069 * return L1's TSC value to ensure backwards-compatible
4070 * behavior for migration.
4074 if (msr_info->host_initiated) {
4075 offset = vcpu->arch.l1_tsc_offset;
4076 ratio = vcpu->arch.l1_tsc_scaling_ratio;
4078 offset = vcpu->arch.tsc_offset;
4079 ratio = vcpu->arch.tsc_scaling_ratio;
4082 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
4086 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
4087 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
4088 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
4089 case 0xcd: /* fsb frequency */
4093 * MSR_EBC_FREQUENCY_ID
4094 * Conservative value valid for even the basic CPU models.
4095 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
4096 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
4097 * and 266MHz for model 3, or 4. Set Core Clock
4098 * Frequency to System Bus Frequency Ratio to 1 (bits
4099 * 31:24) even though these are only valid for CPU
4100 * models > 2, however guests may end up dividing or
4101 * multiplying by zero otherwise.
4103 case MSR_EBC_FREQUENCY_ID:
4104 msr_info->data = 1 << 24;
4106 case MSR_IA32_APICBASE:
4107 msr_info->data = kvm_get_apic_base(vcpu);
4109 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
4110 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
4111 case MSR_IA32_TSC_DEADLINE:
4112 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
4114 case MSR_IA32_TSC_ADJUST:
4115 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
4117 case MSR_IA32_MISC_ENABLE:
4118 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
4120 case MSR_IA32_SMBASE:
4121 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
4123 msr_info->data = vcpu->arch.smbase;
4126 msr_info->data = vcpu->arch.smi_count;
4128 case MSR_IA32_PERF_STATUS:
4129 /* TSC increment by tick */
4130 msr_info->data = 1000ULL;
4131 /* CPU multiplier */
4132 msr_info->data |= (((uint64_t)4ULL) << 40);
4135 msr_info->data = vcpu->arch.efer;
4137 case MSR_KVM_WALL_CLOCK:
4138 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4141 msr_info->data = vcpu->kvm->arch.wall_clock;
4143 case MSR_KVM_WALL_CLOCK_NEW:
4144 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4147 msr_info->data = vcpu->kvm->arch.wall_clock;
4149 case MSR_KVM_SYSTEM_TIME:
4150 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4153 msr_info->data = vcpu->arch.time;
4155 case MSR_KVM_SYSTEM_TIME_NEW:
4156 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4159 msr_info->data = vcpu->arch.time;
4161 case MSR_KVM_ASYNC_PF_EN:
4162 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4165 msr_info->data = vcpu->arch.apf.msr_en_val;
4167 case MSR_KVM_ASYNC_PF_INT:
4168 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4171 msr_info->data = vcpu->arch.apf.msr_int_val;
4173 case MSR_KVM_ASYNC_PF_ACK:
4174 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4179 case MSR_KVM_STEAL_TIME:
4180 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4183 msr_info->data = vcpu->arch.st.msr_val;
4185 case MSR_KVM_PV_EOI_EN:
4186 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4189 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4191 case MSR_KVM_POLL_CONTROL:
4192 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4195 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4197 case MSR_IA32_P5_MC_ADDR:
4198 case MSR_IA32_P5_MC_TYPE:
4199 case MSR_IA32_MCG_CAP:
4200 case MSR_IA32_MCG_CTL:
4201 case MSR_IA32_MCG_STATUS:
4202 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4203 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4204 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4205 msr_info->host_initiated);
4207 if (!msr_info->host_initiated &&
4208 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4210 msr_info->data = vcpu->arch.ia32_xss;
4212 case MSR_K7_CLK_CTL:
4214 * Provide expected ramp-up count for K7. All other
4215 * are set to zero, indicating minimum divisors for
4218 * This prevents guest kernels on AMD host with CPU
4219 * type 6, model 8 and higher from exploding due to
4220 * the rdmsr failing.
4222 msr_info->data = 0x20000000;
4224 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4225 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4226 case HV_X64_MSR_SYNDBG_OPTIONS:
4227 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4228 case HV_X64_MSR_CRASH_CTL:
4229 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4230 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4231 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4232 case HV_X64_MSR_TSC_EMULATION_STATUS:
4233 case HV_X64_MSR_TSC_INVARIANT_CONTROL:
4234 return kvm_hv_get_msr_common(vcpu,
4235 msr_info->index, &msr_info->data,
4236 msr_info->host_initiated);
4237 case MSR_IA32_BBL_CR_CTL3:
4238 /* This legacy MSR exists but isn't fully documented in current
4239 * silicon. It is however accessed by winxp in very narrow
4240 * scenarios where it sets bit #19, itself documented as
4241 * a "reserved" bit. Best effort attempt to source coherent
4242 * read data here should the balance of the register be
4243 * interpreted by the guest:
4245 * L2 cache control register 3: 64GB range, 256KB size,
4246 * enabled, latency 0x1, configured
4248 msr_info->data = 0xbe702111;
4250 case MSR_AMD64_OSVW_ID_LENGTH:
4251 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4253 msr_info->data = vcpu->arch.osvw.length;
4255 case MSR_AMD64_OSVW_STATUS:
4256 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4258 msr_info->data = vcpu->arch.osvw.status;
4260 case MSR_PLATFORM_INFO:
4261 if (!msr_info->host_initiated &&
4262 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4264 msr_info->data = vcpu->arch.msr_platform_info;
4266 case MSR_MISC_FEATURES_ENABLES:
4267 msr_info->data = vcpu->arch.msr_misc_features_enables;
4270 msr_info->data = vcpu->arch.msr_hwcr;
4272 #ifdef CONFIG_X86_64
4274 if (!msr_info->host_initiated &&
4275 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4278 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4280 case MSR_IA32_XFD_ERR:
4281 if (!msr_info->host_initiated &&
4282 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4285 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4289 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4290 return kvm_pmu_get_msr(vcpu, msr_info);
4293 * Userspace is allowed to read MSRs that KVM reports as
4294 * to-be-saved, even if an MSR isn't fully supported.
4296 if (msr_info->host_initiated &&
4297 kvm_is_msr_to_save(msr_info->index)) {
4302 return KVM_MSR_RET_INVALID;
4306 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4309 * Read or write a bunch of msrs. All parameters are kernel addresses.
4311 * @return number of msrs set successfully.
4313 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4314 struct kvm_msr_entry *entries,
4315 int (*do_msr)(struct kvm_vcpu *vcpu,
4316 unsigned index, u64 *data))
4320 for (i = 0; i < msrs->nmsrs; ++i)
4321 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4328 * Read or write a bunch of msrs. Parameters are user addresses.
4330 * @return number of msrs set successfully.
4332 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4333 int (*do_msr)(struct kvm_vcpu *vcpu,
4334 unsigned index, u64 *data),
4337 struct kvm_msrs msrs;
4338 struct kvm_msr_entry *entries;
4343 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4347 if (msrs.nmsrs >= MAX_IO_MSRS)
4350 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4351 entries = memdup_user(user_msrs->entries, size);
4352 if (IS_ERR(entries)) {
4353 r = PTR_ERR(entries);
4357 r = __msr_io(vcpu, &msrs, entries, do_msr);
4359 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4367 static inline bool kvm_can_mwait_in_guest(void)
4369 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4370 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4371 boot_cpu_has(X86_FEATURE_ARAT);
4374 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4375 struct kvm_cpuid2 __user *cpuid_arg)
4377 struct kvm_cpuid2 cpuid;
4381 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4384 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4389 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4395 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4400 case KVM_CAP_IRQCHIP:
4402 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4403 case KVM_CAP_SET_TSS_ADDR:
4404 case KVM_CAP_EXT_CPUID:
4405 case KVM_CAP_EXT_EMUL_CPUID:
4406 case KVM_CAP_CLOCKSOURCE:
4408 case KVM_CAP_NOP_IO_DELAY:
4409 case KVM_CAP_MP_STATE:
4410 case KVM_CAP_SYNC_MMU:
4411 case KVM_CAP_USER_NMI:
4412 case KVM_CAP_REINJECT_CONTROL:
4413 case KVM_CAP_IRQ_INJECT_STATUS:
4414 case KVM_CAP_IOEVENTFD:
4415 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4417 case KVM_CAP_PIT_STATE2:
4418 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4419 case KVM_CAP_VCPU_EVENTS:
4420 case KVM_CAP_HYPERV:
4421 case KVM_CAP_HYPERV_VAPIC:
4422 case KVM_CAP_HYPERV_SPIN:
4423 case KVM_CAP_HYPERV_SYNIC:
4424 case KVM_CAP_HYPERV_SYNIC2:
4425 case KVM_CAP_HYPERV_VP_INDEX:
4426 case KVM_CAP_HYPERV_EVENTFD:
4427 case KVM_CAP_HYPERV_TLBFLUSH:
4428 case KVM_CAP_HYPERV_SEND_IPI:
4429 case KVM_CAP_HYPERV_CPUID:
4430 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4431 case KVM_CAP_SYS_HYPERV_CPUID:
4432 case KVM_CAP_PCI_SEGMENT:
4433 case KVM_CAP_DEBUGREGS:
4434 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4436 case KVM_CAP_ASYNC_PF:
4437 case KVM_CAP_ASYNC_PF_INT:
4438 case KVM_CAP_GET_TSC_KHZ:
4439 case KVM_CAP_KVMCLOCK_CTRL:
4440 case KVM_CAP_READONLY_MEM:
4441 case KVM_CAP_HYPERV_TIME:
4442 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4443 case KVM_CAP_TSC_DEADLINE_TIMER:
4444 case KVM_CAP_DISABLE_QUIRKS:
4445 case KVM_CAP_SET_BOOT_CPU_ID:
4446 case KVM_CAP_SPLIT_IRQCHIP:
4447 case KVM_CAP_IMMEDIATE_EXIT:
4448 case KVM_CAP_PMU_EVENT_FILTER:
4449 case KVM_CAP_PMU_EVENT_MASKED_EVENTS:
4450 case KVM_CAP_GET_MSR_FEATURES:
4451 case KVM_CAP_MSR_PLATFORM_INFO:
4452 case KVM_CAP_EXCEPTION_PAYLOAD:
4453 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
4454 case KVM_CAP_SET_GUEST_DEBUG:
4455 case KVM_CAP_LAST_CPU:
4456 case KVM_CAP_X86_USER_SPACE_MSR:
4457 case KVM_CAP_X86_MSR_FILTER:
4458 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4459 #ifdef CONFIG_X86_SGX_KVM
4460 case KVM_CAP_SGX_ATTRIBUTE:
4462 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4463 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4464 case KVM_CAP_SREGS2:
4465 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4466 case KVM_CAP_VCPU_ATTRIBUTES:
4467 case KVM_CAP_SYS_ATTRIBUTES:
4469 case KVM_CAP_ENABLE_CAP:
4470 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
4473 case KVM_CAP_EXIT_HYPERCALL:
4474 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4476 case KVM_CAP_SET_GUEST_DEBUG2:
4477 return KVM_GUESTDBG_VALID_MASK;
4478 #ifdef CONFIG_KVM_XEN
4479 case KVM_CAP_XEN_HVM:
4480 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4481 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4482 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4483 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4484 KVM_XEN_HVM_CONFIG_EVTCHN_SEND;
4485 if (sched_info_on())
4486 r |= KVM_XEN_HVM_CONFIG_RUNSTATE |
4487 KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG;
4490 case KVM_CAP_SYNC_REGS:
4491 r = KVM_SYNC_X86_VALID_FIELDS;
4493 case KVM_CAP_ADJUST_CLOCK:
4494 r = KVM_CLOCK_VALID_FLAGS;
4496 case KVM_CAP_X86_DISABLE_EXITS:
4497 r = KVM_X86_DISABLE_EXITS_PAUSE;
4499 if (!mitigate_smt_rsb) {
4500 r |= KVM_X86_DISABLE_EXITS_HLT |
4501 KVM_X86_DISABLE_EXITS_CSTATE;
4503 if (kvm_can_mwait_in_guest())
4504 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4507 case KVM_CAP_X86_SMM:
4508 if (!IS_ENABLED(CONFIG_KVM_SMM))
4511 /* SMBASE is usually relocated above 1M on modern chipsets,
4512 * and SMM handlers might indeed rely on 4G segment limits,
4513 * so do not report SMM to be available if real mode is
4514 * emulated via vm86 mode. Still, do not go to great lengths
4515 * to avoid userspace's usage of the feature, because it is a
4516 * fringe case that is not enabled except via specific settings
4517 * of the module parameters.
4519 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4521 case KVM_CAP_NR_VCPUS:
4522 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4524 case KVM_CAP_MAX_VCPUS:
4527 case KVM_CAP_MAX_VCPU_ID:
4528 r = KVM_MAX_VCPU_IDS;
4530 case KVM_CAP_PV_MMU: /* obsolete */
4534 r = KVM_MAX_MCE_BANKS;
4537 r = boot_cpu_has(X86_FEATURE_XSAVE);
4539 case KVM_CAP_TSC_CONTROL:
4540 case KVM_CAP_VM_TSC_CONTROL:
4541 r = kvm_caps.has_tsc_control;
4543 case KVM_CAP_X2APIC_API:
4544 r = KVM_X2APIC_API_VALID_FLAGS;
4546 case KVM_CAP_NESTED_STATE:
4547 r = kvm_x86_ops.nested_ops->get_state ?
4548 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4550 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4551 r = kvm_x86_ops.enable_l2_tlb_flush != NULL;
4553 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4554 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4556 case KVM_CAP_SMALLER_MAXPHYADDR:
4557 r = (int) allow_smaller_maxphyaddr;
4559 case KVM_CAP_STEAL_TIME:
4560 r = sched_info_on();
4562 case KVM_CAP_X86_BUS_LOCK_EXIT:
4563 if (kvm_caps.has_bus_lock_exit)
4564 r = KVM_BUS_LOCK_DETECTION_OFF |
4565 KVM_BUS_LOCK_DETECTION_EXIT;
4569 case KVM_CAP_XSAVE2: {
4570 u64 guest_perm = xstate_get_guest_group_perm();
4572 r = xstate_required_size(kvm_caps.supported_xcr0 & guest_perm, false);
4573 if (r < sizeof(struct kvm_xsave))
4574 r = sizeof(struct kvm_xsave);
4577 case KVM_CAP_PMU_CAPABILITY:
4578 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4580 case KVM_CAP_DISABLE_QUIRKS2:
4581 r = KVM_X86_VALID_QUIRKS;
4583 case KVM_CAP_X86_NOTIFY_VMEXIT:
4584 r = kvm_caps.has_notify_vmexit;
4592 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4594 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4596 if ((u64)(unsigned long)uaddr != attr->addr)
4597 return ERR_PTR_USR(-EFAULT);
4601 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4603 u64 __user *uaddr = kvm_get_attr_addr(attr);
4609 return PTR_ERR(uaddr);
4611 switch (attr->attr) {
4612 case KVM_X86_XCOMP_GUEST_SUPP:
4613 if (put_user(kvm_caps.supported_xcr0, uaddr))
4622 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4627 switch (attr->attr) {
4628 case KVM_X86_XCOMP_GUEST_SUPP:
4635 long kvm_arch_dev_ioctl(struct file *filp,
4636 unsigned int ioctl, unsigned long arg)
4638 void __user *argp = (void __user *)arg;
4642 case KVM_GET_MSR_INDEX_LIST: {
4643 struct kvm_msr_list __user *user_msr_list = argp;
4644 struct kvm_msr_list msr_list;
4648 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4651 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4652 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4655 if (n < msr_list.nmsrs)
4658 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4659 num_msrs_to_save * sizeof(u32)))
4661 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4663 num_emulated_msrs * sizeof(u32)))
4668 case KVM_GET_SUPPORTED_CPUID:
4669 case KVM_GET_EMULATED_CPUID: {
4670 struct kvm_cpuid2 __user *cpuid_arg = argp;
4671 struct kvm_cpuid2 cpuid;
4674 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4677 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4683 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4688 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4690 if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
4691 sizeof(kvm_caps.supported_mce_cap)))
4695 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4696 struct kvm_msr_list __user *user_msr_list = argp;
4697 struct kvm_msr_list msr_list;
4701 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4704 msr_list.nmsrs = num_msr_based_features;
4705 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4708 if (n < msr_list.nmsrs)
4711 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4712 num_msr_based_features * sizeof(u32)))
4718 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4720 case KVM_GET_SUPPORTED_HV_CPUID:
4721 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4723 case KVM_GET_DEVICE_ATTR: {
4724 struct kvm_device_attr attr;
4726 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4728 r = kvm_x86_dev_get_attr(&attr);
4731 case KVM_HAS_DEVICE_ATTR: {
4732 struct kvm_device_attr attr;
4734 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4736 r = kvm_x86_dev_has_attr(&attr);
4747 static void wbinvd_ipi(void *garbage)
4752 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4754 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4757 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4759 /* Address WBINVD may be executed by guest */
4760 if (need_emulate_wbinvd(vcpu)) {
4761 if (static_call(kvm_x86_has_wbinvd_exit)())
4762 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4763 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4764 smp_call_function_single(vcpu->cpu,
4765 wbinvd_ipi, NULL, 1);
4768 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4770 /* Save host pkru register if supported */
4771 vcpu->arch.host_pkru = read_pkru();
4773 /* Apply any externally detected TSC adjustments (due to suspend) */
4774 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4775 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4776 vcpu->arch.tsc_offset_adjustment = 0;
4777 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4780 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4781 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4782 rdtsc() - vcpu->arch.last_host_tsc;
4784 mark_tsc_unstable("KVM discovered backwards TSC");
4786 if (kvm_check_tsc_unstable()) {
4787 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4788 vcpu->arch.last_guest_tsc);
4789 kvm_vcpu_write_tsc_offset(vcpu, offset);
4790 vcpu->arch.tsc_catchup = 1;
4793 if (kvm_lapic_hv_timer_in_use(vcpu))
4794 kvm_lapic_restart_hv_timer(vcpu);
4797 * On a host with synchronized TSC, there is no need to update
4798 * kvmclock on vcpu->cpu migration
4800 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4801 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4802 if (vcpu->cpu != cpu)
4803 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4807 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4810 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4812 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4813 struct kvm_steal_time __user *st;
4814 struct kvm_memslots *slots;
4815 static const u8 preempted = KVM_VCPU_PREEMPTED;
4816 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
4819 * The vCPU can be marked preempted if and only if the VM-Exit was on
4820 * an instruction boundary and will not trigger guest emulation of any
4821 * kind (see vcpu_run). Vendor specific code controls (conservatively)
4822 * when this is true, for example allowing the vCPU to be marked
4823 * preempted if and only if the VM-Exit was due to a host interrupt.
4825 if (!vcpu->arch.at_instruction_boundary) {
4826 vcpu->stat.preemption_other++;
4830 vcpu->stat.preemption_reported++;
4831 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4834 if (vcpu->arch.st.preempted)
4837 /* This happens on process exit */
4838 if (unlikely(current->mm != vcpu->kvm->mm))
4841 slots = kvm_memslots(vcpu->kvm);
4843 if (unlikely(slots->generation != ghc->generation ||
4845 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4848 st = (struct kvm_steal_time __user *)ghc->hva;
4849 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4851 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4852 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4854 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4857 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4861 if (vcpu->preempted) {
4862 if (!vcpu->arch.guest_state_protected)
4863 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4866 * Take the srcu lock as memslots will be accessed to check the gfn
4867 * cache generation against the memslots generation.
4869 idx = srcu_read_lock(&vcpu->kvm->srcu);
4870 if (kvm_xen_msr_enabled(vcpu->kvm))
4871 kvm_xen_runstate_set_preempted(vcpu);
4873 kvm_steal_time_set_preempted(vcpu);
4874 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4877 static_call(kvm_x86_vcpu_put)(vcpu);
4878 vcpu->arch.last_host_tsc = rdtsc();
4881 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4882 struct kvm_lapic_state *s)
4884 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4886 return kvm_apic_get_state(vcpu, s);
4889 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4890 struct kvm_lapic_state *s)
4894 r = kvm_apic_set_state(vcpu, s);
4897 update_cr8_intercept(vcpu);
4902 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4905 * We can accept userspace's request for interrupt injection
4906 * as long as we have a place to store the interrupt number.
4907 * The actual injection will happen when the CPU is able to
4908 * deliver the interrupt.
4910 if (kvm_cpu_has_extint(vcpu))
4913 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4914 return (!lapic_in_kernel(vcpu) ||
4915 kvm_apic_accept_pic_intr(vcpu));
4918 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4921 * Do not cause an interrupt window exit if an exception
4922 * is pending or an event needs reinjection; userspace
4923 * might want to inject the interrupt manually using KVM_SET_REGS
4924 * or KVM_SET_SREGS. For that to work, we must be at an
4925 * instruction boundary and with no events half-injected.
4927 return (kvm_arch_interrupt_allowed(vcpu) &&
4928 kvm_cpu_accept_dm_intr(vcpu) &&
4929 !kvm_event_needs_reinjection(vcpu) &&
4930 !kvm_is_exception_pending(vcpu));
4933 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4934 struct kvm_interrupt *irq)
4936 if (irq->irq >= KVM_NR_INTERRUPTS)
4939 if (!irqchip_in_kernel(vcpu->kvm)) {
4940 kvm_queue_interrupt(vcpu, irq->irq, false);
4941 kvm_make_request(KVM_REQ_EVENT, vcpu);
4946 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4947 * fail for in-kernel 8259.
4949 if (pic_in_kernel(vcpu->kvm))
4952 if (vcpu->arch.pending_external_vector != -1)
4955 vcpu->arch.pending_external_vector = irq->irq;
4956 kvm_make_request(KVM_REQ_EVENT, vcpu);
4960 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4962 kvm_inject_nmi(vcpu);
4967 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4968 struct kvm_tpr_access_ctl *tac)
4972 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4976 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4980 unsigned bank_num = mcg_cap & 0xff, bank;
4983 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4985 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
4988 vcpu->arch.mcg_cap = mcg_cap;
4989 /* Init IA32_MCG_CTL to all 1s */
4990 if (mcg_cap & MCG_CTL_P)
4991 vcpu->arch.mcg_ctl = ~(u64)0;
4992 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
4993 for (bank = 0; bank < bank_num; bank++) {
4994 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4995 if (mcg_cap & MCG_CMCI_P)
4996 vcpu->arch.mci_ctl2_banks[bank] = 0;
4999 kvm_apic_after_set_mcg_cap(vcpu);
5001 static_call(kvm_x86_setup_mce)(vcpu);
5007 * Validate this is an UCNA (uncorrectable no action) error by checking the
5008 * MCG_STATUS and MCi_STATUS registers:
5009 * - none of the bits for Machine Check Exceptions are set
5010 * - both the VAL (valid) and UC (uncorrectable) bits are set
5011 * MCI_STATUS_PCC - Processor Context Corrupted
5012 * MCI_STATUS_S - Signaled as a Machine Check Exception
5013 * MCI_STATUS_AR - Software recoverable Action Required
5015 static bool is_ucna(struct kvm_x86_mce *mce)
5017 return !mce->mcg_status &&
5018 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) &&
5019 (mce->status & MCI_STATUS_VAL) &&
5020 (mce->status & MCI_STATUS_UC);
5023 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks)
5025 u64 mcg_cap = vcpu->arch.mcg_cap;
5027 banks[1] = mce->status;
5028 banks[2] = mce->addr;
5029 banks[3] = mce->misc;
5030 vcpu->arch.mcg_status = mce->mcg_status;
5032 if (!(mcg_cap & MCG_CMCI_P) ||
5033 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
5036 if (lapic_in_kernel(vcpu))
5037 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);
5042 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
5043 struct kvm_x86_mce *mce)
5045 u64 mcg_cap = vcpu->arch.mcg_cap;
5046 unsigned bank_num = mcg_cap & 0xff;
5047 u64 *banks = vcpu->arch.mce_banks;
5049 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
5052 banks += array_index_nospec(4 * mce->bank, 4 * bank_num);
5055 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks);
5058 * if IA32_MCG_CTL is not all 1s, the uncorrected error
5059 * reporting is disabled
5061 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
5062 vcpu->arch.mcg_ctl != ~(u64)0)
5065 * if IA32_MCi_CTL is not all 1s, the uncorrected error
5066 * reporting is disabled for the bank
5068 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
5070 if (mce->status & MCI_STATUS_UC) {
5071 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
5072 !kvm_is_cr4_bit_set(vcpu, X86_CR4_MCE)) {
5073 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5076 if (banks[1] & MCI_STATUS_VAL)
5077 mce->status |= MCI_STATUS_OVER;
5078 banks[2] = mce->addr;
5079 banks[3] = mce->misc;
5080 vcpu->arch.mcg_status = mce->mcg_status;
5081 banks[1] = mce->status;
5082 kvm_queue_exception(vcpu, MC_VECTOR);
5083 } else if (!(banks[1] & MCI_STATUS_VAL)
5084 || !(banks[1] & MCI_STATUS_UC)) {
5085 if (banks[1] & MCI_STATUS_VAL)
5086 mce->status |= MCI_STATUS_OVER;
5087 banks[2] = mce->addr;
5088 banks[3] = mce->misc;
5089 banks[1] = mce->status;
5091 banks[1] |= MCI_STATUS_OVER;
5095 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
5096 struct kvm_vcpu_events *events)
5098 struct kvm_queued_exception *ex;
5102 #ifdef CONFIG_KVM_SMM
5103 if (kvm_check_request(KVM_REQ_SMI, vcpu))
5108 * KVM's ABI only allows for one exception to be migrated. Luckily,
5109 * the only time there can be two queued exceptions is if there's a
5110 * non-exiting _injected_ exception, and a pending exiting exception.
5111 * In that case, ignore the VM-Exiting exception as it's an extension
5112 * of the injected exception.
5114 if (vcpu->arch.exception_vmexit.pending &&
5115 !vcpu->arch.exception.pending &&
5116 !vcpu->arch.exception.injected)
5117 ex = &vcpu->arch.exception_vmexit;
5119 ex = &vcpu->arch.exception;
5122 * In guest mode, payload delivery should be deferred if the exception
5123 * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1
5124 * intercepts #PF, ditto for DR6 and #DBs. If the per-VM capability,
5125 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not
5126 * propagate the payload and so it cannot be safely deferred. Deliver
5127 * the payload if the capability hasn't been requested.
5129 if (!vcpu->kvm->arch.exception_payload_enabled &&
5130 ex->pending && ex->has_payload)
5131 kvm_deliver_exception_payload(vcpu, ex);
5133 memset(events, 0, sizeof(*events));
5136 * The API doesn't provide the instruction length for software
5137 * exceptions, so don't report them. As long as the guest RIP
5138 * isn't advanced, we should expect to encounter the exception
5141 if (!kvm_exception_is_soft(ex->vector)) {
5142 events->exception.injected = ex->injected;
5143 events->exception.pending = ex->pending;
5145 * For ABI compatibility, deliberately conflate
5146 * pending and injected exceptions when
5147 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
5149 if (!vcpu->kvm->arch.exception_payload_enabled)
5150 events->exception.injected |= ex->pending;
5152 events->exception.nr = ex->vector;
5153 events->exception.has_error_code = ex->has_error_code;
5154 events->exception.error_code = ex->error_code;
5155 events->exception_has_payload = ex->has_payload;
5156 events->exception_payload = ex->payload;
5158 events->interrupt.injected =
5159 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
5160 events->interrupt.nr = vcpu->arch.interrupt.nr;
5161 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
5163 events->nmi.injected = vcpu->arch.nmi_injected;
5164 events->nmi.pending = vcpu->arch.nmi_pending != 0;
5165 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
5167 /* events->sipi_vector is never valid when reporting to user space */
5169 #ifdef CONFIG_KVM_SMM
5170 events->smi.smm = is_smm(vcpu);
5171 events->smi.pending = vcpu->arch.smi_pending;
5172 events->smi.smm_inside_nmi =
5173 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
5175 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
5177 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
5178 | KVM_VCPUEVENT_VALID_SHADOW
5179 | KVM_VCPUEVENT_VALID_SMM);
5180 if (vcpu->kvm->arch.exception_payload_enabled)
5181 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5182 if (vcpu->kvm->arch.triple_fault_event) {
5183 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5184 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5188 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
5189 struct kvm_vcpu_events *events)
5191 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
5192 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
5193 | KVM_VCPUEVENT_VALID_SHADOW
5194 | KVM_VCPUEVENT_VALID_SMM
5195 | KVM_VCPUEVENT_VALID_PAYLOAD
5196 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
5199 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5200 if (!vcpu->kvm->arch.exception_payload_enabled)
5202 if (events->exception.pending)
5203 events->exception.injected = 0;
5205 events->exception_has_payload = 0;
5207 events->exception.pending = 0;
5208 events->exception_has_payload = 0;
5211 if ((events->exception.injected || events->exception.pending) &&
5212 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
5215 /* INITs are latched while in SMM */
5216 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
5217 (events->smi.smm || events->smi.pending) &&
5218 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
5224 * Flag that userspace is stuffing an exception, the next KVM_RUN will
5225 * morph the exception to a VM-Exit if appropriate. Do this only for
5226 * pending exceptions, already-injected exceptions are not subject to
5227 * intercpetion. Note, userspace that conflates pending and injected
5228 * is hosed, and will incorrectly convert an injected exception into a
5229 * pending exception, which in turn may cause a spurious VM-Exit.
5231 vcpu->arch.exception_from_userspace = events->exception.pending;
5233 vcpu->arch.exception_vmexit.pending = false;
5235 vcpu->arch.exception.injected = events->exception.injected;
5236 vcpu->arch.exception.pending = events->exception.pending;
5237 vcpu->arch.exception.vector = events->exception.nr;
5238 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
5239 vcpu->arch.exception.error_code = events->exception.error_code;
5240 vcpu->arch.exception.has_payload = events->exception_has_payload;
5241 vcpu->arch.exception.payload = events->exception_payload;
5243 vcpu->arch.interrupt.injected = events->interrupt.injected;
5244 vcpu->arch.interrupt.nr = events->interrupt.nr;
5245 vcpu->arch.interrupt.soft = events->interrupt.soft;
5246 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
5247 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
5248 events->interrupt.shadow);
5250 vcpu->arch.nmi_injected = events->nmi.injected;
5251 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
5252 vcpu->arch.nmi_pending = events->nmi.pending;
5253 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
5255 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
5256 lapic_in_kernel(vcpu))
5257 vcpu->arch.apic->sipi_vector = events->sipi_vector;
5259 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
5260 #ifdef CONFIG_KVM_SMM
5261 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
5262 kvm_leave_nested(vcpu);
5263 kvm_smm_changed(vcpu, events->smi.smm);
5266 vcpu->arch.smi_pending = events->smi.pending;
5268 if (events->smi.smm) {
5269 if (events->smi.smm_inside_nmi)
5270 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
5272 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
5276 if (events->smi.smm || events->smi.pending ||
5277 events->smi.smm_inside_nmi)
5281 if (lapic_in_kernel(vcpu)) {
5282 if (events->smi.latched_init)
5283 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5285 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5289 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5290 if (!vcpu->kvm->arch.triple_fault_event)
5292 if (events->triple_fault.pending)
5293 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5295 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5298 kvm_make_request(KVM_REQ_EVENT, vcpu);
5303 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
5304 struct kvm_debugregs *dbgregs)
5308 memset(dbgregs, 0, sizeof(*dbgregs));
5309 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5310 kvm_get_dr(vcpu, 6, &val);
5312 dbgregs->dr7 = vcpu->arch.dr7;
5315 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5316 struct kvm_debugregs *dbgregs)
5321 if (!kvm_dr6_valid(dbgregs->dr6))
5323 if (!kvm_dr7_valid(dbgregs->dr7))
5326 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5327 kvm_update_dr0123(vcpu);
5328 vcpu->arch.dr6 = dbgregs->dr6;
5329 vcpu->arch.dr7 = dbgregs->dr7;
5330 kvm_update_dr7(vcpu);
5335 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5336 struct kvm_xsave *guest_xsave)
5338 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5341 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5342 guest_xsave->region,
5343 sizeof(guest_xsave->region),
5347 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5348 u8 *state, unsigned int size)
5350 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5353 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5354 state, size, vcpu->arch.pkru);
5357 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5358 struct kvm_xsave *guest_xsave)
5360 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5363 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5364 guest_xsave->region,
5365 kvm_caps.supported_xcr0,
5369 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5370 struct kvm_xcrs *guest_xcrs)
5372 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5373 guest_xcrs->nr_xcrs = 0;
5377 guest_xcrs->nr_xcrs = 1;
5378 guest_xcrs->flags = 0;
5379 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5380 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5383 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5384 struct kvm_xcrs *guest_xcrs)
5388 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5391 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5394 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5395 /* Only support XCR0 currently */
5396 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5397 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5398 guest_xcrs->xcrs[i].value);
5407 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5408 * stopped by the hypervisor. This function will be called from the host only.
5409 * EINVAL is returned when the host attempts to set the flag for a guest that
5410 * does not support pv clocks.
5412 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5414 if (!vcpu->arch.pv_time.active)
5416 vcpu->arch.pvclock_set_guest_stopped_request = true;
5417 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5421 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5422 struct kvm_device_attr *attr)
5426 switch (attr->attr) {
5427 case KVM_VCPU_TSC_OFFSET:
5437 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5438 struct kvm_device_attr *attr)
5440 u64 __user *uaddr = kvm_get_attr_addr(attr);
5444 return PTR_ERR(uaddr);
5446 switch (attr->attr) {
5447 case KVM_VCPU_TSC_OFFSET:
5449 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5460 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5461 struct kvm_device_attr *attr)
5463 u64 __user *uaddr = kvm_get_attr_addr(attr);
5464 struct kvm *kvm = vcpu->kvm;
5468 return PTR_ERR(uaddr);
5470 switch (attr->attr) {
5471 case KVM_VCPU_TSC_OFFSET: {
5472 u64 offset, tsc, ns;
5473 unsigned long flags;
5477 if (get_user(offset, uaddr))
5480 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5482 matched = (vcpu->arch.virtual_tsc_khz &&
5483 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5484 kvm->arch.last_tsc_offset == offset);
5486 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5487 ns = get_kvmclock_base_ns();
5489 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5490 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5502 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5506 struct kvm_device_attr attr;
5509 if (copy_from_user(&attr, argp, sizeof(attr)))
5512 if (attr.group != KVM_VCPU_TSC_CTRL)
5516 case KVM_HAS_DEVICE_ATTR:
5517 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5519 case KVM_GET_DEVICE_ATTR:
5520 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5522 case KVM_SET_DEVICE_ATTR:
5523 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5530 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5531 struct kvm_enable_cap *cap)
5534 uint16_t vmcs_version;
5535 void __user *user_ptr;
5541 case KVM_CAP_HYPERV_SYNIC2:
5546 case KVM_CAP_HYPERV_SYNIC:
5547 if (!irqchip_in_kernel(vcpu->kvm))
5549 return kvm_hv_activate_synic(vcpu, cap->cap ==
5550 KVM_CAP_HYPERV_SYNIC2);
5551 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5552 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5554 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5556 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5557 if (copy_to_user(user_ptr, &vmcs_version,
5558 sizeof(vmcs_version)))
5562 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5563 if (!kvm_x86_ops.enable_l2_tlb_flush)
5566 return static_call(kvm_x86_enable_l2_tlb_flush)(vcpu);
5568 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5569 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5571 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5572 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5573 if (vcpu->arch.pv_cpuid.enforce)
5574 kvm_update_pv_runtime(vcpu);
5582 long kvm_arch_vcpu_ioctl(struct file *filp,
5583 unsigned int ioctl, unsigned long arg)
5585 struct kvm_vcpu *vcpu = filp->private_data;
5586 void __user *argp = (void __user *)arg;
5589 struct kvm_sregs2 *sregs2;
5590 struct kvm_lapic_state *lapic;
5591 struct kvm_xsave *xsave;
5592 struct kvm_xcrs *xcrs;
5600 case KVM_GET_LAPIC: {
5602 if (!lapic_in_kernel(vcpu))
5604 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5605 GFP_KERNEL_ACCOUNT);
5610 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5614 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5619 case KVM_SET_LAPIC: {
5621 if (!lapic_in_kernel(vcpu))
5623 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5624 if (IS_ERR(u.lapic)) {
5625 r = PTR_ERR(u.lapic);
5629 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5632 case KVM_INTERRUPT: {
5633 struct kvm_interrupt irq;
5636 if (copy_from_user(&irq, argp, sizeof(irq)))
5638 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5642 r = kvm_vcpu_ioctl_nmi(vcpu);
5646 r = kvm_inject_smi(vcpu);
5649 case KVM_SET_CPUID: {
5650 struct kvm_cpuid __user *cpuid_arg = argp;
5651 struct kvm_cpuid cpuid;
5654 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5656 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5659 case KVM_SET_CPUID2: {
5660 struct kvm_cpuid2 __user *cpuid_arg = argp;
5661 struct kvm_cpuid2 cpuid;
5664 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5666 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5667 cpuid_arg->entries);
5670 case KVM_GET_CPUID2: {
5671 struct kvm_cpuid2 __user *cpuid_arg = argp;
5672 struct kvm_cpuid2 cpuid;
5675 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5677 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5678 cpuid_arg->entries);
5682 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5687 case KVM_GET_MSRS: {
5688 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5689 r = msr_io(vcpu, argp, do_get_msr, 1);
5690 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5693 case KVM_SET_MSRS: {
5694 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5695 r = msr_io(vcpu, argp, do_set_msr, 0);
5696 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5699 case KVM_TPR_ACCESS_REPORTING: {
5700 struct kvm_tpr_access_ctl tac;
5703 if (copy_from_user(&tac, argp, sizeof(tac)))
5705 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5709 if (copy_to_user(argp, &tac, sizeof(tac)))
5714 case KVM_SET_VAPIC_ADDR: {
5715 struct kvm_vapic_addr va;
5719 if (!lapic_in_kernel(vcpu))
5722 if (copy_from_user(&va, argp, sizeof(va)))
5724 idx = srcu_read_lock(&vcpu->kvm->srcu);
5725 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5726 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5729 case KVM_X86_SETUP_MCE: {
5733 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5735 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5738 case KVM_X86_SET_MCE: {
5739 struct kvm_x86_mce mce;
5742 if (copy_from_user(&mce, argp, sizeof(mce)))
5744 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5747 case KVM_GET_VCPU_EVENTS: {
5748 struct kvm_vcpu_events events;
5750 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5753 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5758 case KVM_SET_VCPU_EVENTS: {
5759 struct kvm_vcpu_events events;
5762 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5765 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5768 case KVM_GET_DEBUGREGS: {
5769 struct kvm_debugregs dbgregs;
5771 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5774 if (copy_to_user(argp, &dbgregs,
5775 sizeof(struct kvm_debugregs)))
5780 case KVM_SET_DEBUGREGS: {
5781 struct kvm_debugregs dbgregs;
5784 if (copy_from_user(&dbgregs, argp,
5785 sizeof(struct kvm_debugregs)))
5788 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5791 case KVM_GET_XSAVE: {
5793 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5796 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5801 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5804 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5809 case KVM_SET_XSAVE: {
5810 int size = vcpu->arch.guest_fpu.uabi_size;
5812 u.xsave = memdup_user(argp, size);
5813 if (IS_ERR(u.xsave)) {
5814 r = PTR_ERR(u.xsave);
5818 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5822 case KVM_GET_XSAVE2: {
5823 int size = vcpu->arch.guest_fpu.uabi_size;
5825 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5830 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5833 if (copy_to_user(argp, u.xsave, size))
5840 case KVM_GET_XCRS: {
5841 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5846 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5849 if (copy_to_user(argp, u.xcrs,
5850 sizeof(struct kvm_xcrs)))
5855 case KVM_SET_XCRS: {
5856 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5857 if (IS_ERR(u.xcrs)) {
5858 r = PTR_ERR(u.xcrs);
5862 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5865 case KVM_SET_TSC_KHZ: {
5869 user_tsc_khz = (u32)arg;
5871 if (kvm_caps.has_tsc_control &&
5872 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
5875 if (user_tsc_khz == 0)
5876 user_tsc_khz = tsc_khz;
5878 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5883 case KVM_GET_TSC_KHZ: {
5884 r = vcpu->arch.virtual_tsc_khz;
5887 case KVM_KVMCLOCK_CTRL: {
5888 r = kvm_set_guest_paused(vcpu);
5891 case KVM_ENABLE_CAP: {
5892 struct kvm_enable_cap cap;
5895 if (copy_from_user(&cap, argp, sizeof(cap)))
5897 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5900 case KVM_GET_NESTED_STATE: {
5901 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5905 if (!kvm_x86_ops.nested_ops->get_state)
5908 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5910 if (get_user(user_data_size, &user_kvm_nested_state->size))
5913 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5918 if (r > user_data_size) {
5919 if (put_user(r, &user_kvm_nested_state->size))
5929 case KVM_SET_NESTED_STATE: {
5930 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5931 struct kvm_nested_state kvm_state;
5935 if (!kvm_x86_ops.nested_ops->set_state)
5939 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5943 if (kvm_state.size < sizeof(kvm_state))
5946 if (kvm_state.flags &
5947 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5948 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5949 | KVM_STATE_NESTED_GIF_SET))
5952 /* nested_run_pending implies guest_mode. */
5953 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5954 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5957 idx = srcu_read_lock(&vcpu->kvm->srcu);
5958 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5959 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5962 case KVM_GET_SUPPORTED_HV_CPUID:
5963 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5965 #ifdef CONFIG_KVM_XEN
5966 case KVM_XEN_VCPU_GET_ATTR: {
5967 struct kvm_xen_vcpu_attr xva;
5970 if (copy_from_user(&xva, argp, sizeof(xva)))
5972 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
5973 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
5977 case KVM_XEN_VCPU_SET_ATTR: {
5978 struct kvm_xen_vcpu_attr xva;
5981 if (copy_from_user(&xva, argp, sizeof(xva)))
5983 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
5987 case KVM_GET_SREGS2: {
5988 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
5992 __get_sregs2(vcpu, u.sregs2);
5994 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
5999 case KVM_SET_SREGS2: {
6000 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
6001 if (IS_ERR(u.sregs2)) {
6002 r = PTR_ERR(u.sregs2);
6006 r = __set_sregs2(vcpu, u.sregs2);
6009 case KVM_HAS_DEVICE_ATTR:
6010 case KVM_GET_DEVICE_ATTR:
6011 case KVM_SET_DEVICE_ATTR:
6012 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
6024 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
6026 return VM_FAULT_SIGBUS;
6029 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
6033 if (addr > (unsigned int)(-3 * PAGE_SIZE))
6035 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
6039 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
6042 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
6045 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
6046 unsigned long kvm_nr_mmu_pages)
6048 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
6051 mutex_lock(&kvm->slots_lock);
6053 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
6054 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
6056 mutex_unlock(&kvm->slots_lock);
6060 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6062 struct kvm_pic *pic = kvm->arch.vpic;
6066 switch (chip->chip_id) {
6067 case KVM_IRQCHIP_PIC_MASTER:
6068 memcpy(&chip->chip.pic, &pic->pics[0],
6069 sizeof(struct kvm_pic_state));
6071 case KVM_IRQCHIP_PIC_SLAVE:
6072 memcpy(&chip->chip.pic, &pic->pics[1],
6073 sizeof(struct kvm_pic_state));
6075 case KVM_IRQCHIP_IOAPIC:
6076 kvm_get_ioapic(kvm, &chip->chip.ioapic);
6085 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6087 struct kvm_pic *pic = kvm->arch.vpic;
6091 switch (chip->chip_id) {
6092 case KVM_IRQCHIP_PIC_MASTER:
6093 spin_lock(&pic->lock);
6094 memcpy(&pic->pics[0], &chip->chip.pic,
6095 sizeof(struct kvm_pic_state));
6096 spin_unlock(&pic->lock);
6098 case KVM_IRQCHIP_PIC_SLAVE:
6099 spin_lock(&pic->lock);
6100 memcpy(&pic->pics[1], &chip->chip.pic,
6101 sizeof(struct kvm_pic_state));
6102 spin_unlock(&pic->lock);
6104 case KVM_IRQCHIP_IOAPIC:
6105 kvm_set_ioapic(kvm, &chip->chip.ioapic);
6111 kvm_pic_update_irq(pic);
6115 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6117 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
6119 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
6121 mutex_lock(&kps->lock);
6122 memcpy(ps, &kps->channels, sizeof(*ps));
6123 mutex_unlock(&kps->lock);
6127 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6130 struct kvm_pit *pit = kvm->arch.vpit;
6132 mutex_lock(&pit->pit_state.lock);
6133 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
6134 for (i = 0; i < 3; i++)
6135 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
6136 mutex_unlock(&pit->pit_state.lock);
6140 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6142 mutex_lock(&kvm->arch.vpit->pit_state.lock);
6143 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
6144 sizeof(ps->channels));
6145 ps->flags = kvm->arch.vpit->pit_state.flags;
6146 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
6147 memset(&ps->reserved, 0, sizeof(ps->reserved));
6151 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6155 u32 prev_legacy, cur_legacy;
6156 struct kvm_pit *pit = kvm->arch.vpit;
6158 mutex_lock(&pit->pit_state.lock);
6159 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
6160 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
6161 if (!prev_legacy && cur_legacy)
6163 memcpy(&pit->pit_state.channels, &ps->channels,
6164 sizeof(pit->pit_state.channels));
6165 pit->pit_state.flags = ps->flags;
6166 for (i = 0; i < 3; i++)
6167 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
6169 mutex_unlock(&pit->pit_state.lock);
6173 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
6174 struct kvm_reinject_control *control)
6176 struct kvm_pit *pit = kvm->arch.vpit;
6178 /* pit->pit_state.lock was overloaded to prevent userspace from getting
6179 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
6180 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
6182 mutex_lock(&pit->pit_state.lock);
6183 kvm_pit_set_reinject(pit, control->pit_reinject);
6184 mutex_unlock(&pit->pit_state.lock);
6189 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
6193 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
6194 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
6195 * on all VM-Exits, thus we only need to kick running vCPUs to force a
6198 struct kvm_vcpu *vcpu;
6201 kvm_for_each_vcpu(i, vcpu, kvm)
6202 kvm_vcpu_kick(vcpu);
6205 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
6208 if (!irqchip_in_kernel(kvm))
6211 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
6212 irq_event->irq, irq_event->level,
6217 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
6218 struct kvm_enable_cap *cap)
6226 case KVM_CAP_DISABLE_QUIRKS2:
6228 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
6231 case KVM_CAP_DISABLE_QUIRKS:
6232 kvm->arch.disabled_quirks = cap->args[0];
6235 case KVM_CAP_SPLIT_IRQCHIP: {
6236 mutex_lock(&kvm->lock);
6238 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
6239 goto split_irqchip_unlock;
6241 if (irqchip_in_kernel(kvm))
6242 goto split_irqchip_unlock;
6243 if (kvm->created_vcpus)
6244 goto split_irqchip_unlock;
6245 r = kvm_setup_empty_irq_routing(kvm);
6247 goto split_irqchip_unlock;
6248 /* Pairs with irqchip_in_kernel. */
6250 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
6251 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
6252 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6254 split_irqchip_unlock:
6255 mutex_unlock(&kvm->lock);
6258 case KVM_CAP_X2APIC_API:
6260 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
6263 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
6264 kvm->arch.x2apic_format = true;
6265 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
6266 kvm->arch.x2apic_broadcast_quirk_disabled = true;
6270 case KVM_CAP_X86_DISABLE_EXITS:
6272 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
6275 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
6276 kvm->arch.pause_in_guest = true;
6278 #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \
6279 "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests."
6281 if (!mitigate_smt_rsb) {
6282 if (boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible() &&
6283 (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE))
6284 pr_warn_once(SMT_RSB_MSG);
6286 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
6287 kvm_can_mwait_in_guest())
6288 kvm->arch.mwait_in_guest = true;
6289 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
6290 kvm->arch.hlt_in_guest = true;
6291 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
6292 kvm->arch.cstate_in_guest = true;
6297 case KVM_CAP_MSR_PLATFORM_INFO:
6298 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
6301 case KVM_CAP_EXCEPTION_PAYLOAD:
6302 kvm->arch.exception_payload_enabled = cap->args[0];
6305 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
6306 kvm->arch.triple_fault_event = cap->args[0];
6309 case KVM_CAP_X86_USER_SPACE_MSR:
6311 if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK)
6313 kvm->arch.user_space_msr_mask = cap->args[0];
6316 case KVM_CAP_X86_BUS_LOCK_EXIT:
6318 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6321 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6322 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6325 if (kvm_caps.has_bus_lock_exit &&
6326 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6327 kvm->arch.bus_lock_detection_enabled = true;
6330 #ifdef CONFIG_X86_SGX_KVM
6331 case KVM_CAP_SGX_ATTRIBUTE: {
6332 unsigned long allowed_attributes = 0;
6334 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6338 /* KVM only supports the PROVISIONKEY privileged attribute. */
6339 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6340 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6341 kvm->arch.sgx_provisioning_allowed = true;
6347 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6349 if (!kvm_x86_ops.vm_copy_enc_context_from)
6352 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6354 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6356 if (!kvm_x86_ops.vm_move_enc_context_from)
6359 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6361 case KVM_CAP_EXIT_HYPERCALL:
6362 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6366 kvm->arch.hypercall_exit_enabled = cap->args[0];
6369 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6371 if (cap->args[0] & ~1)
6373 kvm->arch.exit_on_emulation_error = cap->args[0];
6376 case KVM_CAP_PMU_CAPABILITY:
6378 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6381 mutex_lock(&kvm->lock);
6382 if (!kvm->created_vcpus) {
6383 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6386 mutex_unlock(&kvm->lock);
6388 case KVM_CAP_MAX_VCPU_ID:
6390 if (cap->args[0] > KVM_MAX_VCPU_IDS)
6393 mutex_lock(&kvm->lock);
6394 if (kvm->arch.max_vcpu_ids == cap->args[0]) {
6396 } else if (!kvm->arch.max_vcpu_ids) {
6397 kvm->arch.max_vcpu_ids = cap->args[0];
6400 mutex_unlock(&kvm->lock);
6402 case KVM_CAP_X86_NOTIFY_VMEXIT:
6404 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
6406 if (!kvm_caps.has_notify_vmexit)
6408 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
6410 mutex_lock(&kvm->lock);
6411 if (!kvm->created_vcpus) {
6412 kvm->arch.notify_window = cap->args[0] >> 32;
6413 kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
6416 mutex_unlock(&kvm->lock);
6418 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
6422 * Since the risk of disabling NX hugepages is a guest crashing
6423 * the system, ensure the userspace process has permission to
6424 * reboot the system.
6426 * Note that unlike the reboot() syscall, the process must have
6427 * this capability in the root namespace because exposing
6428 * /dev/kvm into a container does not limit the scope of the
6429 * iTLB multihit bug to that container. In other words,
6430 * this must use capable(), not ns_capable().
6432 if (!capable(CAP_SYS_BOOT)) {
6440 mutex_lock(&kvm->lock);
6441 if (!kvm->created_vcpus) {
6442 kvm->arch.disable_nx_huge_pages = true;
6445 mutex_unlock(&kvm->lock);
6454 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6456 struct kvm_x86_msr_filter *msr_filter;
6458 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6462 msr_filter->default_allow = default_allow;
6466 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6473 for (i = 0; i < msr_filter->count; i++)
6474 kfree(msr_filter->ranges[i].bitmap);
6479 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6480 struct kvm_msr_filter_range *user_range)
6482 unsigned long *bitmap = NULL;
6485 if (!user_range->nmsrs)
6488 if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK)
6491 if (!user_range->flags)
6494 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6495 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6498 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6500 return PTR_ERR(bitmap);
6502 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6503 .flags = user_range->flags,
6504 .base = user_range->base,
6505 .nmsrs = user_range->nmsrs,
6509 msr_filter->count++;
6513 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm,
6514 struct kvm_msr_filter *filter)
6516 struct kvm_x86_msr_filter *new_filter, *old_filter;
6522 if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK)
6525 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++)
6526 empty &= !filter->ranges[i].nmsrs;
6528 default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY);
6529 if (empty && !default_allow)
6532 new_filter = kvm_alloc_msr_filter(default_allow);
6536 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) {
6537 r = kvm_add_msr_filter(new_filter, &filter->ranges[i]);
6539 kvm_free_msr_filter(new_filter);
6544 mutex_lock(&kvm->lock);
6545 old_filter = rcu_replace_pointer(kvm->arch.msr_filter, new_filter,
6546 mutex_is_locked(&kvm->lock));
6547 mutex_unlock(&kvm->lock);
6548 synchronize_srcu(&kvm->srcu);
6550 kvm_free_msr_filter(old_filter);
6552 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6557 #ifdef CONFIG_KVM_COMPAT
6558 /* for KVM_X86_SET_MSR_FILTER */
6559 struct kvm_msr_filter_range_compat {
6566 struct kvm_msr_filter_compat {
6568 struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES];
6571 #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat)
6573 long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl,
6576 void __user *argp = (void __user *)arg;
6577 struct kvm *kvm = filp->private_data;
6581 case KVM_X86_SET_MSR_FILTER_COMPAT: {
6582 struct kvm_msr_filter __user *user_msr_filter = argp;
6583 struct kvm_msr_filter_compat filter_compat;
6584 struct kvm_msr_filter filter;
6587 if (copy_from_user(&filter_compat, user_msr_filter,
6588 sizeof(filter_compat)))
6591 filter.flags = filter_compat.flags;
6592 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6593 struct kvm_msr_filter_range_compat *cr;
6595 cr = &filter_compat.ranges[i];
6596 filter.ranges[i] = (struct kvm_msr_filter_range) {
6600 .bitmap = (__u8 *)(ulong)cr->bitmap,
6604 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
6613 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6614 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6616 struct kvm_vcpu *vcpu;
6620 mutex_lock(&kvm->lock);
6621 kvm_for_each_vcpu(i, vcpu, kvm) {
6622 if (!vcpu->arch.pv_time.active)
6625 ret = kvm_set_guest_paused(vcpu);
6627 kvm_err("Failed to pause guest VCPU%d: %d\n",
6628 vcpu->vcpu_id, ret);
6632 mutex_unlock(&kvm->lock);
6634 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6637 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6640 case PM_HIBERNATION_PREPARE:
6641 case PM_SUSPEND_PREPARE:
6642 return kvm_arch_suspend_notifier(kvm);
6647 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6649 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6651 struct kvm_clock_data data = { 0 };
6653 get_kvmclock(kvm, &data);
6654 if (copy_to_user(argp, &data, sizeof(data)))
6660 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6662 struct kvm_arch *ka = &kvm->arch;
6663 struct kvm_clock_data data;
6666 if (copy_from_user(&data, argp, sizeof(data)))
6670 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6671 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6673 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6676 kvm_hv_request_tsc_page_update(kvm);
6677 kvm_start_pvclock_update(kvm);
6678 pvclock_update_vm_gtod_copy(kvm);
6681 * This pairs with kvm_guest_time_update(): when masterclock is
6682 * in use, we use master_kernel_ns + kvmclock_offset to set
6683 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6684 * is slightly ahead) here we risk going negative on unsigned
6685 * 'system_time' when 'data.clock' is very small.
6687 if (data.flags & KVM_CLOCK_REALTIME) {
6688 u64 now_real_ns = ktime_get_real_ns();
6691 * Avoid stepping the kvmclock backwards.
6693 if (now_real_ns > data.realtime)
6694 data.clock += now_real_ns - data.realtime;
6697 if (ka->use_master_clock)
6698 now_raw_ns = ka->master_kernel_ns;
6700 now_raw_ns = get_kvmclock_base_ns();
6701 ka->kvmclock_offset = data.clock - now_raw_ns;
6702 kvm_end_pvclock_update(kvm);
6706 int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
6708 struct kvm *kvm = filp->private_data;
6709 void __user *argp = (void __user *)arg;
6712 * This union makes it completely explicit to gcc-3.x
6713 * that these two variables' stack usage should be
6714 * combined, not added together.
6717 struct kvm_pit_state ps;
6718 struct kvm_pit_state2 ps2;
6719 struct kvm_pit_config pit_config;
6723 case KVM_SET_TSS_ADDR:
6724 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6726 case KVM_SET_IDENTITY_MAP_ADDR: {
6729 mutex_lock(&kvm->lock);
6731 if (kvm->created_vcpus)
6732 goto set_identity_unlock;
6734 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6735 goto set_identity_unlock;
6736 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6737 set_identity_unlock:
6738 mutex_unlock(&kvm->lock);
6741 case KVM_SET_NR_MMU_PAGES:
6742 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6744 case KVM_CREATE_IRQCHIP: {
6745 mutex_lock(&kvm->lock);
6748 if (irqchip_in_kernel(kvm))
6749 goto create_irqchip_unlock;
6752 if (kvm->created_vcpus)
6753 goto create_irqchip_unlock;
6755 r = kvm_pic_init(kvm);
6757 goto create_irqchip_unlock;
6759 r = kvm_ioapic_init(kvm);
6761 kvm_pic_destroy(kvm);
6762 goto create_irqchip_unlock;
6765 r = kvm_setup_default_irq_routing(kvm);
6767 kvm_ioapic_destroy(kvm);
6768 kvm_pic_destroy(kvm);
6769 goto create_irqchip_unlock;
6771 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6773 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6774 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6775 create_irqchip_unlock:
6776 mutex_unlock(&kvm->lock);
6779 case KVM_CREATE_PIT:
6780 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6782 case KVM_CREATE_PIT2:
6784 if (copy_from_user(&u.pit_config, argp,
6785 sizeof(struct kvm_pit_config)))
6788 mutex_lock(&kvm->lock);
6791 goto create_pit_unlock;
6793 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6797 mutex_unlock(&kvm->lock);
6799 case KVM_GET_IRQCHIP: {
6800 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6801 struct kvm_irqchip *chip;
6803 chip = memdup_user(argp, sizeof(*chip));
6810 if (!irqchip_kernel(kvm))
6811 goto get_irqchip_out;
6812 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6814 goto get_irqchip_out;
6816 if (copy_to_user(argp, chip, sizeof(*chip)))
6817 goto get_irqchip_out;
6823 case KVM_SET_IRQCHIP: {
6824 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6825 struct kvm_irqchip *chip;
6827 chip = memdup_user(argp, sizeof(*chip));
6834 if (!irqchip_kernel(kvm))
6835 goto set_irqchip_out;
6836 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6843 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6846 if (!kvm->arch.vpit)
6848 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6852 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6859 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6861 mutex_lock(&kvm->lock);
6863 if (!kvm->arch.vpit)
6865 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6867 mutex_unlock(&kvm->lock);
6870 case KVM_GET_PIT2: {
6872 if (!kvm->arch.vpit)
6874 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6878 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6883 case KVM_SET_PIT2: {
6885 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6887 mutex_lock(&kvm->lock);
6889 if (!kvm->arch.vpit)
6891 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6893 mutex_unlock(&kvm->lock);
6896 case KVM_REINJECT_CONTROL: {
6897 struct kvm_reinject_control control;
6899 if (copy_from_user(&control, argp, sizeof(control)))
6902 if (!kvm->arch.vpit)
6904 r = kvm_vm_ioctl_reinject(kvm, &control);
6907 case KVM_SET_BOOT_CPU_ID:
6909 mutex_lock(&kvm->lock);
6910 if (kvm->created_vcpus)
6913 kvm->arch.bsp_vcpu_id = arg;
6914 mutex_unlock(&kvm->lock);
6916 #ifdef CONFIG_KVM_XEN
6917 case KVM_XEN_HVM_CONFIG: {
6918 struct kvm_xen_hvm_config xhc;
6920 if (copy_from_user(&xhc, argp, sizeof(xhc)))
6922 r = kvm_xen_hvm_config(kvm, &xhc);
6925 case KVM_XEN_HVM_GET_ATTR: {
6926 struct kvm_xen_hvm_attr xha;
6929 if (copy_from_user(&xha, argp, sizeof(xha)))
6931 r = kvm_xen_hvm_get_attr(kvm, &xha);
6932 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
6936 case KVM_XEN_HVM_SET_ATTR: {
6937 struct kvm_xen_hvm_attr xha;
6940 if (copy_from_user(&xha, argp, sizeof(xha)))
6942 r = kvm_xen_hvm_set_attr(kvm, &xha);
6945 case KVM_XEN_HVM_EVTCHN_SEND: {
6946 struct kvm_irq_routing_xen_evtchn uxe;
6949 if (copy_from_user(&uxe, argp, sizeof(uxe)))
6951 r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
6956 r = kvm_vm_ioctl_set_clock(kvm, argp);
6959 r = kvm_vm_ioctl_get_clock(kvm, argp);
6961 case KVM_SET_TSC_KHZ: {
6965 user_tsc_khz = (u32)arg;
6967 if (kvm_caps.has_tsc_control &&
6968 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
6971 if (user_tsc_khz == 0)
6972 user_tsc_khz = tsc_khz;
6974 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
6979 case KVM_GET_TSC_KHZ: {
6980 r = READ_ONCE(kvm->arch.default_tsc_khz);
6983 case KVM_MEMORY_ENCRYPT_OP: {
6985 if (!kvm_x86_ops.mem_enc_ioctl)
6988 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
6991 case KVM_MEMORY_ENCRYPT_REG_REGION: {
6992 struct kvm_enc_region region;
6995 if (copy_from_user(®ion, argp, sizeof(region)))
6999 if (!kvm_x86_ops.mem_enc_register_region)
7002 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
7005 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
7006 struct kvm_enc_region region;
7009 if (copy_from_user(®ion, argp, sizeof(region)))
7013 if (!kvm_x86_ops.mem_enc_unregister_region)
7016 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
7019 case KVM_HYPERV_EVENTFD: {
7020 struct kvm_hyperv_eventfd hvevfd;
7023 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
7025 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
7028 case KVM_SET_PMU_EVENT_FILTER:
7029 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
7031 case KVM_X86_SET_MSR_FILTER: {
7032 struct kvm_msr_filter __user *user_msr_filter = argp;
7033 struct kvm_msr_filter filter;
7035 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
7038 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
7048 static void kvm_probe_msr_to_save(u32 msr_index)
7052 if (rdmsr_safe(msr_index, &dummy[0], &dummy[1]))
7056 * Even MSRs that are valid in the host may not be exposed to guests in
7059 switch (msr_index) {
7060 case MSR_IA32_BNDCFGS:
7061 if (!kvm_mpx_supported())
7065 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
7066 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
7069 case MSR_IA32_UMWAIT_CONTROL:
7070 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
7073 case MSR_IA32_RTIT_CTL:
7074 case MSR_IA32_RTIT_STATUS:
7075 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
7078 case MSR_IA32_RTIT_CR3_MATCH:
7079 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7080 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
7083 case MSR_IA32_RTIT_OUTPUT_BASE:
7084 case MSR_IA32_RTIT_OUTPUT_MASK:
7085 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7086 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
7087 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
7090 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
7091 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7092 (msr_index - MSR_IA32_RTIT_ADDR0_A >=
7093 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2))
7096 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
7097 if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >=
7098 kvm_pmu_cap.num_counters_gp)
7101 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
7102 if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >=
7103 kvm_pmu_cap.num_counters_gp)
7106 case MSR_ARCH_PERFMON_FIXED_CTR0 ... MSR_ARCH_PERFMON_FIXED_CTR_MAX:
7107 if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >=
7108 kvm_pmu_cap.num_counters_fixed)
7112 case MSR_IA32_XFD_ERR:
7113 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
7120 msrs_to_save[num_msrs_to_save++] = msr_index;
7123 static void kvm_init_msr_list(void)
7127 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
7128 "Please update the fixed PMCs in msrs_to_save_pmu[]");
7130 num_msrs_to_save = 0;
7131 num_emulated_msrs = 0;
7132 num_msr_based_features = 0;
7134 for (i = 0; i < ARRAY_SIZE(msrs_to_save_base); i++)
7135 kvm_probe_msr_to_save(msrs_to_save_base[i]);
7138 for (i = 0; i < ARRAY_SIZE(msrs_to_save_pmu); i++)
7139 kvm_probe_msr_to_save(msrs_to_save_pmu[i]);
7142 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
7143 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
7146 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
7149 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
7150 struct kvm_msr_entry msr;
7152 msr.index = msr_based_features_all[i];
7153 if (kvm_get_msr_feature(&msr))
7156 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
7160 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
7168 if (!(lapic_in_kernel(vcpu) &&
7169 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
7170 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
7181 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
7188 if (!(lapic_in_kernel(vcpu) &&
7189 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
7191 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
7193 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
7203 void kvm_set_segment(struct kvm_vcpu *vcpu,
7204 struct kvm_segment *var, int seg)
7206 static_call(kvm_x86_set_segment)(vcpu, var, seg);
7209 void kvm_get_segment(struct kvm_vcpu *vcpu,
7210 struct kvm_segment *var, int seg)
7212 static_call(kvm_x86_get_segment)(vcpu, var, seg);
7215 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
7216 struct x86_exception *exception)
7218 struct kvm_mmu *mmu = vcpu->arch.mmu;
7221 BUG_ON(!mmu_is_nested(vcpu));
7223 /* NPT walks are always user-walks */
7224 access |= PFERR_USER_MASK;
7225 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
7230 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
7231 struct x86_exception *exception)
7233 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7235 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7236 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7238 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
7240 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
7241 struct x86_exception *exception)
7243 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7245 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7246 access |= PFERR_WRITE_MASK;
7247 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7249 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
7251 /* uses this to access any guest's mapped memory without checking CPL */
7252 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
7253 struct x86_exception *exception)
7255 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7257 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
7260 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7261 struct kvm_vcpu *vcpu, u64 access,
7262 struct x86_exception *exception)
7264 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7266 int r = X86EMUL_CONTINUE;
7269 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7270 unsigned offset = addr & (PAGE_SIZE-1);
7271 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
7274 if (gpa == INVALID_GPA)
7275 return X86EMUL_PROPAGATE_FAULT;
7276 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
7279 r = X86EMUL_IO_NEEDED;
7291 /* used for instruction fetching */
7292 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
7293 gva_t addr, void *val, unsigned int bytes,
7294 struct x86_exception *exception)
7296 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7297 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7298 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7302 /* Inline kvm_read_guest_virt_helper for speed. */
7303 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
7305 if (unlikely(gpa == INVALID_GPA))
7306 return X86EMUL_PROPAGATE_FAULT;
7308 offset = addr & (PAGE_SIZE-1);
7309 if (WARN_ON(offset + bytes > PAGE_SIZE))
7310 bytes = (unsigned)PAGE_SIZE - offset;
7311 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
7313 if (unlikely(ret < 0))
7314 return X86EMUL_IO_NEEDED;
7316 return X86EMUL_CONTINUE;
7319 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
7320 gva_t addr, void *val, unsigned int bytes,
7321 struct x86_exception *exception)
7323 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7326 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
7327 * is returned, but our callers are not ready for that and they blindly
7328 * call kvm_inject_page_fault. Ensure that they at least do not leak
7329 * uninitialized kernel stack memory into cr2 and error code.
7331 memset(exception, 0, sizeof(*exception));
7332 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
7335 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
7337 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
7338 gva_t addr, void *val, unsigned int bytes,
7339 struct x86_exception *exception, bool system)
7341 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7345 access |= PFERR_IMPLICIT_ACCESS;
7346 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7347 access |= PFERR_USER_MASK;
7349 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
7352 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7353 struct kvm_vcpu *vcpu, u64 access,
7354 struct x86_exception *exception)
7356 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7358 int r = X86EMUL_CONTINUE;
7361 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7362 unsigned offset = addr & (PAGE_SIZE-1);
7363 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
7366 if (gpa == INVALID_GPA)
7367 return X86EMUL_PROPAGATE_FAULT;
7368 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
7370 r = X86EMUL_IO_NEEDED;
7382 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
7383 unsigned int bytes, struct x86_exception *exception,
7386 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7387 u64 access = PFERR_WRITE_MASK;
7390 access |= PFERR_IMPLICIT_ACCESS;
7391 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7392 access |= PFERR_USER_MASK;
7394 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7398 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
7399 unsigned int bytes, struct x86_exception *exception)
7401 /* kvm_write_guest_virt_system can pull in tons of pages. */
7402 vcpu->arch.l1tf_flush_l1d = true;
7404 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7405 PFERR_WRITE_MASK, exception);
7407 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
7409 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
7410 void *insn, int insn_len)
7412 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
7416 int handle_ud(struct kvm_vcpu *vcpu)
7418 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
7419 int fep_flags = READ_ONCE(force_emulation_prefix);
7420 int emul_type = EMULTYPE_TRAP_UD;
7421 char sig[5]; /* ud2; .ascii "kvm" */
7422 struct x86_exception e;
7424 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
7428 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
7429 sig, sizeof(sig), &e) == 0 &&
7430 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
7431 if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF)
7432 kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF);
7433 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
7434 emul_type = EMULTYPE_TRAP_UD_FORCED;
7437 return kvm_emulate_instruction(vcpu, emul_type);
7439 EXPORT_SYMBOL_GPL(handle_ud);
7441 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7442 gpa_t gpa, bool write)
7444 /* For APIC access vmexit */
7445 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7448 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7449 trace_vcpu_match_mmio(gva, gpa, write, true);
7456 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7457 gpa_t *gpa, struct x86_exception *exception,
7460 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7461 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7462 | (write ? PFERR_WRITE_MASK : 0);
7465 * currently PKRU is only applied to ept enabled guest so
7466 * there is no pkey in EPT page table for L1 guest or EPT
7467 * shadow page table for L2 guest.
7469 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7470 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7471 vcpu->arch.mmio_access, 0, access))) {
7472 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7473 (gva & (PAGE_SIZE - 1));
7474 trace_vcpu_match_mmio(gva, *gpa, write, false);
7478 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7480 if (*gpa == INVALID_GPA)
7483 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7486 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7487 const void *val, int bytes)
7491 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7494 kvm_page_track_write(vcpu, gpa, val, bytes);
7498 struct read_write_emulator_ops {
7499 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7501 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7502 void *val, int bytes);
7503 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7504 int bytes, void *val);
7505 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7506 void *val, int bytes);
7510 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7512 if (vcpu->mmio_read_completed) {
7513 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7514 vcpu->mmio_fragments[0].gpa, val);
7515 vcpu->mmio_read_completed = 0;
7522 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7523 void *val, int bytes)
7525 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7528 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7529 void *val, int bytes)
7531 return emulator_write_phys(vcpu, gpa, val, bytes);
7534 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7536 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7537 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7540 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7541 void *val, int bytes)
7543 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7544 return X86EMUL_IO_NEEDED;
7547 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7548 void *val, int bytes)
7550 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7552 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7553 return X86EMUL_CONTINUE;
7556 static const struct read_write_emulator_ops read_emultor = {
7557 .read_write_prepare = read_prepare,
7558 .read_write_emulate = read_emulate,
7559 .read_write_mmio = vcpu_mmio_read,
7560 .read_write_exit_mmio = read_exit_mmio,
7563 static const struct read_write_emulator_ops write_emultor = {
7564 .read_write_emulate = write_emulate,
7565 .read_write_mmio = write_mmio,
7566 .read_write_exit_mmio = write_exit_mmio,
7570 static int emulator_read_write_onepage(unsigned long addr, void *val,
7572 struct x86_exception *exception,
7573 struct kvm_vcpu *vcpu,
7574 const struct read_write_emulator_ops *ops)
7578 bool write = ops->write;
7579 struct kvm_mmio_fragment *frag;
7580 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7583 * If the exit was due to a NPF we may already have a GPA.
7584 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7585 * Note, this cannot be used on string operations since string
7586 * operation using rep will only have the initial GPA from the NPF
7589 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7590 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7591 gpa = ctxt->gpa_val;
7592 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7594 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7596 return X86EMUL_PROPAGATE_FAULT;
7599 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7600 return X86EMUL_CONTINUE;
7603 * Is this MMIO handled locally?
7605 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7606 if (handled == bytes)
7607 return X86EMUL_CONTINUE;
7613 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7614 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7618 return X86EMUL_CONTINUE;
7621 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7623 void *val, unsigned int bytes,
7624 struct x86_exception *exception,
7625 const struct read_write_emulator_ops *ops)
7627 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7631 if (ops->read_write_prepare &&
7632 ops->read_write_prepare(vcpu, val, bytes))
7633 return X86EMUL_CONTINUE;
7635 vcpu->mmio_nr_fragments = 0;
7637 /* Crossing a page boundary? */
7638 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7641 now = -addr & ~PAGE_MASK;
7642 rc = emulator_read_write_onepage(addr, val, now, exception,
7645 if (rc != X86EMUL_CONTINUE)
7648 if (ctxt->mode != X86EMUL_MODE_PROT64)
7654 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7656 if (rc != X86EMUL_CONTINUE)
7659 if (!vcpu->mmio_nr_fragments)
7662 gpa = vcpu->mmio_fragments[0].gpa;
7664 vcpu->mmio_needed = 1;
7665 vcpu->mmio_cur_fragment = 0;
7667 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7668 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7669 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7670 vcpu->run->mmio.phys_addr = gpa;
7672 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7675 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7679 struct x86_exception *exception)
7681 return emulator_read_write(ctxt, addr, val, bytes,
7682 exception, &read_emultor);
7685 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7689 struct x86_exception *exception)
7691 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7692 exception, &write_emultor);
7695 #define emulator_try_cmpxchg_user(t, ptr, old, new) \
7696 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t))
7698 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7703 struct x86_exception *exception)
7705 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7711 /* guests cmpxchg8b have to be emulated atomically */
7712 if (bytes > 8 || (bytes & (bytes - 1)))
7715 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7717 if (gpa == INVALID_GPA ||
7718 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7722 * Emulate the atomic as a straight write to avoid #AC if SLD is
7723 * enabled in the host and the access splits a cache line.
7725 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7726 page_line_mask = ~(cache_line_size() - 1);
7728 page_line_mask = PAGE_MASK;
7730 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7733 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa));
7734 if (kvm_is_error_hva(hva))
7737 hva += offset_in_page(gpa);
7741 r = emulator_try_cmpxchg_user(u8, hva, old, new);
7744 r = emulator_try_cmpxchg_user(u16, hva, old, new);
7747 r = emulator_try_cmpxchg_user(u32, hva, old, new);
7750 r = emulator_try_cmpxchg_user(u64, hva, old, new);
7757 return X86EMUL_UNHANDLEABLE;
7759 return X86EMUL_CMPXCHG_FAILED;
7761 kvm_page_track_write(vcpu, gpa, new, bytes);
7763 return X86EMUL_CONTINUE;
7766 pr_warn_once("emulating exchange as write\n");
7768 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7771 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7772 unsigned short port, void *data,
7773 unsigned int count, bool in)
7778 WARN_ON_ONCE(vcpu->arch.pio.count);
7779 for (i = 0; i < count; i++) {
7781 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data);
7783 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data);
7790 * Userspace must have unregistered the device while PIO
7791 * was running. Drop writes / read as 0.
7794 memset(data, 0, size * (count - i));
7803 vcpu->arch.pio.port = port;
7804 vcpu->arch.pio.in = in;
7805 vcpu->arch.pio.count = count;
7806 vcpu->arch.pio.size = size;
7809 memset(vcpu->arch.pio_data, 0, size * count);
7811 memcpy(vcpu->arch.pio_data, data, size * count);
7813 vcpu->run->exit_reason = KVM_EXIT_IO;
7814 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7815 vcpu->run->io.size = size;
7816 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7817 vcpu->run->io.count = count;
7818 vcpu->run->io.port = port;
7822 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7823 unsigned short port, void *val, unsigned int count)
7825 int r = emulator_pio_in_out(vcpu, size, port, val, count, true);
7827 trace_kvm_pio(KVM_PIO_IN, port, size, count, val);
7832 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7834 int size = vcpu->arch.pio.size;
7835 unsigned int count = vcpu->arch.pio.count;
7836 memcpy(val, vcpu->arch.pio_data, size * count);
7837 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7838 vcpu->arch.pio.count = 0;
7841 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7842 int size, unsigned short port, void *val,
7845 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7846 if (vcpu->arch.pio.count) {
7848 * Complete a previous iteration that required userspace I/O.
7849 * Note, @count isn't guaranteed to match pio.count as userspace
7850 * can modify ECX before rerunning the vCPU. Ignore any such
7851 * shenanigans as KVM doesn't support modifying the rep count,
7852 * and the emulator ensures @count doesn't overflow the buffer.
7854 complete_emulator_pio_in(vcpu, val);
7858 return emulator_pio_in(vcpu, size, port, val, count);
7861 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7862 unsigned short port, const void *val,
7865 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val);
7866 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
7869 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7870 int size, unsigned short port,
7871 const void *val, unsigned int count)
7873 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7876 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7878 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7881 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7883 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7886 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7888 if (!need_emulate_wbinvd(vcpu))
7889 return X86EMUL_CONTINUE;
7891 if (static_call(kvm_x86_has_wbinvd_exit)()) {
7892 int cpu = get_cpu();
7894 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7895 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7896 wbinvd_ipi, NULL, 1);
7898 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7901 return X86EMUL_CONTINUE;
7904 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
7906 kvm_emulate_wbinvd_noskip(vcpu);
7907 return kvm_skip_emulated_instruction(vcpu);
7909 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
7913 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
7915 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
7918 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
7919 unsigned long *dest)
7921 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
7924 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
7925 unsigned long value)
7928 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
7931 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
7933 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
7936 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
7938 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7939 unsigned long value;
7943 value = kvm_read_cr0(vcpu);
7946 value = vcpu->arch.cr2;
7949 value = kvm_read_cr3(vcpu);
7952 value = kvm_read_cr4(vcpu);
7955 value = kvm_get_cr8(vcpu);
7958 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7965 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
7967 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7972 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
7975 vcpu->arch.cr2 = val;
7978 res = kvm_set_cr3(vcpu, val);
7981 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
7984 res = kvm_set_cr8(vcpu, val);
7987 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7994 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
7996 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
7999 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8001 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
8004 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8006 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
8009 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8011 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
8014 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8016 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
8019 static unsigned long emulator_get_cached_segment_base(
8020 struct x86_emulate_ctxt *ctxt, int seg)
8022 return get_segment_base(emul_to_vcpu(ctxt), seg);
8025 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
8026 struct desc_struct *desc, u32 *base3,
8029 struct kvm_segment var;
8031 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
8032 *selector = var.selector;
8035 memset(desc, 0, sizeof(*desc));
8043 set_desc_limit(desc, var.limit);
8044 set_desc_base(desc, (unsigned long)var.base);
8045 #ifdef CONFIG_X86_64
8047 *base3 = var.base >> 32;
8049 desc->type = var.type;
8051 desc->dpl = var.dpl;
8052 desc->p = var.present;
8053 desc->avl = var.avl;
8061 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
8062 struct desc_struct *desc, u32 base3,
8065 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8066 struct kvm_segment var;
8068 var.selector = selector;
8069 var.base = get_desc_base(desc);
8070 #ifdef CONFIG_X86_64
8071 var.base |= ((u64)base3) << 32;
8073 var.limit = get_desc_limit(desc);
8075 var.limit = (var.limit << 12) | 0xfff;
8076 var.type = desc->type;
8077 var.dpl = desc->dpl;
8082 var.avl = desc->avl;
8083 var.present = desc->p;
8084 var.unusable = !var.present;
8087 kvm_set_segment(vcpu, &var, seg);
8091 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8092 u32 msr_index, u64 *pdata)
8094 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8097 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
8099 return X86EMUL_UNHANDLEABLE;
8102 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
8103 complete_emulated_rdmsr, r))
8104 return X86EMUL_IO_NEEDED;
8106 trace_kvm_msr_read_ex(msr_index);
8107 return X86EMUL_PROPAGATE_FAULT;
8110 trace_kvm_msr_read(msr_index, *pdata);
8111 return X86EMUL_CONTINUE;
8114 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8115 u32 msr_index, u64 data)
8117 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8120 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
8122 return X86EMUL_UNHANDLEABLE;
8125 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
8126 complete_emulated_msr_access, r))
8127 return X86EMUL_IO_NEEDED;
8129 trace_kvm_msr_write_ex(msr_index, data);
8130 return X86EMUL_PROPAGATE_FAULT;
8133 trace_kvm_msr_write(msr_index, data);
8134 return X86EMUL_CONTINUE;
8137 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
8138 u32 msr_index, u64 *pdata)
8140 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
8143 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
8146 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
8151 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
8152 u32 pmc, u64 *pdata)
8154 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
8157 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
8159 emul_to_vcpu(ctxt)->arch.halt_request = 1;
8162 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8163 struct x86_instruction_info *info,
8164 enum x86_intercept_stage stage)
8166 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
8170 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
8171 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
8174 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
8177 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
8179 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
8182 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
8184 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
8187 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
8189 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
8192 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
8194 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
8197 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
8199 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
8202 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
8204 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
8207 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
8209 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
8212 static bool emulator_is_smm(struct x86_emulate_ctxt *ctxt)
8214 return is_smm(emul_to_vcpu(ctxt));
8217 static bool emulator_is_guest_mode(struct x86_emulate_ctxt *ctxt)
8219 return is_guest_mode(emul_to_vcpu(ctxt));
8222 #ifndef CONFIG_KVM_SMM
8223 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt)
8226 return X86EMUL_UNHANDLEABLE;
8230 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
8232 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
8235 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
8237 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
8240 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
8242 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
8244 if (!kvm->vm_bugged)
8248 static const struct x86_emulate_ops emulate_ops = {
8249 .vm_bugged = emulator_vm_bugged,
8250 .read_gpr = emulator_read_gpr,
8251 .write_gpr = emulator_write_gpr,
8252 .read_std = emulator_read_std,
8253 .write_std = emulator_write_std,
8254 .fetch = kvm_fetch_guest_virt,
8255 .read_emulated = emulator_read_emulated,
8256 .write_emulated = emulator_write_emulated,
8257 .cmpxchg_emulated = emulator_cmpxchg_emulated,
8258 .invlpg = emulator_invlpg,
8259 .pio_in_emulated = emulator_pio_in_emulated,
8260 .pio_out_emulated = emulator_pio_out_emulated,
8261 .get_segment = emulator_get_segment,
8262 .set_segment = emulator_set_segment,
8263 .get_cached_segment_base = emulator_get_cached_segment_base,
8264 .get_gdt = emulator_get_gdt,
8265 .get_idt = emulator_get_idt,
8266 .set_gdt = emulator_set_gdt,
8267 .set_idt = emulator_set_idt,
8268 .get_cr = emulator_get_cr,
8269 .set_cr = emulator_set_cr,
8270 .cpl = emulator_get_cpl,
8271 .get_dr = emulator_get_dr,
8272 .set_dr = emulator_set_dr,
8273 .set_msr_with_filter = emulator_set_msr_with_filter,
8274 .get_msr_with_filter = emulator_get_msr_with_filter,
8275 .get_msr = emulator_get_msr,
8276 .check_pmc = emulator_check_pmc,
8277 .read_pmc = emulator_read_pmc,
8278 .halt = emulator_halt,
8279 .wbinvd = emulator_wbinvd,
8280 .fix_hypercall = emulator_fix_hypercall,
8281 .intercept = emulator_intercept,
8282 .get_cpuid = emulator_get_cpuid,
8283 .guest_has_long_mode = emulator_guest_has_long_mode,
8284 .guest_has_movbe = emulator_guest_has_movbe,
8285 .guest_has_fxsr = emulator_guest_has_fxsr,
8286 .guest_has_rdpid = emulator_guest_has_rdpid,
8287 .set_nmi_mask = emulator_set_nmi_mask,
8288 .is_smm = emulator_is_smm,
8289 .is_guest_mode = emulator_is_guest_mode,
8290 .leave_smm = emulator_leave_smm,
8291 .triple_fault = emulator_triple_fault,
8292 .set_xcr = emulator_set_xcr,
8295 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
8297 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8299 * an sti; sti; sequence only disable interrupts for the first
8300 * instruction. So, if the last instruction, be it emulated or
8301 * not, left the system with the INT_STI flag enabled, it
8302 * means that the last instruction is an sti. We should not
8303 * leave the flag on in this case. The same goes for mov ss
8305 if (int_shadow & mask)
8307 if (unlikely(int_shadow || mask)) {
8308 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
8310 kvm_make_request(KVM_REQ_EVENT, vcpu);
8314 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
8316 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8318 if (ctxt->exception.vector == PF_VECTOR)
8319 kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
8320 else if (ctxt->exception.error_code_valid)
8321 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
8322 ctxt->exception.error_code);
8324 kvm_queue_exception(vcpu, ctxt->exception.vector);
8327 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
8329 struct x86_emulate_ctxt *ctxt;
8331 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
8333 pr_err("failed to allocate vcpu's emulator\n");
8338 ctxt->ops = &emulate_ops;
8339 vcpu->arch.emulate_ctxt = ctxt;
8344 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
8346 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8349 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
8351 ctxt->gpa_available = false;
8352 ctxt->eflags = kvm_get_rflags(vcpu);
8353 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
8355 ctxt->eip = kvm_rip_read(vcpu);
8356 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
8357 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
8358 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
8359 cs_db ? X86EMUL_MODE_PROT32 :
8360 X86EMUL_MODE_PROT16;
8361 ctxt->interruptibility = 0;
8362 ctxt->have_exception = false;
8363 ctxt->exception.vector = -1;
8364 ctxt->perm_ok = false;
8366 init_decode_cache(ctxt);
8367 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8370 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
8372 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8375 init_emulate_ctxt(vcpu);
8379 ctxt->_eip = ctxt->eip + inc_eip;
8380 ret = emulate_int_real(ctxt, irq);
8382 if (ret != X86EMUL_CONTINUE) {
8383 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8385 ctxt->eip = ctxt->_eip;
8386 kvm_rip_write(vcpu, ctxt->eip);
8387 kvm_set_rflags(vcpu, ctxt->eflags);
8390 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
8392 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8393 u8 ndata, u8 *insn_bytes, u8 insn_size)
8395 struct kvm_run *run = vcpu->run;
8400 * Zero the whole array used to retrieve the exit info, as casting to
8401 * u32 for select entries will leave some chunks uninitialized.
8403 memset(&info, 0, sizeof(info));
8405 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
8406 &info[2], (u32 *)&info[3],
8409 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8410 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
8413 * There's currently space for 13 entries, but 5 are used for the exit
8414 * reason and info. Restrict to 4 to reduce the maintenance burden
8415 * when expanding kvm_run.emulation_failure in the future.
8417 if (WARN_ON_ONCE(ndata > 4))
8420 /* Always include the flags as a 'data' entry. */
8422 run->emulation_failure.flags = 0;
8425 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8426 sizeof(run->emulation_failure.insn_bytes) != 16));
8428 run->emulation_failure.flags |=
8429 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8430 run->emulation_failure.insn_size = insn_size;
8431 memset(run->emulation_failure.insn_bytes, 0x90,
8432 sizeof(run->emulation_failure.insn_bytes));
8433 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8436 memcpy(&run->internal.data[info_start], info, sizeof(info));
8437 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8438 ndata * sizeof(data[0]));
8440 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8443 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8445 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8447 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8448 ctxt->fetch.end - ctxt->fetch.data);
8451 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8454 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8456 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8458 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8460 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8462 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8464 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8466 struct kvm *kvm = vcpu->kvm;
8468 ++vcpu->stat.insn_emulation_fail;
8469 trace_kvm_emulate_insn_failed(vcpu);
8471 if (emulation_type & EMULTYPE_VMWARE_GP) {
8472 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8476 if (kvm->arch.exit_on_emulation_error ||
8477 (emulation_type & EMULTYPE_SKIP)) {
8478 prepare_emulation_ctxt_failure_exit(vcpu);
8482 kvm_queue_exception(vcpu, UD_VECTOR);
8484 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8485 prepare_emulation_ctxt_failure_exit(vcpu);
8492 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8495 gpa_t gpa = cr2_or_gpa;
8498 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8501 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8502 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8505 if (!vcpu->arch.mmu->root_role.direct) {
8507 * Write permission should be allowed since only
8508 * write access need to be emulated.
8510 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8513 * If the mapping is invalid in guest, let cpu retry
8514 * it to generate fault.
8516 if (gpa == INVALID_GPA)
8521 * Do not retry the unhandleable instruction if it faults on the
8522 * readonly host memory, otherwise it will goto a infinite loop:
8523 * retry instruction -> write #PF -> emulation fail -> retry
8524 * instruction -> ...
8526 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8529 * If the instruction failed on the error pfn, it can not be fixed,
8530 * report the error to userspace.
8532 if (is_error_noslot_pfn(pfn))
8535 kvm_release_pfn_clean(pfn);
8537 /* The instructions are well-emulated on direct mmu. */
8538 if (vcpu->arch.mmu->root_role.direct) {
8539 unsigned int indirect_shadow_pages;
8541 write_lock(&vcpu->kvm->mmu_lock);
8542 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8543 write_unlock(&vcpu->kvm->mmu_lock);
8545 if (indirect_shadow_pages)
8546 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8552 * if emulation was due to access to shadowed page table
8553 * and it failed try to unshadow page and re-enter the
8554 * guest to let CPU execute the instruction.
8556 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8559 * If the access faults on its page table, it can not
8560 * be fixed by unprotecting shadow page and it should
8561 * be reported to userspace.
8563 return !(emulation_type & EMULTYPE_WRITE_PF_TO_SP);
8566 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8567 gpa_t cr2_or_gpa, int emulation_type)
8569 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8570 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8572 last_retry_eip = vcpu->arch.last_retry_eip;
8573 last_retry_addr = vcpu->arch.last_retry_addr;
8576 * If the emulation is caused by #PF and it is non-page_table
8577 * writing instruction, it means the VM-EXIT is caused by shadow
8578 * page protected, we can zap the shadow page and retry this
8579 * instruction directly.
8581 * Note: if the guest uses a non-page-table modifying instruction
8582 * on the PDE that points to the instruction, then we will unmap
8583 * the instruction and go to an infinite loop. So, we cache the
8584 * last retried eip and the last fault address, if we meet the eip
8585 * and the address again, we can break out of the potential infinite
8588 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8590 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8593 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8594 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8597 if (x86_page_table_writing_insn(ctxt))
8600 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8603 vcpu->arch.last_retry_eip = ctxt->eip;
8604 vcpu->arch.last_retry_addr = cr2_or_gpa;
8606 if (!vcpu->arch.mmu->root_role.direct)
8607 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8609 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8614 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8615 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8617 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8626 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8627 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8632 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8634 struct kvm_run *kvm_run = vcpu->run;
8636 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8637 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8638 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8639 kvm_run->debug.arch.exception = DB_VECTOR;
8640 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8643 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8647 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8649 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8652 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8656 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8659 * rflags is the old, "raw" value of the flags. The new value has
8660 * not been saved yet.
8662 * This is correct even for TF set by the guest, because "the
8663 * processor will not generate this exception after the instruction
8664 * that sets the TF flag".
8666 if (unlikely(rflags & X86_EFLAGS_TF))
8667 r = kvm_vcpu_do_singlestep(vcpu);
8670 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8672 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
8676 if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
8680 * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
8681 * but AMD CPUs do not. MOV/POP SS blocking is rare, check that first
8682 * to avoid the relatively expensive CPUID lookup.
8684 shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8685 return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
8686 guest_cpuid_is_intel(vcpu);
8689 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,
8690 int emulation_type, int *r)
8692 WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE);
8695 * Do not check for code breakpoints if hardware has already done the
8696 * checks, as inferred from the emulation type. On NO_DECODE and SKIP,
8697 * the instruction has passed all exception checks, and all intercepted
8698 * exceptions that trigger emulation have lower priority than code
8699 * breakpoints, i.e. the fact that the intercepted exception occurred
8700 * means any code breakpoints have already been serviced.
8702 * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as
8703 * hardware has checked the RIP of the magic prefix, but not the RIP of
8704 * the instruction being emulated. The intent of forced emulation is
8705 * to behave as if KVM intercepted the instruction without an exception
8706 * and without a prefix.
8708 if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
8709 EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF))
8712 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8713 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8714 struct kvm_run *kvm_run = vcpu->run;
8715 unsigned long eip = kvm_get_linear_rip(vcpu);
8716 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8717 vcpu->arch.guest_debug_dr7,
8721 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8722 kvm_run->debug.arch.pc = eip;
8723 kvm_run->debug.arch.exception = DB_VECTOR;
8724 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8730 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8731 !kvm_is_code_breakpoint_inhibited(vcpu)) {
8732 unsigned long eip = kvm_get_linear_rip(vcpu);
8733 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8738 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8747 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8749 switch (ctxt->opcode_len) {
8756 case 0xe6: /* OUT */
8760 case 0x6c: /* INS */
8762 case 0x6e: /* OUTS */
8769 case 0x33: /* RDPMC */
8779 * Decode an instruction for emulation. The caller is responsible for handling
8780 * code breakpoints. Note, manually detecting code breakpoints is unnecessary
8781 * (and wrong) when emulating on an intercepted fault-like exception[*], as
8782 * code breakpoints have higher priority and thus have already been done by
8785 * [*] Except #MC, which is higher priority, but KVM should never emulate in
8786 * response to a machine check.
8788 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8789 void *insn, int insn_len)
8791 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8794 init_emulate_ctxt(vcpu);
8796 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8798 trace_kvm_emulate_insn_start(vcpu);
8799 ++vcpu->stat.insn_emulation;
8803 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8805 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8806 int emulation_type, void *insn, int insn_len)
8809 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8810 bool writeback = true;
8812 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8815 vcpu->arch.l1tf_flush_l1d = true;
8817 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8818 kvm_clear_exception_queue(vcpu);
8821 * Return immediately if RIP hits a code breakpoint, such #DBs
8822 * are fault-like and are higher priority than any faults on
8823 * the code fetch itself.
8825 if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r))
8828 r = x86_decode_emulated_instruction(vcpu, emulation_type,
8830 if (r != EMULATION_OK) {
8831 if ((emulation_type & EMULTYPE_TRAP_UD) ||
8832 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8833 kvm_queue_exception(vcpu, UD_VECTOR);
8836 if (reexecute_instruction(vcpu, cr2_or_gpa,
8840 if (ctxt->have_exception &&
8841 !(emulation_type & EMULTYPE_SKIP)) {
8843 * #UD should result in just EMULATION_FAILED, and trap-like
8844 * exception should not be encountered during decode.
8846 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8847 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8848 inject_emulated_exception(vcpu);
8851 return handle_emulation_failure(vcpu, emulation_type);
8855 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8856 !is_vmware_backdoor_opcode(ctxt)) {
8857 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8862 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8863 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8864 * The caller is responsible for updating interruptibility state and
8865 * injecting single-step #DBs.
8867 if (emulation_type & EMULTYPE_SKIP) {
8868 if (ctxt->mode != X86EMUL_MODE_PROT64)
8869 ctxt->eip = (u32)ctxt->_eip;
8871 ctxt->eip = ctxt->_eip;
8873 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8878 kvm_rip_write(vcpu, ctxt->eip);
8879 if (ctxt->eflags & X86_EFLAGS_RF)
8880 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8884 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8887 /* this is needed for vmware backdoor interface to work since it
8888 changes registers values during IO operation */
8889 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8890 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8891 emulator_invalidate_register_cache(ctxt);
8895 if (emulation_type & EMULTYPE_PF) {
8896 /* Save the faulting GPA (cr2) in the address field */
8897 ctxt->exception.address = cr2_or_gpa;
8899 /* With shadow page tables, cr2 contains a GVA or nGPA. */
8900 if (vcpu->arch.mmu->root_role.direct) {
8901 ctxt->gpa_available = true;
8902 ctxt->gpa_val = cr2_or_gpa;
8905 /* Sanitize the address out of an abundance of paranoia. */
8906 ctxt->exception.address = 0;
8909 r = x86_emulate_insn(ctxt);
8911 if (r == EMULATION_INTERCEPTED)
8914 if (r == EMULATION_FAILED) {
8915 if (reexecute_instruction(vcpu, cr2_or_gpa, emulation_type))
8918 return handle_emulation_failure(vcpu, emulation_type);
8921 if (ctxt->have_exception) {
8923 inject_emulated_exception(vcpu);
8924 } else if (vcpu->arch.pio.count) {
8925 if (!vcpu->arch.pio.in) {
8926 /* FIXME: return into emulator if single-stepping. */
8927 vcpu->arch.pio.count = 0;
8930 vcpu->arch.complete_userspace_io = complete_emulated_pio;
8933 } else if (vcpu->mmio_needed) {
8934 ++vcpu->stat.mmio_exits;
8936 if (!vcpu->mmio_is_write)
8939 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8940 } else if (vcpu->arch.complete_userspace_io) {
8943 } else if (r == EMULATION_RESTART)
8950 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8951 toggle_interruptibility(vcpu, ctxt->interruptibility);
8952 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8955 * Note, EXCPT_DB is assumed to be fault-like as the emulator
8956 * only supports code breakpoints and general detect #DB, both
8957 * of which are fault-like.
8959 if (!ctxt->have_exception ||
8960 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
8961 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8962 if (ctxt->is_branch)
8963 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
8964 kvm_rip_write(vcpu, ctxt->eip);
8965 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
8966 r = kvm_vcpu_do_singlestep(vcpu);
8967 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
8968 __kvm_set_rflags(vcpu, ctxt->eflags);
8972 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
8973 * do nothing, and it will be requested again as soon as
8974 * the shadow expires. But we still need to check here,
8975 * because POPF has no interrupt shadow.
8977 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
8978 kvm_make_request(KVM_REQ_EVENT, vcpu);
8980 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
8985 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
8987 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
8989 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
8991 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
8992 void *insn, int insn_len)
8994 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
8996 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
8998 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
9000 vcpu->arch.pio.count = 0;
9004 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
9006 vcpu->arch.pio.count = 0;
9008 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
9011 return kvm_skip_emulated_instruction(vcpu);
9014 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
9015 unsigned short port)
9017 unsigned long val = kvm_rax_read(vcpu);
9018 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
9024 * Workaround userspace that relies on old KVM behavior of %rip being
9025 * incremented prior to exiting to userspace to handle "OUT 0x7e".
9028 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
9029 vcpu->arch.complete_userspace_io =
9030 complete_fast_pio_out_port_0x7e;
9031 kvm_skip_emulated_instruction(vcpu);
9033 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9034 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
9039 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
9043 /* We should only ever be called with arch.pio.count equal to 1 */
9044 BUG_ON(vcpu->arch.pio.count != 1);
9046 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
9047 vcpu->arch.pio.count = 0;
9051 /* For size less than 4 we merge, else we zero extend */
9052 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
9054 complete_emulator_pio_in(vcpu, &val);
9055 kvm_rax_write(vcpu, val);
9057 return kvm_skip_emulated_instruction(vcpu);
9060 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
9061 unsigned short port)
9066 /* For size less than 4 we merge, else we zero extend */
9067 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
9069 ret = emulator_pio_in(vcpu, size, port, &val, 1);
9071 kvm_rax_write(vcpu, val);
9075 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9076 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
9081 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
9086 ret = kvm_fast_pio_in(vcpu, size, port);
9088 ret = kvm_fast_pio_out(vcpu, size, port);
9089 return ret && kvm_skip_emulated_instruction(vcpu);
9091 EXPORT_SYMBOL_GPL(kvm_fast_pio);
9093 static int kvmclock_cpu_down_prep(unsigned int cpu)
9095 __this_cpu_write(cpu_tsc_khz, 0);
9099 static void tsc_khz_changed(void *data)
9101 struct cpufreq_freqs *freq = data;
9102 unsigned long khz = 0;
9104 WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC));
9109 khz = cpufreq_quick_get(raw_smp_processor_id());
9112 __this_cpu_write(cpu_tsc_khz, khz);
9115 #ifdef CONFIG_X86_64
9116 static void kvm_hyperv_tsc_notifier(void)
9121 mutex_lock(&kvm_lock);
9122 list_for_each_entry(kvm, &vm_list, vm_list)
9123 kvm_make_mclock_inprogress_request(kvm);
9125 /* no guest entries from this point */
9126 hyperv_stop_tsc_emulation();
9128 /* TSC frequency always matches when on Hyper-V */
9129 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9130 for_each_present_cpu(cpu)
9131 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
9133 kvm_caps.max_guest_tsc_khz = tsc_khz;
9135 list_for_each_entry(kvm, &vm_list, vm_list) {
9136 __kvm_start_pvclock_update(kvm);
9137 pvclock_update_vm_gtod_copy(kvm);
9138 kvm_end_pvclock_update(kvm);
9141 mutex_unlock(&kvm_lock);
9145 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
9148 struct kvm_vcpu *vcpu;
9153 * We allow guests to temporarily run on slowing clocks,
9154 * provided we notify them after, or to run on accelerating
9155 * clocks, provided we notify them before. Thus time never
9158 * However, we have a problem. We can't atomically update
9159 * the frequency of a given CPU from this function; it is
9160 * merely a notifier, which can be called from any CPU.
9161 * Changing the TSC frequency at arbitrary points in time
9162 * requires a recomputation of local variables related to
9163 * the TSC for each VCPU. We must flag these local variables
9164 * to be updated and be sure the update takes place with the
9165 * new frequency before any guests proceed.
9167 * Unfortunately, the combination of hotplug CPU and frequency
9168 * change creates an intractable locking scenario; the order
9169 * of when these callouts happen is undefined with respect to
9170 * CPU hotplug, and they can race with each other. As such,
9171 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
9172 * undefined; you can actually have a CPU frequency change take
9173 * place in between the computation of X and the setting of the
9174 * variable. To protect against this problem, all updates of
9175 * the per_cpu tsc_khz variable are done in an interrupt
9176 * protected IPI, and all callers wishing to update the value
9177 * must wait for a synchronous IPI to complete (which is trivial
9178 * if the caller is on the CPU already). This establishes the
9179 * necessary total order on variable updates.
9181 * Note that because a guest time update may take place
9182 * anytime after the setting of the VCPU's request bit, the
9183 * correct TSC value must be set before the request. However,
9184 * to ensure the update actually makes it to any guest which
9185 * starts running in hardware virtualization between the set
9186 * and the acquisition of the spinlock, we must also ping the
9187 * CPU after setting the request bit.
9191 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9193 mutex_lock(&kvm_lock);
9194 list_for_each_entry(kvm, &vm_list, vm_list) {
9195 kvm_for_each_vcpu(i, vcpu, kvm) {
9196 if (vcpu->cpu != cpu)
9198 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9199 if (vcpu->cpu != raw_smp_processor_id())
9203 mutex_unlock(&kvm_lock);
9205 if (freq->old < freq->new && send_ipi) {
9207 * We upscale the frequency. Must make the guest
9208 * doesn't see old kvmclock values while running with
9209 * the new frequency, otherwise we risk the guest sees
9210 * time go backwards.
9212 * In case we update the frequency for another cpu
9213 * (which might be in guest context) send an interrupt
9214 * to kick the cpu out of guest context. Next time
9215 * guest context is entered kvmclock will be updated,
9216 * so the guest will not see stale values.
9218 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9222 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
9225 struct cpufreq_freqs *freq = data;
9228 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
9230 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
9233 for_each_cpu(cpu, freq->policy->cpus)
9234 __kvmclock_cpufreq_notifier(freq, cpu);
9239 static struct notifier_block kvmclock_cpufreq_notifier_block = {
9240 .notifier_call = kvmclock_cpufreq_notifier
9243 static int kvmclock_cpu_online(unsigned int cpu)
9245 tsc_khz_changed(NULL);
9249 static void kvm_timer_init(void)
9251 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9252 max_tsc_khz = tsc_khz;
9254 if (IS_ENABLED(CONFIG_CPU_FREQ)) {
9255 struct cpufreq_policy *policy;
9259 policy = cpufreq_cpu_get(cpu);
9261 if (policy->cpuinfo.max_freq)
9262 max_tsc_khz = policy->cpuinfo.max_freq;
9263 cpufreq_cpu_put(policy);
9267 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
9268 CPUFREQ_TRANSITION_NOTIFIER);
9270 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
9271 kvmclock_cpu_online, kvmclock_cpu_down_prep);
9275 #ifdef CONFIG_X86_64
9276 static void pvclock_gtod_update_fn(struct work_struct *work)
9279 struct kvm_vcpu *vcpu;
9282 mutex_lock(&kvm_lock);
9283 list_for_each_entry(kvm, &vm_list, vm_list)
9284 kvm_for_each_vcpu(i, vcpu, kvm)
9285 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9286 atomic_set(&kvm_guest_has_master_clock, 0);
9287 mutex_unlock(&kvm_lock);
9290 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
9293 * Indirection to move queue_work() out of the tk_core.seq write held
9294 * region to prevent possible deadlocks against time accessors which
9295 * are invoked with work related locks held.
9297 static void pvclock_irq_work_fn(struct irq_work *w)
9299 queue_work(system_long_wq, &pvclock_gtod_work);
9302 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
9305 * Notification about pvclock gtod data update.
9307 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
9310 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
9311 struct timekeeper *tk = priv;
9313 update_pvclock_gtod(tk);
9316 * Disable master clock if host does not trust, or does not use,
9317 * TSC based clocksource. Delegate queue_work() to irq_work as
9318 * this is invoked with tk_core.seq write held.
9320 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
9321 atomic_read(&kvm_guest_has_master_clock) != 0)
9322 irq_work_queue(&pvclock_irq_work);
9326 static struct notifier_block pvclock_gtod_notifier = {
9327 .notifier_call = pvclock_gtod_notify,
9331 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
9333 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9335 #define __KVM_X86_OP(func) \
9336 static_call_update(kvm_x86_##func, kvm_x86_ops.func);
9337 #define KVM_X86_OP(func) \
9338 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func)
9339 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP
9340 #define KVM_X86_OP_OPTIONAL_RET0(func) \
9341 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \
9342 (void *)__static_call_return0);
9343 #include <asm/kvm-x86-ops.h>
9346 kvm_pmu_ops_update(ops->pmu_ops);
9349 static int kvm_x86_check_processor_compatibility(void)
9351 int cpu = smp_processor_id();
9352 struct cpuinfo_x86 *c = &cpu_data(cpu);
9355 * Compatibility checks are done when loading KVM and when enabling
9356 * hardware, e.g. during CPU hotplug, to ensure all online CPUs are
9357 * compatible, i.e. KVM should never perform a compatibility check on
9360 WARN_ON(!cpu_online(cpu));
9362 if (__cr4_reserved_bits(cpu_has, c) !=
9363 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9366 return static_call(kvm_x86_check_processor_compatibility)();
9369 static void kvm_x86_check_cpu_compat(void *ret)
9371 *(int *)ret = kvm_x86_check_processor_compatibility();
9374 static int __kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9379 if (kvm_x86_ops.hardware_enable) {
9380 pr_err("already loaded vendor module '%s'\n", kvm_x86_ops.name);
9385 * KVM explicitly assumes that the guest has an FPU and
9386 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
9387 * vCPU's FPU state as a fxregs_state struct.
9389 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
9390 pr_err("inadequate fpu\n");
9394 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9395 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
9400 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes
9401 * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something
9402 * other than WB. Note, EPT doesn't utilize the PAT, but don't bother
9403 * with an exception. PAT[0] is set to WB on RESET and also by the
9404 * kernel, i.e. failure indicates a kernel bug or broken firmware.
9406 if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) ||
9407 (host_pat & GENMASK(2, 0)) != 6) {
9408 pr_err("host PAT[0] is not WB\n");
9412 x86_emulator_cache = kvm_alloc_emulator_cache();
9413 if (!x86_emulator_cache) {
9414 pr_err("failed to allocate cache for x86 emulator\n");
9418 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
9419 if (!user_return_msrs) {
9420 pr_err("failed to allocate percpu kvm_user_return_msrs\n");
9422 goto out_free_x86_emulator_cache;
9424 kvm_nr_uret_msrs = 0;
9426 r = kvm_mmu_vendor_module_init();
9428 goto out_free_percpu;
9430 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
9431 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
9432 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
9435 rdmsrl_safe(MSR_EFER, &host_efer);
9437 if (boot_cpu_has(X86_FEATURE_XSAVES))
9438 rdmsrl(MSR_IA32_XSS, host_xss);
9440 kvm_init_pmu_capability(ops->pmu_ops);
9442 r = ops->hardware_setup();
9446 kvm_ops_update(ops);
9448 for_each_online_cpu(cpu) {
9449 smp_call_function_single(cpu, kvm_x86_check_cpu_compat, &r, 1);
9451 goto out_unwind_ops;
9455 * Point of no return! DO NOT add error paths below this point unless
9456 * absolutely necessary, as most operations from this point forward
9457 * require unwinding.
9461 if (pi_inject_timer == -1)
9462 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
9463 #ifdef CONFIG_X86_64
9464 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
9466 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9467 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
9470 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
9472 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9473 kvm_caps.supported_xss = 0;
9475 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9476 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9477 #undef __kvm_cpu_cap_has
9479 if (kvm_caps.has_tsc_control) {
9481 * Make sure the user can only configure tsc_khz values that
9482 * fit into a signed integer.
9483 * A min value is not calculated because it will always
9484 * be 1 on all machines.
9486 u64 max = min(0x7fffffffULL,
9487 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
9488 kvm_caps.max_guest_tsc_khz = max;
9490 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
9491 kvm_init_msr_list();
9495 kvm_x86_ops.hardware_enable = NULL;
9496 static_call(kvm_x86_hardware_unsetup)();
9498 kvm_mmu_vendor_module_exit();
9500 free_percpu(user_return_msrs);
9501 out_free_x86_emulator_cache:
9502 kmem_cache_destroy(x86_emulator_cache);
9506 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9510 mutex_lock(&vendor_module_lock);
9511 r = __kvm_x86_vendor_init(ops);
9512 mutex_unlock(&vendor_module_lock);
9516 EXPORT_SYMBOL_GPL(kvm_x86_vendor_init);
9518 void kvm_x86_vendor_exit(void)
9520 kvm_unregister_perf_callbacks();
9522 #ifdef CONFIG_X86_64
9523 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9524 clear_hv_tscchange_cb();
9528 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9529 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
9530 CPUFREQ_TRANSITION_NOTIFIER);
9531 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
9533 #ifdef CONFIG_X86_64
9534 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9535 irq_work_sync(&pvclock_irq_work);
9536 cancel_work_sync(&pvclock_gtod_work);
9538 static_call(kvm_x86_hardware_unsetup)();
9539 kvm_mmu_vendor_module_exit();
9540 free_percpu(user_return_msrs);
9541 kmem_cache_destroy(x86_emulator_cache);
9542 #ifdef CONFIG_KVM_XEN
9543 static_key_deferred_flush(&kvm_xen_enabled);
9544 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9546 mutex_lock(&vendor_module_lock);
9547 kvm_x86_ops.hardware_enable = NULL;
9548 mutex_unlock(&vendor_module_lock);
9550 EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit);
9552 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9555 * The vCPU has halted, e.g. executed HLT. Update the run state if the
9556 * local APIC is in-kernel, the run loop will detect the non-runnable
9557 * state and halt the vCPU. Exit to userspace if the local APIC is
9558 * managed by userspace, in which case userspace is responsible for
9559 * handling wake events.
9561 ++vcpu->stat.halt_exits;
9562 if (lapic_in_kernel(vcpu)) {
9563 vcpu->arch.mp_state = state;
9566 vcpu->run->exit_reason = reason;
9571 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9573 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9575 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9577 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9579 int ret = kvm_skip_emulated_instruction(vcpu);
9581 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9582 * KVM_EXIT_DEBUG here.
9584 return kvm_emulate_halt_noskip(vcpu) && ret;
9586 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9588 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9590 int ret = kvm_skip_emulated_instruction(vcpu);
9592 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9593 KVM_EXIT_AP_RESET_HOLD) && ret;
9595 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9597 #ifdef CONFIG_X86_64
9598 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9599 unsigned long clock_type)
9601 struct kvm_clock_pairing clock_pairing;
9602 struct timespec64 ts;
9606 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9607 return -KVM_EOPNOTSUPP;
9610 * When tsc is in permanent catchup mode guests won't be able to use
9611 * pvclock_read_retry loop to get consistent view of pvclock
9613 if (vcpu->arch.tsc_always_catchup)
9614 return -KVM_EOPNOTSUPP;
9616 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9617 return -KVM_EOPNOTSUPP;
9619 clock_pairing.sec = ts.tv_sec;
9620 clock_pairing.nsec = ts.tv_nsec;
9621 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9622 clock_pairing.flags = 0;
9623 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9626 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9627 sizeof(struct kvm_clock_pairing)))
9635 * kvm_pv_kick_cpu_op: Kick a vcpu.
9637 * @apicid - apicid of vcpu to be kicked.
9639 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9642 * All other fields are unused for APIC_DM_REMRD, but may be consumed by
9643 * common code, e.g. for tracing. Defer initialization to the compiler.
9645 struct kvm_lapic_irq lapic_irq = {
9646 .delivery_mode = APIC_DM_REMRD,
9647 .dest_mode = APIC_DEST_PHYSICAL,
9648 .shorthand = APIC_DEST_NOSHORT,
9652 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9655 bool kvm_apicv_activated(struct kvm *kvm)
9657 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9659 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9661 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
9663 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
9664 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
9666 return (vm_reasons | vcpu_reasons) == 0;
9668 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
9670 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9671 enum kvm_apicv_inhibit reason, bool set)
9674 __set_bit(reason, inhibits);
9676 __clear_bit(reason, inhibits);
9678 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9681 static void kvm_apicv_init(struct kvm *kvm)
9683 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9685 init_rwsem(&kvm->arch.apicv_update_lock);
9687 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9690 set_or_clear_apicv_inhibit(inhibits,
9691 APICV_INHIBIT_REASON_DISABLE, true);
9694 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9696 struct kvm_vcpu *target = NULL;
9697 struct kvm_apic_map *map;
9699 vcpu->stat.directed_yield_attempted++;
9701 if (single_task_running())
9705 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9707 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9708 target = map->phys_map[dest_id]->vcpu;
9712 if (!target || !READ_ONCE(target->ready))
9715 /* Ignore requests to yield to self */
9719 if (kvm_vcpu_yield_to(target) <= 0)
9722 vcpu->stat.directed_yield_successful++;
9728 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9730 u64 ret = vcpu->run->hypercall.ret;
9732 if (!is_64_bit_mode(vcpu))
9734 kvm_rax_write(vcpu, ret);
9735 ++vcpu->stat.hypercalls;
9736 return kvm_skip_emulated_instruction(vcpu);
9739 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9741 unsigned long nr, a0, a1, a2, a3, ret;
9744 if (kvm_xen_hypercall_enabled(vcpu->kvm))
9745 return kvm_xen_hypercall(vcpu);
9747 if (kvm_hv_hypercall_enabled(vcpu))
9748 return kvm_hv_hypercall(vcpu);
9750 nr = kvm_rax_read(vcpu);
9751 a0 = kvm_rbx_read(vcpu);
9752 a1 = kvm_rcx_read(vcpu);
9753 a2 = kvm_rdx_read(vcpu);
9754 a3 = kvm_rsi_read(vcpu);
9756 trace_kvm_hypercall(nr, a0, a1, a2, a3);
9758 op_64_bit = is_64_bit_hypercall(vcpu);
9767 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9775 case KVM_HC_VAPIC_POLL_IRQ:
9778 case KVM_HC_KICK_CPU:
9779 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9782 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9783 kvm_sched_yield(vcpu, a1);
9786 #ifdef CONFIG_X86_64
9787 case KVM_HC_CLOCK_PAIRING:
9788 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9791 case KVM_HC_SEND_IPI:
9792 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9795 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9797 case KVM_HC_SCHED_YIELD:
9798 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9801 kvm_sched_yield(vcpu, a0);
9804 case KVM_HC_MAP_GPA_RANGE: {
9805 u64 gpa = a0, npages = a1, attrs = a2;
9808 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9811 if (!PAGE_ALIGNED(gpa) || !npages ||
9812 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9817 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
9818 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
9819 vcpu->run->hypercall.args[0] = gpa;
9820 vcpu->run->hypercall.args[1] = npages;
9821 vcpu->run->hypercall.args[2] = attrs;
9822 vcpu->run->hypercall.flags = 0;
9824 vcpu->run->hypercall.flags |= KVM_EXIT_HYPERCALL_LONG_MODE;
9826 WARN_ON_ONCE(vcpu->run->hypercall.flags & KVM_EXIT_HYPERCALL_MBZ);
9827 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9837 kvm_rax_write(vcpu, ret);
9839 ++vcpu->stat.hypercalls;
9840 return kvm_skip_emulated_instruction(vcpu);
9842 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9844 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9846 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9847 char instruction[3];
9848 unsigned long rip = kvm_rip_read(vcpu);
9851 * If the quirk is disabled, synthesize a #UD and let the guest pick up
9854 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
9855 ctxt->exception.error_code_valid = false;
9856 ctxt->exception.vector = UD_VECTOR;
9857 ctxt->have_exception = true;
9858 return X86EMUL_PROPAGATE_FAULT;
9861 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9863 return emulator_write_emulated(ctxt, rip, instruction, 3,
9867 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9869 return vcpu->run->request_interrupt_window &&
9870 likely(!pic_in_kernel(vcpu->kvm));
9873 /* Called within kvm->srcu read side. */
9874 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9876 struct kvm_run *kvm_run = vcpu->run;
9878 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9879 kvm_run->cr8 = kvm_get_cr8(vcpu);
9880 kvm_run->apic_base = kvm_get_apic_base(vcpu);
9882 kvm_run->ready_for_interrupt_injection =
9883 pic_in_kernel(vcpu->kvm) ||
9884 kvm_vcpu_ready_for_interrupt_injection(vcpu);
9887 kvm_run->flags |= KVM_RUN_X86_SMM;
9890 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9894 if (!kvm_x86_ops.update_cr8_intercept)
9897 if (!lapic_in_kernel(vcpu))
9900 if (vcpu->arch.apic->apicv_active)
9903 if (!vcpu->arch.apic->vapic_addr)
9904 max_irr = kvm_lapic_find_highest_irr(vcpu);
9911 tpr = kvm_lapic_get_cr8(vcpu);
9913 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
9917 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
9919 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9920 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9924 return kvm_x86_ops.nested_ops->check_events(vcpu);
9927 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
9929 trace_kvm_inj_exception(vcpu->arch.exception.vector,
9930 vcpu->arch.exception.has_error_code,
9931 vcpu->arch.exception.error_code,
9932 vcpu->arch.exception.injected);
9934 if (vcpu->arch.exception.error_code && !is_protmode(vcpu))
9935 vcpu->arch.exception.error_code = false;
9936 static_call(kvm_x86_inject_exception)(vcpu);
9940 * Check for any event (interrupt or exception) that is ready to be injected,
9941 * and if there is at least one event, inject the event with the highest
9942 * priority. This handles both "pending" events, i.e. events that have never
9943 * been injected into the guest, and "injected" events, i.e. events that were
9944 * injected as part of a previous VM-Enter, but weren't successfully delivered
9945 * and need to be re-injected.
9947 * Note, this is not guaranteed to be invoked on a guest instruction boundary,
9948 * i.e. doesn't guarantee that there's an event window in the guest. KVM must
9949 * be able to inject exceptions in the "middle" of an instruction, and so must
9950 * also be able to re-inject NMIs and IRQs in the middle of an instruction.
9951 * I.e. for exceptions and re-injected events, NOT invoking this on instruction
9952 * boundaries is necessary and correct.
9954 * For simplicity, KVM uses a single path to inject all events (except events
9955 * that are injected directly from L1 to L2) and doesn't explicitly track
9956 * instruction boundaries for asynchronous events. However, because VM-Exits
9957 * that can occur during instruction execution typically result in KVM skipping
9958 * the instruction or injecting an exception, e.g. instruction and exception
9959 * intercepts, and because pending exceptions have higher priority than pending
9960 * interrupts, KVM still honors instruction boundaries in most scenarios.
9962 * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip
9963 * the instruction or inject an exception, then KVM can incorrecty inject a new
9964 * asynchrounous event if the event became pending after the CPU fetched the
9965 * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation)
9966 * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be
9967 * injected on the restarted instruction instead of being deferred until the
9968 * instruction completes.
9970 * In practice, this virtualization hole is unlikely to be observed by the
9971 * guest, and even less likely to cause functional problems. To detect the
9972 * hole, the guest would have to trigger an event on a side effect of an early
9973 * phase of instruction execution, e.g. on the instruction fetch from memory.
9974 * And for it to be a functional problem, the guest would need to depend on the
9975 * ordering between that side effect, the instruction completing, _and_ the
9976 * delivery of the asynchronous event.
9978 static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu,
9979 bool *req_immediate_exit)
9985 * Process nested events first, as nested VM-Exit supercedes event
9986 * re-injection. If there's an event queued for re-injection, it will
9987 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit.
9989 if (is_guest_mode(vcpu))
9990 r = kvm_check_nested_events(vcpu);
9995 * Re-inject exceptions and events *especially* if immediate entry+exit
9996 * to/from L2 is needed, as any event that has already been injected
9997 * into L2 needs to complete its lifecycle before injecting a new event.
9999 * Don't re-inject an NMI or interrupt if there is a pending exception.
10000 * This collision arises if an exception occurred while vectoring the
10001 * injected event, KVM intercepted said exception, and KVM ultimately
10002 * determined the fault belongs to the guest and queues the exception
10003 * for injection back into the guest.
10005 * "Injected" interrupts can also collide with pending exceptions if
10006 * userspace ignores the "ready for injection" flag and blindly queues
10007 * an interrupt. In that case, prioritizing the exception is correct,
10008 * as the exception "occurred" before the exit to userspace. Trap-like
10009 * exceptions, e.g. most #DBs, have higher priority than interrupts.
10010 * And while fault-like exceptions, e.g. #GP and #PF, are the lowest
10011 * priority, they're only generated (pended) during instruction
10012 * execution, and interrupts are recognized at instruction boundaries.
10013 * Thus a pending fault-like exception means the fault occurred on the
10014 * *previous* instruction and must be serviced prior to recognizing any
10015 * new events in order to fully complete the previous instruction.
10017 if (vcpu->arch.exception.injected)
10018 kvm_inject_exception(vcpu);
10019 else if (kvm_is_exception_pending(vcpu))
10021 else if (vcpu->arch.nmi_injected)
10022 static_call(kvm_x86_inject_nmi)(vcpu);
10023 else if (vcpu->arch.interrupt.injected)
10024 static_call(kvm_x86_inject_irq)(vcpu, true);
10027 * Exceptions that morph to VM-Exits are handled above, and pending
10028 * exceptions on top of injected exceptions that do not VM-Exit should
10029 * either morph to #DF or, sadly, override the injected exception.
10031 WARN_ON_ONCE(vcpu->arch.exception.injected &&
10032 vcpu->arch.exception.pending);
10035 * Bail if immediate entry+exit to/from the guest is needed to complete
10036 * nested VM-Enter or event re-injection so that a different pending
10037 * event can be serviced (or if KVM needs to exit to userspace).
10039 * Otherwise, continue processing events even if VM-Exit occurred. The
10040 * VM-Exit will have cleared exceptions that were meant for L2, but
10041 * there may now be events that can be injected into L1.
10047 * A pending exception VM-Exit should either result in nested VM-Exit
10048 * or force an immediate re-entry and exit to/from L2, and exception
10049 * VM-Exits cannot be injected (flag should _never_ be set).
10051 WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected ||
10052 vcpu->arch.exception_vmexit.pending);
10055 * New events, other than exceptions, cannot be injected if KVM needs
10056 * to re-inject a previous event. See above comments on re-injecting
10057 * for why pending exceptions get priority.
10059 can_inject = !kvm_event_needs_reinjection(vcpu);
10061 if (vcpu->arch.exception.pending) {
10063 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS
10064 * value pushed on the stack. Trap-like exception and all #DBs
10065 * leave RF as-is (KVM follows Intel's behavior in this regard;
10066 * AMD states that code breakpoint #DBs excplitly clear RF=0).
10068 * Note, most versions of Intel's SDM and AMD's APM incorrectly
10069 * describe the behavior of General Detect #DBs, which are
10070 * fault-like. They do _not_ set RF, a la code breakpoints.
10072 if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT)
10073 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
10076 if (vcpu->arch.exception.vector == DB_VECTOR) {
10077 kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception);
10078 if (vcpu->arch.dr7 & DR7_GD) {
10079 vcpu->arch.dr7 &= ~DR7_GD;
10080 kvm_update_dr7(vcpu);
10084 kvm_inject_exception(vcpu);
10086 vcpu->arch.exception.pending = false;
10087 vcpu->arch.exception.injected = true;
10089 can_inject = false;
10092 /* Don't inject interrupts if the user asked to avoid doing so */
10093 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
10097 * Finally, inject interrupt events. If an event cannot be injected
10098 * due to architectural conditions (e.g. IF=0) a window-open exit
10099 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
10100 * and can architecturally be injected, but we cannot do it right now:
10101 * an interrupt could have arrived just now and we have to inject it
10102 * as a vmexit, or there could already an event in the queue, which is
10103 * indicated by can_inject. In that case we request an immediate exit
10104 * in order to make progress and get back here for another iteration.
10105 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
10107 #ifdef CONFIG_KVM_SMM
10108 if (vcpu->arch.smi_pending) {
10109 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
10113 vcpu->arch.smi_pending = false;
10114 ++vcpu->arch.smi_count;
10116 can_inject = false;
10118 static_call(kvm_x86_enable_smi_window)(vcpu);
10122 if (vcpu->arch.nmi_pending) {
10123 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
10127 --vcpu->arch.nmi_pending;
10128 vcpu->arch.nmi_injected = true;
10129 static_call(kvm_x86_inject_nmi)(vcpu);
10130 can_inject = false;
10131 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
10133 if (vcpu->arch.nmi_pending)
10134 static_call(kvm_x86_enable_nmi_window)(vcpu);
10137 if (kvm_cpu_has_injectable_intr(vcpu)) {
10138 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
10142 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
10143 static_call(kvm_x86_inject_irq)(vcpu, false);
10144 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
10146 if (kvm_cpu_has_injectable_intr(vcpu))
10147 static_call(kvm_x86_enable_irq_window)(vcpu);
10150 if (is_guest_mode(vcpu) &&
10151 kvm_x86_ops.nested_ops->has_events &&
10152 kvm_x86_ops.nested_ops->has_events(vcpu))
10153 *req_immediate_exit = true;
10156 * KVM must never queue a new exception while injecting an event; KVM
10157 * is done emulating and should only propagate the to-be-injected event
10158 * to the VMCS/VMCB. Queueing a new exception can put the vCPU into an
10159 * infinite loop as KVM will bail from VM-Enter to inject the pending
10160 * exception and start the cycle all over.
10162 * Exempt triple faults as they have special handling and won't put the
10163 * vCPU into an infinite loop. Triple fault can be queued when running
10164 * VMX without unrestricted guest, as that requires KVM to emulate Real
10165 * Mode events (see kvm_inject_realmode_interrupt()).
10167 WARN_ON_ONCE(vcpu->arch.exception.pending ||
10168 vcpu->arch.exception_vmexit.pending);
10173 *req_immediate_exit = true;
10179 static void process_nmi(struct kvm_vcpu *vcpu)
10181 unsigned limit = 2;
10184 * x86 is limited to one NMI running, and one NMI pending after it.
10185 * If an NMI is already in progress, limit further NMIs to just one.
10186 * Otherwise, allow two (and we'll inject the first one immediately).
10188 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
10191 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
10192 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
10193 kvm_make_request(KVM_REQ_EVENT, vcpu);
10196 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
10197 unsigned long *vcpu_bitmap)
10199 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
10202 void kvm_make_scan_ioapic_request(struct kvm *kvm)
10204 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
10207 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10209 struct kvm_lapic *apic = vcpu->arch.apic;
10212 if (!lapic_in_kernel(vcpu))
10215 down_read(&vcpu->kvm->arch.apicv_update_lock);
10218 /* Do not activate APICV when APIC is disabled */
10219 activate = kvm_vcpu_apicv_activated(vcpu) &&
10220 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED);
10222 if (apic->apicv_active == activate)
10225 apic->apicv_active = activate;
10226 kvm_apic_update_apicv(vcpu);
10227 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
10230 * When APICv gets disabled, we may still have injected interrupts
10231 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10232 * still active when the interrupt got accepted. Make sure
10233 * kvm_check_and_inject_events() is called to check for that.
10235 if (!apic->apicv_active)
10236 kvm_make_request(KVM_REQ_EVENT, vcpu);
10240 up_read(&vcpu->kvm->arch.apicv_update_lock);
10242 EXPORT_SYMBOL_GPL(__kvm_vcpu_update_apicv);
10244 static void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10246 if (!lapic_in_kernel(vcpu))
10250 * Due to sharing page tables across vCPUs, the xAPIC memslot must be
10251 * deleted if any vCPU has xAPIC virtualization and x2APIC enabled, but
10252 * and hardware doesn't support x2APIC virtualization. E.g. some AMD
10253 * CPUs support AVIC but not x2APIC. KVM still allows enabling AVIC in
10254 * this case so that KVM can the AVIC doorbell to inject interrupts to
10255 * running vCPUs, but KVM must not create SPTEs for the APIC base as
10256 * the vCPU would incorrectly be able to access the vAPIC page via MMIO
10257 * despite being in x2APIC mode. For simplicity, inhibiting the APIC
10258 * access page is sticky.
10260 if (apic_x2apic_mode(vcpu->arch.apic) &&
10261 kvm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization)
10262 kvm_inhibit_apic_access_page(vcpu);
10264 __kvm_vcpu_update_apicv(vcpu);
10267 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10268 enum kvm_apicv_inhibit reason, bool set)
10270 unsigned long old, new;
10272 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
10274 if (!(kvm_x86_ops.required_apicv_inhibits & BIT(reason)))
10277 old = new = kvm->arch.apicv_inhibit_reasons;
10279 set_or_clear_apicv_inhibit(&new, reason, set);
10281 if (!!old != !!new) {
10283 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
10284 * false positives in the sanity check WARN in svm_vcpu_run().
10285 * This task will wait for all vCPUs to ack the kick IRQ before
10286 * updating apicv_inhibit_reasons, and all other vCPUs will
10287 * block on acquiring apicv_update_lock so that vCPUs can't
10288 * redo svm_vcpu_run() without seeing the new inhibit state.
10290 * Note, holding apicv_update_lock and taking it in the read
10291 * side (handling the request) also prevents other vCPUs from
10292 * servicing the request with a stale apicv_inhibit_reasons.
10294 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
10295 kvm->arch.apicv_inhibit_reasons = new;
10297 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
10298 int idx = srcu_read_lock(&kvm->srcu);
10300 kvm_zap_gfn_range(kvm, gfn, gfn+1);
10301 srcu_read_unlock(&kvm->srcu, idx);
10304 kvm->arch.apicv_inhibit_reasons = new;
10308 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10309 enum kvm_apicv_inhibit reason, bool set)
10314 down_write(&kvm->arch.apicv_update_lock);
10315 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10316 up_write(&kvm->arch.apicv_update_lock);
10318 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
10320 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
10322 if (!kvm_apic_present(vcpu))
10325 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
10327 if (irqchip_split(vcpu->kvm))
10328 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
10330 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10331 if (ioapic_in_kernel(vcpu->kvm))
10332 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
10335 if (is_guest_mode(vcpu))
10336 vcpu->arch.load_eoi_exitmap_pending = true;
10338 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
10341 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
10343 u64 eoi_exit_bitmap[4];
10345 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
10348 if (to_hv_vcpu(vcpu)) {
10349 bitmap_or((ulong *)eoi_exit_bitmap,
10350 vcpu->arch.ioapic_handled_vectors,
10351 to_hv_synic(vcpu)->vec_bitmap, 256);
10352 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
10356 static_call_cond(kvm_x86_load_eoi_exitmap)(
10357 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
10360 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
10361 unsigned long start, unsigned long end)
10363 unsigned long apic_address;
10366 * The physical address of apic access page is stored in the VMCS.
10367 * Update it when it becomes invalid.
10369 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
10370 if (start <= apic_address && apic_address < end)
10371 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
10374 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
10376 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
10379 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
10381 if (!lapic_in_kernel(vcpu))
10384 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
10387 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
10389 smp_send_reschedule(vcpu->cpu);
10391 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
10394 * Called within kvm->srcu read side.
10395 * Returns 1 to let vcpu_run() continue the guest execution loop without
10396 * exiting to the userspace. Otherwise, the value will be returned to the
10399 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
10403 dm_request_for_irq_injection(vcpu) &&
10404 kvm_cpu_accept_dm_intr(vcpu);
10405 fastpath_t exit_fastpath;
10407 bool req_immediate_exit = false;
10409 if (kvm_request_pending(vcpu)) {
10410 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
10415 if (kvm_dirty_ring_check_request(vcpu)) {
10420 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
10421 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
10426 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
10427 kvm_mmu_free_obsolete_roots(vcpu);
10428 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
10429 __kvm_migrate_timers(vcpu);
10430 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
10431 kvm_update_masterclock(vcpu->kvm);
10432 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
10433 kvm_gen_kvmclock_update(vcpu);
10434 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
10435 r = kvm_guest_time_update(vcpu);
10439 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10440 kvm_mmu_sync_roots(vcpu);
10441 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10442 kvm_mmu_load_pgd(vcpu);
10445 * Note, the order matters here, as flushing "all" TLB entries
10446 * also flushes the "current" TLB entries, i.e. servicing the
10447 * flush "all" will clear any request to flush "current".
10449 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
10450 kvm_vcpu_flush_tlb_all(vcpu);
10452 kvm_service_local_tlb_flush_requests(vcpu);
10455 * Fall back to a "full" guest flush if Hyper-V's precise
10456 * flushing fails. Note, Hyper-V's flushing is per-vCPU, but
10457 * the flushes are considered "remote" and not "local" because
10458 * the requests can be initiated from other vCPUs.
10460 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) &&
10461 kvm_hv_vcpu_flush_tlb(vcpu))
10462 kvm_vcpu_flush_tlb_guest(vcpu);
10464 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10465 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10469 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10470 if (is_guest_mode(vcpu))
10471 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10473 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10474 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10475 vcpu->mmio_needed = 0;
10480 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10481 /* Page is swapped out. Do synthetic halt */
10482 vcpu->arch.apf.halted = true;
10486 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10487 record_steal_time(vcpu);
10488 #ifdef CONFIG_KVM_SMM
10489 if (kvm_check_request(KVM_REQ_SMI, vcpu))
10492 if (kvm_check_request(KVM_REQ_NMI, vcpu))
10494 if (kvm_check_request(KVM_REQ_PMU, vcpu))
10495 kvm_pmu_handle_event(vcpu);
10496 if (kvm_check_request(KVM_REQ_PMI, vcpu))
10497 kvm_pmu_deliver_pmi(vcpu);
10498 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10499 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10500 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10501 vcpu->arch.ioapic_handled_vectors)) {
10502 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10503 vcpu->run->eoi.vector =
10504 vcpu->arch.pending_ioapic_eoi;
10509 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10510 vcpu_scan_ioapic(vcpu);
10511 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10512 vcpu_load_eoi_exitmap(vcpu);
10513 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10514 kvm_vcpu_reload_apic_access_page(vcpu);
10515 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10516 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10517 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10518 vcpu->run->system_event.ndata = 0;
10522 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10523 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10524 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10525 vcpu->run->system_event.ndata = 0;
10529 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10530 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10532 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10533 vcpu->run->hyperv = hv_vcpu->exit;
10539 * KVM_REQ_HV_STIMER has to be processed after
10540 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10541 * depend on the guest clock being up-to-date
10543 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10544 kvm_hv_process_stimers(vcpu);
10545 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10546 kvm_vcpu_update_apicv(vcpu);
10547 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10548 kvm_check_async_pf_completion(vcpu);
10549 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10550 static_call(kvm_x86_msr_filter_changed)(vcpu);
10552 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10553 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10556 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10557 kvm_xen_has_interrupt(vcpu)) {
10558 ++vcpu->stat.req_event;
10559 r = kvm_apic_accept_events(vcpu);
10564 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10569 r = kvm_check_and_inject_events(vcpu, &req_immediate_exit);
10575 static_call(kvm_x86_enable_irq_window)(vcpu);
10577 if (kvm_lapic_enabled(vcpu)) {
10578 update_cr8_intercept(vcpu);
10579 kvm_lapic_sync_to_vapic(vcpu);
10583 r = kvm_mmu_reload(vcpu);
10585 goto cancel_injection;
10590 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10593 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10594 * IPI are then delayed after guest entry, which ensures that they
10595 * result in virtual interrupt delivery.
10597 local_irq_disable();
10599 /* Store vcpu->apicv_active before vcpu->mode. */
10600 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10602 kvm_vcpu_srcu_read_unlock(vcpu);
10605 * 1) We should set ->mode before checking ->requests. Please see
10606 * the comment in kvm_vcpu_exiting_guest_mode().
10608 * 2) For APICv, we should set ->mode before checking PID.ON. This
10609 * pairs with the memory barrier implicit in pi_test_and_set_on
10610 * (see vmx_deliver_posted_interrupt).
10612 * 3) This also orders the write to mode from any reads to the page
10613 * tables done while the VCPU is running. Please see the comment
10614 * in kvm_flush_remote_tlbs.
10616 smp_mb__after_srcu_read_unlock();
10619 * Process pending posted interrupts to handle the case where the
10620 * notification IRQ arrived in the host, or was never sent (because the
10621 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10622 * status, KVM doesn't update assigned devices when APICv is inhibited,
10623 * i.e. they can post interrupts even if APICv is temporarily disabled.
10625 if (kvm_lapic_enabled(vcpu))
10626 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10628 if (kvm_vcpu_exit_request(vcpu)) {
10629 vcpu->mode = OUTSIDE_GUEST_MODE;
10631 local_irq_enable();
10633 kvm_vcpu_srcu_read_lock(vcpu);
10635 goto cancel_injection;
10638 if (req_immediate_exit) {
10639 kvm_make_request(KVM_REQ_EVENT, vcpu);
10640 static_call(kvm_x86_request_immediate_exit)(vcpu);
10643 fpregs_assert_state_consistent();
10644 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10645 switch_fpu_return();
10647 if (vcpu->arch.guest_fpu.xfd_err)
10648 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10650 if (unlikely(vcpu->arch.switch_db_regs)) {
10651 set_debugreg(0, 7);
10652 set_debugreg(vcpu->arch.eff_db[0], 0);
10653 set_debugreg(vcpu->arch.eff_db[1], 1);
10654 set_debugreg(vcpu->arch.eff_db[2], 2);
10655 set_debugreg(vcpu->arch.eff_db[3], 3);
10656 } else if (unlikely(hw_breakpoint_active())) {
10657 set_debugreg(0, 7);
10660 guest_timing_enter_irqoff();
10664 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10665 * update must kick and wait for all vCPUs before toggling the
10666 * per-VM state, and responsing vCPUs must wait for the update
10667 * to complete before servicing KVM_REQ_APICV_UPDATE.
10669 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&
10670 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED));
10672 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10673 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10676 if (kvm_lapic_enabled(vcpu))
10677 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10679 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10680 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10686 * Do this here before restoring debug registers on the host. And
10687 * since we do this before handling the vmexit, a DR access vmexit
10688 * can (a) read the correct value of the debug registers, (b) set
10689 * KVM_DEBUGREG_WONT_EXIT again.
10691 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10692 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10693 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10694 kvm_update_dr0123(vcpu);
10695 kvm_update_dr7(vcpu);
10699 * If the guest has used debug registers, at least dr7
10700 * will be disabled while returning to the host.
10701 * If we don't have active breakpoints in the host, we don't
10702 * care about the messed up debug address registers. But if
10703 * we have some of them active, restore the old state.
10705 if (hw_breakpoint_active())
10706 hw_breakpoint_restore();
10708 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10709 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10711 vcpu->mode = OUTSIDE_GUEST_MODE;
10715 * Sync xfd before calling handle_exit_irqoff() which may
10716 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10717 * in #NM irqoff handler).
10719 if (vcpu->arch.xfd_no_write_intercept)
10720 fpu_sync_guest_vmexit_xfd_state();
10722 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10724 if (vcpu->arch.guest_fpu.xfd_err)
10725 wrmsrl(MSR_IA32_XFD_ERR, 0);
10728 * Consume any pending interrupts, including the possible source of
10729 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10730 * An instruction is required after local_irq_enable() to fully unblock
10731 * interrupts on processors that implement an interrupt shadow, the
10732 * stat.exits increment will do nicely.
10734 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10735 local_irq_enable();
10736 ++vcpu->stat.exits;
10737 local_irq_disable();
10738 kvm_after_interrupt(vcpu);
10741 * Wait until after servicing IRQs to account guest time so that any
10742 * ticks that occurred while running the guest are properly accounted
10743 * to the guest. Waiting until IRQs are enabled degrades the accuracy
10744 * of accounting via context tracking, but the loss of accuracy is
10745 * acceptable for all known use cases.
10747 guest_timing_exit_irqoff();
10749 local_irq_enable();
10752 kvm_vcpu_srcu_read_lock(vcpu);
10755 * Profile KVM exit RIPs:
10757 if (unlikely(prof_on == KVM_PROFILING)) {
10758 unsigned long rip = kvm_rip_read(vcpu);
10759 profile_hit(KVM_PROFILING, (void *)rip);
10762 if (unlikely(vcpu->arch.tsc_always_catchup))
10763 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10765 if (vcpu->arch.apic_attention)
10766 kvm_lapic_sync_from_vapic(vcpu);
10768 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10772 if (req_immediate_exit)
10773 kvm_make_request(KVM_REQ_EVENT, vcpu);
10774 static_call(kvm_x86_cancel_injection)(vcpu);
10775 if (unlikely(vcpu->arch.apic_attention))
10776 kvm_lapic_sync_from_vapic(vcpu);
10781 /* Called within kvm->srcu read side. */
10782 static inline int vcpu_block(struct kvm_vcpu *vcpu)
10786 if (!kvm_arch_vcpu_runnable(vcpu)) {
10788 * Switch to the software timer before halt-polling/blocking as
10789 * the guest's timer may be a break event for the vCPU, and the
10790 * hypervisor timer runs only when the CPU is in guest mode.
10791 * Switch before halt-polling so that KVM recognizes an expired
10792 * timer before blocking.
10794 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10796 kvm_lapic_switch_to_sw_timer(vcpu);
10798 kvm_vcpu_srcu_read_unlock(vcpu);
10799 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10800 kvm_vcpu_halt(vcpu);
10802 kvm_vcpu_block(vcpu);
10803 kvm_vcpu_srcu_read_lock(vcpu);
10806 kvm_lapic_switch_to_hv_timer(vcpu);
10809 * If the vCPU is not runnable, a signal or another host event
10810 * of some kind is pending; service it without changing the
10811 * vCPU's activity state.
10813 if (!kvm_arch_vcpu_runnable(vcpu))
10818 * Evaluate nested events before exiting the halted state. This allows
10819 * the halt state to be recorded properly in the VMCS12's activity
10820 * state field (AMD does not have a similar field and a VM-Exit always
10821 * causes a spurious wakeup from HLT).
10823 if (is_guest_mode(vcpu)) {
10824 if (kvm_check_nested_events(vcpu) < 0)
10828 if (kvm_apic_accept_events(vcpu) < 0)
10830 switch(vcpu->arch.mp_state) {
10831 case KVM_MP_STATE_HALTED:
10832 case KVM_MP_STATE_AP_RESET_HOLD:
10833 vcpu->arch.pv.pv_unhalted = false;
10834 vcpu->arch.mp_state =
10835 KVM_MP_STATE_RUNNABLE;
10837 case KVM_MP_STATE_RUNNABLE:
10838 vcpu->arch.apf.halted = false;
10840 case KVM_MP_STATE_INIT_RECEIVED:
10849 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10851 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10852 !vcpu->arch.apf.halted);
10855 /* Called within kvm->srcu read side. */
10856 static int vcpu_run(struct kvm_vcpu *vcpu)
10860 vcpu->arch.l1tf_flush_l1d = true;
10864 * If another guest vCPU requests a PV TLB flush in the middle
10865 * of instruction emulation, the rest of the emulation could
10866 * use a stale page translation. Assume that any code after
10867 * this point can start executing an instruction.
10869 vcpu->arch.at_instruction_boundary = false;
10870 if (kvm_vcpu_running(vcpu)) {
10871 r = vcpu_enter_guest(vcpu);
10873 r = vcpu_block(vcpu);
10879 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
10880 if (kvm_xen_has_pending_events(vcpu))
10881 kvm_xen_inject_pending_events(vcpu);
10883 if (kvm_cpu_has_pending_timer(vcpu))
10884 kvm_inject_pending_timer_irqs(vcpu);
10886 if (dm_request_for_irq_injection(vcpu) &&
10887 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
10889 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
10890 ++vcpu->stat.request_irq_exits;
10894 if (__xfer_to_guest_mode_work_pending()) {
10895 kvm_vcpu_srcu_read_unlock(vcpu);
10896 r = xfer_to_guest_mode_handle_work(vcpu);
10897 kvm_vcpu_srcu_read_lock(vcpu);
10906 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
10908 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
10911 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
10913 BUG_ON(!vcpu->arch.pio.count);
10915 return complete_emulated_io(vcpu);
10919 * Implements the following, as a state machine:
10922 * for each fragment
10923 * for each mmio piece in the fragment
10930 * for each fragment
10931 * for each mmio piece in the fragment
10936 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
10938 struct kvm_run *run = vcpu->run;
10939 struct kvm_mmio_fragment *frag;
10942 BUG_ON(!vcpu->mmio_needed);
10944 /* Complete previous fragment */
10945 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
10946 len = min(8u, frag->len);
10947 if (!vcpu->mmio_is_write)
10948 memcpy(frag->data, run->mmio.data, len);
10950 if (frag->len <= 8) {
10951 /* Switch to the next fragment. */
10953 vcpu->mmio_cur_fragment++;
10955 /* Go forward to the next mmio piece. */
10961 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
10962 vcpu->mmio_needed = 0;
10964 /* FIXME: return into emulator if single-stepping. */
10965 if (vcpu->mmio_is_write)
10967 vcpu->mmio_read_completed = 1;
10968 return complete_emulated_io(vcpu);
10971 run->exit_reason = KVM_EXIT_MMIO;
10972 run->mmio.phys_addr = frag->gpa;
10973 if (vcpu->mmio_is_write)
10974 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
10975 run->mmio.len = min(8u, frag->len);
10976 run->mmio.is_write = vcpu->mmio_is_write;
10977 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
10981 /* Swap (qemu) user FPU context for the guest FPU context. */
10982 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
10984 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
10985 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
10989 /* When vcpu_run ends, restore user space FPU context. */
10990 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
10992 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
10993 ++vcpu->stat.fpu_reload;
10997 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
10999 struct kvm_queued_exception *ex = &vcpu->arch.exception;
11000 struct kvm_run *kvm_run = vcpu->run;
11004 kvm_sigset_activate(vcpu);
11005 kvm_run->flags = 0;
11006 kvm_load_guest_fpu(vcpu);
11008 kvm_vcpu_srcu_read_lock(vcpu);
11009 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
11010 if (kvm_run->immediate_exit) {
11015 * It should be impossible for the hypervisor timer to be in
11016 * use before KVM has ever run the vCPU.
11018 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu));
11020 kvm_vcpu_srcu_read_unlock(vcpu);
11021 kvm_vcpu_block(vcpu);
11022 kvm_vcpu_srcu_read_lock(vcpu);
11024 if (kvm_apic_accept_events(vcpu) < 0) {
11029 if (signal_pending(current)) {
11031 kvm_run->exit_reason = KVM_EXIT_INTR;
11032 ++vcpu->stat.signal_exits;
11037 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
11038 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
11043 if (kvm_run->kvm_dirty_regs) {
11044 r = sync_regs(vcpu);
11049 /* re-sync apic's tpr */
11050 if (!lapic_in_kernel(vcpu)) {
11051 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
11058 * If userspace set a pending exception and L2 is active, convert it to
11059 * a pending VM-Exit if L1 wants to intercept the exception.
11061 if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) &&
11062 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector,
11064 kvm_queue_exception_vmexit(vcpu, ex->vector,
11065 ex->has_error_code, ex->error_code,
11066 ex->has_payload, ex->payload);
11067 ex->injected = false;
11068 ex->pending = false;
11070 vcpu->arch.exception_from_userspace = false;
11072 if (unlikely(vcpu->arch.complete_userspace_io)) {
11073 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
11074 vcpu->arch.complete_userspace_io = NULL;
11079 WARN_ON_ONCE(vcpu->arch.pio.count);
11080 WARN_ON_ONCE(vcpu->mmio_needed);
11083 if (kvm_run->immediate_exit) {
11088 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
11092 r = vcpu_run(vcpu);
11095 kvm_put_guest_fpu(vcpu);
11096 if (kvm_run->kvm_valid_regs)
11098 post_kvm_run_save(vcpu);
11099 kvm_vcpu_srcu_read_unlock(vcpu);
11101 kvm_sigset_deactivate(vcpu);
11106 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11108 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
11110 * We are here if userspace calls get_regs() in the middle of
11111 * instruction emulation. Registers state needs to be copied
11112 * back from emulation context to vcpu. Userspace shouldn't do
11113 * that usually, but some bad designed PV devices (vmware
11114 * backdoor interface) need this to work
11116 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
11117 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11119 regs->rax = kvm_rax_read(vcpu);
11120 regs->rbx = kvm_rbx_read(vcpu);
11121 regs->rcx = kvm_rcx_read(vcpu);
11122 regs->rdx = kvm_rdx_read(vcpu);
11123 regs->rsi = kvm_rsi_read(vcpu);
11124 regs->rdi = kvm_rdi_read(vcpu);
11125 regs->rsp = kvm_rsp_read(vcpu);
11126 regs->rbp = kvm_rbp_read(vcpu);
11127 #ifdef CONFIG_X86_64
11128 regs->r8 = kvm_r8_read(vcpu);
11129 regs->r9 = kvm_r9_read(vcpu);
11130 regs->r10 = kvm_r10_read(vcpu);
11131 regs->r11 = kvm_r11_read(vcpu);
11132 regs->r12 = kvm_r12_read(vcpu);
11133 regs->r13 = kvm_r13_read(vcpu);
11134 regs->r14 = kvm_r14_read(vcpu);
11135 regs->r15 = kvm_r15_read(vcpu);
11138 regs->rip = kvm_rip_read(vcpu);
11139 regs->rflags = kvm_get_rflags(vcpu);
11142 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11145 __get_regs(vcpu, regs);
11150 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11152 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
11153 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11155 kvm_rax_write(vcpu, regs->rax);
11156 kvm_rbx_write(vcpu, regs->rbx);
11157 kvm_rcx_write(vcpu, regs->rcx);
11158 kvm_rdx_write(vcpu, regs->rdx);
11159 kvm_rsi_write(vcpu, regs->rsi);
11160 kvm_rdi_write(vcpu, regs->rdi);
11161 kvm_rsp_write(vcpu, regs->rsp);
11162 kvm_rbp_write(vcpu, regs->rbp);
11163 #ifdef CONFIG_X86_64
11164 kvm_r8_write(vcpu, regs->r8);
11165 kvm_r9_write(vcpu, regs->r9);
11166 kvm_r10_write(vcpu, regs->r10);
11167 kvm_r11_write(vcpu, regs->r11);
11168 kvm_r12_write(vcpu, regs->r12);
11169 kvm_r13_write(vcpu, regs->r13);
11170 kvm_r14_write(vcpu, regs->r14);
11171 kvm_r15_write(vcpu, regs->r15);
11174 kvm_rip_write(vcpu, regs->rip);
11175 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
11177 vcpu->arch.exception.pending = false;
11178 vcpu->arch.exception_vmexit.pending = false;
11180 kvm_make_request(KVM_REQ_EVENT, vcpu);
11183 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11186 __set_regs(vcpu, regs);
11191 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11193 struct desc_ptr dt;
11195 if (vcpu->arch.guest_state_protected)
11196 goto skip_protected_regs;
11198 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11199 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11200 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11201 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11202 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11203 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11205 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11206 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11208 static_call(kvm_x86_get_idt)(vcpu, &dt);
11209 sregs->idt.limit = dt.size;
11210 sregs->idt.base = dt.address;
11211 static_call(kvm_x86_get_gdt)(vcpu, &dt);
11212 sregs->gdt.limit = dt.size;
11213 sregs->gdt.base = dt.address;
11215 sregs->cr2 = vcpu->arch.cr2;
11216 sregs->cr3 = kvm_read_cr3(vcpu);
11218 skip_protected_regs:
11219 sregs->cr0 = kvm_read_cr0(vcpu);
11220 sregs->cr4 = kvm_read_cr4(vcpu);
11221 sregs->cr8 = kvm_get_cr8(vcpu);
11222 sregs->efer = vcpu->arch.efer;
11223 sregs->apic_base = kvm_get_apic_base(vcpu);
11226 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11228 __get_sregs_common(vcpu, sregs);
11230 if (vcpu->arch.guest_state_protected)
11233 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
11234 set_bit(vcpu->arch.interrupt.nr,
11235 (unsigned long *)sregs->interrupt_bitmap);
11238 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11242 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
11244 if (vcpu->arch.guest_state_protected)
11247 if (is_pae_paging(vcpu)) {
11248 for (i = 0 ; i < 4 ; i++)
11249 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
11250 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
11254 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
11255 struct kvm_sregs *sregs)
11258 __get_sregs(vcpu, sregs);
11263 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
11264 struct kvm_mp_state *mp_state)
11269 if (kvm_mpx_supported())
11270 kvm_load_guest_fpu(vcpu);
11272 r = kvm_apic_accept_events(vcpu);
11277 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
11278 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
11279 vcpu->arch.pv.pv_unhalted)
11280 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
11282 mp_state->mp_state = vcpu->arch.mp_state;
11285 if (kvm_mpx_supported())
11286 kvm_put_guest_fpu(vcpu);
11291 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
11292 struct kvm_mp_state *mp_state)
11298 switch (mp_state->mp_state) {
11299 case KVM_MP_STATE_UNINITIALIZED:
11300 case KVM_MP_STATE_HALTED:
11301 case KVM_MP_STATE_AP_RESET_HOLD:
11302 case KVM_MP_STATE_INIT_RECEIVED:
11303 case KVM_MP_STATE_SIPI_RECEIVED:
11304 if (!lapic_in_kernel(vcpu))
11308 case KVM_MP_STATE_RUNNABLE:
11316 * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow
11317 * forcing the guest into INIT/SIPI if those events are supposed to be
11318 * blocked. KVM prioritizes SMI over INIT, so reject INIT/SIPI state
11319 * if an SMI is pending as well.
11321 if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) &&
11322 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
11323 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
11326 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
11327 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
11328 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
11330 vcpu->arch.mp_state = mp_state->mp_state;
11331 kvm_make_request(KVM_REQ_EVENT, vcpu);
11339 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
11340 int reason, bool has_error_code, u32 error_code)
11342 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
11345 init_emulate_ctxt(vcpu);
11347 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
11348 has_error_code, error_code);
11350 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11351 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11352 vcpu->run->internal.ndata = 0;
11356 kvm_rip_write(vcpu, ctxt->eip);
11357 kvm_set_rflags(vcpu, ctxt->eflags);
11360 EXPORT_SYMBOL_GPL(kvm_task_switch);
11362 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11364 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
11366 * When EFER.LME and CR0.PG are set, the processor is in
11367 * 64-bit mode (though maybe in a 32-bit code segment).
11368 * CR4.PAE and EFER.LMA must be set.
11370 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
11372 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
11376 * Not in 64-bit mode: EFER.LMA is clear and the code
11377 * segment cannot be 64-bit.
11379 if (sregs->efer & EFER_LMA || sregs->cs.l)
11383 return kvm_is_valid_cr4(vcpu, sregs->cr4);
11386 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
11387 int *mmu_reset_needed, bool update_pdptrs)
11389 struct msr_data apic_base_msr;
11391 struct desc_ptr dt;
11393 if (!kvm_is_valid_sregs(vcpu, sregs))
11396 apic_base_msr.data = sregs->apic_base;
11397 apic_base_msr.host_initiated = true;
11398 if (kvm_set_apic_base(vcpu, &apic_base_msr))
11401 if (vcpu->arch.guest_state_protected)
11404 dt.size = sregs->idt.limit;
11405 dt.address = sregs->idt.base;
11406 static_call(kvm_x86_set_idt)(vcpu, &dt);
11407 dt.size = sregs->gdt.limit;
11408 dt.address = sregs->gdt.base;
11409 static_call(kvm_x86_set_gdt)(vcpu, &dt);
11411 vcpu->arch.cr2 = sregs->cr2;
11412 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
11413 vcpu->arch.cr3 = sregs->cr3;
11414 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11415 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
11417 kvm_set_cr8(vcpu, sregs->cr8);
11419 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
11420 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
11422 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
11423 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
11424 vcpu->arch.cr0 = sregs->cr0;
11426 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
11427 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
11429 if (update_pdptrs) {
11430 idx = srcu_read_lock(&vcpu->kvm->srcu);
11431 if (is_pae_paging(vcpu)) {
11432 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
11433 *mmu_reset_needed = 1;
11435 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11438 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11439 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11440 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11441 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11442 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11443 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11445 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11446 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11448 update_cr8_intercept(vcpu);
11450 /* Older userspace won't unhalt the vcpu on reset. */
11451 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
11452 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
11453 !is_protmode(vcpu))
11454 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11459 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11461 int pending_vec, max_bits;
11462 int mmu_reset_needed = 0;
11463 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
11468 if (mmu_reset_needed)
11469 kvm_mmu_reset_context(vcpu);
11471 max_bits = KVM_NR_INTERRUPTS;
11472 pending_vec = find_first_bit(
11473 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
11475 if (pending_vec < max_bits) {
11476 kvm_queue_interrupt(vcpu, pending_vec, false);
11477 pr_debug("Set back pending irq %d\n", pending_vec);
11478 kvm_make_request(KVM_REQ_EVENT, vcpu);
11483 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11485 int mmu_reset_needed = 0;
11486 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
11487 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
11488 !(sregs2->efer & EFER_LMA);
11491 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11494 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11497 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11498 &mmu_reset_needed, !valid_pdptrs);
11502 if (valid_pdptrs) {
11503 for (i = 0; i < 4 ; i++)
11504 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11506 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11507 mmu_reset_needed = 1;
11508 vcpu->arch.pdptrs_from_userspace = true;
11510 if (mmu_reset_needed)
11511 kvm_mmu_reset_context(vcpu);
11515 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11516 struct kvm_sregs *sregs)
11521 ret = __set_sregs(vcpu, sregs);
11526 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11529 struct kvm_vcpu *vcpu;
11535 down_write(&kvm->arch.apicv_update_lock);
11537 kvm_for_each_vcpu(i, vcpu, kvm) {
11538 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11543 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11544 up_write(&kvm->arch.apicv_update_lock);
11547 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11548 struct kvm_guest_debug *dbg)
11550 unsigned long rflags;
11553 if (vcpu->arch.guest_state_protected)
11558 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11560 if (kvm_is_exception_pending(vcpu))
11562 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11563 kvm_queue_exception(vcpu, DB_VECTOR);
11565 kvm_queue_exception(vcpu, BP_VECTOR);
11569 * Read rflags as long as potentially injected trace flags are still
11572 rflags = kvm_get_rflags(vcpu);
11574 vcpu->guest_debug = dbg->control;
11575 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11576 vcpu->guest_debug = 0;
11578 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11579 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11580 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11581 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11583 for (i = 0; i < KVM_NR_DB_REGS; i++)
11584 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11586 kvm_update_dr7(vcpu);
11588 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11589 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11592 * Trigger an rflags update that will inject or remove the trace
11595 kvm_set_rflags(vcpu, rflags);
11597 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11599 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11609 * Translate a guest virtual address to a guest physical address.
11611 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11612 struct kvm_translation *tr)
11614 unsigned long vaddr = tr->linear_address;
11620 idx = srcu_read_lock(&vcpu->kvm->srcu);
11621 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11622 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11623 tr->physical_address = gpa;
11624 tr->valid = gpa != INVALID_GPA;
11632 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11634 struct fxregs_state *fxsave;
11636 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11641 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11642 memcpy(fpu->fpr, fxsave->st_space, 128);
11643 fpu->fcw = fxsave->cwd;
11644 fpu->fsw = fxsave->swd;
11645 fpu->ftwx = fxsave->twd;
11646 fpu->last_opcode = fxsave->fop;
11647 fpu->last_ip = fxsave->rip;
11648 fpu->last_dp = fxsave->rdp;
11649 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11655 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11657 struct fxregs_state *fxsave;
11659 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11664 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11666 memcpy(fxsave->st_space, fpu->fpr, 128);
11667 fxsave->cwd = fpu->fcw;
11668 fxsave->swd = fpu->fsw;
11669 fxsave->twd = fpu->ftwx;
11670 fxsave->fop = fpu->last_opcode;
11671 fxsave->rip = fpu->last_ip;
11672 fxsave->rdp = fpu->last_dp;
11673 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11679 static void store_regs(struct kvm_vcpu *vcpu)
11681 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11683 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11684 __get_regs(vcpu, &vcpu->run->s.regs.regs);
11686 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11687 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11689 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11690 kvm_vcpu_ioctl_x86_get_vcpu_events(
11691 vcpu, &vcpu->run->s.regs.events);
11694 static int sync_regs(struct kvm_vcpu *vcpu)
11696 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11697 __set_regs(vcpu, &vcpu->run->s.regs.regs);
11698 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11700 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11701 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
11703 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11705 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11706 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
11707 vcpu, &vcpu->run->s.regs.events))
11709 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11715 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11717 if (kvm_check_tsc_unstable() && kvm->created_vcpus)
11718 pr_warn_once("SMP vm created on host with unstable TSC; "
11719 "guest TSC will not be reliable\n");
11721 if (!kvm->arch.max_vcpu_ids)
11722 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
11724 if (id >= kvm->arch.max_vcpu_ids)
11727 return static_call(kvm_x86_vcpu_precreate)(kvm);
11730 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11735 vcpu->arch.last_vmentry_cpu = -1;
11736 vcpu->arch.regs_avail = ~0;
11737 vcpu->arch.regs_dirty = ~0;
11739 kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm, vcpu, KVM_HOST_USES_PFN);
11741 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11742 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11744 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11746 r = kvm_mmu_create(vcpu);
11750 if (irqchip_in_kernel(vcpu->kvm)) {
11751 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11753 goto fail_mmu_destroy;
11756 * Defer evaluating inhibits until the vCPU is first run, as
11757 * this vCPU will not get notified of any changes until this
11758 * vCPU is visible to other vCPUs (marked online and added to
11759 * the set of vCPUs). Opportunistically mark APICv active as
11760 * VMX in particularly is highly unlikely to have inhibits.
11761 * Ignore the current per-VM APICv state so that vCPU creation
11762 * is guaranteed to run with a deterministic value, the request
11763 * will ensure the vCPU gets the correct state before VM-Entry.
11765 if (enable_apicv) {
11766 vcpu->arch.apic->apicv_active = true;
11767 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
11770 static_branch_inc(&kvm_has_noapic_vcpu);
11774 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11776 goto fail_free_lapic;
11777 vcpu->arch.pio_data = page_address(page);
11779 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
11780 GFP_KERNEL_ACCOUNT);
11781 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
11782 GFP_KERNEL_ACCOUNT);
11783 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
11784 goto fail_free_mce_banks;
11785 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11787 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11788 GFP_KERNEL_ACCOUNT))
11789 goto fail_free_mce_banks;
11791 if (!alloc_emulate_ctxt(vcpu))
11792 goto free_wbinvd_dirty_mask;
11794 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11795 pr_err("failed to allocate vcpu's fpu\n");
11796 goto free_emulate_ctxt;
11799 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11800 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11802 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11804 kvm_async_pf_hash_reset(vcpu);
11806 vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap;
11807 kvm_pmu_init(vcpu);
11809 vcpu->arch.pending_external_vector = -1;
11810 vcpu->arch.preempted_in_kernel = false;
11812 #if IS_ENABLED(CONFIG_HYPERV)
11813 vcpu->arch.hv_root_tdp = INVALID_PAGE;
11816 r = static_call(kvm_x86_vcpu_create)(vcpu);
11818 goto free_guest_fpu;
11820 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11821 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11822 kvm_xen_init_vcpu(vcpu);
11823 kvm_vcpu_mtrr_init(vcpu);
11825 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
11826 kvm_vcpu_reset(vcpu, false);
11827 kvm_init_mmu(vcpu);
11832 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11834 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11835 free_wbinvd_dirty_mask:
11836 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11837 fail_free_mce_banks:
11838 kfree(vcpu->arch.mce_banks);
11839 kfree(vcpu->arch.mci_ctl2_banks);
11840 free_page((unsigned long)vcpu->arch.pio_data);
11842 kvm_free_lapic(vcpu);
11844 kvm_mmu_destroy(vcpu);
11848 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11850 struct kvm *kvm = vcpu->kvm;
11852 if (mutex_lock_killable(&vcpu->mutex))
11855 kvm_synchronize_tsc(vcpu, 0);
11858 /* poll control enabled by default */
11859 vcpu->arch.msr_kvm_poll_control = 1;
11861 mutex_unlock(&vcpu->mutex);
11863 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11864 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
11865 KVMCLOCK_SYNC_PERIOD);
11868 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
11872 kvmclock_reset(vcpu);
11874 static_call(kvm_x86_vcpu_free)(vcpu);
11876 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11877 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11878 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11880 kvm_xen_destroy_vcpu(vcpu);
11881 kvm_hv_vcpu_uninit(vcpu);
11882 kvm_pmu_destroy(vcpu);
11883 kfree(vcpu->arch.mce_banks);
11884 kfree(vcpu->arch.mci_ctl2_banks);
11885 kvm_free_lapic(vcpu);
11886 idx = srcu_read_lock(&vcpu->kvm->srcu);
11887 kvm_mmu_destroy(vcpu);
11888 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11889 free_page((unsigned long)vcpu->arch.pio_data);
11890 kvfree(vcpu->arch.cpuid_entries);
11891 if (!lapic_in_kernel(vcpu))
11892 static_branch_dec(&kvm_has_noapic_vcpu);
11895 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
11897 struct kvm_cpuid_entry2 *cpuid_0x1;
11898 unsigned long old_cr0 = kvm_read_cr0(vcpu);
11899 unsigned long new_cr0;
11902 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
11903 * to handle side effects. RESET emulation hits those flows and relies
11904 * on emulated/virtualized registers, including those that are loaded
11905 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
11906 * to detect improper or missing initialization.
11908 WARN_ON_ONCE(!init_event &&
11909 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
11912 * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's
11913 * possible to INIT the vCPU while L2 is active. Force the vCPU back
11914 * into L1 as EFER.SVME is cleared on INIT (along with all other EFER
11915 * bits), i.e. virtualization is disabled.
11917 if (is_guest_mode(vcpu))
11918 kvm_leave_nested(vcpu);
11920 kvm_lapic_reset(vcpu, init_event);
11922 WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu));
11923 vcpu->arch.hflags = 0;
11925 vcpu->arch.smi_pending = 0;
11926 vcpu->arch.smi_count = 0;
11927 atomic_set(&vcpu->arch.nmi_queued, 0);
11928 vcpu->arch.nmi_pending = 0;
11929 vcpu->arch.nmi_injected = false;
11930 kvm_clear_interrupt_queue(vcpu);
11931 kvm_clear_exception_queue(vcpu);
11933 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
11934 kvm_update_dr0123(vcpu);
11935 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
11936 vcpu->arch.dr7 = DR7_FIXED_1;
11937 kvm_update_dr7(vcpu);
11939 vcpu->arch.cr2 = 0;
11941 kvm_make_request(KVM_REQ_EVENT, vcpu);
11942 vcpu->arch.apf.msr_en_val = 0;
11943 vcpu->arch.apf.msr_int_val = 0;
11944 vcpu->arch.st.msr_val = 0;
11946 kvmclock_reset(vcpu);
11948 kvm_clear_async_pf_completion_queue(vcpu);
11949 kvm_async_pf_hash_reset(vcpu);
11950 vcpu->arch.apf.halted = false;
11952 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
11953 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
11956 * All paths that lead to INIT are required to load the guest's
11957 * FPU state (because most paths are buried in KVM_RUN).
11960 kvm_put_guest_fpu(vcpu);
11962 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
11963 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
11966 kvm_load_guest_fpu(vcpu);
11970 kvm_pmu_reset(vcpu);
11971 vcpu->arch.smbase = 0x30000;
11973 vcpu->arch.msr_misc_features_enables = 0;
11974 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
11975 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
11977 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
11978 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
11981 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
11982 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
11983 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
11986 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
11987 * if no CPUID match is found. Note, it's impossible to get a match at
11988 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
11989 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
11990 * on RESET. But, go through the motions in case that's ever remedied.
11992 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1);
11993 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
11995 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
11997 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
11998 kvm_rip_write(vcpu, 0xfff0);
12000 vcpu->arch.cr3 = 0;
12001 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
12004 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
12005 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
12006 * (or qualify) that with a footnote stating that CD/NW are preserved.
12008 new_cr0 = X86_CR0_ET;
12010 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
12012 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
12014 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
12015 static_call(kvm_x86_set_cr4)(vcpu, 0);
12016 static_call(kvm_x86_set_efer)(vcpu, 0);
12017 static_call(kvm_x86_update_exception_bitmap)(vcpu);
12020 * On the standard CR0/CR4/EFER modification paths, there are several
12021 * complex conditions determining whether the MMU has to be reset and/or
12022 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
12023 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
12024 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
12025 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
12027 if (old_cr0 & X86_CR0_PG) {
12028 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12029 kvm_mmu_reset_context(vcpu);
12033 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
12034 * APM states the TLBs are untouched by INIT, but it also states that
12035 * the TLBs are flushed on "External initialization of the processor."
12036 * Flush the guest TLB regardless of vendor, there is no meaningful
12037 * benefit in relying on the guest to flush the TLB immediately after
12038 * INIT. A spurious TLB flush is benign and likely negligible from a
12039 * performance perspective.
12042 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12044 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
12046 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
12048 struct kvm_segment cs;
12050 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
12051 cs.selector = vector << 8;
12052 cs.base = vector << 12;
12053 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
12054 kvm_rip_write(vcpu, 0);
12056 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
12058 int kvm_arch_hardware_enable(void)
12061 struct kvm_vcpu *vcpu;
12066 bool stable, backwards_tsc = false;
12068 kvm_user_return_msr_cpu_online();
12070 ret = kvm_x86_check_processor_compatibility();
12074 ret = static_call(kvm_x86_hardware_enable)();
12078 local_tsc = rdtsc();
12079 stable = !kvm_check_tsc_unstable();
12080 list_for_each_entry(kvm, &vm_list, vm_list) {
12081 kvm_for_each_vcpu(i, vcpu, kvm) {
12082 if (!stable && vcpu->cpu == smp_processor_id())
12083 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
12084 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
12085 backwards_tsc = true;
12086 if (vcpu->arch.last_host_tsc > max_tsc)
12087 max_tsc = vcpu->arch.last_host_tsc;
12093 * Sometimes, even reliable TSCs go backwards. This happens on
12094 * platforms that reset TSC during suspend or hibernate actions, but
12095 * maintain synchronization. We must compensate. Fortunately, we can
12096 * detect that condition here, which happens early in CPU bringup,
12097 * before any KVM threads can be running. Unfortunately, we can't
12098 * bring the TSCs fully up to date with real time, as we aren't yet far
12099 * enough into CPU bringup that we know how much real time has actually
12100 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
12101 * variables that haven't been updated yet.
12103 * So we simply find the maximum observed TSC above, then record the
12104 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
12105 * the adjustment will be applied. Note that we accumulate
12106 * adjustments, in case multiple suspend cycles happen before some VCPU
12107 * gets a chance to run again. In the event that no KVM threads get a
12108 * chance to run, we will miss the entire elapsed period, as we'll have
12109 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
12110 * loose cycle time. This isn't too big a deal, since the loss will be
12111 * uniform across all VCPUs (not to mention the scenario is extremely
12112 * unlikely). It is possible that a second hibernate recovery happens
12113 * much faster than a first, causing the observed TSC here to be
12114 * smaller; this would require additional padding adjustment, which is
12115 * why we set last_host_tsc to the local tsc observed here.
12117 * N.B. - this code below runs only on platforms with reliable TSC,
12118 * as that is the only way backwards_tsc is set above. Also note
12119 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
12120 * have the same delta_cyc adjustment applied if backwards_tsc
12121 * is detected. Note further, this adjustment is only done once,
12122 * as we reset last_host_tsc on all VCPUs to stop this from being
12123 * called multiple times (one for each physical CPU bringup).
12125 * Platforms with unreliable TSCs don't have to deal with this, they
12126 * will be compensated by the logic in vcpu_load, which sets the TSC to
12127 * catchup mode. This will catchup all VCPUs to real time, but cannot
12128 * guarantee that they stay in perfect synchronization.
12130 if (backwards_tsc) {
12131 u64 delta_cyc = max_tsc - local_tsc;
12132 list_for_each_entry(kvm, &vm_list, vm_list) {
12133 kvm->arch.backwards_tsc_observed = true;
12134 kvm_for_each_vcpu(i, vcpu, kvm) {
12135 vcpu->arch.tsc_offset_adjustment += delta_cyc;
12136 vcpu->arch.last_host_tsc = local_tsc;
12137 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
12141 * We have to disable TSC offset matching.. if you were
12142 * booting a VM while issuing an S4 host suspend....
12143 * you may have some problem. Solving this issue is
12144 * left as an exercise to the reader.
12146 kvm->arch.last_tsc_nsec = 0;
12147 kvm->arch.last_tsc_write = 0;
12154 void kvm_arch_hardware_disable(void)
12156 static_call(kvm_x86_hardware_disable)();
12157 drop_user_return_notifiers();
12160 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
12162 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
12165 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
12167 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
12170 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
12171 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
12173 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
12175 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
12177 vcpu->arch.l1tf_flush_l1d = true;
12178 if (pmu->version && unlikely(pmu->event_count)) {
12179 pmu->need_cleanup = true;
12180 kvm_make_request(KVM_REQ_PMU, vcpu);
12182 static_call(kvm_x86_sched_in)(vcpu, cpu);
12185 void kvm_arch_free_vm(struct kvm *kvm)
12187 kfree(to_kvm_hv(kvm)->hv_pa_pg);
12188 __kvm_arch_free_vm(kvm);
12192 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
12195 unsigned long flags;
12200 ret = kvm_page_track_init(kvm);
12204 ret = kvm_mmu_init_vm(kvm);
12206 goto out_page_track;
12208 ret = static_call(kvm_x86_vm_init)(kvm);
12210 goto out_uninit_mmu;
12212 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
12213 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
12214 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
12216 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
12217 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
12218 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
12219 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
12220 &kvm->arch.irq_sources_bitmap);
12222 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
12223 mutex_init(&kvm->arch.apic_map_lock);
12224 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
12225 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
12227 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
12228 pvclock_update_vm_gtod_copy(kvm);
12229 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
12231 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
12232 kvm->arch.guest_can_read_msr_platform_info = true;
12233 kvm->arch.enable_pmu = enable_pmu;
12235 #if IS_ENABLED(CONFIG_HYPERV)
12236 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
12237 kvm->arch.hv_root_tdp = INVALID_PAGE;
12240 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
12241 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
12243 kvm_apicv_init(kvm);
12244 kvm_hv_init_vm(kvm);
12245 kvm_xen_init_vm(kvm);
12250 kvm_mmu_uninit_vm(kvm);
12252 kvm_page_track_cleanup(kvm);
12257 int kvm_arch_post_init_vm(struct kvm *kvm)
12259 return kvm_mmu_post_init_vm(kvm);
12262 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
12265 kvm_mmu_unload(vcpu);
12269 static void kvm_unload_vcpu_mmus(struct kvm *kvm)
12272 struct kvm_vcpu *vcpu;
12274 kvm_for_each_vcpu(i, vcpu, kvm) {
12275 kvm_clear_async_pf_completion_queue(vcpu);
12276 kvm_unload_vcpu_mmu(vcpu);
12280 void kvm_arch_sync_events(struct kvm *kvm)
12282 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
12283 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
12288 * __x86_set_memory_region: Setup KVM internal memory slot
12290 * @kvm: the kvm pointer to the VM.
12291 * @id: the slot ID to setup.
12292 * @gpa: the GPA to install the slot (unused when @size == 0).
12293 * @size: the size of the slot. Set to zero to uninstall a slot.
12295 * This function helps to setup a KVM internal memory slot. Specify
12296 * @size > 0 to install a new slot, while @size == 0 to uninstall a
12297 * slot. The return code can be one of the following:
12299 * HVA: on success (uninstall will return a bogus HVA)
12302 * The caller should always use IS_ERR() to check the return value
12303 * before use. Note, the KVM internal memory slots are guaranteed to
12304 * remain valid and unchanged until the VM is destroyed, i.e., the
12305 * GPA->HVA translation will not change. However, the HVA is a user
12306 * address, i.e. its accessibility is not guaranteed, and must be
12307 * accessed via __copy_{to,from}_user().
12309 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
12313 unsigned long hva, old_npages;
12314 struct kvm_memslots *slots = kvm_memslots(kvm);
12315 struct kvm_memory_slot *slot;
12317 /* Called with kvm->slots_lock held. */
12318 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
12319 return ERR_PTR_USR(-EINVAL);
12321 slot = id_to_memslot(slots, id);
12323 if (slot && slot->npages)
12324 return ERR_PTR_USR(-EEXIST);
12327 * MAP_SHARED to prevent internal slot pages from being moved
12330 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
12331 MAP_SHARED | MAP_ANONYMOUS, 0);
12332 if (IS_ERR_VALUE(hva))
12333 return (void __user *)hva;
12335 if (!slot || !slot->npages)
12338 old_npages = slot->npages;
12339 hva = slot->userspace_addr;
12342 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
12343 struct kvm_userspace_memory_region m;
12345 m.slot = id | (i << 16);
12347 m.guest_phys_addr = gpa;
12348 m.userspace_addr = hva;
12349 m.memory_size = size;
12350 r = __kvm_set_memory_region(kvm, &m);
12352 return ERR_PTR_USR(r);
12356 vm_munmap(hva, old_npages * PAGE_SIZE);
12358 return (void __user *)hva;
12360 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
12362 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
12364 kvm_mmu_pre_destroy_vm(kvm);
12367 void kvm_arch_destroy_vm(struct kvm *kvm)
12369 if (current->mm == kvm->mm) {
12371 * Free memory regions allocated on behalf of userspace,
12372 * unless the memory map has changed due to process exit
12375 mutex_lock(&kvm->slots_lock);
12376 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
12378 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
12380 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
12381 mutex_unlock(&kvm->slots_lock);
12383 kvm_unload_vcpu_mmus(kvm);
12384 static_call_cond(kvm_x86_vm_destroy)(kvm);
12385 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
12386 kvm_pic_destroy(kvm);
12387 kvm_ioapic_destroy(kvm);
12388 kvm_destroy_vcpus(kvm);
12389 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
12390 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
12391 kvm_mmu_uninit_vm(kvm);
12392 kvm_page_track_cleanup(kvm);
12393 kvm_xen_destroy_vm(kvm);
12394 kvm_hv_destroy_vm(kvm);
12397 static void memslot_rmap_free(struct kvm_memory_slot *slot)
12401 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12402 kvfree(slot->arch.rmap[i]);
12403 slot->arch.rmap[i] = NULL;
12407 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
12411 memslot_rmap_free(slot);
12413 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12414 kvfree(slot->arch.lpage_info[i - 1]);
12415 slot->arch.lpage_info[i - 1] = NULL;
12418 kvm_page_track_free_memslot(slot);
12421 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
12423 const int sz = sizeof(*slot->arch.rmap[0]);
12426 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12428 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12430 if (slot->arch.rmap[i])
12433 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
12434 if (!slot->arch.rmap[i]) {
12435 memslot_rmap_free(slot);
12443 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
12444 struct kvm_memory_slot *slot)
12446 unsigned long npages = slot->npages;
12450 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
12451 * old arrays will be freed by __kvm_set_memory_region() if installing
12452 * the new memslot is successful.
12454 memset(&slot->arch, 0, sizeof(slot->arch));
12456 if (kvm_memslots_have_rmaps(kvm)) {
12457 r = memslot_rmap_alloc(slot, npages);
12462 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12463 struct kvm_lpage_info *linfo;
12464 unsigned long ugfn;
12468 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12470 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
12474 slot->arch.lpage_info[i - 1] = linfo;
12476 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12477 linfo[0].disallow_lpage = 1;
12478 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12479 linfo[lpages - 1].disallow_lpage = 1;
12480 ugfn = slot->userspace_addr >> PAGE_SHIFT;
12482 * If the gfn and userspace address are not aligned wrt each
12483 * other, disable large page support for this slot.
12485 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12488 for (j = 0; j < lpages; ++j)
12489 linfo[j].disallow_lpage = 1;
12493 if (kvm_page_track_create_memslot(kvm, slot, npages))
12499 memslot_rmap_free(slot);
12501 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12502 kvfree(slot->arch.lpage_info[i - 1]);
12503 slot->arch.lpage_info[i - 1] = NULL;
12508 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12510 struct kvm_vcpu *vcpu;
12514 * memslots->generation has been incremented.
12515 * mmio generation may have reached its maximum value.
12517 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12519 /* Force re-initialization of steal_time cache */
12520 kvm_for_each_vcpu(i, vcpu, kvm)
12521 kvm_vcpu_kick(vcpu);
12524 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12525 const struct kvm_memory_slot *old,
12526 struct kvm_memory_slot *new,
12527 enum kvm_mr_change change)
12529 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
12530 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
12533 return kvm_alloc_memslot_metadata(kvm, new);
12536 if (change == KVM_MR_FLAGS_ONLY)
12537 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12538 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12545 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12549 if (!kvm_x86_ops.cpu_dirty_log_size)
12552 nr_slots = atomic_read(&kvm->nr_memslots_dirty_logging);
12553 if ((enable && nr_slots == 1) || !nr_slots)
12554 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12557 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12558 struct kvm_memory_slot *old,
12559 const struct kvm_memory_slot *new,
12560 enum kvm_mr_change change)
12562 u32 old_flags = old ? old->flags : 0;
12563 u32 new_flags = new ? new->flags : 0;
12564 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12567 * Update CPU dirty logging if dirty logging is being toggled. This
12568 * applies to all operations.
12570 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12571 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12574 * Nothing more to do for RO slots (which can't be dirtied and can't be
12575 * made writable) or CREATE/MOVE/DELETE of a slot.
12577 * For a memslot with dirty logging disabled:
12578 * CREATE: No dirty mappings will already exist.
12579 * MOVE/DELETE: The old mappings will already have been cleaned up by
12580 * kvm_arch_flush_shadow_memslot()
12582 * For a memslot with dirty logging enabled:
12583 * CREATE: No shadow pages exist, thus nothing to write-protect
12584 * and no dirty bits to clear.
12585 * MOVE/DELETE: The old mappings will already have been cleaned up by
12586 * kvm_arch_flush_shadow_memslot().
12588 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12592 * READONLY and non-flags changes were filtered out above, and the only
12593 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12594 * logging isn't being toggled on or off.
12596 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12599 if (!log_dirty_pages) {
12601 * Dirty logging tracks sptes in 4k granularity, meaning that
12602 * large sptes have to be split. If live migration succeeds,
12603 * the guest in the source machine will be destroyed and large
12604 * sptes will be created in the destination. However, if the
12605 * guest continues to run in the source machine (for example if
12606 * live migration fails), small sptes will remain around and
12607 * cause bad performance.
12609 * Scan sptes if dirty logging has been stopped, dropping those
12610 * which can be collapsed into a single large-page spte. Later
12611 * page faults will create the large-page sptes.
12613 kvm_mmu_zap_collapsible_sptes(kvm, new);
12616 * Initially-all-set does not require write protecting any page,
12617 * because they're all assumed to be dirty.
12619 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12622 if (READ_ONCE(eager_page_split))
12623 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12625 if (kvm_x86_ops.cpu_dirty_log_size) {
12626 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12627 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12629 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12633 * Unconditionally flush the TLBs after enabling dirty logging.
12634 * A flush is almost always going to be necessary (see below),
12635 * and unconditionally flushing allows the helpers to omit
12636 * the subtly complex checks when removing write access.
12638 * Do the flush outside of mmu_lock to reduce the amount of
12639 * time mmu_lock is held. Flushing after dropping mmu_lock is
12640 * safe as KVM only needs to guarantee the slot is fully
12641 * write-protected before returning to userspace, i.e. before
12642 * userspace can consume the dirty status.
12644 * Flushing outside of mmu_lock requires KVM to be careful when
12645 * making decisions based on writable status of an SPTE, e.g. a
12646 * !writable SPTE doesn't guarantee a CPU can't perform writes.
12648 * Specifically, KVM also write-protects guest page tables to
12649 * monitor changes when using shadow paging, and must guarantee
12650 * no CPUs can write to those page before mmu_lock is dropped.
12651 * Because CPUs may have stale TLB entries at this point, a
12652 * !writable SPTE doesn't guarantee CPUs can't perform writes.
12654 * KVM also allows making SPTES writable outside of mmu_lock,
12655 * e.g. to allow dirty logging without taking mmu_lock.
12657 * To handle these scenarios, KVM uses a separate software-only
12658 * bit (MMU-writable) to track if a SPTE is !writable due to
12659 * a guest page table being write-protected (KVM clears the
12660 * MMU-writable flag when write-protecting for shadow paging).
12662 * The use of MMU-writable is also the primary motivation for
12663 * the unconditional flush. Because KVM must guarantee that a
12664 * CPU doesn't contain stale, writable TLB entries for a
12665 * !MMU-writable SPTE, KVM must flush if it encounters any
12666 * MMU-writable SPTE regardless of whether the actual hardware
12667 * writable bit was set. I.e. KVM is almost guaranteed to need
12668 * to flush, while unconditionally flushing allows the "remove
12669 * write access" helpers to ignore MMU-writable entirely.
12671 * See is_writable_pte() for more details (the case involving
12672 * access-tracked SPTEs is particularly relevant).
12674 kvm_arch_flush_remote_tlbs_memslot(kvm, new);
12678 void kvm_arch_commit_memory_region(struct kvm *kvm,
12679 struct kvm_memory_slot *old,
12680 const struct kvm_memory_slot *new,
12681 enum kvm_mr_change change)
12683 if (!kvm->arch.n_requested_mmu_pages &&
12684 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12685 unsigned long nr_mmu_pages;
12687 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12688 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12689 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12692 kvm_mmu_slot_apply_flags(kvm, old, new, change);
12694 /* Free the arrays associated with the old memslot. */
12695 if (change == KVM_MR_MOVE)
12696 kvm_arch_free_memslot(kvm, old);
12699 void kvm_arch_flush_shadow_all(struct kvm *kvm)
12701 kvm_mmu_zap_all(kvm);
12704 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
12705 struct kvm_memory_slot *slot)
12707 kvm_page_track_flush_slot(kvm, slot);
12710 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12712 return (is_guest_mode(vcpu) &&
12713 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12716 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12718 if (!list_empty_careful(&vcpu->async_pf.done))
12721 if (kvm_apic_has_pending_init_or_sipi(vcpu) &&
12722 kvm_apic_init_sipi_allowed(vcpu))
12725 if (vcpu->arch.pv.pv_unhalted)
12728 if (kvm_is_exception_pending(vcpu))
12731 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12732 (vcpu->arch.nmi_pending &&
12733 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12736 #ifdef CONFIG_KVM_SMM
12737 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12738 (vcpu->arch.smi_pending &&
12739 static_call(kvm_x86_smi_allowed)(vcpu, false)))
12743 if (kvm_arch_interrupt_allowed(vcpu) &&
12744 (kvm_cpu_has_interrupt(vcpu) ||
12745 kvm_guest_apic_has_interrupt(vcpu)))
12748 if (kvm_hv_has_stimer_pending(vcpu))
12751 if (is_guest_mode(vcpu) &&
12752 kvm_x86_ops.nested_ops->has_events &&
12753 kvm_x86_ops.nested_ops->has_events(vcpu))
12756 if (kvm_xen_has_pending_events(vcpu))
12762 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12764 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12767 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12769 if (kvm_vcpu_apicv_active(vcpu) &&
12770 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12776 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12778 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12781 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12782 #ifdef CONFIG_KVM_SMM
12783 kvm_test_request(KVM_REQ_SMI, vcpu) ||
12785 kvm_test_request(KVM_REQ_EVENT, vcpu))
12788 return kvm_arch_dy_has_pending_interrupt(vcpu);
12791 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
12793 if (vcpu->arch.guest_state_protected)
12796 return vcpu->arch.preempted_in_kernel;
12799 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
12801 return kvm_rip_read(vcpu);
12804 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
12806 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
12809 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
12811 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
12814 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
12816 /* Can't read the RIP when guest state is protected, just return 0 */
12817 if (vcpu->arch.guest_state_protected)
12820 if (is_64_bit_mode(vcpu))
12821 return kvm_rip_read(vcpu);
12822 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
12823 kvm_rip_read(vcpu));
12825 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
12827 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
12829 return kvm_get_linear_rip(vcpu) == linear_rip;
12831 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
12833 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
12835 unsigned long rflags;
12837 rflags = static_call(kvm_x86_get_rflags)(vcpu);
12838 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12839 rflags &= ~X86_EFLAGS_TF;
12842 EXPORT_SYMBOL_GPL(kvm_get_rflags);
12844 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12846 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
12847 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
12848 rflags |= X86_EFLAGS_TF;
12849 static_call(kvm_x86_set_rflags)(vcpu, rflags);
12852 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12854 __kvm_set_rflags(vcpu, rflags);
12855 kvm_make_request(KVM_REQ_EVENT, vcpu);
12857 EXPORT_SYMBOL_GPL(kvm_set_rflags);
12859 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
12861 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
12863 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
12866 static inline u32 kvm_async_pf_next_probe(u32 key)
12868 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
12871 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12873 u32 key = kvm_async_pf_hash_fn(gfn);
12875 while (vcpu->arch.apf.gfns[key] != ~0)
12876 key = kvm_async_pf_next_probe(key);
12878 vcpu->arch.apf.gfns[key] = gfn;
12881 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
12884 u32 key = kvm_async_pf_hash_fn(gfn);
12886 for (i = 0; i < ASYNC_PF_PER_VCPU &&
12887 (vcpu->arch.apf.gfns[key] != gfn &&
12888 vcpu->arch.apf.gfns[key] != ~0); i++)
12889 key = kvm_async_pf_next_probe(key);
12894 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12896 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
12899 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12903 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
12905 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
12909 vcpu->arch.apf.gfns[i] = ~0;
12911 j = kvm_async_pf_next_probe(j);
12912 if (vcpu->arch.apf.gfns[j] == ~0)
12914 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
12916 * k lies cyclically in ]i,j]
12918 * |....j i.k.| or |.k..j i...|
12920 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
12921 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
12926 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
12928 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
12930 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
12934 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
12936 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12938 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12939 &token, offset, sizeof(token));
12942 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
12944 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12947 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12948 &val, offset, sizeof(val)))
12954 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
12957 if (!kvm_pv_async_pf_enabled(vcpu))
12960 if (vcpu->arch.apf.send_user_only &&
12961 static_call(kvm_x86_get_cpl)(vcpu) == 0)
12964 if (is_guest_mode(vcpu)) {
12966 * L1 needs to opt into the special #PF vmexits that are
12967 * used to deliver async page faults.
12969 return vcpu->arch.apf.delivery_as_pf_vmexit;
12972 * Play it safe in case the guest temporarily disables paging.
12973 * The real mode IDT in particular is unlikely to have a #PF
12976 return is_paging(vcpu);
12980 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
12982 if (unlikely(!lapic_in_kernel(vcpu) ||
12983 kvm_event_needs_reinjection(vcpu) ||
12984 kvm_is_exception_pending(vcpu)))
12987 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
12991 * If interrupts are off we cannot even use an artificial
12994 return kvm_arch_interrupt_allowed(vcpu);
12997 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
12998 struct kvm_async_pf *work)
13000 struct x86_exception fault;
13002 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
13003 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
13005 if (kvm_can_deliver_async_pf(vcpu) &&
13006 !apf_put_user_notpresent(vcpu)) {
13007 fault.vector = PF_VECTOR;
13008 fault.error_code_valid = true;
13009 fault.error_code = 0;
13010 fault.nested_page_fault = false;
13011 fault.address = work->arch.token;
13012 fault.async_page_fault = true;
13013 kvm_inject_page_fault(vcpu, &fault);
13017 * It is not possible to deliver a paravirtualized asynchronous
13018 * page fault, but putting the guest in an artificial halt state
13019 * can be beneficial nevertheless: if an interrupt arrives, we
13020 * can deliver it timely and perhaps the guest will schedule
13021 * another process. When the instruction that triggered a page
13022 * fault is retried, hopefully the page will be ready in the host.
13024 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
13029 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
13030 struct kvm_async_pf *work)
13032 struct kvm_lapic_irq irq = {
13033 .delivery_mode = APIC_DM_FIXED,
13034 .vector = vcpu->arch.apf.vec
13037 if (work->wakeup_all)
13038 work->arch.token = ~0; /* broadcast wakeup */
13040 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
13041 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
13043 if ((work->wakeup_all || work->notpresent_injected) &&
13044 kvm_pv_async_pf_enabled(vcpu) &&
13045 !apf_put_user_ready(vcpu, work->arch.token)) {
13046 vcpu->arch.apf.pageready_pending = true;
13047 kvm_apic_set_irq(vcpu, &irq, NULL);
13050 vcpu->arch.apf.halted = false;
13051 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13054 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
13056 kvm_make_request(KVM_REQ_APF_READY, vcpu);
13057 if (!vcpu->arch.apf.pageready_pending)
13058 kvm_vcpu_kick(vcpu);
13061 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
13063 if (!kvm_pv_async_pf_enabled(vcpu))
13066 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
13069 void kvm_arch_start_assignment(struct kvm *kvm)
13071 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
13072 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
13074 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
13076 void kvm_arch_end_assignment(struct kvm *kvm)
13078 atomic_dec(&kvm->arch.assigned_device_count);
13080 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
13082 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm)
13084 return arch_atomic_read(&kvm->arch.assigned_device_count);
13086 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
13088 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
13090 atomic_inc(&kvm->arch.noncoherent_dma_count);
13092 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
13094 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
13096 atomic_dec(&kvm->arch.noncoherent_dma_count);
13098 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
13100 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
13102 return atomic_read(&kvm->arch.noncoherent_dma_count);
13104 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
13106 bool kvm_arch_has_irq_bypass(void)
13111 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
13112 struct irq_bypass_producer *prod)
13114 struct kvm_kernel_irqfd *irqfd =
13115 container_of(cons, struct kvm_kernel_irqfd, consumer);
13118 irqfd->producer = prod;
13119 kvm_arch_start_assignment(irqfd->kvm);
13120 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
13121 prod->irq, irqfd->gsi, 1);
13124 kvm_arch_end_assignment(irqfd->kvm);
13129 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
13130 struct irq_bypass_producer *prod)
13133 struct kvm_kernel_irqfd *irqfd =
13134 container_of(cons, struct kvm_kernel_irqfd, consumer);
13136 WARN_ON(irqfd->producer != prod);
13137 irqfd->producer = NULL;
13140 * When producer of consumer is unregistered, we change back to
13141 * remapped mode, so we can re-use the current implementation
13142 * when the irq is masked/disabled or the consumer side (KVM
13143 * int this case doesn't want to receive the interrupts.
13145 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
13147 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
13148 " fails: %d\n", irqfd->consumer.token, ret);
13150 kvm_arch_end_assignment(irqfd->kvm);
13153 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
13154 uint32_t guest_irq, bool set)
13156 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
13159 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
13160 struct kvm_kernel_irq_routing_entry *new)
13162 if (new->type != KVM_IRQ_ROUTING_MSI)
13165 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
13168 bool kvm_vector_hashing_enabled(void)
13170 return vector_hashing;
13173 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
13175 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
13177 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
13180 int kvm_spec_ctrl_test_value(u64 value)
13183 * test that setting IA32_SPEC_CTRL to given value
13184 * is allowed by the host processor
13188 unsigned long flags;
13191 local_irq_save(flags);
13193 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
13195 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
13198 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
13200 local_irq_restore(flags);
13204 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
13206 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
13208 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
13209 struct x86_exception fault;
13210 u64 access = error_code &
13211 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
13213 if (!(error_code & PFERR_PRESENT_MASK) ||
13214 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) {
13216 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
13217 * tables probably do not match the TLB. Just proceed
13218 * with the error code that the processor gave.
13220 fault.vector = PF_VECTOR;
13221 fault.error_code_valid = true;
13222 fault.error_code = error_code;
13223 fault.nested_page_fault = false;
13224 fault.address = gva;
13225 fault.async_page_fault = false;
13227 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
13229 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
13232 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
13233 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
13234 * indicates whether exit to userspace is needed.
13236 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
13237 struct x86_exception *e)
13239 if (r == X86EMUL_PROPAGATE_FAULT) {
13240 if (KVM_BUG_ON(!e, vcpu->kvm))
13243 kvm_inject_emulated_page_fault(vcpu, e);
13248 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
13249 * while handling a VMX instruction KVM could've handled the request
13250 * correctly by exiting to userspace and performing I/O but there
13251 * doesn't seem to be a real use-case behind such requests, just return
13252 * KVM_EXIT_INTERNAL_ERROR for now.
13254 kvm_prepare_emulation_failure_exit(vcpu);
13258 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
13260 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
13263 struct x86_exception e;
13270 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
13271 if (r != X86EMUL_CONTINUE)
13272 return kvm_handle_memory_failure(vcpu, r, &e);
13274 if (operand.pcid >> 12 != 0) {
13275 kvm_inject_gp(vcpu, 0);
13279 pcid_enabled = kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE);
13282 case INVPCID_TYPE_INDIV_ADDR:
13283 if ((!pcid_enabled && (operand.pcid != 0)) ||
13284 is_noncanonical_address(operand.gla, vcpu)) {
13285 kvm_inject_gp(vcpu, 0);
13288 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
13289 return kvm_skip_emulated_instruction(vcpu);
13291 case INVPCID_TYPE_SINGLE_CTXT:
13292 if (!pcid_enabled && (operand.pcid != 0)) {
13293 kvm_inject_gp(vcpu, 0);
13297 kvm_invalidate_pcid(vcpu, operand.pcid);
13298 return kvm_skip_emulated_instruction(vcpu);
13300 case INVPCID_TYPE_ALL_NON_GLOBAL:
13302 * Currently, KVM doesn't mark global entries in the shadow
13303 * page tables, so a non-global flush just degenerates to a
13304 * global flush. If needed, we could optimize this later by
13305 * keeping track of global entries in shadow page tables.
13309 case INVPCID_TYPE_ALL_INCL_GLOBAL:
13310 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
13311 return kvm_skip_emulated_instruction(vcpu);
13314 kvm_inject_gp(vcpu, 0);
13318 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
13320 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
13322 struct kvm_run *run = vcpu->run;
13323 struct kvm_mmio_fragment *frag;
13326 BUG_ON(!vcpu->mmio_needed);
13328 /* Complete previous fragment */
13329 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
13330 len = min(8u, frag->len);
13331 if (!vcpu->mmio_is_write)
13332 memcpy(frag->data, run->mmio.data, len);
13334 if (frag->len <= 8) {
13335 /* Switch to the next fragment. */
13337 vcpu->mmio_cur_fragment++;
13339 /* Go forward to the next mmio piece. */
13345 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
13346 vcpu->mmio_needed = 0;
13348 // VMG change, at this point, we're always done
13349 // RIP has already been advanced
13353 // More MMIO is needed
13354 run->mmio.phys_addr = frag->gpa;
13355 run->mmio.len = min(8u, frag->len);
13356 run->mmio.is_write = vcpu->mmio_is_write;
13357 if (run->mmio.is_write)
13358 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
13359 run->exit_reason = KVM_EXIT_MMIO;
13361 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13366 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13370 struct kvm_mmio_fragment *frag;
13375 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13376 if (handled == bytes)
13383 /*TODO: Check if need to increment number of frags */
13384 frag = vcpu->mmio_fragments;
13385 vcpu->mmio_nr_fragments = 1;
13390 vcpu->mmio_needed = 1;
13391 vcpu->mmio_cur_fragment = 0;
13393 vcpu->run->mmio.phys_addr = gpa;
13394 vcpu->run->mmio.len = min(8u, frag->len);
13395 vcpu->run->mmio.is_write = 1;
13396 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
13397 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13399 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13403 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
13405 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13409 struct kvm_mmio_fragment *frag;
13414 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13415 if (handled == bytes)
13422 /*TODO: Check if need to increment number of frags */
13423 frag = vcpu->mmio_fragments;
13424 vcpu->mmio_nr_fragments = 1;
13429 vcpu->mmio_needed = 1;
13430 vcpu->mmio_cur_fragment = 0;
13432 vcpu->run->mmio.phys_addr = gpa;
13433 vcpu->run->mmio.len = min(8u, frag->len);
13434 vcpu->run->mmio.is_write = 0;
13435 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13437 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13441 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
13443 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size)
13445 vcpu->arch.sev_pio_count -= count;
13446 vcpu->arch.sev_pio_data += count * size;
13449 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13450 unsigned int port);
13452 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
13454 int size = vcpu->arch.pio.size;
13455 int port = vcpu->arch.pio.port;
13457 vcpu->arch.pio.count = 0;
13458 if (vcpu->arch.sev_pio_count)
13459 return kvm_sev_es_outs(vcpu, size, port);
13463 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13467 unsigned int count =
13468 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13469 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
13471 /* memcpy done already by emulator_pio_out. */
13472 advance_sev_es_emulated_pio(vcpu, count, size);
13476 /* Emulation done by the kernel. */
13477 if (!vcpu->arch.sev_pio_count)
13481 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
13485 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13486 unsigned int port);
13488 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
13490 unsigned count = vcpu->arch.pio.count;
13491 int size = vcpu->arch.pio.size;
13492 int port = vcpu->arch.pio.port;
13494 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
13495 advance_sev_es_emulated_pio(vcpu, count, size);
13496 if (vcpu->arch.sev_pio_count)
13497 return kvm_sev_es_ins(vcpu, size, port);
13501 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13505 unsigned int count =
13506 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13507 if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count))
13510 /* Emulation done by the kernel. */
13511 advance_sev_es_emulated_pio(vcpu, count, size);
13512 if (!vcpu->arch.sev_pio_count)
13516 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13520 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13521 unsigned int port, void *data, unsigned int count,
13524 vcpu->arch.sev_pio_data = data;
13525 vcpu->arch.sev_pio_count = count;
13526 return in ? kvm_sev_es_ins(vcpu, size, port)
13527 : kvm_sev_es_outs(vcpu, size, port);
13529 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13531 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13532 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13533 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13534 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13535 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13536 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13537 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13538 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter);
13539 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13540 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13541 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13542 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13543 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13544 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13545 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13546 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13547 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13548 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13549 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13550 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13551 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13552 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13553 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath);
13554 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell);
13555 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13556 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13557 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13558 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13559 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13561 static int __init kvm_x86_init(void)
13563 kvm_mmu_x86_module_init();
13564 mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible();
13567 module_init(kvm_x86_init);
13569 static void __exit kvm_x86_exit(void)
13572 * If module_init() is implemented, module_exit() must also be
13573 * implemented to allow module unload.
13576 module_exit(kvm_x86_exit);