1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/kvm_host.h>
26 #include "kvm_cache_regs.h"
27 #include "kvm_emulate.h"
36 #include <linux/clocksource.h>
37 #include <linux/interrupt.h>
38 #include <linux/kvm.h>
40 #include <linux/vmalloc.h>
41 #include <linux/export.h>
42 #include <linux/moduleparam.h>
43 #include <linux/mman.h>
44 #include <linux/highmem.h>
45 #include <linux/iommu.h>
46 #include <linux/cpufreq.h>
47 #include <linux/user-return-notifier.h>
48 #include <linux/srcu.h>
49 #include <linux/slab.h>
50 #include <linux/perf_event.h>
51 #include <linux/uaccess.h>
52 #include <linux/hash.h>
53 #include <linux/pci.h>
54 #include <linux/timekeeper_internal.h>
55 #include <linux/pvclock_gtod.h>
56 #include <linux/kvm_irqfd.h>
57 #include <linux/irqbypass.h>
58 #include <linux/sched/stat.h>
59 #include <linux/sched/isolation.h>
60 #include <linux/mem_encrypt.h>
61 #include <linux/entry-kvm.h>
62 #include <linux/suspend.h>
63 #include <linux/smp.h>
65 #include <trace/events/ipi.h>
66 #include <trace/events/kvm.h>
68 #include <asm/debugreg.h>
73 #include <linux/kernel_stat.h>
74 #include <asm/fpu/api.h>
75 #include <asm/fpu/xcr.h>
76 #include <asm/fpu/xstate.h>
77 #include <asm/pvclock.h>
78 #include <asm/div64.h>
79 #include <asm/irq_remapping.h>
80 #include <asm/mshyperv.h>
81 #include <asm/hypervisor.h>
82 #include <asm/tlbflush.h>
83 #include <asm/intel_pt.h>
84 #include <asm/emulate_prefix.h>
86 #include <clocksource/hyperv_timer.h>
88 #define CREATE_TRACE_POINTS
91 #define MAX_IO_MSRS 256
92 #define KVM_MAX_MCE_BANKS 32
94 struct kvm_caps kvm_caps __read_mostly = {
95 .supported_mce_cap = MCG_CTL_P | MCG_SER_P,
97 EXPORT_SYMBOL_GPL(kvm_caps);
99 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
101 #define emul_to_vcpu(ctxt) \
102 ((struct kvm_vcpu *)(ctxt)->vcpu)
105 * - enable syscall per default because its emulated by KVM
106 * - enable LME and LMA per default on 64 bit KVM
110 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
112 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
115 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
117 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
119 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
121 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
122 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
124 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
125 static void process_nmi(struct kvm_vcpu *vcpu);
126 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
127 static void store_regs(struct kvm_vcpu *vcpu);
128 static int sync_regs(struct kvm_vcpu *vcpu);
129 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
131 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
132 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
134 static DEFINE_MUTEX(vendor_module_lock);
135 struct kvm_x86_ops kvm_x86_ops __read_mostly;
137 #define KVM_X86_OP(func) \
138 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
139 *(((struct kvm_x86_ops *)0)->func));
140 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
141 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
142 #include <asm/kvm-x86-ops.h>
143 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
144 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
146 static bool __read_mostly ignore_msrs = 0;
147 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
149 bool __read_mostly report_ignored_msrs = true;
150 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
151 EXPORT_SYMBOL_GPL(report_ignored_msrs);
153 unsigned int min_timer_period_us = 200;
154 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
156 static bool __read_mostly kvmclock_periodic_sync = true;
157 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
159 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
160 static u32 __read_mostly tsc_tolerance_ppm = 250;
161 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
164 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
165 * adaptive tuning starting from default advancement of 1000ns. '0' disables
166 * advancement entirely. Any other value is used as-is and disables adaptive
167 * tuning, i.e. allows privileged userspace to set an exact advancement time.
169 static int __read_mostly lapic_timer_advance_ns = -1;
170 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
172 static bool __read_mostly vector_hashing = true;
173 module_param(vector_hashing, bool, S_IRUGO);
175 bool __read_mostly enable_vmware_backdoor = false;
176 module_param(enable_vmware_backdoor, bool, S_IRUGO);
177 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
180 * Flags to manipulate forced emulation behavior (any non-zero value will
181 * enable forced emulation).
183 #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1)
184 static int __read_mostly force_emulation_prefix;
185 module_param(force_emulation_prefix, int, 0644);
187 int __read_mostly pi_inject_timer = -1;
188 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
190 /* Enable/disable PMU virtualization */
191 bool __read_mostly enable_pmu = true;
192 EXPORT_SYMBOL_GPL(enable_pmu);
193 module_param(enable_pmu, bool, 0444);
195 bool __read_mostly eager_page_split = true;
196 module_param(eager_page_split, bool, 0644);
198 /* Enable/disable SMT_RSB bug mitigation */
199 static bool __read_mostly mitigate_smt_rsb;
200 module_param(mitigate_smt_rsb, bool, 0444);
203 * Restoring the host value for MSRs that are only consumed when running in
204 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
205 * returns to userspace, i.e. the kernel can run with the guest's value.
207 #define KVM_MAX_NR_USER_RETURN_MSRS 16
209 struct kvm_user_return_msrs {
210 struct user_return_notifier urn;
212 struct kvm_user_return_msr_values {
215 } values[KVM_MAX_NR_USER_RETURN_MSRS];
218 u32 __read_mostly kvm_nr_uret_msrs;
219 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
220 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
221 static struct kvm_user_return_msrs __percpu *user_return_msrs;
223 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
224 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
225 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
226 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
228 u64 __read_mostly host_efer;
229 EXPORT_SYMBOL_GPL(host_efer);
231 bool __read_mostly allow_smaller_maxphyaddr = 0;
232 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
234 bool __read_mostly enable_apicv = true;
235 EXPORT_SYMBOL_GPL(enable_apicv);
237 u64 __read_mostly host_xss;
238 EXPORT_SYMBOL_GPL(host_xss);
240 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
241 KVM_GENERIC_VM_STATS(),
242 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
243 STATS_DESC_COUNTER(VM, mmu_pte_write),
244 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
245 STATS_DESC_COUNTER(VM, mmu_flooded),
246 STATS_DESC_COUNTER(VM, mmu_recycled),
247 STATS_DESC_COUNTER(VM, mmu_cache_miss),
248 STATS_DESC_ICOUNTER(VM, mmu_unsync),
249 STATS_DESC_ICOUNTER(VM, pages_4k),
250 STATS_DESC_ICOUNTER(VM, pages_2m),
251 STATS_DESC_ICOUNTER(VM, pages_1g),
252 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
253 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
254 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
257 const struct kvm_stats_header kvm_vm_stats_header = {
258 .name_size = KVM_STATS_NAME_SIZE,
259 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
260 .id_offset = sizeof(struct kvm_stats_header),
261 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
262 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
263 sizeof(kvm_vm_stats_desc),
266 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
267 KVM_GENERIC_VCPU_STATS(),
268 STATS_DESC_COUNTER(VCPU, pf_taken),
269 STATS_DESC_COUNTER(VCPU, pf_fixed),
270 STATS_DESC_COUNTER(VCPU, pf_emulate),
271 STATS_DESC_COUNTER(VCPU, pf_spurious),
272 STATS_DESC_COUNTER(VCPU, pf_fast),
273 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created),
274 STATS_DESC_COUNTER(VCPU, pf_guest),
275 STATS_DESC_COUNTER(VCPU, tlb_flush),
276 STATS_DESC_COUNTER(VCPU, invlpg),
277 STATS_DESC_COUNTER(VCPU, exits),
278 STATS_DESC_COUNTER(VCPU, io_exits),
279 STATS_DESC_COUNTER(VCPU, mmio_exits),
280 STATS_DESC_COUNTER(VCPU, signal_exits),
281 STATS_DESC_COUNTER(VCPU, irq_window_exits),
282 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
283 STATS_DESC_COUNTER(VCPU, l1d_flush),
284 STATS_DESC_COUNTER(VCPU, halt_exits),
285 STATS_DESC_COUNTER(VCPU, request_irq_exits),
286 STATS_DESC_COUNTER(VCPU, irq_exits),
287 STATS_DESC_COUNTER(VCPU, host_state_reload),
288 STATS_DESC_COUNTER(VCPU, fpu_reload),
289 STATS_DESC_COUNTER(VCPU, insn_emulation),
290 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
291 STATS_DESC_COUNTER(VCPU, hypercalls),
292 STATS_DESC_COUNTER(VCPU, irq_injections),
293 STATS_DESC_COUNTER(VCPU, nmi_injections),
294 STATS_DESC_COUNTER(VCPU, req_event),
295 STATS_DESC_COUNTER(VCPU, nested_run),
296 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
297 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
298 STATS_DESC_COUNTER(VCPU, preemption_reported),
299 STATS_DESC_COUNTER(VCPU, preemption_other),
300 STATS_DESC_IBOOLEAN(VCPU, guest_mode),
301 STATS_DESC_COUNTER(VCPU, notify_window_exits),
304 const struct kvm_stats_header kvm_vcpu_stats_header = {
305 .name_size = KVM_STATS_NAME_SIZE,
306 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
307 .id_offset = sizeof(struct kvm_stats_header),
308 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
309 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
310 sizeof(kvm_vcpu_stats_desc),
313 u64 __read_mostly host_xcr0;
315 static struct kmem_cache *x86_emulator_cache;
318 * When called, it means the previous get/set msr reached an invalid msr.
319 * Return true if we want to ignore/silent this failed msr access.
321 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
323 const char *op = write ? "wrmsr" : "rdmsr";
326 if (report_ignored_msrs)
327 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
332 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
338 static struct kmem_cache *kvm_alloc_emulator_cache(void)
340 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
341 unsigned int size = sizeof(struct x86_emulate_ctxt);
343 return kmem_cache_create_usercopy("x86_emulator", size,
344 __alignof__(struct x86_emulate_ctxt),
345 SLAB_ACCOUNT, useroffset,
346 size - useroffset, NULL);
349 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
351 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
354 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
355 vcpu->arch.apf.gfns[i] = ~0;
358 static void kvm_on_user_return(struct user_return_notifier *urn)
361 struct kvm_user_return_msrs *msrs
362 = container_of(urn, struct kvm_user_return_msrs, urn);
363 struct kvm_user_return_msr_values *values;
367 * Disabling irqs at this point since the following code could be
368 * interrupted and executed through kvm_arch_hardware_disable()
370 local_irq_save(flags);
371 if (msrs->registered) {
372 msrs->registered = false;
373 user_return_notifier_unregister(urn);
375 local_irq_restore(flags);
376 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
377 values = &msrs->values[slot];
378 if (values->host != values->curr) {
379 wrmsrl(kvm_uret_msrs_list[slot], values->host);
380 values->curr = values->host;
385 static int kvm_probe_user_return_msr(u32 msr)
391 ret = rdmsrl_safe(msr, &val);
394 ret = wrmsrl_safe(msr, val);
400 int kvm_add_user_return_msr(u32 msr)
402 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
404 if (kvm_probe_user_return_msr(msr))
407 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
408 return kvm_nr_uret_msrs++;
410 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
412 int kvm_find_user_return_msr(u32 msr)
416 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
417 if (kvm_uret_msrs_list[i] == msr)
422 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
424 static void kvm_user_return_msr_cpu_online(void)
426 unsigned int cpu = smp_processor_id();
427 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
431 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
432 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
433 msrs->values[i].host = value;
434 msrs->values[i].curr = value;
438 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
440 unsigned int cpu = smp_processor_id();
441 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
444 value = (value & mask) | (msrs->values[slot].host & ~mask);
445 if (value == msrs->values[slot].curr)
447 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
451 msrs->values[slot].curr = value;
452 if (!msrs->registered) {
453 msrs->urn.on_user_return = kvm_on_user_return;
454 user_return_notifier_register(&msrs->urn);
455 msrs->registered = true;
459 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
461 static void drop_user_return_notifiers(void)
463 unsigned int cpu = smp_processor_id();
464 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
466 if (msrs->registered)
467 kvm_on_user_return(&msrs->urn);
470 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
472 return vcpu->arch.apic_base;
475 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
477 return kvm_apic_mode(kvm_get_apic_base(vcpu));
479 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
481 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
483 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
484 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
485 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
486 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
488 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
490 if (!msr_info->host_initiated) {
491 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
493 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
497 kvm_lapic_set_base(vcpu, msr_info->data);
498 kvm_recalculate_apic_map(vcpu->kvm);
503 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
505 * Hardware virtualization extension instructions may fault if a reboot turns
506 * off virtualization while processes are running. Usually after catching the
507 * fault we just panic; during reboot instead the instruction is ignored.
509 noinstr void kvm_spurious_fault(void)
511 /* Fault while not rebooting. We want the trace. */
512 BUG_ON(!kvm_rebooting);
514 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
516 #define EXCPT_BENIGN 0
517 #define EXCPT_CONTRIBUTORY 1
520 static int exception_class(int vector)
530 return EXCPT_CONTRIBUTORY;
537 #define EXCPT_FAULT 0
539 #define EXCPT_ABORT 2
540 #define EXCPT_INTERRUPT 3
543 static int exception_type(int vector)
547 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
548 return EXCPT_INTERRUPT;
553 * #DBs can be trap-like or fault-like, the caller must check other CPU
554 * state, e.g. DR6, to determine whether a #DB is a trap or fault.
556 if (mask & (1 << DB_VECTOR))
559 if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR)))
562 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
565 /* Reserved exceptions will result in fault */
569 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
570 struct kvm_queued_exception *ex)
572 if (!ex->has_payload)
575 switch (ex->vector) {
578 * "Certain debug exceptions may clear bit 0-3. The
579 * remaining contents of the DR6 register are never
580 * cleared by the processor".
582 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
584 * In order to reflect the #DB exception payload in guest
585 * dr6, three components need to be considered: active low
586 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
588 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
589 * In the target guest dr6:
590 * FIXED_1 bits should always be set.
591 * Active low bits should be cleared if 1-setting in payload.
592 * Active high bits should be set if 1-setting in payload.
594 * Note, the payload is compatible with the pending debug
595 * exceptions/exit qualification under VMX, that active_low bits
596 * are active high in payload.
597 * So they need to be flipped for DR6.
599 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
600 vcpu->arch.dr6 |= ex->payload;
601 vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW;
604 * The #DB payload is defined as compatible with the 'pending
605 * debug exceptions' field under VMX, not DR6. While bit 12 is
606 * defined in the 'pending debug exceptions' field (enabled
607 * breakpoint), it is reserved and must be zero in DR6.
609 vcpu->arch.dr6 &= ~BIT(12);
612 vcpu->arch.cr2 = ex->payload;
616 ex->has_payload = false;
619 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
621 static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector,
622 bool has_error_code, u32 error_code,
623 bool has_payload, unsigned long payload)
625 struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit;
628 ex->injected = false;
630 ex->has_error_code = has_error_code;
631 ex->error_code = error_code;
632 ex->has_payload = has_payload;
633 ex->payload = payload;
636 /* Forcibly leave the nested mode in cases like a vCPU reset */
637 static void kvm_leave_nested(struct kvm_vcpu *vcpu)
639 kvm_x86_ops.nested_ops->leave_nested(vcpu);
642 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
643 unsigned nr, bool has_error, u32 error_code,
644 bool has_payload, unsigned long payload, bool reinject)
649 kvm_make_request(KVM_REQ_EVENT, vcpu);
652 * If the exception is destined for L2 and isn't being reinjected,
653 * morph it to a VM-Exit if L1 wants to intercept the exception. A
654 * previously injected exception is not checked because it was checked
655 * when it was original queued, and re-checking is incorrect if _L1_
656 * injected the exception, in which case it's exempt from interception.
658 if (!reinject && is_guest_mode(vcpu) &&
659 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) {
660 kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code,
661 has_payload, payload);
665 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
669 * On VM-Entry, an exception can be pending if and only
670 * if event injection was blocked by nested_run_pending.
671 * In that case, however, vcpu_enter_guest() requests an
672 * immediate exit, and the guest shouldn't proceed far
673 * enough to need reinjection.
675 WARN_ON_ONCE(kvm_is_exception_pending(vcpu));
676 vcpu->arch.exception.injected = true;
677 if (WARN_ON_ONCE(has_payload)) {
679 * A reinjected event has already
680 * delivered its payload.
686 vcpu->arch.exception.pending = true;
687 vcpu->arch.exception.injected = false;
689 vcpu->arch.exception.has_error_code = has_error;
690 vcpu->arch.exception.vector = nr;
691 vcpu->arch.exception.error_code = error_code;
692 vcpu->arch.exception.has_payload = has_payload;
693 vcpu->arch.exception.payload = payload;
694 if (!is_guest_mode(vcpu))
695 kvm_deliver_exception_payload(vcpu,
696 &vcpu->arch.exception);
700 /* to check exception */
701 prev_nr = vcpu->arch.exception.vector;
702 if (prev_nr == DF_VECTOR) {
703 /* triple fault -> shutdown */
704 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
707 class1 = exception_class(prev_nr);
708 class2 = exception_class(nr);
709 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) ||
710 (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
712 * Synthesize #DF. Clear the previously injected or pending
713 * exception so as not to incorrectly trigger shutdown.
715 vcpu->arch.exception.injected = false;
716 vcpu->arch.exception.pending = false;
718 kvm_queue_exception_e(vcpu, DF_VECTOR, 0);
720 /* replace previous exception with a new one in a hope
721 that instruction re-execution will regenerate lost
727 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
729 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
731 EXPORT_SYMBOL_GPL(kvm_queue_exception);
733 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
735 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
737 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
739 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
740 unsigned long payload)
742 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
744 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
746 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
747 u32 error_code, unsigned long payload)
749 kvm_multiple_exception(vcpu, nr, true, error_code,
750 true, payload, false);
753 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
756 kvm_inject_gp(vcpu, 0);
758 return kvm_skip_emulated_instruction(vcpu);
762 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
764 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
767 kvm_inject_gp(vcpu, 0);
771 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
772 EMULTYPE_COMPLETE_USER_EXIT);
775 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
777 ++vcpu->stat.pf_guest;
780 * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of
781 * whether or not L1 wants to intercept "regular" #PF.
783 if (is_guest_mode(vcpu) && fault->async_page_fault)
784 kvm_queue_exception_vmexit(vcpu, PF_VECTOR,
785 true, fault->error_code,
786 true, fault->address);
788 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
792 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
793 struct x86_exception *fault)
795 struct kvm_mmu *fault_mmu;
796 WARN_ON_ONCE(fault->vector != PF_VECTOR);
798 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
802 * Invalidate the TLB entry for the faulting address, if it exists,
803 * else the access will fault indefinitely (and to emulate hardware).
805 if ((fault->error_code & PFERR_PRESENT_MASK) &&
806 !(fault->error_code & PFERR_RSVD_MASK))
807 kvm_mmu_invalidate_addr(vcpu, fault_mmu, fault->address,
808 KVM_MMU_ROOT_CURRENT);
810 fault_mmu->inject_page_fault(vcpu, fault);
812 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
814 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
816 atomic_inc(&vcpu->arch.nmi_queued);
817 kvm_make_request(KVM_REQ_NMI, vcpu);
820 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
822 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
824 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
826 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
828 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
830 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
833 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
834 * a #GP and return false.
836 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
838 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
840 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
844 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
846 if ((dr != 4 && dr != 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE))
849 kvm_queue_exception(vcpu, UD_VECTOR);
852 EXPORT_SYMBOL_GPL(kvm_require_dr);
854 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
856 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
860 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
862 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
864 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
865 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
869 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
872 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
875 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
876 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
877 if (real_gpa == INVALID_GPA)
880 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
881 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
882 cr3 & GENMASK(11, 5), sizeof(pdpte));
886 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
887 if ((pdpte[i] & PT_PRESENT_MASK) &&
888 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
894 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
895 * Shadow page roots need to be reconstructed instead.
897 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
898 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
900 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
901 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
902 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
903 vcpu->arch.pdptrs_from_userspace = false;
907 EXPORT_SYMBOL_GPL(load_pdptrs);
909 static bool kvm_is_valid_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
912 if (cr0 & 0xffffffff00000000UL)
916 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
919 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
922 return static_call(kvm_x86_is_valid_cr0)(vcpu, cr0);
925 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
928 * CR0.WP is incorporated into the MMU role, but only for non-nested,
929 * indirect shadow MMUs. If paging is disabled, no updates are needed
930 * as there are no permission bits to emulate. If TDP is enabled, the
931 * MMU's metadata needs to be updated, e.g. so that emulating guest
932 * translations does the right thing, but there's no need to unload the
933 * root as CR0.WP doesn't affect SPTEs.
935 if ((cr0 ^ old_cr0) == X86_CR0_WP) {
936 if (!(cr0 & X86_CR0_PG))
945 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
946 kvm_clear_async_pf_completion_queue(vcpu);
947 kvm_async_pf_hash_reset(vcpu);
950 * Clearing CR0.PG is defined to flush the TLB from the guest's
953 if (!(cr0 & X86_CR0_PG))
954 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
957 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
958 kvm_mmu_reset_context(vcpu);
960 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
961 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
962 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
963 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
965 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
967 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
969 unsigned long old_cr0 = kvm_read_cr0(vcpu);
971 if (!kvm_is_valid_cr0(vcpu, cr0))
976 /* Write to CR0 reserved bits are ignored, even on Intel. */
977 cr0 &= ~CR0_RESERVED_BITS;
980 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
981 (cr0 & X86_CR0_PG)) {
986 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
991 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
992 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
993 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
996 if (!(cr0 & X86_CR0_PG) &&
997 (is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)))
1000 static_call(kvm_x86_set_cr0)(vcpu, cr0);
1002 kvm_post_set_cr0(vcpu, old_cr0, cr0);
1006 EXPORT_SYMBOL_GPL(kvm_set_cr0);
1008 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
1010 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
1012 EXPORT_SYMBOL_GPL(kvm_lmsw);
1014 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
1016 if (vcpu->arch.guest_state_protected)
1019 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1021 if (vcpu->arch.xcr0 != host_xcr0)
1022 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
1024 if (vcpu->arch.xsaves_enabled &&
1025 vcpu->arch.ia32_xss != host_xss)
1026 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
1029 if (cpu_feature_enabled(X86_FEATURE_PKU) &&
1030 vcpu->arch.pkru != vcpu->arch.host_pkru &&
1031 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1032 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)))
1033 write_pkru(vcpu->arch.pkru);
1035 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
1037 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
1039 if (vcpu->arch.guest_state_protected)
1042 if (cpu_feature_enabled(X86_FEATURE_PKU) &&
1043 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1044 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) {
1045 vcpu->arch.pkru = rdpkru();
1046 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
1047 write_pkru(vcpu->arch.host_pkru);
1050 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1052 if (vcpu->arch.xcr0 != host_xcr0)
1053 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
1055 if (vcpu->arch.xsaves_enabled &&
1056 vcpu->arch.ia32_xss != host_xss)
1057 wrmsrl(MSR_IA32_XSS, host_xss);
1061 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1063 #ifdef CONFIG_X86_64
1064 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1066 return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC;
1070 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1073 u64 old_xcr0 = vcpu->arch.xcr0;
1076 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1077 if (index != XCR_XFEATURE_ENABLED_MASK)
1079 if (!(xcr0 & XFEATURE_MASK_FP))
1081 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1085 * Do not allow the guest to set bits that we do not support
1086 * saving. However, xcr0 bit 0 is always set, even if the
1087 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1089 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
1090 if (xcr0 & ~valid_bits)
1093 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1094 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1097 if (xcr0 & XFEATURE_MASK_AVX512) {
1098 if (!(xcr0 & XFEATURE_MASK_YMM))
1100 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1104 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1105 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1108 vcpu->arch.xcr0 = xcr0;
1110 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1111 kvm_update_cpuid_runtime(vcpu);
1115 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1117 /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
1118 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1119 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1120 kvm_inject_gp(vcpu, 0);
1124 return kvm_skip_emulated_instruction(vcpu);
1126 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1128 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1130 if (cr4 & cr4_reserved_bits)
1133 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1138 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4);
1140 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1142 return __kvm_is_valid_cr4(vcpu, cr4) &&
1143 static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1146 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1148 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1149 kvm_mmu_reset_context(vcpu);
1152 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1153 * according to the SDM; however, stale prev_roots could be reused
1154 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1155 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1156 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1160 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1161 kvm_mmu_unload(vcpu);
1164 * The TLB has to be flushed for all PCIDs if any of the following
1165 * (architecturally required) changes happen:
1166 * - CR4.PCIDE is changed from 1 to 0
1167 * - CR4.PGE is toggled
1169 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1171 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1172 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1173 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1176 * The TLB has to be flushed for the current PCID if any of the
1177 * following (architecturally required) changes happen:
1178 * - CR4.SMEP is changed from 0 to 1
1179 * - CR4.PAE is toggled
1181 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1182 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1183 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1186 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1188 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1190 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1192 if (!kvm_is_valid_cr4(vcpu, cr4))
1195 if (is_long_mode(vcpu)) {
1196 if (!(cr4 & X86_CR4_PAE))
1198 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1200 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1201 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1202 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1205 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1206 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1207 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1211 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1213 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1217 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1219 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1221 struct kvm_mmu *mmu = vcpu->arch.mmu;
1222 unsigned long roots_to_free = 0;
1226 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1227 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1228 * also via the emulator. KVM's TDP page tables are not in the scope of
1229 * the invalidation, but the guest's TLB entries need to be flushed as
1230 * the CPU may have cached entries in its TLB for the target PCID.
1232 if (unlikely(tdp_enabled)) {
1233 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1238 * If neither the current CR3 nor any of the prev_roots use the given
1239 * PCID, then nothing needs to be done here because a resync will
1240 * happen anyway before switching to any other CR3.
1242 if (kvm_get_active_pcid(vcpu) == pcid) {
1243 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1244 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1248 * If PCID is disabled, there is no need to free prev_roots even if the
1249 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1252 if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))
1255 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1256 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1257 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1259 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1262 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1264 bool skip_tlb_flush = false;
1265 unsigned long pcid = 0;
1266 #ifdef CONFIG_X86_64
1267 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) {
1268 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1269 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1270 pcid = cr3 & X86_CR3_PCID_MASK;
1274 /* PDPTRs are always reloaded for PAE paging. */
1275 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1276 goto handle_tlb_flush;
1279 * Do not condition the GPA check on long mode, this helper is used to
1280 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1281 * the current vCPU mode is accurate.
1283 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1286 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1289 if (cr3 != kvm_read_cr3(vcpu))
1290 kvm_mmu_new_pgd(vcpu, cr3);
1292 vcpu->arch.cr3 = cr3;
1293 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1294 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1298 * A load of CR3 that flushes the TLB flushes only the current PCID,
1299 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1300 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1301 * and it's impossible to use a non-zero PCID when PCID is disabled,
1302 * i.e. only PCID=0 can be relevant.
1304 if (!skip_tlb_flush)
1305 kvm_invalidate_pcid(vcpu, pcid);
1309 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1311 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1313 if (cr8 & CR8_RESERVED_BITS)
1315 if (lapic_in_kernel(vcpu))
1316 kvm_lapic_set_tpr(vcpu, cr8);
1318 vcpu->arch.cr8 = cr8;
1321 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1323 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1325 if (lapic_in_kernel(vcpu))
1326 return kvm_lapic_get_cr8(vcpu);
1328 return vcpu->arch.cr8;
1330 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1332 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1336 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1337 for (i = 0; i < KVM_NR_DB_REGS; i++)
1338 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1342 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1346 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1347 dr7 = vcpu->arch.guest_debug_dr7;
1349 dr7 = vcpu->arch.dr7;
1350 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1351 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1352 if (dr7 & DR7_BP_EN_MASK)
1353 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1355 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1357 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1359 u64 fixed = DR6_FIXED_1;
1361 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1364 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1365 fixed |= DR6_BUS_LOCK;
1369 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1371 size_t size = ARRAY_SIZE(vcpu->arch.db);
1375 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1376 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1377 vcpu->arch.eff_db[dr] = val;
1381 if (!kvm_dr6_valid(val))
1383 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1387 if (!kvm_dr7_valid(val))
1389 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1390 kvm_update_dr7(vcpu);
1396 EXPORT_SYMBOL_GPL(kvm_set_dr);
1398 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1400 size_t size = ARRAY_SIZE(vcpu->arch.db);
1404 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1408 *val = vcpu->arch.dr6;
1412 *val = vcpu->arch.dr7;
1416 EXPORT_SYMBOL_GPL(kvm_get_dr);
1418 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1420 u32 ecx = kvm_rcx_read(vcpu);
1423 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1424 kvm_inject_gp(vcpu, 0);
1428 kvm_rax_write(vcpu, (u32)data);
1429 kvm_rdx_write(vcpu, data >> 32);
1430 return kvm_skip_emulated_instruction(vcpu);
1432 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1435 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) track
1436 * the set of MSRs that KVM exposes to userspace through KVM_GET_MSRS,
1437 * KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. msrs_to_save holds MSRs that
1438 * require host support, i.e. should be probed via RDMSR. emulated_msrs holds
1439 * MSRs that KVM emulates without strictly requiring host support.
1440 * msr_based_features holds MSRs that enumerate features, i.e. are effectively
1441 * CPUID leafs. Note, msr_based_features isn't mutually exclusive with
1442 * msrs_to_save and emulated_msrs.
1445 static const u32 msrs_to_save_base[] = {
1446 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1448 #ifdef CONFIG_X86_64
1449 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1451 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1452 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1453 MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL,
1454 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1455 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1456 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1457 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1458 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1459 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1460 MSR_IA32_UMWAIT_CONTROL,
1462 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1465 static const u32 msrs_to_save_pmu[] = {
1466 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1467 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1468 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1469 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1470 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1472 /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
1473 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1474 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1475 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1476 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1477 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1478 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1479 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1480 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1482 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1483 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1485 /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
1486 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1487 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1488 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1489 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1491 MSR_AMD64_PERF_CNTR_GLOBAL_CTL,
1492 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS,
1493 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,
1496 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) +
1497 ARRAY_SIZE(msrs_to_save_pmu)];
1498 static unsigned num_msrs_to_save;
1500 static const u32 emulated_msrs_all[] = {
1501 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1502 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1503 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1504 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1505 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1506 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1507 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1509 HV_X64_MSR_VP_INDEX,
1510 HV_X64_MSR_VP_RUNTIME,
1511 HV_X64_MSR_SCONTROL,
1512 HV_X64_MSR_STIMER0_CONFIG,
1513 HV_X64_MSR_VP_ASSIST_PAGE,
1514 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1515 HV_X64_MSR_TSC_EMULATION_STATUS, HV_X64_MSR_TSC_INVARIANT_CONTROL,
1516 HV_X64_MSR_SYNDBG_OPTIONS,
1517 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1518 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1519 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1521 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1522 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1524 MSR_IA32_TSC_ADJUST,
1525 MSR_IA32_TSC_DEADLINE,
1526 MSR_IA32_ARCH_CAPABILITIES,
1527 MSR_IA32_PERF_CAPABILITIES,
1528 MSR_IA32_MISC_ENABLE,
1529 MSR_IA32_MCG_STATUS,
1531 MSR_IA32_MCG_EXT_CTL,
1535 MSR_MISC_FEATURES_ENABLES,
1536 MSR_AMD64_VIRT_SPEC_CTRL,
1537 MSR_AMD64_TSC_RATIO,
1542 * KVM always supports the "true" VMX control MSRs, even if the host
1543 * does not. The VMX MSRs as a whole are considered "emulated" as KVM
1544 * doesn't strictly require them to exist in the host (ignoring that
1545 * KVM would refuse to load in the first place if the core set of MSRs
1546 * aren't supported).
1549 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1550 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1551 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1552 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1554 MSR_IA32_VMX_CR0_FIXED0,
1555 MSR_IA32_VMX_CR4_FIXED0,
1556 MSR_IA32_VMX_VMCS_ENUM,
1557 MSR_IA32_VMX_PROCBASED_CTLS2,
1558 MSR_IA32_VMX_EPT_VPID_CAP,
1559 MSR_IA32_VMX_VMFUNC,
1562 MSR_KVM_POLL_CONTROL,
1565 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1566 static unsigned num_emulated_msrs;
1569 * List of MSRs that control the existence of MSR-based features, i.e. MSRs
1570 * that are effectively CPUID leafs. VMX MSRs are also included in the set of
1571 * feature MSRs, but are handled separately to allow expedited lookups.
1573 static const u32 msr_based_features_all_except_vmx[] = {
1576 MSR_IA32_ARCH_CAPABILITIES,
1577 MSR_IA32_PERF_CAPABILITIES,
1580 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all_except_vmx) +
1581 (KVM_LAST_EMULATED_VMX_MSR - KVM_FIRST_EMULATED_VMX_MSR + 1)];
1582 static unsigned int num_msr_based_features;
1585 * All feature MSRs except uCode revID, which tracks the currently loaded uCode
1586 * patch, are immutable once the vCPU model is defined.
1588 static bool kvm_is_immutable_feature_msr(u32 msr)
1592 if (msr >= KVM_FIRST_EMULATED_VMX_MSR && msr <= KVM_LAST_EMULATED_VMX_MSR)
1595 for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) {
1596 if (msr == msr_based_features_all_except_vmx[i])
1597 return msr != MSR_IA32_UCODE_REV;
1604 * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM
1605 * does not yet virtualize. These include:
1606 * 10 - MISC_PACKAGE_CTRLS
1607 * 11 - ENERGY_FILTERING_CTL
1609 * 18 - FB_CLEAR_CTRL
1610 * 21 - XAPIC_DISABLE_STATUS
1611 * 23 - OVERCLOCKING_STATUS
1614 #define KVM_SUPPORTED_ARCH_CAP \
1615 (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \
1616 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \
1617 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \
1618 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \
1619 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO | ARCH_CAP_GDS_NO)
1621 static u64 kvm_get_arch_capabilities(void)
1625 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
1626 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1627 data &= KVM_SUPPORTED_ARCH_CAP;
1631 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1632 * the nested hypervisor runs with NX huge pages. If it is not,
1633 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1634 * L1 guests, so it need not worry about its own (L2) guests.
1636 data |= ARCH_CAP_PSCHANGE_MC_NO;
1639 * If we're doing cache flushes (either "always" or "cond")
1640 * we will do one whenever the guest does a vmlaunch/vmresume.
1641 * If an outer hypervisor is doing the cache flush for us
1642 * (ARCH_CAP_SKIP_VMENTRY_L1DFLUSH), we can safely pass that
1643 * capability to the guest too, and if EPT is disabled we're not
1644 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1645 * require a nested hypervisor to do a flush of its own.
1647 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1648 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1650 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1651 data |= ARCH_CAP_RDCL_NO;
1652 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1653 data |= ARCH_CAP_SSB_NO;
1654 if (!boot_cpu_has_bug(X86_BUG_MDS))
1655 data |= ARCH_CAP_MDS_NO;
1657 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1659 * If RTM=0 because the kernel has disabled TSX, the host might
1660 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1661 * and therefore knows that there cannot be TAA) but keep
1662 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1663 * and we want to allow migrating those guests to tsx=off hosts.
1665 data &= ~ARCH_CAP_TAA_NO;
1666 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1667 data |= ARCH_CAP_TAA_NO;
1670 * Nothing to do here; we emulate TSX_CTRL if present on the
1671 * host so the guest can choose between disabling TSX or
1672 * using VERW to clear CPU buffers.
1676 if (!boot_cpu_has_bug(X86_BUG_GDS) || gds_ucode_mitigated())
1677 data |= ARCH_CAP_GDS_NO;
1682 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1684 switch (msr->index) {
1685 case MSR_IA32_ARCH_CAPABILITIES:
1686 msr->data = kvm_get_arch_capabilities();
1688 case MSR_IA32_PERF_CAPABILITIES:
1689 msr->data = kvm_caps.supported_perf_cap;
1691 case MSR_IA32_UCODE_REV:
1692 rdmsrl_safe(msr->index, &msr->data);
1695 return static_call(kvm_x86_get_msr_feature)(msr);
1700 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1702 struct kvm_msr_entry msr;
1706 r = kvm_get_msr_feature(&msr);
1708 if (r == KVM_MSR_RET_INVALID) {
1709 /* Unconditionally clear the output for simplicity */
1711 if (kvm_msr_ignored_check(index, 0, false))
1723 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1725 if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS))
1728 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1731 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1734 if (efer & (EFER_LME | EFER_LMA) &&
1735 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1738 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1744 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1746 if (efer & efer_reserved_bits)
1749 return __kvm_valid_efer(vcpu, efer);
1751 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1753 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1755 u64 old_efer = vcpu->arch.efer;
1756 u64 efer = msr_info->data;
1759 if (efer & efer_reserved_bits)
1762 if (!msr_info->host_initiated) {
1763 if (!__kvm_valid_efer(vcpu, efer))
1766 if (is_paging(vcpu) &&
1767 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1772 efer |= vcpu->arch.efer & EFER_LMA;
1774 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1780 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1781 kvm_mmu_reset_context(vcpu);
1786 void kvm_enable_efer_bits(u64 mask)
1788 efer_reserved_bits &= ~mask;
1790 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1792 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1794 struct kvm_x86_msr_filter *msr_filter;
1795 struct msr_bitmap_range *ranges;
1796 struct kvm *kvm = vcpu->kvm;
1801 /* x2APIC MSRs do not support filtering. */
1802 if (index >= 0x800 && index <= 0x8ff)
1805 idx = srcu_read_lock(&kvm->srcu);
1807 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1813 allowed = msr_filter->default_allow;
1814 ranges = msr_filter->ranges;
1816 for (i = 0; i < msr_filter->count; i++) {
1817 u32 start = ranges[i].base;
1818 u32 end = start + ranges[i].nmsrs;
1819 u32 flags = ranges[i].flags;
1820 unsigned long *bitmap = ranges[i].bitmap;
1822 if ((index >= start) && (index < end) && (flags & type)) {
1823 allowed = test_bit(index - start, bitmap);
1829 srcu_read_unlock(&kvm->srcu, idx);
1833 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1836 * Write @data into the MSR specified by @index. Select MSR specific fault
1837 * checks are bypassed if @host_initiated is %true.
1838 * Returns 0 on success, non-0 otherwise.
1839 * Assumes vcpu_load() was already called.
1841 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1842 bool host_initiated)
1844 struct msr_data msr;
1849 case MSR_KERNEL_GS_BASE:
1852 if (is_noncanonical_address(data, vcpu))
1855 case MSR_IA32_SYSENTER_EIP:
1856 case MSR_IA32_SYSENTER_ESP:
1858 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1859 * non-canonical address is written on Intel but not on
1860 * AMD (which ignores the top 32-bits, because it does
1861 * not implement 64-bit SYSENTER).
1863 * 64-bit code should hence be able to write a non-canonical
1864 * value on AMD. Making the address canonical ensures that
1865 * vmentry does not fail on Intel after writing a non-canonical
1866 * value, and that something deterministic happens if the guest
1867 * invokes 64-bit SYSENTER.
1869 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1872 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1875 if (!host_initiated &&
1876 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1877 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1881 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1882 * incomplete and conflicting architectural behavior. Current
1883 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1884 * reserved and always read as zeros. Enforce Intel's reserved
1885 * bits check if and only if the guest CPU is Intel, and clear
1886 * the bits in all other cases. This ensures cross-vendor
1887 * migration will provide consistent behavior for the guest.
1889 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1898 msr.host_initiated = host_initiated;
1900 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1903 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1904 u32 index, u64 data, bool host_initiated)
1906 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1908 if (ret == KVM_MSR_RET_INVALID)
1909 if (kvm_msr_ignored_check(index, data, true))
1916 * Read the MSR specified by @index into @data. Select MSR specific fault
1917 * checks are bypassed if @host_initiated is %true.
1918 * Returns 0 on success, non-0 otherwise.
1919 * Assumes vcpu_load() was already called.
1921 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1922 bool host_initiated)
1924 struct msr_data msr;
1929 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1932 if (!host_initiated &&
1933 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1934 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1940 msr.host_initiated = host_initiated;
1942 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1948 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1949 u32 index, u64 *data, bool host_initiated)
1951 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1953 if (ret == KVM_MSR_RET_INVALID) {
1954 /* Unconditionally clear *data for simplicity */
1956 if (kvm_msr_ignored_check(index, 0, false))
1963 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1965 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1966 return KVM_MSR_RET_FILTERED;
1967 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1970 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1972 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1973 return KVM_MSR_RET_FILTERED;
1974 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1977 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1979 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1981 EXPORT_SYMBOL_GPL(kvm_get_msr);
1983 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1985 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1987 EXPORT_SYMBOL_GPL(kvm_set_msr);
1989 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1991 if (!vcpu->run->msr.error) {
1992 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1993 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1997 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1999 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
2002 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
2004 complete_userspace_rdmsr(vcpu);
2005 return complete_emulated_msr_access(vcpu);
2008 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
2010 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
2013 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
2015 complete_userspace_rdmsr(vcpu);
2016 return complete_fast_msr_access(vcpu);
2019 static u64 kvm_msr_reason(int r)
2022 case KVM_MSR_RET_INVALID:
2023 return KVM_MSR_EXIT_REASON_UNKNOWN;
2024 case KVM_MSR_RET_FILTERED:
2025 return KVM_MSR_EXIT_REASON_FILTER;
2027 return KVM_MSR_EXIT_REASON_INVAL;
2031 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
2032 u32 exit_reason, u64 data,
2033 int (*completion)(struct kvm_vcpu *vcpu),
2036 u64 msr_reason = kvm_msr_reason(r);
2038 /* Check if the user wanted to know about this MSR fault */
2039 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
2042 vcpu->run->exit_reason = exit_reason;
2043 vcpu->run->msr.error = 0;
2044 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
2045 vcpu->run->msr.reason = msr_reason;
2046 vcpu->run->msr.index = index;
2047 vcpu->run->msr.data = data;
2048 vcpu->arch.complete_userspace_io = completion;
2053 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
2055 u32 ecx = kvm_rcx_read(vcpu);
2059 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
2062 trace_kvm_msr_read(ecx, data);
2064 kvm_rax_write(vcpu, data & -1u);
2065 kvm_rdx_write(vcpu, (data >> 32) & -1u);
2067 /* MSR read failed? See if we should ask user space */
2068 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
2069 complete_fast_rdmsr, r))
2071 trace_kvm_msr_read_ex(ecx);
2074 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2076 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
2078 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
2080 u32 ecx = kvm_rcx_read(vcpu);
2081 u64 data = kvm_read_edx_eax(vcpu);
2084 r = kvm_set_msr_with_filter(vcpu, ecx, data);
2087 trace_kvm_msr_write(ecx, data);
2089 /* MSR write failed? See if we should ask user space */
2090 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2091 complete_fast_msr_access, r))
2093 /* Signal all other negative errors to userspace */
2096 trace_kvm_msr_write_ex(ecx, data);
2099 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2101 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2103 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2105 return kvm_skip_emulated_instruction(vcpu);
2108 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2110 /* Treat an INVD instruction as a NOP and just skip it. */
2111 return kvm_emulate_as_nop(vcpu);
2113 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2115 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2117 kvm_queue_exception(vcpu, UD_VECTOR);
2120 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2123 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
2125 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) &&
2126 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT))
2127 return kvm_handle_invalid_op(vcpu);
2129 pr_warn_once("%s instruction emulated as NOP!\n", insn);
2130 return kvm_emulate_as_nop(vcpu);
2132 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2134 return kvm_emulate_monitor_mwait(vcpu, "MWAIT");
2136 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2138 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2140 return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
2142 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2144 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2146 xfer_to_guest_mode_prepare();
2147 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2148 xfer_to_guest_mode_work_pending();
2152 * The fast path for frequent and performance sensitive wrmsr emulation,
2153 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2154 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2155 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2156 * other cases which must be called after interrupts are enabled on the host.
2158 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2160 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2163 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2164 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2165 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2166 ((u32)(data >> 32) != X2APIC_BROADCAST))
2167 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2172 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2174 if (!kvm_can_use_hv_timer(vcpu))
2177 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2181 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2183 u32 msr = kvm_rcx_read(vcpu);
2185 fastpath_t ret = EXIT_FASTPATH_NONE;
2187 kvm_vcpu_srcu_read_lock(vcpu);
2190 case APIC_BASE_MSR + (APIC_ICR >> 4):
2191 data = kvm_read_edx_eax(vcpu);
2192 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2193 kvm_skip_emulated_instruction(vcpu);
2194 ret = EXIT_FASTPATH_EXIT_HANDLED;
2197 case MSR_IA32_TSC_DEADLINE:
2198 data = kvm_read_edx_eax(vcpu);
2199 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2200 kvm_skip_emulated_instruction(vcpu);
2201 ret = EXIT_FASTPATH_REENTER_GUEST;
2208 if (ret != EXIT_FASTPATH_NONE)
2209 trace_kvm_msr_write(msr, data);
2211 kvm_vcpu_srcu_read_unlock(vcpu);
2215 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2218 * Adapt set_msr() to msr_io()'s calling convention
2220 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2222 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2225 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2230 * Disallow writes to immutable feature MSRs after KVM_RUN. KVM does
2231 * not support modifying the guest vCPU model on the fly, e.g. changing
2232 * the nVMX capabilities while L2 is running is nonsensical. Ignore
2233 * writes of the same value, e.g. to allow userspace to blindly stuff
2234 * all MSRs when emulating RESET.
2236 if (kvm_vcpu_has_run(vcpu) && kvm_is_immutable_feature_msr(index)) {
2237 if (do_get_msr(vcpu, index, &val) || *data != val)
2243 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2246 #ifdef CONFIG_X86_64
2247 struct pvclock_clock {
2257 struct pvclock_gtod_data {
2260 struct pvclock_clock clock; /* extract of a clocksource struct */
2261 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2267 static struct pvclock_gtod_data pvclock_gtod_data;
2269 static void update_pvclock_gtod(struct timekeeper *tk)
2271 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2273 write_seqcount_begin(&vdata->seq);
2275 /* copy pvclock gtod data */
2276 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2277 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2278 vdata->clock.mask = tk->tkr_mono.mask;
2279 vdata->clock.mult = tk->tkr_mono.mult;
2280 vdata->clock.shift = tk->tkr_mono.shift;
2281 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2282 vdata->clock.offset = tk->tkr_mono.base;
2284 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2285 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2286 vdata->raw_clock.mask = tk->tkr_raw.mask;
2287 vdata->raw_clock.mult = tk->tkr_raw.mult;
2288 vdata->raw_clock.shift = tk->tkr_raw.shift;
2289 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2290 vdata->raw_clock.offset = tk->tkr_raw.base;
2292 vdata->wall_time_sec = tk->xtime_sec;
2294 vdata->offs_boot = tk->offs_boot;
2296 write_seqcount_end(&vdata->seq);
2299 static s64 get_kvmclock_base_ns(void)
2301 /* Count up from boot time, but with the frequency of the raw clock. */
2302 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2305 static s64 get_kvmclock_base_ns(void)
2307 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2308 return ktime_get_boottime_ns();
2312 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2316 struct pvclock_wall_clock wc;
2323 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2328 ++version; /* first time write, random junk */
2332 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2336 * The guest calculates current wall clock time by adding
2337 * system time (updated by kvm_guest_time_update below) to the
2338 * wall clock specified here. We do the reverse here.
2340 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2342 wc.nsec = do_div(wall_nsec, 1000000000);
2343 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2344 wc.version = version;
2346 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2349 wc_sec_hi = wall_nsec >> 32;
2350 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2351 &wc_sec_hi, sizeof(wc_sec_hi));
2355 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2358 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2359 bool old_msr, bool host_initiated)
2361 struct kvm_arch *ka = &vcpu->kvm->arch;
2363 if (vcpu->vcpu_id == 0 && !host_initiated) {
2364 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2365 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2367 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2370 vcpu->arch.time = system_time;
2371 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2373 /* we verify if the enable bit is set... */
2374 if (system_time & 1)
2375 kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL,
2376 sizeof(struct pvclock_vcpu_time_info));
2378 kvm_gpc_deactivate(&vcpu->arch.pv_time);
2383 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2385 do_shl32_div32(dividend, divisor);
2389 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2390 s8 *pshift, u32 *pmultiplier)
2398 scaled64 = scaled_hz;
2399 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2404 tps32 = (uint32_t)tps64;
2405 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2406 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2414 *pmultiplier = div_frac(scaled64, tps32);
2417 #ifdef CONFIG_X86_64
2418 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2421 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2422 static unsigned long max_tsc_khz;
2424 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2426 u64 v = (u64)khz * (1000000 + ppm);
2431 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2433 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2437 /* Guest TSC same frequency as host TSC? */
2439 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2443 /* TSC scaling supported? */
2444 if (!kvm_caps.has_tsc_control) {
2445 if (user_tsc_khz > tsc_khz) {
2446 vcpu->arch.tsc_catchup = 1;
2447 vcpu->arch.tsc_always_catchup = 1;
2450 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2455 /* TSC scaling required - calculate ratio */
2456 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
2457 user_tsc_khz, tsc_khz);
2459 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
2460 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2465 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2469 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2471 u32 thresh_lo, thresh_hi;
2472 int use_scaling = 0;
2474 /* tsc_khz can be zero if TSC calibration fails */
2475 if (user_tsc_khz == 0) {
2476 /* set tsc_scaling_ratio to a safe value */
2477 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2481 /* Compute a scale to convert nanoseconds in TSC cycles */
2482 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2483 &vcpu->arch.virtual_tsc_shift,
2484 &vcpu->arch.virtual_tsc_mult);
2485 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2488 * Compute the variation in TSC rate which is acceptable
2489 * within the range of tolerance and decide if the
2490 * rate being applied is within that bounds of the hardware
2491 * rate. If so, no scaling or compensation need be done.
2493 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2494 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2495 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2496 pr_debug("requested TSC rate %u falls outside tolerance [%u,%u]\n",
2497 user_tsc_khz, thresh_lo, thresh_hi);
2500 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2503 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2505 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2506 vcpu->arch.virtual_tsc_mult,
2507 vcpu->arch.virtual_tsc_shift);
2508 tsc += vcpu->arch.this_tsc_write;
2512 #ifdef CONFIG_X86_64
2513 static inline int gtod_is_based_on_tsc(int mode)
2515 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2519 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2521 #ifdef CONFIG_X86_64
2523 struct kvm_arch *ka = &vcpu->kvm->arch;
2524 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2526 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2527 atomic_read(&vcpu->kvm->online_vcpus));
2530 * Once the masterclock is enabled, always perform request in
2531 * order to update it.
2533 * In order to enable masterclock, the host clocksource must be TSC
2534 * and the vcpus need to have matched TSCs. When that happens,
2535 * perform request to enable masterclock.
2537 if (ka->use_master_clock ||
2538 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2539 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2541 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2542 atomic_read(&vcpu->kvm->online_vcpus),
2543 ka->use_master_clock, gtod->clock.vclock_mode);
2548 * Multiply tsc by a fixed point number represented by ratio.
2550 * The most significant 64-N bits (mult) of ratio represent the
2551 * integral part of the fixed point number; the remaining N bits
2552 * (frac) represent the fractional part, ie. ratio represents a fixed
2553 * point number (mult + frac * 2^(-N)).
2555 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
2557 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2559 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
2562 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2566 if (ratio != kvm_caps.default_tsc_scaling_ratio)
2567 _tsc = __scale_tsc(ratio, tsc);
2572 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2576 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2578 return target_tsc - tsc;
2581 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2583 return vcpu->arch.l1_tsc_offset +
2584 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2586 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2588 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2592 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
2593 nested_offset = l1_offset;
2595 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2596 kvm_caps.tsc_scaling_ratio_frac_bits);
2598 nested_offset += l2_offset;
2599 return nested_offset;
2601 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2603 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2605 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
2606 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2607 kvm_caps.tsc_scaling_ratio_frac_bits);
2609 return l1_multiplier;
2611 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2613 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2615 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2616 vcpu->arch.l1_tsc_offset,
2619 vcpu->arch.l1_tsc_offset = l1_offset;
2622 * If we are here because L1 chose not to trap WRMSR to TSC then
2623 * according to the spec this should set L1's TSC (as opposed to
2624 * setting L1's offset for L2).
2626 if (is_guest_mode(vcpu))
2627 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2629 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2630 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2632 vcpu->arch.tsc_offset = l1_offset;
2634 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset);
2637 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2639 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2641 /* Userspace is changing the multiplier while L2 is active */
2642 if (is_guest_mode(vcpu))
2643 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2645 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2647 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2649 if (kvm_caps.has_tsc_control)
2650 static_call(kvm_x86_write_tsc_multiplier)(
2651 vcpu, vcpu->arch.tsc_scaling_ratio);
2654 static inline bool kvm_check_tsc_unstable(void)
2656 #ifdef CONFIG_X86_64
2658 * TSC is marked unstable when we're running on Hyper-V,
2659 * 'TSC page' clocksource is good.
2661 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2664 return check_tsc_unstable();
2668 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2669 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2672 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2673 u64 ns, bool matched)
2675 struct kvm *kvm = vcpu->kvm;
2677 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2680 * We also track th most recent recorded KHZ, write and time to
2681 * allow the matching interval to be extended at each write.
2683 kvm->arch.last_tsc_nsec = ns;
2684 kvm->arch.last_tsc_write = tsc;
2685 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2686 kvm->arch.last_tsc_offset = offset;
2688 vcpu->arch.last_guest_tsc = tsc;
2690 kvm_vcpu_write_tsc_offset(vcpu, offset);
2694 * We split periods of matched TSC writes into generations.
2695 * For each generation, we track the original measured
2696 * nanosecond time, offset, and write, so if TSCs are in
2697 * sync, we can match exact offset, and if not, we can match
2698 * exact software computation in compute_guest_tsc()
2700 * These values are tracked in kvm->arch.cur_xxx variables.
2702 kvm->arch.cur_tsc_generation++;
2703 kvm->arch.cur_tsc_nsec = ns;
2704 kvm->arch.cur_tsc_write = tsc;
2705 kvm->arch.cur_tsc_offset = offset;
2706 kvm->arch.nr_vcpus_matched_tsc = 0;
2707 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2708 kvm->arch.nr_vcpus_matched_tsc++;
2711 /* Keep track of which generation this VCPU has synchronized to */
2712 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2713 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2714 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2716 kvm_track_tsc_matching(vcpu);
2719 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2721 struct kvm *kvm = vcpu->kvm;
2722 u64 offset, ns, elapsed;
2723 unsigned long flags;
2724 bool matched = false;
2725 bool synchronizing = false;
2727 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2728 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2729 ns = get_kvmclock_base_ns();
2730 elapsed = ns - kvm->arch.last_tsc_nsec;
2732 if (vcpu->arch.virtual_tsc_khz) {
2735 * detection of vcpu initialization -- need to sync
2736 * with other vCPUs. This particularly helps to keep
2737 * kvm_clock stable after CPU hotplug
2739 synchronizing = true;
2741 u64 tsc_exp = kvm->arch.last_tsc_write +
2742 nsec_to_cycles(vcpu, elapsed);
2743 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2745 * Special case: TSC write with a small delta (1 second)
2746 * of virtual cycle time against real time is
2747 * interpreted as an attempt to synchronize the CPU.
2749 synchronizing = data < tsc_exp + tsc_hz &&
2750 data + tsc_hz > tsc_exp;
2755 * For a reliable TSC, we can match TSC offsets, and for an unstable
2756 * TSC, we add elapsed time in this computation. We could let the
2757 * compensation code attempt to catch up if we fall behind, but
2758 * it's better to try to match offsets from the beginning.
2760 if (synchronizing &&
2761 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2762 if (!kvm_check_tsc_unstable()) {
2763 offset = kvm->arch.cur_tsc_offset;
2765 u64 delta = nsec_to_cycles(vcpu, elapsed);
2767 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2772 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2773 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2776 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2779 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2780 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2783 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2785 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
2786 WARN_ON(adjustment < 0);
2787 adjustment = kvm_scale_tsc((u64) adjustment,
2788 vcpu->arch.l1_tsc_scaling_ratio);
2789 adjust_tsc_offset_guest(vcpu, adjustment);
2792 #ifdef CONFIG_X86_64
2794 static u64 read_tsc(void)
2796 u64 ret = (u64)rdtsc_ordered();
2797 u64 last = pvclock_gtod_data.clock.cycle_last;
2799 if (likely(ret >= last))
2803 * GCC likes to generate cmov here, but this branch is extremely
2804 * predictable (it's just a function of time and the likely is
2805 * very likely) and there's a data dependence, so force GCC
2806 * to generate a branch instead. I don't barrier() because
2807 * we don't actually need a barrier, and if this function
2808 * ever gets inlined it will generate worse code.
2814 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2820 switch (clock->vclock_mode) {
2821 case VDSO_CLOCKMODE_HVCLOCK:
2822 if (hv_read_tsc_page_tsc(hv_get_tsc_page(),
2823 tsc_timestamp, &tsc_pg_val)) {
2824 /* TSC page valid */
2825 *mode = VDSO_CLOCKMODE_HVCLOCK;
2826 v = (tsc_pg_val - clock->cycle_last) &
2829 /* TSC page invalid */
2830 *mode = VDSO_CLOCKMODE_NONE;
2833 case VDSO_CLOCKMODE_TSC:
2834 *mode = VDSO_CLOCKMODE_TSC;
2835 *tsc_timestamp = read_tsc();
2836 v = (*tsc_timestamp - clock->cycle_last) &
2840 *mode = VDSO_CLOCKMODE_NONE;
2843 if (*mode == VDSO_CLOCKMODE_NONE)
2844 *tsc_timestamp = v = 0;
2846 return v * clock->mult;
2849 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2851 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2857 seq = read_seqcount_begin(>od->seq);
2858 ns = gtod->raw_clock.base_cycles;
2859 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2860 ns >>= gtod->raw_clock.shift;
2861 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2862 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2868 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2870 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2876 seq = read_seqcount_begin(>od->seq);
2877 ts->tv_sec = gtod->wall_time_sec;
2878 ns = gtod->clock.base_cycles;
2879 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2880 ns >>= gtod->clock.shift;
2881 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2883 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2889 /* returns true if host is using TSC based clocksource */
2890 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2892 /* checked again under seqlock below */
2893 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2896 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2900 /* returns true if host is using TSC based clocksource */
2901 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2904 /* checked again under seqlock below */
2905 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2908 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2914 * Assuming a stable TSC across physical CPUS, and a stable TSC
2915 * across virtual CPUs, the following condition is possible.
2916 * Each numbered line represents an event visible to both
2917 * CPUs at the next numbered event.
2919 * "timespecX" represents host monotonic time. "tscX" represents
2922 * VCPU0 on CPU0 | VCPU1 on CPU1
2924 * 1. read timespec0,tsc0
2925 * 2. | timespec1 = timespec0 + N
2927 * 3. transition to guest | transition to guest
2928 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2929 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2930 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2932 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2935 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2937 * - 0 < N - M => M < N
2939 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2940 * always the case (the difference between two distinct xtime instances
2941 * might be smaller then the difference between corresponding TSC reads,
2942 * when updating guest vcpus pvclock areas).
2944 * To avoid that problem, do not allow visibility of distinct
2945 * system_timestamp/tsc_timestamp values simultaneously: use a master
2946 * copy of host monotonic time values. Update that master copy
2949 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2953 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2955 #ifdef CONFIG_X86_64
2956 struct kvm_arch *ka = &kvm->arch;
2958 bool host_tsc_clocksource, vcpus_matched;
2960 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2961 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2962 atomic_read(&kvm->online_vcpus));
2965 * If the host uses TSC clock, then passthrough TSC as stable
2968 host_tsc_clocksource = kvm_get_time_and_clockread(
2969 &ka->master_kernel_ns,
2970 &ka->master_cycle_now);
2972 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2973 && !ka->backwards_tsc_observed
2974 && !ka->boot_vcpu_runs_old_kvmclock;
2976 if (ka->use_master_clock)
2977 atomic_set(&kvm_guest_has_master_clock, 1);
2979 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2980 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2985 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2987 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2990 static void __kvm_start_pvclock_update(struct kvm *kvm)
2992 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2993 write_seqcount_begin(&kvm->arch.pvclock_sc);
2996 static void kvm_start_pvclock_update(struct kvm *kvm)
2998 kvm_make_mclock_inprogress_request(kvm);
3000 /* no guest entries from this point */
3001 __kvm_start_pvclock_update(kvm);
3004 static void kvm_end_pvclock_update(struct kvm *kvm)
3006 struct kvm_arch *ka = &kvm->arch;
3007 struct kvm_vcpu *vcpu;
3010 write_seqcount_end(&ka->pvclock_sc);
3011 raw_spin_unlock_irq(&ka->tsc_write_lock);
3012 kvm_for_each_vcpu(i, vcpu, kvm)
3013 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3015 /* guest entries allowed */
3016 kvm_for_each_vcpu(i, vcpu, kvm)
3017 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
3020 static void kvm_update_masterclock(struct kvm *kvm)
3022 kvm_hv_request_tsc_page_update(kvm);
3023 kvm_start_pvclock_update(kvm);
3024 pvclock_update_vm_gtod_copy(kvm);
3025 kvm_end_pvclock_update(kvm);
3029 * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's
3030 * per-CPU value (which may be zero if a CPU is going offline). Note, tsc_khz
3031 * can change during boot even if the TSC is constant, as it's possible for KVM
3032 * to be loaded before TSC calibration completes. Ideally, KVM would get a
3033 * notification when calibration completes, but practically speaking calibration
3034 * will complete before userspace is alive enough to create VMs.
3036 static unsigned long get_cpu_tsc_khz(void)
3038 if (static_cpu_has(X86_FEATURE_CONSTANT_TSC))
3041 return __this_cpu_read(cpu_tsc_khz);
3044 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
3045 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3047 struct kvm_arch *ka = &kvm->arch;
3048 struct pvclock_vcpu_time_info hv_clock;
3050 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
3054 if (ka->use_master_clock &&
3055 (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) {
3056 #ifdef CONFIG_X86_64
3057 struct timespec64 ts;
3059 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
3060 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
3061 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
3064 data->host_tsc = rdtsc();
3066 data->flags |= KVM_CLOCK_TSC_STABLE;
3067 hv_clock.tsc_timestamp = ka->master_cycle_now;
3068 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3069 kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL,
3070 &hv_clock.tsc_shift,
3071 &hv_clock.tsc_to_system_mul);
3072 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
3074 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
3080 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3082 struct kvm_arch *ka = &kvm->arch;
3086 seq = read_seqcount_begin(&ka->pvclock_sc);
3087 __get_kvmclock(kvm, data);
3088 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3091 u64 get_kvmclock_ns(struct kvm *kvm)
3093 struct kvm_clock_data data;
3095 get_kvmclock(kvm, &data);
3099 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
3100 struct gfn_to_pfn_cache *gpc,
3101 unsigned int offset)
3103 struct kvm_vcpu_arch *vcpu = &v->arch;
3104 struct pvclock_vcpu_time_info *guest_hv_clock;
3105 unsigned long flags;
3107 read_lock_irqsave(&gpc->lock, flags);
3108 while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) {
3109 read_unlock_irqrestore(&gpc->lock, flags);
3111 if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock)))
3114 read_lock_irqsave(&gpc->lock, flags);
3117 guest_hv_clock = (void *)(gpc->khva + offset);
3120 * This VCPU is paused, but it's legal for a guest to read another
3121 * VCPU's kvmclock, so we really have to follow the specification where
3122 * it says that version is odd if data is being modified, and even after
3126 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
3129 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3130 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3132 if (vcpu->pvclock_set_guest_stopped_request) {
3133 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3134 vcpu->pvclock_set_guest_stopped_request = false;
3137 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3140 guest_hv_clock->version = ++vcpu->hv_clock.version;
3142 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT);
3143 read_unlock_irqrestore(&gpc->lock, flags);
3145 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3148 static int kvm_guest_time_update(struct kvm_vcpu *v)
3150 unsigned long flags, tgt_tsc_khz;
3152 struct kvm_vcpu_arch *vcpu = &v->arch;
3153 struct kvm_arch *ka = &v->kvm->arch;
3155 u64 tsc_timestamp, host_tsc;
3157 bool use_master_clock;
3163 * If the host uses TSC clock, then passthrough TSC as stable
3167 seq = read_seqcount_begin(&ka->pvclock_sc);
3168 use_master_clock = ka->use_master_clock;
3169 if (use_master_clock) {
3170 host_tsc = ka->master_cycle_now;
3171 kernel_ns = ka->master_kernel_ns;
3173 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3175 /* Keep irq disabled to prevent changes to the clock */
3176 local_irq_save(flags);
3177 tgt_tsc_khz = get_cpu_tsc_khz();
3178 if (unlikely(tgt_tsc_khz == 0)) {
3179 local_irq_restore(flags);
3180 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3183 if (!use_master_clock) {
3185 kernel_ns = get_kvmclock_base_ns();
3188 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3191 * We may have to catch up the TSC to match elapsed wall clock
3192 * time for two reasons, even if kvmclock is used.
3193 * 1) CPU could have been running below the maximum TSC rate
3194 * 2) Broken TSC compensation resets the base at each VCPU
3195 * entry to avoid unknown leaps of TSC even when running
3196 * again on the same CPU. This may cause apparent elapsed
3197 * time to disappear, and the guest to stand still or run
3200 if (vcpu->tsc_catchup) {
3201 u64 tsc = compute_guest_tsc(v, kernel_ns);
3202 if (tsc > tsc_timestamp) {
3203 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3204 tsc_timestamp = tsc;
3208 local_irq_restore(flags);
3210 /* With all the info we got, fill in the values */
3212 if (kvm_caps.has_tsc_control)
3213 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3214 v->arch.l1_tsc_scaling_ratio);
3216 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3217 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3218 &vcpu->hv_clock.tsc_shift,
3219 &vcpu->hv_clock.tsc_to_system_mul);
3220 vcpu->hw_tsc_khz = tgt_tsc_khz;
3221 kvm_xen_update_tsc_info(v);
3224 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3225 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3226 vcpu->last_guest_tsc = tsc_timestamp;
3228 /* If the host uses TSC clocksource, then it is stable */
3230 if (use_master_clock)
3231 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3233 vcpu->hv_clock.flags = pvclock_flags;
3235 if (vcpu->pv_time.active)
3236 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0);
3237 if (vcpu->xen.vcpu_info_cache.active)
3238 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3239 offsetof(struct compat_vcpu_info, time));
3240 if (vcpu->xen.vcpu_time_info_cache.active)
3241 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0);
3242 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3247 * kvmclock updates which are isolated to a given vcpu, such as
3248 * vcpu->cpu migration, should not allow system_timestamp from
3249 * the rest of the vcpus to remain static. Otherwise ntp frequency
3250 * correction applies to one vcpu's system_timestamp but not
3253 * So in those cases, request a kvmclock update for all vcpus.
3254 * We need to rate-limit these requests though, as they can
3255 * considerably slow guests that have a large number of vcpus.
3256 * The time for a remote vcpu to update its kvmclock is bound
3257 * by the delay we use to rate-limit the updates.
3260 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3262 static void kvmclock_update_fn(struct work_struct *work)
3265 struct delayed_work *dwork = to_delayed_work(work);
3266 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3267 kvmclock_update_work);
3268 struct kvm *kvm = container_of(ka, struct kvm, arch);
3269 struct kvm_vcpu *vcpu;
3271 kvm_for_each_vcpu(i, vcpu, kvm) {
3272 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3273 kvm_vcpu_kick(vcpu);
3277 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3279 struct kvm *kvm = v->kvm;
3281 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3282 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3283 KVMCLOCK_UPDATE_DELAY);
3286 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3288 static void kvmclock_sync_fn(struct work_struct *work)
3290 struct delayed_work *dwork = to_delayed_work(work);
3291 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3292 kvmclock_sync_work);
3293 struct kvm *kvm = container_of(ka, struct kvm, arch);
3295 if (!kvmclock_periodic_sync)
3298 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3299 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3300 KVMCLOCK_SYNC_PERIOD);
3303 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
3304 static bool is_mci_control_msr(u32 msr)
3306 return (msr & 3) == 0;
3308 static bool is_mci_status_msr(u32 msr)
3310 return (msr & 3) == 1;
3314 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3316 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3318 /* McStatusWrEn enabled? */
3319 if (guest_cpuid_is_amd_or_hygon(vcpu))
3320 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3325 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3327 u64 mcg_cap = vcpu->arch.mcg_cap;
3328 unsigned bank_num = mcg_cap & 0xff;
3329 u32 msr = msr_info->index;
3330 u64 data = msr_info->data;
3331 u32 offset, last_msr;
3334 case MSR_IA32_MCG_STATUS:
3335 vcpu->arch.mcg_status = data;
3337 case MSR_IA32_MCG_CTL:
3338 if (!(mcg_cap & MCG_CTL_P) &&
3339 (data || !msr_info->host_initiated))
3341 if (data != 0 && data != ~(u64)0)
3343 vcpu->arch.mcg_ctl = data;
3345 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3346 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3350 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
3352 /* An attempt to write a 1 to a reserved bit raises #GP */
3353 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
3355 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3356 last_msr + 1 - MSR_IA32_MC0_CTL2);
3357 vcpu->arch.mci_ctl2_banks[offset] = data;
3359 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3360 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3365 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other
3366 * values are architecturally undefined. But, some Linux
3367 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
3368 * issue on AMD K8s, allow bit 10 to be clear when setting all
3369 * other bits in order to avoid an uncaught #GP in the guest.
3371 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable,
3372 * single-bit ECC data errors.
3374 if (is_mci_control_msr(msr) &&
3375 data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
3379 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
3380 * AMD-based CPUs allow non-zero values, but if and only if
3381 * HWCR[McStatusWrEn] is set.
3383 if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
3384 data != 0 && !can_set_mci_status(vcpu))
3387 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3388 last_msr + 1 - MSR_IA32_MC0_CTL);
3389 vcpu->arch.mce_banks[offset] = data;
3397 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3399 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3401 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3404 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3406 gpa_t gpa = data & ~0x3f;
3408 /* Bits 4:5 are reserved, Should be zero */
3412 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3413 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3416 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3417 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3420 if (!lapic_in_kernel(vcpu))
3421 return data ? 1 : 0;
3423 vcpu->arch.apf.msr_en_val = data;
3425 if (!kvm_pv_async_pf_enabled(vcpu)) {
3426 kvm_clear_async_pf_completion_queue(vcpu);
3427 kvm_async_pf_hash_reset(vcpu);
3431 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3435 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3436 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3438 kvm_async_pf_wakeup_all(vcpu);
3443 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3445 /* Bits 8-63 are reserved */
3449 if (!lapic_in_kernel(vcpu))
3452 vcpu->arch.apf.msr_int_val = data;
3454 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3459 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3461 kvm_gpc_deactivate(&vcpu->arch.pv_time);
3462 vcpu->arch.time = 0;
3465 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3467 ++vcpu->stat.tlb_flush;
3468 static_call(kvm_x86_flush_tlb_all)(vcpu);
3470 /* Flushing all ASIDs flushes the current ASID... */
3471 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3474 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3476 ++vcpu->stat.tlb_flush;
3480 * A TLB flush on behalf of the guest is equivalent to
3481 * INVPCID(all), toggling CR4.PGE, etc., which requires
3482 * a forced sync of the shadow page tables. Ensure all the
3483 * roots are synced and the guest TLB in hardware is clean.
3485 kvm_mmu_sync_roots(vcpu);
3486 kvm_mmu_sync_prev_roots(vcpu);
3489 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3492 * Flushing all "guest" TLB is always a superset of Hyper-V's fine
3495 kvm_hv_vcpu_purge_flush_tlb(vcpu);
3499 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3501 ++vcpu->stat.tlb_flush;
3502 static_call(kvm_x86_flush_tlb_current)(vcpu);
3506 * Service "local" TLB flush requests, which are specific to the current MMU
3507 * context. In addition to the generic event handling in vcpu_enter_guest(),
3508 * TLB flushes that are targeted at an MMU context also need to be serviced
3509 * prior before nested VM-Enter/VM-Exit.
3511 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3513 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3514 kvm_vcpu_flush_tlb_current(vcpu);
3516 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3517 kvm_vcpu_flush_tlb_guest(vcpu);
3519 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3521 static void record_steal_time(struct kvm_vcpu *vcpu)
3523 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3524 struct kvm_steal_time __user *st;
3525 struct kvm_memslots *slots;
3526 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3530 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3531 kvm_xen_runstate_set_running(vcpu);
3535 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3538 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3541 slots = kvm_memslots(vcpu->kvm);
3543 if (unlikely(slots->generation != ghc->generation ||
3545 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3546 /* We rely on the fact that it fits in a single page. */
3547 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3549 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) ||
3550 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3554 st = (struct kvm_steal_time __user *)ghc->hva;
3556 * Doing a TLB flush here, on the guest's behalf, can avoid
3559 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3560 u8 st_preempted = 0;
3563 if (!user_access_begin(st, sizeof(*st)))
3566 asm volatile("1: xchgb %0, %2\n"
3569 _ASM_EXTABLE_UA(1b, 2b)
3570 : "+q" (st_preempted),
3572 "+m" (st->preempted));
3578 vcpu->arch.st.preempted = 0;
3580 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3581 st_preempted & KVM_VCPU_FLUSH_TLB);
3582 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3583 kvm_vcpu_flush_tlb_guest(vcpu);
3585 if (!user_access_begin(st, sizeof(*st)))
3588 if (!user_access_begin(st, sizeof(*st)))
3591 unsafe_put_user(0, &st->preempted, out);
3592 vcpu->arch.st.preempted = 0;
3595 unsafe_get_user(version, &st->version, out);
3597 version += 1; /* first time write, random junk */
3600 unsafe_put_user(version, &st->version, out);
3604 unsafe_get_user(steal, &st->steal, out);
3605 steal += current->sched_info.run_delay -
3606 vcpu->arch.st.last_steal;
3607 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3608 unsafe_put_user(steal, &st->steal, out);
3611 unsafe_put_user(version, &st->version, out);
3616 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3619 static bool kvm_is_msr_to_save(u32 msr_index)
3623 for (i = 0; i < num_msrs_to_save; i++) {
3624 if (msrs_to_save[i] == msr_index)
3631 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3633 u32 msr = msr_info->index;
3634 u64 data = msr_info->data;
3636 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3637 return kvm_xen_write_hypercall_page(vcpu, data);
3640 case MSR_AMD64_NB_CFG:
3641 case MSR_IA32_UCODE_WRITE:
3642 case MSR_VM_HSAVE_PA:
3643 case MSR_AMD64_PATCH_LOADER:
3644 case MSR_AMD64_BU_CFG2:
3645 case MSR_AMD64_DC_CFG:
3646 case MSR_F15H_EX_CFG:
3649 case MSR_IA32_UCODE_REV:
3650 if (msr_info->host_initiated)
3651 vcpu->arch.microcode_version = data;
3653 case MSR_IA32_ARCH_CAPABILITIES:
3654 if (!msr_info->host_initiated)
3656 vcpu->arch.arch_capabilities = data;
3658 case MSR_IA32_PERF_CAPABILITIES:
3659 if (!msr_info->host_initiated)
3661 if (data & ~kvm_caps.supported_perf_cap)
3665 * Note, this is not just a performance optimization! KVM
3666 * disallows changing feature MSRs after the vCPU has run; PMU
3667 * refresh will bug the VM if called after the vCPU has run.
3669 if (vcpu->arch.perf_capabilities == data)
3672 vcpu->arch.perf_capabilities = data;
3673 kvm_pmu_refresh(vcpu);
3675 case MSR_IA32_PRED_CMD:
3676 if (!msr_info->host_initiated && !guest_has_pred_cmd_msr(vcpu))
3679 if (!boot_cpu_has(X86_FEATURE_IBPB) || (data & ~PRED_CMD_IBPB))
3684 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3686 case MSR_IA32_FLUSH_CMD:
3687 if (!msr_info->host_initiated &&
3688 !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D))
3691 if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH))
3696 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
3699 return set_efer(vcpu, msr_info);
3701 data &= ~(u64)0x40; /* ignore flush filter disable */
3702 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3703 data &= ~(u64)0x8; /* ignore TLB cache disable */
3705 /* Handle McStatusWrEn */
3706 if (data == BIT_ULL(18)) {
3707 vcpu->arch.msr_hwcr = data;
3708 } else if (data != 0) {
3709 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3713 case MSR_FAM10H_MMIO_CONF_BASE:
3715 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3719 case MSR_IA32_CR_PAT:
3720 if (!kvm_pat_valid(data))
3723 vcpu->arch.pat = data;
3725 case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000:
3726 case MSR_MTRRdefType:
3727 return kvm_mtrr_set_msr(vcpu, msr, data);
3728 case MSR_IA32_APICBASE:
3729 return kvm_set_apic_base(vcpu, msr_info);
3730 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3731 return kvm_x2apic_msr_write(vcpu, msr, data);
3732 case MSR_IA32_TSC_DEADLINE:
3733 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3735 case MSR_IA32_TSC_ADJUST:
3736 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3737 if (!msr_info->host_initiated) {
3738 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3739 adjust_tsc_offset_guest(vcpu, adj);
3740 /* Before back to guest, tsc_timestamp must be adjusted
3741 * as well, otherwise guest's percpu pvclock time could jump.
3743 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3745 vcpu->arch.ia32_tsc_adjust_msr = data;
3748 case MSR_IA32_MISC_ENABLE: {
3749 u64 old_val = vcpu->arch.ia32_misc_enable_msr;
3751 if (!msr_info->host_initiated) {
3753 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)
3756 /* R bits, i.e. writes are ignored, but don't fault. */
3757 data = data & ~MSR_IA32_MISC_ENABLE_EMON;
3758 data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
3761 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3762 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3763 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3765 vcpu->arch.ia32_misc_enable_msr = data;
3766 kvm_update_cpuid_runtime(vcpu);
3768 vcpu->arch.ia32_misc_enable_msr = data;
3772 case MSR_IA32_SMBASE:
3773 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
3775 vcpu->arch.smbase = data;
3777 case MSR_IA32_POWER_CTL:
3778 vcpu->arch.msr_ia32_power_ctl = data;
3781 if (msr_info->host_initiated) {
3782 kvm_synchronize_tsc(vcpu, data);
3784 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3785 adjust_tsc_offset_guest(vcpu, adj);
3786 vcpu->arch.ia32_tsc_adjust_msr += adj;
3790 if (!msr_info->host_initiated &&
3791 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3794 * KVM supports exposing PT to the guest, but does not support
3795 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3796 * XSAVES/XRSTORS to save/restore PT MSRs.
3798 if (data & ~kvm_caps.supported_xss)
3800 vcpu->arch.ia32_xss = data;
3801 kvm_update_cpuid_runtime(vcpu);
3804 if (!msr_info->host_initiated)
3806 vcpu->arch.smi_count = data;
3808 case MSR_KVM_WALL_CLOCK_NEW:
3809 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3812 vcpu->kvm->arch.wall_clock = data;
3813 kvm_write_wall_clock(vcpu->kvm, data, 0);
3815 case MSR_KVM_WALL_CLOCK:
3816 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3819 vcpu->kvm->arch.wall_clock = data;
3820 kvm_write_wall_clock(vcpu->kvm, data, 0);
3822 case MSR_KVM_SYSTEM_TIME_NEW:
3823 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3826 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3828 case MSR_KVM_SYSTEM_TIME:
3829 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3832 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3834 case MSR_KVM_ASYNC_PF_EN:
3835 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3838 if (kvm_pv_enable_async_pf(vcpu, data))
3841 case MSR_KVM_ASYNC_PF_INT:
3842 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3845 if (kvm_pv_enable_async_pf_int(vcpu, data))
3848 case MSR_KVM_ASYNC_PF_ACK:
3849 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3852 vcpu->arch.apf.pageready_pending = false;
3853 kvm_check_async_pf_completion(vcpu);
3856 case MSR_KVM_STEAL_TIME:
3857 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3860 if (unlikely(!sched_info_on()))
3863 if (data & KVM_STEAL_RESERVED_MASK)
3866 vcpu->arch.st.msr_val = data;
3868 if (!(data & KVM_MSR_ENABLED))
3871 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3874 case MSR_KVM_PV_EOI_EN:
3875 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3878 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3882 case MSR_KVM_POLL_CONTROL:
3883 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3886 /* only enable bit supported */
3887 if (data & (-1ULL << 1))
3890 vcpu->arch.msr_kvm_poll_control = data;
3893 case MSR_IA32_MCG_CTL:
3894 case MSR_IA32_MCG_STATUS:
3895 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3896 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3897 return set_msr_mce(vcpu, msr_info);
3899 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3900 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3901 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3902 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3903 if (kvm_pmu_is_valid_msr(vcpu, msr))
3904 return kvm_pmu_set_msr(vcpu, msr_info);
3907 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3909 case MSR_K7_CLK_CTL:
3911 * Ignore all writes to this no longer documented MSR.
3912 * Writes are only relevant for old K7 processors,
3913 * all pre-dating SVM, but a recommended workaround from
3914 * AMD for these chips. It is possible to specify the
3915 * affected processor models on the command line, hence
3916 * the need to ignore the workaround.
3919 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3920 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3921 case HV_X64_MSR_SYNDBG_OPTIONS:
3922 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3923 case HV_X64_MSR_CRASH_CTL:
3924 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3925 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3926 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3927 case HV_X64_MSR_TSC_EMULATION_STATUS:
3928 case HV_X64_MSR_TSC_INVARIANT_CONTROL:
3929 return kvm_hv_set_msr_common(vcpu, msr, data,
3930 msr_info->host_initiated);
3931 case MSR_IA32_BBL_CR_CTL3:
3932 /* Drop writes to this legacy MSR -- see rdmsr
3933 * counterpart for further detail.
3935 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3937 case MSR_AMD64_OSVW_ID_LENGTH:
3938 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3940 vcpu->arch.osvw.length = data;
3942 case MSR_AMD64_OSVW_STATUS:
3943 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3945 vcpu->arch.osvw.status = data;
3947 case MSR_PLATFORM_INFO:
3948 if (!msr_info->host_initiated ||
3949 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3950 cpuid_fault_enabled(vcpu)))
3952 vcpu->arch.msr_platform_info = data;
3954 case MSR_MISC_FEATURES_ENABLES:
3955 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3956 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3957 !supports_cpuid_fault(vcpu)))
3959 vcpu->arch.msr_misc_features_enables = data;
3961 #ifdef CONFIG_X86_64
3963 if (!msr_info->host_initiated &&
3964 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3967 if (data & ~kvm_guest_supported_xfd(vcpu))
3970 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3972 case MSR_IA32_XFD_ERR:
3973 if (!msr_info->host_initiated &&
3974 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3977 if (data & ~kvm_guest_supported_xfd(vcpu))
3980 vcpu->arch.guest_fpu.xfd_err = data;
3984 if (kvm_pmu_is_valid_msr(vcpu, msr))
3985 return kvm_pmu_set_msr(vcpu, msr_info);
3988 * Userspace is allowed to write '0' to MSRs that KVM reports
3989 * as to-be-saved, even if an MSRs isn't fully supported.
3991 if (msr_info->host_initiated && !data &&
3992 kvm_is_msr_to_save(msr))
3995 return KVM_MSR_RET_INVALID;
3999 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
4001 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
4004 u64 mcg_cap = vcpu->arch.mcg_cap;
4005 unsigned bank_num = mcg_cap & 0xff;
4006 u32 offset, last_msr;
4009 case MSR_IA32_P5_MC_ADDR:
4010 case MSR_IA32_P5_MC_TYPE:
4013 case MSR_IA32_MCG_CAP:
4014 data = vcpu->arch.mcg_cap;
4016 case MSR_IA32_MCG_CTL:
4017 if (!(mcg_cap & MCG_CTL_P) && !host)
4019 data = vcpu->arch.mcg_ctl;
4021 case MSR_IA32_MCG_STATUS:
4022 data = vcpu->arch.mcg_status;
4024 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4025 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
4029 if (!(mcg_cap & MCG_CMCI_P) && !host)
4031 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
4032 last_msr + 1 - MSR_IA32_MC0_CTL2);
4033 data = vcpu->arch.mci_ctl2_banks[offset];
4035 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4036 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
4040 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
4041 last_msr + 1 - MSR_IA32_MC0_CTL);
4042 data = vcpu->arch.mce_banks[offset];
4051 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4053 switch (msr_info->index) {
4054 case MSR_IA32_PLATFORM_ID:
4055 case MSR_IA32_EBL_CR_POWERON:
4056 case MSR_IA32_LASTBRANCHFROMIP:
4057 case MSR_IA32_LASTBRANCHTOIP:
4058 case MSR_IA32_LASTINTFROMIP:
4059 case MSR_IA32_LASTINTTOIP:
4060 case MSR_AMD64_SYSCFG:
4061 case MSR_K8_TSEG_ADDR:
4062 case MSR_K8_TSEG_MASK:
4063 case MSR_VM_HSAVE_PA:
4064 case MSR_K8_INT_PENDING_MSG:
4065 case MSR_AMD64_NB_CFG:
4066 case MSR_FAM10H_MMIO_CONF_BASE:
4067 case MSR_AMD64_BU_CFG2:
4068 case MSR_IA32_PERF_CTL:
4069 case MSR_AMD64_DC_CFG:
4070 case MSR_F15H_EX_CFG:
4072 * Intel Sandy Bridge CPUs must support the RAPL (running average power
4073 * limit) MSRs. Just return 0, as we do not want to expose the host
4074 * data here. Do not conditionalize this on CPUID, as KVM does not do
4075 * so for existing CPU-specific MSRs.
4077 case MSR_RAPL_POWER_UNIT:
4078 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
4079 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
4080 case MSR_PKG_ENERGY_STATUS: /* Total package */
4081 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
4084 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
4085 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
4086 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
4087 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
4088 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4089 return kvm_pmu_get_msr(vcpu, msr_info);
4092 case MSR_IA32_UCODE_REV:
4093 msr_info->data = vcpu->arch.microcode_version;
4095 case MSR_IA32_ARCH_CAPABILITIES:
4096 if (!msr_info->host_initiated &&
4097 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4099 msr_info->data = vcpu->arch.arch_capabilities;
4101 case MSR_IA32_PERF_CAPABILITIES:
4102 if (!msr_info->host_initiated &&
4103 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
4105 msr_info->data = vcpu->arch.perf_capabilities;
4107 case MSR_IA32_POWER_CTL:
4108 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
4110 case MSR_IA32_TSC: {
4112 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
4113 * even when not intercepted. AMD manual doesn't explicitly
4114 * state this but appears to behave the same.
4116 * On userspace reads and writes, however, we unconditionally
4117 * return L1's TSC value to ensure backwards-compatible
4118 * behavior for migration.
4122 if (msr_info->host_initiated) {
4123 offset = vcpu->arch.l1_tsc_offset;
4124 ratio = vcpu->arch.l1_tsc_scaling_ratio;
4126 offset = vcpu->arch.tsc_offset;
4127 ratio = vcpu->arch.tsc_scaling_ratio;
4130 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
4133 case MSR_IA32_CR_PAT:
4134 msr_info->data = vcpu->arch.pat;
4137 case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000:
4138 case MSR_MTRRdefType:
4139 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
4140 case 0xcd: /* fsb frequency */
4144 * MSR_EBC_FREQUENCY_ID
4145 * Conservative value valid for even the basic CPU models.
4146 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
4147 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
4148 * and 266MHz for model 3, or 4. Set Core Clock
4149 * Frequency to System Bus Frequency Ratio to 1 (bits
4150 * 31:24) even though these are only valid for CPU
4151 * models > 2, however guests may end up dividing or
4152 * multiplying by zero otherwise.
4154 case MSR_EBC_FREQUENCY_ID:
4155 msr_info->data = 1 << 24;
4157 case MSR_IA32_APICBASE:
4158 msr_info->data = kvm_get_apic_base(vcpu);
4160 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
4161 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
4162 case MSR_IA32_TSC_DEADLINE:
4163 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
4165 case MSR_IA32_TSC_ADJUST:
4166 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
4168 case MSR_IA32_MISC_ENABLE:
4169 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
4171 case MSR_IA32_SMBASE:
4172 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
4174 msr_info->data = vcpu->arch.smbase;
4177 msr_info->data = vcpu->arch.smi_count;
4179 case MSR_IA32_PERF_STATUS:
4180 /* TSC increment by tick */
4181 msr_info->data = 1000ULL;
4182 /* CPU multiplier */
4183 msr_info->data |= (((uint64_t)4ULL) << 40);
4186 msr_info->data = vcpu->arch.efer;
4188 case MSR_KVM_WALL_CLOCK:
4189 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4192 msr_info->data = vcpu->kvm->arch.wall_clock;
4194 case MSR_KVM_WALL_CLOCK_NEW:
4195 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4198 msr_info->data = vcpu->kvm->arch.wall_clock;
4200 case MSR_KVM_SYSTEM_TIME:
4201 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4204 msr_info->data = vcpu->arch.time;
4206 case MSR_KVM_SYSTEM_TIME_NEW:
4207 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4210 msr_info->data = vcpu->arch.time;
4212 case MSR_KVM_ASYNC_PF_EN:
4213 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4216 msr_info->data = vcpu->arch.apf.msr_en_val;
4218 case MSR_KVM_ASYNC_PF_INT:
4219 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4222 msr_info->data = vcpu->arch.apf.msr_int_val;
4224 case MSR_KVM_ASYNC_PF_ACK:
4225 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4230 case MSR_KVM_STEAL_TIME:
4231 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4234 msr_info->data = vcpu->arch.st.msr_val;
4236 case MSR_KVM_PV_EOI_EN:
4237 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4240 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4242 case MSR_KVM_POLL_CONTROL:
4243 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4246 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4248 case MSR_IA32_P5_MC_ADDR:
4249 case MSR_IA32_P5_MC_TYPE:
4250 case MSR_IA32_MCG_CAP:
4251 case MSR_IA32_MCG_CTL:
4252 case MSR_IA32_MCG_STATUS:
4253 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4254 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4255 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4256 msr_info->host_initiated);
4258 if (!msr_info->host_initiated &&
4259 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4261 msr_info->data = vcpu->arch.ia32_xss;
4263 case MSR_K7_CLK_CTL:
4265 * Provide expected ramp-up count for K7. All other
4266 * are set to zero, indicating minimum divisors for
4269 * This prevents guest kernels on AMD host with CPU
4270 * type 6, model 8 and higher from exploding due to
4271 * the rdmsr failing.
4273 msr_info->data = 0x20000000;
4275 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4276 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4277 case HV_X64_MSR_SYNDBG_OPTIONS:
4278 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4279 case HV_X64_MSR_CRASH_CTL:
4280 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4281 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4282 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4283 case HV_X64_MSR_TSC_EMULATION_STATUS:
4284 case HV_X64_MSR_TSC_INVARIANT_CONTROL:
4285 return kvm_hv_get_msr_common(vcpu,
4286 msr_info->index, &msr_info->data,
4287 msr_info->host_initiated);
4288 case MSR_IA32_BBL_CR_CTL3:
4289 /* This legacy MSR exists but isn't fully documented in current
4290 * silicon. It is however accessed by winxp in very narrow
4291 * scenarios where it sets bit #19, itself documented as
4292 * a "reserved" bit. Best effort attempt to source coherent
4293 * read data here should the balance of the register be
4294 * interpreted by the guest:
4296 * L2 cache control register 3: 64GB range, 256KB size,
4297 * enabled, latency 0x1, configured
4299 msr_info->data = 0xbe702111;
4301 case MSR_AMD64_OSVW_ID_LENGTH:
4302 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4304 msr_info->data = vcpu->arch.osvw.length;
4306 case MSR_AMD64_OSVW_STATUS:
4307 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4309 msr_info->data = vcpu->arch.osvw.status;
4311 case MSR_PLATFORM_INFO:
4312 if (!msr_info->host_initiated &&
4313 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4315 msr_info->data = vcpu->arch.msr_platform_info;
4317 case MSR_MISC_FEATURES_ENABLES:
4318 msr_info->data = vcpu->arch.msr_misc_features_enables;
4321 msr_info->data = vcpu->arch.msr_hwcr;
4323 #ifdef CONFIG_X86_64
4325 if (!msr_info->host_initiated &&
4326 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4329 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4331 case MSR_IA32_XFD_ERR:
4332 if (!msr_info->host_initiated &&
4333 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4336 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4340 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4341 return kvm_pmu_get_msr(vcpu, msr_info);
4344 * Userspace is allowed to read MSRs that KVM reports as
4345 * to-be-saved, even if an MSR isn't fully supported.
4347 if (msr_info->host_initiated &&
4348 kvm_is_msr_to_save(msr_info->index)) {
4353 return KVM_MSR_RET_INVALID;
4357 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4360 * Read or write a bunch of msrs. All parameters are kernel addresses.
4362 * @return number of msrs set successfully.
4364 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4365 struct kvm_msr_entry *entries,
4366 int (*do_msr)(struct kvm_vcpu *vcpu,
4367 unsigned index, u64 *data))
4371 for (i = 0; i < msrs->nmsrs; ++i)
4372 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4379 * Read or write a bunch of msrs. Parameters are user addresses.
4381 * @return number of msrs set successfully.
4383 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4384 int (*do_msr)(struct kvm_vcpu *vcpu,
4385 unsigned index, u64 *data),
4388 struct kvm_msrs msrs;
4389 struct kvm_msr_entry *entries;
4394 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4398 if (msrs.nmsrs >= MAX_IO_MSRS)
4401 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4402 entries = memdup_user(user_msrs->entries, size);
4403 if (IS_ERR(entries)) {
4404 r = PTR_ERR(entries);
4408 r = __msr_io(vcpu, &msrs, entries, do_msr);
4410 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4418 static inline bool kvm_can_mwait_in_guest(void)
4420 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4421 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4422 boot_cpu_has(X86_FEATURE_ARAT);
4425 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4426 struct kvm_cpuid2 __user *cpuid_arg)
4428 struct kvm_cpuid2 cpuid;
4432 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4435 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4440 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4446 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4451 case KVM_CAP_IRQCHIP:
4453 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4454 case KVM_CAP_SET_TSS_ADDR:
4455 case KVM_CAP_EXT_CPUID:
4456 case KVM_CAP_EXT_EMUL_CPUID:
4457 case KVM_CAP_CLOCKSOURCE:
4459 case KVM_CAP_NOP_IO_DELAY:
4460 case KVM_CAP_MP_STATE:
4461 case KVM_CAP_SYNC_MMU:
4462 case KVM_CAP_USER_NMI:
4463 case KVM_CAP_REINJECT_CONTROL:
4464 case KVM_CAP_IRQ_INJECT_STATUS:
4465 case KVM_CAP_IOEVENTFD:
4466 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4468 case KVM_CAP_PIT_STATE2:
4469 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4470 case KVM_CAP_VCPU_EVENTS:
4471 case KVM_CAP_HYPERV:
4472 case KVM_CAP_HYPERV_VAPIC:
4473 case KVM_CAP_HYPERV_SPIN:
4474 case KVM_CAP_HYPERV_SYNIC:
4475 case KVM_CAP_HYPERV_SYNIC2:
4476 case KVM_CAP_HYPERV_VP_INDEX:
4477 case KVM_CAP_HYPERV_EVENTFD:
4478 case KVM_CAP_HYPERV_TLBFLUSH:
4479 case KVM_CAP_HYPERV_SEND_IPI:
4480 case KVM_CAP_HYPERV_CPUID:
4481 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4482 case KVM_CAP_SYS_HYPERV_CPUID:
4483 case KVM_CAP_PCI_SEGMENT:
4484 case KVM_CAP_DEBUGREGS:
4485 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4487 case KVM_CAP_ASYNC_PF:
4488 case KVM_CAP_ASYNC_PF_INT:
4489 case KVM_CAP_GET_TSC_KHZ:
4490 case KVM_CAP_KVMCLOCK_CTRL:
4491 case KVM_CAP_READONLY_MEM:
4492 case KVM_CAP_HYPERV_TIME:
4493 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4494 case KVM_CAP_TSC_DEADLINE_TIMER:
4495 case KVM_CAP_DISABLE_QUIRKS:
4496 case KVM_CAP_SET_BOOT_CPU_ID:
4497 case KVM_CAP_SPLIT_IRQCHIP:
4498 case KVM_CAP_IMMEDIATE_EXIT:
4499 case KVM_CAP_PMU_EVENT_FILTER:
4500 case KVM_CAP_PMU_EVENT_MASKED_EVENTS:
4501 case KVM_CAP_GET_MSR_FEATURES:
4502 case KVM_CAP_MSR_PLATFORM_INFO:
4503 case KVM_CAP_EXCEPTION_PAYLOAD:
4504 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
4505 case KVM_CAP_SET_GUEST_DEBUG:
4506 case KVM_CAP_LAST_CPU:
4507 case KVM_CAP_X86_USER_SPACE_MSR:
4508 case KVM_CAP_X86_MSR_FILTER:
4509 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4510 #ifdef CONFIG_X86_SGX_KVM
4511 case KVM_CAP_SGX_ATTRIBUTE:
4513 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4514 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4515 case KVM_CAP_SREGS2:
4516 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4517 case KVM_CAP_VCPU_ATTRIBUTES:
4518 case KVM_CAP_SYS_ATTRIBUTES:
4520 case KVM_CAP_ENABLE_CAP:
4521 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
4522 case KVM_CAP_IRQFD_RESAMPLE:
4525 case KVM_CAP_EXIT_HYPERCALL:
4526 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4528 case KVM_CAP_SET_GUEST_DEBUG2:
4529 return KVM_GUESTDBG_VALID_MASK;
4530 #ifdef CONFIG_KVM_XEN
4531 case KVM_CAP_XEN_HVM:
4532 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4533 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4534 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4535 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4536 KVM_XEN_HVM_CONFIG_EVTCHN_SEND;
4537 if (sched_info_on())
4538 r |= KVM_XEN_HVM_CONFIG_RUNSTATE |
4539 KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG;
4542 case KVM_CAP_SYNC_REGS:
4543 r = KVM_SYNC_X86_VALID_FIELDS;
4545 case KVM_CAP_ADJUST_CLOCK:
4546 r = KVM_CLOCK_VALID_FLAGS;
4548 case KVM_CAP_X86_DISABLE_EXITS:
4549 r = KVM_X86_DISABLE_EXITS_PAUSE;
4551 if (!mitigate_smt_rsb) {
4552 r |= KVM_X86_DISABLE_EXITS_HLT |
4553 KVM_X86_DISABLE_EXITS_CSTATE;
4555 if (kvm_can_mwait_in_guest())
4556 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4559 case KVM_CAP_X86_SMM:
4560 if (!IS_ENABLED(CONFIG_KVM_SMM))
4563 /* SMBASE is usually relocated above 1M on modern chipsets,
4564 * and SMM handlers might indeed rely on 4G segment limits,
4565 * so do not report SMM to be available if real mode is
4566 * emulated via vm86 mode. Still, do not go to great lengths
4567 * to avoid userspace's usage of the feature, because it is a
4568 * fringe case that is not enabled except via specific settings
4569 * of the module parameters.
4571 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4573 case KVM_CAP_NR_VCPUS:
4574 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4576 case KVM_CAP_MAX_VCPUS:
4579 case KVM_CAP_MAX_VCPU_ID:
4580 r = KVM_MAX_VCPU_IDS;
4582 case KVM_CAP_PV_MMU: /* obsolete */
4586 r = KVM_MAX_MCE_BANKS;
4589 r = boot_cpu_has(X86_FEATURE_XSAVE);
4591 case KVM_CAP_TSC_CONTROL:
4592 case KVM_CAP_VM_TSC_CONTROL:
4593 r = kvm_caps.has_tsc_control;
4595 case KVM_CAP_X2APIC_API:
4596 r = KVM_X2APIC_API_VALID_FLAGS;
4598 case KVM_CAP_NESTED_STATE:
4599 r = kvm_x86_ops.nested_ops->get_state ?
4600 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4602 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4603 r = kvm_x86_ops.enable_l2_tlb_flush != NULL;
4605 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4606 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4608 case KVM_CAP_SMALLER_MAXPHYADDR:
4609 r = (int) allow_smaller_maxphyaddr;
4611 case KVM_CAP_STEAL_TIME:
4612 r = sched_info_on();
4614 case KVM_CAP_X86_BUS_LOCK_EXIT:
4615 if (kvm_caps.has_bus_lock_exit)
4616 r = KVM_BUS_LOCK_DETECTION_OFF |
4617 KVM_BUS_LOCK_DETECTION_EXIT;
4621 case KVM_CAP_XSAVE2: {
4622 r = xstate_required_size(kvm_get_filtered_xcr0(), false);
4623 if (r < sizeof(struct kvm_xsave))
4624 r = sizeof(struct kvm_xsave);
4627 case KVM_CAP_PMU_CAPABILITY:
4628 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4630 case KVM_CAP_DISABLE_QUIRKS2:
4631 r = KVM_X86_VALID_QUIRKS;
4633 case KVM_CAP_X86_NOTIFY_VMEXIT:
4634 r = kvm_caps.has_notify_vmexit;
4642 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4644 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4646 if ((u64)(unsigned long)uaddr != attr->addr)
4647 return ERR_PTR_USR(-EFAULT);
4651 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4653 u64 __user *uaddr = kvm_get_attr_addr(attr);
4659 return PTR_ERR(uaddr);
4661 switch (attr->attr) {
4662 case KVM_X86_XCOMP_GUEST_SUPP:
4663 if (put_user(kvm_caps.supported_xcr0, uaddr))
4672 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4677 switch (attr->attr) {
4678 case KVM_X86_XCOMP_GUEST_SUPP:
4685 long kvm_arch_dev_ioctl(struct file *filp,
4686 unsigned int ioctl, unsigned long arg)
4688 void __user *argp = (void __user *)arg;
4692 case KVM_GET_MSR_INDEX_LIST: {
4693 struct kvm_msr_list __user *user_msr_list = argp;
4694 struct kvm_msr_list msr_list;
4698 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4701 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4702 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4705 if (n < msr_list.nmsrs)
4708 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4709 num_msrs_to_save * sizeof(u32)))
4711 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4713 num_emulated_msrs * sizeof(u32)))
4718 case KVM_GET_SUPPORTED_CPUID:
4719 case KVM_GET_EMULATED_CPUID: {
4720 struct kvm_cpuid2 __user *cpuid_arg = argp;
4721 struct kvm_cpuid2 cpuid;
4724 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4727 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4733 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4738 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4740 if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
4741 sizeof(kvm_caps.supported_mce_cap)))
4745 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4746 struct kvm_msr_list __user *user_msr_list = argp;
4747 struct kvm_msr_list msr_list;
4751 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4754 msr_list.nmsrs = num_msr_based_features;
4755 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4758 if (n < msr_list.nmsrs)
4761 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4762 num_msr_based_features * sizeof(u32)))
4768 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4770 case KVM_GET_SUPPORTED_HV_CPUID:
4771 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4773 case KVM_GET_DEVICE_ATTR: {
4774 struct kvm_device_attr attr;
4776 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4778 r = kvm_x86_dev_get_attr(&attr);
4781 case KVM_HAS_DEVICE_ATTR: {
4782 struct kvm_device_attr attr;
4784 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4786 r = kvm_x86_dev_has_attr(&attr);
4797 static void wbinvd_ipi(void *garbage)
4802 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4804 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4807 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4809 /* Address WBINVD may be executed by guest */
4810 if (need_emulate_wbinvd(vcpu)) {
4811 if (static_call(kvm_x86_has_wbinvd_exit)())
4812 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4813 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4814 smp_call_function_single(vcpu->cpu,
4815 wbinvd_ipi, NULL, 1);
4818 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4820 /* Save host pkru register if supported */
4821 vcpu->arch.host_pkru = read_pkru();
4823 /* Apply any externally detected TSC adjustments (due to suspend) */
4824 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4825 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4826 vcpu->arch.tsc_offset_adjustment = 0;
4827 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4830 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4831 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4832 rdtsc() - vcpu->arch.last_host_tsc;
4834 mark_tsc_unstable("KVM discovered backwards TSC");
4836 if (kvm_check_tsc_unstable()) {
4837 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4838 vcpu->arch.last_guest_tsc);
4839 kvm_vcpu_write_tsc_offset(vcpu, offset);
4840 vcpu->arch.tsc_catchup = 1;
4843 if (kvm_lapic_hv_timer_in_use(vcpu))
4844 kvm_lapic_restart_hv_timer(vcpu);
4847 * On a host with synchronized TSC, there is no need to update
4848 * kvmclock on vcpu->cpu migration
4850 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4851 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4852 if (vcpu->cpu != cpu)
4853 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4857 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4860 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4862 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4863 struct kvm_steal_time __user *st;
4864 struct kvm_memslots *slots;
4865 static const u8 preempted = KVM_VCPU_PREEMPTED;
4866 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
4869 * The vCPU can be marked preempted if and only if the VM-Exit was on
4870 * an instruction boundary and will not trigger guest emulation of any
4871 * kind (see vcpu_run). Vendor specific code controls (conservatively)
4872 * when this is true, for example allowing the vCPU to be marked
4873 * preempted if and only if the VM-Exit was due to a host interrupt.
4875 if (!vcpu->arch.at_instruction_boundary) {
4876 vcpu->stat.preemption_other++;
4880 vcpu->stat.preemption_reported++;
4881 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4884 if (vcpu->arch.st.preempted)
4887 /* This happens on process exit */
4888 if (unlikely(current->mm != vcpu->kvm->mm))
4891 slots = kvm_memslots(vcpu->kvm);
4893 if (unlikely(slots->generation != ghc->generation ||
4895 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4898 st = (struct kvm_steal_time __user *)ghc->hva;
4899 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4901 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4902 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4904 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4907 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4911 if (vcpu->preempted) {
4912 if (!vcpu->arch.guest_state_protected)
4913 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4916 * Take the srcu lock as memslots will be accessed to check the gfn
4917 * cache generation against the memslots generation.
4919 idx = srcu_read_lock(&vcpu->kvm->srcu);
4920 if (kvm_xen_msr_enabled(vcpu->kvm))
4921 kvm_xen_runstate_set_preempted(vcpu);
4923 kvm_steal_time_set_preempted(vcpu);
4924 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4927 static_call(kvm_x86_vcpu_put)(vcpu);
4928 vcpu->arch.last_host_tsc = rdtsc();
4931 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4932 struct kvm_lapic_state *s)
4934 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4936 return kvm_apic_get_state(vcpu, s);
4939 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4940 struct kvm_lapic_state *s)
4944 r = kvm_apic_set_state(vcpu, s);
4947 update_cr8_intercept(vcpu);
4952 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4955 * We can accept userspace's request for interrupt injection
4956 * as long as we have a place to store the interrupt number.
4957 * The actual injection will happen when the CPU is able to
4958 * deliver the interrupt.
4960 if (kvm_cpu_has_extint(vcpu))
4963 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4964 return (!lapic_in_kernel(vcpu) ||
4965 kvm_apic_accept_pic_intr(vcpu));
4968 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4971 * Do not cause an interrupt window exit if an exception
4972 * is pending or an event needs reinjection; userspace
4973 * might want to inject the interrupt manually using KVM_SET_REGS
4974 * or KVM_SET_SREGS. For that to work, we must be at an
4975 * instruction boundary and with no events half-injected.
4977 return (kvm_arch_interrupt_allowed(vcpu) &&
4978 kvm_cpu_accept_dm_intr(vcpu) &&
4979 !kvm_event_needs_reinjection(vcpu) &&
4980 !kvm_is_exception_pending(vcpu));
4983 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4984 struct kvm_interrupt *irq)
4986 if (irq->irq >= KVM_NR_INTERRUPTS)
4989 if (!irqchip_in_kernel(vcpu->kvm)) {
4990 kvm_queue_interrupt(vcpu, irq->irq, false);
4991 kvm_make_request(KVM_REQ_EVENT, vcpu);
4996 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4997 * fail for in-kernel 8259.
4999 if (pic_in_kernel(vcpu->kvm))
5002 if (vcpu->arch.pending_external_vector != -1)
5005 vcpu->arch.pending_external_vector = irq->irq;
5006 kvm_make_request(KVM_REQ_EVENT, vcpu);
5010 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
5012 kvm_inject_nmi(vcpu);
5017 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
5018 struct kvm_tpr_access_ctl *tac)
5022 vcpu->arch.tpr_access_reporting = !!tac->enabled;
5026 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
5030 unsigned bank_num = mcg_cap & 0xff, bank;
5033 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
5035 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
5038 vcpu->arch.mcg_cap = mcg_cap;
5039 /* Init IA32_MCG_CTL to all 1s */
5040 if (mcg_cap & MCG_CTL_P)
5041 vcpu->arch.mcg_ctl = ~(u64)0;
5042 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
5043 for (bank = 0; bank < bank_num; bank++) {
5044 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
5045 if (mcg_cap & MCG_CMCI_P)
5046 vcpu->arch.mci_ctl2_banks[bank] = 0;
5049 kvm_apic_after_set_mcg_cap(vcpu);
5051 static_call(kvm_x86_setup_mce)(vcpu);
5057 * Validate this is an UCNA (uncorrectable no action) error by checking the
5058 * MCG_STATUS and MCi_STATUS registers:
5059 * - none of the bits for Machine Check Exceptions are set
5060 * - both the VAL (valid) and UC (uncorrectable) bits are set
5061 * MCI_STATUS_PCC - Processor Context Corrupted
5062 * MCI_STATUS_S - Signaled as a Machine Check Exception
5063 * MCI_STATUS_AR - Software recoverable Action Required
5065 static bool is_ucna(struct kvm_x86_mce *mce)
5067 return !mce->mcg_status &&
5068 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) &&
5069 (mce->status & MCI_STATUS_VAL) &&
5070 (mce->status & MCI_STATUS_UC);
5073 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks)
5075 u64 mcg_cap = vcpu->arch.mcg_cap;
5077 banks[1] = mce->status;
5078 banks[2] = mce->addr;
5079 banks[3] = mce->misc;
5080 vcpu->arch.mcg_status = mce->mcg_status;
5082 if (!(mcg_cap & MCG_CMCI_P) ||
5083 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
5086 if (lapic_in_kernel(vcpu))
5087 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);
5092 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
5093 struct kvm_x86_mce *mce)
5095 u64 mcg_cap = vcpu->arch.mcg_cap;
5096 unsigned bank_num = mcg_cap & 0xff;
5097 u64 *banks = vcpu->arch.mce_banks;
5099 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
5102 banks += array_index_nospec(4 * mce->bank, 4 * bank_num);
5105 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks);
5108 * if IA32_MCG_CTL is not all 1s, the uncorrected error
5109 * reporting is disabled
5111 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
5112 vcpu->arch.mcg_ctl != ~(u64)0)
5115 * if IA32_MCi_CTL is not all 1s, the uncorrected error
5116 * reporting is disabled for the bank
5118 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
5120 if (mce->status & MCI_STATUS_UC) {
5121 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
5122 !kvm_is_cr4_bit_set(vcpu, X86_CR4_MCE)) {
5123 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5126 if (banks[1] & MCI_STATUS_VAL)
5127 mce->status |= MCI_STATUS_OVER;
5128 banks[2] = mce->addr;
5129 banks[3] = mce->misc;
5130 vcpu->arch.mcg_status = mce->mcg_status;
5131 banks[1] = mce->status;
5132 kvm_queue_exception(vcpu, MC_VECTOR);
5133 } else if (!(banks[1] & MCI_STATUS_VAL)
5134 || !(banks[1] & MCI_STATUS_UC)) {
5135 if (banks[1] & MCI_STATUS_VAL)
5136 mce->status |= MCI_STATUS_OVER;
5137 banks[2] = mce->addr;
5138 banks[3] = mce->misc;
5139 banks[1] = mce->status;
5141 banks[1] |= MCI_STATUS_OVER;
5145 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
5146 struct kvm_vcpu_events *events)
5148 struct kvm_queued_exception *ex;
5152 #ifdef CONFIG_KVM_SMM
5153 if (kvm_check_request(KVM_REQ_SMI, vcpu))
5158 * KVM's ABI only allows for one exception to be migrated. Luckily,
5159 * the only time there can be two queued exceptions is if there's a
5160 * non-exiting _injected_ exception, and a pending exiting exception.
5161 * In that case, ignore the VM-Exiting exception as it's an extension
5162 * of the injected exception.
5164 if (vcpu->arch.exception_vmexit.pending &&
5165 !vcpu->arch.exception.pending &&
5166 !vcpu->arch.exception.injected)
5167 ex = &vcpu->arch.exception_vmexit;
5169 ex = &vcpu->arch.exception;
5172 * In guest mode, payload delivery should be deferred if the exception
5173 * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1
5174 * intercepts #PF, ditto for DR6 and #DBs. If the per-VM capability,
5175 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not
5176 * propagate the payload and so it cannot be safely deferred. Deliver
5177 * the payload if the capability hasn't been requested.
5179 if (!vcpu->kvm->arch.exception_payload_enabled &&
5180 ex->pending && ex->has_payload)
5181 kvm_deliver_exception_payload(vcpu, ex);
5183 memset(events, 0, sizeof(*events));
5186 * The API doesn't provide the instruction length for software
5187 * exceptions, so don't report them. As long as the guest RIP
5188 * isn't advanced, we should expect to encounter the exception
5191 if (!kvm_exception_is_soft(ex->vector)) {
5192 events->exception.injected = ex->injected;
5193 events->exception.pending = ex->pending;
5195 * For ABI compatibility, deliberately conflate
5196 * pending and injected exceptions when
5197 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
5199 if (!vcpu->kvm->arch.exception_payload_enabled)
5200 events->exception.injected |= ex->pending;
5202 events->exception.nr = ex->vector;
5203 events->exception.has_error_code = ex->has_error_code;
5204 events->exception.error_code = ex->error_code;
5205 events->exception_has_payload = ex->has_payload;
5206 events->exception_payload = ex->payload;
5208 events->interrupt.injected =
5209 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
5210 events->interrupt.nr = vcpu->arch.interrupt.nr;
5211 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
5213 events->nmi.injected = vcpu->arch.nmi_injected;
5214 events->nmi.pending = kvm_get_nr_pending_nmis(vcpu);
5215 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
5217 /* events->sipi_vector is never valid when reporting to user space */
5219 #ifdef CONFIG_KVM_SMM
5220 events->smi.smm = is_smm(vcpu);
5221 events->smi.pending = vcpu->arch.smi_pending;
5222 events->smi.smm_inside_nmi =
5223 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
5225 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
5227 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
5228 | KVM_VCPUEVENT_VALID_SHADOW
5229 | KVM_VCPUEVENT_VALID_SMM);
5230 if (vcpu->kvm->arch.exception_payload_enabled)
5231 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5232 if (vcpu->kvm->arch.triple_fault_event) {
5233 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5234 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5238 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
5239 struct kvm_vcpu_events *events)
5241 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
5242 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
5243 | KVM_VCPUEVENT_VALID_SHADOW
5244 | KVM_VCPUEVENT_VALID_SMM
5245 | KVM_VCPUEVENT_VALID_PAYLOAD
5246 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
5249 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5250 if (!vcpu->kvm->arch.exception_payload_enabled)
5252 if (events->exception.pending)
5253 events->exception.injected = 0;
5255 events->exception_has_payload = 0;
5257 events->exception.pending = 0;
5258 events->exception_has_payload = 0;
5261 if ((events->exception.injected || events->exception.pending) &&
5262 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
5265 /* INITs are latched while in SMM */
5266 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
5267 (events->smi.smm || events->smi.pending) &&
5268 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
5274 * Flag that userspace is stuffing an exception, the next KVM_RUN will
5275 * morph the exception to a VM-Exit if appropriate. Do this only for
5276 * pending exceptions, already-injected exceptions are not subject to
5277 * intercpetion. Note, userspace that conflates pending and injected
5278 * is hosed, and will incorrectly convert an injected exception into a
5279 * pending exception, which in turn may cause a spurious VM-Exit.
5281 vcpu->arch.exception_from_userspace = events->exception.pending;
5283 vcpu->arch.exception_vmexit.pending = false;
5285 vcpu->arch.exception.injected = events->exception.injected;
5286 vcpu->arch.exception.pending = events->exception.pending;
5287 vcpu->arch.exception.vector = events->exception.nr;
5288 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
5289 vcpu->arch.exception.error_code = events->exception.error_code;
5290 vcpu->arch.exception.has_payload = events->exception_has_payload;
5291 vcpu->arch.exception.payload = events->exception_payload;
5293 vcpu->arch.interrupt.injected = events->interrupt.injected;
5294 vcpu->arch.interrupt.nr = events->interrupt.nr;
5295 vcpu->arch.interrupt.soft = events->interrupt.soft;
5296 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
5297 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
5298 events->interrupt.shadow);
5300 vcpu->arch.nmi_injected = events->nmi.injected;
5301 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) {
5302 vcpu->arch.nmi_pending = 0;
5303 atomic_set(&vcpu->arch.nmi_queued, events->nmi.pending);
5304 kvm_make_request(KVM_REQ_NMI, vcpu);
5306 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
5308 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
5309 lapic_in_kernel(vcpu))
5310 vcpu->arch.apic->sipi_vector = events->sipi_vector;
5312 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
5313 #ifdef CONFIG_KVM_SMM
5314 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
5315 kvm_leave_nested(vcpu);
5316 kvm_smm_changed(vcpu, events->smi.smm);
5319 vcpu->arch.smi_pending = events->smi.pending;
5321 if (events->smi.smm) {
5322 if (events->smi.smm_inside_nmi)
5323 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
5325 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
5329 if (events->smi.smm || events->smi.pending ||
5330 events->smi.smm_inside_nmi)
5334 if (lapic_in_kernel(vcpu)) {
5335 if (events->smi.latched_init)
5336 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5338 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5342 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5343 if (!vcpu->kvm->arch.triple_fault_event)
5345 if (events->triple_fault.pending)
5346 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5348 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5351 kvm_make_request(KVM_REQ_EVENT, vcpu);
5356 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
5357 struct kvm_debugregs *dbgregs)
5361 memset(dbgregs, 0, sizeof(*dbgregs));
5362 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5363 kvm_get_dr(vcpu, 6, &val);
5365 dbgregs->dr7 = vcpu->arch.dr7;
5368 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5369 struct kvm_debugregs *dbgregs)
5374 if (!kvm_dr6_valid(dbgregs->dr6))
5376 if (!kvm_dr7_valid(dbgregs->dr7))
5379 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5380 kvm_update_dr0123(vcpu);
5381 vcpu->arch.dr6 = dbgregs->dr6;
5382 vcpu->arch.dr7 = dbgregs->dr7;
5383 kvm_update_dr7(vcpu);
5388 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5389 struct kvm_xsave *guest_xsave)
5391 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5394 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5395 guest_xsave->region,
5396 sizeof(guest_xsave->region),
5400 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5401 u8 *state, unsigned int size)
5403 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5406 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5407 state, size, vcpu->arch.pkru);
5410 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5411 struct kvm_xsave *guest_xsave)
5413 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5416 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5417 guest_xsave->region,
5418 kvm_caps.supported_xcr0,
5422 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5423 struct kvm_xcrs *guest_xcrs)
5425 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5426 guest_xcrs->nr_xcrs = 0;
5430 guest_xcrs->nr_xcrs = 1;
5431 guest_xcrs->flags = 0;
5432 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5433 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5436 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5437 struct kvm_xcrs *guest_xcrs)
5441 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5444 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5447 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5448 /* Only support XCR0 currently */
5449 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5450 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5451 guest_xcrs->xcrs[i].value);
5460 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5461 * stopped by the hypervisor. This function will be called from the host only.
5462 * EINVAL is returned when the host attempts to set the flag for a guest that
5463 * does not support pv clocks.
5465 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5467 if (!vcpu->arch.pv_time.active)
5469 vcpu->arch.pvclock_set_guest_stopped_request = true;
5470 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5474 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5475 struct kvm_device_attr *attr)
5479 switch (attr->attr) {
5480 case KVM_VCPU_TSC_OFFSET:
5490 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5491 struct kvm_device_attr *attr)
5493 u64 __user *uaddr = kvm_get_attr_addr(attr);
5497 return PTR_ERR(uaddr);
5499 switch (attr->attr) {
5500 case KVM_VCPU_TSC_OFFSET:
5502 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5513 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5514 struct kvm_device_attr *attr)
5516 u64 __user *uaddr = kvm_get_attr_addr(attr);
5517 struct kvm *kvm = vcpu->kvm;
5521 return PTR_ERR(uaddr);
5523 switch (attr->attr) {
5524 case KVM_VCPU_TSC_OFFSET: {
5525 u64 offset, tsc, ns;
5526 unsigned long flags;
5530 if (get_user(offset, uaddr))
5533 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5535 matched = (vcpu->arch.virtual_tsc_khz &&
5536 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5537 kvm->arch.last_tsc_offset == offset);
5539 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5540 ns = get_kvmclock_base_ns();
5542 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5543 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5555 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5559 struct kvm_device_attr attr;
5562 if (copy_from_user(&attr, argp, sizeof(attr)))
5565 if (attr.group != KVM_VCPU_TSC_CTRL)
5569 case KVM_HAS_DEVICE_ATTR:
5570 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5572 case KVM_GET_DEVICE_ATTR:
5573 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5575 case KVM_SET_DEVICE_ATTR:
5576 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5583 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5584 struct kvm_enable_cap *cap)
5587 uint16_t vmcs_version;
5588 void __user *user_ptr;
5594 case KVM_CAP_HYPERV_SYNIC2:
5599 case KVM_CAP_HYPERV_SYNIC:
5600 if (!irqchip_in_kernel(vcpu->kvm))
5602 return kvm_hv_activate_synic(vcpu, cap->cap ==
5603 KVM_CAP_HYPERV_SYNIC2);
5604 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5605 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5607 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5609 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5610 if (copy_to_user(user_ptr, &vmcs_version,
5611 sizeof(vmcs_version)))
5615 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5616 if (!kvm_x86_ops.enable_l2_tlb_flush)
5619 return static_call(kvm_x86_enable_l2_tlb_flush)(vcpu);
5621 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5622 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5624 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5625 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5626 if (vcpu->arch.pv_cpuid.enforce)
5627 kvm_update_pv_runtime(vcpu);
5635 long kvm_arch_vcpu_ioctl(struct file *filp,
5636 unsigned int ioctl, unsigned long arg)
5638 struct kvm_vcpu *vcpu = filp->private_data;
5639 void __user *argp = (void __user *)arg;
5642 struct kvm_sregs2 *sregs2;
5643 struct kvm_lapic_state *lapic;
5644 struct kvm_xsave *xsave;
5645 struct kvm_xcrs *xcrs;
5653 case KVM_GET_LAPIC: {
5655 if (!lapic_in_kernel(vcpu))
5657 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5658 GFP_KERNEL_ACCOUNT);
5663 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5667 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5672 case KVM_SET_LAPIC: {
5674 if (!lapic_in_kernel(vcpu))
5676 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5677 if (IS_ERR(u.lapic)) {
5678 r = PTR_ERR(u.lapic);
5682 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5685 case KVM_INTERRUPT: {
5686 struct kvm_interrupt irq;
5689 if (copy_from_user(&irq, argp, sizeof(irq)))
5691 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5695 r = kvm_vcpu_ioctl_nmi(vcpu);
5699 r = kvm_inject_smi(vcpu);
5702 case KVM_SET_CPUID: {
5703 struct kvm_cpuid __user *cpuid_arg = argp;
5704 struct kvm_cpuid cpuid;
5707 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5709 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5712 case KVM_SET_CPUID2: {
5713 struct kvm_cpuid2 __user *cpuid_arg = argp;
5714 struct kvm_cpuid2 cpuid;
5717 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5719 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5720 cpuid_arg->entries);
5723 case KVM_GET_CPUID2: {
5724 struct kvm_cpuid2 __user *cpuid_arg = argp;
5725 struct kvm_cpuid2 cpuid;
5728 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5730 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5731 cpuid_arg->entries);
5735 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5740 case KVM_GET_MSRS: {
5741 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5742 r = msr_io(vcpu, argp, do_get_msr, 1);
5743 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5746 case KVM_SET_MSRS: {
5747 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5748 r = msr_io(vcpu, argp, do_set_msr, 0);
5749 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5752 case KVM_TPR_ACCESS_REPORTING: {
5753 struct kvm_tpr_access_ctl tac;
5756 if (copy_from_user(&tac, argp, sizeof(tac)))
5758 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5762 if (copy_to_user(argp, &tac, sizeof(tac)))
5767 case KVM_SET_VAPIC_ADDR: {
5768 struct kvm_vapic_addr va;
5772 if (!lapic_in_kernel(vcpu))
5775 if (copy_from_user(&va, argp, sizeof(va)))
5777 idx = srcu_read_lock(&vcpu->kvm->srcu);
5778 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5779 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5782 case KVM_X86_SETUP_MCE: {
5786 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5788 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5791 case KVM_X86_SET_MCE: {
5792 struct kvm_x86_mce mce;
5795 if (copy_from_user(&mce, argp, sizeof(mce)))
5797 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5800 case KVM_GET_VCPU_EVENTS: {
5801 struct kvm_vcpu_events events;
5803 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5806 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5811 case KVM_SET_VCPU_EVENTS: {
5812 struct kvm_vcpu_events events;
5815 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5818 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5821 case KVM_GET_DEBUGREGS: {
5822 struct kvm_debugregs dbgregs;
5824 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5827 if (copy_to_user(argp, &dbgregs,
5828 sizeof(struct kvm_debugregs)))
5833 case KVM_SET_DEBUGREGS: {
5834 struct kvm_debugregs dbgregs;
5837 if (copy_from_user(&dbgregs, argp,
5838 sizeof(struct kvm_debugregs)))
5841 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5844 case KVM_GET_XSAVE: {
5846 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5849 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5854 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5857 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5862 case KVM_SET_XSAVE: {
5863 int size = vcpu->arch.guest_fpu.uabi_size;
5865 u.xsave = memdup_user(argp, size);
5866 if (IS_ERR(u.xsave)) {
5867 r = PTR_ERR(u.xsave);
5871 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5875 case KVM_GET_XSAVE2: {
5876 int size = vcpu->arch.guest_fpu.uabi_size;
5878 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5883 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5886 if (copy_to_user(argp, u.xsave, size))
5893 case KVM_GET_XCRS: {
5894 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5899 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5902 if (copy_to_user(argp, u.xcrs,
5903 sizeof(struct kvm_xcrs)))
5908 case KVM_SET_XCRS: {
5909 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5910 if (IS_ERR(u.xcrs)) {
5911 r = PTR_ERR(u.xcrs);
5915 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5918 case KVM_SET_TSC_KHZ: {
5922 user_tsc_khz = (u32)arg;
5924 if (kvm_caps.has_tsc_control &&
5925 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
5928 if (user_tsc_khz == 0)
5929 user_tsc_khz = tsc_khz;
5931 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5936 case KVM_GET_TSC_KHZ: {
5937 r = vcpu->arch.virtual_tsc_khz;
5940 case KVM_KVMCLOCK_CTRL: {
5941 r = kvm_set_guest_paused(vcpu);
5944 case KVM_ENABLE_CAP: {
5945 struct kvm_enable_cap cap;
5948 if (copy_from_user(&cap, argp, sizeof(cap)))
5950 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5953 case KVM_GET_NESTED_STATE: {
5954 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5958 if (!kvm_x86_ops.nested_ops->get_state)
5961 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5963 if (get_user(user_data_size, &user_kvm_nested_state->size))
5966 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5971 if (r > user_data_size) {
5972 if (put_user(r, &user_kvm_nested_state->size))
5982 case KVM_SET_NESTED_STATE: {
5983 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5984 struct kvm_nested_state kvm_state;
5988 if (!kvm_x86_ops.nested_ops->set_state)
5992 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5996 if (kvm_state.size < sizeof(kvm_state))
5999 if (kvm_state.flags &
6000 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
6001 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
6002 | KVM_STATE_NESTED_GIF_SET))
6005 /* nested_run_pending implies guest_mode. */
6006 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
6007 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
6010 idx = srcu_read_lock(&vcpu->kvm->srcu);
6011 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
6012 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6015 case KVM_GET_SUPPORTED_HV_CPUID:
6016 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
6018 #ifdef CONFIG_KVM_XEN
6019 case KVM_XEN_VCPU_GET_ATTR: {
6020 struct kvm_xen_vcpu_attr xva;
6023 if (copy_from_user(&xva, argp, sizeof(xva)))
6025 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
6026 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
6030 case KVM_XEN_VCPU_SET_ATTR: {
6031 struct kvm_xen_vcpu_attr xva;
6034 if (copy_from_user(&xva, argp, sizeof(xva)))
6036 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
6040 case KVM_GET_SREGS2: {
6041 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
6045 __get_sregs2(vcpu, u.sregs2);
6047 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
6052 case KVM_SET_SREGS2: {
6053 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
6054 if (IS_ERR(u.sregs2)) {
6055 r = PTR_ERR(u.sregs2);
6059 r = __set_sregs2(vcpu, u.sregs2);
6062 case KVM_HAS_DEVICE_ATTR:
6063 case KVM_GET_DEVICE_ATTR:
6064 case KVM_SET_DEVICE_ATTR:
6065 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
6077 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
6079 return VM_FAULT_SIGBUS;
6082 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
6086 if (addr > (unsigned int)(-3 * PAGE_SIZE))
6088 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
6092 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
6095 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
6098 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
6099 unsigned long kvm_nr_mmu_pages)
6101 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
6104 mutex_lock(&kvm->slots_lock);
6106 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
6107 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
6109 mutex_unlock(&kvm->slots_lock);
6113 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6115 struct kvm_pic *pic = kvm->arch.vpic;
6119 switch (chip->chip_id) {
6120 case KVM_IRQCHIP_PIC_MASTER:
6121 memcpy(&chip->chip.pic, &pic->pics[0],
6122 sizeof(struct kvm_pic_state));
6124 case KVM_IRQCHIP_PIC_SLAVE:
6125 memcpy(&chip->chip.pic, &pic->pics[1],
6126 sizeof(struct kvm_pic_state));
6128 case KVM_IRQCHIP_IOAPIC:
6129 kvm_get_ioapic(kvm, &chip->chip.ioapic);
6138 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6140 struct kvm_pic *pic = kvm->arch.vpic;
6144 switch (chip->chip_id) {
6145 case KVM_IRQCHIP_PIC_MASTER:
6146 spin_lock(&pic->lock);
6147 memcpy(&pic->pics[0], &chip->chip.pic,
6148 sizeof(struct kvm_pic_state));
6149 spin_unlock(&pic->lock);
6151 case KVM_IRQCHIP_PIC_SLAVE:
6152 spin_lock(&pic->lock);
6153 memcpy(&pic->pics[1], &chip->chip.pic,
6154 sizeof(struct kvm_pic_state));
6155 spin_unlock(&pic->lock);
6157 case KVM_IRQCHIP_IOAPIC:
6158 kvm_set_ioapic(kvm, &chip->chip.ioapic);
6164 kvm_pic_update_irq(pic);
6168 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6170 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
6172 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
6174 mutex_lock(&kps->lock);
6175 memcpy(ps, &kps->channels, sizeof(*ps));
6176 mutex_unlock(&kps->lock);
6180 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6183 struct kvm_pit *pit = kvm->arch.vpit;
6185 mutex_lock(&pit->pit_state.lock);
6186 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
6187 for (i = 0; i < 3; i++)
6188 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
6189 mutex_unlock(&pit->pit_state.lock);
6193 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6195 mutex_lock(&kvm->arch.vpit->pit_state.lock);
6196 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
6197 sizeof(ps->channels));
6198 ps->flags = kvm->arch.vpit->pit_state.flags;
6199 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
6200 memset(&ps->reserved, 0, sizeof(ps->reserved));
6204 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6208 u32 prev_legacy, cur_legacy;
6209 struct kvm_pit *pit = kvm->arch.vpit;
6211 mutex_lock(&pit->pit_state.lock);
6212 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
6213 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
6214 if (!prev_legacy && cur_legacy)
6216 memcpy(&pit->pit_state.channels, &ps->channels,
6217 sizeof(pit->pit_state.channels));
6218 pit->pit_state.flags = ps->flags;
6219 for (i = 0; i < 3; i++)
6220 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
6222 mutex_unlock(&pit->pit_state.lock);
6226 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
6227 struct kvm_reinject_control *control)
6229 struct kvm_pit *pit = kvm->arch.vpit;
6231 /* pit->pit_state.lock was overloaded to prevent userspace from getting
6232 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
6233 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
6235 mutex_lock(&pit->pit_state.lock);
6236 kvm_pit_set_reinject(pit, control->pit_reinject);
6237 mutex_unlock(&pit->pit_state.lock);
6242 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
6246 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
6247 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
6248 * on all VM-Exits, thus we only need to kick running vCPUs to force a
6251 struct kvm_vcpu *vcpu;
6254 kvm_for_each_vcpu(i, vcpu, kvm)
6255 kvm_vcpu_kick(vcpu);
6258 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
6261 if (!irqchip_in_kernel(kvm))
6264 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
6265 irq_event->irq, irq_event->level,
6270 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
6271 struct kvm_enable_cap *cap)
6279 case KVM_CAP_DISABLE_QUIRKS2:
6281 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
6284 case KVM_CAP_DISABLE_QUIRKS:
6285 kvm->arch.disabled_quirks = cap->args[0];
6288 case KVM_CAP_SPLIT_IRQCHIP: {
6289 mutex_lock(&kvm->lock);
6291 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
6292 goto split_irqchip_unlock;
6294 if (irqchip_in_kernel(kvm))
6295 goto split_irqchip_unlock;
6296 if (kvm->created_vcpus)
6297 goto split_irqchip_unlock;
6298 r = kvm_setup_empty_irq_routing(kvm);
6300 goto split_irqchip_unlock;
6301 /* Pairs with irqchip_in_kernel. */
6303 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
6304 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
6305 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6307 split_irqchip_unlock:
6308 mutex_unlock(&kvm->lock);
6311 case KVM_CAP_X2APIC_API:
6313 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
6316 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
6317 kvm->arch.x2apic_format = true;
6318 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
6319 kvm->arch.x2apic_broadcast_quirk_disabled = true;
6323 case KVM_CAP_X86_DISABLE_EXITS:
6325 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
6328 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
6329 kvm->arch.pause_in_guest = true;
6331 #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \
6332 "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests."
6334 if (!mitigate_smt_rsb) {
6335 if (boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible() &&
6336 (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE))
6337 pr_warn_once(SMT_RSB_MSG);
6339 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
6340 kvm_can_mwait_in_guest())
6341 kvm->arch.mwait_in_guest = true;
6342 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
6343 kvm->arch.hlt_in_guest = true;
6344 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
6345 kvm->arch.cstate_in_guest = true;
6350 case KVM_CAP_MSR_PLATFORM_INFO:
6351 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
6354 case KVM_CAP_EXCEPTION_PAYLOAD:
6355 kvm->arch.exception_payload_enabled = cap->args[0];
6358 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
6359 kvm->arch.triple_fault_event = cap->args[0];
6362 case KVM_CAP_X86_USER_SPACE_MSR:
6364 if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK)
6366 kvm->arch.user_space_msr_mask = cap->args[0];
6369 case KVM_CAP_X86_BUS_LOCK_EXIT:
6371 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6374 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6375 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6378 if (kvm_caps.has_bus_lock_exit &&
6379 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6380 kvm->arch.bus_lock_detection_enabled = true;
6383 #ifdef CONFIG_X86_SGX_KVM
6384 case KVM_CAP_SGX_ATTRIBUTE: {
6385 unsigned long allowed_attributes = 0;
6387 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6391 /* KVM only supports the PROVISIONKEY privileged attribute. */
6392 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6393 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6394 kvm->arch.sgx_provisioning_allowed = true;
6400 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6402 if (!kvm_x86_ops.vm_copy_enc_context_from)
6405 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6407 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6409 if (!kvm_x86_ops.vm_move_enc_context_from)
6412 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6414 case KVM_CAP_EXIT_HYPERCALL:
6415 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6419 kvm->arch.hypercall_exit_enabled = cap->args[0];
6422 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6424 if (cap->args[0] & ~1)
6426 kvm->arch.exit_on_emulation_error = cap->args[0];
6429 case KVM_CAP_PMU_CAPABILITY:
6431 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6434 mutex_lock(&kvm->lock);
6435 if (!kvm->created_vcpus) {
6436 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6439 mutex_unlock(&kvm->lock);
6441 case KVM_CAP_MAX_VCPU_ID:
6443 if (cap->args[0] > KVM_MAX_VCPU_IDS)
6446 mutex_lock(&kvm->lock);
6447 if (kvm->arch.max_vcpu_ids == cap->args[0]) {
6449 } else if (!kvm->arch.max_vcpu_ids) {
6450 kvm->arch.max_vcpu_ids = cap->args[0];
6453 mutex_unlock(&kvm->lock);
6455 case KVM_CAP_X86_NOTIFY_VMEXIT:
6457 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
6459 if (!kvm_caps.has_notify_vmexit)
6461 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
6463 mutex_lock(&kvm->lock);
6464 if (!kvm->created_vcpus) {
6465 kvm->arch.notify_window = cap->args[0] >> 32;
6466 kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
6469 mutex_unlock(&kvm->lock);
6471 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
6475 * Since the risk of disabling NX hugepages is a guest crashing
6476 * the system, ensure the userspace process has permission to
6477 * reboot the system.
6479 * Note that unlike the reboot() syscall, the process must have
6480 * this capability in the root namespace because exposing
6481 * /dev/kvm into a container does not limit the scope of the
6482 * iTLB multihit bug to that container. In other words,
6483 * this must use capable(), not ns_capable().
6485 if (!capable(CAP_SYS_BOOT)) {
6493 mutex_lock(&kvm->lock);
6494 if (!kvm->created_vcpus) {
6495 kvm->arch.disable_nx_huge_pages = true;
6498 mutex_unlock(&kvm->lock);
6507 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6509 struct kvm_x86_msr_filter *msr_filter;
6511 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6515 msr_filter->default_allow = default_allow;
6519 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6526 for (i = 0; i < msr_filter->count; i++)
6527 kfree(msr_filter->ranges[i].bitmap);
6532 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6533 struct kvm_msr_filter_range *user_range)
6535 unsigned long *bitmap = NULL;
6538 if (!user_range->nmsrs)
6541 if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK)
6544 if (!user_range->flags)
6547 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6548 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6551 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6553 return PTR_ERR(bitmap);
6555 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6556 .flags = user_range->flags,
6557 .base = user_range->base,
6558 .nmsrs = user_range->nmsrs,
6562 msr_filter->count++;
6566 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm,
6567 struct kvm_msr_filter *filter)
6569 struct kvm_x86_msr_filter *new_filter, *old_filter;
6575 if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK)
6578 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++)
6579 empty &= !filter->ranges[i].nmsrs;
6581 default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY);
6582 if (empty && !default_allow)
6585 new_filter = kvm_alloc_msr_filter(default_allow);
6589 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) {
6590 r = kvm_add_msr_filter(new_filter, &filter->ranges[i]);
6592 kvm_free_msr_filter(new_filter);
6597 mutex_lock(&kvm->lock);
6598 old_filter = rcu_replace_pointer(kvm->arch.msr_filter, new_filter,
6599 mutex_is_locked(&kvm->lock));
6600 mutex_unlock(&kvm->lock);
6601 synchronize_srcu(&kvm->srcu);
6603 kvm_free_msr_filter(old_filter);
6605 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6610 #ifdef CONFIG_KVM_COMPAT
6611 /* for KVM_X86_SET_MSR_FILTER */
6612 struct kvm_msr_filter_range_compat {
6619 struct kvm_msr_filter_compat {
6621 struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES];
6624 #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat)
6626 long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl,
6629 void __user *argp = (void __user *)arg;
6630 struct kvm *kvm = filp->private_data;
6634 case KVM_X86_SET_MSR_FILTER_COMPAT: {
6635 struct kvm_msr_filter __user *user_msr_filter = argp;
6636 struct kvm_msr_filter_compat filter_compat;
6637 struct kvm_msr_filter filter;
6640 if (copy_from_user(&filter_compat, user_msr_filter,
6641 sizeof(filter_compat)))
6644 filter.flags = filter_compat.flags;
6645 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6646 struct kvm_msr_filter_range_compat *cr;
6648 cr = &filter_compat.ranges[i];
6649 filter.ranges[i] = (struct kvm_msr_filter_range) {
6653 .bitmap = (__u8 *)(ulong)cr->bitmap,
6657 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
6666 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6667 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6669 struct kvm_vcpu *vcpu;
6673 mutex_lock(&kvm->lock);
6674 kvm_for_each_vcpu(i, vcpu, kvm) {
6675 if (!vcpu->arch.pv_time.active)
6678 ret = kvm_set_guest_paused(vcpu);
6680 kvm_err("Failed to pause guest VCPU%d: %d\n",
6681 vcpu->vcpu_id, ret);
6685 mutex_unlock(&kvm->lock);
6687 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6690 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6693 case PM_HIBERNATION_PREPARE:
6694 case PM_SUSPEND_PREPARE:
6695 return kvm_arch_suspend_notifier(kvm);
6700 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6702 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6704 struct kvm_clock_data data = { 0 };
6706 get_kvmclock(kvm, &data);
6707 if (copy_to_user(argp, &data, sizeof(data)))
6713 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6715 struct kvm_arch *ka = &kvm->arch;
6716 struct kvm_clock_data data;
6719 if (copy_from_user(&data, argp, sizeof(data)))
6723 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6724 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6726 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6729 kvm_hv_request_tsc_page_update(kvm);
6730 kvm_start_pvclock_update(kvm);
6731 pvclock_update_vm_gtod_copy(kvm);
6734 * This pairs with kvm_guest_time_update(): when masterclock is
6735 * in use, we use master_kernel_ns + kvmclock_offset to set
6736 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6737 * is slightly ahead) here we risk going negative on unsigned
6738 * 'system_time' when 'data.clock' is very small.
6740 if (data.flags & KVM_CLOCK_REALTIME) {
6741 u64 now_real_ns = ktime_get_real_ns();
6744 * Avoid stepping the kvmclock backwards.
6746 if (now_real_ns > data.realtime)
6747 data.clock += now_real_ns - data.realtime;
6750 if (ka->use_master_clock)
6751 now_raw_ns = ka->master_kernel_ns;
6753 now_raw_ns = get_kvmclock_base_ns();
6754 ka->kvmclock_offset = data.clock - now_raw_ns;
6755 kvm_end_pvclock_update(kvm);
6759 int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
6761 struct kvm *kvm = filp->private_data;
6762 void __user *argp = (void __user *)arg;
6765 * This union makes it completely explicit to gcc-3.x
6766 * that these two variables' stack usage should be
6767 * combined, not added together.
6770 struct kvm_pit_state ps;
6771 struct kvm_pit_state2 ps2;
6772 struct kvm_pit_config pit_config;
6776 case KVM_SET_TSS_ADDR:
6777 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6779 case KVM_SET_IDENTITY_MAP_ADDR: {
6782 mutex_lock(&kvm->lock);
6784 if (kvm->created_vcpus)
6785 goto set_identity_unlock;
6787 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6788 goto set_identity_unlock;
6789 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6790 set_identity_unlock:
6791 mutex_unlock(&kvm->lock);
6794 case KVM_SET_NR_MMU_PAGES:
6795 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6797 case KVM_CREATE_IRQCHIP: {
6798 mutex_lock(&kvm->lock);
6801 if (irqchip_in_kernel(kvm))
6802 goto create_irqchip_unlock;
6805 if (kvm->created_vcpus)
6806 goto create_irqchip_unlock;
6808 r = kvm_pic_init(kvm);
6810 goto create_irqchip_unlock;
6812 r = kvm_ioapic_init(kvm);
6814 kvm_pic_destroy(kvm);
6815 goto create_irqchip_unlock;
6818 r = kvm_setup_default_irq_routing(kvm);
6820 kvm_ioapic_destroy(kvm);
6821 kvm_pic_destroy(kvm);
6822 goto create_irqchip_unlock;
6824 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6826 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6827 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6828 create_irqchip_unlock:
6829 mutex_unlock(&kvm->lock);
6832 case KVM_CREATE_PIT:
6833 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6835 case KVM_CREATE_PIT2:
6837 if (copy_from_user(&u.pit_config, argp,
6838 sizeof(struct kvm_pit_config)))
6841 mutex_lock(&kvm->lock);
6844 goto create_pit_unlock;
6846 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6850 mutex_unlock(&kvm->lock);
6852 case KVM_GET_IRQCHIP: {
6853 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6854 struct kvm_irqchip *chip;
6856 chip = memdup_user(argp, sizeof(*chip));
6863 if (!irqchip_kernel(kvm))
6864 goto get_irqchip_out;
6865 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6867 goto get_irqchip_out;
6869 if (copy_to_user(argp, chip, sizeof(*chip)))
6870 goto get_irqchip_out;
6876 case KVM_SET_IRQCHIP: {
6877 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6878 struct kvm_irqchip *chip;
6880 chip = memdup_user(argp, sizeof(*chip));
6887 if (!irqchip_kernel(kvm))
6888 goto set_irqchip_out;
6889 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6896 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6899 if (!kvm->arch.vpit)
6901 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6905 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6912 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6914 mutex_lock(&kvm->lock);
6916 if (!kvm->arch.vpit)
6918 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6920 mutex_unlock(&kvm->lock);
6923 case KVM_GET_PIT2: {
6925 if (!kvm->arch.vpit)
6927 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6931 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6936 case KVM_SET_PIT2: {
6938 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6940 mutex_lock(&kvm->lock);
6942 if (!kvm->arch.vpit)
6944 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6946 mutex_unlock(&kvm->lock);
6949 case KVM_REINJECT_CONTROL: {
6950 struct kvm_reinject_control control;
6952 if (copy_from_user(&control, argp, sizeof(control)))
6955 if (!kvm->arch.vpit)
6957 r = kvm_vm_ioctl_reinject(kvm, &control);
6960 case KVM_SET_BOOT_CPU_ID:
6962 mutex_lock(&kvm->lock);
6963 if (kvm->created_vcpus)
6966 kvm->arch.bsp_vcpu_id = arg;
6967 mutex_unlock(&kvm->lock);
6969 #ifdef CONFIG_KVM_XEN
6970 case KVM_XEN_HVM_CONFIG: {
6971 struct kvm_xen_hvm_config xhc;
6973 if (copy_from_user(&xhc, argp, sizeof(xhc)))
6975 r = kvm_xen_hvm_config(kvm, &xhc);
6978 case KVM_XEN_HVM_GET_ATTR: {
6979 struct kvm_xen_hvm_attr xha;
6982 if (copy_from_user(&xha, argp, sizeof(xha)))
6984 r = kvm_xen_hvm_get_attr(kvm, &xha);
6985 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
6989 case KVM_XEN_HVM_SET_ATTR: {
6990 struct kvm_xen_hvm_attr xha;
6993 if (copy_from_user(&xha, argp, sizeof(xha)))
6995 r = kvm_xen_hvm_set_attr(kvm, &xha);
6998 case KVM_XEN_HVM_EVTCHN_SEND: {
6999 struct kvm_irq_routing_xen_evtchn uxe;
7002 if (copy_from_user(&uxe, argp, sizeof(uxe)))
7004 r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
7009 r = kvm_vm_ioctl_set_clock(kvm, argp);
7012 r = kvm_vm_ioctl_get_clock(kvm, argp);
7014 case KVM_SET_TSC_KHZ: {
7018 user_tsc_khz = (u32)arg;
7020 if (kvm_caps.has_tsc_control &&
7021 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
7024 if (user_tsc_khz == 0)
7025 user_tsc_khz = tsc_khz;
7027 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
7032 case KVM_GET_TSC_KHZ: {
7033 r = READ_ONCE(kvm->arch.default_tsc_khz);
7036 case KVM_MEMORY_ENCRYPT_OP: {
7038 if (!kvm_x86_ops.mem_enc_ioctl)
7041 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
7044 case KVM_MEMORY_ENCRYPT_REG_REGION: {
7045 struct kvm_enc_region region;
7048 if (copy_from_user(®ion, argp, sizeof(region)))
7052 if (!kvm_x86_ops.mem_enc_register_region)
7055 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
7058 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
7059 struct kvm_enc_region region;
7062 if (copy_from_user(®ion, argp, sizeof(region)))
7066 if (!kvm_x86_ops.mem_enc_unregister_region)
7069 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
7072 case KVM_HYPERV_EVENTFD: {
7073 struct kvm_hyperv_eventfd hvevfd;
7076 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
7078 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
7081 case KVM_SET_PMU_EVENT_FILTER:
7082 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
7084 case KVM_X86_SET_MSR_FILTER: {
7085 struct kvm_msr_filter __user *user_msr_filter = argp;
7086 struct kvm_msr_filter filter;
7088 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
7091 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
7101 static void kvm_probe_feature_msr(u32 msr_index)
7103 struct kvm_msr_entry msr = {
7107 if (kvm_get_msr_feature(&msr))
7110 msr_based_features[num_msr_based_features++] = msr_index;
7113 static void kvm_probe_msr_to_save(u32 msr_index)
7117 if (rdmsr_safe(msr_index, &dummy[0], &dummy[1]))
7121 * Even MSRs that are valid in the host may not be exposed to guests in
7124 switch (msr_index) {
7125 case MSR_IA32_BNDCFGS:
7126 if (!kvm_mpx_supported())
7130 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
7131 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
7134 case MSR_IA32_UMWAIT_CONTROL:
7135 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
7138 case MSR_IA32_RTIT_CTL:
7139 case MSR_IA32_RTIT_STATUS:
7140 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
7143 case MSR_IA32_RTIT_CR3_MATCH:
7144 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7145 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
7148 case MSR_IA32_RTIT_OUTPUT_BASE:
7149 case MSR_IA32_RTIT_OUTPUT_MASK:
7150 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7151 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
7152 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
7155 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
7156 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7157 (msr_index - MSR_IA32_RTIT_ADDR0_A >=
7158 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2))
7161 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
7162 if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >=
7163 kvm_pmu_cap.num_counters_gp)
7166 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
7167 if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >=
7168 kvm_pmu_cap.num_counters_gp)
7171 case MSR_ARCH_PERFMON_FIXED_CTR0 ... MSR_ARCH_PERFMON_FIXED_CTR_MAX:
7172 if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >=
7173 kvm_pmu_cap.num_counters_fixed)
7176 case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
7177 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
7178 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
7179 if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2))
7183 case MSR_IA32_XFD_ERR:
7184 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
7187 case MSR_IA32_TSX_CTRL:
7188 if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR))
7195 msrs_to_save[num_msrs_to_save++] = msr_index;
7198 static void kvm_init_msr_lists(void)
7202 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
7203 "Please update the fixed PMCs in msrs_to_save_pmu[]");
7205 num_msrs_to_save = 0;
7206 num_emulated_msrs = 0;
7207 num_msr_based_features = 0;
7209 for (i = 0; i < ARRAY_SIZE(msrs_to_save_base); i++)
7210 kvm_probe_msr_to_save(msrs_to_save_base[i]);
7213 for (i = 0; i < ARRAY_SIZE(msrs_to_save_pmu); i++)
7214 kvm_probe_msr_to_save(msrs_to_save_pmu[i]);
7217 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
7218 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
7221 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
7224 for (i = KVM_FIRST_EMULATED_VMX_MSR; i <= KVM_LAST_EMULATED_VMX_MSR; i++)
7225 kvm_probe_feature_msr(i);
7227 for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++)
7228 kvm_probe_feature_msr(msr_based_features_all_except_vmx[i]);
7231 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
7239 if (!(lapic_in_kernel(vcpu) &&
7240 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
7241 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
7252 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
7259 if (!(lapic_in_kernel(vcpu) &&
7260 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
7262 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
7264 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
7274 void kvm_set_segment(struct kvm_vcpu *vcpu,
7275 struct kvm_segment *var, int seg)
7277 static_call(kvm_x86_set_segment)(vcpu, var, seg);
7280 void kvm_get_segment(struct kvm_vcpu *vcpu,
7281 struct kvm_segment *var, int seg)
7283 static_call(kvm_x86_get_segment)(vcpu, var, seg);
7286 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
7287 struct x86_exception *exception)
7289 struct kvm_mmu *mmu = vcpu->arch.mmu;
7292 BUG_ON(!mmu_is_nested(vcpu));
7294 /* NPT walks are always user-walks */
7295 access |= PFERR_USER_MASK;
7296 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
7301 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
7302 struct x86_exception *exception)
7304 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7306 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7307 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7309 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
7311 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
7312 struct x86_exception *exception)
7314 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7316 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7317 access |= PFERR_WRITE_MASK;
7318 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7320 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
7322 /* uses this to access any guest's mapped memory without checking CPL */
7323 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
7324 struct x86_exception *exception)
7326 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7328 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
7331 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7332 struct kvm_vcpu *vcpu, u64 access,
7333 struct x86_exception *exception)
7335 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7337 int r = X86EMUL_CONTINUE;
7340 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7341 unsigned offset = addr & (PAGE_SIZE-1);
7342 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
7345 if (gpa == INVALID_GPA)
7346 return X86EMUL_PROPAGATE_FAULT;
7347 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
7350 r = X86EMUL_IO_NEEDED;
7362 /* used for instruction fetching */
7363 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
7364 gva_t addr, void *val, unsigned int bytes,
7365 struct x86_exception *exception)
7367 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7368 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7369 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7373 /* Inline kvm_read_guest_virt_helper for speed. */
7374 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
7376 if (unlikely(gpa == INVALID_GPA))
7377 return X86EMUL_PROPAGATE_FAULT;
7379 offset = addr & (PAGE_SIZE-1);
7380 if (WARN_ON(offset + bytes > PAGE_SIZE))
7381 bytes = (unsigned)PAGE_SIZE - offset;
7382 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
7384 if (unlikely(ret < 0))
7385 return X86EMUL_IO_NEEDED;
7387 return X86EMUL_CONTINUE;
7390 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
7391 gva_t addr, void *val, unsigned int bytes,
7392 struct x86_exception *exception)
7394 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7397 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
7398 * is returned, but our callers are not ready for that and they blindly
7399 * call kvm_inject_page_fault. Ensure that they at least do not leak
7400 * uninitialized kernel stack memory into cr2 and error code.
7402 memset(exception, 0, sizeof(*exception));
7403 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
7406 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
7408 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
7409 gva_t addr, void *val, unsigned int bytes,
7410 struct x86_exception *exception, bool system)
7412 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7416 access |= PFERR_IMPLICIT_ACCESS;
7417 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7418 access |= PFERR_USER_MASK;
7420 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
7423 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7424 struct kvm_vcpu *vcpu, u64 access,
7425 struct x86_exception *exception)
7427 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7429 int r = X86EMUL_CONTINUE;
7432 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7433 unsigned offset = addr & (PAGE_SIZE-1);
7434 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
7437 if (gpa == INVALID_GPA)
7438 return X86EMUL_PROPAGATE_FAULT;
7439 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
7441 r = X86EMUL_IO_NEEDED;
7453 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
7454 unsigned int bytes, struct x86_exception *exception,
7457 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7458 u64 access = PFERR_WRITE_MASK;
7461 access |= PFERR_IMPLICIT_ACCESS;
7462 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7463 access |= PFERR_USER_MASK;
7465 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7469 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
7470 unsigned int bytes, struct x86_exception *exception)
7472 /* kvm_write_guest_virt_system can pull in tons of pages. */
7473 vcpu->arch.l1tf_flush_l1d = true;
7475 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7476 PFERR_WRITE_MASK, exception);
7478 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
7480 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
7481 void *insn, int insn_len)
7483 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
7487 int handle_ud(struct kvm_vcpu *vcpu)
7489 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
7490 int fep_flags = READ_ONCE(force_emulation_prefix);
7491 int emul_type = EMULTYPE_TRAP_UD;
7492 char sig[5]; /* ud2; .ascii "kvm" */
7493 struct x86_exception e;
7495 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
7499 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
7500 sig, sizeof(sig), &e) == 0 &&
7501 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
7502 if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF)
7503 kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF);
7504 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
7505 emul_type = EMULTYPE_TRAP_UD_FORCED;
7508 return kvm_emulate_instruction(vcpu, emul_type);
7510 EXPORT_SYMBOL_GPL(handle_ud);
7512 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7513 gpa_t gpa, bool write)
7515 /* For APIC access vmexit */
7516 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7519 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7520 trace_vcpu_match_mmio(gva, gpa, write, true);
7527 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7528 gpa_t *gpa, struct x86_exception *exception,
7531 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7532 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7533 | (write ? PFERR_WRITE_MASK : 0);
7536 * currently PKRU is only applied to ept enabled guest so
7537 * there is no pkey in EPT page table for L1 guest or EPT
7538 * shadow page table for L2 guest.
7540 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7541 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7542 vcpu->arch.mmio_access, 0, access))) {
7543 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7544 (gva & (PAGE_SIZE - 1));
7545 trace_vcpu_match_mmio(gva, *gpa, write, false);
7549 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7551 if (*gpa == INVALID_GPA)
7554 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7557 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7558 const void *val, int bytes)
7562 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7565 kvm_page_track_write(vcpu, gpa, val, bytes);
7569 struct read_write_emulator_ops {
7570 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7572 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7573 void *val, int bytes);
7574 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7575 int bytes, void *val);
7576 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7577 void *val, int bytes);
7581 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7583 if (vcpu->mmio_read_completed) {
7584 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7585 vcpu->mmio_fragments[0].gpa, val);
7586 vcpu->mmio_read_completed = 0;
7593 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7594 void *val, int bytes)
7596 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7599 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7600 void *val, int bytes)
7602 return emulator_write_phys(vcpu, gpa, val, bytes);
7605 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7607 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7608 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7611 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7612 void *val, int bytes)
7614 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7615 return X86EMUL_IO_NEEDED;
7618 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7619 void *val, int bytes)
7621 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7623 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7624 return X86EMUL_CONTINUE;
7627 static const struct read_write_emulator_ops read_emultor = {
7628 .read_write_prepare = read_prepare,
7629 .read_write_emulate = read_emulate,
7630 .read_write_mmio = vcpu_mmio_read,
7631 .read_write_exit_mmio = read_exit_mmio,
7634 static const struct read_write_emulator_ops write_emultor = {
7635 .read_write_emulate = write_emulate,
7636 .read_write_mmio = write_mmio,
7637 .read_write_exit_mmio = write_exit_mmio,
7641 static int emulator_read_write_onepage(unsigned long addr, void *val,
7643 struct x86_exception *exception,
7644 struct kvm_vcpu *vcpu,
7645 const struct read_write_emulator_ops *ops)
7649 bool write = ops->write;
7650 struct kvm_mmio_fragment *frag;
7651 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7654 * If the exit was due to a NPF we may already have a GPA.
7655 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7656 * Note, this cannot be used on string operations since string
7657 * operation using rep will only have the initial GPA from the NPF
7660 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7661 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7662 gpa = ctxt->gpa_val;
7663 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7665 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7667 return X86EMUL_PROPAGATE_FAULT;
7670 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7671 return X86EMUL_CONTINUE;
7674 * Is this MMIO handled locally?
7676 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7677 if (handled == bytes)
7678 return X86EMUL_CONTINUE;
7684 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7685 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7689 return X86EMUL_CONTINUE;
7692 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7694 void *val, unsigned int bytes,
7695 struct x86_exception *exception,
7696 const struct read_write_emulator_ops *ops)
7698 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7702 if (ops->read_write_prepare &&
7703 ops->read_write_prepare(vcpu, val, bytes))
7704 return X86EMUL_CONTINUE;
7706 vcpu->mmio_nr_fragments = 0;
7708 /* Crossing a page boundary? */
7709 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7712 now = -addr & ~PAGE_MASK;
7713 rc = emulator_read_write_onepage(addr, val, now, exception,
7716 if (rc != X86EMUL_CONTINUE)
7719 if (ctxt->mode != X86EMUL_MODE_PROT64)
7725 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7727 if (rc != X86EMUL_CONTINUE)
7730 if (!vcpu->mmio_nr_fragments)
7733 gpa = vcpu->mmio_fragments[0].gpa;
7735 vcpu->mmio_needed = 1;
7736 vcpu->mmio_cur_fragment = 0;
7738 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7739 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7740 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7741 vcpu->run->mmio.phys_addr = gpa;
7743 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7746 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7750 struct x86_exception *exception)
7752 return emulator_read_write(ctxt, addr, val, bytes,
7753 exception, &read_emultor);
7756 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7760 struct x86_exception *exception)
7762 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7763 exception, &write_emultor);
7766 #define emulator_try_cmpxchg_user(t, ptr, old, new) \
7767 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t))
7769 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7774 struct x86_exception *exception)
7776 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7782 /* guests cmpxchg8b have to be emulated atomically */
7783 if (bytes > 8 || (bytes & (bytes - 1)))
7786 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7788 if (gpa == INVALID_GPA ||
7789 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7793 * Emulate the atomic as a straight write to avoid #AC if SLD is
7794 * enabled in the host and the access splits a cache line.
7796 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7797 page_line_mask = ~(cache_line_size() - 1);
7799 page_line_mask = PAGE_MASK;
7801 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7804 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa));
7805 if (kvm_is_error_hva(hva))
7808 hva += offset_in_page(gpa);
7812 r = emulator_try_cmpxchg_user(u8, hva, old, new);
7815 r = emulator_try_cmpxchg_user(u16, hva, old, new);
7818 r = emulator_try_cmpxchg_user(u32, hva, old, new);
7821 r = emulator_try_cmpxchg_user(u64, hva, old, new);
7828 return X86EMUL_UNHANDLEABLE;
7830 return X86EMUL_CMPXCHG_FAILED;
7832 kvm_page_track_write(vcpu, gpa, new, bytes);
7834 return X86EMUL_CONTINUE;
7837 pr_warn_once("emulating exchange as write\n");
7839 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7842 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7843 unsigned short port, void *data,
7844 unsigned int count, bool in)
7849 WARN_ON_ONCE(vcpu->arch.pio.count);
7850 for (i = 0; i < count; i++) {
7852 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data);
7854 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data);
7861 * Userspace must have unregistered the device while PIO
7862 * was running. Drop writes / read as 0.
7865 memset(data, 0, size * (count - i));
7874 vcpu->arch.pio.port = port;
7875 vcpu->arch.pio.in = in;
7876 vcpu->arch.pio.count = count;
7877 vcpu->arch.pio.size = size;
7880 memset(vcpu->arch.pio_data, 0, size * count);
7882 memcpy(vcpu->arch.pio_data, data, size * count);
7884 vcpu->run->exit_reason = KVM_EXIT_IO;
7885 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7886 vcpu->run->io.size = size;
7887 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7888 vcpu->run->io.count = count;
7889 vcpu->run->io.port = port;
7893 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7894 unsigned short port, void *val, unsigned int count)
7896 int r = emulator_pio_in_out(vcpu, size, port, val, count, true);
7898 trace_kvm_pio(KVM_PIO_IN, port, size, count, val);
7903 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7905 int size = vcpu->arch.pio.size;
7906 unsigned int count = vcpu->arch.pio.count;
7907 memcpy(val, vcpu->arch.pio_data, size * count);
7908 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7909 vcpu->arch.pio.count = 0;
7912 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7913 int size, unsigned short port, void *val,
7916 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7917 if (vcpu->arch.pio.count) {
7919 * Complete a previous iteration that required userspace I/O.
7920 * Note, @count isn't guaranteed to match pio.count as userspace
7921 * can modify ECX before rerunning the vCPU. Ignore any such
7922 * shenanigans as KVM doesn't support modifying the rep count,
7923 * and the emulator ensures @count doesn't overflow the buffer.
7925 complete_emulator_pio_in(vcpu, val);
7929 return emulator_pio_in(vcpu, size, port, val, count);
7932 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7933 unsigned short port, const void *val,
7936 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val);
7937 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
7940 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7941 int size, unsigned short port,
7942 const void *val, unsigned int count)
7944 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7947 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7949 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7952 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7954 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7957 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7959 if (!need_emulate_wbinvd(vcpu))
7960 return X86EMUL_CONTINUE;
7962 if (static_call(kvm_x86_has_wbinvd_exit)()) {
7963 int cpu = get_cpu();
7965 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7966 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7967 wbinvd_ipi, NULL, 1);
7969 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7972 return X86EMUL_CONTINUE;
7975 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
7977 kvm_emulate_wbinvd_noskip(vcpu);
7978 return kvm_skip_emulated_instruction(vcpu);
7980 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
7984 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
7986 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
7989 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
7990 unsigned long *dest)
7992 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
7995 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
7996 unsigned long value)
7999 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
8002 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
8004 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
8007 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
8009 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8010 unsigned long value;
8014 value = kvm_read_cr0(vcpu);
8017 value = vcpu->arch.cr2;
8020 value = kvm_read_cr3(vcpu);
8023 value = kvm_read_cr4(vcpu);
8026 value = kvm_get_cr8(vcpu);
8029 kvm_err("%s: unexpected cr %u\n", __func__, cr);
8036 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
8038 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8043 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
8046 vcpu->arch.cr2 = val;
8049 res = kvm_set_cr3(vcpu, val);
8052 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8055 res = kvm_set_cr8(vcpu, val);
8058 kvm_err("%s: unexpected cr %u\n", __func__, cr);
8065 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
8067 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
8070 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8072 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
8075 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8077 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
8080 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8082 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
8085 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8087 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
8090 static unsigned long emulator_get_cached_segment_base(
8091 struct x86_emulate_ctxt *ctxt, int seg)
8093 return get_segment_base(emul_to_vcpu(ctxt), seg);
8096 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
8097 struct desc_struct *desc, u32 *base3,
8100 struct kvm_segment var;
8102 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
8103 *selector = var.selector;
8106 memset(desc, 0, sizeof(*desc));
8114 set_desc_limit(desc, var.limit);
8115 set_desc_base(desc, (unsigned long)var.base);
8116 #ifdef CONFIG_X86_64
8118 *base3 = var.base >> 32;
8120 desc->type = var.type;
8122 desc->dpl = var.dpl;
8123 desc->p = var.present;
8124 desc->avl = var.avl;
8132 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
8133 struct desc_struct *desc, u32 base3,
8136 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8137 struct kvm_segment var;
8139 var.selector = selector;
8140 var.base = get_desc_base(desc);
8141 #ifdef CONFIG_X86_64
8142 var.base |= ((u64)base3) << 32;
8144 var.limit = get_desc_limit(desc);
8146 var.limit = (var.limit << 12) | 0xfff;
8147 var.type = desc->type;
8148 var.dpl = desc->dpl;
8153 var.avl = desc->avl;
8154 var.present = desc->p;
8155 var.unusable = !var.present;
8158 kvm_set_segment(vcpu, &var, seg);
8162 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8163 u32 msr_index, u64 *pdata)
8165 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8168 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
8170 return X86EMUL_UNHANDLEABLE;
8173 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
8174 complete_emulated_rdmsr, r))
8175 return X86EMUL_IO_NEEDED;
8177 trace_kvm_msr_read_ex(msr_index);
8178 return X86EMUL_PROPAGATE_FAULT;
8181 trace_kvm_msr_read(msr_index, *pdata);
8182 return X86EMUL_CONTINUE;
8185 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8186 u32 msr_index, u64 data)
8188 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8191 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
8193 return X86EMUL_UNHANDLEABLE;
8196 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
8197 complete_emulated_msr_access, r))
8198 return X86EMUL_IO_NEEDED;
8200 trace_kvm_msr_write_ex(msr_index, data);
8201 return X86EMUL_PROPAGATE_FAULT;
8204 trace_kvm_msr_write(msr_index, data);
8205 return X86EMUL_CONTINUE;
8208 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
8209 u32 msr_index, u64 *pdata)
8211 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
8214 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
8217 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
8222 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
8223 u32 pmc, u64 *pdata)
8225 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
8228 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
8230 emul_to_vcpu(ctxt)->arch.halt_request = 1;
8233 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8234 struct x86_instruction_info *info,
8235 enum x86_intercept_stage stage)
8237 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
8241 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
8242 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
8245 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
8248 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
8250 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
8253 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
8255 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
8258 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
8260 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
8263 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
8265 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
8268 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
8270 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
8273 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
8275 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
8278 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
8280 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
8283 static bool emulator_is_smm(struct x86_emulate_ctxt *ctxt)
8285 return is_smm(emul_to_vcpu(ctxt));
8288 static bool emulator_is_guest_mode(struct x86_emulate_ctxt *ctxt)
8290 return is_guest_mode(emul_to_vcpu(ctxt));
8293 #ifndef CONFIG_KVM_SMM
8294 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt)
8297 return X86EMUL_UNHANDLEABLE;
8301 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
8303 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
8306 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
8308 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
8311 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
8313 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
8315 if (!kvm->vm_bugged)
8319 static const struct x86_emulate_ops emulate_ops = {
8320 .vm_bugged = emulator_vm_bugged,
8321 .read_gpr = emulator_read_gpr,
8322 .write_gpr = emulator_write_gpr,
8323 .read_std = emulator_read_std,
8324 .write_std = emulator_write_std,
8325 .fetch = kvm_fetch_guest_virt,
8326 .read_emulated = emulator_read_emulated,
8327 .write_emulated = emulator_write_emulated,
8328 .cmpxchg_emulated = emulator_cmpxchg_emulated,
8329 .invlpg = emulator_invlpg,
8330 .pio_in_emulated = emulator_pio_in_emulated,
8331 .pio_out_emulated = emulator_pio_out_emulated,
8332 .get_segment = emulator_get_segment,
8333 .set_segment = emulator_set_segment,
8334 .get_cached_segment_base = emulator_get_cached_segment_base,
8335 .get_gdt = emulator_get_gdt,
8336 .get_idt = emulator_get_idt,
8337 .set_gdt = emulator_set_gdt,
8338 .set_idt = emulator_set_idt,
8339 .get_cr = emulator_get_cr,
8340 .set_cr = emulator_set_cr,
8341 .cpl = emulator_get_cpl,
8342 .get_dr = emulator_get_dr,
8343 .set_dr = emulator_set_dr,
8344 .set_msr_with_filter = emulator_set_msr_with_filter,
8345 .get_msr_with_filter = emulator_get_msr_with_filter,
8346 .get_msr = emulator_get_msr,
8347 .check_pmc = emulator_check_pmc,
8348 .read_pmc = emulator_read_pmc,
8349 .halt = emulator_halt,
8350 .wbinvd = emulator_wbinvd,
8351 .fix_hypercall = emulator_fix_hypercall,
8352 .intercept = emulator_intercept,
8353 .get_cpuid = emulator_get_cpuid,
8354 .guest_has_long_mode = emulator_guest_has_long_mode,
8355 .guest_has_movbe = emulator_guest_has_movbe,
8356 .guest_has_fxsr = emulator_guest_has_fxsr,
8357 .guest_has_rdpid = emulator_guest_has_rdpid,
8358 .set_nmi_mask = emulator_set_nmi_mask,
8359 .is_smm = emulator_is_smm,
8360 .is_guest_mode = emulator_is_guest_mode,
8361 .leave_smm = emulator_leave_smm,
8362 .triple_fault = emulator_triple_fault,
8363 .set_xcr = emulator_set_xcr,
8366 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
8368 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8370 * an sti; sti; sequence only disable interrupts for the first
8371 * instruction. So, if the last instruction, be it emulated or
8372 * not, left the system with the INT_STI flag enabled, it
8373 * means that the last instruction is an sti. We should not
8374 * leave the flag on in this case. The same goes for mov ss
8376 if (int_shadow & mask)
8378 if (unlikely(int_shadow || mask)) {
8379 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
8381 kvm_make_request(KVM_REQ_EVENT, vcpu);
8385 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
8387 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8389 if (ctxt->exception.vector == PF_VECTOR)
8390 kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
8391 else if (ctxt->exception.error_code_valid)
8392 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
8393 ctxt->exception.error_code);
8395 kvm_queue_exception(vcpu, ctxt->exception.vector);
8398 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
8400 struct x86_emulate_ctxt *ctxt;
8402 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
8404 pr_err("failed to allocate vcpu's emulator\n");
8409 ctxt->ops = &emulate_ops;
8410 vcpu->arch.emulate_ctxt = ctxt;
8415 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
8417 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8420 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
8422 ctxt->gpa_available = false;
8423 ctxt->eflags = kvm_get_rflags(vcpu);
8424 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
8426 ctxt->eip = kvm_rip_read(vcpu);
8427 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
8428 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
8429 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
8430 cs_db ? X86EMUL_MODE_PROT32 :
8431 X86EMUL_MODE_PROT16;
8432 ctxt->interruptibility = 0;
8433 ctxt->have_exception = false;
8434 ctxt->exception.vector = -1;
8435 ctxt->perm_ok = false;
8437 init_decode_cache(ctxt);
8438 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8441 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
8443 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8446 init_emulate_ctxt(vcpu);
8450 ctxt->_eip = ctxt->eip + inc_eip;
8451 ret = emulate_int_real(ctxt, irq);
8453 if (ret != X86EMUL_CONTINUE) {
8454 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8456 ctxt->eip = ctxt->_eip;
8457 kvm_rip_write(vcpu, ctxt->eip);
8458 kvm_set_rflags(vcpu, ctxt->eflags);
8461 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
8463 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8464 u8 ndata, u8 *insn_bytes, u8 insn_size)
8466 struct kvm_run *run = vcpu->run;
8471 * Zero the whole array used to retrieve the exit info, as casting to
8472 * u32 for select entries will leave some chunks uninitialized.
8474 memset(&info, 0, sizeof(info));
8476 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
8477 &info[2], (u32 *)&info[3],
8480 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8481 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
8484 * There's currently space for 13 entries, but 5 are used for the exit
8485 * reason and info. Restrict to 4 to reduce the maintenance burden
8486 * when expanding kvm_run.emulation_failure in the future.
8488 if (WARN_ON_ONCE(ndata > 4))
8491 /* Always include the flags as a 'data' entry. */
8493 run->emulation_failure.flags = 0;
8496 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8497 sizeof(run->emulation_failure.insn_bytes) != 16));
8499 run->emulation_failure.flags |=
8500 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8501 run->emulation_failure.insn_size = insn_size;
8502 memset(run->emulation_failure.insn_bytes, 0x90,
8503 sizeof(run->emulation_failure.insn_bytes));
8504 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8507 memcpy(&run->internal.data[info_start], info, sizeof(info));
8508 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8509 ndata * sizeof(data[0]));
8511 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8514 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8516 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8518 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8519 ctxt->fetch.end - ctxt->fetch.data);
8522 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8525 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8527 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8529 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8531 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8533 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8535 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8537 struct kvm *kvm = vcpu->kvm;
8539 ++vcpu->stat.insn_emulation_fail;
8540 trace_kvm_emulate_insn_failed(vcpu);
8542 if (emulation_type & EMULTYPE_VMWARE_GP) {
8543 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8547 if (kvm->arch.exit_on_emulation_error ||
8548 (emulation_type & EMULTYPE_SKIP)) {
8549 prepare_emulation_ctxt_failure_exit(vcpu);
8553 kvm_queue_exception(vcpu, UD_VECTOR);
8555 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8556 prepare_emulation_ctxt_failure_exit(vcpu);
8563 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8566 gpa_t gpa = cr2_or_gpa;
8569 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8572 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8573 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8576 if (!vcpu->arch.mmu->root_role.direct) {
8578 * Write permission should be allowed since only
8579 * write access need to be emulated.
8581 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8584 * If the mapping is invalid in guest, let cpu retry
8585 * it to generate fault.
8587 if (gpa == INVALID_GPA)
8592 * Do not retry the unhandleable instruction if it faults on the
8593 * readonly host memory, otherwise it will goto a infinite loop:
8594 * retry instruction -> write #PF -> emulation fail -> retry
8595 * instruction -> ...
8597 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8600 * If the instruction failed on the error pfn, it can not be fixed,
8601 * report the error to userspace.
8603 if (is_error_noslot_pfn(pfn))
8606 kvm_release_pfn_clean(pfn);
8608 /* The instructions are well-emulated on direct mmu. */
8609 if (vcpu->arch.mmu->root_role.direct) {
8610 unsigned int indirect_shadow_pages;
8612 write_lock(&vcpu->kvm->mmu_lock);
8613 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8614 write_unlock(&vcpu->kvm->mmu_lock);
8616 if (indirect_shadow_pages)
8617 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8623 * if emulation was due to access to shadowed page table
8624 * and it failed try to unshadow page and re-enter the
8625 * guest to let CPU execute the instruction.
8627 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8630 * If the access faults on its page table, it can not
8631 * be fixed by unprotecting shadow page and it should
8632 * be reported to userspace.
8634 return !(emulation_type & EMULTYPE_WRITE_PF_TO_SP);
8637 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8638 gpa_t cr2_or_gpa, int emulation_type)
8640 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8641 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8643 last_retry_eip = vcpu->arch.last_retry_eip;
8644 last_retry_addr = vcpu->arch.last_retry_addr;
8647 * If the emulation is caused by #PF and it is non-page_table
8648 * writing instruction, it means the VM-EXIT is caused by shadow
8649 * page protected, we can zap the shadow page and retry this
8650 * instruction directly.
8652 * Note: if the guest uses a non-page-table modifying instruction
8653 * on the PDE that points to the instruction, then we will unmap
8654 * the instruction and go to an infinite loop. So, we cache the
8655 * last retried eip and the last fault address, if we meet the eip
8656 * and the address again, we can break out of the potential infinite
8659 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8661 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8664 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8665 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8668 if (x86_page_table_writing_insn(ctxt))
8671 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8674 vcpu->arch.last_retry_eip = ctxt->eip;
8675 vcpu->arch.last_retry_addr = cr2_or_gpa;
8677 if (!vcpu->arch.mmu->root_role.direct)
8678 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8680 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8685 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8686 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8688 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8697 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8698 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8703 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8705 struct kvm_run *kvm_run = vcpu->run;
8707 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8708 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8709 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8710 kvm_run->debug.arch.exception = DB_VECTOR;
8711 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8714 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8718 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8720 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8723 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8727 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8730 * rflags is the old, "raw" value of the flags. The new value has
8731 * not been saved yet.
8733 * This is correct even for TF set by the guest, because "the
8734 * processor will not generate this exception after the instruction
8735 * that sets the TF flag".
8737 if (unlikely(rflags & X86_EFLAGS_TF))
8738 r = kvm_vcpu_do_singlestep(vcpu);
8741 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8743 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
8747 if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
8751 * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
8752 * but AMD CPUs do not. MOV/POP SS blocking is rare, check that first
8753 * to avoid the relatively expensive CPUID lookup.
8755 shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8756 return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
8757 guest_cpuid_is_intel(vcpu);
8760 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,
8761 int emulation_type, int *r)
8763 WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE);
8766 * Do not check for code breakpoints if hardware has already done the
8767 * checks, as inferred from the emulation type. On NO_DECODE and SKIP,
8768 * the instruction has passed all exception checks, and all intercepted
8769 * exceptions that trigger emulation have lower priority than code
8770 * breakpoints, i.e. the fact that the intercepted exception occurred
8771 * means any code breakpoints have already been serviced.
8773 * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as
8774 * hardware has checked the RIP of the magic prefix, but not the RIP of
8775 * the instruction being emulated. The intent of forced emulation is
8776 * to behave as if KVM intercepted the instruction without an exception
8777 * and without a prefix.
8779 if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
8780 EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF))
8783 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8784 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8785 struct kvm_run *kvm_run = vcpu->run;
8786 unsigned long eip = kvm_get_linear_rip(vcpu);
8787 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8788 vcpu->arch.guest_debug_dr7,
8792 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8793 kvm_run->debug.arch.pc = eip;
8794 kvm_run->debug.arch.exception = DB_VECTOR;
8795 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8801 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8802 !kvm_is_code_breakpoint_inhibited(vcpu)) {
8803 unsigned long eip = kvm_get_linear_rip(vcpu);
8804 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8809 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8818 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8820 switch (ctxt->opcode_len) {
8827 case 0xe6: /* OUT */
8831 case 0x6c: /* INS */
8833 case 0x6e: /* OUTS */
8840 case 0x33: /* RDPMC */
8850 * Decode an instruction for emulation. The caller is responsible for handling
8851 * code breakpoints. Note, manually detecting code breakpoints is unnecessary
8852 * (and wrong) when emulating on an intercepted fault-like exception[*], as
8853 * code breakpoints have higher priority and thus have already been done by
8856 * [*] Except #MC, which is higher priority, but KVM should never emulate in
8857 * response to a machine check.
8859 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8860 void *insn, int insn_len)
8862 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8865 init_emulate_ctxt(vcpu);
8867 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8869 trace_kvm_emulate_insn_start(vcpu);
8870 ++vcpu->stat.insn_emulation;
8874 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8876 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8877 int emulation_type, void *insn, int insn_len)
8880 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8881 bool writeback = true;
8883 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8886 vcpu->arch.l1tf_flush_l1d = true;
8888 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8889 kvm_clear_exception_queue(vcpu);
8892 * Return immediately if RIP hits a code breakpoint, such #DBs
8893 * are fault-like and are higher priority than any faults on
8894 * the code fetch itself.
8896 if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r))
8899 r = x86_decode_emulated_instruction(vcpu, emulation_type,
8901 if (r != EMULATION_OK) {
8902 if ((emulation_type & EMULTYPE_TRAP_UD) ||
8903 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8904 kvm_queue_exception(vcpu, UD_VECTOR);
8907 if (reexecute_instruction(vcpu, cr2_or_gpa,
8911 if (ctxt->have_exception &&
8912 !(emulation_type & EMULTYPE_SKIP)) {
8914 * #UD should result in just EMULATION_FAILED, and trap-like
8915 * exception should not be encountered during decode.
8917 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8918 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8919 inject_emulated_exception(vcpu);
8922 return handle_emulation_failure(vcpu, emulation_type);
8926 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8927 !is_vmware_backdoor_opcode(ctxt)) {
8928 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8933 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8934 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8935 * The caller is responsible for updating interruptibility state and
8936 * injecting single-step #DBs.
8938 if (emulation_type & EMULTYPE_SKIP) {
8939 if (ctxt->mode != X86EMUL_MODE_PROT64)
8940 ctxt->eip = (u32)ctxt->_eip;
8942 ctxt->eip = ctxt->_eip;
8944 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8949 kvm_rip_write(vcpu, ctxt->eip);
8950 if (ctxt->eflags & X86_EFLAGS_RF)
8951 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8955 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8958 /* this is needed for vmware backdoor interface to work since it
8959 changes registers values during IO operation */
8960 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8961 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8962 emulator_invalidate_register_cache(ctxt);
8966 if (emulation_type & EMULTYPE_PF) {
8967 /* Save the faulting GPA (cr2) in the address field */
8968 ctxt->exception.address = cr2_or_gpa;
8970 /* With shadow page tables, cr2 contains a GVA or nGPA. */
8971 if (vcpu->arch.mmu->root_role.direct) {
8972 ctxt->gpa_available = true;
8973 ctxt->gpa_val = cr2_or_gpa;
8976 /* Sanitize the address out of an abundance of paranoia. */
8977 ctxt->exception.address = 0;
8980 r = x86_emulate_insn(ctxt);
8982 if (r == EMULATION_INTERCEPTED)
8985 if (r == EMULATION_FAILED) {
8986 if (reexecute_instruction(vcpu, cr2_or_gpa, emulation_type))
8989 return handle_emulation_failure(vcpu, emulation_type);
8992 if (ctxt->have_exception) {
8993 WARN_ON_ONCE(vcpu->mmio_needed && !vcpu->mmio_is_write);
8994 vcpu->mmio_needed = false;
8996 inject_emulated_exception(vcpu);
8997 } else if (vcpu->arch.pio.count) {
8998 if (!vcpu->arch.pio.in) {
8999 /* FIXME: return into emulator if single-stepping. */
9000 vcpu->arch.pio.count = 0;
9003 vcpu->arch.complete_userspace_io = complete_emulated_pio;
9006 } else if (vcpu->mmio_needed) {
9007 ++vcpu->stat.mmio_exits;
9009 if (!vcpu->mmio_is_write)
9012 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9013 } else if (vcpu->arch.complete_userspace_io) {
9016 } else if (r == EMULATION_RESTART)
9023 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
9024 toggle_interruptibility(vcpu, ctxt->interruptibility);
9025 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9028 * Note, EXCPT_DB is assumed to be fault-like as the emulator
9029 * only supports code breakpoints and general detect #DB, both
9030 * of which are fault-like.
9032 if (!ctxt->have_exception ||
9033 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
9034 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
9035 if (ctxt->is_branch)
9036 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
9037 kvm_rip_write(vcpu, ctxt->eip);
9038 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
9039 r = kvm_vcpu_do_singlestep(vcpu);
9040 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
9041 __kvm_set_rflags(vcpu, ctxt->eflags);
9045 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
9046 * do nothing, and it will be requested again as soon as
9047 * the shadow expires. But we still need to check here,
9048 * because POPF has no interrupt shadow.
9050 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
9051 kvm_make_request(KVM_REQ_EVENT, vcpu);
9053 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
9058 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
9060 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
9062 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
9064 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
9065 void *insn, int insn_len)
9067 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
9069 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
9071 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
9073 vcpu->arch.pio.count = 0;
9077 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
9079 vcpu->arch.pio.count = 0;
9081 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
9084 return kvm_skip_emulated_instruction(vcpu);
9087 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
9088 unsigned short port)
9090 unsigned long val = kvm_rax_read(vcpu);
9091 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
9097 * Workaround userspace that relies on old KVM behavior of %rip being
9098 * incremented prior to exiting to userspace to handle "OUT 0x7e".
9101 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
9102 vcpu->arch.complete_userspace_io =
9103 complete_fast_pio_out_port_0x7e;
9104 kvm_skip_emulated_instruction(vcpu);
9106 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9107 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
9112 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
9116 /* We should only ever be called with arch.pio.count equal to 1 */
9117 BUG_ON(vcpu->arch.pio.count != 1);
9119 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
9120 vcpu->arch.pio.count = 0;
9124 /* For size less than 4 we merge, else we zero extend */
9125 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
9127 complete_emulator_pio_in(vcpu, &val);
9128 kvm_rax_write(vcpu, val);
9130 return kvm_skip_emulated_instruction(vcpu);
9133 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
9134 unsigned short port)
9139 /* For size less than 4 we merge, else we zero extend */
9140 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
9142 ret = emulator_pio_in(vcpu, size, port, &val, 1);
9144 kvm_rax_write(vcpu, val);
9148 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9149 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
9154 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
9159 ret = kvm_fast_pio_in(vcpu, size, port);
9161 ret = kvm_fast_pio_out(vcpu, size, port);
9162 return ret && kvm_skip_emulated_instruction(vcpu);
9164 EXPORT_SYMBOL_GPL(kvm_fast_pio);
9166 static int kvmclock_cpu_down_prep(unsigned int cpu)
9168 __this_cpu_write(cpu_tsc_khz, 0);
9172 static void tsc_khz_changed(void *data)
9174 struct cpufreq_freqs *freq = data;
9175 unsigned long khz = 0;
9177 WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC));
9182 khz = cpufreq_quick_get(raw_smp_processor_id());
9185 __this_cpu_write(cpu_tsc_khz, khz);
9188 #ifdef CONFIG_X86_64
9189 static void kvm_hyperv_tsc_notifier(void)
9194 mutex_lock(&kvm_lock);
9195 list_for_each_entry(kvm, &vm_list, vm_list)
9196 kvm_make_mclock_inprogress_request(kvm);
9198 /* no guest entries from this point */
9199 hyperv_stop_tsc_emulation();
9201 /* TSC frequency always matches when on Hyper-V */
9202 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9203 for_each_present_cpu(cpu)
9204 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
9206 kvm_caps.max_guest_tsc_khz = tsc_khz;
9208 list_for_each_entry(kvm, &vm_list, vm_list) {
9209 __kvm_start_pvclock_update(kvm);
9210 pvclock_update_vm_gtod_copy(kvm);
9211 kvm_end_pvclock_update(kvm);
9214 mutex_unlock(&kvm_lock);
9218 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
9221 struct kvm_vcpu *vcpu;
9226 * We allow guests to temporarily run on slowing clocks,
9227 * provided we notify them after, or to run on accelerating
9228 * clocks, provided we notify them before. Thus time never
9231 * However, we have a problem. We can't atomically update
9232 * the frequency of a given CPU from this function; it is
9233 * merely a notifier, which can be called from any CPU.
9234 * Changing the TSC frequency at arbitrary points in time
9235 * requires a recomputation of local variables related to
9236 * the TSC for each VCPU. We must flag these local variables
9237 * to be updated and be sure the update takes place with the
9238 * new frequency before any guests proceed.
9240 * Unfortunately, the combination of hotplug CPU and frequency
9241 * change creates an intractable locking scenario; the order
9242 * of when these callouts happen is undefined with respect to
9243 * CPU hotplug, and they can race with each other. As such,
9244 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
9245 * undefined; you can actually have a CPU frequency change take
9246 * place in between the computation of X and the setting of the
9247 * variable. To protect against this problem, all updates of
9248 * the per_cpu tsc_khz variable are done in an interrupt
9249 * protected IPI, and all callers wishing to update the value
9250 * must wait for a synchronous IPI to complete (which is trivial
9251 * if the caller is on the CPU already). This establishes the
9252 * necessary total order on variable updates.
9254 * Note that because a guest time update may take place
9255 * anytime after the setting of the VCPU's request bit, the
9256 * correct TSC value must be set before the request. However,
9257 * to ensure the update actually makes it to any guest which
9258 * starts running in hardware virtualization between the set
9259 * and the acquisition of the spinlock, we must also ping the
9260 * CPU after setting the request bit.
9264 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9266 mutex_lock(&kvm_lock);
9267 list_for_each_entry(kvm, &vm_list, vm_list) {
9268 kvm_for_each_vcpu(i, vcpu, kvm) {
9269 if (vcpu->cpu != cpu)
9271 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9272 if (vcpu->cpu != raw_smp_processor_id())
9276 mutex_unlock(&kvm_lock);
9278 if (freq->old < freq->new && send_ipi) {
9280 * We upscale the frequency. Must make the guest
9281 * doesn't see old kvmclock values while running with
9282 * the new frequency, otherwise we risk the guest sees
9283 * time go backwards.
9285 * In case we update the frequency for another cpu
9286 * (which might be in guest context) send an interrupt
9287 * to kick the cpu out of guest context. Next time
9288 * guest context is entered kvmclock will be updated,
9289 * so the guest will not see stale values.
9291 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9295 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
9298 struct cpufreq_freqs *freq = data;
9301 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
9303 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
9306 for_each_cpu(cpu, freq->policy->cpus)
9307 __kvmclock_cpufreq_notifier(freq, cpu);
9312 static struct notifier_block kvmclock_cpufreq_notifier_block = {
9313 .notifier_call = kvmclock_cpufreq_notifier
9316 static int kvmclock_cpu_online(unsigned int cpu)
9318 tsc_khz_changed(NULL);
9322 static void kvm_timer_init(void)
9324 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9325 max_tsc_khz = tsc_khz;
9327 if (IS_ENABLED(CONFIG_CPU_FREQ)) {
9328 struct cpufreq_policy *policy;
9332 policy = cpufreq_cpu_get(cpu);
9334 if (policy->cpuinfo.max_freq)
9335 max_tsc_khz = policy->cpuinfo.max_freq;
9336 cpufreq_cpu_put(policy);
9340 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
9341 CPUFREQ_TRANSITION_NOTIFIER);
9343 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
9344 kvmclock_cpu_online, kvmclock_cpu_down_prep);
9348 #ifdef CONFIG_X86_64
9349 static void pvclock_gtod_update_fn(struct work_struct *work)
9352 struct kvm_vcpu *vcpu;
9355 mutex_lock(&kvm_lock);
9356 list_for_each_entry(kvm, &vm_list, vm_list)
9357 kvm_for_each_vcpu(i, vcpu, kvm)
9358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9359 atomic_set(&kvm_guest_has_master_clock, 0);
9360 mutex_unlock(&kvm_lock);
9363 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
9366 * Indirection to move queue_work() out of the tk_core.seq write held
9367 * region to prevent possible deadlocks against time accessors which
9368 * are invoked with work related locks held.
9370 static void pvclock_irq_work_fn(struct irq_work *w)
9372 queue_work(system_long_wq, &pvclock_gtod_work);
9375 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
9378 * Notification about pvclock gtod data update.
9380 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
9383 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
9384 struct timekeeper *tk = priv;
9386 update_pvclock_gtod(tk);
9389 * Disable master clock if host does not trust, or does not use,
9390 * TSC based clocksource. Delegate queue_work() to irq_work as
9391 * this is invoked with tk_core.seq write held.
9393 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
9394 atomic_read(&kvm_guest_has_master_clock) != 0)
9395 irq_work_queue(&pvclock_irq_work);
9399 static struct notifier_block pvclock_gtod_notifier = {
9400 .notifier_call = pvclock_gtod_notify,
9404 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
9406 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9408 #define __KVM_X86_OP(func) \
9409 static_call_update(kvm_x86_##func, kvm_x86_ops.func);
9410 #define KVM_X86_OP(func) \
9411 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func)
9412 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP
9413 #define KVM_X86_OP_OPTIONAL_RET0(func) \
9414 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \
9415 (void *)__static_call_return0);
9416 #include <asm/kvm-x86-ops.h>
9419 kvm_pmu_ops_update(ops->pmu_ops);
9422 static int kvm_x86_check_processor_compatibility(void)
9424 int cpu = smp_processor_id();
9425 struct cpuinfo_x86 *c = &cpu_data(cpu);
9428 * Compatibility checks are done when loading KVM and when enabling
9429 * hardware, e.g. during CPU hotplug, to ensure all online CPUs are
9430 * compatible, i.e. KVM should never perform a compatibility check on
9433 WARN_ON(!cpu_online(cpu));
9435 if (__cr4_reserved_bits(cpu_has, c) !=
9436 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9439 return static_call(kvm_x86_check_processor_compatibility)();
9442 static void kvm_x86_check_cpu_compat(void *ret)
9444 *(int *)ret = kvm_x86_check_processor_compatibility();
9447 static int __kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9452 if (kvm_x86_ops.hardware_enable) {
9453 pr_err("already loaded vendor module '%s'\n", kvm_x86_ops.name);
9458 * KVM explicitly assumes that the guest has an FPU and
9459 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
9460 * vCPU's FPU state as a fxregs_state struct.
9462 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
9463 pr_err("inadequate fpu\n");
9467 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9468 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
9473 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes
9474 * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something
9475 * other than WB. Note, EPT doesn't utilize the PAT, but don't bother
9476 * with an exception. PAT[0] is set to WB on RESET and also by the
9477 * kernel, i.e. failure indicates a kernel bug or broken firmware.
9479 if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) ||
9480 (host_pat & GENMASK(2, 0)) != 6) {
9481 pr_err("host PAT[0] is not WB\n");
9485 x86_emulator_cache = kvm_alloc_emulator_cache();
9486 if (!x86_emulator_cache) {
9487 pr_err("failed to allocate cache for x86 emulator\n");
9491 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
9492 if (!user_return_msrs) {
9493 pr_err("failed to allocate percpu kvm_user_return_msrs\n");
9495 goto out_free_x86_emulator_cache;
9497 kvm_nr_uret_msrs = 0;
9499 r = kvm_mmu_vendor_module_init();
9501 goto out_free_percpu;
9503 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
9504 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
9505 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
9508 rdmsrl_safe(MSR_EFER, &host_efer);
9510 if (boot_cpu_has(X86_FEATURE_XSAVES))
9511 rdmsrl(MSR_IA32_XSS, host_xss);
9513 kvm_init_pmu_capability(ops->pmu_ops);
9515 r = ops->hardware_setup();
9519 kvm_ops_update(ops);
9521 for_each_online_cpu(cpu) {
9522 smp_call_function_single(cpu, kvm_x86_check_cpu_compat, &r, 1);
9524 goto out_unwind_ops;
9528 * Point of no return! DO NOT add error paths below this point unless
9529 * absolutely necessary, as most operations from this point forward
9530 * require unwinding.
9534 if (pi_inject_timer == -1)
9535 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
9536 #ifdef CONFIG_X86_64
9537 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
9539 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9540 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
9543 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
9545 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9546 kvm_caps.supported_xss = 0;
9548 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9549 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9550 #undef __kvm_cpu_cap_has
9552 if (kvm_caps.has_tsc_control) {
9554 * Make sure the user can only configure tsc_khz values that
9555 * fit into a signed integer.
9556 * A min value is not calculated because it will always
9557 * be 1 on all machines.
9559 u64 max = min(0x7fffffffULL,
9560 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
9561 kvm_caps.max_guest_tsc_khz = max;
9563 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
9564 kvm_init_msr_lists();
9568 kvm_x86_ops.hardware_enable = NULL;
9569 static_call(kvm_x86_hardware_unsetup)();
9571 kvm_mmu_vendor_module_exit();
9573 free_percpu(user_return_msrs);
9574 out_free_x86_emulator_cache:
9575 kmem_cache_destroy(x86_emulator_cache);
9579 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9583 mutex_lock(&vendor_module_lock);
9584 r = __kvm_x86_vendor_init(ops);
9585 mutex_unlock(&vendor_module_lock);
9589 EXPORT_SYMBOL_GPL(kvm_x86_vendor_init);
9591 void kvm_x86_vendor_exit(void)
9593 kvm_unregister_perf_callbacks();
9595 #ifdef CONFIG_X86_64
9596 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9597 clear_hv_tscchange_cb();
9601 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9602 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
9603 CPUFREQ_TRANSITION_NOTIFIER);
9604 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
9606 #ifdef CONFIG_X86_64
9607 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9608 irq_work_sync(&pvclock_irq_work);
9609 cancel_work_sync(&pvclock_gtod_work);
9611 static_call(kvm_x86_hardware_unsetup)();
9612 kvm_mmu_vendor_module_exit();
9613 free_percpu(user_return_msrs);
9614 kmem_cache_destroy(x86_emulator_cache);
9615 #ifdef CONFIG_KVM_XEN
9616 static_key_deferred_flush(&kvm_xen_enabled);
9617 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9619 mutex_lock(&vendor_module_lock);
9620 kvm_x86_ops.hardware_enable = NULL;
9621 mutex_unlock(&vendor_module_lock);
9623 EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit);
9625 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9628 * The vCPU has halted, e.g. executed HLT. Update the run state if the
9629 * local APIC is in-kernel, the run loop will detect the non-runnable
9630 * state and halt the vCPU. Exit to userspace if the local APIC is
9631 * managed by userspace, in which case userspace is responsible for
9632 * handling wake events.
9634 ++vcpu->stat.halt_exits;
9635 if (lapic_in_kernel(vcpu)) {
9636 vcpu->arch.mp_state = state;
9639 vcpu->run->exit_reason = reason;
9644 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9646 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9648 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9650 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9652 int ret = kvm_skip_emulated_instruction(vcpu);
9654 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9655 * KVM_EXIT_DEBUG here.
9657 return kvm_emulate_halt_noskip(vcpu) && ret;
9659 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9661 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9663 int ret = kvm_skip_emulated_instruction(vcpu);
9665 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9666 KVM_EXIT_AP_RESET_HOLD) && ret;
9668 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9670 #ifdef CONFIG_X86_64
9671 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9672 unsigned long clock_type)
9674 struct kvm_clock_pairing clock_pairing;
9675 struct timespec64 ts;
9679 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9680 return -KVM_EOPNOTSUPP;
9683 * When tsc is in permanent catchup mode guests won't be able to use
9684 * pvclock_read_retry loop to get consistent view of pvclock
9686 if (vcpu->arch.tsc_always_catchup)
9687 return -KVM_EOPNOTSUPP;
9689 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9690 return -KVM_EOPNOTSUPP;
9692 clock_pairing.sec = ts.tv_sec;
9693 clock_pairing.nsec = ts.tv_nsec;
9694 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9695 clock_pairing.flags = 0;
9696 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9699 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9700 sizeof(struct kvm_clock_pairing)))
9708 * kvm_pv_kick_cpu_op: Kick a vcpu.
9710 * @apicid - apicid of vcpu to be kicked.
9712 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9715 * All other fields are unused for APIC_DM_REMRD, but may be consumed by
9716 * common code, e.g. for tracing. Defer initialization to the compiler.
9718 struct kvm_lapic_irq lapic_irq = {
9719 .delivery_mode = APIC_DM_REMRD,
9720 .dest_mode = APIC_DEST_PHYSICAL,
9721 .shorthand = APIC_DEST_NOSHORT,
9725 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9728 bool kvm_apicv_activated(struct kvm *kvm)
9730 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9732 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9734 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
9736 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
9737 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
9739 return (vm_reasons | vcpu_reasons) == 0;
9741 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
9743 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9744 enum kvm_apicv_inhibit reason, bool set)
9747 __set_bit(reason, inhibits);
9749 __clear_bit(reason, inhibits);
9751 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9754 static void kvm_apicv_init(struct kvm *kvm)
9756 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9758 init_rwsem(&kvm->arch.apicv_update_lock);
9760 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9763 set_or_clear_apicv_inhibit(inhibits,
9764 APICV_INHIBIT_REASON_DISABLE, true);
9767 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9769 struct kvm_vcpu *target = NULL;
9770 struct kvm_apic_map *map;
9772 vcpu->stat.directed_yield_attempted++;
9774 if (single_task_running())
9778 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9780 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9781 target = map->phys_map[dest_id]->vcpu;
9785 if (!target || !READ_ONCE(target->ready))
9788 /* Ignore requests to yield to self */
9792 if (kvm_vcpu_yield_to(target) <= 0)
9795 vcpu->stat.directed_yield_successful++;
9801 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9803 u64 ret = vcpu->run->hypercall.ret;
9805 if (!is_64_bit_mode(vcpu))
9807 kvm_rax_write(vcpu, ret);
9808 ++vcpu->stat.hypercalls;
9809 return kvm_skip_emulated_instruction(vcpu);
9812 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9814 unsigned long nr, a0, a1, a2, a3, ret;
9817 if (kvm_xen_hypercall_enabled(vcpu->kvm))
9818 return kvm_xen_hypercall(vcpu);
9820 if (kvm_hv_hypercall_enabled(vcpu))
9821 return kvm_hv_hypercall(vcpu);
9823 nr = kvm_rax_read(vcpu);
9824 a0 = kvm_rbx_read(vcpu);
9825 a1 = kvm_rcx_read(vcpu);
9826 a2 = kvm_rdx_read(vcpu);
9827 a3 = kvm_rsi_read(vcpu);
9829 trace_kvm_hypercall(nr, a0, a1, a2, a3);
9831 op_64_bit = is_64_bit_hypercall(vcpu);
9840 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9848 case KVM_HC_VAPIC_POLL_IRQ:
9851 case KVM_HC_KICK_CPU:
9852 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9855 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9856 kvm_sched_yield(vcpu, a1);
9859 #ifdef CONFIG_X86_64
9860 case KVM_HC_CLOCK_PAIRING:
9861 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9864 case KVM_HC_SEND_IPI:
9865 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9868 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9870 case KVM_HC_SCHED_YIELD:
9871 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9874 kvm_sched_yield(vcpu, a0);
9877 case KVM_HC_MAP_GPA_RANGE: {
9878 u64 gpa = a0, npages = a1, attrs = a2;
9881 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9884 if (!PAGE_ALIGNED(gpa) || !npages ||
9885 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9890 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
9891 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
9892 vcpu->run->hypercall.args[0] = gpa;
9893 vcpu->run->hypercall.args[1] = npages;
9894 vcpu->run->hypercall.args[2] = attrs;
9895 vcpu->run->hypercall.flags = 0;
9897 vcpu->run->hypercall.flags |= KVM_EXIT_HYPERCALL_LONG_MODE;
9899 WARN_ON_ONCE(vcpu->run->hypercall.flags & KVM_EXIT_HYPERCALL_MBZ);
9900 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9910 kvm_rax_write(vcpu, ret);
9912 ++vcpu->stat.hypercalls;
9913 return kvm_skip_emulated_instruction(vcpu);
9915 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9917 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9919 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9920 char instruction[3];
9921 unsigned long rip = kvm_rip_read(vcpu);
9924 * If the quirk is disabled, synthesize a #UD and let the guest pick up
9927 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
9928 ctxt->exception.error_code_valid = false;
9929 ctxt->exception.vector = UD_VECTOR;
9930 ctxt->have_exception = true;
9931 return X86EMUL_PROPAGATE_FAULT;
9934 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9936 return emulator_write_emulated(ctxt, rip, instruction, 3,
9940 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9942 return vcpu->run->request_interrupt_window &&
9943 likely(!pic_in_kernel(vcpu->kvm));
9946 /* Called within kvm->srcu read side. */
9947 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9949 struct kvm_run *kvm_run = vcpu->run;
9951 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9952 kvm_run->cr8 = kvm_get_cr8(vcpu);
9953 kvm_run->apic_base = kvm_get_apic_base(vcpu);
9955 kvm_run->ready_for_interrupt_injection =
9956 pic_in_kernel(vcpu->kvm) ||
9957 kvm_vcpu_ready_for_interrupt_injection(vcpu);
9960 kvm_run->flags |= KVM_RUN_X86_SMM;
9963 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9967 if (!kvm_x86_ops.update_cr8_intercept)
9970 if (!lapic_in_kernel(vcpu))
9973 if (vcpu->arch.apic->apicv_active)
9976 if (!vcpu->arch.apic->vapic_addr)
9977 max_irr = kvm_lapic_find_highest_irr(vcpu);
9984 tpr = kvm_lapic_get_cr8(vcpu);
9986 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
9990 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
9992 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9993 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9997 return kvm_x86_ops.nested_ops->check_events(vcpu);
10000 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
10003 * Suppress the error code if the vCPU is in Real Mode, as Real Mode
10004 * exceptions don't report error codes. The presence of an error code
10005 * is carried with the exception and only stripped when the exception
10006 * is injected as intercepted #PF VM-Exits for AMD's Paged Real Mode do
10007 * report an error code despite the CPU being in Real Mode.
10009 vcpu->arch.exception.has_error_code &= is_protmode(vcpu);
10011 trace_kvm_inj_exception(vcpu->arch.exception.vector,
10012 vcpu->arch.exception.has_error_code,
10013 vcpu->arch.exception.error_code,
10014 vcpu->arch.exception.injected);
10016 static_call(kvm_x86_inject_exception)(vcpu);
10020 * Check for any event (interrupt or exception) that is ready to be injected,
10021 * and if there is at least one event, inject the event with the highest
10022 * priority. This handles both "pending" events, i.e. events that have never
10023 * been injected into the guest, and "injected" events, i.e. events that were
10024 * injected as part of a previous VM-Enter, but weren't successfully delivered
10025 * and need to be re-injected.
10027 * Note, this is not guaranteed to be invoked on a guest instruction boundary,
10028 * i.e. doesn't guarantee that there's an event window in the guest. KVM must
10029 * be able to inject exceptions in the "middle" of an instruction, and so must
10030 * also be able to re-inject NMIs and IRQs in the middle of an instruction.
10031 * I.e. for exceptions and re-injected events, NOT invoking this on instruction
10032 * boundaries is necessary and correct.
10034 * For simplicity, KVM uses a single path to inject all events (except events
10035 * that are injected directly from L1 to L2) and doesn't explicitly track
10036 * instruction boundaries for asynchronous events. However, because VM-Exits
10037 * that can occur during instruction execution typically result in KVM skipping
10038 * the instruction or injecting an exception, e.g. instruction and exception
10039 * intercepts, and because pending exceptions have higher priority than pending
10040 * interrupts, KVM still honors instruction boundaries in most scenarios.
10042 * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip
10043 * the instruction or inject an exception, then KVM can incorrecty inject a new
10044 * asynchrounous event if the event became pending after the CPU fetched the
10045 * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation)
10046 * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be
10047 * injected on the restarted instruction instead of being deferred until the
10048 * instruction completes.
10050 * In practice, this virtualization hole is unlikely to be observed by the
10051 * guest, and even less likely to cause functional problems. To detect the
10052 * hole, the guest would have to trigger an event on a side effect of an early
10053 * phase of instruction execution, e.g. on the instruction fetch from memory.
10054 * And for it to be a functional problem, the guest would need to depend on the
10055 * ordering between that side effect, the instruction completing, _and_ the
10056 * delivery of the asynchronous event.
10058 static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu,
10059 bool *req_immediate_exit)
10065 * Process nested events first, as nested VM-Exit supercedes event
10066 * re-injection. If there's an event queued for re-injection, it will
10067 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit.
10069 if (is_guest_mode(vcpu))
10070 r = kvm_check_nested_events(vcpu);
10075 * Re-inject exceptions and events *especially* if immediate entry+exit
10076 * to/from L2 is needed, as any event that has already been injected
10077 * into L2 needs to complete its lifecycle before injecting a new event.
10079 * Don't re-inject an NMI or interrupt if there is a pending exception.
10080 * This collision arises if an exception occurred while vectoring the
10081 * injected event, KVM intercepted said exception, and KVM ultimately
10082 * determined the fault belongs to the guest and queues the exception
10083 * for injection back into the guest.
10085 * "Injected" interrupts can also collide with pending exceptions if
10086 * userspace ignores the "ready for injection" flag and blindly queues
10087 * an interrupt. In that case, prioritizing the exception is correct,
10088 * as the exception "occurred" before the exit to userspace. Trap-like
10089 * exceptions, e.g. most #DBs, have higher priority than interrupts.
10090 * And while fault-like exceptions, e.g. #GP and #PF, are the lowest
10091 * priority, they're only generated (pended) during instruction
10092 * execution, and interrupts are recognized at instruction boundaries.
10093 * Thus a pending fault-like exception means the fault occurred on the
10094 * *previous* instruction and must be serviced prior to recognizing any
10095 * new events in order to fully complete the previous instruction.
10097 if (vcpu->arch.exception.injected)
10098 kvm_inject_exception(vcpu);
10099 else if (kvm_is_exception_pending(vcpu))
10101 else if (vcpu->arch.nmi_injected)
10102 static_call(kvm_x86_inject_nmi)(vcpu);
10103 else if (vcpu->arch.interrupt.injected)
10104 static_call(kvm_x86_inject_irq)(vcpu, true);
10107 * Exceptions that morph to VM-Exits are handled above, and pending
10108 * exceptions on top of injected exceptions that do not VM-Exit should
10109 * either morph to #DF or, sadly, override the injected exception.
10111 WARN_ON_ONCE(vcpu->arch.exception.injected &&
10112 vcpu->arch.exception.pending);
10115 * Bail if immediate entry+exit to/from the guest is needed to complete
10116 * nested VM-Enter or event re-injection so that a different pending
10117 * event can be serviced (or if KVM needs to exit to userspace).
10119 * Otherwise, continue processing events even if VM-Exit occurred. The
10120 * VM-Exit will have cleared exceptions that were meant for L2, but
10121 * there may now be events that can be injected into L1.
10127 * A pending exception VM-Exit should either result in nested VM-Exit
10128 * or force an immediate re-entry and exit to/from L2, and exception
10129 * VM-Exits cannot be injected (flag should _never_ be set).
10131 WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected ||
10132 vcpu->arch.exception_vmexit.pending);
10135 * New events, other than exceptions, cannot be injected if KVM needs
10136 * to re-inject a previous event. See above comments on re-injecting
10137 * for why pending exceptions get priority.
10139 can_inject = !kvm_event_needs_reinjection(vcpu);
10141 if (vcpu->arch.exception.pending) {
10143 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS
10144 * value pushed on the stack. Trap-like exception and all #DBs
10145 * leave RF as-is (KVM follows Intel's behavior in this regard;
10146 * AMD states that code breakpoint #DBs excplitly clear RF=0).
10148 * Note, most versions of Intel's SDM and AMD's APM incorrectly
10149 * describe the behavior of General Detect #DBs, which are
10150 * fault-like. They do _not_ set RF, a la code breakpoints.
10152 if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT)
10153 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
10156 if (vcpu->arch.exception.vector == DB_VECTOR) {
10157 kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception);
10158 if (vcpu->arch.dr7 & DR7_GD) {
10159 vcpu->arch.dr7 &= ~DR7_GD;
10160 kvm_update_dr7(vcpu);
10164 kvm_inject_exception(vcpu);
10166 vcpu->arch.exception.pending = false;
10167 vcpu->arch.exception.injected = true;
10169 can_inject = false;
10172 /* Don't inject interrupts if the user asked to avoid doing so */
10173 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
10177 * Finally, inject interrupt events. If an event cannot be injected
10178 * due to architectural conditions (e.g. IF=0) a window-open exit
10179 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
10180 * and can architecturally be injected, but we cannot do it right now:
10181 * an interrupt could have arrived just now and we have to inject it
10182 * as a vmexit, or there could already an event in the queue, which is
10183 * indicated by can_inject. In that case we request an immediate exit
10184 * in order to make progress and get back here for another iteration.
10185 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
10187 #ifdef CONFIG_KVM_SMM
10188 if (vcpu->arch.smi_pending) {
10189 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
10193 vcpu->arch.smi_pending = false;
10194 ++vcpu->arch.smi_count;
10196 can_inject = false;
10198 static_call(kvm_x86_enable_smi_window)(vcpu);
10202 if (vcpu->arch.nmi_pending) {
10203 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
10207 --vcpu->arch.nmi_pending;
10208 vcpu->arch.nmi_injected = true;
10209 static_call(kvm_x86_inject_nmi)(vcpu);
10210 can_inject = false;
10211 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
10213 if (vcpu->arch.nmi_pending)
10214 static_call(kvm_x86_enable_nmi_window)(vcpu);
10217 if (kvm_cpu_has_injectable_intr(vcpu)) {
10218 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
10222 int irq = kvm_cpu_get_interrupt(vcpu);
10224 if (!WARN_ON_ONCE(irq == -1)) {
10225 kvm_queue_interrupt(vcpu, irq, false);
10226 static_call(kvm_x86_inject_irq)(vcpu, false);
10227 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
10230 if (kvm_cpu_has_injectable_intr(vcpu))
10231 static_call(kvm_x86_enable_irq_window)(vcpu);
10234 if (is_guest_mode(vcpu) &&
10235 kvm_x86_ops.nested_ops->has_events &&
10236 kvm_x86_ops.nested_ops->has_events(vcpu))
10237 *req_immediate_exit = true;
10240 * KVM must never queue a new exception while injecting an event; KVM
10241 * is done emulating and should only propagate the to-be-injected event
10242 * to the VMCS/VMCB. Queueing a new exception can put the vCPU into an
10243 * infinite loop as KVM will bail from VM-Enter to inject the pending
10244 * exception and start the cycle all over.
10246 * Exempt triple faults as they have special handling and won't put the
10247 * vCPU into an infinite loop. Triple fault can be queued when running
10248 * VMX without unrestricted guest, as that requires KVM to emulate Real
10249 * Mode events (see kvm_inject_realmode_interrupt()).
10251 WARN_ON_ONCE(vcpu->arch.exception.pending ||
10252 vcpu->arch.exception_vmexit.pending);
10257 *req_immediate_exit = true;
10263 static void process_nmi(struct kvm_vcpu *vcpu)
10265 unsigned int limit;
10268 * x86 is limited to one NMI pending, but because KVM can't react to
10269 * incoming NMIs as quickly as bare metal, e.g. if the vCPU is
10270 * scheduled out, KVM needs to play nice with two queued NMIs showing
10271 * up at the same time. To handle this scenario, allow two NMIs to be
10272 * (temporarily) pending so long as NMIs are not blocked and KVM is not
10273 * waiting for a previous NMI injection to complete (which effectively
10274 * blocks NMIs). KVM will immediately inject one of the two NMIs, and
10275 * will request an NMI window to handle the second NMI.
10277 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
10283 * Adjust the limit to account for pending virtual NMIs, which aren't
10284 * tracked in vcpu->arch.nmi_pending.
10286 if (static_call(kvm_x86_is_vnmi_pending)(vcpu))
10289 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
10290 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
10292 if (vcpu->arch.nmi_pending &&
10293 (static_call(kvm_x86_set_vnmi_pending)(vcpu)))
10294 vcpu->arch.nmi_pending--;
10296 if (vcpu->arch.nmi_pending)
10297 kvm_make_request(KVM_REQ_EVENT, vcpu);
10300 /* Return total number of NMIs pending injection to the VM */
10301 int kvm_get_nr_pending_nmis(struct kvm_vcpu *vcpu)
10303 return vcpu->arch.nmi_pending +
10304 static_call(kvm_x86_is_vnmi_pending)(vcpu);
10307 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
10308 unsigned long *vcpu_bitmap)
10310 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
10313 void kvm_make_scan_ioapic_request(struct kvm *kvm)
10315 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
10318 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10320 struct kvm_lapic *apic = vcpu->arch.apic;
10323 if (!lapic_in_kernel(vcpu))
10326 down_read(&vcpu->kvm->arch.apicv_update_lock);
10329 /* Do not activate APICV when APIC is disabled */
10330 activate = kvm_vcpu_apicv_activated(vcpu) &&
10331 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED);
10333 if (apic->apicv_active == activate)
10336 apic->apicv_active = activate;
10337 kvm_apic_update_apicv(vcpu);
10338 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
10341 * When APICv gets disabled, we may still have injected interrupts
10342 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10343 * still active when the interrupt got accepted. Make sure
10344 * kvm_check_and_inject_events() is called to check for that.
10346 if (!apic->apicv_active)
10347 kvm_make_request(KVM_REQ_EVENT, vcpu);
10351 up_read(&vcpu->kvm->arch.apicv_update_lock);
10353 EXPORT_SYMBOL_GPL(__kvm_vcpu_update_apicv);
10355 static void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10357 if (!lapic_in_kernel(vcpu))
10361 * Due to sharing page tables across vCPUs, the xAPIC memslot must be
10362 * deleted if any vCPU has xAPIC virtualization and x2APIC enabled, but
10363 * and hardware doesn't support x2APIC virtualization. E.g. some AMD
10364 * CPUs support AVIC but not x2APIC. KVM still allows enabling AVIC in
10365 * this case so that KVM can the AVIC doorbell to inject interrupts to
10366 * running vCPUs, but KVM must not create SPTEs for the APIC base as
10367 * the vCPU would incorrectly be able to access the vAPIC page via MMIO
10368 * despite being in x2APIC mode. For simplicity, inhibiting the APIC
10369 * access page is sticky.
10371 if (apic_x2apic_mode(vcpu->arch.apic) &&
10372 kvm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization)
10373 kvm_inhibit_apic_access_page(vcpu);
10375 __kvm_vcpu_update_apicv(vcpu);
10378 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10379 enum kvm_apicv_inhibit reason, bool set)
10381 unsigned long old, new;
10383 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
10385 if (!(kvm_x86_ops.required_apicv_inhibits & BIT(reason)))
10388 old = new = kvm->arch.apicv_inhibit_reasons;
10390 set_or_clear_apicv_inhibit(&new, reason, set);
10392 if (!!old != !!new) {
10394 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
10395 * false positives in the sanity check WARN in svm_vcpu_run().
10396 * This task will wait for all vCPUs to ack the kick IRQ before
10397 * updating apicv_inhibit_reasons, and all other vCPUs will
10398 * block on acquiring apicv_update_lock so that vCPUs can't
10399 * redo svm_vcpu_run() without seeing the new inhibit state.
10401 * Note, holding apicv_update_lock and taking it in the read
10402 * side (handling the request) also prevents other vCPUs from
10403 * servicing the request with a stale apicv_inhibit_reasons.
10405 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
10406 kvm->arch.apicv_inhibit_reasons = new;
10408 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
10409 int idx = srcu_read_lock(&kvm->srcu);
10411 kvm_zap_gfn_range(kvm, gfn, gfn+1);
10412 srcu_read_unlock(&kvm->srcu, idx);
10415 kvm->arch.apicv_inhibit_reasons = new;
10419 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10420 enum kvm_apicv_inhibit reason, bool set)
10425 down_write(&kvm->arch.apicv_update_lock);
10426 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10427 up_write(&kvm->arch.apicv_update_lock);
10429 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
10431 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
10433 if (!kvm_apic_present(vcpu))
10436 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
10438 if (irqchip_split(vcpu->kvm))
10439 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
10441 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10442 if (ioapic_in_kernel(vcpu->kvm))
10443 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
10446 if (is_guest_mode(vcpu))
10447 vcpu->arch.load_eoi_exitmap_pending = true;
10449 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
10452 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
10454 u64 eoi_exit_bitmap[4];
10456 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
10459 if (to_hv_vcpu(vcpu)) {
10460 bitmap_or((ulong *)eoi_exit_bitmap,
10461 vcpu->arch.ioapic_handled_vectors,
10462 to_hv_synic(vcpu)->vec_bitmap, 256);
10463 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
10467 static_call_cond(kvm_x86_load_eoi_exitmap)(
10468 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
10471 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
10473 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
10476 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
10478 if (!lapic_in_kernel(vcpu))
10481 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
10484 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
10486 smp_send_reschedule(vcpu->cpu);
10488 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
10491 * Called within kvm->srcu read side.
10492 * Returns 1 to let vcpu_run() continue the guest execution loop without
10493 * exiting to the userspace. Otherwise, the value will be returned to the
10496 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
10500 dm_request_for_irq_injection(vcpu) &&
10501 kvm_cpu_accept_dm_intr(vcpu);
10502 fastpath_t exit_fastpath;
10504 bool req_immediate_exit = false;
10506 if (kvm_request_pending(vcpu)) {
10507 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
10512 if (kvm_dirty_ring_check_request(vcpu)) {
10517 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
10518 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
10523 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
10524 kvm_mmu_free_obsolete_roots(vcpu);
10525 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
10526 __kvm_migrate_timers(vcpu);
10527 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
10528 kvm_update_masterclock(vcpu->kvm);
10529 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
10530 kvm_gen_kvmclock_update(vcpu);
10531 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
10532 r = kvm_guest_time_update(vcpu);
10536 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10537 kvm_mmu_sync_roots(vcpu);
10538 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10539 kvm_mmu_load_pgd(vcpu);
10542 * Note, the order matters here, as flushing "all" TLB entries
10543 * also flushes the "current" TLB entries, i.e. servicing the
10544 * flush "all" will clear any request to flush "current".
10546 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
10547 kvm_vcpu_flush_tlb_all(vcpu);
10549 kvm_service_local_tlb_flush_requests(vcpu);
10552 * Fall back to a "full" guest flush if Hyper-V's precise
10553 * flushing fails. Note, Hyper-V's flushing is per-vCPU, but
10554 * the flushes are considered "remote" and not "local" because
10555 * the requests can be initiated from other vCPUs.
10557 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) &&
10558 kvm_hv_vcpu_flush_tlb(vcpu))
10559 kvm_vcpu_flush_tlb_guest(vcpu);
10561 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10562 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10566 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10567 if (is_guest_mode(vcpu))
10568 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10570 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10571 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10572 vcpu->mmio_needed = 0;
10577 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10578 /* Page is swapped out. Do synthetic halt */
10579 vcpu->arch.apf.halted = true;
10583 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10584 record_steal_time(vcpu);
10585 #ifdef CONFIG_KVM_SMM
10586 if (kvm_check_request(KVM_REQ_SMI, vcpu))
10589 if (kvm_check_request(KVM_REQ_NMI, vcpu))
10591 if (kvm_check_request(KVM_REQ_PMU, vcpu))
10592 kvm_pmu_handle_event(vcpu);
10593 if (kvm_check_request(KVM_REQ_PMI, vcpu))
10594 kvm_pmu_deliver_pmi(vcpu);
10595 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10596 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10597 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10598 vcpu->arch.ioapic_handled_vectors)) {
10599 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10600 vcpu->run->eoi.vector =
10601 vcpu->arch.pending_ioapic_eoi;
10606 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10607 vcpu_scan_ioapic(vcpu);
10608 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10609 vcpu_load_eoi_exitmap(vcpu);
10610 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10611 kvm_vcpu_reload_apic_access_page(vcpu);
10612 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10613 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10614 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10615 vcpu->run->system_event.ndata = 0;
10619 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10620 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10621 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10622 vcpu->run->system_event.ndata = 0;
10626 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10627 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10629 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10630 vcpu->run->hyperv = hv_vcpu->exit;
10636 * KVM_REQ_HV_STIMER has to be processed after
10637 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10638 * depend on the guest clock being up-to-date
10640 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10641 kvm_hv_process_stimers(vcpu);
10642 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10643 kvm_vcpu_update_apicv(vcpu);
10644 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10645 kvm_check_async_pf_completion(vcpu);
10646 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10647 static_call(kvm_x86_msr_filter_changed)(vcpu);
10649 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10650 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10653 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10654 kvm_xen_has_interrupt(vcpu)) {
10655 ++vcpu->stat.req_event;
10656 r = kvm_apic_accept_events(vcpu);
10661 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10666 r = kvm_check_and_inject_events(vcpu, &req_immediate_exit);
10672 static_call(kvm_x86_enable_irq_window)(vcpu);
10674 if (kvm_lapic_enabled(vcpu)) {
10675 update_cr8_intercept(vcpu);
10676 kvm_lapic_sync_to_vapic(vcpu);
10680 r = kvm_mmu_reload(vcpu);
10682 goto cancel_injection;
10687 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10690 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10691 * IPI are then delayed after guest entry, which ensures that they
10692 * result in virtual interrupt delivery.
10694 local_irq_disable();
10696 /* Store vcpu->apicv_active before vcpu->mode. */
10697 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10699 kvm_vcpu_srcu_read_unlock(vcpu);
10702 * 1) We should set ->mode before checking ->requests. Please see
10703 * the comment in kvm_vcpu_exiting_guest_mode().
10705 * 2) For APICv, we should set ->mode before checking PID.ON. This
10706 * pairs with the memory barrier implicit in pi_test_and_set_on
10707 * (see vmx_deliver_posted_interrupt).
10709 * 3) This also orders the write to mode from any reads to the page
10710 * tables done while the VCPU is running. Please see the comment
10711 * in kvm_flush_remote_tlbs.
10713 smp_mb__after_srcu_read_unlock();
10716 * Process pending posted interrupts to handle the case where the
10717 * notification IRQ arrived in the host, or was never sent (because the
10718 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10719 * status, KVM doesn't update assigned devices when APICv is inhibited,
10720 * i.e. they can post interrupts even if APICv is temporarily disabled.
10722 if (kvm_lapic_enabled(vcpu))
10723 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10725 if (kvm_vcpu_exit_request(vcpu)) {
10726 vcpu->mode = OUTSIDE_GUEST_MODE;
10728 local_irq_enable();
10730 kvm_vcpu_srcu_read_lock(vcpu);
10732 goto cancel_injection;
10735 if (req_immediate_exit) {
10736 kvm_make_request(KVM_REQ_EVENT, vcpu);
10737 static_call(kvm_x86_request_immediate_exit)(vcpu);
10740 fpregs_assert_state_consistent();
10741 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10742 switch_fpu_return();
10744 if (vcpu->arch.guest_fpu.xfd_err)
10745 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10747 if (unlikely(vcpu->arch.switch_db_regs)) {
10748 set_debugreg(0, 7);
10749 set_debugreg(vcpu->arch.eff_db[0], 0);
10750 set_debugreg(vcpu->arch.eff_db[1], 1);
10751 set_debugreg(vcpu->arch.eff_db[2], 2);
10752 set_debugreg(vcpu->arch.eff_db[3], 3);
10753 } else if (unlikely(hw_breakpoint_active())) {
10754 set_debugreg(0, 7);
10757 guest_timing_enter_irqoff();
10761 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10762 * update must kick and wait for all vCPUs before toggling the
10763 * per-VM state, and responsing vCPUs must wait for the update
10764 * to complete before servicing KVM_REQ_APICV_UPDATE.
10766 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&
10767 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED));
10769 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10770 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10773 if (kvm_lapic_enabled(vcpu))
10774 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10776 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10777 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10781 /* Note, VM-Exits that go down the "slow" path are accounted below. */
10782 ++vcpu->stat.exits;
10786 * Do this here before restoring debug registers on the host. And
10787 * since we do this before handling the vmexit, a DR access vmexit
10788 * can (a) read the correct value of the debug registers, (b) set
10789 * KVM_DEBUGREG_WONT_EXIT again.
10791 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10792 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10793 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10794 kvm_update_dr0123(vcpu);
10795 kvm_update_dr7(vcpu);
10799 * If the guest has used debug registers, at least dr7
10800 * will be disabled while returning to the host.
10801 * If we don't have active breakpoints in the host, we don't
10802 * care about the messed up debug address registers. But if
10803 * we have some of them active, restore the old state.
10805 if (hw_breakpoint_active())
10806 hw_breakpoint_restore();
10808 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10809 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10811 vcpu->mode = OUTSIDE_GUEST_MODE;
10815 * Sync xfd before calling handle_exit_irqoff() which may
10816 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10817 * in #NM irqoff handler).
10819 if (vcpu->arch.xfd_no_write_intercept)
10820 fpu_sync_guest_vmexit_xfd_state();
10822 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10824 if (vcpu->arch.guest_fpu.xfd_err)
10825 wrmsrl(MSR_IA32_XFD_ERR, 0);
10828 * Consume any pending interrupts, including the possible source of
10829 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10830 * An instruction is required after local_irq_enable() to fully unblock
10831 * interrupts on processors that implement an interrupt shadow, the
10832 * stat.exits increment will do nicely.
10834 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10835 local_irq_enable();
10836 ++vcpu->stat.exits;
10837 local_irq_disable();
10838 kvm_after_interrupt(vcpu);
10841 * Wait until after servicing IRQs to account guest time so that any
10842 * ticks that occurred while running the guest are properly accounted
10843 * to the guest. Waiting until IRQs are enabled degrades the accuracy
10844 * of accounting via context tracking, but the loss of accuracy is
10845 * acceptable for all known use cases.
10847 guest_timing_exit_irqoff();
10849 local_irq_enable();
10852 kvm_vcpu_srcu_read_lock(vcpu);
10855 * Profile KVM exit RIPs:
10857 if (unlikely(prof_on == KVM_PROFILING)) {
10858 unsigned long rip = kvm_rip_read(vcpu);
10859 profile_hit(KVM_PROFILING, (void *)rip);
10862 if (unlikely(vcpu->arch.tsc_always_catchup))
10863 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10865 if (vcpu->arch.apic_attention)
10866 kvm_lapic_sync_from_vapic(vcpu);
10868 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10872 if (req_immediate_exit)
10873 kvm_make_request(KVM_REQ_EVENT, vcpu);
10874 static_call(kvm_x86_cancel_injection)(vcpu);
10875 if (unlikely(vcpu->arch.apic_attention))
10876 kvm_lapic_sync_from_vapic(vcpu);
10881 /* Called within kvm->srcu read side. */
10882 static inline int vcpu_block(struct kvm_vcpu *vcpu)
10886 if (!kvm_arch_vcpu_runnable(vcpu)) {
10888 * Switch to the software timer before halt-polling/blocking as
10889 * the guest's timer may be a break event for the vCPU, and the
10890 * hypervisor timer runs only when the CPU is in guest mode.
10891 * Switch before halt-polling so that KVM recognizes an expired
10892 * timer before blocking.
10894 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10896 kvm_lapic_switch_to_sw_timer(vcpu);
10898 kvm_vcpu_srcu_read_unlock(vcpu);
10899 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10900 kvm_vcpu_halt(vcpu);
10902 kvm_vcpu_block(vcpu);
10903 kvm_vcpu_srcu_read_lock(vcpu);
10906 kvm_lapic_switch_to_hv_timer(vcpu);
10909 * If the vCPU is not runnable, a signal or another host event
10910 * of some kind is pending; service it without changing the
10911 * vCPU's activity state.
10913 if (!kvm_arch_vcpu_runnable(vcpu))
10918 * Evaluate nested events before exiting the halted state. This allows
10919 * the halt state to be recorded properly in the VMCS12's activity
10920 * state field (AMD does not have a similar field and a VM-Exit always
10921 * causes a spurious wakeup from HLT).
10923 if (is_guest_mode(vcpu)) {
10924 if (kvm_check_nested_events(vcpu) < 0)
10928 if (kvm_apic_accept_events(vcpu) < 0)
10930 switch(vcpu->arch.mp_state) {
10931 case KVM_MP_STATE_HALTED:
10932 case KVM_MP_STATE_AP_RESET_HOLD:
10933 vcpu->arch.pv.pv_unhalted = false;
10934 vcpu->arch.mp_state =
10935 KVM_MP_STATE_RUNNABLE;
10937 case KVM_MP_STATE_RUNNABLE:
10938 vcpu->arch.apf.halted = false;
10940 case KVM_MP_STATE_INIT_RECEIVED:
10949 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10951 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10952 !vcpu->arch.apf.halted);
10955 /* Called within kvm->srcu read side. */
10956 static int vcpu_run(struct kvm_vcpu *vcpu)
10960 vcpu->arch.l1tf_flush_l1d = true;
10964 * If another guest vCPU requests a PV TLB flush in the middle
10965 * of instruction emulation, the rest of the emulation could
10966 * use a stale page translation. Assume that any code after
10967 * this point can start executing an instruction.
10969 vcpu->arch.at_instruction_boundary = false;
10970 if (kvm_vcpu_running(vcpu)) {
10971 r = vcpu_enter_guest(vcpu);
10973 r = vcpu_block(vcpu);
10979 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
10980 if (kvm_xen_has_pending_events(vcpu))
10981 kvm_xen_inject_pending_events(vcpu);
10983 if (kvm_cpu_has_pending_timer(vcpu))
10984 kvm_inject_pending_timer_irqs(vcpu);
10986 if (dm_request_for_irq_injection(vcpu) &&
10987 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
10989 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
10990 ++vcpu->stat.request_irq_exits;
10994 if (__xfer_to_guest_mode_work_pending()) {
10995 kvm_vcpu_srcu_read_unlock(vcpu);
10996 r = xfer_to_guest_mode_handle_work(vcpu);
10997 kvm_vcpu_srcu_read_lock(vcpu);
11006 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
11008 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
11011 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
11013 BUG_ON(!vcpu->arch.pio.count);
11015 return complete_emulated_io(vcpu);
11019 * Implements the following, as a state machine:
11022 * for each fragment
11023 * for each mmio piece in the fragment
11030 * for each fragment
11031 * for each mmio piece in the fragment
11036 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
11038 struct kvm_run *run = vcpu->run;
11039 struct kvm_mmio_fragment *frag;
11042 BUG_ON(!vcpu->mmio_needed);
11044 /* Complete previous fragment */
11045 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11046 len = min(8u, frag->len);
11047 if (!vcpu->mmio_is_write)
11048 memcpy(frag->data, run->mmio.data, len);
11050 if (frag->len <= 8) {
11051 /* Switch to the next fragment. */
11053 vcpu->mmio_cur_fragment++;
11055 /* Go forward to the next mmio piece. */
11061 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11062 vcpu->mmio_needed = 0;
11064 /* FIXME: return into emulator if single-stepping. */
11065 if (vcpu->mmio_is_write)
11067 vcpu->mmio_read_completed = 1;
11068 return complete_emulated_io(vcpu);
11071 run->exit_reason = KVM_EXIT_MMIO;
11072 run->mmio.phys_addr = frag->gpa;
11073 if (vcpu->mmio_is_write)
11074 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11075 run->mmio.len = min(8u, frag->len);
11076 run->mmio.is_write = vcpu->mmio_is_write;
11077 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
11081 /* Swap (qemu) user FPU context for the guest FPU context. */
11082 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
11084 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
11085 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
11089 /* When vcpu_run ends, restore user space FPU context. */
11090 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
11092 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
11093 ++vcpu->stat.fpu_reload;
11097 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
11099 struct kvm_queued_exception *ex = &vcpu->arch.exception;
11100 struct kvm_run *kvm_run = vcpu->run;
11104 kvm_sigset_activate(vcpu);
11105 kvm_run->flags = 0;
11106 kvm_load_guest_fpu(vcpu);
11108 kvm_vcpu_srcu_read_lock(vcpu);
11109 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
11110 if (kvm_run->immediate_exit) {
11115 * It should be impossible for the hypervisor timer to be in
11116 * use before KVM has ever run the vCPU.
11118 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu));
11120 kvm_vcpu_srcu_read_unlock(vcpu);
11121 kvm_vcpu_block(vcpu);
11122 kvm_vcpu_srcu_read_lock(vcpu);
11124 if (kvm_apic_accept_events(vcpu) < 0) {
11129 if (signal_pending(current)) {
11131 kvm_run->exit_reason = KVM_EXIT_INTR;
11132 ++vcpu->stat.signal_exits;
11137 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
11138 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
11143 if (kvm_run->kvm_dirty_regs) {
11144 r = sync_regs(vcpu);
11149 /* re-sync apic's tpr */
11150 if (!lapic_in_kernel(vcpu)) {
11151 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
11158 * If userspace set a pending exception and L2 is active, convert it to
11159 * a pending VM-Exit if L1 wants to intercept the exception.
11161 if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) &&
11162 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector,
11164 kvm_queue_exception_vmexit(vcpu, ex->vector,
11165 ex->has_error_code, ex->error_code,
11166 ex->has_payload, ex->payload);
11167 ex->injected = false;
11168 ex->pending = false;
11170 vcpu->arch.exception_from_userspace = false;
11172 if (unlikely(vcpu->arch.complete_userspace_io)) {
11173 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
11174 vcpu->arch.complete_userspace_io = NULL;
11179 WARN_ON_ONCE(vcpu->arch.pio.count);
11180 WARN_ON_ONCE(vcpu->mmio_needed);
11183 if (kvm_run->immediate_exit) {
11188 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
11192 r = vcpu_run(vcpu);
11195 kvm_put_guest_fpu(vcpu);
11196 if (kvm_run->kvm_valid_regs)
11198 post_kvm_run_save(vcpu);
11199 kvm_vcpu_srcu_read_unlock(vcpu);
11201 kvm_sigset_deactivate(vcpu);
11206 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11208 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
11210 * We are here if userspace calls get_regs() in the middle of
11211 * instruction emulation. Registers state needs to be copied
11212 * back from emulation context to vcpu. Userspace shouldn't do
11213 * that usually, but some bad designed PV devices (vmware
11214 * backdoor interface) need this to work
11216 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
11217 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11219 regs->rax = kvm_rax_read(vcpu);
11220 regs->rbx = kvm_rbx_read(vcpu);
11221 regs->rcx = kvm_rcx_read(vcpu);
11222 regs->rdx = kvm_rdx_read(vcpu);
11223 regs->rsi = kvm_rsi_read(vcpu);
11224 regs->rdi = kvm_rdi_read(vcpu);
11225 regs->rsp = kvm_rsp_read(vcpu);
11226 regs->rbp = kvm_rbp_read(vcpu);
11227 #ifdef CONFIG_X86_64
11228 regs->r8 = kvm_r8_read(vcpu);
11229 regs->r9 = kvm_r9_read(vcpu);
11230 regs->r10 = kvm_r10_read(vcpu);
11231 regs->r11 = kvm_r11_read(vcpu);
11232 regs->r12 = kvm_r12_read(vcpu);
11233 regs->r13 = kvm_r13_read(vcpu);
11234 regs->r14 = kvm_r14_read(vcpu);
11235 regs->r15 = kvm_r15_read(vcpu);
11238 regs->rip = kvm_rip_read(vcpu);
11239 regs->rflags = kvm_get_rflags(vcpu);
11242 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11245 __get_regs(vcpu, regs);
11250 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11252 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
11253 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11255 kvm_rax_write(vcpu, regs->rax);
11256 kvm_rbx_write(vcpu, regs->rbx);
11257 kvm_rcx_write(vcpu, regs->rcx);
11258 kvm_rdx_write(vcpu, regs->rdx);
11259 kvm_rsi_write(vcpu, regs->rsi);
11260 kvm_rdi_write(vcpu, regs->rdi);
11261 kvm_rsp_write(vcpu, regs->rsp);
11262 kvm_rbp_write(vcpu, regs->rbp);
11263 #ifdef CONFIG_X86_64
11264 kvm_r8_write(vcpu, regs->r8);
11265 kvm_r9_write(vcpu, regs->r9);
11266 kvm_r10_write(vcpu, regs->r10);
11267 kvm_r11_write(vcpu, regs->r11);
11268 kvm_r12_write(vcpu, regs->r12);
11269 kvm_r13_write(vcpu, regs->r13);
11270 kvm_r14_write(vcpu, regs->r14);
11271 kvm_r15_write(vcpu, regs->r15);
11274 kvm_rip_write(vcpu, regs->rip);
11275 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
11277 vcpu->arch.exception.pending = false;
11278 vcpu->arch.exception_vmexit.pending = false;
11280 kvm_make_request(KVM_REQ_EVENT, vcpu);
11283 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11286 __set_regs(vcpu, regs);
11291 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11293 struct desc_ptr dt;
11295 if (vcpu->arch.guest_state_protected)
11296 goto skip_protected_regs;
11298 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11299 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11300 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11301 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11302 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11303 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11305 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11306 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11308 static_call(kvm_x86_get_idt)(vcpu, &dt);
11309 sregs->idt.limit = dt.size;
11310 sregs->idt.base = dt.address;
11311 static_call(kvm_x86_get_gdt)(vcpu, &dt);
11312 sregs->gdt.limit = dt.size;
11313 sregs->gdt.base = dt.address;
11315 sregs->cr2 = vcpu->arch.cr2;
11316 sregs->cr3 = kvm_read_cr3(vcpu);
11318 skip_protected_regs:
11319 sregs->cr0 = kvm_read_cr0(vcpu);
11320 sregs->cr4 = kvm_read_cr4(vcpu);
11321 sregs->cr8 = kvm_get_cr8(vcpu);
11322 sregs->efer = vcpu->arch.efer;
11323 sregs->apic_base = kvm_get_apic_base(vcpu);
11326 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11328 __get_sregs_common(vcpu, sregs);
11330 if (vcpu->arch.guest_state_protected)
11333 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
11334 set_bit(vcpu->arch.interrupt.nr,
11335 (unsigned long *)sregs->interrupt_bitmap);
11338 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11342 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
11344 if (vcpu->arch.guest_state_protected)
11347 if (is_pae_paging(vcpu)) {
11348 for (i = 0 ; i < 4 ; i++)
11349 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
11350 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
11354 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
11355 struct kvm_sregs *sregs)
11358 __get_sregs(vcpu, sregs);
11363 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
11364 struct kvm_mp_state *mp_state)
11369 if (kvm_mpx_supported())
11370 kvm_load_guest_fpu(vcpu);
11372 r = kvm_apic_accept_events(vcpu);
11377 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
11378 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
11379 vcpu->arch.pv.pv_unhalted)
11380 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
11382 mp_state->mp_state = vcpu->arch.mp_state;
11385 if (kvm_mpx_supported())
11386 kvm_put_guest_fpu(vcpu);
11391 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
11392 struct kvm_mp_state *mp_state)
11398 switch (mp_state->mp_state) {
11399 case KVM_MP_STATE_UNINITIALIZED:
11400 case KVM_MP_STATE_HALTED:
11401 case KVM_MP_STATE_AP_RESET_HOLD:
11402 case KVM_MP_STATE_INIT_RECEIVED:
11403 case KVM_MP_STATE_SIPI_RECEIVED:
11404 if (!lapic_in_kernel(vcpu))
11408 case KVM_MP_STATE_RUNNABLE:
11416 * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow
11417 * forcing the guest into INIT/SIPI if those events are supposed to be
11418 * blocked. KVM prioritizes SMI over INIT, so reject INIT/SIPI state
11419 * if an SMI is pending as well.
11421 if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) &&
11422 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
11423 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
11426 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
11427 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
11428 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
11430 vcpu->arch.mp_state = mp_state->mp_state;
11431 kvm_make_request(KVM_REQ_EVENT, vcpu);
11439 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
11440 int reason, bool has_error_code, u32 error_code)
11442 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
11445 init_emulate_ctxt(vcpu);
11447 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
11448 has_error_code, error_code);
11450 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11451 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11452 vcpu->run->internal.ndata = 0;
11456 kvm_rip_write(vcpu, ctxt->eip);
11457 kvm_set_rflags(vcpu, ctxt->eflags);
11460 EXPORT_SYMBOL_GPL(kvm_task_switch);
11462 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11464 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
11466 * When EFER.LME and CR0.PG are set, the processor is in
11467 * 64-bit mode (though maybe in a 32-bit code segment).
11468 * CR4.PAE and EFER.LMA must be set.
11470 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
11472 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
11476 * Not in 64-bit mode: EFER.LMA is clear and the code
11477 * segment cannot be 64-bit.
11479 if (sregs->efer & EFER_LMA || sregs->cs.l)
11483 return kvm_is_valid_cr4(vcpu, sregs->cr4) &&
11484 kvm_is_valid_cr0(vcpu, sregs->cr0);
11487 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
11488 int *mmu_reset_needed, bool update_pdptrs)
11490 struct msr_data apic_base_msr;
11492 struct desc_ptr dt;
11494 if (!kvm_is_valid_sregs(vcpu, sregs))
11497 apic_base_msr.data = sregs->apic_base;
11498 apic_base_msr.host_initiated = true;
11499 if (kvm_set_apic_base(vcpu, &apic_base_msr))
11502 if (vcpu->arch.guest_state_protected)
11505 dt.size = sregs->idt.limit;
11506 dt.address = sregs->idt.base;
11507 static_call(kvm_x86_set_idt)(vcpu, &dt);
11508 dt.size = sregs->gdt.limit;
11509 dt.address = sregs->gdt.base;
11510 static_call(kvm_x86_set_gdt)(vcpu, &dt);
11512 vcpu->arch.cr2 = sregs->cr2;
11513 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
11514 vcpu->arch.cr3 = sregs->cr3;
11515 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11516 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
11518 kvm_set_cr8(vcpu, sregs->cr8);
11520 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
11521 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
11523 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
11524 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
11525 vcpu->arch.cr0 = sregs->cr0;
11527 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
11528 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
11530 if (update_pdptrs) {
11531 idx = srcu_read_lock(&vcpu->kvm->srcu);
11532 if (is_pae_paging(vcpu)) {
11533 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
11534 *mmu_reset_needed = 1;
11536 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11539 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11540 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11541 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11542 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11543 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11544 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11546 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11547 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11549 update_cr8_intercept(vcpu);
11551 /* Older userspace won't unhalt the vcpu on reset. */
11552 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
11553 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
11554 !is_protmode(vcpu))
11555 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11560 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11562 int pending_vec, max_bits;
11563 int mmu_reset_needed = 0;
11564 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
11569 if (mmu_reset_needed)
11570 kvm_mmu_reset_context(vcpu);
11572 max_bits = KVM_NR_INTERRUPTS;
11573 pending_vec = find_first_bit(
11574 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
11576 if (pending_vec < max_bits) {
11577 kvm_queue_interrupt(vcpu, pending_vec, false);
11578 pr_debug("Set back pending irq %d\n", pending_vec);
11579 kvm_make_request(KVM_REQ_EVENT, vcpu);
11584 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11586 int mmu_reset_needed = 0;
11587 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
11588 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
11589 !(sregs2->efer & EFER_LMA);
11592 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11595 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11598 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11599 &mmu_reset_needed, !valid_pdptrs);
11603 if (valid_pdptrs) {
11604 for (i = 0; i < 4 ; i++)
11605 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11607 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11608 mmu_reset_needed = 1;
11609 vcpu->arch.pdptrs_from_userspace = true;
11611 if (mmu_reset_needed)
11612 kvm_mmu_reset_context(vcpu);
11616 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11617 struct kvm_sregs *sregs)
11622 ret = __set_sregs(vcpu, sregs);
11627 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11630 struct kvm_vcpu *vcpu;
11636 down_write(&kvm->arch.apicv_update_lock);
11638 kvm_for_each_vcpu(i, vcpu, kvm) {
11639 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11644 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11645 up_write(&kvm->arch.apicv_update_lock);
11648 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11649 struct kvm_guest_debug *dbg)
11651 unsigned long rflags;
11654 if (vcpu->arch.guest_state_protected)
11659 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11661 if (kvm_is_exception_pending(vcpu))
11663 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11664 kvm_queue_exception(vcpu, DB_VECTOR);
11666 kvm_queue_exception(vcpu, BP_VECTOR);
11670 * Read rflags as long as potentially injected trace flags are still
11673 rflags = kvm_get_rflags(vcpu);
11675 vcpu->guest_debug = dbg->control;
11676 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11677 vcpu->guest_debug = 0;
11679 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11680 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11681 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11682 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11684 for (i = 0; i < KVM_NR_DB_REGS; i++)
11685 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11687 kvm_update_dr7(vcpu);
11689 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11690 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11693 * Trigger an rflags update that will inject or remove the trace
11696 kvm_set_rflags(vcpu, rflags);
11698 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11700 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11710 * Translate a guest virtual address to a guest physical address.
11712 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11713 struct kvm_translation *tr)
11715 unsigned long vaddr = tr->linear_address;
11721 idx = srcu_read_lock(&vcpu->kvm->srcu);
11722 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11723 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11724 tr->physical_address = gpa;
11725 tr->valid = gpa != INVALID_GPA;
11733 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11735 struct fxregs_state *fxsave;
11737 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11742 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11743 memcpy(fpu->fpr, fxsave->st_space, 128);
11744 fpu->fcw = fxsave->cwd;
11745 fpu->fsw = fxsave->swd;
11746 fpu->ftwx = fxsave->twd;
11747 fpu->last_opcode = fxsave->fop;
11748 fpu->last_ip = fxsave->rip;
11749 fpu->last_dp = fxsave->rdp;
11750 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11756 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11758 struct fxregs_state *fxsave;
11760 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11765 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11767 memcpy(fxsave->st_space, fpu->fpr, 128);
11768 fxsave->cwd = fpu->fcw;
11769 fxsave->swd = fpu->fsw;
11770 fxsave->twd = fpu->ftwx;
11771 fxsave->fop = fpu->last_opcode;
11772 fxsave->rip = fpu->last_ip;
11773 fxsave->rdp = fpu->last_dp;
11774 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11780 static void store_regs(struct kvm_vcpu *vcpu)
11782 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11784 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11785 __get_regs(vcpu, &vcpu->run->s.regs.regs);
11787 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11788 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11790 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11791 kvm_vcpu_ioctl_x86_get_vcpu_events(
11792 vcpu, &vcpu->run->s.regs.events);
11795 static int sync_regs(struct kvm_vcpu *vcpu)
11797 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11798 __set_regs(vcpu, &vcpu->run->s.regs.regs);
11799 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11802 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11803 struct kvm_sregs sregs = vcpu->run->s.regs.sregs;
11805 if (__set_sregs(vcpu, &sregs))
11808 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11811 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11812 struct kvm_vcpu_events events = vcpu->run->s.regs.events;
11814 if (kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events))
11817 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11823 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11825 if (kvm_check_tsc_unstable() && kvm->created_vcpus)
11826 pr_warn_once("SMP vm created on host with unstable TSC; "
11827 "guest TSC will not be reliable\n");
11829 if (!kvm->arch.max_vcpu_ids)
11830 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
11832 if (id >= kvm->arch.max_vcpu_ids)
11835 return static_call(kvm_x86_vcpu_precreate)(kvm);
11838 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11843 vcpu->arch.last_vmentry_cpu = -1;
11844 vcpu->arch.regs_avail = ~0;
11845 vcpu->arch.regs_dirty = ~0;
11847 kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm, vcpu, KVM_HOST_USES_PFN);
11849 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11850 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11852 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11854 r = kvm_mmu_create(vcpu);
11858 if (irqchip_in_kernel(vcpu->kvm)) {
11859 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11861 goto fail_mmu_destroy;
11864 * Defer evaluating inhibits until the vCPU is first run, as
11865 * this vCPU will not get notified of any changes until this
11866 * vCPU is visible to other vCPUs (marked online and added to
11867 * the set of vCPUs). Opportunistically mark APICv active as
11868 * VMX in particularly is highly unlikely to have inhibits.
11869 * Ignore the current per-VM APICv state so that vCPU creation
11870 * is guaranteed to run with a deterministic value, the request
11871 * will ensure the vCPU gets the correct state before VM-Entry.
11873 if (enable_apicv) {
11874 vcpu->arch.apic->apicv_active = true;
11875 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
11878 static_branch_inc(&kvm_has_noapic_vcpu);
11882 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11884 goto fail_free_lapic;
11885 vcpu->arch.pio_data = page_address(page);
11887 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
11888 GFP_KERNEL_ACCOUNT);
11889 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
11890 GFP_KERNEL_ACCOUNT);
11891 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
11892 goto fail_free_mce_banks;
11893 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11895 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11896 GFP_KERNEL_ACCOUNT))
11897 goto fail_free_mce_banks;
11899 if (!alloc_emulate_ctxt(vcpu))
11900 goto free_wbinvd_dirty_mask;
11902 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11903 pr_err("failed to allocate vcpu's fpu\n");
11904 goto free_emulate_ctxt;
11907 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11908 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11910 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11912 kvm_async_pf_hash_reset(vcpu);
11914 vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap;
11915 kvm_pmu_init(vcpu);
11917 vcpu->arch.pending_external_vector = -1;
11918 vcpu->arch.preempted_in_kernel = false;
11920 #if IS_ENABLED(CONFIG_HYPERV)
11921 vcpu->arch.hv_root_tdp = INVALID_PAGE;
11924 r = static_call(kvm_x86_vcpu_create)(vcpu);
11926 goto free_guest_fpu;
11928 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11929 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11930 kvm_xen_init_vcpu(vcpu);
11931 kvm_vcpu_mtrr_init(vcpu);
11933 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
11934 kvm_vcpu_reset(vcpu, false);
11935 kvm_init_mmu(vcpu);
11940 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11942 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11943 free_wbinvd_dirty_mask:
11944 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11945 fail_free_mce_banks:
11946 kfree(vcpu->arch.mce_banks);
11947 kfree(vcpu->arch.mci_ctl2_banks);
11948 free_page((unsigned long)vcpu->arch.pio_data);
11950 kvm_free_lapic(vcpu);
11952 kvm_mmu_destroy(vcpu);
11956 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11958 struct kvm *kvm = vcpu->kvm;
11960 if (mutex_lock_killable(&vcpu->mutex))
11963 kvm_synchronize_tsc(vcpu, 0);
11966 /* poll control enabled by default */
11967 vcpu->arch.msr_kvm_poll_control = 1;
11969 mutex_unlock(&vcpu->mutex);
11971 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11972 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
11973 KVMCLOCK_SYNC_PERIOD);
11976 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
11980 kvmclock_reset(vcpu);
11982 static_call(kvm_x86_vcpu_free)(vcpu);
11984 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11985 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11986 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11988 kvm_xen_destroy_vcpu(vcpu);
11989 kvm_hv_vcpu_uninit(vcpu);
11990 kvm_pmu_destroy(vcpu);
11991 kfree(vcpu->arch.mce_banks);
11992 kfree(vcpu->arch.mci_ctl2_banks);
11993 kvm_free_lapic(vcpu);
11994 idx = srcu_read_lock(&vcpu->kvm->srcu);
11995 kvm_mmu_destroy(vcpu);
11996 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11997 free_page((unsigned long)vcpu->arch.pio_data);
11998 kvfree(vcpu->arch.cpuid_entries);
11999 if (!lapic_in_kernel(vcpu))
12000 static_branch_dec(&kvm_has_noapic_vcpu);
12003 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
12005 struct kvm_cpuid_entry2 *cpuid_0x1;
12006 unsigned long old_cr0 = kvm_read_cr0(vcpu);
12007 unsigned long new_cr0;
12010 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
12011 * to handle side effects. RESET emulation hits those flows and relies
12012 * on emulated/virtualized registers, including those that are loaded
12013 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
12014 * to detect improper or missing initialization.
12016 WARN_ON_ONCE(!init_event &&
12017 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
12020 * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's
12021 * possible to INIT the vCPU while L2 is active. Force the vCPU back
12022 * into L1 as EFER.SVME is cleared on INIT (along with all other EFER
12023 * bits), i.e. virtualization is disabled.
12025 if (is_guest_mode(vcpu))
12026 kvm_leave_nested(vcpu);
12028 kvm_lapic_reset(vcpu, init_event);
12030 WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu));
12031 vcpu->arch.hflags = 0;
12033 vcpu->arch.smi_pending = 0;
12034 vcpu->arch.smi_count = 0;
12035 atomic_set(&vcpu->arch.nmi_queued, 0);
12036 vcpu->arch.nmi_pending = 0;
12037 vcpu->arch.nmi_injected = false;
12038 kvm_clear_interrupt_queue(vcpu);
12039 kvm_clear_exception_queue(vcpu);
12041 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
12042 kvm_update_dr0123(vcpu);
12043 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
12044 vcpu->arch.dr7 = DR7_FIXED_1;
12045 kvm_update_dr7(vcpu);
12047 vcpu->arch.cr2 = 0;
12049 kvm_make_request(KVM_REQ_EVENT, vcpu);
12050 vcpu->arch.apf.msr_en_val = 0;
12051 vcpu->arch.apf.msr_int_val = 0;
12052 vcpu->arch.st.msr_val = 0;
12054 kvmclock_reset(vcpu);
12056 kvm_clear_async_pf_completion_queue(vcpu);
12057 kvm_async_pf_hash_reset(vcpu);
12058 vcpu->arch.apf.halted = false;
12060 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
12061 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
12064 * All paths that lead to INIT are required to load the guest's
12065 * FPU state (because most paths are buried in KVM_RUN).
12068 kvm_put_guest_fpu(vcpu);
12070 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
12071 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
12074 kvm_load_guest_fpu(vcpu);
12078 kvm_pmu_reset(vcpu);
12079 vcpu->arch.smbase = 0x30000;
12081 vcpu->arch.msr_misc_features_enables = 0;
12082 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
12083 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
12085 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
12086 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
12089 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
12090 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
12091 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
12094 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
12095 * if no CPUID match is found. Note, it's impossible to get a match at
12096 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
12097 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
12098 * on RESET. But, go through the motions in case that's ever remedied.
12100 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1);
12101 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
12103 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
12105 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
12106 kvm_rip_write(vcpu, 0xfff0);
12108 vcpu->arch.cr3 = 0;
12109 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
12112 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
12113 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
12114 * (or qualify) that with a footnote stating that CD/NW are preserved.
12116 new_cr0 = X86_CR0_ET;
12118 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
12120 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
12122 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
12123 static_call(kvm_x86_set_cr4)(vcpu, 0);
12124 static_call(kvm_x86_set_efer)(vcpu, 0);
12125 static_call(kvm_x86_update_exception_bitmap)(vcpu);
12128 * On the standard CR0/CR4/EFER modification paths, there are several
12129 * complex conditions determining whether the MMU has to be reset and/or
12130 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
12131 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
12132 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
12133 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
12135 if (old_cr0 & X86_CR0_PG) {
12136 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12137 kvm_mmu_reset_context(vcpu);
12141 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
12142 * APM states the TLBs are untouched by INIT, but it also states that
12143 * the TLBs are flushed on "External initialization of the processor."
12144 * Flush the guest TLB regardless of vendor, there is no meaningful
12145 * benefit in relying on the guest to flush the TLB immediately after
12146 * INIT. A spurious TLB flush is benign and likely negligible from a
12147 * performance perspective.
12150 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12152 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
12154 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
12156 struct kvm_segment cs;
12158 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
12159 cs.selector = vector << 8;
12160 cs.base = vector << 12;
12161 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
12162 kvm_rip_write(vcpu, 0);
12164 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
12166 int kvm_arch_hardware_enable(void)
12169 struct kvm_vcpu *vcpu;
12174 bool stable, backwards_tsc = false;
12176 kvm_user_return_msr_cpu_online();
12178 ret = kvm_x86_check_processor_compatibility();
12182 ret = static_call(kvm_x86_hardware_enable)();
12186 local_tsc = rdtsc();
12187 stable = !kvm_check_tsc_unstable();
12188 list_for_each_entry(kvm, &vm_list, vm_list) {
12189 kvm_for_each_vcpu(i, vcpu, kvm) {
12190 if (!stable && vcpu->cpu == smp_processor_id())
12191 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
12192 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
12193 backwards_tsc = true;
12194 if (vcpu->arch.last_host_tsc > max_tsc)
12195 max_tsc = vcpu->arch.last_host_tsc;
12201 * Sometimes, even reliable TSCs go backwards. This happens on
12202 * platforms that reset TSC during suspend or hibernate actions, but
12203 * maintain synchronization. We must compensate. Fortunately, we can
12204 * detect that condition here, which happens early in CPU bringup,
12205 * before any KVM threads can be running. Unfortunately, we can't
12206 * bring the TSCs fully up to date with real time, as we aren't yet far
12207 * enough into CPU bringup that we know how much real time has actually
12208 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
12209 * variables that haven't been updated yet.
12211 * So we simply find the maximum observed TSC above, then record the
12212 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
12213 * the adjustment will be applied. Note that we accumulate
12214 * adjustments, in case multiple suspend cycles happen before some VCPU
12215 * gets a chance to run again. In the event that no KVM threads get a
12216 * chance to run, we will miss the entire elapsed period, as we'll have
12217 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
12218 * loose cycle time. This isn't too big a deal, since the loss will be
12219 * uniform across all VCPUs (not to mention the scenario is extremely
12220 * unlikely). It is possible that a second hibernate recovery happens
12221 * much faster than a first, causing the observed TSC here to be
12222 * smaller; this would require additional padding adjustment, which is
12223 * why we set last_host_tsc to the local tsc observed here.
12225 * N.B. - this code below runs only on platforms with reliable TSC,
12226 * as that is the only way backwards_tsc is set above. Also note
12227 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
12228 * have the same delta_cyc adjustment applied if backwards_tsc
12229 * is detected. Note further, this adjustment is only done once,
12230 * as we reset last_host_tsc on all VCPUs to stop this from being
12231 * called multiple times (one for each physical CPU bringup).
12233 * Platforms with unreliable TSCs don't have to deal with this, they
12234 * will be compensated by the logic in vcpu_load, which sets the TSC to
12235 * catchup mode. This will catchup all VCPUs to real time, but cannot
12236 * guarantee that they stay in perfect synchronization.
12238 if (backwards_tsc) {
12239 u64 delta_cyc = max_tsc - local_tsc;
12240 list_for_each_entry(kvm, &vm_list, vm_list) {
12241 kvm->arch.backwards_tsc_observed = true;
12242 kvm_for_each_vcpu(i, vcpu, kvm) {
12243 vcpu->arch.tsc_offset_adjustment += delta_cyc;
12244 vcpu->arch.last_host_tsc = local_tsc;
12245 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
12249 * We have to disable TSC offset matching.. if you were
12250 * booting a VM while issuing an S4 host suspend....
12251 * you may have some problem. Solving this issue is
12252 * left as an exercise to the reader.
12254 kvm->arch.last_tsc_nsec = 0;
12255 kvm->arch.last_tsc_write = 0;
12262 void kvm_arch_hardware_disable(void)
12264 static_call(kvm_x86_hardware_disable)();
12265 drop_user_return_notifiers();
12268 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
12270 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
12273 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
12275 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
12278 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
12279 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
12281 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
12283 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
12285 vcpu->arch.l1tf_flush_l1d = true;
12286 if (pmu->version && unlikely(pmu->event_count)) {
12287 pmu->need_cleanup = true;
12288 kvm_make_request(KVM_REQ_PMU, vcpu);
12290 static_call(kvm_x86_sched_in)(vcpu, cpu);
12293 void kvm_arch_free_vm(struct kvm *kvm)
12295 kfree(to_kvm_hv(kvm)->hv_pa_pg);
12296 __kvm_arch_free_vm(kvm);
12300 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
12303 unsigned long flags;
12308 ret = kvm_page_track_init(kvm);
12312 ret = kvm_mmu_init_vm(kvm);
12314 goto out_page_track;
12316 ret = static_call(kvm_x86_vm_init)(kvm);
12318 goto out_uninit_mmu;
12320 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
12321 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
12322 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
12324 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
12325 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
12326 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
12327 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
12328 &kvm->arch.irq_sources_bitmap);
12330 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
12331 mutex_init(&kvm->arch.apic_map_lock);
12332 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
12333 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
12335 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
12336 pvclock_update_vm_gtod_copy(kvm);
12337 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
12339 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
12340 kvm->arch.guest_can_read_msr_platform_info = true;
12341 kvm->arch.enable_pmu = enable_pmu;
12343 #if IS_ENABLED(CONFIG_HYPERV)
12344 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
12345 kvm->arch.hv_root_tdp = INVALID_PAGE;
12348 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
12349 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
12351 kvm_apicv_init(kvm);
12352 kvm_hv_init_vm(kvm);
12353 kvm_xen_init_vm(kvm);
12358 kvm_mmu_uninit_vm(kvm);
12360 kvm_page_track_cleanup(kvm);
12365 int kvm_arch_post_init_vm(struct kvm *kvm)
12367 return kvm_mmu_post_init_vm(kvm);
12370 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
12373 kvm_mmu_unload(vcpu);
12377 static void kvm_unload_vcpu_mmus(struct kvm *kvm)
12380 struct kvm_vcpu *vcpu;
12382 kvm_for_each_vcpu(i, vcpu, kvm) {
12383 kvm_clear_async_pf_completion_queue(vcpu);
12384 kvm_unload_vcpu_mmu(vcpu);
12388 void kvm_arch_sync_events(struct kvm *kvm)
12390 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
12391 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
12396 * __x86_set_memory_region: Setup KVM internal memory slot
12398 * @kvm: the kvm pointer to the VM.
12399 * @id: the slot ID to setup.
12400 * @gpa: the GPA to install the slot (unused when @size == 0).
12401 * @size: the size of the slot. Set to zero to uninstall a slot.
12403 * This function helps to setup a KVM internal memory slot. Specify
12404 * @size > 0 to install a new slot, while @size == 0 to uninstall a
12405 * slot. The return code can be one of the following:
12407 * HVA: on success (uninstall will return a bogus HVA)
12410 * The caller should always use IS_ERR() to check the return value
12411 * before use. Note, the KVM internal memory slots are guaranteed to
12412 * remain valid and unchanged until the VM is destroyed, i.e., the
12413 * GPA->HVA translation will not change. However, the HVA is a user
12414 * address, i.e. its accessibility is not guaranteed, and must be
12415 * accessed via __copy_{to,from}_user().
12417 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
12421 unsigned long hva, old_npages;
12422 struct kvm_memslots *slots = kvm_memslots(kvm);
12423 struct kvm_memory_slot *slot;
12425 /* Called with kvm->slots_lock held. */
12426 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
12427 return ERR_PTR_USR(-EINVAL);
12429 slot = id_to_memslot(slots, id);
12431 if (slot && slot->npages)
12432 return ERR_PTR_USR(-EEXIST);
12435 * MAP_SHARED to prevent internal slot pages from being moved
12438 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
12439 MAP_SHARED | MAP_ANONYMOUS, 0);
12440 if (IS_ERR_VALUE(hva))
12441 return (void __user *)hva;
12443 if (!slot || !slot->npages)
12446 old_npages = slot->npages;
12447 hva = slot->userspace_addr;
12450 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
12451 struct kvm_userspace_memory_region m;
12453 m.slot = id | (i << 16);
12455 m.guest_phys_addr = gpa;
12456 m.userspace_addr = hva;
12457 m.memory_size = size;
12458 r = __kvm_set_memory_region(kvm, &m);
12460 return ERR_PTR_USR(r);
12464 vm_munmap(hva, old_npages * PAGE_SIZE);
12466 return (void __user *)hva;
12468 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
12470 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
12472 kvm_mmu_pre_destroy_vm(kvm);
12475 void kvm_arch_destroy_vm(struct kvm *kvm)
12477 if (current->mm == kvm->mm) {
12479 * Free memory regions allocated on behalf of userspace,
12480 * unless the memory map has changed due to process exit
12483 mutex_lock(&kvm->slots_lock);
12484 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
12486 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
12488 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
12489 mutex_unlock(&kvm->slots_lock);
12491 kvm_unload_vcpu_mmus(kvm);
12492 static_call_cond(kvm_x86_vm_destroy)(kvm);
12493 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
12494 kvm_pic_destroy(kvm);
12495 kvm_ioapic_destroy(kvm);
12496 kvm_destroy_vcpus(kvm);
12497 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
12498 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
12499 kvm_mmu_uninit_vm(kvm);
12500 kvm_page_track_cleanup(kvm);
12501 kvm_xen_destroy_vm(kvm);
12502 kvm_hv_destroy_vm(kvm);
12505 static void memslot_rmap_free(struct kvm_memory_slot *slot)
12509 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12510 kvfree(slot->arch.rmap[i]);
12511 slot->arch.rmap[i] = NULL;
12515 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
12519 memslot_rmap_free(slot);
12521 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12522 kvfree(slot->arch.lpage_info[i - 1]);
12523 slot->arch.lpage_info[i - 1] = NULL;
12526 kvm_page_track_free_memslot(slot);
12529 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
12531 const int sz = sizeof(*slot->arch.rmap[0]);
12534 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12536 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12538 if (slot->arch.rmap[i])
12541 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
12542 if (!slot->arch.rmap[i]) {
12543 memslot_rmap_free(slot);
12551 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
12552 struct kvm_memory_slot *slot)
12554 unsigned long npages = slot->npages;
12558 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
12559 * old arrays will be freed by __kvm_set_memory_region() if installing
12560 * the new memslot is successful.
12562 memset(&slot->arch, 0, sizeof(slot->arch));
12564 if (kvm_memslots_have_rmaps(kvm)) {
12565 r = memslot_rmap_alloc(slot, npages);
12570 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12571 struct kvm_lpage_info *linfo;
12572 unsigned long ugfn;
12576 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12578 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
12582 slot->arch.lpage_info[i - 1] = linfo;
12584 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12585 linfo[0].disallow_lpage = 1;
12586 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12587 linfo[lpages - 1].disallow_lpage = 1;
12588 ugfn = slot->userspace_addr >> PAGE_SHIFT;
12590 * If the gfn and userspace address are not aligned wrt each
12591 * other, disable large page support for this slot.
12593 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12596 for (j = 0; j < lpages; ++j)
12597 linfo[j].disallow_lpage = 1;
12601 if (kvm_page_track_create_memslot(kvm, slot, npages))
12607 memslot_rmap_free(slot);
12609 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12610 kvfree(slot->arch.lpage_info[i - 1]);
12611 slot->arch.lpage_info[i - 1] = NULL;
12616 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12618 struct kvm_vcpu *vcpu;
12622 * memslots->generation has been incremented.
12623 * mmio generation may have reached its maximum value.
12625 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12627 /* Force re-initialization of steal_time cache */
12628 kvm_for_each_vcpu(i, vcpu, kvm)
12629 kvm_vcpu_kick(vcpu);
12632 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12633 const struct kvm_memory_slot *old,
12634 struct kvm_memory_slot *new,
12635 enum kvm_mr_change change)
12637 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
12638 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
12641 return kvm_alloc_memslot_metadata(kvm, new);
12644 if (change == KVM_MR_FLAGS_ONLY)
12645 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12646 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12653 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12657 if (!kvm_x86_ops.cpu_dirty_log_size)
12660 nr_slots = atomic_read(&kvm->nr_memslots_dirty_logging);
12661 if ((enable && nr_slots == 1) || !nr_slots)
12662 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12665 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12666 struct kvm_memory_slot *old,
12667 const struct kvm_memory_slot *new,
12668 enum kvm_mr_change change)
12670 u32 old_flags = old ? old->flags : 0;
12671 u32 new_flags = new ? new->flags : 0;
12672 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12675 * Update CPU dirty logging if dirty logging is being toggled. This
12676 * applies to all operations.
12678 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12679 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12682 * Nothing more to do for RO slots (which can't be dirtied and can't be
12683 * made writable) or CREATE/MOVE/DELETE of a slot.
12685 * For a memslot with dirty logging disabled:
12686 * CREATE: No dirty mappings will already exist.
12687 * MOVE/DELETE: The old mappings will already have been cleaned up by
12688 * kvm_arch_flush_shadow_memslot()
12690 * For a memslot with dirty logging enabled:
12691 * CREATE: No shadow pages exist, thus nothing to write-protect
12692 * and no dirty bits to clear.
12693 * MOVE/DELETE: The old mappings will already have been cleaned up by
12694 * kvm_arch_flush_shadow_memslot().
12696 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12700 * READONLY and non-flags changes were filtered out above, and the only
12701 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12702 * logging isn't being toggled on or off.
12704 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12707 if (!log_dirty_pages) {
12709 * Dirty logging tracks sptes in 4k granularity, meaning that
12710 * large sptes have to be split. If live migration succeeds,
12711 * the guest in the source machine will be destroyed and large
12712 * sptes will be created in the destination. However, if the
12713 * guest continues to run in the source machine (for example if
12714 * live migration fails), small sptes will remain around and
12715 * cause bad performance.
12717 * Scan sptes if dirty logging has been stopped, dropping those
12718 * which can be collapsed into a single large-page spte. Later
12719 * page faults will create the large-page sptes.
12721 kvm_mmu_zap_collapsible_sptes(kvm, new);
12724 * Initially-all-set does not require write protecting any page,
12725 * because they're all assumed to be dirty.
12727 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12730 if (READ_ONCE(eager_page_split))
12731 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12733 if (kvm_x86_ops.cpu_dirty_log_size) {
12734 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12735 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12737 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12741 * Unconditionally flush the TLBs after enabling dirty logging.
12742 * A flush is almost always going to be necessary (see below),
12743 * and unconditionally flushing allows the helpers to omit
12744 * the subtly complex checks when removing write access.
12746 * Do the flush outside of mmu_lock to reduce the amount of
12747 * time mmu_lock is held. Flushing after dropping mmu_lock is
12748 * safe as KVM only needs to guarantee the slot is fully
12749 * write-protected before returning to userspace, i.e. before
12750 * userspace can consume the dirty status.
12752 * Flushing outside of mmu_lock requires KVM to be careful when
12753 * making decisions based on writable status of an SPTE, e.g. a
12754 * !writable SPTE doesn't guarantee a CPU can't perform writes.
12756 * Specifically, KVM also write-protects guest page tables to
12757 * monitor changes when using shadow paging, and must guarantee
12758 * no CPUs can write to those page before mmu_lock is dropped.
12759 * Because CPUs may have stale TLB entries at this point, a
12760 * !writable SPTE doesn't guarantee CPUs can't perform writes.
12762 * KVM also allows making SPTES writable outside of mmu_lock,
12763 * e.g. to allow dirty logging without taking mmu_lock.
12765 * To handle these scenarios, KVM uses a separate software-only
12766 * bit (MMU-writable) to track if a SPTE is !writable due to
12767 * a guest page table being write-protected (KVM clears the
12768 * MMU-writable flag when write-protecting for shadow paging).
12770 * The use of MMU-writable is also the primary motivation for
12771 * the unconditional flush. Because KVM must guarantee that a
12772 * CPU doesn't contain stale, writable TLB entries for a
12773 * !MMU-writable SPTE, KVM must flush if it encounters any
12774 * MMU-writable SPTE regardless of whether the actual hardware
12775 * writable bit was set. I.e. KVM is almost guaranteed to need
12776 * to flush, while unconditionally flushing allows the "remove
12777 * write access" helpers to ignore MMU-writable entirely.
12779 * See is_writable_pte() for more details (the case involving
12780 * access-tracked SPTEs is particularly relevant).
12782 kvm_flush_remote_tlbs_memslot(kvm, new);
12786 void kvm_arch_commit_memory_region(struct kvm *kvm,
12787 struct kvm_memory_slot *old,
12788 const struct kvm_memory_slot *new,
12789 enum kvm_mr_change change)
12791 if (!kvm->arch.n_requested_mmu_pages &&
12792 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12793 unsigned long nr_mmu_pages;
12795 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12796 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12797 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12800 kvm_mmu_slot_apply_flags(kvm, old, new, change);
12802 /* Free the arrays associated with the old memslot. */
12803 if (change == KVM_MR_MOVE)
12804 kvm_arch_free_memslot(kvm, old);
12807 void kvm_arch_flush_shadow_all(struct kvm *kvm)
12809 kvm_mmu_zap_all(kvm);
12812 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
12813 struct kvm_memory_slot *slot)
12815 kvm_page_track_flush_slot(kvm, slot);
12818 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12820 return (is_guest_mode(vcpu) &&
12821 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12824 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12826 if (!list_empty_careful(&vcpu->async_pf.done))
12829 if (kvm_apic_has_pending_init_or_sipi(vcpu) &&
12830 kvm_apic_init_sipi_allowed(vcpu))
12833 if (vcpu->arch.pv.pv_unhalted)
12836 if (kvm_is_exception_pending(vcpu))
12839 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12840 (vcpu->arch.nmi_pending &&
12841 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12844 #ifdef CONFIG_KVM_SMM
12845 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12846 (vcpu->arch.smi_pending &&
12847 static_call(kvm_x86_smi_allowed)(vcpu, false)))
12851 if (kvm_arch_interrupt_allowed(vcpu) &&
12852 (kvm_cpu_has_interrupt(vcpu) ||
12853 kvm_guest_apic_has_interrupt(vcpu)))
12856 if (kvm_hv_has_stimer_pending(vcpu))
12859 if (is_guest_mode(vcpu) &&
12860 kvm_x86_ops.nested_ops->has_events &&
12861 kvm_x86_ops.nested_ops->has_events(vcpu))
12864 if (kvm_xen_has_pending_events(vcpu))
12870 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12872 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12875 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12877 if (kvm_vcpu_apicv_active(vcpu) &&
12878 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12884 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12886 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12889 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12890 #ifdef CONFIG_KVM_SMM
12891 kvm_test_request(KVM_REQ_SMI, vcpu) ||
12893 kvm_test_request(KVM_REQ_EVENT, vcpu))
12896 return kvm_arch_dy_has_pending_interrupt(vcpu);
12899 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
12901 if (vcpu->arch.guest_state_protected)
12904 return vcpu->arch.preempted_in_kernel;
12907 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
12909 return kvm_rip_read(vcpu);
12912 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
12914 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
12917 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
12919 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
12922 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
12924 /* Can't read the RIP when guest state is protected, just return 0 */
12925 if (vcpu->arch.guest_state_protected)
12928 if (is_64_bit_mode(vcpu))
12929 return kvm_rip_read(vcpu);
12930 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
12931 kvm_rip_read(vcpu));
12933 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
12935 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
12937 return kvm_get_linear_rip(vcpu) == linear_rip;
12939 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
12941 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
12943 unsigned long rflags;
12945 rflags = static_call(kvm_x86_get_rflags)(vcpu);
12946 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12947 rflags &= ~X86_EFLAGS_TF;
12950 EXPORT_SYMBOL_GPL(kvm_get_rflags);
12952 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12954 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
12955 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
12956 rflags |= X86_EFLAGS_TF;
12957 static_call(kvm_x86_set_rflags)(vcpu, rflags);
12960 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12962 __kvm_set_rflags(vcpu, rflags);
12963 kvm_make_request(KVM_REQ_EVENT, vcpu);
12965 EXPORT_SYMBOL_GPL(kvm_set_rflags);
12967 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
12969 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
12971 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
12974 static inline u32 kvm_async_pf_next_probe(u32 key)
12976 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
12979 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12981 u32 key = kvm_async_pf_hash_fn(gfn);
12983 while (vcpu->arch.apf.gfns[key] != ~0)
12984 key = kvm_async_pf_next_probe(key);
12986 vcpu->arch.apf.gfns[key] = gfn;
12989 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
12992 u32 key = kvm_async_pf_hash_fn(gfn);
12994 for (i = 0; i < ASYNC_PF_PER_VCPU &&
12995 (vcpu->arch.apf.gfns[key] != gfn &&
12996 vcpu->arch.apf.gfns[key] != ~0); i++)
12997 key = kvm_async_pf_next_probe(key);
13002 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13004 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
13007 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13011 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
13013 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
13017 vcpu->arch.apf.gfns[i] = ~0;
13019 j = kvm_async_pf_next_probe(j);
13020 if (vcpu->arch.apf.gfns[j] == ~0)
13022 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
13024 * k lies cyclically in ]i,j]
13026 * |....j i.k.| or |.k..j i...|
13028 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
13029 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
13034 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
13036 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
13038 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
13042 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
13044 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13046 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13047 &token, offset, sizeof(token));
13050 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
13052 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13055 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13056 &val, offset, sizeof(val)))
13062 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
13065 if (!kvm_pv_async_pf_enabled(vcpu))
13068 if (vcpu->arch.apf.send_user_only &&
13069 static_call(kvm_x86_get_cpl)(vcpu) == 0)
13072 if (is_guest_mode(vcpu)) {
13074 * L1 needs to opt into the special #PF vmexits that are
13075 * used to deliver async page faults.
13077 return vcpu->arch.apf.delivery_as_pf_vmexit;
13080 * Play it safe in case the guest temporarily disables paging.
13081 * The real mode IDT in particular is unlikely to have a #PF
13084 return is_paging(vcpu);
13088 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
13090 if (unlikely(!lapic_in_kernel(vcpu) ||
13091 kvm_event_needs_reinjection(vcpu) ||
13092 kvm_is_exception_pending(vcpu)))
13095 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
13099 * If interrupts are off we cannot even use an artificial
13102 return kvm_arch_interrupt_allowed(vcpu);
13105 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
13106 struct kvm_async_pf *work)
13108 struct x86_exception fault;
13110 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
13111 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
13113 if (kvm_can_deliver_async_pf(vcpu) &&
13114 !apf_put_user_notpresent(vcpu)) {
13115 fault.vector = PF_VECTOR;
13116 fault.error_code_valid = true;
13117 fault.error_code = 0;
13118 fault.nested_page_fault = false;
13119 fault.address = work->arch.token;
13120 fault.async_page_fault = true;
13121 kvm_inject_page_fault(vcpu, &fault);
13125 * It is not possible to deliver a paravirtualized asynchronous
13126 * page fault, but putting the guest in an artificial halt state
13127 * can be beneficial nevertheless: if an interrupt arrives, we
13128 * can deliver it timely and perhaps the guest will schedule
13129 * another process. When the instruction that triggered a page
13130 * fault is retried, hopefully the page will be ready in the host.
13132 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
13137 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
13138 struct kvm_async_pf *work)
13140 struct kvm_lapic_irq irq = {
13141 .delivery_mode = APIC_DM_FIXED,
13142 .vector = vcpu->arch.apf.vec
13145 if (work->wakeup_all)
13146 work->arch.token = ~0; /* broadcast wakeup */
13148 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
13149 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
13151 if ((work->wakeup_all || work->notpresent_injected) &&
13152 kvm_pv_async_pf_enabled(vcpu) &&
13153 !apf_put_user_ready(vcpu, work->arch.token)) {
13154 vcpu->arch.apf.pageready_pending = true;
13155 kvm_apic_set_irq(vcpu, &irq, NULL);
13158 vcpu->arch.apf.halted = false;
13159 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13162 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
13164 kvm_make_request(KVM_REQ_APF_READY, vcpu);
13165 if (!vcpu->arch.apf.pageready_pending)
13166 kvm_vcpu_kick(vcpu);
13169 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
13171 if (!kvm_pv_async_pf_enabled(vcpu))
13174 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
13177 void kvm_arch_start_assignment(struct kvm *kvm)
13179 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
13180 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
13182 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
13184 void kvm_arch_end_assignment(struct kvm *kvm)
13186 atomic_dec(&kvm->arch.assigned_device_count);
13188 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
13190 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm)
13192 return raw_atomic_read(&kvm->arch.assigned_device_count);
13194 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
13196 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
13198 atomic_inc(&kvm->arch.noncoherent_dma_count);
13200 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
13202 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
13204 atomic_dec(&kvm->arch.noncoherent_dma_count);
13206 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
13208 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
13210 return atomic_read(&kvm->arch.noncoherent_dma_count);
13212 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
13214 bool kvm_arch_has_irq_bypass(void)
13216 return enable_apicv && irq_remapping_cap(IRQ_POSTING_CAP);
13219 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
13220 struct irq_bypass_producer *prod)
13222 struct kvm_kernel_irqfd *irqfd =
13223 container_of(cons, struct kvm_kernel_irqfd, consumer);
13226 irqfd->producer = prod;
13227 kvm_arch_start_assignment(irqfd->kvm);
13228 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
13229 prod->irq, irqfd->gsi, 1);
13232 kvm_arch_end_assignment(irqfd->kvm);
13237 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
13238 struct irq_bypass_producer *prod)
13241 struct kvm_kernel_irqfd *irqfd =
13242 container_of(cons, struct kvm_kernel_irqfd, consumer);
13244 WARN_ON(irqfd->producer != prod);
13245 irqfd->producer = NULL;
13248 * When producer of consumer is unregistered, we change back to
13249 * remapped mode, so we can re-use the current implementation
13250 * when the irq is masked/disabled or the consumer side (KVM
13251 * int this case doesn't want to receive the interrupts.
13253 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
13255 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
13256 " fails: %d\n", irqfd->consumer.token, ret);
13258 kvm_arch_end_assignment(irqfd->kvm);
13261 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
13262 uint32_t guest_irq, bool set)
13264 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
13267 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
13268 struct kvm_kernel_irq_routing_entry *new)
13270 if (new->type != KVM_IRQ_ROUTING_MSI)
13273 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
13276 bool kvm_vector_hashing_enabled(void)
13278 return vector_hashing;
13281 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
13283 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
13285 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
13288 int kvm_spec_ctrl_test_value(u64 value)
13291 * test that setting IA32_SPEC_CTRL to given value
13292 * is allowed by the host processor
13296 unsigned long flags;
13299 local_irq_save(flags);
13301 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
13303 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
13306 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
13308 local_irq_restore(flags);
13312 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
13314 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
13316 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
13317 struct x86_exception fault;
13318 u64 access = error_code &
13319 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
13321 if (!(error_code & PFERR_PRESENT_MASK) ||
13322 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) {
13324 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
13325 * tables probably do not match the TLB. Just proceed
13326 * with the error code that the processor gave.
13328 fault.vector = PF_VECTOR;
13329 fault.error_code_valid = true;
13330 fault.error_code = error_code;
13331 fault.nested_page_fault = false;
13332 fault.address = gva;
13333 fault.async_page_fault = false;
13335 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
13337 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
13340 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
13341 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
13342 * indicates whether exit to userspace is needed.
13344 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
13345 struct x86_exception *e)
13347 if (r == X86EMUL_PROPAGATE_FAULT) {
13348 if (KVM_BUG_ON(!e, vcpu->kvm))
13351 kvm_inject_emulated_page_fault(vcpu, e);
13356 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
13357 * while handling a VMX instruction KVM could've handled the request
13358 * correctly by exiting to userspace and performing I/O but there
13359 * doesn't seem to be a real use-case behind such requests, just return
13360 * KVM_EXIT_INTERNAL_ERROR for now.
13362 kvm_prepare_emulation_failure_exit(vcpu);
13366 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
13368 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
13371 struct x86_exception e;
13378 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
13379 if (r != X86EMUL_CONTINUE)
13380 return kvm_handle_memory_failure(vcpu, r, &e);
13382 if (operand.pcid >> 12 != 0) {
13383 kvm_inject_gp(vcpu, 0);
13387 pcid_enabled = kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE);
13390 case INVPCID_TYPE_INDIV_ADDR:
13391 if ((!pcid_enabled && (operand.pcid != 0)) ||
13392 is_noncanonical_address(operand.gla, vcpu)) {
13393 kvm_inject_gp(vcpu, 0);
13396 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
13397 return kvm_skip_emulated_instruction(vcpu);
13399 case INVPCID_TYPE_SINGLE_CTXT:
13400 if (!pcid_enabled && (operand.pcid != 0)) {
13401 kvm_inject_gp(vcpu, 0);
13405 kvm_invalidate_pcid(vcpu, operand.pcid);
13406 return kvm_skip_emulated_instruction(vcpu);
13408 case INVPCID_TYPE_ALL_NON_GLOBAL:
13410 * Currently, KVM doesn't mark global entries in the shadow
13411 * page tables, so a non-global flush just degenerates to a
13412 * global flush. If needed, we could optimize this later by
13413 * keeping track of global entries in shadow page tables.
13417 case INVPCID_TYPE_ALL_INCL_GLOBAL:
13418 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
13419 return kvm_skip_emulated_instruction(vcpu);
13422 kvm_inject_gp(vcpu, 0);
13426 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
13428 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
13430 struct kvm_run *run = vcpu->run;
13431 struct kvm_mmio_fragment *frag;
13434 BUG_ON(!vcpu->mmio_needed);
13436 /* Complete previous fragment */
13437 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
13438 len = min(8u, frag->len);
13439 if (!vcpu->mmio_is_write)
13440 memcpy(frag->data, run->mmio.data, len);
13442 if (frag->len <= 8) {
13443 /* Switch to the next fragment. */
13445 vcpu->mmio_cur_fragment++;
13447 /* Go forward to the next mmio piece. */
13453 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
13454 vcpu->mmio_needed = 0;
13456 // VMG change, at this point, we're always done
13457 // RIP has already been advanced
13461 // More MMIO is needed
13462 run->mmio.phys_addr = frag->gpa;
13463 run->mmio.len = min(8u, frag->len);
13464 run->mmio.is_write = vcpu->mmio_is_write;
13465 if (run->mmio.is_write)
13466 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
13467 run->exit_reason = KVM_EXIT_MMIO;
13469 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13474 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13478 struct kvm_mmio_fragment *frag;
13483 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13484 if (handled == bytes)
13491 /*TODO: Check if need to increment number of frags */
13492 frag = vcpu->mmio_fragments;
13493 vcpu->mmio_nr_fragments = 1;
13498 vcpu->mmio_needed = 1;
13499 vcpu->mmio_cur_fragment = 0;
13501 vcpu->run->mmio.phys_addr = gpa;
13502 vcpu->run->mmio.len = min(8u, frag->len);
13503 vcpu->run->mmio.is_write = 1;
13504 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
13505 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13507 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13511 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
13513 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13517 struct kvm_mmio_fragment *frag;
13522 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13523 if (handled == bytes)
13530 /*TODO: Check if need to increment number of frags */
13531 frag = vcpu->mmio_fragments;
13532 vcpu->mmio_nr_fragments = 1;
13537 vcpu->mmio_needed = 1;
13538 vcpu->mmio_cur_fragment = 0;
13540 vcpu->run->mmio.phys_addr = gpa;
13541 vcpu->run->mmio.len = min(8u, frag->len);
13542 vcpu->run->mmio.is_write = 0;
13543 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13545 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13549 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
13551 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size)
13553 vcpu->arch.sev_pio_count -= count;
13554 vcpu->arch.sev_pio_data += count * size;
13557 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13558 unsigned int port);
13560 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
13562 int size = vcpu->arch.pio.size;
13563 int port = vcpu->arch.pio.port;
13565 vcpu->arch.pio.count = 0;
13566 if (vcpu->arch.sev_pio_count)
13567 return kvm_sev_es_outs(vcpu, size, port);
13571 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13575 unsigned int count =
13576 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13577 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
13579 /* memcpy done already by emulator_pio_out. */
13580 advance_sev_es_emulated_pio(vcpu, count, size);
13584 /* Emulation done by the kernel. */
13585 if (!vcpu->arch.sev_pio_count)
13589 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
13593 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13594 unsigned int port);
13596 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
13598 unsigned count = vcpu->arch.pio.count;
13599 int size = vcpu->arch.pio.size;
13600 int port = vcpu->arch.pio.port;
13602 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
13603 advance_sev_es_emulated_pio(vcpu, count, size);
13604 if (vcpu->arch.sev_pio_count)
13605 return kvm_sev_es_ins(vcpu, size, port);
13609 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13613 unsigned int count =
13614 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13615 if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count))
13618 /* Emulation done by the kernel. */
13619 advance_sev_es_emulated_pio(vcpu, count, size);
13620 if (!vcpu->arch.sev_pio_count)
13624 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13628 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13629 unsigned int port, void *data, unsigned int count,
13632 vcpu->arch.sev_pio_data = data;
13633 vcpu->arch.sev_pio_count = count;
13634 return in ? kvm_sev_es_ins(vcpu, size, port)
13635 : kvm_sev_es_outs(vcpu, size, port);
13637 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13639 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13640 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13641 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13642 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13643 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13644 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13645 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13646 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter);
13647 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13648 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13649 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13650 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13651 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13652 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13653 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13654 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13655 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13656 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13657 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13658 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13659 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13660 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13661 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath);
13662 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell);
13663 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13664 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13665 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13666 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13667 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13669 static int __init kvm_x86_init(void)
13671 kvm_mmu_x86_module_init();
13672 mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible();
13675 module_init(kvm_x86_init);
13677 static void __exit kvm_x86_exit(void)
13680 * If module_init() is implemented, module_exit() must also be
13681 * implemented to allow module unload.
13684 module_exit(kvm_x86_exit);