2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
30 #include "assigned-dev.h"
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
38 #include <linux/vmalloc.h>
39 #include <linux/module.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <trace/events/kvm.h>
58 #define CREATE_TRACE_POINTS
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
71 #define MAX_IO_MSRS 256
72 #define KVM_MAX_MCE_BANKS 32
73 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
75 #define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
84 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
86 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
89 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
92 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
93 static void process_nmi(struct kvm_vcpu *vcpu);
94 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
96 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
97 EXPORT_SYMBOL_GPL(kvm_x86_ops);
99 static bool __read_mostly ignore_msrs = 0;
100 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
102 unsigned int min_timer_period_us = 500;
103 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
105 static bool __read_mostly kvmclock_periodic_sync = true;
106 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
108 bool __read_mostly kvm_has_tsc_control;
109 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
110 u32 __read_mostly kvm_max_guest_tsc_khz;
111 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
112 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114 u64 __read_mostly kvm_max_tsc_scaling_ratio;
115 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
116 static u64 __read_mostly kvm_default_tsc_scaling_ratio;
118 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
119 static u32 __read_mostly tsc_tolerance_ppm = 250;
120 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
122 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
123 unsigned int __read_mostly lapic_timer_advance_ns = 0;
124 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
126 static bool __read_mostly vector_hashing = true;
127 module_param(vector_hashing, bool, S_IRUGO);
129 static bool __read_mostly backwards_tsc_observed = false;
131 #define KVM_NR_SHARED_MSRS 16
133 struct kvm_shared_msrs_global {
135 u32 msrs[KVM_NR_SHARED_MSRS];
138 struct kvm_shared_msrs {
139 struct user_return_notifier urn;
141 struct kvm_shared_msr_values {
144 } values[KVM_NR_SHARED_MSRS];
147 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
148 static struct kvm_shared_msrs __percpu *shared_msrs;
150 struct kvm_stats_debugfs_item debugfs_entries[] = {
151 { "pf_fixed", VCPU_STAT(pf_fixed) },
152 { "pf_guest", VCPU_STAT(pf_guest) },
153 { "tlb_flush", VCPU_STAT(tlb_flush) },
154 { "invlpg", VCPU_STAT(invlpg) },
155 { "exits", VCPU_STAT(exits) },
156 { "io_exits", VCPU_STAT(io_exits) },
157 { "mmio_exits", VCPU_STAT(mmio_exits) },
158 { "signal_exits", VCPU_STAT(signal_exits) },
159 { "irq_window", VCPU_STAT(irq_window_exits) },
160 { "nmi_window", VCPU_STAT(nmi_window_exits) },
161 { "halt_exits", VCPU_STAT(halt_exits) },
162 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
163 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
164 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
165 { "hypercalls", VCPU_STAT(hypercalls) },
166 { "request_irq", VCPU_STAT(request_irq_exits) },
167 { "irq_exits", VCPU_STAT(irq_exits) },
168 { "host_state_reload", VCPU_STAT(host_state_reload) },
169 { "efer_reload", VCPU_STAT(efer_reload) },
170 { "fpu_reload", VCPU_STAT(fpu_reload) },
171 { "insn_emulation", VCPU_STAT(insn_emulation) },
172 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
173 { "irq_injections", VCPU_STAT(irq_injections) },
174 { "nmi_injections", VCPU_STAT(nmi_injections) },
175 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
176 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
177 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
178 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
179 { "mmu_flooded", VM_STAT(mmu_flooded) },
180 { "mmu_recycled", VM_STAT(mmu_recycled) },
181 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
182 { "mmu_unsync", VM_STAT(mmu_unsync) },
183 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
184 { "largepages", VM_STAT(lpages) },
188 u64 __read_mostly host_xcr0;
190 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
192 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
195 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
196 vcpu->arch.apf.gfns[i] = ~0;
199 static void kvm_on_user_return(struct user_return_notifier *urn)
202 struct kvm_shared_msrs *locals
203 = container_of(urn, struct kvm_shared_msrs, urn);
204 struct kvm_shared_msr_values *values;
206 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
207 values = &locals->values[slot];
208 if (values->host != values->curr) {
209 wrmsrl(shared_msrs_global.msrs[slot], values->host);
210 values->curr = values->host;
213 locals->registered = false;
214 user_return_notifier_unregister(urn);
217 static void shared_msr_update(unsigned slot, u32 msr)
220 unsigned int cpu = smp_processor_id();
221 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
223 /* only read, and nobody should modify it at this time,
224 * so don't need lock */
225 if (slot >= shared_msrs_global.nr) {
226 printk(KERN_ERR "kvm: invalid MSR slot!");
229 rdmsrl_safe(msr, &value);
230 smsr->values[slot].host = value;
231 smsr->values[slot].curr = value;
234 void kvm_define_shared_msr(unsigned slot, u32 msr)
236 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
237 shared_msrs_global.msrs[slot] = msr;
238 if (slot >= shared_msrs_global.nr)
239 shared_msrs_global.nr = slot + 1;
241 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
243 static void kvm_shared_msr_cpu_online(void)
247 for (i = 0; i < shared_msrs_global.nr; ++i)
248 shared_msr_update(i, shared_msrs_global.msrs[i]);
251 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
257 if (((value ^ smsr->values[slot].curr) & mask) == 0)
259 smsr->values[slot].curr = value;
260 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
264 if (!smsr->registered) {
265 smsr->urn.on_user_return = kvm_on_user_return;
266 user_return_notifier_register(&smsr->urn);
267 smsr->registered = true;
271 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
273 static void drop_user_return_notifiers(void)
275 unsigned int cpu = smp_processor_id();
276 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
278 if (smsr->registered)
279 kvm_on_user_return(&smsr->urn);
282 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
284 return vcpu->arch.apic_base;
286 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
288 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
290 u64 old_state = vcpu->arch.apic_base &
291 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
292 u64 new_state = msr_info->data &
293 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
294 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
295 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
297 if (!msr_info->host_initiated &&
298 ((msr_info->data & reserved_bits) != 0 ||
299 new_state == X2APIC_ENABLE ||
300 (new_state == MSR_IA32_APICBASE_ENABLE &&
301 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
302 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
306 kvm_lapic_set_base(vcpu, msr_info->data);
309 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
311 asmlinkage __visible void kvm_spurious_fault(void)
313 /* Fault while not rebooting. We want the trace. */
316 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
318 #define EXCPT_BENIGN 0
319 #define EXCPT_CONTRIBUTORY 1
322 static int exception_class(int vector)
332 return EXCPT_CONTRIBUTORY;
339 #define EXCPT_FAULT 0
341 #define EXCPT_ABORT 2
342 #define EXCPT_INTERRUPT 3
344 static int exception_type(int vector)
348 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
349 return EXCPT_INTERRUPT;
353 /* #DB is trap, as instruction watchpoints are handled elsewhere */
354 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
357 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
360 /* Reserved exceptions will result in fault */
364 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
365 unsigned nr, bool has_error, u32 error_code,
371 kvm_make_request(KVM_REQ_EVENT, vcpu);
373 if (!vcpu->arch.exception.pending) {
375 if (has_error && !is_protmode(vcpu))
377 vcpu->arch.exception.pending = true;
378 vcpu->arch.exception.has_error_code = has_error;
379 vcpu->arch.exception.nr = nr;
380 vcpu->arch.exception.error_code = error_code;
381 vcpu->arch.exception.reinject = reinject;
385 /* to check exception */
386 prev_nr = vcpu->arch.exception.nr;
387 if (prev_nr == DF_VECTOR) {
388 /* triple fault -> shutdown */
389 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
392 class1 = exception_class(prev_nr);
393 class2 = exception_class(nr);
394 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
395 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
396 /* generate double fault per SDM Table 5-5 */
397 vcpu->arch.exception.pending = true;
398 vcpu->arch.exception.has_error_code = true;
399 vcpu->arch.exception.nr = DF_VECTOR;
400 vcpu->arch.exception.error_code = 0;
402 /* replace previous exception with a new one in a hope
403 that instruction re-execution will regenerate lost
408 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
410 kvm_multiple_exception(vcpu, nr, false, 0, false);
412 EXPORT_SYMBOL_GPL(kvm_queue_exception);
414 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
416 kvm_multiple_exception(vcpu, nr, false, 0, true);
418 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
420 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
423 kvm_inject_gp(vcpu, 0);
425 kvm_x86_ops->skip_emulated_instruction(vcpu);
427 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
429 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
431 ++vcpu->stat.pf_guest;
432 vcpu->arch.cr2 = fault->address;
433 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
435 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
437 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
439 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
440 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
442 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
444 return fault->nested_page_fault;
447 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
449 atomic_inc(&vcpu->arch.nmi_queued);
450 kvm_make_request(KVM_REQ_NMI, vcpu);
452 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
454 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
456 kvm_multiple_exception(vcpu, nr, true, error_code, false);
458 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
460 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
462 kvm_multiple_exception(vcpu, nr, true, error_code, true);
464 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
467 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
468 * a #GP and return false.
470 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
472 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
474 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
477 EXPORT_SYMBOL_GPL(kvm_require_cpl);
479 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
481 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
484 kvm_queue_exception(vcpu, UD_VECTOR);
487 EXPORT_SYMBOL_GPL(kvm_require_dr);
490 * This function will be used to read from the physical memory of the currently
491 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
492 * can read from guest physical or from the guest's guest physical memory.
494 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
495 gfn_t ngfn, void *data, int offset, int len,
498 struct x86_exception exception;
502 ngpa = gfn_to_gpa(ngfn);
503 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
504 if (real_gfn == UNMAPPED_GVA)
507 real_gfn = gpa_to_gfn(real_gfn);
509 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
511 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
513 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
514 void *data, int offset, int len, u32 access)
516 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
517 data, offset, len, access);
521 * Load the pae pdptrs. Return true is they are all valid.
523 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
525 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
526 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
529 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
531 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
532 offset * sizeof(u64), sizeof(pdpte),
533 PFERR_USER_MASK|PFERR_WRITE_MASK);
538 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
539 if (is_present_gpte(pdpte[i]) &&
541 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
548 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
549 __set_bit(VCPU_EXREG_PDPTR,
550 (unsigned long *)&vcpu->arch.regs_avail);
551 __set_bit(VCPU_EXREG_PDPTR,
552 (unsigned long *)&vcpu->arch.regs_dirty);
557 EXPORT_SYMBOL_GPL(load_pdptrs);
559 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
561 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
567 if (is_long_mode(vcpu) || !is_pae(vcpu))
570 if (!test_bit(VCPU_EXREG_PDPTR,
571 (unsigned long *)&vcpu->arch.regs_avail))
574 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
575 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
576 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
577 PFERR_USER_MASK | PFERR_WRITE_MASK);
580 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
586 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
588 unsigned long old_cr0 = kvm_read_cr0(vcpu);
589 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
594 if (cr0 & 0xffffffff00000000UL)
598 cr0 &= ~CR0_RESERVED_BITS;
600 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
603 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
606 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
608 if ((vcpu->arch.efer & EFER_LME)) {
613 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
618 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
623 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
626 kvm_x86_ops->set_cr0(vcpu, cr0);
628 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
629 kvm_clear_async_pf_completion_queue(vcpu);
630 kvm_async_pf_hash_reset(vcpu);
633 if ((cr0 ^ old_cr0) & update_bits)
634 kvm_mmu_reset_context(vcpu);
636 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
637 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
638 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
639 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
643 EXPORT_SYMBOL_GPL(kvm_set_cr0);
645 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
647 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
649 EXPORT_SYMBOL_GPL(kvm_lmsw);
651 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
653 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
654 !vcpu->guest_xcr0_loaded) {
655 /* kvm_set_xcr() also depends on this */
656 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
657 vcpu->guest_xcr0_loaded = 1;
661 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
663 if (vcpu->guest_xcr0_loaded) {
664 if (vcpu->arch.xcr0 != host_xcr0)
665 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
666 vcpu->guest_xcr0_loaded = 0;
670 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
673 u64 old_xcr0 = vcpu->arch.xcr0;
676 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
677 if (index != XCR_XFEATURE_ENABLED_MASK)
679 if (!(xcr0 & XFEATURE_MASK_FP))
681 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
685 * Do not allow the guest to set bits that we do not support
686 * saving. However, xcr0 bit 0 is always set, even if the
687 * emulated CPU does not support XSAVE (see fx_init).
689 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
690 if (xcr0 & ~valid_bits)
693 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
694 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
697 if (xcr0 & XFEATURE_MASK_AVX512) {
698 if (!(xcr0 & XFEATURE_MASK_YMM))
700 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
703 vcpu->arch.xcr0 = xcr0;
705 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
706 kvm_update_cpuid(vcpu);
710 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
712 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
713 __kvm_set_xcr(vcpu, index, xcr)) {
714 kvm_inject_gp(vcpu, 0);
719 EXPORT_SYMBOL_GPL(kvm_set_xcr);
721 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
723 unsigned long old_cr4 = kvm_read_cr4(vcpu);
724 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
725 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
727 if (cr4 & CR4_RESERVED_BITS)
730 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
733 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
736 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
739 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
742 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
745 if (is_long_mode(vcpu)) {
746 if (!(cr4 & X86_CR4_PAE))
748 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
749 && ((cr4 ^ old_cr4) & pdptr_bits)
750 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
754 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
755 if (!guest_cpuid_has_pcid(vcpu))
758 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
759 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
763 if (kvm_x86_ops->set_cr4(vcpu, cr4))
766 if (((cr4 ^ old_cr4) & pdptr_bits) ||
767 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
768 kvm_mmu_reset_context(vcpu);
770 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
771 kvm_update_cpuid(vcpu);
775 EXPORT_SYMBOL_GPL(kvm_set_cr4);
777 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
780 cr3 &= ~CR3_PCID_INVD;
783 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
784 kvm_mmu_sync_roots(vcpu);
785 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
789 if (is_long_mode(vcpu)) {
790 if (cr3 & CR3_L_MODE_RESERVED_BITS)
792 } else if (is_pae(vcpu) && is_paging(vcpu) &&
793 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
796 vcpu->arch.cr3 = cr3;
797 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
798 kvm_mmu_new_cr3(vcpu);
801 EXPORT_SYMBOL_GPL(kvm_set_cr3);
803 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
805 if (cr8 & CR8_RESERVED_BITS)
807 if (lapic_in_kernel(vcpu))
808 kvm_lapic_set_tpr(vcpu, cr8);
810 vcpu->arch.cr8 = cr8;
813 EXPORT_SYMBOL_GPL(kvm_set_cr8);
815 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
817 if (lapic_in_kernel(vcpu))
818 return kvm_lapic_get_cr8(vcpu);
820 return vcpu->arch.cr8;
822 EXPORT_SYMBOL_GPL(kvm_get_cr8);
824 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
828 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
829 for (i = 0; i < KVM_NR_DB_REGS; i++)
830 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
831 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
835 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
837 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
838 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
841 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
845 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
846 dr7 = vcpu->arch.guest_debug_dr7;
848 dr7 = vcpu->arch.dr7;
849 kvm_x86_ops->set_dr7(vcpu, dr7);
850 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
851 if (dr7 & DR7_BP_EN_MASK)
852 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
855 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
857 u64 fixed = DR6_FIXED_1;
859 if (!guest_cpuid_has_rtm(vcpu))
864 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
868 vcpu->arch.db[dr] = val;
869 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
870 vcpu->arch.eff_db[dr] = val;
875 if (val & 0xffffffff00000000ULL)
877 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
878 kvm_update_dr6(vcpu);
883 if (val & 0xffffffff00000000ULL)
885 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
886 kvm_update_dr7(vcpu);
893 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
895 if (__kvm_set_dr(vcpu, dr, val)) {
896 kvm_inject_gp(vcpu, 0);
901 EXPORT_SYMBOL_GPL(kvm_set_dr);
903 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
907 *val = vcpu->arch.db[dr];
912 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
913 *val = vcpu->arch.dr6;
915 *val = kvm_x86_ops->get_dr6(vcpu);
920 *val = vcpu->arch.dr7;
925 EXPORT_SYMBOL_GPL(kvm_get_dr);
927 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
929 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
933 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
936 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
937 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
940 EXPORT_SYMBOL_GPL(kvm_rdpmc);
943 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
944 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
946 * This list is modified at module load time to reflect the
947 * capabilities of the host cpu. This capabilities test skips MSRs that are
948 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
949 * may depend on host virtualization features rather than host cpu features.
952 static u32 msrs_to_save[] = {
953 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
956 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
958 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
959 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
962 static unsigned num_msrs_to_save;
964 static u32 emulated_msrs[] = {
965 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
966 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
967 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
968 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
969 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
970 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
973 HV_X64_MSR_VP_RUNTIME,
975 HV_X64_MSR_STIMER0_CONFIG,
976 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
980 MSR_IA32_TSCDEADLINE,
981 MSR_IA32_MISC_ENABLE,
987 static unsigned num_emulated_msrs;
989 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
991 if (efer & efer_reserved_bits)
994 if (efer & EFER_FFXSR) {
995 struct kvm_cpuid_entry2 *feat;
997 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
998 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
1002 if (efer & EFER_SVME) {
1003 struct kvm_cpuid_entry2 *feat;
1005 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
1006 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
1012 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1014 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1016 u64 old_efer = vcpu->arch.efer;
1018 if (!kvm_valid_efer(vcpu, efer))
1022 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1026 efer |= vcpu->arch.efer & EFER_LMA;
1028 kvm_x86_ops->set_efer(vcpu, efer);
1030 /* Update reserved bits */
1031 if ((efer ^ old_efer) & EFER_NX)
1032 kvm_mmu_reset_context(vcpu);
1037 void kvm_enable_efer_bits(u64 mask)
1039 efer_reserved_bits &= ~mask;
1041 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1044 * Writes msr value into into the appropriate "register".
1045 * Returns 0 on success, non-0 otherwise.
1046 * Assumes vcpu_load() was already called.
1048 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1050 switch (msr->index) {
1053 case MSR_KERNEL_GS_BASE:
1056 if (is_noncanonical_address(msr->data))
1059 case MSR_IA32_SYSENTER_EIP:
1060 case MSR_IA32_SYSENTER_ESP:
1062 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1063 * non-canonical address is written on Intel but not on
1064 * AMD (which ignores the top 32-bits, because it does
1065 * not implement 64-bit SYSENTER).
1067 * 64-bit code should hence be able to write a non-canonical
1068 * value on AMD. Making the address canonical ensures that
1069 * vmentry does not fail on Intel after writing a non-canonical
1070 * value, and that something deterministic happens if the guest
1071 * invokes 64-bit SYSENTER.
1073 msr->data = get_canonical(msr->data);
1075 return kvm_x86_ops->set_msr(vcpu, msr);
1077 EXPORT_SYMBOL_GPL(kvm_set_msr);
1080 * Adapt set_msr() to msr_io()'s calling convention
1082 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1084 struct msr_data msr;
1088 msr.host_initiated = true;
1089 r = kvm_get_msr(vcpu, &msr);
1097 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1099 struct msr_data msr;
1103 msr.host_initiated = true;
1104 return kvm_set_msr(vcpu, &msr);
1107 #ifdef CONFIG_X86_64
1108 struct pvclock_gtod_data {
1111 struct { /* extract of a clocksource struct */
1123 static struct pvclock_gtod_data pvclock_gtod_data;
1125 static void update_pvclock_gtod(struct timekeeper *tk)
1127 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1130 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1132 write_seqcount_begin(&vdata->seq);
1134 /* copy pvclock gtod data */
1135 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1136 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1137 vdata->clock.mask = tk->tkr_mono.mask;
1138 vdata->clock.mult = tk->tkr_mono.mult;
1139 vdata->clock.shift = tk->tkr_mono.shift;
1141 vdata->boot_ns = boot_ns;
1142 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
1144 write_seqcount_end(&vdata->seq);
1148 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1151 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1152 * vcpu_enter_guest. This function is only called from
1153 * the physical CPU that is running vcpu.
1155 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1158 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1162 struct pvclock_wall_clock wc;
1163 struct timespec boot;
1168 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1173 ++version; /* first time write, random junk */
1177 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1181 * The guest calculates current wall clock time by adding
1182 * system time (updated by kvm_guest_time_update below) to the
1183 * wall clock specified here. guest system time equals host
1184 * system time for us, thus we must fill in host boot time here.
1188 if (kvm->arch.kvmclock_offset) {
1189 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1190 boot = timespec_sub(boot, ts);
1192 wc.sec = boot.tv_sec;
1193 wc.nsec = boot.tv_nsec;
1194 wc.version = version;
1196 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1199 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1202 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1204 do_shl32_div32(dividend, divisor);
1208 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1209 s8 *pshift, u32 *pmultiplier)
1217 scaled64 = scaled_hz;
1218 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1223 tps32 = (uint32_t)tps64;
1224 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1225 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1233 *pmultiplier = div_frac(scaled64, tps32);
1235 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1236 __func__, base_hz, scaled_hz, shift, *pmultiplier);
1239 #ifdef CONFIG_X86_64
1240 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1243 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1244 static unsigned long max_tsc_khz;
1246 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1248 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1249 vcpu->arch.virtual_tsc_shift);
1252 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1254 u64 v = (u64)khz * (1000000 + ppm);
1259 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1263 /* Guest TSC same frequency as host TSC? */
1265 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1269 /* TSC scaling supported? */
1270 if (!kvm_has_tsc_control) {
1271 if (user_tsc_khz > tsc_khz) {
1272 vcpu->arch.tsc_catchup = 1;
1273 vcpu->arch.tsc_always_catchup = 1;
1276 WARN(1, "user requested TSC rate below hardware speed\n");
1281 /* TSC scaling required - calculate ratio */
1282 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1283 user_tsc_khz, tsc_khz);
1285 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1286 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1291 vcpu->arch.tsc_scaling_ratio = ratio;
1295 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1297 u32 thresh_lo, thresh_hi;
1298 int use_scaling = 0;
1300 /* tsc_khz can be zero if TSC calibration fails */
1301 if (user_tsc_khz == 0) {
1302 /* set tsc_scaling_ratio to a safe value */
1303 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1307 /* Compute a scale to convert nanoseconds in TSC cycles */
1308 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1309 &vcpu->arch.virtual_tsc_shift,
1310 &vcpu->arch.virtual_tsc_mult);
1311 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1314 * Compute the variation in TSC rate which is acceptable
1315 * within the range of tolerance and decide if the
1316 * rate being applied is within that bounds of the hardware
1317 * rate. If so, no scaling or compensation need be done.
1319 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1320 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1321 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1322 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1325 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1328 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1330 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1331 vcpu->arch.virtual_tsc_mult,
1332 vcpu->arch.virtual_tsc_shift);
1333 tsc += vcpu->arch.this_tsc_write;
1337 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1339 #ifdef CONFIG_X86_64
1341 struct kvm_arch *ka = &vcpu->kvm->arch;
1342 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1345 atomic_read(&vcpu->kvm->online_vcpus));
1348 * Once the masterclock is enabled, always perform request in
1349 * order to update it.
1351 * In order to enable masterclock, the host clocksource must be TSC
1352 * and the vcpus need to have matched TSCs. When that happens,
1353 * perform request to enable masterclock.
1355 if (ka->use_master_clock ||
1356 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1357 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1359 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1360 atomic_read(&vcpu->kvm->online_vcpus),
1361 ka->use_master_clock, gtod->clock.vclock_mode);
1365 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1367 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1368 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1372 * Multiply tsc by a fixed point number represented by ratio.
1374 * The most significant 64-N bits (mult) of ratio represent the
1375 * integral part of the fixed point number; the remaining N bits
1376 * (frac) represent the fractional part, ie. ratio represents a fixed
1377 * point number (mult + frac * 2^(-N)).
1379 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1381 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1383 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1386 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1389 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1391 if (ratio != kvm_default_tsc_scaling_ratio)
1392 _tsc = __scale_tsc(ratio, tsc);
1396 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1398 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1402 tsc = kvm_scale_tsc(vcpu, rdtsc());
1404 return target_tsc - tsc;
1407 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1409 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1411 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1413 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1415 struct kvm *kvm = vcpu->kvm;
1416 u64 offset, ns, elapsed;
1417 unsigned long flags;
1420 bool already_matched;
1421 u64 data = msr->data;
1423 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1424 offset = kvm_compute_tsc_offset(vcpu, data);
1425 ns = get_kernel_ns();
1426 elapsed = ns - kvm->arch.last_tsc_nsec;
1428 if (vcpu->arch.virtual_tsc_khz) {
1431 /* n.b - signed multiplication and division required */
1432 usdiff = data - kvm->arch.last_tsc_write;
1433 #ifdef CONFIG_X86_64
1434 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1436 /* do_div() only does unsigned */
1437 asm("1: idivl %[divisor]\n"
1438 "2: xor %%edx, %%edx\n"
1439 " movl $0, %[faulted]\n"
1441 ".section .fixup,\"ax\"\n"
1442 "4: movl $1, %[faulted]\n"
1446 _ASM_EXTABLE(1b, 4b)
1448 : "=A"(usdiff), [faulted] "=r" (faulted)
1449 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1452 do_div(elapsed, 1000);
1457 /* idivl overflow => difference is larger than USEC_PER_SEC */
1459 usdiff = USEC_PER_SEC;
1461 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1464 * Special case: TSC write with a small delta (1 second) of virtual
1465 * cycle time against real time is interpreted as an attempt to
1466 * synchronize the CPU.
1468 * For a reliable TSC, we can match TSC offsets, and for an unstable
1469 * TSC, we add elapsed time in this computation. We could let the
1470 * compensation code attempt to catch up if we fall behind, but
1471 * it's better to try to match offsets from the beginning.
1473 if (usdiff < USEC_PER_SEC &&
1474 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1475 if (!check_tsc_unstable()) {
1476 offset = kvm->arch.cur_tsc_offset;
1477 pr_debug("kvm: matched tsc offset for %llu\n", data);
1479 u64 delta = nsec_to_cycles(vcpu, elapsed);
1481 offset = kvm_compute_tsc_offset(vcpu, data);
1482 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1485 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1488 * We split periods of matched TSC writes into generations.
1489 * For each generation, we track the original measured
1490 * nanosecond time, offset, and write, so if TSCs are in
1491 * sync, we can match exact offset, and if not, we can match
1492 * exact software computation in compute_guest_tsc()
1494 * These values are tracked in kvm->arch.cur_xxx variables.
1496 kvm->arch.cur_tsc_generation++;
1497 kvm->arch.cur_tsc_nsec = ns;
1498 kvm->arch.cur_tsc_write = data;
1499 kvm->arch.cur_tsc_offset = offset;
1501 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1502 kvm->arch.cur_tsc_generation, data);
1506 * We also track th most recent recorded KHZ, write and time to
1507 * allow the matching interval to be extended at each write.
1509 kvm->arch.last_tsc_nsec = ns;
1510 kvm->arch.last_tsc_write = data;
1511 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1513 vcpu->arch.last_guest_tsc = data;
1515 /* Keep track of which generation this VCPU has synchronized to */
1516 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1517 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1518 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1520 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1521 update_ia32_tsc_adjust_msr(vcpu, offset);
1522 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1523 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1525 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1527 kvm->arch.nr_vcpus_matched_tsc = 0;
1528 } else if (!already_matched) {
1529 kvm->arch.nr_vcpus_matched_tsc++;
1532 kvm_track_tsc_matching(vcpu);
1533 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1536 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1538 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1541 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1544 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1546 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1547 WARN_ON(adjustment < 0);
1548 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1549 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1552 #ifdef CONFIG_X86_64
1554 static cycle_t read_tsc(void)
1556 cycle_t ret = (cycle_t)rdtsc_ordered();
1557 u64 last = pvclock_gtod_data.clock.cycle_last;
1559 if (likely(ret >= last))
1563 * GCC likes to generate cmov here, but this branch is extremely
1564 * predictable (it's just a function of time and the likely is
1565 * very likely) and there's a data dependence, so force GCC
1566 * to generate a branch instead. I don't barrier() because
1567 * we don't actually need a barrier, and if this function
1568 * ever gets inlined it will generate worse code.
1574 static inline u64 vgettsc(cycle_t *cycle_now)
1577 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1579 *cycle_now = read_tsc();
1581 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1582 return v * gtod->clock.mult;
1585 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1587 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1593 seq = read_seqcount_begin(>od->seq);
1594 mode = gtod->clock.vclock_mode;
1595 ns = gtod->nsec_base;
1596 ns += vgettsc(cycle_now);
1597 ns >>= gtod->clock.shift;
1598 ns += gtod->boot_ns;
1599 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
1605 /* returns true if host is using tsc clocksource */
1606 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1608 /* checked again under seqlock below */
1609 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1612 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1618 * Assuming a stable TSC across physical CPUS, and a stable TSC
1619 * across virtual CPUs, the following condition is possible.
1620 * Each numbered line represents an event visible to both
1621 * CPUs at the next numbered event.
1623 * "timespecX" represents host monotonic time. "tscX" represents
1626 * VCPU0 on CPU0 | VCPU1 on CPU1
1628 * 1. read timespec0,tsc0
1629 * 2. | timespec1 = timespec0 + N
1631 * 3. transition to guest | transition to guest
1632 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1633 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1634 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1636 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1639 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1641 * - 0 < N - M => M < N
1643 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1644 * always the case (the difference between two distinct xtime instances
1645 * might be smaller then the difference between corresponding TSC reads,
1646 * when updating guest vcpus pvclock areas).
1648 * To avoid that problem, do not allow visibility of distinct
1649 * system_timestamp/tsc_timestamp values simultaneously: use a master
1650 * copy of host monotonic time values. Update that master copy
1653 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1657 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1659 #ifdef CONFIG_X86_64
1660 struct kvm_arch *ka = &kvm->arch;
1662 bool host_tsc_clocksource, vcpus_matched;
1664 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1665 atomic_read(&kvm->online_vcpus));
1668 * If the host uses TSC clock, then passthrough TSC as stable
1671 host_tsc_clocksource = kvm_get_time_and_clockread(
1672 &ka->master_kernel_ns,
1673 &ka->master_cycle_now);
1675 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1676 && !backwards_tsc_observed
1677 && !ka->boot_vcpu_runs_old_kvmclock;
1679 if (ka->use_master_clock)
1680 atomic_set(&kvm_guest_has_master_clock, 1);
1682 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1683 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1688 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1690 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1693 static void kvm_gen_update_masterclock(struct kvm *kvm)
1695 #ifdef CONFIG_X86_64
1697 struct kvm_vcpu *vcpu;
1698 struct kvm_arch *ka = &kvm->arch;
1700 spin_lock(&ka->pvclock_gtod_sync_lock);
1701 kvm_make_mclock_inprogress_request(kvm);
1702 /* no guest entries from this point */
1703 pvclock_update_vm_gtod_copy(kvm);
1705 kvm_for_each_vcpu(i, vcpu, kvm)
1706 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1708 /* guest entries allowed */
1709 kvm_for_each_vcpu(i, vcpu, kvm)
1710 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1712 spin_unlock(&ka->pvclock_gtod_sync_lock);
1716 static int kvm_guest_time_update(struct kvm_vcpu *v)
1718 unsigned long flags, tgt_tsc_khz;
1719 struct kvm_vcpu_arch *vcpu = &v->arch;
1720 struct kvm_arch *ka = &v->kvm->arch;
1722 u64 tsc_timestamp, host_tsc;
1723 struct pvclock_vcpu_time_info guest_hv_clock;
1725 bool use_master_clock;
1731 * If the host uses TSC clock, then passthrough TSC as stable
1734 spin_lock(&ka->pvclock_gtod_sync_lock);
1735 use_master_clock = ka->use_master_clock;
1736 if (use_master_clock) {
1737 host_tsc = ka->master_cycle_now;
1738 kernel_ns = ka->master_kernel_ns;
1740 spin_unlock(&ka->pvclock_gtod_sync_lock);
1742 /* Keep irq disabled to prevent changes to the clock */
1743 local_irq_save(flags);
1744 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1745 if (unlikely(tgt_tsc_khz == 0)) {
1746 local_irq_restore(flags);
1747 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1750 if (!use_master_clock) {
1752 kernel_ns = get_kernel_ns();
1755 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
1758 * We may have to catch up the TSC to match elapsed wall clock
1759 * time for two reasons, even if kvmclock is used.
1760 * 1) CPU could have been running below the maximum TSC rate
1761 * 2) Broken TSC compensation resets the base at each VCPU
1762 * entry to avoid unknown leaps of TSC even when running
1763 * again on the same CPU. This may cause apparent elapsed
1764 * time to disappear, and the guest to stand still or run
1767 if (vcpu->tsc_catchup) {
1768 u64 tsc = compute_guest_tsc(v, kernel_ns);
1769 if (tsc > tsc_timestamp) {
1770 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1771 tsc_timestamp = tsc;
1775 local_irq_restore(flags);
1777 if (!vcpu->pv_time_enabled)
1780 if (kvm_has_tsc_control)
1781 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1783 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
1784 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
1785 &vcpu->hv_clock.tsc_shift,
1786 &vcpu->hv_clock.tsc_to_system_mul);
1787 vcpu->hw_tsc_khz = tgt_tsc_khz;
1790 /* With all the info we got, fill in the values */
1791 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1792 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1793 vcpu->last_guest_tsc = tsc_timestamp;
1795 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1796 &guest_hv_clock, sizeof(guest_hv_clock))))
1799 /* This VCPU is paused, but it's legal for a guest to read another
1800 * VCPU's kvmclock, so we really have to follow the specification where
1801 * it says that version is odd if data is being modified, and even after
1804 * Version field updates must be kept separate. This is because
1805 * kvm_write_guest_cached might use a "rep movs" instruction, and
1806 * writes within a string instruction are weakly ordered. So there
1807 * are three writes overall.
1809 * As a small optimization, only write the version field in the first
1810 * and third write. The vcpu->pv_time cache is still valid, because the
1811 * version field is the first in the struct.
1813 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1815 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1816 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1818 sizeof(vcpu->hv_clock.version));
1822 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1823 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1825 if (vcpu->pvclock_set_guest_stopped_request) {
1826 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1827 vcpu->pvclock_set_guest_stopped_request = false;
1830 /* If the host uses TSC clocksource, then it is stable */
1831 if (use_master_clock)
1832 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1834 vcpu->hv_clock.flags = pvclock_flags;
1836 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1838 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1840 sizeof(vcpu->hv_clock));
1844 vcpu->hv_clock.version++;
1845 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1847 sizeof(vcpu->hv_clock.version));
1852 * kvmclock updates which are isolated to a given vcpu, such as
1853 * vcpu->cpu migration, should not allow system_timestamp from
1854 * the rest of the vcpus to remain static. Otherwise ntp frequency
1855 * correction applies to one vcpu's system_timestamp but not
1858 * So in those cases, request a kvmclock update for all vcpus.
1859 * We need to rate-limit these requests though, as they can
1860 * considerably slow guests that have a large number of vcpus.
1861 * The time for a remote vcpu to update its kvmclock is bound
1862 * by the delay we use to rate-limit the updates.
1865 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1867 static void kvmclock_update_fn(struct work_struct *work)
1870 struct delayed_work *dwork = to_delayed_work(work);
1871 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1872 kvmclock_update_work);
1873 struct kvm *kvm = container_of(ka, struct kvm, arch);
1874 struct kvm_vcpu *vcpu;
1876 kvm_for_each_vcpu(i, vcpu, kvm) {
1877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1878 kvm_vcpu_kick(vcpu);
1882 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1884 struct kvm *kvm = v->kvm;
1886 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1887 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1888 KVMCLOCK_UPDATE_DELAY);
1891 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1893 static void kvmclock_sync_fn(struct work_struct *work)
1895 struct delayed_work *dwork = to_delayed_work(work);
1896 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1897 kvmclock_sync_work);
1898 struct kvm *kvm = container_of(ka, struct kvm, arch);
1900 if (!kvmclock_periodic_sync)
1903 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1904 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1905 KVMCLOCK_SYNC_PERIOD);
1908 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1910 u64 mcg_cap = vcpu->arch.mcg_cap;
1911 unsigned bank_num = mcg_cap & 0xff;
1914 case MSR_IA32_MCG_STATUS:
1915 vcpu->arch.mcg_status = data;
1917 case MSR_IA32_MCG_CTL:
1918 if (!(mcg_cap & MCG_CTL_P))
1920 if (data != 0 && data != ~(u64)0)
1922 vcpu->arch.mcg_ctl = data;
1925 if (msr >= MSR_IA32_MC0_CTL &&
1926 msr < MSR_IA32_MCx_CTL(bank_num)) {
1927 u32 offset = msr - MSR_IA32_MC0_CTL;
1928 /* only 0 or all 1s can be written to IA32_MCi_CTL
1929 * some Linux kernels though clear bit 10 in bank 4 to
1930 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1931 * this to avoid an uncatched #GP in the guest
1933 if ((offset & 0x3) == 0 &&
1934 data != 0 && (data | (1 << 10)) != ~(u64)0)
1936 vcpu->arch.mce_banks[offset] = data;
1944 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1946 struct kvm *kvm = vcpu->kvm;
1947 int lm = is_long_mode(vcpu);
1948 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1949 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1950 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1951 : kvm->arch.xen_hvm_config.blob_size_32;
1952 u32 page_num = data & ~PAGE_MASK;
1953 u64 page_addr = data & PAGE_MASK;
1958 if (page_num >= blob_size)
1961 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1966 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
1975 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1977 gpa_t gpa = data & ~0x3f;
1979 /* Bits 2:5 are reserved, Should be zero */
1983 vcpu->arch.apf.msr_val = data;
1985 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1986 kvm_clear_async_pf_completion_queue(vcpu);
1987 kvm_async_pf_hash_reset(vcpu);
1991 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1995 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1996 kvm_async_pf_wakeup_all(vcpu);
2000 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2002 vcpu->arch.pv_time_enabled = false;
2005 static void record_steal_time(struct kvm_vcpu *vcpu)
2007 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2010 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2011 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2014 if (vcpu->arch.st.steal.version & 1)
2015 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2017 vcpu->arch.st.steal.version += 1;
2019 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2020 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2024 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2025 vcpu->arch.st.last_steal;
2026 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2028 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2029 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2033 vcpu->arch.st.steal.version += 1;
2035 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2036 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2039 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2042 u32 msr = msr_info->index;
2043 u64 data = msr_info->data;
2046 case MSR_AMD64_NB_CFG:
2047 case MSR_IA32_UCODE_REV:
2048 case MSR_IA32_UCODE_WRITE:
2049 case MSR_VM_HSAVE_PA:
2050 case MSR_AMD64_PATCH_LOADER:
2051 case MSR_AMD64_BU_CFG2:
2055 return set_efer(vcpu, data);
2057 data &= ~(u64)0x40; /* ignore flush filter disable */
2058 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2059 data &= ~(u64)0x8; /* ignore TLB cache disable */
2060 data &= ~(u64)0x40000; /* ignore Mc status write enable */
2062 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2067 case MSR_FAM10H_MMIO_CONF_BASE:
2069 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2074 case MSR_IA32_DEBUGCTLMSR:
2076 /* We support the non-activated case already */
2078 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2079 /* Values other than LBR and BTF are vendor-specific,
2080 thus reserved and should throw a #GP */
2083 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2086 case 0x200 ... 0x2ff:
2087 return kvm_mtrr_set_msr(vcpu, msr, data);
2088 case MSR_IA32_APICBASE:
2089 return kvm_set_apic_base(vcpu, msr_info);
2090 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2091 return kvm_x2apic_msr_write(vcpu, msr, data);
2092 case MSR_IA32_TSCDEADLINE:
2093 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2095 case MSR_IA32_TSC_ADJUST:
2096 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2097 if (!msr_info->host_initiated) {
2098 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2099 adjust_tsc_offset_guest(vcpu, adj);
2101 vcpu->arch.ia32_tsc_adjust_msr = data;
2104 case MSR_IA32_MISC_ENABLE:
2105 vcpu->arch.ia32_misc_enable_msr = data;
2107 case MSR_IA32_SMBASE:
2108 if (!msr_info->host_initiated)
2110 vcpu->arch.smbase = data;
2112 case MSR_KVM_WALL_CLOCK_NEW:
2113 case MSR_KVM_WALL_CLOCK:
2114 vcpu->kvm->arch.wall_clock = data;
2115 kvm_write_wall_clock(vcpu->kvm, data);
2117 case MSR_KVM_SYSTEM_TIME_NEW:
2118 case MSR_KVM_SYSTEM_TIME: {
2120 struct kvm_arch *ka = &vcpu->kvm->arch;
2122 kvmclock_reset(vcpu);
2124 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2125 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2127 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2128 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2131 ka->boot_vcpu_runs_old_kvmclock = tmp;
2134 vcpu->arch.time = data;
2135 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2137 /* we verify if the enable bit is set... */
2141 gpa_offset = data & ~(PAGE_MASK | 1);
2143 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2144 &vcpu->arch.pv_time, data & ~1ULL,
2145 sizeof(struct pvclock_vcpu_time_info)))
2146 vcpu->arch.pv_time_enabled = false;
2148 vcpu->arch.pv_time_enabled = true;
2152 case MSR_KVM_ASYNC_PF_EN:
2153 if (kvm_pv_enable_async_pf(vcpu, data))
2156 case MSR_KVM_STEAL_TIME:
2158 if (unlikely(!sched_info_on()))
2161 if (data & KVM_STEAL_RESERVED_MASK)
2164 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2165 data & KVM_STEAL_VALID_BITS,
2166 sizeof(struct kvm_steal_time)))
2169 vcpu->arch.st.msr_val = data;
2171 if (!(data & KVM_MSR_ENABLED))
2174 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2177 case MSR_KVM_PV_EOI_EN:
2178 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2182 case MSR_IA32_MCG_CTL:
2183 case MSR_IA32_MCG_STATUS:
2184 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2185 return set_msr_mce(vcpu, msr, data);
2187 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2188 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2189 pr = true; /* fall through */
2190 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2191 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2192 if (kvm_pmu_is_valid_msr(vcpu, msr))
2193 return kvm_pmu_set_msr(vcpu, msr_info);
2195 if (pr || data != 0)
2196 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2197 "0x%x data 0x%llx\n", msr, data);
2199 case MSR_K7_CLK_CTL:
2201 * Ignore all writes to this no longer documented MSR.
2202 * Writes are only relevant for old K7 processors,
2203 * all pre-dating SVM, but a recommended workaround from
2204 * AMD for these chips. It is possible to specify the
2205 * affected processor models on the command line, hence
2206 * the need to ignore the workaround.
2209 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2210 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2211 case HV_X64_MSR_CRASH_CTL:
2212 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2213 return kvm_hv_set_msr_common(vcpu, msr, data,
2214 msr_info->host_initiated);
2215 case MSR_IA32_BBL_CR_CTL3:
2216 /* Drop writes to this legacy MSR -- see rdmsr
2217 * counterpart for further detail.
2219 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2221 case MSR_AMD64_OSVW_ID_LENGTH:
2222 if (!guest_cpuid_has_osvw(vcpu))
2224 vcpu->arch.osvw.length = data;
2226 case MSR_AMD64_OSVW_STATUS:
2227 if (!guest_cpuid_has_osvw(vcpu))
2229 vcpu->arch.osvw.status = data;
2232 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2233 return xen_hvm_config(vcpu, data);
2234 if (kvm_pmu_is_valid_msr(vcpu, msr))
2235 return kvm_pmu_set_msr(vcpu, msr_info);
2237 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2241 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2248 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2252 * Reads an msr value (of 'msr_index') into 'pdata'.
2253 * Returns 0 on success, non-0 otherwise.
2254 * Assumes vcpu_load() was already called.
2256 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2258 return kvm_x86_ops->get_msr(vcpu, msr);
2260 EXPORT_SYMBOL_GPL(kvm_get_msr);
2262 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2265 u64 mcg_cap = vcpu->arch.mcg_cap;
2266 unsigned bank_num = mcg_cap & 0xff;
2269 case MSR_IA32_P5_MC_ADDR:
2270 case MSR_IA32_P5_MC_TYPE:
2273 case MSR_IA32_MCG_CAP:
2274 data = vcpu->arch.mcg_cap;
2276 case MSR_IA32_MCG_CTL:
2277 if (!(mcg_cap & MCG_CTL_P))
2279 data = vcpu->arch.mcg_ctl;
2281 case MSR_IA32_MCG_STATUS:
2282 data = vcpu->arch.mcg_status;
2285 if (msr >= MSR_IA32_MC0_CTL &&
2286 msr < MSR_IA32_MCx_CTL(bank_num)) {
2287 u32 offset = msr - MSR_IA32_MC0_CTL;
2288 data = vcpu->arch.mce_banks[offset];
2297 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2299 switch (msr_info->index) {
2300 case MSR_IA32_PLATFORM_ID:
2301 case MSR_IA32_EBL_CR_POWERON:
2302 case MSR_IA32_DEBUGCTLMSR:
2303 case MSR_IA32_LASTBRANCHFROMIP:
2304 case MSR_IA32_LASTBRANCHTOIP:
2305 case MSR_IA32_LASTINTFROMIP:
2306 case MSR_IA32_LASTINTTOIP:
2308 case MSR_K8_TSEG_ADDR:
2309 case MSR_K8_TSEG_MASK:
2311 case MSR_VM_HSAVE_PA:
2312 case MSR_K8_INT_PENDING_MSG:
2313 case MSR_AMD64_NB_CFG:
2314 case MSR_FAM10H_MMIO_CONF_BASE:
2315 case MSR_AMD64_BU_CFG2:
2318 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2319 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2320 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2321 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2322 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2323 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2326 case MSR_IA32_UCODE_REV:
2327 msr_info->data = 0x100000000ULL;
2330 case 0x200 ... 0x2ff:
2331 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2332 case 0xcd: /* fsb frequency */
2336 * MSR_EBC_FREQUENCY_ID
2337 * Conservative value valid for even the basic CPU models.
2338 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2339 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2340 * and 266MHz for model 3, or 4. Set Core Clock
2341 * Frequency to System Bus Frequency Ratio to 1 (bits
2342 * 31:24) even though these are only valid for CPU
2343 * models > 2, however guests may end up dividing or
2344 * multiplying by zero otherwise.
2346 case MSR_EBC_FREQUENCY_ID:
2347 msr_info->data = 1 << 24;
2349 case MSR_IA32_APICBASE:
2350 msr_info->data = kvm_get_apic_base(vcpu);
2352 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2353 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2355 case MSR_IA32_TSCDEADLINE:
2356 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2358 case MSR_IA32_TSC_ADJUST:
2359 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2361 case MSR_IA32_MISC_ENABLE:
2362 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2364 case MSR_IA32_SMBASE:
2365 if (!msr_info->host_initiated)
2367 msr_info->data = vcpu->arch.smbase;
2369 case MSR_IA32_PERF_STATUS:
2370 /* TSC increment by tick */
2371 msr_info->data = 1000ULL;
2372 /* CPU multiplier */
2373 msr_info->data |= (((uint64_t)4ULL) << 40);
2376 msr_info->data = vcpu->arch.efer;
2378 case MSR_KVM_WALL_CLOCK:
2379 case MSR_KVM_WALL_CLOCK_NEW:
2380 msr_info->data = vcpu->kvm->arch.wall_clock;
2382 case MSR_KVM_SYSTEM_TIME:
2383 case MSR_KVM_SYSTEM_TIME_NEW:
2384 msr_info->data = vcpu->arch.time;
2386 case MSR_KVM_ASYNC_PF_EN:
2387 msr_info->data = vcpu->arch.apf.msr_val;
2389 case MSR_KVM_STEAL_TIME:
2390 msr_info->data = vcpu->arch.st.msr_val;
2392 case MSR_KVM_PV_EOI_EN:
2393 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2395 case MSR_IA32_P5_MC_ADDR:
2396 case MSR_IA32_P5_MC_TYPE:
2397 case MSR_IA32_MCG_CAP:
2398 case MSR_IA32_MCG_CTL:
2399 case MSR_IA32_MCG_STATUS:
2400 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2401 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2402 case MSR_K7_CLK_CTL:
2404 * Provide expected ramp-up count for K7. All other
2405 * are set to zero, indicating minimum divisors for
2408 * This prevents guest kernels on AMD host with CPU
2409 * type 6, model 8 and higher from exploding due to
2410 * the rdmsr failing.
2412 msr_info->data = 0x20000000;
2414 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2415 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2416 case HV_X64_MSR_CRASH_CTL:
2417 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2418 return kvm_hv_get_msr_common(vcpu,
2419 msr_info->index, &msr_info->data);
2421 case MSR_IA32_BBL_CR_CTL3:
2422 /* This legacy MSR exists but isn't fully documented in current
2423 * silicon. It is however accessed by winxp in very narrow
2424 * scenarios where it sets bit #19, itself documented as
2425 * a "reserved" bit. Best effort attempt to source coherent
2426 * read data here should the balance of the register be
2427 * interpreted by the guest:
2429 * L2 cache control register 3: 64GB range, 256KB size,
2430 * enabled, latency 0x1, configured
2432 msr_info->data = 0xbe702111;
2434 case MSR_AMD64_OSVW_ID_LENGTH:
2435 if (!guest_cpuid_has_osvw(vcpu))
2437 msr_info->data = vcpu->arch.osvw.length;
2439 case MSR_AMD64_OSVW_STATUS:
2440 if (!guest_cpuid_has_osvw(vcpu))
2442 msr_info->data = vcpu->arch.osvw.status;
2445 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2446 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2448 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
2451 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2458 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2461 * Read or write a bunch of msrs. All parameters are kernel addresses.
2463 * @return number of msrs set successfully.
2465 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2466 struct kvm_msr_entry *entries,
2467 int (*do_msr)(struct kvm_vcpu *vcpu,
2468 unsigned index, u64 *data))
2472 idx = srcu_read_lock(&vcpu->kvm->srcu);
2473 for (i = 0; i < msrs->nmsrs; ++i)
2474 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2476 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2482 * Read or write a bunch of msrs. Parameters are user addresses.
2484 * @return number of msrs set successfully.
2486 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2487 int (*do_msr)(struct kvm_vcpu *vcpu,
2488 unsigned index, u64 *data),
2491 struct kvm_msrs msrs;
2492 struct kvm_msr_entry *entries;
2497 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2501 if (msrs.nmsrs >= MAX_IO_MSRS)
2504 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2505 entries = memdup_user(user_msrs->entries, size);
2506 if (IS_ERR(entries)) {
2507 r = PTR_ERR(entries);
2511 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2516 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2527 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2532 case KVM_CAP_IRQCHIP:
2534 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2535 case KVM_CAP_SET_TSS_ADDR:
2536 case KVM_CAP_EXT_CPUID:
2537 case KVM_CAP_EXT_EMUL_CPUID:
2538 case KVM_CAP_CLOCKSOURCE:
2540 case KVM_CAP_NOP_IO_DELAY:
2541 case KVM_CAP_MP_STATE:
2542 case KVM_CAP_SYNC_MMU:
2543 case KVM_CAP_USER_NMI:
2544 case KVM_CAP_REINJECT_CONTROL:
2545 case KVM_CAP_IRQ_INJECT_STATUS:
2546 case KVM_CAP_IOEVENTFD:
2547 case KVM_CAP_IOEVENTFD_NO_LENGTH:
2549 case KVM_CAP_PIT_STATE2:
2550 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2551 case KVM_CAP_XEN_HVM:
2552 case KVM_CAP_ADJUST_CLOCK:
2553 case KVM_CAP_VCPU_EVENTS:
2554 case KVM_CAP_HYPERV:
2555 case KVM_CAP_HYPERV_VAPIC:
2556 case KVM_CAP_HYPERV_SPIN:
2557 case KVM_CAP_HYPERV_SYNIC:
2558 case KVM_CAP_PCI_SEGMENT:
2559 case KVM_CAP_DEBUGREGS:
2560 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2562 case KVM_CAP_ASYNC_PF:
2563 case KVM_CAP_GET_TSC_KHZ:
2564 case KVM_CAP_KVMCLOCK_CTRL:
2565 case KVM_CAP_READONLY_MEM:
2566 case KVM_CAP_HYPERV_TIME:
2567 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2568 case KVM_CAP_TSC_DEADLINE_TIMER:
2569 case KVM_CAP_ENABLE_CAP_VM:
2570 case KVM_CAP_DISABLE_QUIRKS:
2571 case KVM_CAP_SET_BOOT_CPU_ID:
2572 case KVM_CAP_SPLIT_IRQCHIP:
2573 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2574 case KVM_CAP_ASSIGN_DEV_IRQ:
2575 case KVM_CAP_PCI_2_3:
2579 case KVM_CAP_X86_SMM:
2580 /* SMBASE is usually relocated above 1M on modern chipsets,
2581 * and SMM handlers might indeed rely on 4G segment limits,
2582 * so do not report SMM to be available if real mode is
2583 * emulated via vm86 mode. Still, do not go to great lengths
2584 * to avoid userspace's usage of the feature, because it is a
2585 * fringe case that is not enabled except via specific settings
2586 * of the module parameters.
2588 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2590 case KVM_CAP_COALESCED_MMIO:
2591 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2594 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2596 case KVM_CAP_NR_VCPUS:
2597 r = KVM_SOFT_MAX_VCPUS;
2599 case KVM_CAP_MAX_VCPUS:
2602 case KVM_CAP_NR_MEMSLOTS:
2603 r = KVM_USER_MEM_SLOTS;
2605 case KVM_CAP_PV_MMU: /* obsolete */
2608 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2610 r = iommu_present(&pci_bus_type);
2614 r = KVM_MAX_MCE_BANKS;
2619 case KVM_CAP_TSC_CONTROL:
2620 r = kvm_has_tsc_control;
2630 long kvm_arch_dev_ioctl(struct file *filp,
2631 unsigned int ioctl, unsigned long arg)
2633 void __user *argp = (void __user *)arg;
2637 case KVM_GET_MSR_INDEX_LIST: {
2638 struct kvm_msr_list __user *user_msr_list = argp;
2639 struct kvm_msr_list msr_list;
2643 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2646 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2647 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2650 if (n < msr_list.nmsrs)
2653 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2654 num_msrs_to_save * sizeof(u32)))
2656 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2658 num_emulated_msrs * sizeof(u32)))
2663 case KVM_GET_SUPPORTED_CPUID:
2664 case KVM_GET_EMULATED_CPUID: {
2665 struct kvm_cpuid2 __user *cpuid_arg = argp;
2666 struct kvm_cpuid2 cpuid;
2669 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2672 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2678 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2683 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2686 mce_cap = KVM_MCE_CAP_SUPPORTED;
2688 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2700 static void wbinvd_ipi(void *garbage)
2705 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2707 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2710 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2712 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2715 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2717 /* Address WBINVD may be executed by guest */
2718 if (need_emulate_wbinvd(vcpu)) {
2719 if (kvm_x86_ops->has_wbinvd_exit())
2720 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2721 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2722 smp_call_function_single(vcpu->cpu,
2723 wbinvd_ipi, NULL, 1);
2726 kvm_x86_ops->vcpu_load(vcpu, cpu);
2728 /* Apply any externally detected TSC adjustments (due to suspend) */
2729 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2730 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2731 vcpu->arch.tsc_offset_adjustment = 0;
2732 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2735 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2736 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2737 rdtsc() - vcpu->arch.last_host_tsc;
2739 mark_tsc_unstable("KVM discovered backwards TSC");
2740 if (check_tsc_unstable()) {
2741 u64 offset = kvm_compute_tsc_offset(vcpu,
2742 vcpu->arch.last_guest_tsc);
2743 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2744 vcpu->arch.tsc_catchup = 1;
2747 * On a host with synchronized TSC, there is no need to update
2748 * kvmclock on vcpu->cpu migration
2750 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2751 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2752 if (vcpu->cpu != cpu)
2753 kvm_migrate_timers(vcpu);
2757 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2760 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2762 kvm_x86_ops->vcpu_put(vcpu);
2763 kvm_put_guest_fpu(vcpu);
2764 vcpu->arch.last_host_tsc = rdtsc();
2767 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2768 struct kvm_lapic_state *s)
2770 if (vcpu->arch.apicv_active)
2771 kvm_x86_ops->sync_pir_to_irr(vcpu);
2773 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2778 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2779 struct kvm_lapic_state *s)
2781 kvm_apic_post_state_restore(vcpu, s);
2782 update_cr8_intercept(vcpu);
2787 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2789 return (!lapic_in_kernel(vcpu) ||
2790 kvm_apic_accept_pic_intr(vcpu));
2794 * if userspace requested an interrupt window, check that the
2795 * interrupt window is open.
2797 * No need to exit to userspace if we already have an interrupt queued.
2799 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2801 return kvm_arch_interrupt_allowed(vcpu) &&
2802 !kvm_cpu_has_interrupt(vcpu) &&
2803 !kvm_event_needs_reinjection(vcpu) &&
2804 kvm_cpu_accept_dm_intr(vcpu);
2807 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2808 struct kvm_interrupt *irq)
2810 if (irq->irq >= KVM_NR_INTERRUPTS)
2813 if (!irqchip_in_kernel(vcpu->kvm)) {
2814 kvm_queue_interrupt(vcpu, irq->irq, false);
2815 kvm_make_request(KVM_REQ_EVENT, vcpu);
2820 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2821 * fail for in-kernel 8259.
2823 if (pic_in_kernel(vcpu->kvm))
2826 if (vcpu->arch.pending_external_vector != -1)
2829 vcpu->arch.pending_external_vector = irq->irq;
2830 kvm_make_request(KVM_REQ_EVENT, vcpu);
2834 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2836 kvm_inject_nmi(vcpu);
2841 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2843 kvm_make_request(KVM_REQ_SMI, vcpu);
2848 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2849 struct kvm_tpr_access_ctl *tac)
2853 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2857 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2861 unsigned bank_num = mcg_cap & 0xff, bank;
2864 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2866 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2869 vcpu->arch.mcg_cap = mcg_cap;
2870 /* Init IA32_MCG_CTL to all 1s */
2871 if (mcg_cap & MCG_CTL_P)
2872 vcpu->arch.mcg_ctl = ~(u64)0;
2873 /* Init IA32_MCi_CTL to all 1s */
2874 for (bank = 0; bank < bank_num; bank++)
2875 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2880 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2881 struct kvm_x86_mce *mce)
2883 u64 mcg_cap = vcpu->arch.mcg_cap;
2884 unsigned bank_num = mcg_cap & 0xff;
2885 u64 *banks = vcpu->arch.mce_banks;
2887 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2890 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2891 * reporting is disabled
2893 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2894 vcpu->arch.mcg_ctl != ~(u64)0)
2896 banks += 4 * mce->bank;
2898 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2899 * reporting is disabled for the bank
2901 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2903 if (mce->status & MCI_STATUS_UC) {
2904 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2905 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2906 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2909 if (banks[1] & MCI_STATUS_VAL)
2910 mce->status |= MCI_STATUS_OVER;
2911 banks[2] = mce->addr;
2912 banks[3] = mce->misc;
2913 vcpu->arch.mcg_status = mce->mcg_status;
2914 banks[1] = mce->status;
2915 kvm_queue_exception(vcpu, MC_VECTOR);
2916 } else if (!(banks[1] & MCI_STATUS_VAL)
2917 || !(banks[1] & MCI_STATUS_UC)) {
2918 if (banks[1] & MCI_STATUS_VAL)
2919 mce->status |= MCI_STATUS_OVER;
2920 banks[2] = mce->addr;
2921 banks[3] = mce->misc;
2922 banks[1] = mce->status;
2924 banks[1] |= MCI_STATUS_OVER;
2928 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2929 struct kvm_vcpu_events *events)
2932 events->exception.injected =
2933 vcpu->arch.exception.pending &&
2934 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2935 events->exception.nr = vcpu->arch.exception.nr;
2936 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2937 events->exception.pad = 0;
2938 events->exception.error_code = vcpu->arch.exception.error_code;
2940 events->interrupt.injected =
2941 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2942 events->interrupt.nr = vcpu->arch.interrupt.nr;
2943 events->interrupt.soft = 0;
2944 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
2946 events->nmi.injected = vcpu->arch.nmi_injected;
2947 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2948 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2949 events->nmi.pad = 0;
2951 events->sipi_vector = 0; /* never valid when reporting to user space */
2953 events->smi.smm = is_smm(vcpu);
2954 events->smi.pending = vcpu->arch.smi_pending;
2955 events->smi.smm_inside_nmi =
2956 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2957 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2959 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2960 | KVM_VCPUEVENT_VALID_SHADOW
2961 | KVM_VCPUEVENT_VALID_SMM);
2962 memset(&events->reserved, 0, sizeof(events->reserved));
2965 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2966 struct kvm_vcpu_events *events)
2968 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2969 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2970 | KVM_VCPUEVENT_VALID_SHADOW
2971 | KVM_VCPUEVENT_VALID_SMM))
2975 vcpu->arch.exception.pending = events->exception.injected;
2976 vcpu->arch.exception.nr = events->exception.nr;
2977 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2978 vcpu->arch.exception.error_code = events->exception.error_code;
2980 vcpu->arch.interrupt.pending = events->interrupt.injected;
2981 vcpu->arch.interrupt.nr = events->interrupt.nr;
2982 vcpu->arch.interrupt.soft = events->interrupt.soft;
2983 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2984 kvm_x86_ops->set_interrupt_shadow(vcpu,
2985 events->interrupt.shadow);
2987 vcpu->arch.nmi_injected = events->nmi.injected;
2988 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2989 vcpu->arch.nmi_pending = events->nmi.pending;
2990 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2992 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2993 lapic_in_kernel(vcpu))
2994 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2996 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2997 if (events->smi.smm)
2998 vcpu->arch.hflags |= HF_SMM_MASK;
3000 vcpu->arch.hflags &= ~HF_SMM_MASK;
3001 vcpu->arch.smi_pending = events->smi.pending;
3002 if (events->smi.smm_inside_nmi)
3003 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3005 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3006 if (lapic_in_kernel(vcpu)) {
3007 if (events->smi.latched_init)
3008 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3010 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3014 kvm_make_request(KVM_REQ_EVENT, vcpu);
3019 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3020 struct kvm_debugregs *dbgregs)
3024 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3025 kvm_get_dr(vcpu, 6, &val);
3027 dbgregs->dr7 = vcpu->arch.dr7;
3029 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3032 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3033 struct kvm_debugregs *dbgregs)
3038 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3039 kvm_update_dr0123(vcpu);
3040 vcpu->arch.dr6 = dbgregs->dr6;
3041 kvm_update_dr6(vcpu);
3042 vcpu->arch.dr7 = dbgregs->dr7;
3043 kvm_update_dr7(vcpu);
3048 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3050 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3052 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3053 u64 xstate_bv = xsave->header.xfeatures;
3057 * Copy legacy XSAVE area, to avoid complications with CPUID
3058 * leaves 0 and 1 in the loop below.
3060 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3063 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3066 * Copy each region from the possibly compacted offset to the
3067 * non-compacted offset.
3069 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3071 u64 feature = valid & -valid;
3072 int index = fls64(feature) - 1;
3073 void *src = get_xsave_addr(xsave, feature);
3076 u32 size, offset, ecx, edx;
3077 cpuid_count(XSTATE_CPUID, index,
3078 &size, &offset, &ecx, &edx);
3079 memcpy(dest + offset, src, size);
3086 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3088 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
3089 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3093 * Copy legacy XSAVE area, to avoid complications with CPUID
3094 * leaves 0 and 1 in the loop below.
3096 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3098 /* Set XSTATE_BV and possibly XCOMP_BV. */
3099 xsave->header.xfeatures = xstate_bv;
3101 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3104 * Copy each region from the non-compacted offset to the
3105 * possibly compacted offset.
3107 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
3109 u64 feature = valid & -valid;
3110 int index = fls64(feature) - 1;
3111 void *dest = get_xsave_addr(xsave, feature);
3114 u32 size, offset, ecx, edx;
3115 cpuid_count(XSTATE_CPUID, index,
3116 &size, &offset, &ecx, &edx);
3117 memcpy(dest, src + offset, size);
3124 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3125 struct kvm_xsave *guest_xsave)
3127 if (cpu_has_xsave) {
3128 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3129 fill_xsave((u8 *) guest_xsave->region, vcpu);
3131 memcpy(guest_xsave->region,
3132 &vcpu->arch.guest_fpu.state.fxsave,
3133 sizeof(struct fxregs_state));
3134 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3135 XFEATURE_MASK_FPSSE;
3139 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3140 struct kvm_xsave *guest_xsave)
3143 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3145 if (cpu_has_xsave) {
3147 * Here we allow setting states that are not present in
3148 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3149 * with old userspace.
3151 if (xstate_bv & ~kvm_supported_xcr0())
3153 load_xsave(vcpu, (u8 *)guest_xsave->region);
3155 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
3157 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
3158 guest_xsave->region, sizeof(struct fxregs_state));
3163 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3164 struct kvm_xcrs *guest_xcrs)
3166 if (!cpu_has_xsave) {
3167 guest_xcrs->nr_xcrs = 0;
3171 guest_xcrs->nr_xcrs = 1;
3172 guest_xcrs->flags = 0;
3173 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3174 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3177 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3178 struct kvm_xcrs *guest_xcrs)
3185 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3188 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3189 /* Only support XCR0 currently */
3190 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3191 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3192 guest_xcrs->xcrs[i].value);
3201 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3202 * stopped by the hypervisor. This function will be called from the host only.
3203 * EINVAL is returned when the host attempts to set the flag for a guest that
3204 * does not support pv clocks.
3206 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3208 if (!vcpu->arch.pv_time_enabled)
3210 vcpu->arch.pvclock_set_guest_stopped_request = true;
3211 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3215 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3216 struct kvm_enable_cap *cap)
3222 case KVM_CAP_HYPERV_SYNIC:
3223 return kvm_hv_activate_synic(vcpu);
3229 long kvm_arch_vcpu_ioctl(struct file *filp,
3230 unsigned int ioctl, unsigned long arg)
3232 struct kvm_vcpu *vcpu = filp->private_data;
3233 void __user *argp = (void __user *)arg;
3236 struct kvm_lapic_state *lapic;
3237 struct kvm_xsave *xsave;
3238 struct kvm_xcrs *xcrs;
3244 case KVM_GET_LAPIC: {
3246 if (!lapic_in_kernel(vcpu))
3248 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3253 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3257 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3262 case KVM_SET_LAPIC: {
3264 if (!lapic_in_kernel(vcpu))
3266 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3267 if (IS_ERR(u.lapic))
3268 return PTR_ERR(u.lapic);
3270 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3273 case KVM_INTERRUPT: {
3274 struct kvm_interrupt irq;
3277 if (copy_from_user(&irq, argp, sizeof irq))
3279 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3283 r = kvm_vcpu_ioctl_nmi(vcpu);
3287 r = kvm_vcpu_ioctl_smi(vcpu);
3290 case KVM_SET_CPUID: {
3291 struct kvm_cpuid __user *cpuid_arg = argp;
3292 struct kvm_cpuid cpuid;
3295 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3297 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3300 case KVM_SET_CPUID2: {
3301 struct kvm_cpuid2 __user *cpuid_arg = argp;
3302 struct kvm_cpuid2 cpuid;
3305 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3307 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3308 cpuid_arg->entries);
3311 case KVM_GET_CPUID2: {
3312 struct kvm_cpuid2 __user *cpuid_arg = argp;
3313 struct kvm_cpuid2 cpuid;
3316 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3318 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3319 cpuid_arg->entries);
3323 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3329 r = msr_io(vcpu, argp, do_get_msr, 1);
3332 r = msr_io(vcpu, argp, do_set_msr, 0);
3334 case KVM_TPR_ACCESS_REPORTING: {
3335 struct kvm_tpr_access_ctl tac;
3338 if (copy_from_user(&tac, argp, sizeof tac))
3340 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3344 if (copy_to_user(argp, &tac, sizeof tac))
3349 case KVM_SET_VAPIC_ADDR: {
3350 struct kvm_vapic_addr va;
3353 if (!lapic_in_kernel(vcpu))
3356 if (copy_from_user(&va, argp, sizeof va))
3358 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3361 case KVM_X86_SETUP_MCE: {
3365 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3367 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3370 case KVM_X86_SET_MCE: {
3371 struct kvm_x86_mce mce;
3374 if (copy_from_user(&mce, argp, sizeof mce))
3376 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3379 case KVM_GET_VCPU_EVENTS: {
3380 struct kvm_vcpu_events events;
3382 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3385 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3390 case KVM_SET_VCPU_EVENTS: {
3391 struct kvm_vcpu_events events;
3394 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3397 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3400 case KVM_GET_DEBUGREGS: {
3401 struct kvm_debugregs dbgregs;
3403 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3406 if (copy_to_user(argp, &dbgregs,
3407 sizeof(struct kvm_debugregs)))
3412 case KVM_SET_DEBUGREGS: {
3413 struct kvm_debugregs dbgregs;
3416 if (copy_from_user(&dbgregs, argp,
3417 sizeof(struct kvm_debugregs)))
3420 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3423 case KVM_GET_XSAVE: {
3424 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3429 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3432 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3437 case KVM_SET_XSAVE: {
3438 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3439 if (IS_ERR(u.xsave))
3440 return PTR_ERR(u.xsave);
3442 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3445 case KVM_GET_XCRS: {
3446 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3451 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3454 if (copy_to_user(argp, u.xcrs,
3455 sizeof(struct kvm_xcrs)))
3460 case KVM_SET_XCRS: {
3461 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3463 return PTR_ERR(u.xcrs);
3465 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3468 case KVM_SET_TSC_KHZ: {
3472 user_tsc_khz = (u32)arg;
3474 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3477 if (user_tsc_khz == 0)
3478 user_tsc_khz = tsc_khz;
3480 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3485 case KVM_GET_TSC_KHZ: {
3486 r = vcpu->arch.virtual_tsc_khz;
3489 case KVM_KVMCLOCK_CTRL: {
3490 r = kvm_set_guest_paused(vcpu);
3493 case KVM_ENABLE_CAP: {
3494 struct kvm_enable_cap cap;
3497 if (copy_from_user(&cap, argp, sizeof(cap)))
3499 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3510 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3512 return VM_FAULT_SIGBUS;
3515 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3519 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3521 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3525 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3528 kvm->arch.ept_identity_map_addr = ident_addr;
3532 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3533 u32 kvm_nr_mmu_pages)
3535 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3538 mutex_lock(&kvm->slots_lock);
3540 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3541 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3543 mutex_unlock(&kvm->slots_lock);
3547 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3549 return kvm->arch.n_max_mmu_pages;
3552 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3557 switch (chip->chip_id) {
3558 case KVM_IRQCHIP_PIC_MASTER:
3559 memcpy(&chip->chip.pic,
3560 &pic_irqchip(kvm)->pics[0],
3561 sizeof(struct kvm_pic_state));
3563 case KVM_IRQCHIP_PIC_SLAVE:
3564 memcpy(&chip->chip.pic,
3565 &pic_irqchip(kvm)->pics[1],
3566 sizeof(struct kvm_pic_state));
3568 case KVM_IRQCHIP_IOAPIC:
3569 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3578 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3583 switch (chip->chip_id) {
3584 case KVM_IRQCHIP_PIC_MASTER:
3585 spin_lock(&pic_irqchip(kvm)->lock);
3586 memcpy(&pic_irqchip(kvm)->pics[0],
3588 sizeof(struct kvm_pic_state));
3589 spin_unlock(&pic_irqchip(kvm)->lock);
3591 case KVM_IRQCHIP_PIC_SLAVE:
3592 spin_lock(&pic_irqchip(kvm)->lock);
3593 memcpy(&pic_irqchip(kvm)->pics[1],
3595 sizeof(struct kvm_pic_state));
3596 spin_unlock(&pic_irqchip(kvm)->lock);
3598 case KVM_IRQCHIP_IOAPIC:
3599 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3605 kvm_pic_update_irq(pic_irqchip(kvm));
3609 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3611 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3613 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3615 mutex_lock(&kps->lock);
3616 memcpy(ps, &kps->channels, sizeof(*ps));
3617 mutex_unlock(&kps->lock);
3621 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3624 struct kvm_pit *pit = kvm->arch.vpit;
3626 mutex_lock(&pit->pit_state.lock);
3627 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
3628 for (i = 0; i < 3; i++)
3629 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3630 mutex_unlock(&pit->pit_state.lock);
3634 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3636 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3637 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3638 sizeof(ps->channels));
3639 ps->flags = kvm->arch.vpit->pit_state.flags;
3640 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3641 memset(&ps->reserved, 0, sizeof(ps->reserved));
3645 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3649 u32 prev_legacy, cur_legacy;
3650 struct kvm_pit *pit = kvm->arch.vpit;
3652 mutex_lock(&pit->pit_state.lock);
3653 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3654 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3655 if (!prev_legacy && cur_legacy)
3657 memcpy(&pit->pit_state.channels, &ps->channels,
3658 sizeof(pit->pit_state.channels));
3659 pit->pit_state.flags = ps->flags;
3660 for (i = 0; i < 3; i++)
3661 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
3663 mutex_unlock(&pit->pit_state.lock);
3667 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3668 struct kvm_reinject_control *control)
3670 struct kvm_pit *pit = kvm->arch.vpit;
3675 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3676 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3677 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3679 mutex_lock(&pit->pit_state.lock);
3680 kvm_pit_set_reinject(pit, control->pit_reinject);
3681 mutex_unlock(&pit->pit_state.lock);
3687 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3688 * @kvm: kvm instance
3689 * @log: slot id and address to which we copy the log
3691 * Steps 1-4 below provide general overview of dirty page logging. See
3692 * kvm_get_dirty_log_protect() function description for additional details.
3694 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3695 * always flush the TLB (step 4) even if previous step failed and the dirty
3696 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3697 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3698 * writes will be marked dirty for next log read.
3700 * 1. Take a snapshot of the bit and clear it if needed.
3701 * 2. Write protect the corresponding page.
3702 * 3. Copy the snapshot to the userspace.
3703 * 4. Flush TLB's if needed.
3705 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3707 bool is_dirty = false;
3710 mutex_lock(&kvm->slots_lock);
3713 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3715 if (kvm_x86_ops->flush_log_dirty)
3716 kvm_x86_ops->flush_log_dirty(kvm);
3718 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3721 * All the TLBs can be flushed out of mmu lock, see the comments in
3722 * kvm_mmu_slot_remove_write_access().
3724 lockdep_assert_held(&kvm->slots_lock);
3726 kvm_flush_remote_tlbs(kvm);
3728 mutex_unlock(&kvm->slots_lock);
3732 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3735 if (!irqchip_in_kernel(kvm))
3738 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3739 irq_event->irq, irq_event->level,
3744 static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3745 struct kvm_enable_cap *cap)
3753 case KVM_CAP_DISABLE_QUIRKS:
3754 kvm->arch.disabled_quirks = cap->args[0];
3757 case KVM_CAP_SPLIT_IRQCHIP: {
3758 mutex_lock(&kvm->lock);
3760 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3761 goto split_irqchip_unlock;
3763 if (irqchip_in_kernel(kvm))
3764 goto split_irqchip_unlock;
3765 if (atomic_read(&kvm->online_vcpus))
3766 goto split_irqchip_unlock;
3767 r = kvm_setup_empty_irq_routing(kvm);
3769 goto split_irqchip_unlock;
3770 /* Pairs with irqchip_in_kernel. */
3772 kvm->arch.irqchip_split = true;
3773 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
3775 split_irqchip_unlock:
3776 mutex_unlock(&kvm->lock);
3786 long kvm_arch_vm_ioctl(struct file *filp,
3787 unsigned int ioctl, unsigned long arg)
3789 struct kvm *kvm = filp->private_data;
3790 void __user *argp = (void __user *)arg;
3793 * This union makes it completely explicit to gcc-3.x
3794 * that these two variables' stack usage should be
3795 * combined, not added together.
3798 struct kvm_pit_state ps;
3799 struct kvm_pit_state2 ps2;
3800 struct kvm_pit_config pit_config;
3804 case KVM_SET_TSS_ADDR:
3805 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3807 case KVM_SET_IDENTITY_MAP_ADDR: {
3811 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3813 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3816 case KVM_SET_NR_MMU_PAGES:
3817 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3819 case KVM_GET_NR_MMU_PAGES:
3820 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3822 case KVM_CREATE_IRQCHIP: {
3823 struct kvm_pic *vpic;
3825 mutex_lock(&kvm->lock);
3828 goto create_irqchip_unlock;
3830 if (atomic_read(&kvm->online_vcpus))
3831 goto create_irqchip_unlock;
3833 vpic = kvm_create_pic(kvm);
3835 r = kvm_ioapic_init(kvm);
3837 mutex_lock(&kvm->slots_lock);
3838 kvm_destroy_pic(vpic);
3839 mutex_unlock(&kvm->slots_lock);
3840 goto create_irqchip_unlock;
3843 goto create_irqchip_unlock;
3844 r = kvm_setup_default_irq_routing(kvm);
3846 mutex_lock(&kvm->slots_lock);
3847 mutex_lock(&kvm->irq_lock);
3848 kvm_ioapic_destroy(kvm);
3849 kvm_destroy_pic(vpic);
3850 mutex_unlock(&kvm->irq_lock);
3851 mutex_unlock(&kvm->slots_lock);
3852 goto create_irqchip_unlock;
3854 /* Write kvm->irq_routing before kvm->arch.vpic. */
3856 kvm->arch.vpic = vpic;
3857 create_irqchip_unlock:
3858 mutex_unlock(&kvm->lock);
3861 case KVM_CREATE_PIT:
3862 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3864 case KVM_CREATE_PIT2:
3866 if (copy_from_user(&u.pit_config, argp,
3867 sizeof(struct kvm_pit_config)))
3870 mutex_lock(&kvm->slots_lock);
3873 goto create_pit_unlock;
3875 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3879 mutex_unlock(&kvm->slots_lock);
3881 case KVM_GET_IRQCHIP: {
3882 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3883 struct kvm_irqchip *chip;
3885 chip = memdup_user(argp, sizeof(*chip));
3892 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3893 goto get_irqchip_out;
3894 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3896 goto get_irqchip_out;
3898 if (copy_to_user(argp, chip, sizeof *chip))
3899 goto get_irqchip_out;
3905 case KVM_SET_IRQCHIP: {
3906 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3907 struct kvm_irqchip *chip;
3909 chip = memdup_user(argp, sizeof(*chip));
3916 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
3917 goto set_irqchip_out;
3918 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3920 goto set_irqchip_out;
3928 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3931 if (!kvm->arch.vpit)
3933 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3937 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3944 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3947 if (!kvm->arch.vpit)
3949 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3952 case KVM_GET_PIT2: {
3954 if (!kvm->arch.vpit)
3956 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3960 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3965 case KVM_SET_PIT2: {
3967 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3970 if (!kvm->arch.vpit)
3972 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3975 case KVM_REINJECT_CONTROL: {
3976 struct kvm_reinject_control control;
3978 if (copy_from_user(&control, argp, sizeof(control)))
3980 r = kvm_vm_ioctl_reinject(kvm, &control);
3983 case KVM_SET_BOOT_CPU_ID:
3985 mutex_lock(&kvm->lock);
3986 if (atomic_read(&kvm->online_vcpus) != 0)
3989 kvm->arch.bsp_vcpu_id = arg;
3990 mutex_unlock(&kvm->lock);
3992 case KVM_XEN_HVM_CONFIG: {
3994 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3995 sizeof(struct kvm_xen_hvm_config)))
3998 if (kvm->arch.xen_hvm_config.flags)
4003 case KVM_SET_CLOCK: {
4004 struct kvm_clock_data user_ns;
4009 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4017 local_irq_disable();
4018 now_ns = get_kernel_ns();
4019 delta = user_ns.clock - now_ns;
4021 kvm->arch.kvmclock_offset = delta;
4022 kvm_gen_update_masterclock(kvm);
4025 case KVM_GET_CLOCK: {
4026 struct kvm_clock_data user_ns;
4029 local_irq_disable();
4030 now_ns = get_kernel_ns();
4031 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4034 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4037 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4042 case KVM_ENABLE_CAP: {
4043 struct kvm_enable_cap cap;
4046 if (copy_from_user(&cap, argp, sizeof(cap)))
4048 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4052 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4058 static void kvm_init_msr_list(void)
4063 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
4064 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4068 * Even MSRs that are valid in the host may not be exposed
4069 * to the guests in some cases.
4071 switch (msrs_to_save[i]) {
4072 case MSR_IA32_BNDCFGS:
4073 if (!kvm_x86_ops->mpx_supported())
4077 if (!kvm_x86_ops->rdtscp_supported())
4085 msrs_to_save[j] = msrs_to_save[i];
4088 num_msrs_to_save = j;
4090 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4091 switch (emulated_msrs[i]) {
4092 case MSR_IA32_SMBASE:
4093 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4101 emulated_msrs[j] = emulated_msrs[i];
4104 num_emulated_msrs = j;
4107 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4115 if (!(lapic_in_kernel(vcpu) &&
4116 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4117 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
4128 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4135 if (!(lapic_in_kernel(vcpu) &&
4136 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4138 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
4140 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4150 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4151 struct kvm_segment *var, int seg)
4153 kvm_x86_ops->set_segment(vcpu, var, seg);
4156 void kvm_get_segment(struct kvm_vcpu *vcpu,
4157 struct kvm_segment *var, int seg)
4159 kvm_x86_ops->get_segment(vcpu, var, seg);
4162 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4163 struct x86_exception *exception)
4167 BUG_ON(!mmu_is_nested(vcpu));
4169 /* NPT walks are always user-walks */
4170 access |= PFERR_USER_MASK;
4171 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4176 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4177 struct x86_exception *exception)
4179 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4180 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4183 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4184 struct x86_exception *exception)
4186 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4187 access |= PFERR_FETCH_MASK;
4188 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4191 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4192 struct x86_exception *exception)
4194 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4195 access |= PFERR_WRITE_MASK;
4196 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4199 /* uses this to access any guest's mapped memory without checking CPL */
4200 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4201 struct x86_exception *exception)
4203 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4206 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4207 struct kvm_vcpu *vcpu, u32 access,
4208 struct x86_exception *exception)
4211 int r = X86EMUL_CONTINUE;
4214 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4216 unsigned offset = addr & (PAGE_SIZE-1);
4217 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4220 if (gpa == UNMAPPED_GVA)
4221 return X86EMUL_PROPAGATE_FAULT;
4222 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4225 r = X86EMUL_IO_NEEDED;
4237 /* used for instruction fetching */
4238 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4239 gva_t addr, void *val, unsigned int bytes,
4240 struct x86_exception *exception)
4242 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4243 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4247 /* Inline kvm_read_guest_virt_helper for speed. */
4248 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4250 if (unlikely(gpa == UNMAPPED_GVA))
4251 return X86EMUL_PROPAGATE_FAULT;
4253 offset = addr & (PAGE_SIZE-1);
4254 if (WARN_ON(offset + bytes > PAGE_SIZE))
4255 bytes = (unsigned)PAGE_SIZE - offset;
4256 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4258 if (unlikely(ret < 0))
4259 return X86EMUL_IO_NEEDED;
4261 return X86EMUL_CONTINUE;
4264 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4265 gva_t addr, void *val, unsigned int bytes,
4266 struct x86_exception *exception)
4268 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4269 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4271 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4274 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4276 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4277 gva_t addr, void *val, unsigned int bytes,
4278 struct x86_exception *exception)
4280 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4281 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4284 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4285 unsigned long addr, void *val, unsigned int bytes)
4287 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4288 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4290 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4293 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4294 gva_t addr, void *val,
4296 struct x86_exception *exception)
4298 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4300 int r = X86EMUL_CONTINUE;
4303 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4306 unsigned offset = addr & (PAGE_SIZE-1);
4307 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4310 if (gpa == UNMAPPED_GVA)
4311 return X86EMUL_PROPAGATE_FAULT;
4312 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
4314 r = X86EMUL_IO_NEEDED;
4325 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4327 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4328 gpa_t *gpa, struct x86_exception *exception,
4331 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4332 | (write ? PFERR_WRITE_MASK : 0);
4335 * currently PKRU is only applied to ept enabled guest so
4336 * there is no pkey in EPT page table for L1 guest or EPT
4337 * shadow page table for L2 guest.
4339 if (vcpu_match_mmio_gva(vcpu, gva)
4340 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4341 vcpu->arch.access, 0, access)) {
4342 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4343 (gva & (PAGE_SIZE - 1));
4344 trace_vcpu_match_mmio(gva, *gpa, write, false);
4348 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4350 if (*gpa == UNMAPPED_GVA)
4353 /* For APIC access vmexit */
4354 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4357 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4358 trace_vcpu_match_mmio(gva, *gpa, write, true);
4365 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4366 const void *val, int bytes)
4370 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
4373 kvm_page_track_write(vcpu, gpa, val, bytes);
4377 struct read_write_emulator_ops {
4378 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4380 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4381 void *val, int bytes);
4382 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4383 int bytes, void *val);
4384 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4385 void *val, int bytes);
4389 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4391 if (vcpu->mmio_read_completed) {
4392 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4393 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4394 vcpu->mmio_read_completed = 0;
4401 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4402 void *val, int bytes)
4404 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
4407 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4408 void *val, int bytes)
4410 return emulator_write_phys(vcpu, gpa, val, bytes);
4413 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4415 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4416 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4419 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4420 void *val, int bytes)
4422 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4423 return X86EMUL_IO_NEEDED;
4426 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4427 void *val, int bytes)
4429 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4431 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4432 return X86EMUL_CONTINUE;
4435 static const struct read_write_emulator_ops read_emultor = {
4436 .read_write_prepare = read_prepare,
4437 .read_write_emulate = read_emulate,
4438 .read_write_mmio = vcpu_mmio_read,
4439 .read_write_exit_mmio = read_exit_mmio,
4442 static const struct read_write_emulator_ops write_emultor = {
4443 .read_write_emulate = write_emulate,
4444 .read_write_mmio = write_mmio,
4445 .read_write_exit_mmio = write_exit_mmio,
4449 static int emulator_read_write_onepage(unsigned long addr, void *val,
4451 struct x86_exception *exception,
4452 struct kvm_vcpu *vcpu,
4453 const struct read_write_emulator_ops *ops)
4457 bool write = ops->write;
4458 struct kvm_mmio_fragment *frag;
4460 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4463 return X86EMUL_PROPAGATE_FAULT;
4465 /* For APIC access vmexit */
4469 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4470 return X86EMUL_CONTINUE;
4474 * Is this MMIO handled locally?
4476 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4477 if (handled == bytes)
4478 return X86EMUL_CONTINUE;
4484 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4485 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4489 return X86EMUL_CONTINUE;
4492 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4494 void *val, unsigned int bytes,
4495 struct x86_exception *exception,
4496 const struct read_write_emulator_ops *ops)
4498 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4502 if (ops->read_write_prepare &&
4503 ops->read_write_prepare(vcpu, val, bytes))
4504 return X86EMUL_CONTINUE;
4506 vcpu->mmio_nr_fragments = 0;
4508 /* Crossing a page boundary? */
4509 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4512 now = -addr & ~PAGE_MASK;
4513 rc = emulator_read_write_onepage(addr, val, now, exception,
4516 if (rc != X86EMUL_CONTINUE)
4519 if (ctxt->mode != X86EMUL_MODE_PROT64)
4525 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4527 if (rc != X86EMUL_CONTINUE)
4530 if (!vcpu->mmio_nr_fragments)
4533 gpa = vcpu->mmio_fragments[0].gpa;
4535 vcpu->mmio_needed = 1;
4536 vcpu->mmio_cur_fragment = 0;
4538 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4539 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4540 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4541 vcpu->run->mmio.phys_addr = gpa;
4543 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4546 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4550 struct x86_exception *exception)
4552 return emulator_read_write(ctxt, addr, val, bytes,
4553 exception, &read_emultor);
4556 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4560 struct x86_exception *exception)
4562 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4563 exception, &write_emultor);
4566 #define CMPXCHG_TYPE(t, ptr, old, new) \
4567 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4569 #ifdef CONFIG_X86_64
4570 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4572 # define CMPXCHG64(ptr, old, new) \
4573 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4576 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4581 struct x86_exception *exception)
4583 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4589 /* guests cmpxchg8b have to be emulated atomically */
4590 if (bytes > 8 || (bytes & (bytes - 1)))
4593 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4595 if (gpa == UNMAPPED_GVA ||
4596 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4599 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4602 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
4603 if (is_error_page(page))
4606 kaddr = kmap_atomic(page);
4607 kaddr += offset_in_page(gpa);
4610 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4613 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4616 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4619 exchanged = CMPXCHG64(kaddr, old, new);
4624 kunmap_atomic(kaddr);
4625 kvm_release_page_dirty(page);
4628 return X86EMUL_CMPXCHG_FAILED;
4630 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
4631 kvm_page_track_write(vcpu, gpa, new, bytes);
4633 return X86EMUL_CONTINUE;
4636 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4638 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4641 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4643 /* TODO: String I/O for in kernel device */
4646 if (vcpu->arch.pio.in)
4647 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4648 vcpu->arch.pio.size, pd);
4650 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4651 vcpu->arch.pio.port, vcpu->arch.pio.size,
4656 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4657 unsigned short port, void *val,
4658 unsigned int count, bool in)
4660 vcpu->arch.pio.port = port;
4661 vcpu->arch.pio.in = in;
4662 vcpu->arch.pio.count = count;
4663 vcpu->arch.pio.size = size;
4665 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4666 vcpu->arch.pio.count = 0;
4670 vcpu->run->exit_reason = KVM_EXIT_IO;
4671 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4672 vcpu->run->io.size = size;
4673 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4674 vcpu->run->io.count = count;
4675 vcpu->run->io.port = port;
4680 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4681 int size, unsigned short port, void *val,
4684 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4687 if (vcpu->arch.pio.count)
4690 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4693 memcpy(val, vcpu->arch.pio_data, size * count);
4694 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4695 vcpu->arch.pio.count = 0;
4702 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4703 int size, unsigned short port,
4704 const void *val, unsigned int count)
4706 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4708 memcpy(vcpu->arch.pio_data, val, size * count);
4709 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4710 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4713 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4715 return kvm_x86_ops->get_segment_base(vcpu, seg);
4718 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4720 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4723 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4725 if (!need_emulate_wbinvd(vcpu))
4726 return X86EMUL_CONTINUE;
4728 if (kvm_x86_ops->has_wbinvd_exit()) {
4729 int cpu = get_cpu();
4731 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4732 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4733 wbinvd_ipi, NULL, 1);
4735 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4738 return X86EMUL_CONTINUE;
4741 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4743 kvm_x86_ops->skip_emulated_instruction(vcpu);
4744 return kvm_emulate_wbinvd_noskip(vcpu);
4746 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4750 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4752 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4755 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4756 unsigned long *dest)
4758 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4761 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4762 unsigned long value)
4765 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4768 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4770 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4773 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4775 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4776 unsigned long value;
4780 value = kvm_read_cr0(vcpu);
4783 value = vcpu->arch.cr2;
4786 value = kvm_read_cr3(vcpu);
4789 value = kvm_read_cr4(vcpu);
4792 value = kvm_get_cr8(vcpu);
4795 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4802 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4804 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4809 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4812 vcpu->arch.cr2 = val;
4815 res = kvm_set_cr3(vcpu, val);
4818 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4821 res = kvm_set_cr8(vcpu, val);
4824 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4831 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4833 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4836 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4838 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4841 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4843 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4846 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4848 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4851 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4853 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4856 static unsigned long emulator_get_cached_segment_base(
4857 struct x86_emulate_ctxt *ctxt, int seg)
4859 return get_segment_base(emul_to_vcpu(ctxt), seg);
4862 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4863 struct desc_struct *desc, u32 *base3,
4866 struct kvm_segment var;
4868 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4869 *selector = var.selector;
4872 memset(desc, 0, sizeof(*desc));
4878 set_desc_limit(desc, var.limit);
4879 set_desc_base(desc, (unsigned long)var.base);
4880 #ifdef CONFIG_X86_64
4882 *base3 = var.base >> 32;
4884 desc->type = var.type;
4886 desc->dpl = var.dpl;
4887 desc->p = var.present;
4888 desc->avl = var.avl;
4896 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4897 struct desc_struct *desc, u32 base3,
4900 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4901 struct kvm_segment var;
4903 var.selector = selector;
4904 var.base = get_desc_base(desc);
4905 #ifdef CONFIG_X86_64
4906 var.base |= ((u64)base3) << 32;
4908 var.limit = get_desc_limit(desc);
4910 var.limit = (var.limit << 12) | 0xfff;
4911 var.type = desc->type;
4912 var.dpl = desc->dpl;
4917 var.avl = desc->avl;
4918 var.present = desc->p;
4919 var.unusable = !var.present;
4922 kvm_set_segment(vcpu, &var, seg);
4926 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4927 u32 msr_index, u64 *pdata)
4929 struct msr_data msr;
4932 msr.index = msr_index;
4933 msr.host_initiated = false;
4934 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4942 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4943 u32 msr_index, u64 data)
4945 struct msr_data msr;
4948 msr.index = msr_index;
4949 msr.host_initiated = false;
4950 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4953 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4955 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4957 return vcpu->arch.smbase;
4960 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4962 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4964 vcpu->arch.smbase = smbase;
4967 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4970 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
4973 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4974 u32 pmc, u64 *pdata)
4976 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
4979 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4981 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4984 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4987 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4989 * CR0.TS may reference the host fpu state, not the guest fpu state,
4990 * so it may be clear at this point.
4995 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5000 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
5001 struct x86_instruction_info *info,
5002 enum x86_intercept_stage stage)
5004 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
5007 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5008 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5010 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
5013 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5015 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5018 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5020 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5023 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5025 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5028 static const struct x86_emulate_ops emulate_ops = {
5029 .read_gpr = emulator_read_gpr,
5030 .write_gpr = emulator_write_gpr,
5031 .read_std = kvm_read_guest_virt_system,
5032 .write_std = kvm_write_guest_virt_system,
5033 .read_phys = kvm_read_guest_phys_system,
5034 .fetch = kvm_fetch_guest_virt,
5035 .read_emulated = emulator_read_emulated,
5036 .write_emulated = emulator_write_emulated,
5037 .cmpxchg_emulated = emulator_cmpxchg_emulated,
5038 .invlpg = emulator_invlpg,
5039 .pio_in_emulated = emulator_pio_in_emulated,
5040 .pio_out_emulated = emulator_pio_out_emulated,
5041 .get_segment = emulator_get_segment,
5042 .set_segment = emulator_set_segment,
5043 .get_cached_segment_base = emulator_get_cached_segment_base,
5044 .get_gdt = emulator_get_gdt,
5045 .get_idt = emulator_get_idt,
5046 .set_gdt = emulator_set_gdt,
5047 .set_idt = emulator_set_idt,
5048 .get_cr = emulator_get_cr,
5049 .set_cr = emulator_set_cr,
5050 .cpl = emulator_get_cpl,
5051 .get_dr = emulator_get_dr,
5052 .set_dr = emulator_set_dr,
5053 .get_smbase = emulator_get_smbase,
5054 .set_smbase = emulator_set_smbase,
5055 .set_msr = emulator_set_msr,
5056 .get_msr = emulator_get_msr,
5057 .check_pmc = emulator_check_pmc,
5058 .read_pmc = emulator_read_pmc,
5059 .halt = emulator_halt,
5060 .wbinvd = emulator_wbinvd,
5061 .fix_hypercall = emulator_fix_hypercall,
5062 .get_fpu = emulator_get_fpu,
5063 .put_fpu = emulator_put_fpu,
5064 .intercept = emulator_intercept,
5065 .get_cpuid = emulator_get_cpuid,
5066 .set_nmi_mask = emulator_set_nmi_mask,
5069 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5071 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5073 * an sti; sti; sequence only disable interrupts for the first
5074 * instruction. So, if the last instruction, be it emulated or
5075 * not, left the system with the INT_STI flag enabled, it
5076 * means that the last instruction is an sti. We should not
5077 * leave the flag on in this case. The same goes for mov ss
5079 if (int_shadow & mask)
5081 if (unlikely(int_shadow || mask)) {
5082 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5084 kvm_make_request(KVM_REQ_EVENT, vcpu);
5088 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5090 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5091 if (ctxt->exception.vector == PF_VECTOR)
5092 return kvm_propagate_fault(vcpu, &ctxt->exception);
5094 if (ctxt->exception.error_code_valid)
5095 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5096 ctxt->exception.error_code);
5098 kvm_queue_exception(vcpu, ctxt->exception.vector);
5102 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5104 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5107 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5109 ctxt->eflags = kvm_get_rflags(vcpu);
5110 ctxt->eip = kvm_rip_read(vcpu);
5111 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5112 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
5113 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
5114 cs_db ? X86EMUL_MODE_PROT32 :
5115 X86EMUL_MODE_PROT16;
5116 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
5117 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5118 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
5119 ctxt->emul_flags = vcpu->arch.hflags;
5121 init_decode_cache(ctxt);
5122 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5125 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5127 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5130 init_emulate_ctxt(vcpu);
5134 ctxt->_eip = ctxt->eip + inc_eip;
5135 ret = emulate_int_real(ctxt, irq);
5137 if (ret != X86EMUL_CONTINUE)
5138 return EMULATE_FAIL;
5140 ctxt->eip = ctxt->_eip;
5141 kvm_rip_write(vcpu, ctxt->eip);
5142 kvm_set_rflags(vcpu, ctxt->eflags);
5144 if (irq == NMI_VECTOR)
5145 vcpu->arch.nmi_pending = 0;
5147 vcpu->arch.interrupt.pending = false;
5149 return EMULATE_DONE;
5151 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5153 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5155 int r = EMULATE_DONE;
5157 ++vcpu->stat.insn_emulation_fail;
5158 trace_kvm_emulate_insn_failed(vcpu);
5159 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5160 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5161 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5162 vcpu->run->internal.ndata = 0;
5165 kvm_queue_exception(vcpu, UD_VECTOR);
5170 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5171 bool write_fault_to_shadow_pgtable,
5177 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5180 if (!vcpu->arch.mmu.direct_map) {
5182 * Write permission should be allowed since only
5183 * write access need to be emulated.
5185 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5188 * If the mapping is invalid in guest, let cpu retry
5189 * it to generate fault.
5191 if (gpa == UNMAPPED_GVA)
5196 * Do not retry the unhandleable instruction if it faults on the
5197 * readonly host memory, otherwise it will goto a infinite loop:
5198 * retry instruction -> write #PF -> emulation fail -> retry
5199 * instruction -> ...
5201 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5204 * If the instruction failed on the error pfn, it can not be fixed,
5205 * report the error to userspace.
5207 if (is_error_noslot_pfn(pfn))
5210 kvm_release_pfn_clean(pfn);
5212 /* The instructions are well-emulated on direct mmu. */
5213 if (vcpu->arch.mmu.direct_map) {
5214 unsigned int indirect_shadow_pages;
5216 spin_lock(&vcpu->kvm->mmu_lock);
5217 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5218 spin_unlock(&vcpu->kvm->mmu_lock);
5220 if (indirect_shadow_pages)
5221 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5227 * if emulation was due to access to shadowed page table
5228 * and it failed try to unshadow page and re-enter the
5229 * guest to let CPU execute the instruction.
5231 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5234 * If the access faults on its page table, it can not
5235 * be fixed by unprotecting shadow page and it should
5236 * be reported to userspace.
5238 return !write_fault_to_shadow_pgtable;
5241 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5242 unsigned long cr2, int emulation_type)
5244 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5245 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5247 last_retry_eip = vcpu->arch.last_retry_eip;
5248 last_retry_addr = vcpu->arch.last_retry_addr;
5251 * If the emulation is caused by #PF and it is non-page_table
5252 * writing instruction, it means the VM-EXIT is caused by shadow
5253 * page protected, we can zap the shadow page and retry this
5254 * instruction directly.
5256 * Note: if the guest uses a non-page-table modifying instruction
5257 * on the PDE that points to the instruction, then we will unmap
5258 * the instruction and go to an infinite loop. So, we cache the
5259 * last retried eip and the last fault address, if we meet the eip
5260 * and the address again, we can break out of the potential infinite
5263 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5265 if (!(emulation_type & EMULTYPE_RETRY))
5268 if (x86_page_table_writing_insn(ctxt))
5271 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5274 vcpu->arch.last_retry_eip = ctxt->eip;
5275 vcpu->arch.last_retry_addr = cr2;
5277 if (!vcpu->arch.mmu.direct_map)
5278 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5280 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5285 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5286 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5288 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
5290 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
5291 /* This is a good place to trace that we are exiting SMM. */
5292 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5294 if (unlikely(vcpu->arch.smi_pending)) {
5295 kvm_make_request(KVM_REQ_SMI, vcpu);
5296 vcpu->arch.smi_pending = 0;
5298 /* Process a latched INIT, if any. */
5299 kvm_make_request(KVM_REQ_EVENT, vcpu);
5303 kvm_mmu_reset_context(vcpu);
5306 static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5308 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5310 vcpu->arch.hflags = emul_flags;
5312 if (changed & HF_SMM_MASK)
5313 kvm_smm_changed(vcpu);
5316 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5325 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5326 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5331 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5333 struct kvm_run *kvm_run = vcpu->run;
5336 * rflags is the old, "raw" value of the flags. The new value has
5337 * not been saved yet.
5339 * This is correct even for TF set by the guest, because "the
5340 * processor will not generate this exception after the instruction
5341 * that sets the TF flag".
5343 if (unlikely(rflags & X86_EFLAGS_TF)) {
5344 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5345 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5347 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5348 kvm_run->debug.arch.exception = DB_VECTOR;
5349 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5350 *r = EMULATE_USER_EXIT;
5352 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5354 * "Certain debug exceptions may clear bit 0-3. The
5355 * remaining contents of the DR6 register are never
5356 * cleared by the processor".
5358 vcpu->arch.dr6 &= ~15;
5359 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5360 kvm_queue_exception(vcpu, DB_VECTOR);
5365 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5367 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5368 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5369 struct kvm_run *kvm_run = vcpu->run;
5370 unsigned long eip = kvm_get_linear_rip(vcpu);
5371 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5372 vcpu->arch.guest_debug_dr7,
5376 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5377 kvm_run->debug.arch.pc = eip;
5378 kvm_run->debug.arch.exception = DB_VECTOR;
5379 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5380 *r = EMULATE_USER_EXIT;
5385 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5386 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5387 unsigned long eip = kvm_get_linear_rip(vcpu);
5388 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5393 vcpu->arch.dr6 &= ~15;
5394 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5395 kvm_queue_exception(vcpu, DB_VECTOR);
5404 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5411 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5412 bool writeback = true;
5413 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5416 * Clear write_fault_to_shadow_pgtable here to ensure it is
5419 vcpu->arch.write_fault_to_shadow_pgtable = false;
5420 kvm_clear_exception_queue(vcpu);
5422 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5423 init_emulate_ctxt(vcpu);
5426 * We will reenter on the same instruction since
5427 * we do not set complete_userspace_io. This does not
5428 * handle watchpoints yet, those would be handled in
5431 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5434 ctxt->interruptibility = 0;
5435 ctxt->have_exception = false;
5436 ctxt->exception.vector = -1;
5437 ctxt->perm_ok = false;
5439 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5441 r = x86_decode_insn(ctxt, insn, insn_len);
5443 trace_kvm_emulate_insn_start(vcpu);
5444 ++vcpu->stat.insn_emulation;
5445 if (r != EMULATION_OK) {
5446 if (emulation_type & EMULTYPE_TRAP_UD)
5447 return EMULATE_FAIL;
5448 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5450 return EMULATE_DONE;
5451 if (emulation_type & EMULTYPE_SKIP)
5452 return EMULATE_FAIL;
5453 return handle_emulation_failure(vcpu);
5457 if (emulation_type & EMULTYPE_SKIP) {
5458 kvm_rip_write(vcpu, ctxt->_eip);
5459 if (ctxt->eflags & X86_EFLAGS_RF)
5460 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5461 return EMULATE_DONE;
5464 if (retry_instruction(ctxt, cr2, emulation_type))
5465 return EMULATE_DONE;
5467 /* this is needed for vmware backdoor interface to work since it
5468 changes registers values during IO operation */
5469 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5470 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5471 emulator_invalidate_register_cache(ctxt);
5475 r = x86_emulate_insn(ctxt);
5477 if (r == EMULATION_INTERCEPTED)
5478 return EMULATE_DONE;
5480 if (r == EMULATION_FAILED) {
5481 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5483 return EMULATE_DONE;
5485 return handle_emulation_failure(vcpu);
5488 if (ctxt->have_exception) {
5490 if (inject_emulated_exception(vcpu))
5492 } else if (vcpu->arch.pio.count) {
5493 if (!vcpu->arch.pio.in) {
5494 /* FIXME: return into emulator if single-stepping. */
5495 vcpu->arch.pio.count = 0;
5498 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5500 r = EMULATE_USER_EXIT;
5501 } else if (vcpu->mmio_needed) {
5502 if (!vcpu->mmio_is_write)
5504 r = EMULATE_USER_EXIT;
5505 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5506 } else if (r == EMULATION_RESTART)
5512 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5513 toggle_interruptibility(vcpu, ctxt->interruptibility);
5514 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5515 if (vcpu->arch.hflags != ctxt->emul_flags)
5516 kvm_set_hflags(vcpu, ctxt->emul_flags);
5517 kvm_rip_write(vcpu, ctxt->eip);
5518 if (r == EMULATE_DONE)
5519 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5520 if (!ctxt->have_exception ||
5521 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5522 __kvm_set_rflags(vcpu, ctxt->eflags);
5525 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5526 * do nothing, and it will be requested again as soon as
5527 * the shadow expires. But we still need to check here,
5528 * because POPF has no interrupt shadow.
5530 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5531 kvm_make_request(KVM_REQ_EVENT, vcpu);
5533 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5537 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5539 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5541 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5542 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5543 size, port, &val, 1);
5544 /* do not return to emulator after return from userspace */
5545 vcpu->arch.pio.count = 0;
5548 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5550 static void tsc_bad(void *info)
5552 __this_cpu_write(cpu_tsc_khz, 0);
5555 static void tsc_khz_changed(void *data)
5557 struct cpufreq_freqs *freq = data;
5558 unsigned long khz = 0;
5562 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5563 khz = cpufreq_quick_get(raw_smp_processor_id());
5566 __this_cpu_write(cpu_tsc_khz, khz);
5569 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5572 struct cpufreq_freqs *freq = data;
5574 struct kvm_vcpu *vcpu;
5575 int i, send_ipi = 0;
5578 * We allow guests to temporarily run on slowing clocks,
5579 * provided we notify them after, or to run on accelerating
5580 * clocks, provided we notify them before. Thus time never
5583 * However, we have a problem. We can't atomically update
5584 * the frequency of a given CPU from this function; it is
5585 * merely a notifier, which can be called from any CPU.
5586 * Changing the TSC frequency at arbitrary points in time
5587 * requires a recomputation of local variables related to
5588 * the TSC for each VCPU. We must flag these local variables
5589 * to be updated and be sure the update takes place with the
5590 * new frequency before any guests proceed.
5592 * Unfortunately, the combination of hotplug CPU and frequency
5593 * change creates an intractable locking scenario; the order
5594 * of when these callouts happen is undefined with respect to
5595 * CPU hotplug, and they can race with each other. As such,
5596 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5597 * undefined; you can actually have a CPU frequency change take
5598 * place in between the computation of X and the setting of the
5599 * variable. To protect against this problem, all updates of
5600 * the per_cpu tsc_khz variable are done in an interrupt
5601 * protected IPI, and all callers wishing to update the value
5602 * must wait for a synchronous IPI to complete (which is trivial
5603 * if the caller is on the CPU already). This establishes the
5604 * necessary total order on variable updates.
5606 * Note that because a guest time update may take place
5607 * anytime after the setting of the VCPU's request bit, the
5608 * correct TSC value must be set before the request. However,
5609 * to ensure the update actually makes it to any guest which
5610 * starts running in hardware virtualization between the set
5611 * and the acquisition of the spinlock, we must also ping the
5612 * CPU after setting the request bit.
5616 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5618 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5621 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5623 spin_lock(&kvm_lock);
5624 list_for_each_entry(kvm, &vm_list, vm_list) {
5625 kvm_for_each_vcpu(i, vcpu, kvm) {
5626 if (vcpu->cpu != freq->cpu)
5628 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5629 if (vcpu->cpu != smp_processor_id())
5633 spin_unlock(&kvm_lock);
5635 if (freq->old < freq->new && send_ipi) {
5637 * We upscale the frequency. Must make the guest
5638 * doesn't see old kvmclock values while running with
5639 * the new frequency, otherwise we risk the guest sees
5640 * time go backwards.
5642 * In case we update the frequency for another cpu
5643 * (which might be in guest context) send an interrupt
5644 * to kick the cpu out of guest context. Next time
5645 * guest context is entered kvmclock will be updated,
5646 * so the guest will not see stale values.
5648 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5653 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5654 .notifier_call = kvmclock_cpufreq_notifier
5657 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5658 unsigned long action, void *hcpu)
5660 unsigned int cpu = (unsigned long)hcpu;
5664 case CPU_DOWN_FAILED:
5665 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5667 case CPU_DOWN_PREPARE:
5668 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5674 static struct notifier_block kvmclock_cpu_notifier_block = {
5675 .notifier_call = kvmclock_cpu_notifier,
5676 .priority = -INT_MAX
5679 static void kvm_timer_init(void)
5683 max_tsc_khz = tsc_khz;
5685 cpu_notifier_register_begin();
5686 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5687 #ifdef CONFIG_CPU_FREQ
5688 struct cpufreq_policy policy;
5689 memset(&policy, 0, sizeof(policy));
5691 cpufreq_get_policy(&policy, cpu);
5692 if (policy.cpuinfo.max_freq)
5693 max_tsc_khz = policy.cpuinfo.max_freq;
5696 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5697 CPUFREQ_TRANSITION_NOTIFIER);
5699 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5700 for_each_online_cpu(cpu)
5701 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5703 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5704 cpu_notifier_register_done();
5708 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5710 int kvm_is_in_guest(void)
5712 return __this_cpu_read(current_vcpu) != NULL;
5715 static int kvm_is_user_mode(void)
5719 if (__this_cpu_read(current_vcpu))
5720 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5722 return user_mode != 0;
5725 static unsigned long kvm_get_guest_ip(void)
5727 unsigned long ip = 0;
5729 if (__this_cpu_read(current_vcpu))
5730 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5735 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5736 .is_in_guest = kvm_is_in_guest,
5737 .is_user_mode = kvm_is_user_mode,
5738 .get_guest_ip = kvm_get_guest_ip,
5741 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5743 __this_cpu_write(current_vcpu, vcpu);
5745 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5747 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5749 __this_cpu_write(current_vcpu, NULL);
5751 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5753 static void kvm_set_mmio_spte_mask(void)
5756 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5759 * Set the reserved bits and the present bit of an paging-structure
5760 * entry to generate page fault with PFER.RSV = 1.
5762 /* Mask the reserved physical address bits. */
5763 mask = rsvd_bits(maxphyaddr, 51);
5765 /* Bit 62 is always reserved for 32bit host. */
5766 mask |= 0x3ull << 62;
5768 /* Set the present bit. */
5771 #ifdef CONFIG_X86_64
5773 * If reserved bit is not supported, clear the present bit to disable
5776 if (maxphyaddr == 52)
5780 kvm_mmu_set_mmio_spte_mask(mask);
5783 #ifdef CONFIG_X86_64
5784 static void pvclock_gtod_update_fn(struct work_struct *work)
5788 struct kvm_vcpu *vcpu;
5791 spin_lock(&kvm_lock);
5792 list_for_each_entry(kvm, &vm_list, vm_list)
5793 kvm_for_each_vcpu(i, vcpu, kvm)
5794 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5795 atomic_set(&kvm_guest_has_master_clock, 0);
5796 spin_unlock(&kvm_lock);
5799 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5802 * Notification about pvclock gtod data update.
5804 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5807 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5808 struct timekeeper *tk = priv;
5810 update_pvclock_gtod(tk);
5812 /* disable master clock if host does not trust, or does not
5813 * use, TSC clocksource
5815 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5816 atomic_read(&kvm_guest_has_master_clock) != 0)
5817 queue_work(system_long_wq, &pvclock_gtod_work);
5822 static struct notifier_block pvclock_gtod_notifier = {
5823 .notifier_call = pvclock_gtod_notify,
5827 int kvm_arch_init(void *opaque)
5830 struct kvm_x86_ops *ops = opaque;
5833 printk(KERN_ERR "kvm: already loaded the other module\n");
5838 if (!ops->cpu_has_kvm_support()) {
5839 printk(KERN_ERR "kvm: no hardware support\n");
5843 if (ops->disabled_by_bios()) {
5844 printk(KERN_ERR "kvm: disabled by bios\n");
5850 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5852 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5856 r = kvm_mmu_module_init();
5858 goto out_free_percpu;
5860 kvm_set_mmio_spte_mask();
5864 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5865 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5869 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5872 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5875 #ifdef CONFIG_X86_64
5876 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5882 free_percpu(shared_msrs);
5887 void kvm_arch_exit(void)
5889 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5891 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5892 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5893 CPUFREQ_TRANSITION_NOTIFIER);
5894 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5895 #ifdef CONFIG_X86_64
5896 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5899 kvm_mmu_module_exit();
5900 free_percpu(shared_msrs);
5903 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5905 ++vcpu->stat.halt_exits;
5906 if (lapic_in_kernel(vcpu)) {
5907 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5910 vcpu->run->exit_reason = KVM_EXIT_HLT;
5914 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5916 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5918 kvm_x86_ops->skip_emulated_instruction(vcpu);
5919 return kvm_vcpu_halt(vcpu);
5921 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5924 * kvm_pv_kick_cpu_op: Kick a vcpu.
5926 * @apicid - apicid of vcpu to be kicked.
5928 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5930 struct kvm_lapic_irq lapic_irq;
5932 lapic_irq.shorthand = 0;
5933 lapic_irq.dest_mode = 0;
5934 lapic_irq.dest_id = apicid;
5935 lapic_irq.msi_redir_hint = false;
5937 lapic_irq.delivery_mode = APIC_DM_REMRD;
5938 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
5941 void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5943 vcpu->arch.apicv_active = false;
5944 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5947 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5949 unsigned long nr, a0, a1, a2, a3, ret;
5950 int op_64_bit, r = 1;
5952 kvm_x86_ops->skip_emulated_instruction(vcpu);
5954 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5955 return kvm_hv_hypercall(vcpu);
5957 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5958 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5959 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5960 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5961 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5963 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5965 op_64_bit = is_64_bit_mode(vcpu);
5974 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5980 case KVM_HC_VAPIC_POLL_IRQ:
5983 case KVM_HC_KICK_CPU:
5984 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5994 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5995 ++vcpu->stat.hypercalls;
5998 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6000 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
6002 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6003 char instruction[3];
6004 unsigned long rip = kvm_rip_read(vcpu);
6006 kvm_x86_ops->patch_hypercall(vcpu, instruction);
6008 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
6011 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
6013 return vcpu->run->request_interrupt_window &&
6014 likely(!pic_in_kernel(vcpu->kvm));
6017 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6019 struct kvm_run *kvm_run = vcpu->run;
6021 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6022 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
6023 kvm_run->cr8 = kvm_get_cr8(vcpu);
6024 kvm_run->apic_base = kvm_get_apic_base(vcpu);
6025 kvm_run->ready_for_interrupt_injection =
6026 pic_in_kernel(vcpu->kvm) ||
6027 kvm_vcpu_ready_for_interrupt_injection(vcpu);
6030 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6034 if (!kvm_x86_ops->update_cr8_intercept)
6037 if (!lapic_in_kernel(vcpu))
6040 if (vcpu->arch.apicv_active)
6043 if (!vcpu->arch.apic->vapic_addr)
6044 max_irr = kvm_lapic_find_highest_irr(vcpu);
6051 tpr = kvm_lapic_get_cr8(vcpu);
6053 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6056 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6060 /* try to reinject previous events if any */
6061 if (vcpu->arch.exception.pending) {
6062 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6063 vcpu->arch.exception.has_error_code,
6064 vcpu->arch.exception.error_code);
6066 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6067 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6070 if (vcpu->arch.exception.nr == DB_VECTOR &&
6071 (vcpu->arch.dr7 & DR7_GD)) {
6072 vcpu->arch.dr7 &= ~DR7_GD;
6073 kvm_update_dr7(vcpu);
6076 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6077 vcpu->arch.exception.has_error_code,
6078 vcpu->arch.exception.error_code,
6079 vcpu->arch.exception.reinject);
6083 if (vcpu->arch.nmi_injected) {
6084 kvm_x86_ops->set_nmi(vcpu);
6088 if (vcpu->arch.interrupt.pending) {
6089 kvm_x86_ops->set_irq(vcpu);
6093 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6094 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6099 /* try to inject new event if pending */
6100 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
6101 --vcpu->arch.nmi_pending;
6102 vcpu->arch.nmi_injected = true;
6103 kvm_x86_ops->set_nmi(vcpu);
6104 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6106 * Because interrupts can be injected asynchronously, we are
6107 * calling check_nested_events again here to avoid a race condition.
6108 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6109 * proposal and current concerns. Perhaps we should be setting
6110 * KVM_REQ_EVENT only on certain events and not unconditionally?
6112 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6113 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6117 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6118 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6120 kvm_x86_ops->set_irq(vcpu);
6126 static void process_nmi(struct kvm_vcpu *vcpu)
6131 * x86 is limited to one NMI running, and one NMI pending after it.
6132 * If an NMI is already in progress, limit further NMIs to just one.
6133 * Otherwise, allow two (and we'll inject the first one immediately).
6135 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6138 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6139 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6140 kvm_make_request(KVM_REQ_EVENT, vcpu);
6143 #define put_smstate(type, buf, offset, val) \
6144 *(type *)((buf) + (offset) - 0x7e00) = val
6146 static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6149 flags |= seg->g << 23;
6150 flags |= seg->db << 22;
6151 flags |= seg->l << 21;
6152 flags |= seg->avl << 20;
6153 flags |= seg->present << 15;
6154 flags |= seg->dpl << 13;
6155 flags |= seg->s << 12;
6156 flags |= seg->type << 8;
6160 static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6162 struct kvm_segment seg;
6165 kvm_get_segment(vcpu, &seg, n);
6166 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6169 offset = 0x7f84 + n * 12;
6171 offset = 0x7f2c + (n - 3) * 12;
6173 put_smstate(u32, buf, offset + 8, seg.base);
6174 put_smstate(u32, buf, offset + 4, seg.limit);
6175 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6178 #ifdef CONFIG_X86_64
6179 static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6181 struct kvm_segment seg;
6185 kvm_get_segment(vcpu, &seg, n);
6186 offset = 0x7e00 + n * 16;
6188 flags = process_smi_get_segment_flags(&seg) >> 8;
6189 put_smstate(u16, buf, offset, seg.selector);
6190 put_smstate(u16, buf, offset + 2, flags);
6191 put_smstate(u32, buf, offset + 4, seg.limit);
6192 put_smstate(u64, buf, offset + 8, seg.base);
6196 static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6199 struct kvm_segment seg;
6203 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6204 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6205 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6206 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6208 for (i = 0; i < 8; i++)
6209 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6211 kvm_get_dr(vcpu, 6, &val);
6212 put_smstate(u32, buf, 0x7fcc, (u32)val);
6213 kvm_get_dr(vcpu, 7, &val);
6214 put_smstate(u32, buf, 0x7fc8, (u32)val);
6216 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6217 put_smstate(u32, buf, 0x7fc4, seg.selector);
6218 put_smstate(u32, buf, 0x7f64, seg.base);
6219 put_smstate(u32, buf, 0x7f60, seg.limit);
6220 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6222 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6223 put_smstate(u32, buf, 0x7fc0, seg.selector);
6224 put_smstate(u32, buf, 0x7f80, seg.base);
6225 put_smstate(u32, buf, 0x7f7c, seg.limit);
6226 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6228 kvm_x86_ops->get_gdt(vcpu, &dt);
6229 put_smstate(u32, buf, 0x7f74, dt.address);
6230 put_smstate(u32, buf, 0x7f70, dt.size);
6232 kvm_x86_ops->get_idt(vcpu, &dt);
6233 put_smstate(u32, buf, 0x7f58, dt.address);
6234 put_smstate(u32, buf, 0x7f54, dt.size);
6236 for (i = 0; i < 6; i++)
6237 process_smi_save_seg_32(vcpu, buf, i);
6239 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6242 put_smstate(u32, buf, 0x7efc, 0x00020000);
6243 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6246 static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6248 #ifdef CONFIG_X86_64
6250 struct kvm_segment seg;
6254 for (i = 0; i < 16; i++)
6255 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6257 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6258 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6260 kvm_get_dr(vcpu, 6, &val);
6261 put_smstate(u64, buf, 0x7f68, val);
6262 kvm_get_dr(vcpu, 7, &val);
6263 put_smstate(u64, buf, 0x7f60, val);
6265 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6266 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6267 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6269 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6272 put_smstate(u32, buf, 0x7efc, 0x00020064);
6274 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6276 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6277 put_smstate(u16, buf, 0x7e90, seg.selector);
6278 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6279 put_smstate(u32, buf, 0x7e94, seg.limit);
6280 put_smstate(u64, buf, 0x7e98, seg.base);
6282 kvm_x86_ops->get_idt(vcpu, &dt);
6283 put_smstate(u32, buf, 0x7e84, dt.size);
6284 put_smstate(u64, buf, 0x7e88, dt.address);
6286 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6287 put_smstate(u16, buf, 0x7e70, seg.selector);
6288 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6289 put_smstate(u32, buf, 0x7e74, seg.limit);
6290 put_smstate(u64, buf, 0x7e78, seg.base);
6292 kvm_x86_ops->get_gdt(vcpu, &dt);
6293 put_smstate(u32, buf, 0x7e64, dt.size);
6294 put_smstate(u64, buf, 0x7e68, dt.address);
6296 for (i = 0; i < 6; i++)
6297 process_smi_save_seg_64(vcpu, buf, i);
6303 static void process_smi(struct kvm_vcpu *vcpu)
6305 struct kvm_segment cs, ds;
6311 vcpu->arch.smi_pending = true;
6315 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6316 vcpu->arch.hflags |= HF_SMM_MASK;
6317 memset(buf, 0, 512);
6318 if (guest_cpuid_has_longmode(vcpu))
6319 process_smi_save_state_64(vcpu, buf);
6321 process_smi_save_state_32(vcpu, buf);
6323 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
6325 if (kvm_x86_ops->get_nmi_mask(vcpu))
6326 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6328 kvm_x86_ops->set_nmi_mask(vcpu, true);
6330 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6331 kvm_rip_write(vcpu, 0x8000);
6333 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6334 kvm_x86_ops->set_cr0(vcpu, cr0);
6335 vcpu->arch.cr0 = cr0;
6337 kvm_x86_ops->set_cr4(vcpu, 0);
6339 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6340 dt.address = dt.size = 0;
6341 kvm_x86_ops->set_idt(vcpu, &dt);
6343 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6345 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6346 cs.base = vcpu->arch.smbase;
6351 cs.limit = ds.limit = 0xffffffff;
6352 cs.type = ds.type = 0x3;
6353 cs.dpl = ds.dpl = 0;
6358 cs.avl = ds.avl = 0;
6359 cs.present = ds.present = 1;
6360 cs.unusable = ds.unusable = 0;
6361 cs.padding = ds.padding = 0;
6363 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6364 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6365 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6366 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6367 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6368 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6370 if (guest_cpuid_has_longmode(vcpu))
6371 kvm_x86_ops->set_efer(vcpu, 0);
6373 kvm_update_cpuid(vcpu);
6374 kvm_mmu_reset_context(vcpu);
6377 void kvm_make_scan_ioapic_request(struct kvm *kvm)
6379 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6382 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6384 u64 eoi_exit_bitmap[4];
6386 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6389 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
6391 if (irqchip_split(vcpu->kvm))
6392 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
6394 if (vcpu->arch.apicv_active)
6395 kvm_x86_ops->sync_pir_to_irr(vcpu);
6396 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
6398 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6399 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6400 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6403 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6405 ++vcpu->stat.tlb_flush;
6406 kvm_x86_ops->tlb_flush(vcpu);
6409 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6411 struct page *page = NULL;
6413 if (!lapic_in_kernel(vcpu))
6416 if (!kvm_x86_ops->set_apic_access_page_addr)
6419 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6420 if (is_error_page(page))
6422 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6425 * Do not pin apic access page in memory, the MMU notifier
6426 * will call us again if it is migrated or swapped out.
6430 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6432 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6433 unsigned long address)
6436 * The physical address of apic access page is stored in the VMCS.
6437 * Update it when it becomes invalid.
6439 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6440 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6444 * Returns 1 to let vcpu_run() continue the guest execution loop without
6445 * exiting to the userspace. Otherwise, the value will be returned to the
6448 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6452 dm_request_for_irq_injection(vcpu) &&
6453 kvm_cpu_accept_dm_intr(vcpu);
6455 bool req_immediate_exit = false;
6457 if (vcpu->requests) {
6458 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6459 kvm_mmu_unload(vcpu);
6460 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6461 __kvm_migrate_timers(vcpu);
6462 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6463 kvm_gen_update_masterclock(vcpu->kvm);
6464 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6465 kvm_gen_kvmclock_update(vcpu);
6466 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6467 r = kvm_guest_time_update(vcpu);
6471 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6472 kvm_mmu_sync_roots(vcpu);
6473 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6474 kvm_vcpu_flush_tlb(vcpu);
6475 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6476 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6480 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6481 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6485 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6486 vcpu->fpu_active = 0;
6487 kvm_x86_ops->fpu_deactivate(vcpu);
6489 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6490 /* Page is swapped out. Do synthetic halt */
6491 vcpu->arch.apf.halted = true;
6495 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6496 record_steal_time(vcpu);
6497 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6499 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6501 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6502 kvm_pmu_handle_event(vcpu);
6503 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6504 kvm_pmu_deliver_pmi(vcpu);
6505 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6506 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6507 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6508 vcpu->arch.ioapic_handled_vectors)) {
6509 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6510 vcpu->run->eoi.vector =
6511 vcpu->arch.pending_ioapic_eoi;
6516 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6517 vcpu_scan_ioapic(vcpu);
6518 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6519 kvm_vcpu_reload_apic_access_page(vcpu);
6520 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6521 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6522 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6526 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6527 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6528 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6532 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6533 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6534 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6540 * KVM_REQ_HV_STIMER has to be processed after
6541 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6542 * depend on the guest clock being up-to-date
6544 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6545 kvm_hv_process_stimers(vcpu);
6549 * KVM_REQ_EVENT is not set when posted interrupts are set by
6550 * VT-d hardware, so we have to update RVI unconditionally.
6552 if (kvm_lapic_enabled(vcpu)) {
6554 * Update architecture specific hints for APIC
6555 * virtual interrupt delivery.
6557 if (vcpu->arch.apicv_active)
6558 kvm_x86_ops->hwapic_irr_update(vcpu,
6559 kvm_lapic_find_highest_irr(vcpu));
6562 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6563 kvm_apic_accept_events(vcpu);
6564 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6569 if (inject_pending_event(vcpu, req_int_win) != 0)
6570 req_immediate_exit = true;
6571 /* enable NMI/IRQ window open exits if needed */
6573 if (vcpu->arch.nmi_pending)
6574 kvm_x86_ops->enable_nmi_window(vcpu);
6575 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6576 kvm_x86_ops->enable_irq_window(vcpu);
6579 if (kvm_lapic_enabled(vcpu)) {
6580 update_cr8_intercept(vcpu);
6581 kvm_lapic_sync_to_vapic(vcpu);
6585 r = kvm_mmu_reload(vcpu);
6587 goto cancel_injection;
6592 kvm_x86_ops->prepare_guest_switch(vcpu);
6593 if (vcpu->fpu_active)
6594 kvm_load_guest_fpu(vcpu);
6595 vcpu->mode = IN_GUEST_MODE;
6597 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6600 * We should set ->mode before check ->requests,
6601 * Please see the comment in kvm_make_all_cpus_request.
6602 * This also orders the write to mode from any reads
6603 * to the page tables done while the VCPU is running.
6604 * Please see the comment in kvm_flush_remote_tlbs.
6606 smp_mb__after_srcu_read_unlock();
6608 local_irq_disable();
6610 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6611 || need_resched() || signal_pending(current)) {
6612 vcpu->mode = OUTSIDE_GUEST_MODE;
6616 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6618 goto cancel_injection;
6621 kvm_load_guest_xcr0(vcpu);
6623 if (req_immediate_exit)
6624 smp_send_reschedule(vcpu->cpu);
6626 trace_kvm_entry(vcpu->vcpu_id);
6627 wait_lapic_expire(vcpu);
6628 __kvm_guest_enter();
6630 if (unlikely(vcpu->arch.switch_db_regs)) {
6632 set_debugreg(vcpu->arch.eff_db[0], 0);
6633 set_debugreg(vcpu->arch.eff_db[1], 1);
6634 set_debugreg(vcpu->arch.eff_db[2], 2);
6635 set_debugreg(vcpu->arch.eff_db[3], 3);
6636 set_debugreg(vcpu->arch.dr6, 6);
6637 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6640 kvm_x86_ops->run(vcpu);
6643 * Do this here before restoring debug registers on the host. And
6644 * since we do this before handling the vmexit, a DR access vmexit
6645 * can (a) read the correct value of the debug registers, (b) set
6646 * KVM_DEBUGREG_WONT_EXIT again.
6648 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6649 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6650 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6651 kvm_update_dr0123(vcpu);
6652 kvm_update_dr6(vcpu);
6653 kvm_update_dr7(vcpu);
6654 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
6658 * If the guest has used debug registers, at least dr7
6659 * will be disabled while returning to the host.
6660 * If we don't have active breakpoints in the host, we don't
6661 * care about the messed up debug address registers. But if
6662 * we have some of them active, restore the old state.
6664 if (hw_breakpoint_active())
6665 hw_breakpoint_restore();
6667 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6669 vcpu->mode = OUTSIDE_GUEST_MODE;
6672 kvm_put_guest_xcr0(vcpu);
6674 /* Interrupt is enabled by handle_external_intr() */
6675 kvm_x86_ops->handle_external_intr(vcpu);
6680 * We must have an instruction between local_irq_enable() and
6681 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6682 * the interrupt shadow. The stat.exits increment will do nicely.
6683 * But we need to prevent reordering, hence this barrier():
6691 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6694 * Profile KVM exit RIPs:
6696 if (unlikely(prof_on == KVM_PROFILING)) {
6697 unsigned long rip = kvm_rip_read(vcpu);
6698 profile_hit(KVM_PROFILING, (void *)rip);
6701 if (unlikely(vcpu->arch.tsc_always_catchup))
6702 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6704 if (vcpu->arch.apic_attention)
6705 kvm_lapic_sync_from_vapic(vcpu);
6707 r = kvm_x86_ops->handle_exit(vcpu);
6711 kvm_x86_ops->cancel_injection(vcpu);
6712 if (unlikely(vcpu->arch.apic_attention))
6713 kvm_lapic_sync_from_vapic(vcpu);
6718 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6720 if (!kvm_arch_vcpu_runnable(vcpu) &&
6721 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
6722 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6723 kvm_vcpu_block(vcpu);
6724 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6726 if (kvm_x86_ops->post_block)
6727 kvm_x86_ops->post_block(vcpu);
6729 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6733 kvm_apic_accept_events(vcpu);
6734 switch(vcpu->arch.mp_state) {
6735 case KVM_MP_STATE_HALTED:
6736 vcpu->arch.pv.pv_unhalted = false;
6737 vcpu->arch.mp_state =
6738 KVM_MP_STATE_RUNNABLE;
6739 case KVM_MP_STATE_RUNNABLE:
6740 vcpu->arch.apf.halted = false;
6742 case KVM_MP_STATE_INIT_RECEIVED:
6751 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6753 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6754 !vcpu->arch.apf.halted);
6757 static int vcpu_run(struct kvm_vcpu *vcpu)
6760 struct kvm *kvm = vcpu->kvm;
6762 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6765 if (kvm_vcpu_running(vcpu)) {
6766 r = vcpu_enter_guest(vcpu);
6768 r = vcpu_block(kvm, vcpu);
6774 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6775 if (kvm_cpu_has_pending_timer(vcpu))
6776 kvm_inject_pending_timer_irqs(vcpu);
6778 if (dm_request_for_irq_injection(vcpu) &&
6779 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
6781 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
6782 ++vcpu->stat.request_irq_exits;
6786 kvm_check_async_pf_completion(vcpu);
6788 if (signal_pending(current)) {
6790 vcpu->run->exit_reason = KVM_EXIT_INTR;
6791 ++vcpu->stat.signal_exits;
6794 if (need_resched()) {
6795 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6797 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6801 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6806 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6809 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6810 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6811 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6812 if (r != EMULATE_DONE)
6817 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6819 BUG_ON(!vcpu->arch.pio.count);
6821 return complete_emulated_io(vcpu);
6825 * Implements the following, as a state machine:
6829 * for each mmio piece in the fragment
6837 * for each mmio piece in the fragment
6842 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6844 struct kvm_run *run = vcpu->run;
6845 struct kvm_mmio_fragment *frag;
6848 BUG_ON(!vcpu->mmio_needed);
6850 /* Complete previous fragment */
6851 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6852 len = min(8u, frag->len);
6853 if (!vcpu->mmio_is_write)
6854 memcpy(frag->data, run->mmio.data, len);
6856 if (frag->len <= 8) {
6857 /* Switch to the next fragment. */
6859 vcpu->mmio_cur_fragment++;
6861 /* Go forward to the next mmio piece. */
6867 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6868 vcpu->mmio_needed = 0;
6870 /* FIXME: return into emulator if single-stepping. */
6871 if (vcpu->mmio_is_write)
6873 vcpu->mmio_read_completed = 1;
6874 return complete_emulated_io(vcpu);
6877 run->exit_reason = KVM_EXIT_MMIO;
6878 run->mmio.phys_addr = frag->gpa;
6879 if (vcpu->mmio_is_write)
6880 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6881 run->mmio.len = min(8u, frag->len);
6882 run->mmio.is_write = vcpu->mmio_is_write;
6883 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6888 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6890 struct fpu *fpu = ¤t->thread.fpu;
6894 fpu__activate_curr(fpu);
6896 if (vcpu->sigset_active)
6897 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6899 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6900 kvm_vcpu_block(vcpu);
6901 kvm_apic_accept_events(vcpu);
6902 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6907 /* re-sync apic's tpr */
6908 if (!lapic_in_kernel(vcpu)) {
6909 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6915 if (unlikely(vcpu->arch.complete_userspace_io)) {
6916 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6917 vcpu->arch.complete_userspace_io = NULL;
6922 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6927 post_kvm_run_save(vcpu);
6928 if (vcpu->sigset_active)
6929 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6934 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6936 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6938 * We are here if userspace calls get_regs() in the middle of
6939 * instruction emulation. Registers state needs to be copied
6940 * back from emulation context to vcpu. Userspace shouldn't do
6941 * that usually, but some bad designed PV devices (vmware
6942 * backdoor interface) need this to work
6944 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6945 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6947 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6948 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6949 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6950 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6951 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6952 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6953 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6954 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6955 #ifdef CONFIG_X86_64
6956 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6957 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6958 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6959 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6960 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6961 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6962 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6963 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6966 regs->rip = kvm_rip_read(vcpu);
6967 regs->rflags = kvm_get_rflags(vcpu);
6972 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6974 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6975 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6977 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6978 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6979 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6980 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6981 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6982 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6983 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6984 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6985 #ifdef CONFIG_X86_64
6986 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6987 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6988 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6989 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6990 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6991 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6992 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6993 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6996 kvm_rip_write(vcpu, regs->rip);
6997 kvm_set_rflags(vcpu, regs->rflags);
6999 vcpu->arch.exception.pending = false;
7001 kvm_make_request(KVM_REQ_EVENT, vcpu);
7006 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7008 struct kvm_segment cs;
7010 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7014 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7016 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7017 struct kvm_sregs *sregs)
7021 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7022 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7023 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7024 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7025 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7026 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7028 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7029 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7031 kvm_x86_ops->get_idt(vcpu, &dt);
7032 sregs->idt.limit = dt.size;
7033 sregs->idt.base = dt.address;
7034 kvm_x86_ops->get_gdt(vcpu, &dt);
7035 sregs->gdt.limit = dt.size;
7036 sregs->gdt.base = dt.address;
7038 sregs->cr0 = kvm_read_cr0(vcpu);
7039 sregs->cr2 = vcpu->arch.cr2;
7040 sregs->cr3 = kvm_read_cr3(vcpu);
7041 sregs->cr4 = kvm_read_cr4(vcpu);
7042 sregs->cr8 = kvm_get_cr8(vcpu);
7043 sregs->efer = vcpu->arch.efer;
7044 sregs->apic_base = kvm_get_apic_base(vcpu);
7046 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
7048 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
7049 set_bit(vcpu->arch.interrupt.nr,
7050 (unsigned long *)sregs->interrupt_bitmap);
7055 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7056 struct kvm_mp_state *mp_state)
7058 kvm_apic_accept_events(vcpu);
7059 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7060 vcpu->arch.pv.pv_unhalted)
7061 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7063 mp_state->mp_state = vcpu->arch.mp_state;
7068 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7069 struct kvm_mp_state *mp_state)
7071 if (!lapic_in_kernel(vcpu) &&
7072 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7075 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7076 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7077 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7079 vcpu->arch.mp_state = mp_state->mp_state;
7080 kvm_make_request(KVM_REQ_EVENT, vcpu);
7084 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7085 int reason, bool has_error_code, u32 error_code)
7087 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7090 init_emulate_ctxt(vcpu);
7092 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
7093 has_error_code, error_code);
7096 return EMULATE_FAIL;
7098 kvm_rip_write(vcpu, ctxt->eip);
7099 kvm_set_rflags(vcpu, ctxt->eflags);
7100 kvm_make_request(KVM_REQ_EVENT, vcpu);
7101 return EMULATE_DONE;
7103 EXPORT_SYMBOL_GPL(kvm_task_switch);
7105 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7106 struct kvm_sregs *sregs)
7108 struct msr_data apic_base_msr;
7109 int mmu_reset_needed = 0;
7110 int pending_vec, max_bits, idx;
7113 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7116 dt.size = sregs->idt.limit;
7117 dt.address = sregs->idt.base;
7118 kvm_x86_ops->set_idt(vcpu, &dt);
7119 dt.size = sregs->gdt.limit;
7120 dt.address = sregs->gdt.base;
7121 kvm_x86_ops->set_gdt(vcpu, &dt);
7123 vcpu->arch.cr2 = sregs->cr2;
7124 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
7125 vcpu->arch.cr3 = sregs->cr3;
7126 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7128 kvm_set_cr8(vcpu, sregs->cr8);
7130 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
7131 kvm_x86_ops->set_efer(vcpu, sregs->efer);
7132 apic_base_msr.data = sregs->apic_base;
7133 apic_base_msr.host_initiated = true;
7134 kvm_set_apic_base(vcpu, &apic_base_msr);
7136 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
7137 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
7138 vcpu->arch.cr0 = sregs->cr0;
7140 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
7141 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7142 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
7143 kvm_update_cpuid(vcpu);
7145 idx = srcu_read_lock(&vcpu->kvm->srcu);
7146 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
7147 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7148 mmu_reset_needed = 1;
7150 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7152 if (mmu_reset_needed)
7153 kvm_mmu_reset_context(vcpu);
7155 max_bits = KVM_NR_INTERRUPTS;
7156 pending_vec = find_first_bit(
7157 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7158 if (pending_vec < max_bits) {
7159 kvm_queue_interrupt(vcpu, pending_vec, false);
7160 pr_debug("Set back pending irq %d\n", pending_vec);
7163 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7164 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7165 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7166 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7167 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7168 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
7170 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7171 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
7173 update_cr8_intercept(vcpu);
7175 /* Older userspace won't unhalt the vcpu on reset. */
7176 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
7177 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
7179 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7181 kvm_make_request(KVM_REQ_EVENT, vcpu);
7186 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7187 struct kvm_guest_debug *dbg)
7189 unsigned long rflags;
7192 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7194 if (vcpu->arch.exception.pending)
7196 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7197 kvm_queue_exception(vcpu, DB_VECTOR);
7199 kvm_queue_exception(vcpu, BP_VECTOR);
7203 * Read rflags as long as potentially injected trace flags are still
7206 rflags = kvm_get_rflags(vcpu);
7208 vcpu->guest_debug = dbg->control;
7209 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7210 vcpu->guest_debug = 0;
7212 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
7213 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7214 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
7215 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
7217 for (i = 0; i < KVM_NR_DB_REGS; i++)
7218 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
7220 kvm_update_dr7(vcpu);
7222 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7223 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7224 get_segment_base(vcpu, VCPU_SREG_CS);
7227 * Trigger an rflags update that will inject or remove the trace
7230 kvm_set_rflags(vcpu, rflags);
7232 kvm_x86_ops->update_bp_intercept(vcpu);
7242 * Translate a guest virtual address to a guest physical address.
7244 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7245 struct kvm_translation *tr)
7247 unsigned long vaddr = tr->linear_address;
7251 idx = srcu_read_lock(&vcpu->kvm->srcu);
7252 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
7253 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7254 tr->physical_address = gpa;
7255 tr->valid = gpa != UNMAPPED_GVA;
7262 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7264 struct fxregs_state *fxsave =
7265 &vcpu->arch.guest_fpu.state.fxsave;
7267 memcpy(fpu->fpr, fxsave->st_space, 128);
7268 fpu->fcw = fxsave->cwd;
7269 fpu->fsw = fxsave->swd;
7270 fpu->ftwx = fxsave->twd;
7271 fpu->last_opcode = fxsave->fop;
7272 fpu->last_ip = fxsave->rip;
7273 fpu->last_dp = fxsave->rdp;
7274 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7279 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7281 struct fxregs_state *fxsave =
7282 &vcpu->arch.guest_fpu.state.fxsave;
7284 memcpy(fxsave->st_space, fpu->fpr, 128);
7285 fxsave->cwd = fpu->fcw;
7286 fxsave->swd = fpu->fsw;
7287 fxsave->twd = fpu->ftwx;
7288 fxsave->fop = fpu->last_opcode;
7289 fxsave->rip = fpu->last_ip;
7290 fxsave->rdp = fpu->last_dp;
7291 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7296 static void fx_init(struct kvm_vcpu *vcpu)
7298 fpstate_init(&vcpu->arch.guest_fpu.state);
7300 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
7301 host_xcr0 | XSTATE_COMPACTION_ENABLED;
7304 * Ensure guest xcr0 is valid for loading
7306 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
7308 vcpu->arch.cr0 |= X86_CR0_ET;
7311 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7313 if (vcpu->guest_fpu_loaded)
7317 * Restore all possible states in the guest,
7318 * and assume host would use all available bits.
7319 * Guest xcr0 would be loaded later.
7321 vcpu->guest_fpu_loaded = 1;
7322 __kernel_fpu_begin();
7323 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
7327 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7329 if (!vcpu->guest_fpu_loaded) {
7330 vcpu->fpu_counter = 0;
7334 vcpu->guest_fpu_loaded = 0;
7335 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7337 ++vcpu->stat.fpu_reload;
7339 * If using eager FPU mode, or if the guest is a frequent user
7340 * of the FPU, just leave the FPU active for next time.
7341 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7342 * the FPU in bursts will revert to loading it on demand.
7344 if (!use_eager_fpu()) {
7345 if (++vcpu->fpu_counter < 5)
7346 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7351 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7353 kvmclock_reset(vcpu);
7355 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7356 kvm_x86_ops->vcpu_free(vcpu);
7359 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7362 struct kvm_vcpu *vcpu;
7364 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7365 printk_once(KERN_WARNING
7366 "kvm: SMP vm created on host with unstable TSC; "
7367 "guest TSC will not be reliable\n");
7369 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7374 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7378 kvm_vcpu_mtrr_init(vcpu);
7379 r = vcpu_load(vcpu);
7382 kvm_vcpu_reset(vcpu, false);
7383 kvm_mmu_setup(vcpu);
7388 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7390 struct msr_data msr;
7391 struct kvm *kvm = vcpu->kvm;
7393 if (vcpu_load(vcpu))
7396 msr.index = MSR_IA32_TSC;
7397 msr.host_initiated = true;
7398 kvm_write_tsc(vcpu, &msr);
7401 if (!kvmclock_periodic_sync)
7404 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7405 KVMCLOCK_SYNC_PERIOD);
7408 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7411 vcpu->arch.apf.msr_val = 0;
7413 r = vcpu_load(vcpu);
7415 kvm_mmu_unload(vcpu);
7418 kvm_x86_ops->vcpu_free(vcpu);
7421 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
7423 vcpu->arch.hflags = 0;
7425 atomic_set(&vcpu->arch.nmi_queued, 0);
7426 vcpu->arch.nmi_pending = 0;
7427 vcpu->arch.nmi_injected = false;
7428 kvm_clear_interrupt_queue(vcpu);
7429 kvm_clear_exception_queue(vcpu);
7431 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7432 kvm_update_dr0123(vcpu);
7433 vcpu->arch.dr6 = DR6_INIT;
7434 kvm_update_dr6(vcpu);
7435 vcpu->arch.dr7 = DR7_FIXED_1;
7436 kvm_update_dr7(vcpu);
7440 kvm_make_request(KVM_REQ_EVENT, vcpu);
7441 vcpu->arch.apf.msr_val = 0;
7442 vcpu->arch.st.msr_val = 0;
7444 kvmclock_reset(vcpu);
7446 kvm_clear_async_pf_completion_queue(vcpu);
7447 kvm_async_pf_hash_reset(vcpu);
7448 vcpu->arch.apf.halted = false;
7451 kvm_pmu_reset(vcpu);
7452 vcpu->arch.smbase = 0x30000;
7455 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7456 vcpu->arch.regs_avail = ~0;
7457 vcpu->arch.regs_dirty = ~0;
7459 kvm_x86_ops->vcpu_reset(vcpu, init_event);
7462 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7464 struct kvm_segment cs;
7466 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7467 cs.selector = vector << 8;
7468 cs.base = vector << 12;
7469 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7470 kvm_rip_write(vcpu, 0);
7473 int kvm_arch_hardware_enable(void)
7476 struct kvm_vcpu *vcpu;
7481 bool stable, backwards_tsc = false;
7483 kvm_shared_msr_cpu_online();
7484 ret = kvm_x86_ops->hardware_enable();
7488 local_tsc = rdtsc();
7489 stable = !check_tsc_unstable();
7490 list_for_each_entry(kvm, &vm_list, vm_list) {
7491 kvm_for_each_vcpu(i, vcpu, kvm) {
7492 if (!stable && vcpu->cpu == smp_processor_id())
7493 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7494 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7495 backwards_tsc = true;
7496 if (vcpu->arch.last_host_tsc > max_tsc)
7497 max_tsc = vcpu->arch.last_host_tsc;
7503 * Sometimes, even reliable TSCs go backwards. This happens on
7504 * platforms that reset TSC during suspend or hibernate actions, but
7505 * maintain synchronization. We must compensate. Fortunately, we can
7506 * detect that condition here, which happens early in CPU bringup,
7507 * before any KVM threads can be running. Unfortunately, we can't
7508 * bring the TSCs fully up to date with real time, as we aren't yet far
7509 * enough into CPU bringup that we know how much real time has actually
7510 * elapsed; our helper function, get_kernel_ns() will be using boot
7511 * variables that haven't been updated yet.
7513 * So we simply find the maximum observed TSC above, then record the
7514 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7515 * the adjustment will be applied. Note that we accumulate
7516 * adjustments, in case multiple suspend cycles happen before some VCPU
7517 * gets a chance to run again. In the event that no KVM threads get a
7518 * chance to run, we will miss the entire elapsed period, as we'll have
7519 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7520 * loose cycle time. This isn't too big a deal, since the loss will be
7521 * uniform across all VCPUs (not to mention the scenario is extremely
7522 * unlikely). It is possible that a second hibernate recovery happens
7523 * much faster than a first, causing the observed TSC here to be
7524 * smaller; this would require additional padding adjustment, which is
7525 * why we set last_host_tsc to the local tsc observed here.
7527 * N.B. - this code below runs only on platforms with reliable TSC,
7528 * as that is the only way backwards_tsc is set above. Also note
7529 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7530 * have the same delta_cyc adjustment applied if backwards_tsc
7531 * is detected. Note further, this adjustment is only done once,
7532 * as we reset last_host_tsc on all VCPUs to stop this from being
7533 * called multiple times (one for each physical CPU bringup).
7535 * Platforms with unreliable TSCs don't have to deal with this, they
7536 * will be compensated by the logic in vcpu_load, which sets the TSC to
7537 * catchup mode. This will catchup all VCPUs to real time, but cannot
7538 * guarantee that they stay in perfect synchronization.
7540 if (backwards_tsc) {
7541 u64 delta_cyc = max_tsc - local_tsc;
7542 backwards_tsc_observed = true;
7543 list_for_each_entry(kvm, &vm_list, vm_list) {
7544 kvm_for_each_vcpu(i, vcpu, kvm) {
7545 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7546 vcpu->arch.last_host_tsc = local_tsc;
7547 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7551 * We have to disable TSC offset matching.. if you were
7552 * booting a VM while issuing an S4 host suspend....
7553 * you may have some problem. Solving this issue is
7554 * left as an exercise to the reader.
7556 kvm->arch.last_tsc_nsec = 0;
7557 kvm->arch.last_tsc_write = 0;
7564 void kvm_arch_hardware_disable(void)
7566 kvm_x86_ops->hardware_disable();
7567 drop_user_return_notifiers();
7570 int kvm_arch_hardware_setup(void)
7574 r = kvm_x86_ops->hardware_setup();
7578 if (kvm_has_tsc_control) {
7580 * Make sure the user can only configure tsc_khz values that
7581 * fit into a signed integer.
7582 * A min value is not calculated needed because it will always
7583 * be 1 on all machines.
7585 u64 max = min(0x7fffffffULL,
7586 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7587 kvm_max_guest_tsc_khz = max;
7589 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
7592 kvm_init_msr_list();
7596 void kvm_arch_hardware_unsetup(void)
7598 kvm_x86_ops->hardware_unsetup();
7601 void kvm_arch_check_processor_compat(void *rtn)
7603 kvm_x86_ops->check_processor_compatibility(rtn);
7606 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7608 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7610 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7612 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7614 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
7617 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7619 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
7622 struct static_key kvm_no_apic_vcpu __read_mostly;
7623 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
7625 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7631 BUG_ON(vcpu->kvm == NULL);
7634 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
7635 vcpu->arch.pv.pv_unhalted = false;
7636 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7637 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
7638 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7640 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7642 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7647 vcpu->arch.pio_data = page_address(page);
7649 kvm_set_tsc_khz(vcpu, max_tsc_khz);
7651 r = kvm_mmu_create(vcpu);
7653 goto fail_free_pio_data;
7655 if (irqchip_in_kernel(kvm)) {
7656 r = kvm_create_lapic(vcpu);
7658 goto fail_mmu_destroy;
7660 static_key_slow_inc(&kvm_no_apic_vcpu);
7662 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7664 if (!vcpu->arch.mce_banks) {
7666 goto fail_free_lapic;
7668 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7670 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7672 goto fail_free_mce_banks;
7677 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7678 vcpu->arch.pv_time_enabled = false;
7680 vcpu->arch.guest_supported_xcr0 = 0;
7681 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7683 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7685 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7687 kvm_async_pf_hash_reset(vcpu);
7690 vcpu->arch.pending_external_vector = -1;
7692 kvm_hv_vcpu_init(vcpu);
7696 fail_free_mce_banks:
7697 kfree(vcpu->arch.mce_banks);
7699 kvm_free_lapic(vcpu);
7701 kvm_mmu_destroy(vcpu);
7703 free_page((unsigned long)vcpu->arch.pio_data);
7708 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7712 kvm_hv_vcpu_uninit(vcpu);
7713 kvm_pmu_destroy(vcpu);
7714 kfree(vcpu->arch.mce_banks);
7715 kvm_free_lapic(vcpu);
7716 idx = srcu_read_lock(&vcpu->kvm->srcu);
7717 kvm_mmu_destroy(vcpu);
7718 srcu_read_unlock(&vcpu->kvm->srcu, idx);
7719 free_page((unsigned long)vcpu->arch.pio_data);
7720 if (!lapic_in_kernel(vcpu))
7721 static_key_slow_dec(&kvm_no_apic_vcpu);
7724 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7726 kvm_x86_ops->sched_in(vcpu, cpu);
7729 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7734 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7735 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7736 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7737 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7738 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7740 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7741 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7742 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7743 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7744 &kvm->arch.irq_sources_bitmap);
7746 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7747 mutex_init(&kvm->arch.apic_map_lock);
7748 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7750 pvclock_update_vm_gtod_copy(kvm);
7752 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7753 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7755 kvm_page_track_init(kvm);
7756 kvm_mmu_init_vm(kvm);
7761 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7764 r = vcpu_load(vcpu);
7766 kvm_mmu_unload(vcpu);
7770 static void kvm_free_vcpus(struct kvm *kvm)
7773 struct kvm_vcpu *vcpu;
7776 * Unpin any mmu pages first.
7778 kvm_for_each_vcpu(i, vcpu, kvm) {
7779 kvm_clear_async_pf_completion_queue(vcpu);
7780 kvm_unload_vcpu_mmu(vcpu);
7782 kvm_for_each_vcpu(i, vcpu, kvm)
7783 kvm_arch_vcpu_free(vcpu);
7785 mutex_lock(&kvm->lock);
7786 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7787 kvm->vcpus[i] = NULL;
7789 atomic_set(&kvm->online_vcpus, 0);
7790 mutex_unlock(&kvm->lock);
7793 void kvm_arch_sync_events(struct kvm *kvm)
7795 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7796 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7797 kvm_free_all_assigned_devices(kvm);
7801 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7805 struct kvm_memslots *slots = kvm_memslots(kvm);
7806 struct kvm_memory_slot *slot, old;
7808 /* Called with kvm->slots_lock held. */
7809 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7812 slot = id_to_memslot(slots, id);
7814 if (WARN_ON(slot->npages))
7818 * MAP_SHARED to prevent internal slot pages from being moved
7821 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7822 MAP_SHARED | MAP_ANONYMOUS, 0);
7823 if (IS_ERR((void *)hva))
7824 return PTR_ERR((void *)hva);
7833 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7834 struct kvm_userspace_memory_region m;
7836 m.slot = id | (i << 16);
7838 m.guest_phys_addr = gpa;
7839 m.userspace_addr = hva;
7840 m.memory_size = size;
7841 r = __kvm_set_memory_region(kvm, &m);
7847 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7853 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7855 int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
7859 mutex_lock(&kvm->slots_lock);
7860 r = __x86_set_memory_region(kvm, id, gpa, size);
7861 mutex_unlock(&kvm->slots_lock);
7865 EXPORT_SYMBOL_GPL(x86_set_memory_region);
7867 void kvm_arch_destroy_vm(struct kvm *kvm)
7869 if (current->mm == kvm->mm) {
7871 * Free memory regions allocated on behalf of userspace,
7872 * unless the the memory map has changed due to process exit
7875 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7876 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7877 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
7879 kvm_iommu_unmap_guest(kvm);
7880 kfree(kvm->arch.vpic);
7881 kfree(kvm->arch.vioapic);
7882 kvm_free_vcpus(kvm);
7883 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7884 kvm_mmu_uninit_vm(kvm);
7887 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7888 struct kvm_memory_slot *dont)
7892 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7893 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7894 kvfree(free->arch.rmap[i]);
7895 free->arch.rmap[i] = NULL;
7900 if (!dont || free->arch.lpage_info[i - 1] !=
7901 dont->arch.lpage_info[i - 1]) {
7902 kvfree(free->arch.lpage_info[i - 1]);
7903 free->arch.lpage_info[i - 1] = NULL;
7907 kvm_page_track_free_memslot(free, dont);
7910 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7911 unsigned long npages)
7915 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7916 struct kvm_lpage_info *linfo;
7921 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7922 slot->base_gfn, level) + 1;
7924 slot->arch.rmap[i] =
7925 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7926 if (!slot->arch.rmap[i])
7931 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7935 slot->arch.lpage_info[i - 1] = linfo;
7937 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7938 linfo[0].disallow_lpage = 1;
7939 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7940 linfo[lpages - 1].disallow_lpage = 1;
7941 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7943 * If the gfn and userspace address are not aligned wrt each
7944 * other, or if explicitly asked to, disable large page
7945 * support for this slot
7947 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7948 !kvm_largepages_enabled()) {
7951 for (j = 0; j < lpages; ++j)
7952 linfo[j].disallow_lpage = 1;
7956 if (kvm_page_track_create_memslot(slot, npages))
7962 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7963 kvfree(slot->arch.rmap[i]);
7964 slot->arch.rmap[i] = NULL;
7968 kvfree(slot->arch.lpage_info[i - 1]);
7969 slot->arch.lpage_info[i - 1] = NULL;
7974 void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
7977 * memslots->generation has been incremented.
7978 * mmio generation may have reached its maximum value.
7980 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
7983 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7984 struct kvm_memory_slot *memslot,
7985 const struct kvm_userspace_memory_region *mem,
7986 enum kvm_mr_change change)
7991 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7992 struct kvm_memory_slot *new)
7994 /* Still write protect RO slot */
7995 if (new->flags & KVM_MEM_READONLY) {
7996 kvm_mmu_slot_remove_write_access(kvm, new);
8001 * Call kvm_x86_ops dirty logging hooks when they are valid.
8003 * kvm_x86_ops->slot_disable_log_dirty is called when:
8005 * - KVM_MR_CREATE with dirty logging is disabled
8006 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8008 * The reason is, in case of PML, we need to set D-bit for any slots
8009 * with dirty logging disabled in order to eliminate unnecessary GPA
8010 * logging in PML buffer (and potential PML buffer full VMEXT). This
8011 * guarantees leaving PML enabled during guest's lifetime won't have
8012 * any additonal overhead from PML when guest is running with dirty
8013 * logging disabled for memory slots.
8015 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8016 * to dirty logging mode.
8018 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8020 * In case of write protect:
8022 * Write protect all pages for dirty logging.
8024 * All the sptes including the large sptes which point to this
8025 * slot are set to readonly. We can not create any new large
8026 * spte on this slot until the end of the logging.
8028 * See the comments in fast_page_fault().
8030 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8031 if (kvm_x86_ops->slot_enable_log_dirty)
8032 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8034 kvm_mmu_slot_remove_write_access(kvm, new);
8036 if (kvm_x86_ops->slot_disable_log_dirty)
8037 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8041 void kvm_arch_commit_memory_region(struct kvm *kvm,
8042 const struct kvm_userspace_memory_region *mem,
8043 const struct kvm_memory_slot *old,
8044 const struct kvm_memory_slot *new,
8045 enum kvm_mr_change change)
8047 int nr_mmu_pages = 0;
8049 if (!kvm->arch.n_requested_mmu_pages)
8050 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8053 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
8056 * Dirty logging tracks sptes in 4k granularity, meaning that large
8057 * sptes have to be split. If live migration is successful, the guest
8058 * in the source machine will be destroyed and large sptes will be
8059 * created in the destination. However, if the guest continues to run
8060 * in the source machine (for example if live migration fails), small
8061 * sptes will remain around and cause bad performance.
8063 * Scan sptes if dirty logging has been stopped, dropping those
8064 * which can be collapsed into a single large-page spte. Later
8065 * page faults will create the large-page sptes.
8067 if ((change != KVM_MR_DELETE) &&
8068 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8069 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8070 kvm_mmu_zap_collapsible_sptes(kvm, new);
8073 * Set up write protection and/or dirty logging for the new slot.
8075 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8076 * been zapped so no dirty logging staff is needed for old slot. For
8077 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8078 * new and it's also covered when dealing with the new slot.
8080 * FIXME: const-ify all uses of struct kvm_memory_slot.
8082 if (change != KVM_MR_DELETE)
8083 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
8086 void kvm_arch_flush_shadow_all(struct kvm *kvm)
8088 kvm_mmu_invalidate_zap_all_pages(kvm);
8091 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8092 struct kvm_memory_slot *slot)
8094 kvm_mmu_invalidate_zap_all_pages(kvm);
8097 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8099 if (!list_empty_careful(&vcpu->async_pf.done))
8102 if (kvm_apic_has_events(vcpu))
8105 if (vcpu->arch.pv.pv_unhalted)
8108 if (atomic_read(&vcpu->arch.nmi_queued))
8111 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8114 if (kvm_arch_interrupt_allowed(vcpu) &&
8115 kvm_cpu_has_interrupt(vcpu))
8118 if (kvm_hv_has_stimer_pending(vcpu))
8124 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8126 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8127 kvm_x86_ops->check_nested_events(vcpu, false);
8129 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
8132 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
8134 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
8137 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8139 return kvm_x86_ops->interrupt_allowed(vcpu);
8142 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
8144 if (is_64_bit_mode(vcpu))
8145 return kvm_rip_read(vcpu);
8146 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8147 kvm_rip_read(vcpu));
8149 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
8151 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8153 return kvm_get_linear_rip(vcpu) == linear_rip;
8155 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8157 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8159 unsigned long rflags;
8161 rflags = kvm_x86_ops->get_rflags(vcpu);
8162 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8163 rflags &= ~X86_EFLAGS_TF;
8166 EXPORT_SYMBOL_GPL(kvm_get_rflags);
8168 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8170 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
8171 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
8172 rflags |= X86_EFLAGS_TF;
8173 kvm_x86_ops->set_rflags(vcpu, rflags);
8176 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8178 __kvm_set_rflags(vcpu, rflags);
8179 kvm_make_request(KVM_REQ_EVENT, vcpu);
8181 EXPORT_SYMBOL_GPL(kvm_set_rflags);
8183 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8187 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
8191 r = kvm_mmu_reload(vcpu);
8195 if (!vcpu->arch.mmu.direct_map &&
8196 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8199 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8202 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8204 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8207 static inline u32 kvm_async_pf_next_probe(u32 key)
8209 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8212 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8214 u32 key = kvm_async_pf_hash_fn(gfn);
8216 while (vcpu->arch.apf.gfns[key] != ~0)
8217 key = kvm_async_pf_next_probe(key);
8219 vcpu->arch.apf.gfns[key] = gfn;
8222 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8225 u32 key = kvm_async_pf_hash_fn(gfn);
8227 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
8228 (vcpu->arch.apf.gfns[key] != gfn &&
8229 vcpu->arch.apf.gfns[key] != ~0); i++)
8230 key = kvm_async_pf_next_probe(key);
8235 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8237 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8240 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8244 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8246 vcpu->arch.apf.gfns[i] = ~0;
8248 j = kvm_async_pf_next_probe(j);
8249 if (vcpu->arch.apf.gfns[j] == ~0)
8251 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8253 * k lies cyclically in ]i,j]
8255 * |....j i.k.| or |.k..j i...|
8257 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8258 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8263 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8266 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8270 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8271 struct kvm_async_pf *work)
8273 struct x86_exception fault;
8275 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
8276 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
8278 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
8279 (vcpu->arch.apf.send_user_only &&
8280 kvm_x86_ops->get_cpl(vcpu) == 0))
8281 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8282 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
8283 fault.vector = PF_VECTOR;
8284 fault.error_code_valid = true;
8285 fault.error_code = 0;
8286 fault.nested_page_fault = false;
8287 fault.address = work->arch.token;
8288 kvm_inject_page_fault(vcpu, &fault);
8292 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8293 struct kvm_async_pf *work)
8295 struct x86_exception fault;
8297 trace_kvm_async_pf_ready(work->arch.token, work->gva);
8298 if (work->wakeup_all)
8299 work->arch.token = ~0; /* broadcast wakeup */
8301 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8303 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8304 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8305 fault.vector = PF_VECTOR;
8306 fault.error_code_valid = true;
8307 fault.error_code = 0;
8308 fault.nested_page_fault = false;
8309 fault.address = work->arch.token;
8310 kvm_inject_page_fault(vcpu, &fault);
8312 vcpu->arch.apf.halted = false;
8313 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8316 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8318 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8321 return !kvm_event_needs_reinjection(vcpu) &&
8322 kvm_x86_ops->interrupt_allowed(vcpu);
8325 void kvm_arch_start_assignment(struct kvm *kvm)
8327 atomic_inc(&kvm->arch.assigned_device_count);
8329 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8331 void kvm_arch_end_assignment(struct kvm *kvm)
8333 atomic_dec(&kvm->arch.assigned_device_count);
8335 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8337 bool kvm_arch_has_assigned_device(struct kvm *kvm)
8339 return atomic_read(&kvm->arch.assigned_device_count);
8341 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8343 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8345 atomic_inc(&kvm->arch.noncoherent_dma_count);
8347 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8349 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8351 atomic_dec(&kvm->arch.noncoherent_dma_count);
8353 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8355 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8357 return atomic_read(&kvm->arch.noncoherent_dma_count);
8359 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8361 bool kvm_arch_has_irq_bypass(void)
8363 return kvm_x86_ops->update_pi_irte != NULL;
8366 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8367 struct irq_bypass_producer *prod)
8369 struct kvm_kernel_irqfd *irqfd =
8370 container_of(cons, struct kvm_kernel_irqfd, consumer);
8372 irqfd->producer = prod;
8374 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8375 prod->irq, irqfd->gsi, 1);
8378 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8379 struct irq_bypass_producer *prod)
8382 struct kvm_kernel_irqfd *irqfd =
8383 container_of(cons, struct kvm_kernel_irqfd, consumer);
8385 WARN_ON(irqfd->producer != prod);
8386 irqfd->producer = NULL;
8389 * When producer of consumer is unregistered, we change back to
8390 * remapped mode, so we can re-use the current implementation
8391 * when the irq is masked/disabed or the consumer side (KVM
8392 * int this case doesn't want to receive the interrupts.
8394 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8396 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8397 " fails: %d\n", irqfd->consumer.token, ret);
8400 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8401 uint32_t guest_irq, bool set)
8403 if (!kvm_x86_ops->update_pi_irte)
8406 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8409 bool kvm_vector_hashing_enabled(void)
8411 return vector_hashing;
8413 EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8415 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8416 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
8417 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8418 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8419 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8420 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
8421 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
8422 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
8423 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
8424 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
8425 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
8426 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
8427 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
8428 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
8429 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
8430 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
8431 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);