1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
32 #include <linux/clocksource.h>
33 #include <linux/interrupt.h>
34 #include <linux/kvm.h>
36 #include <linux/vmalloc.h>
37 #include <linux/export.h>
38 #include <linux/moduleparam.h>
39 #include <linux/mman.h>
40 #include <linux/highmem.h>
41 #include <linux/iommu.h>
42 #include <linux/intel-iommu.h>
43 #include <linux/cpufreq.h>
44 #include <linux/user-return-notifier.h>
45 #include <linux/srcu.h>
46 #include <linux/slab.h>
47 #include <linux/perf_event.h>
48 #include <linux/uaccess.h>
49 #include <linux/hash.h>
50 #include <linux/pci.h>
51 #include <linux/timekeeper_internal.h>
52 #include <linux/pvclock_gtod.h>
53 #include <linux/kvm_irqfd.h>
54 #include <linux/irqbypass.h>
55 #include <linux/sched/stat.h>
56 #include <linux/sched/isolation.h>
57 #include <linux/mem_encrypt.h>
59 #include <trace/events/kvm.h>
61 #include <asm/debugreg.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70 #include <asm/mshyperv.h>
71 #include <asm/hypervisor.h>
72 #include <asm/intel_pt.h>
73 #include <asm/emulate_prefix.h>
74 #include <clocksource/hyperv_timer.h>
76 #define CREATE_TRACE_POINTS
79 #define MAX_IO_MSRS 256
80 #define KVM_MAX_MCE_BANKS 32
81 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
82 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
84 #define emul_to_vcpu(ctxt) \
85 ((struct kvm_vcpu *)(ctxt)->vcpu)
88 * - enable syscall per default because its emulated by KVM
89 * - enable LME and LMA per default on 64 bit KVM
93 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
95 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
98 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
100 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
101 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
107 static void process_nmi(struct kvm_vcpu *vcpu);
108 static void enter_smm(struct kvm_vcpu *vcpu);
109 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
110 static void store_regs(struct kvm_vcpu *vcpu);
111 static int sync_regs(struct kvm_vcpu *vcpu);
113 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
114 EXPORT_SYMBOL_GPL(kvm_x86_ops);
116 static bool __read_mostly ignore_msrs = 0;
117 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
119 static bool __read_mostly report_ignored_msrs = true;
120 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
122 unsigned int min_timer_period_us = 200;
123 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
125 static bool __read_mostly kvmclock_periodic_sync = true;
126 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
128 bool __read_mostly kvm_has_tsc_control;
129 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
130 u32 __read_mostly kvm_max_guest_tsc_khz;
131 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
132 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
133 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
134 u64 __read_mostly kvm_max_tsc_scaling_ratio;
135 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
136 u64 __read_mostly kvm_default_tsc_scaling_ratio;
137 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
139 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
140 static u32 __read_mostly tsc_tolerance_ppm = 250;
141 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
144 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
145 * adaptive tuning starting from default advancment of 1000ns. '0' disables
146 * advancement entirely. Any other value is used as-is and disables adaptive
147 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
149 static int __read_mostly lapic_timer_advance_ns = -1;
150 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
152 static bool __read_mostly vector_hashing = true;
153 module_param(vector_hashing, bool, S_IRUGO);
155 bool __read_mostly enable_vmware_backdoor = false;
156 module_param(enable_vmware_backdoor, bool, S_IRUGO);
157 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
159 static bool __read_mostly force_emulation_prefix = false;
160 module_param(force_emulation_prefix, bool, S_IRUGO);
162 int __read_mostly pi_inject_timer = -1;
163 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
165 #define KVM_NR_SHARED_MSRS 16
167 struct kvm_shared_msrs_global {
169 u32 msrs[KVM_NR_SHARED_MSRS];
172 struct kvm_shared_msrs {
173 struct user_return_notifier urn;
175 struct kvm_shared_msr_values {
178 } values[KVM_NR_SHARED_MSRS];
181 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
182 static struct kvm_shared_msrs __percpu *shared_msrs;
184 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
185 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
186 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
187 | XFEATURE_MASK_PKRU)
189 u64 __read_mostly host_efer;
190 EXPORT_SYMBOL_GPL(host_efer);
192 static u64 __read_mostly host_xss;
193 u64 __read_mostly supported_xss;
194 EXPORT_SYMBOL_GPL(supported_xss);
196 struct kvm_stats_debugfs_item debugfs_entries[] = {
197 { "pf_fixed", VCPU_STAT(pf_fixed) },
198 { "pf_guest", VCPU_STAT(pf_guest) },
199 { "tlb_flush", VCPU_STAT(tlb_flush) },
200 { "invlpg", VCPU_STAT(invlpg) },
201 { "exits", VCPU_STAT(exits) },
202 { "io_exits", VCPU_STAT(io_exits) },
203 { "mmio_exits", VCPU_STAT(mmio_exits) },
204 { "signal_exits", VCPU_STAT(signal_exits) },
205 { "irq_window", VCPU_STAT(irq_window_exits) },
206 { "nmi_window", VCPU_STAT(nmi_window_exits) },
207 { "halt_exits", VCPU_STAT(halt_exits) },
208 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
209 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
210 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
211 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
212 { "hypercalls", VCPU_STAT(hypercalls) },
213 { "request_irq", VCPU_STAT(request_irq_exits) },
214 { "irq_exits", VCPU_STAT(irq_exits) },
215 { "host_state_reload", VCPU_STAT(host_state_reload) },
216 { "fpu_reload", VCPU_STAT(fpu_reload) },
217 { "insn_emulation", VCPU_STAT(insn_emulation) },
218 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
219 { "irq_injections", VCPU_STAT(irq_injections) },
220 { "nmi_injections", VCPU_STAT(nmi_injections) },
221 { "req_event", VCPU_STAT(req_event) },
222 { "l1d_flush", VCPU_STAT(l1d_flush) },
223 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
224 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
225 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
226 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
227 { "mmu_flooded", VM_STAT(mmu_flooded) },
228 { "mmu_recycled", VM_STAT(mmu_recycled) },
229 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
230 { "mmu_unsync", VM_STAT(mmu_unsync) },
231 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
232 { "largepages", VM_STAT(lpages, .mode = 0444) },
233 { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
234 { "max_mmu_page_hash_collisions",
235 VM_STAT(max_mmu_page_hash_collisions) },
239 u64 __read_mostly host_xcr0;
240 u64 __read_mostly supported_xcr0;
241 EXPORT_SYMBOL_GPL(supported_xcr0);
243 struct kmem_cache *x86_fpu_cache;
244 EXPORT_SYMBOL_GPL(x86_fpu_cache);
246 static struct kmem_cache *x86_emulator_cache;
248 static struct kmem_cache *kvm_alloc_emulator_cache(void)
250 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
251 unsigned int size = sizeof(struct x86_emulate_ctxt);
253 return kmem_cache_create_usercopy("x86_emulator", size,
254 __alignof__(struct x86_emulate_ctxt),
255 SLAB_ACCOUNT, useroffset,
256 size - useroffset, NULL);
259 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
261 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
264 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
265 vcpu->arch.apf.gfns[i] = ~0;
268 static void kvm_on_user_return(struct user_return_notifier *urn)
271 struct kvm_shared_msrs *locals
272 = container_of(urn, struct kvm_shared_msrs, urn);
273 struct kvm_shared_msr_values *values;
277 * Disabling irqs at this point since the following code could be
278 * interrupted and executed through kvm_arch_hardware_disable()
280 local_irq_save(flags);
281 if (locals->registered) {
282 locals->registered = false;
283 user_return_notifier_unregister(urn);
285 local_irq_restore(flags);
286 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
287 values = &locals->values[slot];
288 if (values->host != values->curr) {
289 wrmsrl(shared_msrs_global.msrs[slot], values->host);
290 values->curr = values->host;
295 void kvm_define_shared_msr(unsigned slot, u32 msr)
297 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
298 shared_msrs_global.msrs[slot] = msr;
299 if (slot >= shared_msrs_global.nr)
300 shared_msrs_global.nr = slot + 1;
302 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
304 static void kvm_shared_msr_cpu_online(void)
306 unsigned int cpu = smp_processor_id();
307 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
311 for (i = 0; i < shared_msrs_global.nr; ++i) {
312 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
313 smsr->values[i].host = value;
314 smsr->values[i].curr = value;
318 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
324 value = (value & mask) | (smsr->values[slot].host & ~mask);
325 if (value == smsr->values[slot].curr)
327 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
331 smsr->values[slot].curr = value;
332 if (!smsr->registered) {
333 smsr->urn.on_user_return = kvm_on_user_return;
334 user_return_notifier_register(&smsr->urn);
335 smsr->registered = true;
339 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
341 static void drop_user_return_notifiers(void)
343 unsigned int cpu = smp_processor_id();
344 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
346 if (smsr->registered)
347 kvm_on_user_return(&smsr->urn);
350 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
352 return vcpu->arch.apic_base;
354 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
356 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
358 return kvm_apic_mode(kvm_get_apic_base(vcpu));
360 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
362 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
364 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
365 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
366 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
367 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
369 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
371 if (!msr_info->host_initiated) {
372 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
374 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
378 kvm_lapic_set_base(vcpu, msr_info->data);
379 kvm_recalculate_apic_map(vcpu->kvm);
382 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
384 asmlinkage __visible void kvm_spurious_fault(void)
386 /* Fault while not rebooting. We want the trace. */
387 BUG_ON(!kvm_rebooting);
389 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
391 #define EXCPT_BENIGN 0
392 #define EXCPT_CONTRIBUTORY 1
395 static int exception_class(int vector)
405 return EXCPT_CONTRIBUTORY;
412 #define EXCPT_FAULT 0
414 #define EXCPT_ABORT 2
415 #define EXCPT_INTERRUPT 3
417 static int exception_type(int vector)
421 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
422 return EXCPT_INTERRUPT;
426 /* #DB is trap, as instruction watchpoints are handled elsewhere */
427 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
430 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
433 /* Reserved exceptions will result in fault */
437 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
439 unsigned nr = vcpu->arch.exception.nr;
440 bool has_payload = vcpu->arch.exception.has_payload;
441 unsigned long payload = vcpu->arch.exception.payload;
449 * "Certain debug exceptions may clear bit 0-3. The
450 * remaining contents of the DR6 register are never
451 * cleared by the processor".
453 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
455 * DR6.RTM is set by all #DB exceptions that don't clear it.
457 vcpu->arch.dr6 |= DR6_RTM;
458 vcpu->arch.dr6 |= payload;
460 * Bit 16 should be set in the payload whenever the #DB
461 * exception should clear DR6.RTM. This makes the payload
462 * compatible with the pending debug exceptions under VMX.
463 * Though not currently documented in the SDM, this also
464 * makes the payload compatible with the exit qualification
465 * for #DB exceptions under VMX.
467 vcpu->arch.dr6 ^= payload & DR6_RTM;
470 * The #DB payload is defined as compatible with the 'pending
471 * debug exceptions' field under VMX, not DR6. While bit 12 is
472 * defined in the 'pending debug exceptions' field (enabled
473 * breakpoint), it is reserved and must be zero in DR6.
475 vcpu->arch.dr6 &= ~BIT(12);
478 vcpu->arch.cr2 = payload;
482 vcpu->arch.exception.has_payload = false;
483 vcpu->arch.exception.payload = 0;
485 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
487 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
488 unsigned nr, bool has_error, u32 error_code,
489 bool has_payload, unsigned long payload, bool reinject)
494 kvm_make_request(KVM_REQ_EVENT, vcpu);
496 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
498 if (has_error && !is_protmode(vcpu))
502 * On vmentry, vcpu->arch.exception.pending is only
503 * true if an event injection was blocked by
504 * nested_run_pending. In that case, however,
505 * vcpu_enter_guest requests an immediate exit,
506 * and the guest shouldn't proceed far enough to
509 WARN_ON_ONCE(vcpu->arch.exception.pending);
510 vcpu->arch.exception.injected = true;
511 if (WARN_ON_ONCE(has_payload)) {
513 * A reinjected event has already
514 * delivered its payload.
520 vcpu->arch.exception.pending = true;
521 vcpu->arch.exception.injected = false;
523 vcpu->arch.exception.has_error_code = has_error;
524 vcpu->arch.exception.nr = nr;
525 vcpu->arch.exception.error_code = error_code;
526 vcpu->arch.exception.has_payload = has_payload;
527 vcpu->arch.exception.payload = payload;
528 if (!is_guest_mode(vcpu))
529 kvm_deliver_exception_payload(vcpu);
533 /* to check exception */
534 prev_nr = vcpu->arch.exception.nr;
535 if (prev_nr == DF_VECTOR) {
536 /* triple fault -> shutdown */
537 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
540 class1 = exception_class(prev_nr);
541 class2 = exception_class(nr);
542 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
543 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
545 * Generate double fault per SDM Table 5-5. Set
546 * exception.pending = true so that the double fault
547 * can trigger a nested vmexit.
549 vcpu->arch.exception.pending = true;
550 vcpu->arch.exception.injected = false;
551 vcpu->arch.exception.has_error_code = true;
552 vcpu->arch.exception.nr = DF_VECTOR;
553 vcpu->arch.exception.error_code = 0;
554 vcpu->arch.exception.has_payload = false;
555 vcpu->arch.exception.payload = 0;
557 /* replace previous exception with a new one in a hope
558 that instruction re-execution will regenerate lost
563 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
565 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
567 EXPORT_SYMBOL_GPL(kvm_queue_exception);
569 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
571 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
573 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
575 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
576 unsigned long payload)
578 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
581 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
582 u32 error_code, unsigned long payload)
584 kvm_multiple_exception(vcpu, nr, true, error_code,
585 true, payload, false);
588 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
591 kvm_inject_gp(vcpu, 0);
593 return kvm_skip_emulated_instruction(vcpu);
597 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
599 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
601 ++vcpu->stat.pf_guest;
602 vcpu->arch.exception.nested_apf =
603 is_guest_mode(vcpu) && fault->async_page_fault;
604 if (vcpu->arch.exception.nested_apf) {
605 vcpu->arch.apf.nested_apf_token = fault->address;
606 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
608 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
612 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
614 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
616 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
617 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
619 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
621 return fault->nested_page_fault;
624 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
626 atomic_inc(&vcpu->arch.nmi_queued);
627 kvm_make_request(KVM_REQ_NMI, vcpu);
629 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
631 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
633 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
635 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
637 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
639 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
641 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
644 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
645 * a #GP and return false.
647 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
649 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
651 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
654 EXPORT_SYMBOL_GPL(kvm_require_cpl);
656 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
658 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
661 kvm_queue_exception(vcpu, UD_VECTOR);
664 EXPORT_SYMBOL_GPL(kvm_require_dr);
667 * This function will be used to read from the physical memory of the currently
668 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
669 * can read from guest physical or from the guest's guest physical memory.
671 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
672 gfn_t ngfn, void *data, int offset, int len,
675 struct x86_exception exception;
679 ngpa = gfn_to_gpa(ngfn);
680 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
681 if (real_gfn == UNMAPPED_GVA)
684 real_gfn = gpa_to_gfn(real_gfn);
686 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
688 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
690 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
691 void *data, int offset, int len, u32 access)
693 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
694 data, offset, len, access);
697 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
699 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
704 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
706 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
708 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
709 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
712 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
714 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
715 offset * sizeof(u64), sizeof(pdpte),
716 PFERR_USER_MASK|PFERR_WRITE_MASK);
721 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
722 if ((pdpte[i] & PT_PRESENT_MASK) &&
723 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
730 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
731 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
737 EXPORT_SYMBOL_GPL(load_pdptrs);
739 bool pdptrs_changed(struct kvm_vcpu *vcpu)
741 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
746 if (!is_pae_paging(vcpu))
749 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
752 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
753 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
754 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
755 PFERR_USER_MASK | PFERR_WRITE_MASK);
759 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
761 EXPORT_SYMBOL_GPL(pdptrs_changed);
763 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
765 unsigned long old_cr0 = kvm_read_cr0(vcpu);
766 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
771 if (cr0 & 0xffffffff00000000UL)
775 cr0 &= ~CR0_RESERVED_BITS;
777 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
780 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
783 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
785 if ((vcpu->arch.efer & EFER_LME)) {
790 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
795 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
800 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
803 kvm_x86_ops->set_cr0(vcpu, cr0);
805 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
806 kvm_clear_async_pf_completion_queue(vcpu);
807 kvm_async_pf_hash_reset(vcpu);
810 if ((cr0 ^ old_cr0) & update_bits)
811 kvm_mmu_reset_context(vcpu);
813 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
814 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
815 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
816 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
820 EXPORT_SYMBOL_GPL(kvm_set_cr0);
822 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
824 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
826 EXPORT_SYMBOL_GPL(kvm_lmsw);
828 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
830 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
832 if (vcpu->arch.xcr0 != host_xcr0)
833 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
835 if (vcpu->arch.xsaves_enabled &&
836 vcpu->arch.ia32_xss != host_xss)
837 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
840 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
842 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
844 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
846 if (vcpu->arch.xcr0 != host_xcr0)
847 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
849 if (vcpu->arch.xsaves_enabled &&
850 vcpu->arch.ia32_xss != host_xss)
851 wrmsrl(MSR_IA32_XSS, host_xss);
855 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
857 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
860 u64 old_xcr0 = vcpu->arch.xcr0;
863 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
864 if (index != XCR_XFEATURE_ENABLED_MASK)
866 if (!(xcr0 & XFEATURE_MASK_FP))
868 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
872 * Do not allow the guest to set bits that we do not support
873 * saving. However, xcr0 bit 0 is always set, even if the
874 * emulated CPU does not support XSAVE (see fx_init).
876 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
877 if (xcr0 & ~valid_bits)
880 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
881 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
884 if (xcr0 & XFEATURE_MASK_AVX512) {
885 if (!(xcr0 & XFEATURE_MASK_YMM))
887 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
890 vcpu->arch.xcr0 = xcr0;
892 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
893 kvm_update_cpuid(vcpu);
897 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
899 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
900 __kvm_set_xcr(vcpu, index, xcr)) {
901 kvm_inject_gp(vcpu, 0);
906 EXPORT_SYMBOL_GPL(kvm_set_xcr);
908 #define __cr4_reserved_bits(__cpu_has, __c) \
910 u64 __reserved_bits = CR4_RESERVED_BITS; \
912 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
913 __reserved_bits |= X86_CR4_OSXSAVE; \
914 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
915 __reserved_bits |= X86_CR4_SMEP; \
916 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
917 __reserved_bits |= X86_CR4_SMAP; \
918 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
919 __reserved_bits |= X86_CR4_FSGSBASE; \
920 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
921 __reserved_bits |= X86_CR4_PKE; \
922 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
923 __reserved_bits |= X86_CR4_LA57; \
924 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
925 __reserved_bits |= X86_CR4_UMIP; \
929 static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c)
931 u64 reserved_bits = __cr4_reserved_bits(cpu_has, c);
933 if (kvm_cpu_cap_has(X86_FEATURE_LA57))
934 reserved_bits &= ~X86_CR4_LA57;
936 if (kvm_cpu_cap_has(X86_FEATURE_UMIP))
937 reserved_bits &= ~X86_CR4_UMIP;
939 return reserved_bits;
942 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
944 if (cr4 & cr4_reserved_bits)
947 if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
953 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
955 unsigned long old_cr4 = kvm_read_cr4(vcpu);
956 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
957 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
959 if (kvm_valid_cr4(vcpu, cr4))
962 if (is_long_mode(vcpu)) {
963 if (!(cr4 & X86_CR4_PAE))
965 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
966 && ((cr4 ^ old_cr4) & pdptr_bits)
967 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
971 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
972 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
975 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
976 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
980 if (kvm_x86_ops->set_cr4(vcpu, cr4))
983 if (((cr4 ^ old_cr4) & pdptr_bits) ||
984 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
985 kvm_mmu_reset_context(vcpu);
987 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
988 kvm_update_cpuid(vcpu);
992 EXPORT_SYMBOL_GPL(kvm_set_cr4);
994 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
996 bool skip_tlb_flush = false;
998 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1001 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1002 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1006 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1007 if (!skip_tlb_flush) {
1008 kvm_mmu_sync_roots(vcpu);
1009 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1014 if (is_long_mode(vcpu) &&
1015 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1017 else if (is_pae_paging(vcpu) &&
1018 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1021 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
1022 vcpu->arch.cr3 = cr3;
1023 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1027 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1029 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1031 if (cr8 & CR8_RESERVED_BITS)
1033 if (lapic_in_kernel(vcpu))
1034 kvm_lapic_set_tpr(vcpu, cr8);
1036 vcpu->arch.cr8 = cr8;
1039 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1041 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1043 if (lapic_in_kernel(vcpu))
1044 return kvm_lapic_get_cr8(vcpu);
1046 return vcpu->arch.cr8;
1048 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1050 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1054 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1055 for (i = 0; i < KVM_NR_DB_REGS; i++)
1056 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1057 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1061 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1063 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1064 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1067 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1071 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1072 dr7 = vcpu->arch.guest_debug_dr7;
1074 dr7 = vcpu->arch.dr7;
1075 kvm_x86_ops->set_dr7(vcpu, dr7);
1076 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1077 if (dr7 & DR7_BP_EN_MASK)
1078 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1081 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1083 u64 fixed = DR6_FIXED_1;
1085 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1090 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1092 size_t size = ARRAY_SIZE(vcpu->arch.db);
1096 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1097 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1098 vcpu->arch.eff_db[dr] = val;
1103 if (val & 0xffffffff00000000ULL)
1104 return -1; /* #GP */
1105 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1106 kvm_update_dr6(vcpu);
1111 if (!kvm_dr7_valid(val))
1112 return -1; /* #GP */
1113 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1114 kvm_update_dr7(vcpu);
1121 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1123 if (__kvm_set_dr(vcpu, dr, val)) {
1124 kvm_inject_gp(vcpu, 0);
1129 EXPORT_SYMBOL_GPL(kvm_set_dr);
1131 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1133 size_t size = ARRAY_SIZE(vcpu->arch.db);
1137 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1142 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1143 *val = vcpu->arch.dr6;
1145 *val = kvm_x86_ops->get_dr6(vcpu);
1150 *val = vcpu->arch.dr7;
1155 EXPORT_SYMBOL_GPL(kvm_get_dr);
1157 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1159 u32 ecx = kvm_rcx_read(vcpu);
1163 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1166 kvm_rax_write(vcpu, (u32)data);
1167 kvm_rdx_write(vcpu, data >> 32);
1170 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1173 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1174 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1176 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1177 * extract the supported MSRs from the related const lists.
1178 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1179 * capabilities of the host cpu. This capabilities test skips MSRs that are
1180 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1181 * may depend on host virtualization features rather than host cpu features.
1184 static const u32 msrs_to_save_all[] = {
1185 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1187 #ifdef CONFIG_X86_64
1188 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1190 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1191 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1193 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1194 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1195 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1196 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1197 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1198 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1199 MSR_IA32_UMWAIT_CONTROL,
1201 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1202 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1203 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1204 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1205 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1206 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1207 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1208 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1209 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1210 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1211 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1212 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1213 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1214 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1215 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1216 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1217 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1218 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1219 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1220 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1221 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1222 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1225 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1226 static unsigned num_msrs_to_save;
1228 static const u32 emulated_msrs_all[] = {
1229 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1230 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1231 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1232 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1233 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1234 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1235 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1237 HV_X64_MSR_VP_INDEX,
1238 HV_X64_MSR_VP_RUNTIME,
1239 HV_X64_MSR_SCONTROL,
1240 HV_X64_MSR_STIMER0_CONFIG,
1241 HV_X64_MSR_VP_ASSIST_PAGE,
1242 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1243 HV_X64_MSR_TSC_EMULATION_STATUS,
1245 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1248 MSR_IA32_TSC_ADJUST,
1249 MSR_IA32_TSCDEADLINE,
1250 MSR_IA32_ARCH_CAPABILITIES,
1251 MSR_IA32_MISC_ENABLE,
1252 MSR_IA32_MCG_STATUS,
1254 MSR_IA32_MCG_EXT_CTL,
1258 MSR_MISC_FEATURES_ENABLES,
1259 MSR_AMD64_VIRT_SPEC_CTRL,
1264 * The following list leaves out MSRs whose values are determined
1265 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1266 * We always support the "true" VMX control MSRs, even if the host
1267 * processor does not, so I am putting these registers here rather
1268 * than in msrs_to_save_all.
1271 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1272 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1273 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1274 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1276 MSR_IA32_VMX_CR0_FIXED0,
1277 MSR_IA32_VMX_CR4_FIXED0,
1278 MSR_IA32_VMX_VMCS_ENUM,
1279 MSR_IA32_VMX_PROCBASED_CTLS2,
1280 MSR_IA32_VMX_EPT_VPID_CAP,
1281 MSR_IA32_VMX_VMFUNC,
1284 MSR_KVM_POLL_CONTROL,
1287 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1288 static unsigned num_emulated_msrs;
1291 * List of msr numbers which are used to expose MSR-based features that
1292 * can be used by a hypervisor to validate requested CPU features.
1294 static const u32 msr_based_features_all[] = {
1296 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1297 MSR_IA32_VMX_PINBASED_CTLS,
1298 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1299 MSR_IA32_VMX_PROCBASED_CTLS,
1300 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1301 MSR_IA32_VMX_EXIT_CTLS,
1302 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1303 MSR_IA32_VMX_ENTRY_CTLS,
1305 MSR_IA32_VMX_CR0_FIXED0,
1306 MSR_IA32_VMX_CR0_FIXED1,
1307 MSR_IA32_VMX_CR4_FIXED0,
1308 MSR_IA32_VMX_CR4_FIXED1,
1309 MSR_IA32_VMX_VMCS_ENUM,
1310 MSR_IA32_VMX_PROCBASED_CTLS2,
1311 MSR_IA32_VMX_EPT_VPID_CAP,
1312 MSR_IA32_VMX_VMFUNC,
1316 MSR_IA32_ARCH_CAPABILITIES,
1319 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1320 static unsigned int num_msr_based_features;
1322 static u64 kvm_get_arch_capabilities(void)
1326 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1327 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1330 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1331 * the nested hypervisor runs with NX huge pages. If it is not,
1332 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1333 * L1 guests, so it need not worry about its own (L2) guests.
1335 data |= ARCH_CAP_PSCHANGE_MC_NO;
1338 * If we're doing cache flushes (either "always" or "cond")
1339 * we will do one whenever the guest does a vmlaunch/vmresume.
1340 * If an outer hypervisor is doing the cache flush for us
1341 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1342 * capability to the guest too, and if EPT is disabled we're not
1343 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1344 * require a nested hypervisor to do a flush of its own.
1346 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1347 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1349 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1350 data |= ARCH_CAP_RDCL_NO;
1351 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1352 data |= ARCH_CAP_SSB_NO;
1353 if (!boot_cpu_has_bug(X86_BUG_MDS))
1354 data |= ARCH_CAP_MDS_NO;
1357 * On TAA affected systems:
1358 * - nothing to do if TSX is disabled on the host.
1359 * - we emulate TSX_CTRL if present on the host.
1360 * This lets the guest use VERW to clear CPU buffers.
1362 if (!boot_cpu_has(X86_FEATURE_RTM))
1363 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1364 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1365 data |= ARCH_CAP_TAA_NO;
1370 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1372 switch (msr->index) {
1373 case MSR_IA32_ARCH_CAPABILITIES:
1374 msr->data = kvm_get_arch_capabilities();
1376 case MSR_IA32_UCODE_REV:
1377 rdmsrl_safe(msr->index, &msr->data);
1380 if (kvm_x86_ops->get_msr_feature(msr))
1386 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1388 struct kvm_msr_entry msr;
1392 r = kvm_get_msr_feature(&msr);
1401 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1403 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1406 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1409 if (efer & (EFER_LME | EFER_LMA) &&
1410 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1413 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1419 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1421 if (efer & efer_reserved_bits)
1424 return __kvm_valid_efer(vcpu, efer);
1426 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1428 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1430 u64 old_efer = vcpu->arch.efer;
1431 u64 efer = msr_info->data;
1433 if (efer & efer_reserved_bits)
1436 if (!msr_info->host_initiated) {
1437 if (!__kvm_valid_efer(vcpu, efer))
1440 if (is_paging(vcpu) &&
1441 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1446 efer |= vcpu->arch.efer & EFER_LMA;
1448 kvm_x86_ops->set_efer(vcpu, efer);
1450 /* Update reserved bits */
1451 if ((efer ^ old_efer) & EFER_NX)
1452 kvm_mmu_reset_context(vcpu);
1457 void kvm_enable_efer_bits(u64 mask)
1459 efer_reserved_bits &= ~mask;
1461 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1464 * Write @data into the MSR specified by @index. Select MSR specific fault
1465 * checks are bypassed if @host_initiated is %true.
1466 * Returns 0 on success, non-0 otherwise.
1467 * Assumes vcpu_load() was already called.
1469 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1470 bool host_initiated)
1472 struct msr_data msr;
1477 case MSR_KERNEL_GS_BASE:
1480 if (is_noncanonical_address(data, vcpu))
1483 case MSR_IA32_SYSENTER_EIP:
1484 case MSR_IA32_SYSENTER_ESP:
1486 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1487 * non-canonical address is written on Intel but not on
1488 * AMD (which ignores the top 32-bits, because it does
1489 * not implement 64-bit SYSENTER).
1491 * 64-bit code should hence be able to write a non-canonical
1492 * value on AMD. Making the address canonical ensures that
1493 * vmentry does not fail on Intel after writing a non-canonical
1494 * value, and that something deterministic happens if the guest
1495 * invokes 64-bit SYSENTER.
1497 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1502 msr.host_initiated = host_initiated;
1504 return kvm_x86_ops->set_msr(vcpu, &msr);
1508 * Read the MSR specified by @index into @data. Select MSR specific fault
1509 * checks are bypassed if @host_initiated is %true.
1510 * Returns 0 on success, non-0 otherwise.
1511 * Assumes vcpu_load() was already called.
1513 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1514 bool host_initiated)
1516 struct msr_data msr;
1520 msr.host_initiated = host_initiated;
1522 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1528 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1530 return __kvm_get_msr(vcpu, index, data, false);
1532 EXPORT_SYMBOL_GPL(kvm_get_msr);
1534 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1536 return __kvm_set_msr(vcpu, index, data, false);
1538 EXPORT_SYMBOL_GPL(kvm_set_msr);
1540 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1542 u32 ecx = kvm_rcx_read(vcpu);
1545 if (kvm_get_msr(vcpu, ecx, &data)) {
1546 trace_kvm_msr_read_ex(ecx);
1547 kvm_inject_gp(vcpu, 0);
1551 trace_kvm_msr_read(ecx, data);
1553 kvm_rax_write(vcpu, data & -1u);
1554 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1555 return kvm_skip_emulated_instruction(vcpu);
1557 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1559 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1561 u32 ecx = kvm_rcx_read(vcpu);
1562 u64 data = kvm_read_edx_eax(vcpu);
1564 if (kvm_set_msr(vcpu, ecx, data)) {
1565 trace_kvm_msr_write_ex(ecx, data);
1566 kvm_inject_gp(vcpu, 0);
1570 trace_kvm_msr_write(ecx, data);
1571 return kvm_skip_emulated_instruction(vcpu);
1573 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1576 * The fast path for frequent and performance sensitive wrmsr emulation,
1577 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1578 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1579 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1580 * other cases which must be called after interrupts are enabled on the host.
1582 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1584 if (lapic_in_kernel(vcpu) && apic_x2apic_mode(vcpu->arch.apic) &&
1585 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1586 ((data & APIC_MODE_MASK) == APIC_DM_FIXED)) {
1589 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1590 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1591 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1592 trace_kvm_apic_write(APIC_ICR, (u32)data);
1599 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1601 u32 msr = kvm_rcx_read(vcpu);
1606 case APIC_BASE_MSR + (APIC_ICR >> 4):
1607 data = kvm_read_edx_eax(vcpu);
1608 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1611 return EXIT_FASTPATH_NONE;
1615 trace_kvm_msr_write(msr, data);
1616 return EXIT_FASTPATH_SKIP_EMUL_INS;
1619 return EXIT_FASTPATH_NONE;
1621 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1624 * Adapt set_msr() to msr_io()'s calling convention
1626 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1628 return __kvm_get_msr(vcpu, index, data, true);
1631 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1633 return __kvm_set_msr(vcpu, index, *data, true);
1636 #ifdef CONFIG_X86_64
1637 struct pvclock_clock {
1647 struct pvclock_gtod_data {
1650 struct pvclock_clock clock; /* extract of a clocksource struct */
1651 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1657 static struct pvclock_gtod_data pvclock_gtod_data;
1659 static void update_pvclock_gtod(struct timekeeper *tk)
1661 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1663 write_seqcount_begin(&vdata->seq);
1665 /* copy pvclock gtod data */
1666 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1667 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1668 vdata->clock.mask = tk->tkr_mono.mask;
1669 vdata->clock.mult = tk->tkr_mono.mult;
1670 vdata->clock.shift = tk->tkr_mono.shift;
1671 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1672 vdata->clock.offset = tk->tkr_mono.base;
1674 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->archdata.vclock_mode;
1675 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1676 vdata->raw_clock.mask = tk->tkr_raw.mask;
1677 vdata->raw_clock.mult = tk->tkr_raw.mult;
1678 vdata->raw_clock.shift = tk->tkr_raw.shift;
1679 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1680 vdata->raw_clock.offset = tk->tkr_raw.base;
1682 vdata->wall_time_sec = tk->xtime_sec;
1684 vdata->offs_boot = tk->offs_boot;
1686 write_seqcount_end(&vdata->seq);
1689 static s64 get_kvmclock_base_ns(void)
1691 /* Count up from boot time, but with the frequency of the raw clock. */
1692 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1695 static s64 get_kvmclock_base_ns(void)
1697 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1698 return ktime_get_boottime_ns();
1702 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1704 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1705 kvm_vcpu_kick(vcpu);
1708 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1712 struct pvclock_wall_clock wc;
1718 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1723 ++version; /* first time write, random junk */
1727 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1731 * The guest calculates current wall clock time by adding
1732 * system time (updated by kvm_guest_time_update below) to the
1733 * wall clock specified here. We do the reverse here.
1735 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1737 wc.nsec = do_div(wall_nsec, 1000000000);
1738 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1739 wc.version = version;
1741 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1744 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1747 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1749 do_shl32_div32(dividend, divisor);
1753 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1754 s8 *pshift, u32 *pmultiplier)
1762 scaled64 = scaled_hz;
1763 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1768 tps32 = (uint32_t)tps64;
1769 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1770 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1778 *pmultiplier = div_frac(scaled64, tps32);
1781 #ifdef CONFIG_X86_64
1782 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1785 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1786 static unsigned long max_tsc_khz;
1788 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1790 u64 v = (u64)khz * (1000000 + ppm);
1795 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1799 /* Guest TSC same frequency as host TSC? */
1801 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1805 /* TSC scaling supported? */
1806 if (!kvm_has_tsc_control) {
1807 if (user_tsc_khz > tsc_khz) {
1808 vcpu->arch.tsc_catchup = 1;
1809 vcpu->arch.tsc_always_catchup = 1;
1812 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1817 /* TSC scaling required - calculate ratio */
1818 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1819 user_tsc_khz, tsc_khz);
1821 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1822 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1827 vcpu->arch.tsc_scaling_ratio = ratio;
1831 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1833 u32 thresh_lo, thresh_hi;
1834 int use_scaling = 0;
1836 /* tsc_khz can be zero if TSC calibration fails */
1837 if (user_tsc_khz == 0) {
1838 /* set tsc_scaling_ratio to a safe value */
1839 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1843 /* Compute a scale to convert nanoseconds in TSC cycles */
1844 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1845 &vcpu->arch.virtual_tsc_shift,
1846 &vcpu->arch.virtual_tsc_mult);
1847 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1850 * Compute the variation in TSC rate which is acceptable
1851 * within the range of tolerance and decide if the
1852 * rate being applied is within that bounds of the hardware
1853 * rate. If so, no scaling or compensation need be done.
1855 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1856 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1857 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1858 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1861 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1864 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1866 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1867 vcpu->arch.virtual_tsc_mult,
1868 vcpu->arch.virtual_tsc_shift);
1869 tsc += vcpu->arch.this_tsc_write;
1873 static inline int gtod_is_based_on_tsc(int mode)
1875 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1878 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1880 #ifdef CONFIG_X86_64
1882 struct kvm_arch *ka = &vcpu->kvm->arch;
1883 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1885 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1886 atomic_read(&vcpu->kvm->online_vcpus));
1889 * Once the masterclock is enabled, always perform request in
1890 * order to update it.
1892 * In order to enable masterclock, the host clocksource must be TSC
1893 * and the vcpus need to have matched TSCs. When that happens,
1894 * perform request to enable masterclock.
1896 if (ka->use_master_clock ||
1897 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1898 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1900 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1901 atomic_read(&vcpu->kvm->online_vcpus),
1902 ka->use_master_clock, gtod->clock.vclock_mode);
1906 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1908 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1909 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1913 * Multiply tsc by a fixed point number represented by ratio.
1915 * The most significant 64-N bits (mult) of ratio represent the
1916 * integral part of the fixed point number; the remaining N bits
1917 * (frac) represent the fractional part, ie. ratio represents a fixed
1918 * point number (mult + frac * 2^(-N)).
1920 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1922 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1924 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1927 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1930 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1932 if (ratio != kvm_default_tsc_scaling_ratio)
1933 _tsc = __scale_tsc(ratio, tsc);
1937 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1939 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1943 tsc = kvm_scale_tsc(vcpu, rdtsc());
1945 return target_tsc - tsc;
1948 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1950 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1952 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1954 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1956 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1958 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
1961 static inline bool kvm_check_tsc_unstable(void)
1963 #ifdef CONFIG_X86_64
1965 * TSC is marked unstable when we're running on Hyper-V,
1966 * 'TSC page' clocksource is good.
1968 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1971 return check_tsc_unstable();
1974 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1976 struct kvm *kvm = vcpu->kvm;
1977 u64 offset, ns, elapsed;
1978 unsigned long flags;
1980 bool already_matched;
1981 u64 data = msr->data;
1982 bool synchronizing = false;
1984 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1985 offset = kvm_compute_tsc_offset(vcpu, data);
1986 ns = get_kvmclock_base_ns();
1987 elapsed = ns - kvm->arch.last_tsc_nsec;
1989 if (vcpu->arch.virtual_tsc_khz) {
1990 if (data == 0 && msr->host_initiated) {
1992 * detection of vcpu initialization -- need to sync
1993 * with other vCPUs. This particularly helps to keep
1994 * kvm_clock stable after CPU hotplug
1996 synchronizing = true;
1998 u64 tsc_exp = kvm->arch.last_tsc_write +
1999 nsec_to_cycles(vcpu, elapsed);
2000 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2002 * Special case: TSC write with a small delta (1 second)
2003 * of virtual cycle time against real time is
2004 * interpreted as an attempt to synchronize the CPU.
2006 synchronizing = data < tsc_exp + tsc_hz &&
2007 data + tsc_hz > tsc_exp;
2012 * For a reliable TSC, we can match TSC offsets, and for an unstable
2013 * TSC, we add elapsed time in this computation. We could let the
2014 * compensation code attempt to catch up if we fall behind, but
2015 * it's better to try to match offsets from the beginning.
2017 if (synchronizing &&
2018 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2019 if (!kvm_check_tsc_unstable()) {
2020 offset = kvm->arch.cur_tsc_offset;
2022 u64 delta = nsec_to_cycles(vcpu, elapsed);
2024 offset = kvm_compute_tsc_offset(vcpu, data);
2027 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2030 * We split periods of matched TSC writes into generations.
2031 * For each generation, we track the original measured
2032 * nanosecond time, offset, and write, so if TSCs are in
2033 * sync, we can match exact offset, and if not, we can match
2034 * exact software computation in compute_guest_tsc()
2036 * These values are tracked in kvm->arch.cur_xxx variables.
2038 kvm->arch.cur_tsc_generation++;
2039 kvm->arch.cur_tsc_nsec = ns;
2040 kvm->arch.cur_tsc_write = data;
2041 kvm->arch.cur_tsc_offset = offset;
2046 * We also track th most recent recorded KHZ, write and time to
2047 * allow the matching interval to be extended at each write.
2049 kvm->arch.last_tsc_nsec = ns;
2050 kvm->arch.last_tsc_write = data;
2051 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2053 vcpu->arch.last_guest_tsc = data;
2055 /* Keep track of which generation this VCPU has synchronized to */
2056 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2057 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2058 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2060 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2061 update_ia32_tsc_adjust_msr(vcpu, offset);
2063 kvm_vcpu_write_tsc_offset(vcpu, offset);
2064 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2066 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2068 kvm->arch.nr_vcpus_matched_tsc = 0;
2069 } else if (!already_matched) {
2070 kvm->arch.nr_vcpus_matched_tsc++;
2073 kvm_track_tsc_matching(vcpu);
2074 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2077 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2079 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2082 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
2083 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2086 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2088 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2089 WARN_ON(adjustment < 0);
2090 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2091 adjust_tsc_offset_guest(vcpu, adjustment);
2094 #ifdef CONFIG_X86_64
2096 static u64 read_tsc(void)
2098 u64 ret = (u64)rdtsc_ordered();
2099 u64 last = pvclock_gtod_data.clock.cycle_last;
2101 if (likely(ret >= last))
2105 * GCC likes to generate cmov here, but this branch is extremely
2106 * predictable (it's just a function of time and the likely is
2107 * very likely) and there's a data dependence, so force GCC
2108 * to generate a branch instead. I don't barrier() because
2109 * we don't actually need a barrier, and if this function
2110 * ever gets inlined it will generate worse code.
2116 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2122 switch (clock->vclock_mode) {
2123 case VCLOCK_HVCLOCK:
2124 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2126 if (tsc_pg_val != U64_MAX) {
2127 /* TSC page valid */
2128 *mode = VCLOCK_HVCLOCK;
2129 v = (tsc_pg_val - clock->cycle_last) &
2132 /* TSC page invalid */
2133 *mode = VCLOCK_NONE;
2138 *tsc_timestamp = read_tsc();
2139 v = (*tsc_timestamp - clock->cycle_last) &
2143 *mode = VCLOCK_NONE;
2146 if (*mode == VCLOCK_NONE)
2147 *tsc_timestamp = v = 0;
2149 return v * clock->mult;
2152 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2154 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2160 seq = read_seqcount_begin(>od->seq);
2161 ns = gtod->raw_clock.base_cycles;
2162 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2163 ns >>= gtod->raw_clock.shift;
2164 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2165 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2171 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2173 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2179 seq = read_seqcount_begin(>od->seq);
2180 ts->tv_sec = gtod->wall_time_sec;
2181 ns = gtod->clock.base_cycles;
2182 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2183 ns >>= gtod->clock.shift;
2184 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2186 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2192 /* returns true if host is using TSC based clocksource */
2193 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2195 /* checked again under seqlock below */
2196 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2199 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2203 /* returns true if host is using TSC based clocksource */
2204 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2207 /* checked again under seqlock below */
2208 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2211 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2217 * Assuming a stable TSC across physical CPUS, and a stable TSC
2218 * across virtual CPUs, the following condition is possible.
2219 * Each numbered line represents an event visible to both
2220 * CPUs at the next numbered event.
2222 * "timespecX" represents host monotonic time. "tscX" represents
2225 * VCPU0 on CPU0 | VCPU1 on CPU1
2227 * 1. read timespec0,tsc0
2228 * 2. | timespec1 = timespec0 + N
2230 * 3. transition to guest | transition to guest
2231 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2232 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2233 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2235 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2238 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2240 * - 0 < N - M => M < N
2242 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2243 * always the case (the difference between two distinct xtime instances
2244 * might be smaller then the difference between corresponding TSC reads,
2245 * when updating guest vcpus pvclock areas).
2247 * To avoid that problem, do not allow visibility of distinct
2248 * system_timestamp/tsc_timestamp values simultaneously: use a master
2249 * copy of host monotonic time values. Update that master copy
2252 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2256 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2258 #ifdef CONFIG_X86_64
2259 struct kvm_arch *ka = &kvm->arch;
2261 bool host_tsc_clocksource, vcpus_matched;
2263 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2264 atomic_read(&kvm->online_vcpus));
2267 * If the host uses TSC clock, then passthrough TSC as stable
2270 host_tsc_clocksource = kvm_get_time_and_clockread(
2271 &ka->master_kernel_ns,
2272 &ka->master_cycle_now);
2274 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2275 && !ka->backwards_tsc_observed
2276 && !ka->boot_vcpu_runs_old_kvmclock;
2278 if (ka->use_master_clock)
2279 atomic_set(&kvm_guest_has_master_clock, 1);
2281 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2282 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2287 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2289 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2292 static void kvm_gen_update_masterclock(struct kvm *kvm)
2294 #ifdef CONFIG_X86_64
2296 struct kvm_vcpu *vcpu;
2297 struct kvm_arch *ka = &kvm->arch;
2299 spin_lock(&ka->pvclock_gtod_sync_lock);
2300 kvm_make_mclock_inprogress_request(kvm);
2301 /* no guest entries from this point */
2302 pvclock_update_vm_gtod_copy(kvm);
2304 kvm_for_each_vcpu(i, vcpu, kvm)
2305 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2307 /* guest entries allowed */
2308 kvm_for_each_vcpu(i, vcpu, kvm)
2309 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2311 spin_unlock(&ka->pvclock_gtod_sync_lock);
2315 u64 get_kvmclock_ns(struct kvm *kvm)
2317 struct kvm_arch *ka = &kvm->arch;
2318 struct pvclock_vcpu_time_info hv_clock;
2321 spin_lock(&ka->pvclock_gtod_sync_lock);
2322 if (!ka->use_master_clock) {
2323 spin_unlock(&ka->pvclock_gtod_sync_lock);
2324 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2327 hv_clock.tsc_timestamp = ka->master_cycle_now;
2328 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2329 spin_unlock(&ka->pvclock_gtod_sync_lock);
2331 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2334 if (__this_cpu_read(cpu_tsc_khz)) {
2335 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2336 &hv_clock.tsc_shift,
2337 &hv_clock.tsc_to_system_mul);
2338 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2340 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2347 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2349 struct kvm_vcpu_arch *vcpu = &v->arch;
2350 struct pvclock_vcpu_time_info guest_hv_clock;
2352 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2353 &guest_hv_clock, sizeof(guest_hv_clock))))
2356 /* This VCPU is paused, but it's legal for a guest to read another
2357 * VCPU's kvmclock, so we really have to follow the specification where
2358 * it says that version is odd if data is being modified, and even after
2361 * Version field updates must be kept separate. This is because
2362 * kvm_write_guest_cached might use a "rep movs" instruction, and
2363 * writes within a string instruction are weakly ordered. So there
2364 * are three writes overall.
2366 * As a small optimization, only write the version field in the first
2367 * and third write. The vcpu->pv_time cache is still valid, because the
2368 * version field is the first in the struct.
2370 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2372 if (guest_hv_clock.version & 1)
2373 ++guest_hv_clock.version; /* first time write, random junk */
2375 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2376 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2378 sizeof(vcpu->hv_clock.version));
2382 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2383 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2385 if (vcpu->pvclock_set_guest_stopped_request) {
2386 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2387 vcpu->pvclock_set_guest_stopped_request = false;
2390 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2392 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2394 sizeof(vcpu->hv_clock));
2398 vcpu->hv_clock.version++;
2399 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2401 sizeof(vcpu->hv_clock.version));
2404 static int kvm_guest_time_update(struct kvm_vcpu *v)
2406 unsigned long flags, tgt_tsc_khz;
2407 struct kvm_vcpu_arch *vcpu = &v->arch;
2408 struct kvm_arch *ka = &v->kvm->arch;
2410 u64 tsc_timestamp, host_tsc;
2412 bool use_master_clock;
2418 * If the host uses TSC clock, then passthrough TSC as stable
2421 spin_lock(&ka->pvclock_gtod_sync_lock);
2422 use_master_clock = ka->use_master_clock;
2423 if (use_master_clock) {
2424 host_tsc = ka->master_cycle_now;
2425 kernel_ns = ka->master_kernel_ns;
2427 spin_unlock(&ka->pvclock_gtod_sync_lock);
2429 /* Keep irq disabled to prevent changes to the clock */
2430 local_irq_save(flags);
2431 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2432 if (unlikely(tgt_tsc_khz == 0)) {
2433 local_irq_restore(flags);
2434 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2437 if (!use_master_clock) {
2439 kernel_ns = get_kvmclock_base_ns();
2442 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2445 * We may have to catch up the TSC to match elapsed wall clock
2446 * time for two reasons, even if kvmclock is used.
2447 * 1) CPU could have been running below the maximum TSC rate
2448 * 2) Broken TSC compensation resets the base at each VCPU
2449 * entry to avoid unknown leaps of TSC even when running
2450 * again on the same CPU. This may cause apparent elapsed
2451 * time to disappear, and the guest to stand still or run
2454 if (vcpu->tsc_catchup) {
2455 u64 tsc = compute_guest_tsc(v, kernel_ns);
2456 if (tsc > tsc_timestamp) {
2457 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2458 tsc_timestamp = tsc;
2462 local_irq_restore(flags);
2464 /* With all the info we got, fill in the values */
2466 if (kvm_has_tsc_control)
2467 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2469 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2470 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2471 &vcpu->hv_clock.tsc_shift,
2472 &vcpu->hv_clock.tsc_to_system_mul);
2473 vcpu->hw_tsc_khz = tgt_tsc_khz;
2476 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2477 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2478 vcpu->last_guest_tsc = tsc_timestamp;
2479 WARN_ON((s64)vcpu->hv_clock.system_time < 0);
2481 /* If the host uses TSC clocksource, then it is stable */
2483 if (use_master_clock)
2484 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2486 vcpu->hv_clock.flags = pvclock_flags;
2488 if (vcpu->pv_time_enabled)
2489 kvm_setup_pvclock_page(v);
2490 if (v == kvm_get_vcpu(v->kvm, 0))
2491 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2496 * kvmclock updates which are isolated to a given vcpu, such as
2497 * vcpu->cpu migration, should not allow system_timestamp from
2498 * the rest of the vcpus to remain static. Otherwise ntp frequency
2499 * correction applies to one vcpu's system_timestamp but not
2502 * So in those cases, request a kvmclock update for all vcpus.
2503 * We need to rate-limit these requests though, as they can
2504 * considerably slow guests that have a large number of vcpus.
2505 * The time for a remote vcpu to update its kvmclock is bound
2506 * by the delay we use to rate-limit the updates.
2509 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2511 static void kvmclock_update_fn(struct work_struct *work)
2514 struct delayed_work *dwork = to_delayed_work(work);
2515 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2516 kvmclock_update_work);
2517 struct kvm *kvm = container_of(ka, struct kvm, arch);
2518 struct kvm_vcpu *vcpu;
2520 kvm_for_each_vcpu(i, vcpu, kvm) {
2521 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2522 kvm_vcpu_kick(vcpu);
2526 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2528 struct kvm *kvm = v->kvm;
2530 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2531 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2532 KVMCLOCK_UPDATE_DELAY);
2535 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2537 static void kvmclock_sync_fn(struct work_struct *work)
2539 struct delayed_work *dwork = to_delayed_work(work);
2540 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2541 kvmclock_sync_work);
2542 struct kvm *kvm = container_of(ka, struct kvm, arch);
2544 if (!kvmclock_periodic_sync)
2547 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2548 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2549 KVMCLOCK_SYNC_PERIOD);
2553 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2555 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2557 /* McStatusWrEn enabled? */
2558 if (guest_cpuid_is_amd_or_hygon(vcpu))
2559 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2564 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2566 u64 mcg_cap = vcpu->arch.mcg_cap;
2567 unsigned bank_num = mcg_cap & 0xff;
2568 u32 msr = msr_info->index;
2569 u64 data = msr_info->data;
2572 case MSR_IA32_MCG_STATUS:
2573 vcpu->arch.mcg_status = data;
2575 case MSR_IA32_MCG_CTL:
2576 if (!(mcg_cap & MCG_CTL_P) &&
2577 (data || !msr_info->host_initiated))
2579 if (data != 0 && data != ~(u64)0)
2581 vcpu->arch.mcg_ctl = data;
2584 if (msr >= MSR_IA32_MC0_CTL &&
2585 msr < MSR_IA32_MCx_CTL(bank_num)) {
2586 u32 offset = array_index_nospec(
2587 msr - MSR_IA32_MC0_CTL,
2588 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2590 /* only 0 or all 1s can be written to IA32_MCi_CTL
2591 * some Linux kernels though clear bit 10 in bank 4 to
2592 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2593 * this to avoid an uncatched #GP in the guest
2595 if ((offset & 0x3) == 0 &&
2596 data != 0 && (data | (1 << 10)) != ~(u64)0)
2600 if (!msr_info->host_initiated &&
2601 (offset & 0x3) == 1 && data != 0) {
2602 if (!can_set_mci_status(vcpu))
2606 vcpu->arch.mce_banks[offset] = data;
2614 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2616 struct kvm *kvm = vcpu->kvm;
2617 int lm = is_long_mode(vcpu);
2618 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2619 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2620 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2621 : kvm->arch.xen_hvm_config.blob_size_32;
2622 u32 page_num = data & ~PAGE_MASK;
2623 u64 page_addr = data & PAGE_MASK;
2628 if (page_num >= blob_size)
2631 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2636 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2645 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2647 gpa_t gpa = data & ~0x3f;
2649 /* Bits 3:5 are reserved, Should be zero */
2653 vcpu->arch.apf.msr_val = data;
2655 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2656 kvm_clear_async_pf_completion_queue(vcpu);
2657 kvm_async_pf_hash_reset(vcpu);
2661 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2665 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2666 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2667 kvm_async_pf_wakeup_all(vcpu);
2671 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2673 vcpu->arch.pv_time_enabled = false;
2674 vcpu->arch.time = 0;
2677 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2679 ++vcpu->stat.tlb_flush;
2680 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2683 static void record_steal_time(struct kvm_vcpu *vcpu)
2685 struct kvm_host_map map;
2686 struct kvm_steal_time *st;
2688 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2691 /* -EAGAIN is returned in atomic context so we can just return. */
2692 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2693 &map, &vcpu->arch.st.cache, false))
2697 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2700 * Doing a TLB flush here, on the guest's behalf, can avoid
2703 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2704 st->preempted & KVM_VCPU_FLUSH_TLB);
2705 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2706 kvm_vcpu_flush_tlb(vcpu, false);
2708 vcpu->arch.st.preempted = 0;
2710 if (st->version & 1)
2711 st->version += 1; /* first time write, random junk */
2717 st->steal += current->sched_info.run_delay -
2718 vcpu->arch.st.last_steal;
2719 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2725 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2728 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2731 u32 msr = msr_info->index;
2732 u64 data = msr_info->data;
2735 case MSR_AMD64_NB_CFG:
2736 case MSR_IA32_UCODE_WRITE:
2737 case MSR_VM_HSAVE_PA:
2738 case MSR_AMD64_PATCH_LOADER:
2739 case MSR_AMD64_BU_CFG2:
2740 case MSR_AMD64_DC_CFG:
2741 case MSR_F15H_EX_CFG:
2744 case MSR_IA32_UCODE_REV:
2745 if (msr_info->host_initiated)
2746 vcpu->arch.microcode_version = data;
2748 case MSR_IA32_ARCH_CAPABILITIES:
2749 if (!msr_info->host_initiated)
2751 vcpu->arch.arch_capabilities = data;
2754 return set_efer(vcpu, msr_info);
2756 data &= ~(u64)0x40; /* ignore flush filter disable */
2757 data &= ~(u64)0x100; /* ignore ignne emulation enable */
2758 data &= ~(u64)0x8; /* ignore TLB cache disable */
2760 /* Handle McStatusWrEn */
2761 if (data == BIT_ULL(18)) {
2762 vcpu->arch.msr_hwcr = data;
2763 } else if (data != 0) {
2764 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2769 case MSR_FAM10H_MMIO_CONF_BASE:
2771 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2776 case MSR_IA32_DEBUGCTLMSR:
2778 /* We support the non-activated case already */
2780 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2781 /* Values other than LBR and BTF are vendor-specific,
2782 thus reserved and should throw a #GP */
2785 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2788 case 0x200 ... 0x2ff:
2789 return kvm_mtrr_set_msr(vcpu, msr, data);
2790 case MSR_IA32_APICBASE:
2791 return kvm_set_apic_base(vcpu, msr_info);
2792 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2793 return kvm_x2apic_msr_write(vcpu, msr, data);
2794 case MSR_IA32_TSCDEADLINE:
2795 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2797 case MSR_IA32_TSC_ADJUST:
2798 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2799 if (!msr_info->host_initiated) {
2800 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2801 adjust_tsc_offset_guest(vcpu, adj);
2803 vcpu->arch.ia32_tsc_adjust_msr = data;
2806 case MSR_IA32_MISC_ENABLE:
2807 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2808 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2809 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2811 vcpu->arch.ia32_misc_enable_msr = data;
2812 kvm_update_cpuid(vcpu);
2814 vcpu->arch.ia32_misc_enable_msr = data;
2817 case MSR_IA32_SMBASE:
2818 if (!msr_info->host_initiated)
2820 vcpu->arch.smbase = data;
2822 case MSR_IA32_POWER_CTL:
2823 vcpu->arch.msr_ia32_power_ctl = data;
2826 kvm_write_tsc(vcpu, msr_info);
2829 if (!msr_info->host_initiated &&
2830 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2833 * KVM supports exposing PT to the guest, but does not support
2834 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
2835 * XSAVES/XRSTORS to save/restore PT MSRs.
2837 if (data & ~supported_xss)
2839 vcpu->arch.ia32_xss = data;
2842 if (!msr_info->host_initiated)
2844 vcpu->arch.smi_count = data;
2846 case MSR_KVM_WALL_CLOCK_NEW:
2847 case MSR_KVM_WALL_CLOCK:
2848 vcpu->kvm->arch.wall_clock = data;
2849 kvm_write_wall_clock(vcpu->kvm, data);
2851 case MSR_KVM_SYSTEM_TIME_NEW:
2852 case MSR_KVM_SYSTEM_TIME: {
2853 struct kvm_arch *ka = &vcpu->kvm->arch;
2855 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2856 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2858 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2859 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2861 ka->boot_vcpu_runs_old_kvmclock = tmp;
2864 vcpu->arch.time = data;
2865 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2867 /* we verify if the enable bit is set... */
2868 vcpu->arch.pv_time_enabled = false;
2872 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2873 &vcpu->arch.pv_time, data & ~1ULL,
2874 sizeof(struct pvclock_vcpu_time_info)))
2875 vcpu->arch.pv_time_enabled = true;
2879 case MSR_KVM_ASYNC_PF_EN:
2880 if (kvm_pv_enable_async_pf(vcpu, data))
2883 case MSR_KVM_STEAL_TIME:
2885 if (unlikely(!sched_info_on()))
2888 if (data & KVM_STEAL_RESERVED_MASK)
2891 vcpu->arch.st.msr_val = data;
2893 if (!(data & KVM_MSR_ENABLED))
2896 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2899 case MSR_KVM_PV_EOI_EN:
2900 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2904 case MSR_KVM_POLL_CONTROL:
2905 /* only enable bit supported */
2906 if (data & (-1ULL << 1))
2909 vcpu->arch.msr_kvm_poll_control = data;
2912 case MSR_IA32_MCG_CTL:
2913 case MSR_IA32_MCG_STATUS:
2914 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2915 return set_msr_mce(vcpu, msr_info);
2917 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2918 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2919 pr = true; /* fall through */
2920 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2921 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2922 if (kvm_pmu_is_valid_msr(vcpu, msr))
2923 return kvm_pmu_set_msr(vcpu, msr_info);
2925 if (pr || data != 0)
2926 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2927 "0x%x data 0x%llx\n", msr, data);
2929 case MSR_K7_CLK_CTL:
2931 * Ignore all writes to this no longer documented MSR.
2932 * Writes are only relevant for old K7 processors,
2933 * all pre-dating SVM, but a recommended workaround from
2934 * AMD for these chips. It is possible to specify the
2935 * affected processor models on the command line, hence
2936 * the need to ignore the workaround.
2939 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2940 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2941 case HV_X64_MSR_CRASH_CTL:
2942 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2943 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2944 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2945 case HV_X64_MSR_TSC_EMULATION_STATUS:
2946 return kvm_hv_set_msr_common(vcpu, msr, data,
2947 msr_info->host_initiated);
2948 case MSR_IA32_BBL_CR_CTL3:
2949 /* Drop writes to this legacy MSR -- see rdmsr
2950 * counterpart for further detail.
2952 if (report_ignored_msrs)
2953 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2956 case MSR_AMD64_OSVW_ID_LENGTH:
2957 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2959 vcpu->arch.osvw.length = data;
2961 case MSR_AMD64_OSVW_STATUS:
2962 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2964 vcpu->arch.osvw.status = data;
2966 case MSR_PLATFORM_INFO:
2967 if (!msr_info->host_initiated ||
2968 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2969 cpuid_fault_enabled(vcpu)))
2971 vcpu->arch.msr_platform_info = data;
2973 case MSR_MISC_FEATURES_ENABLES:
2974 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2975 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2976 !supports_cpuid_fault(vcpu)))
2978 vcpu->arch.msr_misc_features_enables = data;
2981 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2982 return xen_hvm_config(vcpu, data);
2983 if (kvm_pmu_is_valid_msr(vcpu, msr))
2984 return kvm_pmu_set_msr(vcpu, msr_info);
2986 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2990 if (report_ignored_msrs)
2992 "ignored wrmsr: 0x%x data 0x%llx\n",
2999 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3001 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3004 u64 mcg_cap = vcpu->arch.mcg_cap;
3005 unsigned bank_num = mcg_cap & 0xff;
3008 case MSR_IA32_P5_MC_ADDR:
3009 case MSR_IA32_P5_MC_TYPE:
3012 case MSR_IA32_MCG_CAP:
3013 data = vcpu->arch.mcg_cap;
3015 case MSR_IA32_MCG_CTL:
3016 if (!(mcg_cap & MCG_CTL_P) && !host)
3018 data = vcpu->arch.mcg_ctl;
3020 case MSR_IA32_MCG_STATUS:
3021 data = vcpu->arch.mcg_status;
3024 if (msr >= MSR_IA32_MC0_CTL &&
3025 msr < MSR_IA32_MCx_CTL(bank_num)) {
3026 u32 offset = array_index_nospec(
3027 msr - MSR_IA32_MC0_CTL,
3028 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3030 data = vcpu->arch.mce_banks[offset];
3039 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3041 switch (msr_info->index) {
3042 case MSR_IA32_PLATFORM_ID:
3043 case MSR_IA32_EBL_CR_POWERON:
3044 case MSR_IA32_DEBUGCTLMSR:
3045 case MSR_IA32_LASTBRANCHFROMIP:
3046 case MSR_IA32_LASTBRANCHTOIP:
3047 case MSR_IA32_LASTINTFROMIP:
3048 case MSR_IA32_LASTINTTOIP:
3050 case MSR_K8_TSEG_ADDR:
3051 case MSR_K8_TSEG_MASK:
3052 case MSR_VM_HSAVE_PA:
3053 case MSR_K8_INT_PENDING_MSG:
3054 case MSR_AMD64_NB_CFG:
3055 case MSR_FAM10H_MMIO_CONF_BASE:
3056 case MSR_AMD64_BU_CFG2:
3057 case MSR_IA32_PERF_CTL:
3058 case MSR_AMD64_DC_CFG:
3059 case MSR_F15H_EX_CFG:
3062 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3063 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3064 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3065 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3066 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3067 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3068 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3071 case MSR_IA32_UCODE_REV:
3072 msr_info->data = vcpu->arch.microcode_version;
3074 case MSR_IA32_ARCH_CAPABILITIES:
3075 if (!msr_info->host_initiated &&
3076 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3078 msr_info->data = vcpu->arch.arch_capabilities;
3080 case MSR_IA32_POWER_CTL:
3081 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3084 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3087 case 0x200 ... 0x2ff:
3088 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3089 case 0xcd: /* fsb frequency */
3093 * MSR_EBC_FREQUENCY_ID
3094 * Conservative value valid for even the basic CPU models.
3095 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3096 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3097 * and 266MHz for model 3, or 4. Set Core Clock
3098 * Frequency to System Bus Frequency Ratio to 1 (bits
3099 * 31:24) even though these are only valid for CPU
3100 * models > 2, however guests may end up dividing or
3101 * multiplying by zero otherwise.
3103 case MSR_EBC_FREQUENCY_ID:
3104 msr_info->data = 1 << 24;
3106 case MSR_IA32_APICBASE:
3107 msr_info->data = kvm_get_apic_base(vcpu);
3109 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
3110 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3111 case MSR_IA32_TSCDEADLINE:
3112 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3114 case MSR_IA32_TSC_ADJUST:
3115 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3117 case MSR_IA32_MISC_ENABLE:
3118 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3120 case MSR_IA32_SMBASE:
3121 if (!msr_info->host_initiated)
3123 msr_info->data = vcpu->arch.smbase;
3126 msr_info->data = vcpu->arch.smi_count;
3128 case MSR_IA32_PERF_STATUS:
3129 /* TSC increment by tick */
3130 msr_info->data = 1000ULL;
3131 /* CPU multiplier */
3132 msr_info->data |= (((uint64_t)4ULL) << 40);
3135 msr_info->data = vcpu->arch.efer;
3137 case MSR_KVM_WALL_CLOCK:
3138 case MSR_KVM_WALL_CLOCK_NEW:
3139 msr_info->data = vcpu->kvm->arch.wall_clock;
3141 case MSR_KVM_SYSTEM_TIME:
3142 case MSR_KVM_SYSTEM_TIME_NEW:
3143 msr_info->data = vcpu->arch.time;
3145 case MSR_KVM_ASYNC_PF_EN:
3146 msr_info->data = vcpu->arch.apf.msr_val;
3148 case MSR_KVM_STEAL_TIME:
3149 msr_info->data = vcpu->arch.st.msr_val;
3151 case MSR_KVM_PV_EOI_EN:
3152 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3154 case MSR_KVM_POLL_CONTROL:
3155 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3157 case MSR_IA32_P5_MC_ADDR:
3158 case MSR_IA32_P5_MC_TYPE:
3159 case MSR_IA32_MCG_CAP:
3160 case MSR_IA32_MCG_CTL:
3161 case MSR_IA32_MCG_STATUS:
3162 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3163 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3164 msr_info->host_initiated);
3166 if (!msr_info->host_initiated &&
3167 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3169 msr_info->data = vcpu->arch.ia32_xss;
3171 case MSR_K7_CLK_CTL:
3173 * Provide expected ramp-up count for K7. All other
3174 * are set to zero, indicating minimum divisors for
3177 * This prevents guest kernels on AMD host with CPU
3178 * type 6, model 8 and higher from exploding due to
3179 * the rdmsr failing.
3181 msr_info->data = 0x20000000;
3183 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3184 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3185 case HV_X64_MSR_CRASH_CTL:
3186 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3187 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3188 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3189 case HV_X64_MSR_TSC_EMULATION_STATUS:
3190 return kvm_hv_get_msr_common(vcpu,
3191 msr_info->index, &msr_info->data,
3192 msr_info->host_initiated);
3193 case MSR_IA32_BBL_CR_CTL3:
3194 /* This legacy MSR exists but isn't fully documented in current
3195 * silicon. It is however accessed by winxp in very narrow
3196 * scenarios where it sets bit #19, itself documented as
3197 * a "reserved" bit. Best effort attempt to source coherent
3198 * read data here should the balance of the register be
3199 * interpreted by the guest:
3201 * L2 cache control register 3: 64GB range, 256KB size,
3202 * enabled, latency 0x1, configured
3204 msr_info->data = 0xbe702111;
3206 case MSR_AMD64_OSVW_ID_LENGTH:
3207 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3209 msr_info->data = vcpu->arch.osvw.length;
3211 case MSR_AMD64_OSVW_STATUS:
3212 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3214 msr_info->data = vcpu->arch.osvw.status;
3216 case MSR_PLATFORM_INFO:
3217 if (!msr_info->host_initiated &&
3218 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3220 msr_info->data = vcpu->arch.msr_platform_info;
3222 case MSR_MISC_FEATURES_ENABLES:
3223 msr_info->data = vcpu->arch.msr_misc_features_enables;
3226 msr_info->data = vcpu->arch.msr_hwcr;
3229 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3230 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3232 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3236 if (report_ignored_msrs)
3237 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3245 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3248 * Read or write a bunch of msrs. All parameters are kernel addresses.
3250 * @return number of msrs set successfully.
3252 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3253 struct kvm_msr_entry *entries,
3254 int (*do_msr)(struct kvm_vcpu *vcpu,
3255 unsigned index, u64 *data))
3259 for (i = 0; i < msrs->nmsrs; ++i)
3260 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3267 * Read or write a bunch of msrs. Parameters are user addresses.
3269 * @return number of msrs set successfully.
3271 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3272 int (*do_msr)(struct kvm_vcpu *vcpu,
3273 unsigned index, u64 *data),
3276 struct kvm_msrs msrs;
3277 struct kvm_msr_entry *entries;
3282 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3286 if (msrs.nmsrs >= MAX_IO_MSRS)
3289 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3290 entries = memdup_user(user_msrs->entries, size);
3291 if (IS_ERR(entries)) {
3292 r = PTR_ERR(entries);
3296 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3301 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3312 static inline bool kvm_can_mwait_in_guest(void)
3314 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3315 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3316 boot_cpu_has(X86_FEATURE_ARAT);
3319 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3324 case KVM_CAP_IRQCHIP:
3326 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3327 case KVM_CAP_SET_TSS_ADDR:
3328 case KVM_CAP_EXT_CPUID:
3329 case KVM_CAP_EXT_EMUL_CPUID:
3330 case KVM_CAP_CLOCKSOURCE:
3332 case KVM_CAP_NOP_IO_DELAY:
3333 case KVM_CAP_MP_STATE:
3334 case KVM_CAP_SYNC_MMU:
3335 case KVM_CAP_USER_NMI:
3336 case KVM_CAP_REINJECT_CONTROL:
3337 case KVM_CAP_IRQ_INJECT_STATUS:
3338 case KVM_CAP_IOEVENTFD:
3339 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3341 case KVM_CAP_PIT_STATE2:
3342 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3343 case KVM_CAP_XEN_HVM:
3344 case KVM_CAP_VCPU_EVENTS:
3345 case KVM_CAP_HYPERV:
3346 case KVM_CAP_HYPERV_VAPIC:
3347 case KVM_CAP_HYPERV_SPIN:
3348 case KVM_CAP_HYPERV_SYNIC:
3349 case KVM_CAP_HYPERV_SYNIC2:
3350 case KVM_CAP_HYPERV_VP_INDEX:
3351 case KVM_CAP_HYPERV_EVENTFD:
3352 case KVM_CAP_HYPERV_TLBFLUSH:
3353 case KVM_CAP_HYPERV_SEND_IPI:
3354 case KVM_CAP_HYPERV_CPUID:
3355 case KVM_CAP_PCI_SEGMENT:
3356 case KVM_CAP_DEBUGREGS:
3357 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3359 case KVM_CAP_ASYNC_PF:
3360 case KVM_CAP_GET_TSC_KHZ:
3361 case KVM_CAP_KVMCLOCK_CTRL:
3362 case KVM_CAP_READONLY_MEM:
3363 case KVM_CAP_HYPERV_TIME:
3364 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3365 case KVM_CAP_TSC_DEADLINE_TIMER:
3366 case KVM_CAP_DISABLE_QUIRKS:
3367 case KVM_CAP_SET_BOOT_CPU_ID:
3368 case KVM_CAP_SPLIT_IRQCHIP:
3369 case KVM_CAP_IMMEDIATE_EXIT:
3370 case KVM_CAP_PMU_EVENT_FILTER:
3371 case KVM_CAP_GET_MSR_FEATURES:
3372 case KVM_CAP_MSR_PLATFORM_INFO:
3373 case KVM_CAP_EXCEPTION_PAYLOAD:
3376 case KVM_CAP_SYNC_REGS:
3377 r = KVM_SYNC_X86_VALID_FIELDS;
3379 case KVM_CAP_ADJUST_CLOCK:
3380 r = KVM_CLOCK_TSC_STABLE;
3382 case KVM_CAP_X86_DISABLE_EXITS:
3383 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3384 KVM_X86_DISABLE_EXITS_CSTATE;
3385 if(kvm_can_mwait_in_guest())
3386 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3388 case KVM_CAP_X86_SMM:
3389 /* SMBASE is usually relocated above 1M on modern chipsets,
3390 * and SMM handlers might indeed rely on 4G segment limits,
3391 * so do not report SMM to be available if real mode is
3392 * emulated via vm86 mode. Still, do not go to great lengths
3393 * to avoid userspace's usage of the feature, because it is a
3394 * fringe case that is not enabled except via specific settings
3395 * of the module parameters.
3397 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
3400 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3402 case KVM_CAP_NR_VCPUS:
3403 r = KVM_SOFT_MAX_VCPUS;
3405 case KVM_CAP_MAX_VCPUS:
3408 case KVM_CAP_MAX_VCPU_ID:
3409 r = KVM_MAX_VCPU_ID;
3411 case KVM_CAP_PV_MMU: /* obsolete */
3415 r = KVM_MAX_MCE_BANKS;
3418 r = boot_cpu_has(X86_FEATURE_XSAVE);
3420 case KVM_CAP_TSC_CONTROL:
3421 r = kvm_has_tsc_control;
3423 case KVM_CAP_X2APIC_API:
3424 r = KVM_X2APIC_API_VALID_FLAGS;
3426 case KVM_CAP_NESTED_STATE:
3427 r = kvm_x86_ops->get_nested_state ?
3428 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
3430 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3431 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3433 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3434 r = kvm_x86_ops->nested_enable_evmcs != NULL;
3443 long kvm_arch_dev_ioctl(struct file *filp,
3444 unsigned int ioctl, unsigned long arg)
3446 void __user *argp = (void __user *)arg;
3450 case KVM_GET_MSR_INDEX_LIST: {
3451 struct kvm_msr_list __user *user_msr_list = argp;
3452 struct kvm_msr_list msr_list;
3456 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3459 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3460 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3463 if (n < msr_list.nmsrs)
3466 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3467 num_msrs_to_save * sizeof(u32)))
3469 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3471 num_emulated_msrs * sizeof(u32)))
3476 case KVM_GET_SUPPORTED_CPUID:
3477 case KVM_GET_EMULATED_CPUID: {
3478 struct kvm_cpuid2 __user *cpuid_arg = argp;
3479 struct kvm_cpuid2 cpuid;
3482 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3485 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3491 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3496 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3498 if (copy_to_user(argp, &kvm_mce_cap_supported,
3499 sizeof(kvm_mce_cap_supported)))
3503 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3504 struct kvm_msr_list __user *user_msr_list = argp;
3505 struct kvm_msr_list msr_list;
3509 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3512 msr_list.nmsrs = num_msr_based_features;
3513 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3516 if (n < msr_list.nmsrs)
3519 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3520 num_msr_based_features * sizeof(u32)))
3526 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3536 static void wbinvd_ipi(void *garbage)
3541 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3543 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3546 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3548 /* Address WBINVD may be executed by guest */
3549 if (need_emulate_wbinvd(vcpu)) {
3550 if (kvm_x86_ops->has_wbinvd_exit())
3551 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3552 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3553 smp_call_function_single(vcpu->cpu,
3554 wbinvd_ipi, NULL, 1);
3557 kvm_x86_ops->vcpu_load(vcpu, cpu);
3559 /* Apply any externally detected TSC adjustments (due to suspend) */
3560 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3561 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3562 vcpu->arch.tsc_offset_adjustment = 0;
3563 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3566 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3567 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3568 rdtsc() - vcpu->arch.last_host_tsc;
3570 mark_tsc_unstable("KVM discovered backwards TSC");
3572 if (kvm_check_tsc_unstable()) {
3573 u64 offset = kvm_compute_tsc_offset(vcpu,
3574 vcpu->arch.last_guest_tsc);
3575 kvm_vcpu_write_tsc_offset(vcpu, offset);
3576 vcpu->arch.tsc_catchup = 1;
3579 if (kvm_lapic_hv_timer_in_use(vcpu))
3580 kvm_lapic_restart_hv_timer(vcpu);
3583 * On a host with synchronized TSC, there is no need to update
3584 * kvmclock on vcpu->cpu migration
3586 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3587 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3588 if (vcpu->cpu != cpu)
3589 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3593 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3596 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3598 struct kvm_host_map map;
3599 struct kvm_steal_time *st;
3601 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3604 if (vcpu->arch.st.preempted)
3607 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3608 &vcpu->arch.st.cache, true))
3612 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3614 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3616 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3619 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3623 if (vcpu->preempted)
3624 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3627 * Disable page faults because we're in atomic context here.
3628 * kvm_write_guest_offset_cached() would call might_fault()
3629 * that relies on pagefault_disable() to tell if there's a
3630 * bug. NOTE: the write to guest memory may not go through if
3631 * during postcopy live migration or if there's heavy guest
3634 pagefault_disable();
3636 * kvm_memslots() will be called by
3637 * kvm_write_guest_offset_cached() so take the srcu lock.
3639 idx = srcu_read_lock(&vcpu->kvm->srcu);
3640 kvm_steal_time_set_preempted(vcpu);
3641 srcu_read_unlock(&vcpu->kvm->srcu, idx);
3643 kvm_x86_ops->vcpu_put(vcpu);
3644 vcpu->arch.last_host_tsc = rdtsc();
3646 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3647 * on every vmexit, but if not, we might have a stale dr6 from the
3648 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3653 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3654 struct kvm_lapic_state *s)
3656 if (vcpu->arch.apicv_active)
3657 kvm_x86_ops->sync_pir_to_irr(vcpu);
3659 return kvm_apic_get_state(vcpu, s);
3662 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3663 struct kvm_lapic_state *s)
3667 r = kvm_apic_set_state(vcpu, s);
3670 update_cr8_intercept(vcpu);
3675 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3677 return (!lapic_in_kernel(vcpu) ||
3678 kvm_apic_accept_pic_intr(vcpu));
3682 * if userspace requested an interrupt window, check that the
3683 * interrupt window is open.
3685 * No need to exit to userspace if we already have an interrupt queued.
3687 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3689 return kvm_arch_interrupt_allowed(vcpu) &&
3690 !kvm_cpu_has_interrupt(vcpu) &&
3691 !kvm_event_needs_reinjection(vcpu) &&
3692 kvm_cpu_accept_dm_intr(vcpu);
3695 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3696 struct kvm_interrupt *irq)
3698 if (irq->irq >= KVM_NR_INTERRUPTS)
3701 if (!irqchip_in_kernel(vcpu->kvm)) {
3702 kvm_queue_interrupt(vcpu, irq->irq, false);
3703 kvm_make_request(KVM_REQ_EVENT, vcpu);
3708 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3709 * fail for in-kernel 8259.
3711 if (pic_in_kernel(vcpu->kvm))
3714 if (vcpu->arch.pending_external_vector != -1)
3717 vcpu->arch.pending_external_vector = irq->irq;
3718 kvm_make_request(KVM_REQ_EVENT, vcpu);
3722 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3724 kvm_inject_nmi(vcpu);
3729 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3731 kvm_make_request(KVM_REQ_SMI, vcpu);
3736 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3737 struct kvm_tpr_access_ctl *tac)
3741 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3745 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3749 unsigned bank_num = mcg_cap & 0xff, bank;
3752 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3754 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3757 vcpu->arch.mcg_cap = mcg_cap;
3758 /* Init IA32_MCG_CTL to all 1s */
3759 if (mcg_cap & MCG_CTL_P)
3760 vcpu->arch.mcg_ctl = ~(u64)0;
3761 /* Init IA32_MCi_CTL to all 1s */
3762 for (bank = 0; bank < bank_num; bank++)
3763 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3765 kvm_x86_ops->setup_mce(vcpu);
3770 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3771 struct kvm_x86_mce *mce)
3773 u64 mcg_cap = vcpu->arch.mcg_cap;
3774 unsigned bank_num = mcg_cap & 0xff;
3775 u64 *banks = vcpu->arch.mce_banks;
3777 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3780 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3781 * reporting is disabled
3783 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3784 vcpu->arch.mcg_ctl != ~(u64)0)
3786 banks += 4 * mce->bank;
3788 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3789 * reporting is disabled for the bank
3791 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3793 if (mce->status & MCI_STATUS_UC) {
3794 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3795 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3796 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3799 if (banks[1] & MCI_STATUS_VAL)
3800 mce->status |= MCI_STATUS_OVER;
3801 banks[2] = mce->addr;
3802 banks[3] = mce->misc;
3803 vcpu->arch.mcg_status = mce->mcg_status;
3804 banks[1] = mce->status;
3805 kvm_queue_exception(vcpu, MC_VECTOR);
3806 } else if (!(banks[1] & MCI_STATUS_VAL)
3807 || !(banks[1] & MCI_STATUS_UC)) {
3808 if (banks[1] & MCI_STATUS_VAL)
3809 mce->status |= MCI_STATUS_OVER;
3810 banks[2] = mce->addr;
3811 banks[3] = mce->misc;
3812 banks[1] = mce->status;
3814 banks[1] |= MCI_STATUS_OVER;
3818 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3819 struct kvm_vcpu_events *events)
3824 * In guest mode, payload delivery should be deferred,
3825 * so that the L1 hypervisor can intercept #PF before
3826 * CR2 is modified (or intercept #DB before DR6 is
3827 * modified under nVMX). Unless the per-VM capability,
3828 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3829 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3830 * opportunistically defer the exception payload, deliver it if the
3831 * capability hasn't been requested before processing a
3832 * KVM_GET_VCPU_EVENTS.
3834 if (!vcpu->kvm->arch.exception_payload_enabled &&
3835 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3836 kvm_deliver_exception_payload(vcpu);
3839 * The API doesn't provide the instruction length for software
3840 * exceptions, so don't report them. As long as the guest RIP
3841 * isn't advanced, we should expect to encounter the exception
3844 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3845 events->exception.injected = 0;
3846 events->exception.pending = 0;
3848 events->exception.injected = vcpu->arch.exception.injected;
3849 events->exception.pending = vcpu->arch.exception.pending;
3851 * For ABI compatibility, deliberately conflate
3852 * pending and injected exceptions when
3853 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3855 if (!vcpu->kvm->arch.exception_payload_enabled)
3856 events->exception.injected |=
3857 vcpu->arch.exception.pending;
3859 events->exception.nr = vcpu->arch.exception.nr;
3860 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3861 events->exception.error_code = vcpu->arch.exception.error_code;
3862 events->exception_has_payload = vcpu->arch.exception.has_payload;
3863 events->exception_payload = vcpu->arch.exception.payload;
3865 events->interrupt.injected =
3866 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3867 events->interrupt.nr = vcpu->arch.interrupt.nr;
3868 events->interrupt.soft = 0;
3869 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3871 events->nmi.injected = vcpu->arch.nmi_injected;
3872 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3873 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3874 events->nmi.pad = 0;
3876 events->sipi_vector = 0; /* never valid when reporting to user space */
3878 events->smi.smm = is_smm(vcpu);
3879 events->smi.pending = vcpu->arch.smi_pending;
3880 events->smi.smm_inside_nmi =
3881 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3882 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3884 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3885 | KVM_VCPUEVENT_VALID_SHADOW
3886 | KVM_VCPUEVENT_VALID_SMM);
3887 if (vcpu->kvm->arch.exception_payload_enabled)
3888 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3890 memset(&events->reserved, 0, sizeof(events->reserved));
3893 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3895 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3896 struct kvm_vcpu_events *events)
3898 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3899 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3900 | KVM_VCPUEVENT_VALID_SHADOW
3901 | KVM_VCPUEVENT_VALID_SMM
3902 | KVM_VCPUEVENT_VALID_PAYLOAD))
3905 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3906 if (!vcpu->kvm->arch.exception_payload_enabled)
3908 if (events->exception.pending)
3909 events->exception.injected = 0;
3911 events->exception_has_payload = 0;
3913 events->exception.pending = 0;
3914 events->exception_has_payload = 0;
3917 if ((events->exception.injected || events->exception.pending) &&
3918 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3921 /* INITs are latched while in SMM */
3922 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3923 (events->smi.smm || events->smi.pending) &&
3924 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3928 vcpu->arch.exception.injected = events->exception.injected;
3929 vcpu->arch.exception.pending = events->exception.pending;
3930 vcpu->arch.exception.nr = events->exception.nr;
3931 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3932 vcpu->arch.exception.error_code = events->exception.error_code;
3933 vcpu->arch.exception.has_payload = events->exception_has_payload;
3934 vcpu->arch.exception.payload = events->exception_payload;
3936 vcpu->arch.interrupt.injected = events->interrupt.injected;
3937 vcpu->arch.interrupt.nr = events->interrupt.nr;
3938 vcpu->arch.interrupt.soft = events->interrupt.soft;
3939 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3940 kvm_x86_ops->set_interrupt_shadow(vcpu,
3941 events->interrupt.shadow);
3943 vcpu->arch.nmi_injected = events->nmi.injected;
3944 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3945 vcpu->arch.nmi_pending = events->nmi.pending;
3946 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3948 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3949 lapic_in_kernel(vcpu))
3950 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3952 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3953 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3954 if (events->smi.smm)
3955 vcpu->arch.hflags |= HF_SMM_MASK;
3957 vcpu->arch.hflags &= ~HF_SMM_MASK;
3958 kvm_smm_changed(vcpu);
3961 vcpu->arch.smi_pending = events->smi.pending;
3963 if (events->smi.smm) {
3964 if (events->smi.smm_inside_nmi)
3965 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3967 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3970 if (lapic_in_kernel(vcpu)) {
3971 if (events->smi.latched_init)
3972 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3974 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3978 kvm_make_request(KVM_REQ_EVENT, vcpu);
3983 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3984 struct kvm_debugregs *dbgregs)
3988 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3989 kvm_get_dr(vcpu, 6, &val);
3991 dbgregs->dr7 = vcpu->arch.dr7;
3993 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3996 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3997 struct kvm_debugregs *dbgregs)
4002 if (dbgregs->dr6 & ~0xffffffffull)
4004 if (dbgregs->dr7 & ~0xffffffffull)
4007 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4008 kvm_update_dr0123(vcpu);
4009 vcpu->arch.dr6 = dbgregs->dr6;
4010 kvm_update_dr6(vcpu);
4011 vcpu->arch.dr7 = dbgregs->dr7;
4012 kvm_update_dr7(vcpu);
4017 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4019 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4021 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4022 u64 xstate_bv = xsave->header.xfeatures;
4026 * Copy legacy XSAVE area, to avoid complications with CPUID
4027 * leaves 0 and 1 in the loop below.
4029 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4032 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4033 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4036 * Copy each region from the possibly compacted offset to the
4037 * non-compacted offset.
4039 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4041 u64 xfeature_mask = valid & -valid;
4042 int xfeature_nr = fls64(xfeature_mask) - 1;
4043 void *src = get_xsave_addr(xsave, xfeature_nr);
4046 u32 size, offset, ecx, edx;
4047 cpuid_count(XSTATE_CPUID, xfeature_nr,
4048 &size, &offset, &ecx, &edx);
4049 if (xfeature_nr == XFEATURE_PKRU)
4050 memcpy(dest + offset, &vcpu->arch.pkru,
4051 sizeof(vcpu->arch.pkru));
4053 memcpy(dest + offset, src, size);
4057 valid -= xfeature_mask;
4061 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4063 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4064 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4068 * Copy legacy XSAVE area, to avoid complications with CPUID
4069 * leaves 0 and 1 in the loop below.
4071 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4073 /* Set XSTATE_BV and possibly XCOMP_BV. */
4074 xsave->header.xfeatures = xstate_bv;
4075 if (boot_cpu_has(X86_FEATURE_XSAVES))
4076 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4079 * Copy each region from the non-compacted offset to the
4080 * possibly compacted offset.
4082 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4084 u64 xfeature_mask = valid & -valid;
4085 int xfeature_nr = fls64(xfeature_mask) - 1;
4086 void *dest = get_xsave_addr(xsave, xfeature_nr);
4089 u32 size, offset, ecx, edx;
4090 cpuid_count(XSTATE_CPUID, xfeature_nr,
4091 &size, &offset, &ecx, &edx);
4092 if (xfeature_nr == XFEATURE_PKRU)
4093 memcpy(&vcpu->arch.pkru, src + offset,
4094 sizeof(vcpu->arch.pkru));
4096 memcpy(dest, src + offset, size);
4099 valid -= xfeature_mask;
4103 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4104 struct kvm_xsave *guest_xsave)
4106 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4107 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4108 fill_xsave((u8 *) guest_xsave->region, vcpu);
4110 memcpy(guest_xsave->region,
4111 &vcpu->arch.guest_fpu->state.fxsave,
4112 sizeof(struct fxregs_state));
4113 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4114 XFEATURE_MASK_FPSSE;
4118 #define XSAVE_MXCSR_OFFSET 24
4120 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4121 struct kvm_xsave *guest_xsave)
4124 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4125 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4127 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4129 * Here we allow setting states that are not present in
4130 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4131 * with old userspace.
4133 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4135 load_xsave(vcpu, (u8 *)guest_xsave->region);
4137 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4138 mxcsr & ~mxcsr_feature_mask)
4140 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4141 guest_xsave->region, sizeof(struct fxregs_state));
4146 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4147 struct kvm_xcrs *guest_xcrs)
4149 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4150 guest_xcrs->nr_xcrs = 0;
4154 guest_xcrs->nr_xcrs = 1;
4155 guest_xcrs->flags = 0;
4156 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4157 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4160 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4161 struct kvm_xcrs *guest_xcrs)
4165 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4168 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4171 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4172 /* Only support XCR0 currently */
4173 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4174 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4175 guest_xcrs->xcrs[i].value);
4184 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4185 * stopped by the hypervisor. This function will be called from the host only.
4186 * EINVAL is returned when the host attempts to set the flag for a guest that
4187 * does not support pv clocks.
4189 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4191 if (!vcpu->arch.pv_time_enabled)
4193 vcpu->arch.pvclock_set_guest_stopped_request = true;
4194 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4198 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4199 struct kvm_enable_cap *cap)
4202 uint16_t vmcs_version;
4203 void __user *user_ptr;
4209 case KVM_CAP_HYPERV_SYNIC2:
4214 case KVM_CAP_HYPERV_SYNIC:
4215 if (!irqchip_in_kernel(vcpu->kvm))
4217 return kvm_hv_activate_synic(vcpu, cap->cap ==
4218 KVM_CAP_HYPERV_SYNIC2);
4219 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4220 if (!kvm_x86_ops->nested_enable_evmcs)
4222 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4224 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4225 if (copy_to_user(user_ptr, &vmcs_version,
4226 sizeof(vmcs_version)))
4230 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4231 if (!kvm_x86_ops->enable_direct_tlbflush)
4234 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
4241 long kvm_arch_vcpu_ioctl(struct file *filp,
4242 unsigned int ioctl, unsigned long arg)
4244 struct kvm_vcpu *vcpu = filp->private_data;
4245 void __user *argp = (void __user *)arg;
4248 struct kvm_lapic_state *lapic;
4249 struct kvm_xsave *xsave;
4250 struct kvm_xcrs *xcrs;
4258 case KVM_GET_LAPIC: {
4260 if (!lapic_in_kernel(vcpu))
4262 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4263 GFP_KERNEL_ACCOUNT);
4268 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4272 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4277 case KVM_SET_LAPIC: {
4279 if (!lapic_in_kernel(vcpu))
4281 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4282 if (IS_ERR(u.lapic)) {
4283 r = PTR_ERR(u.lapic);
4287 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4290 case KVM_INTERRUPT: {
4291 struct kvm_interrupt irq;
4294 if (copy_from_user(&irq, argp, sizeof(irq)))
4296 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4300 r = kvm_vcpu_ioctl_nmi(vcpu);
4304 r = kvm_vcpu_ioctl_smi(vcpu);
4307 case KVM_SET_CPUID: {
4308 struct kvm_cpuid __user *cpuid_arg = argp;
4309 struct kvm_cpuid cpuid;
4312 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4314 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4317 case KVM_SET_CPUID2: {
4318 struct kvm_cpuid2 __user *cpuid_arg = argp;
4319 struct kvm_cpuid2 cpuid;
4322 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4324 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4325 cpuid_arg->entries);
4328 case KVM_GET_CPUID2: {
4329 struct kvm_cpuid2 __user *cpuid_arg = argp;
4330 struct kvm_cpuid2 cpuid;
4333 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4335 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4336 cpuid_arg->entries);
4340 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4345 case KVM_GET_MSRS: {
4346 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4347 r = msr_io(vcpu, argp, do_get_msr, 1);
4348 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4351 case KVM_SET_MSRS: {
4352 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4353 r = msr_io(vcpu, argp, do_set_msr, 0);
4354 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4357 case KVM_TPR_ACCESS_REPORTING: {
4358 struct kvm_tpr_access_ctl tac;
4361 if (copy_from_user(&tac, argp, sizeof(tac)))
4363 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4367 if (copy_to_user(argp, &tac, sizeof(tac)))
4372 case KVM_SET_VAPIC_ADDR: {
4373 struct kvm_vapic_addr va;
4377 if (!lapic_in_kernel(vcpu))
4380 if (copy_from_user(&va, argp, sizeof(va)))
4382 idx = srcu_read_lock(&vcpu->kvm->srcu);
4383 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4384 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4387 case KVM_X86_SETUP_MCE: {
4391 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4393 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4396 case KVM_X86_SET_MCE: {
4397 struct kvm_x86_mce mce;
4400 if (copy_from_user(&mce, argp, sizeof(mce)))
4402 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4405 case KVM_GET_VCPU_EVENTS: {
4406 struct kvm_vcpu_events events;
4408 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4411 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4416 case KVM_SET_VCPU_EVENTS: {
4417 struct kvm_vcpu_events events;
4420 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4423 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4426 case KVM_GET_DEBUGREGS: {
4427 struct kvm_debugregs dbgregs;
4429 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4432 if (copy_to_user(argp, &dbgregs,
4433 sizeof(struct kvm_debugregs)))
4438 case KVM_SET_DEBUGREGS: {
4439 struct kvm_debugregs dbgregs;
4442 if (copy_from_user(&dbgregs, argp,
4443 sizeof(struct kvm_debugregs)))
4446 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4449 case KVM_GET_XSAVE: {
4450 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4455 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4458 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4463 case KVM_SET_XSAVE: {
4464 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4465 if (IS_ERR(u.xsave)) {
4466 r = PTR_ERR(u.xsave);
4470 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4473 case KVM_GET_XCRS: {
4474 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4479 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4482 if (copy_to_user(argp, u.xcrs,
4483 sizeof(struct kvm_xcrs)))
4488 case KVM_SET_XCRS: {
4489 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4490 if (IS_ERR(u.xcrs)) {
4491 r = PTR_ERR(u.xcrs);
4495 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4498 case KVM_SET_TSC_KHZ: {
4502 user_tsc_khz = (u32)arg;
4504 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4507 if (user_tsc_khz == 0)
4508 user_tsc_khz = tsc_khz;
4510 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4515 case KVM_GET_TSC_KHZ: {
4516 r = vcpu->arch.virtual_tsc_khz;
4519 case KVM_KVMCLOCK_CTRL: {
4520 r = kvm_set_guest_paused(vcpu);
4523 case KVM_ENABLE_CAP: {
4524 struct kvm_enable_cap cap;
4527 if (copy_from_user(&cap, argp, sizeof(cap)))
4529 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4532 case KVM_GET_NESTED_STATE: {
4533 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4537 if (!kvm_x86_ops->get_nested_state)
4540 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4542 if (get_user(user_data_size, &user_kvm_nested_state->size))
4545 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4550 if (r > user_data_size) {
4551 if (put_user(r, &user_kvm_nested_state->size))
4561 case KVM_SET_NESTED_STATE: {
4562 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4563 struct kvm_nested_state kvm_state;
4567 if (!kvm_x86_ops->set_nested_state)
4571 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4575 if (kvm_state.size < sizeof(kvm_state))
4578 if (kvm_state.flags &
4579 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4580 | KVM_STATE_NESTED_EVMCS))
4583 /* nested_run_pending implies guest_mode. */
4584 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4585 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4588 idx = srcu_read_lock(&vcpu->kvm->srcu);
4589 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4590 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4593 case KVM_GET_SUPPORTED_HV_CPUID: {
4594 struct kvm_cpuid2 __user *cpuid_arg = argp;
4595 struct kvm_cpuid2 cpuid;
4598 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4601 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4602 cpuid_arg->entries);
4607 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4622 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4624 return VM_FAULT_SIGBUS;
4627 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4631 if (addr > (unsigned int)(-3 * PAGE_SIZE))
4633 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4637 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4640 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
4643 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4644 unsigned long kvm_nr_mmu_pages)
4646 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4649 mutex_lock(&kvm->slots_lock);
4651 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4652 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4654 mutex_unlock(&kvm->slots_lock);
4658 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4660 return kvm->arch.n_max_mmu_pages;
4663 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4665 struct kvm_pic *pic = kvm->arch.vpic;
4669 switch (chip->chip_id) {
4670 case KVM_IRQCHIP_PIC_MASTER:
4671 memcpy(&chip->chip.pic, &pic->pics[0],
4672 sizeof(struct kvm_pic_state));
4674 case KVM_IRQCHIP_PIC_SLAVE:
4675 memcpy(&chip->chip.pic, &pic->pics[1],
4676 sizeof(struct kvm_pic_state));
4678 case KVM_IRQCHIP_IOAPIC:
4679 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4688 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4690 struct kvm_pic *pic = kvm->arch.vpic;
4694 switch (chip->chip_id) {
4695 case KVM_IRQCHIP_PIC_MASTER:
4696 spin_lock(&pic->lock);
4697 memcpy(&pic->pics[0], &chip->chip.pic,
4698 sizeof(struct kvm_pic_state));
4699 spin_unlock(&pic->lock);
4701 case KVM_IRQCHIP_PIC_SLAVE:
4702 spin_lock(&pic->lock);
4703 memcpy(&pic->pics[1], &chip->chip.pic,
4704 sizeof(struct kvm_pic_state));
4705 spin_unlock(&pic->lock);
4707 case KVM_IRQCHIP_IOAPIC:
4708 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4714 kvm_pic_update_irq(pic);
4718 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4720 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4722 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4724 mutex_lock(&kps->lock);
4725 memcpy(ps, &kps->channels, sizeof(*ps));
4726 mutex_unlock(&kps->lock);
4730 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4733 struct kvm_pit *pit = kvm->arch.vpit;
4735 mutex_lock(&pit->pit_state.lock);
4736 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4737 for (i = 0; i < 3; i++)
4738 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4739 mutex_unlock(&pit->pit_state.lock);
4743 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4745 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4746 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4747 sizeof(ps->channels));
4748 ps->flags = kvm->arch.vpit->pit_state.flags;
4749 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4750 memset(&ps->reserved, 0, sizeof(ps->reserved));
4754 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4758 u32 prev_legacy, cur_legacy;
4759 struct kvm_pit *pit = kvm->arch.vpit;
4761 mutex_lock(&pit->pit_state.lock);
4762 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4763 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4764 if (!prev_legacy && cur_legacy)
4766 memcpy(&pit->pit_state.channels, &ps->channels,
4767 sizeof(pit->pit_state.channels));
4768 pit->pit_state.flags = ps->flags;
4769 for (i = 0; i < 3; i++)
4770 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4772 mutex_unlock(&pit->pit_state.lock);
4776 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4777 struct kvm_reinject_control *control)
4779 struct kvm_pit *pit = kvm->arch.vpit;
4781 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4782 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4783 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4785 mutex_lock(&pit->pit_state.lock);
4786 kvm_pit_set_reinject(pit, control->pit_reinject);
4787 mutex_unlock(&pit->pit_state.lock);
4792 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
4795 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4797 if (kvm_x86_ops->flush_log_dirty)
4798 kvm_x86_ops->flush_log_dirty(kvm);
4801 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4804 if (!irqchip_in_kernel(kvm))
4807 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4808 irq_event->irq, irq_event->level,
4813 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4814 struct kvm_enable_cap *cap)
4822 case KVM_CAP_DISABLE_QUIRKS:
4823 kvm->arch.disabled_quirks = cap->args[0];
4826 case KVM_CAP_SPLIT_IRQCHIP: {
4827 mutex_lock(&kvm->lock);
4829 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4830 goto split_irqchip_unlock;
4832 if (irqchip_in_kernel(kvm))
4833 goto split_irqchip_unlock;
4834 if (kvm->created_vcpus)
4835 goto split_irqchip_unlock;
4836 r = kvm_setup_empty_irq_routing(kvm);
4838 goto split_irqchip_unlock;
4839 /* Pairs with irqchip_in_kernel. */
4841 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4842 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4844 split_irqchip_unlock:
4845 mutex_unlock(&kvm->lock);
4848 case KVM_CAP_X2APIC_API:
4850 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4853 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4854 kvm->arch.x2apic_format = true;
4855 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4856 kvm->arch.x2apic_broadcast_quirk_disabled = true;
4860 case KVM_CAP_X86_DISABLE_EXITS:
4862 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4865 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4866 kvm_can_mwait_in_guest())
4867 kvm->arch.mwait_in_guest = true;
4868 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4869 kvm->arch.hlt_in_guest = true;
4870 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4871 kvm->arch.pause_in_guest = true;
4872 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4873 kvm->arch.cstate_in_guest = true;
4876 case KVM_CAP_MSR_PLATFORM_INFO:
4877 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4880 case KVM_CAP_EXCEPTION_PAYLOAD:
4881 kvm->arch.exception_payload_enabled = cap->args[0];
4891 long kvm_arch_vm_ioctl(struct file *filp,
4892 unsigned int ioctl, unsigned long arg)
4894 struct kvm *kvm = filp->private_data;
4895 void __user *argp = (void __user *)arg;
4898 * This union makes it completely explicit to gcc-3.x
4899 * that these two variables' stack usage should be
4900 * combined, not added together.
4903 struct kvm_pit_state ps;
4904 struct kvm_pit_state2 ps2;
4905 struct kvm_pit_config pit_config;
4909 case KVM_SET_TSS_ADDR:
4910 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4912 case KVM_SET_IDENTITY_MAP_ADDR: {
4915 mutex_lock(&kvm->lock);
4917 if (kvm->created_vcpus)
4918 goto set_identity_unlock;
4920 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4921 goto set_identity_unlock;
4922 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4923 set_identity_unlock:
4924 mutex_unlock(&kvm->lock);
4927 case KVM_SET_NR_MMU_PAGES:
4928 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4930 case KVM_GET_NR_MMU_PAGES:
4931 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4933 case KVM_CREATE_IRQCHIP: {
4934 mutex_lock(&kvm->lock);
4937 if (irqchip_in_kernel(kvm))
4938 goto create_irqchip_unlock;
4941 if (kvm->created_vcpus)
4942 goto create_irqchip_unlock;
4944 r = kvm_pic_init(kvm);
4946 goto create_irqchip_unlock;
4948 r = kvm_ioapic_init(kvm);
4950 kvm_pic_destroy(kvm);
4951 goto create_irqchip_unlock;
4954 r = kvm_setup_default_irq_routing(kvm);
4956 kvm_ioapic_destroy(kvm);
4957 kvm_pic_destroy(kvm);
4958 goto create_irqchip_unlock;
4960 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4962 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4963 create_irqchip_unlock:
4964 mutex_unlock(&kvm->lock);
4967 case KVM_CREATE_PIT:
4968 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4970 case KVM_CREATE_PIT2:
4972 if (copy_from_user(&u.pit_config, argp,
4973 sizeof(struct kvm_pit_config)))
4976 mutex_lock(&kvm->lock);
4979 goto create_pit_unlock;
4981 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4985 mutex_unlock(&kvm->lock);
4987 case KVM_GET_IRQCHIP: {
4988 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4989 struct kvm_irqchip *chip;
4991 chip = memdup_user(argp, sizeof(*chip));
4998 if (!irqchip_kernel(kvm))
4999 goto get_irqchip_out;
5000 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5002 goto get_irqchip_out;
5004 if (copy_to_user(argp, chip, sizeof(*chip)))
5005 goto get_irqchip_out;
5011 case KVM_SET_IRQCHIP: {
5012 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5013 struct kvm_irqchip *chip;
5015 chip = memdup_user(argp, sizeof(*chip));
5022 if (!irqchip_kernel(kvm))
5023 goto set_irqchip_out;
5024 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5031 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5034 if (!kvm->arch.vpit)
5036 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5040 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5047 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5050 if (!kvm->arch.vpit)
5052 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5055 case KVM_GET_PIT2: {
5057 if (!kvm->arch.vpit)
5059 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5063 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5068 case KVM_SET_PIT2: {
5070 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5073 if (!kvm->arch.vpit)
5075 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5078 case KVM_REINJECT_CONTROL: {
5079 struct kvm_reinject_control control;
5081 if (copy_from_user(&control, argp, sizeof(control)))
5084 if (!kvm->arch.vpit)
5086 r = kvm_vm_ioctl_reinject(kvm, &control);
5089 case KVM_SET_BOOT_CPU_ID:
5091 mutex_lock(&kvm->lock);
5092 if (kvm->created_vcpus)
5095 kvm->arch.bsp_vcpu_id = arg;
5096 mutex_unlock(&kvm->lock);
5098 case KVM_XEN_HVM_CONFIG: {
5099 struct kvm_xen_hvm_config xhc;
5101 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5106 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5110 case KVM_SET_CLOCK: {
5111 struct kvm_clock_data user_ns;
5115 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5124 * TODO: userspace has to take care of races with VCPU_RUN, so
5125 * kvm_gen_update_masterclock() can be cut down to locked
5126 * pvclock_update_vm_gtod_copy().
5128 kvm_gen_update_masterclock(kvm);
5129 now_ns = get_kvmclock_ns(kvm);
5130 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5131 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5134 case KVM_GET_CLOCK: {
5135 struct kvm_clock_data user_ns;
5138 now_ns = get_kvmclock_ns(kvm);
5139 user_ns.clock = now_ns;
5140 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5141 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5144 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5149 case KVM_MEMORY_ENCRYPT_OP: {
5151 if (kvm_x86_ops->mem_enc_op)
5152 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5155 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5156 struct kvm_enc_region region;
5159 if (copy_from_user(®ion, argp, sizeof(region)))
5163 if (kvm_x86_ops->mem_enc_reg_region)
5164 r = kvm_x86_ops->mem_enc_reg_region(kvm, ®ion);
5167 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5168 struct kvm_enc_region region;
5171 if (copy_from_user(®ion, argp, sizeof(region)))
5175 if (kvm_x86_ops->mem_enc_unreg_region)
5176 r = kvm_x86_ops->mem_enc_unreg_region(kvm, ®ion);
5179 case KVM_HYPERV_EVENTFD: {
5180 struct kvm_hyperv_eventfd hvevfd;
5183 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5185 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5188 case KVM_SET_PMU_EVENT_FILTER:
5189 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5198 static void kvm_init_msr_list(void)
5200 struct x86_pmu_capability x86_pmu;
5204 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5205 "Please update the fixed PMCs in msrs_to_saved_all[]");
5207 perf_get_x86_pmu_capability(&x86_pmu);
5209 num_msrs_to_save = 0;
5210 num_emulated_msrs = 0;
5211 num_msr_based_features = 0;
5213 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5214 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5218 * Even MSRs that are valid in the host may not be exposed
5219 * to the guests in some cases.
5221 switch (msrs_to_save_all[i]) {
5222 case MSR_IA32_BNDCFGS:
5223 if (!kvm_mpx_supported())
5227 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5230 case MSR_IA32_RTIT_CTL:
5231 case MSR_IA32_RTIT_STATUS:
5232 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5235 case MSR_IA32_RTIT_CR3_MATCH:
5236 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5237 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5240 case MSR_IA32_RTIT_OUTPUT_BASE:
5241 case MSR_IA32_RTIT_OUTPUT_MASK:
5242 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5243 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5244 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5247 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5248 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5249 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5250 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5253 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5254 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5255 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5258 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5259 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5260 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5267 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5270 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5271 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs_all[i]))
5274 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5277 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5278 struct kvm_msr_entry msr;
5280 msr.index = msr_based_features_all[i];
5281 if (kvm_get_msr_feature(&msr))
5284 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5288 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5296 if (!(lapic_in_kernel(vcpu) &&
5297 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5298 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5309 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5316 if (!(lapic_in_kernel(vcpu) &&
5317 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5319 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5321 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5331 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5332 struct kvm_segment *var, int seg)
5334 kvm_x86_ops->set_segment(vcpu, var, seg);
5337 void kvm_get_segment(struct kvm_vcpu *vcpu,
5338 struct kvm_segment *var, int seg)
5340 kvm_x86_ops->get_segment(vcpu, var, seg);
5343 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5344 struct x86_exception *exception)
5348 BUG_ON(!mmu_is_nested(vcpu));
5350 /* NPT walks are always user-walks */
5351 access |= PFERR_USER_MASK;
5352 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5357 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5358 struct x86_exception *exception)
5360 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5361 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5364 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5365 struct x86_exception *exception)
5367 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5368 access |= PFERR_FETCH_MASK;
5369 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5372 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5373 struct x86_exception *exception)
5375 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5376 access |= PFERR_WRITE_MASK;
5377 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5380 /* uses this to access any guest's mapped memory without checking CPL */
5381 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5382 struct x86_exception *exception)
5384 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5387 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5388 struct kvm_vcpu *vcpu, u32 access,
5389 struct x86_exception *exception)
5392 int r = X86EMUL_CONTINUE;
5395 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5397 unsigned offset = addr & (PAGE_SIZE-1);
5398 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5401 if (gpa == UNMAPPED_GVA)
5402 return X86EMUL_PROPAGATE_FAULT;
5403 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5406 r = X86EMUL_IO_NEEDED;
5418 /* used for instruction fetching */
5419 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5420 gva_t addr, void *val, unsigned int bytes,
5421 struct x86_exception *exception)
5423 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5424 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5428 /* Inline kvm_read_guest_virt_helper for speed. */
5429 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5431 if (unlikely(gpa == UNMAPPED_GVA))
5432 return X86EMUL_PROPAGATE_FAULT;
5434 offset = addr & (PAGE_SIZE-1);
5435 if (WARN_ON(offset + bytes > PAGE_SIZE))
5436 bytes = (unsigned)PAGE_SIZE - offset;
5437 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5439 if (unlikely(ret < 0))
5440 return X86EMUL_IO_NEEDED;
5442 return X86EMUL_CONTINUE;
5445 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5446 gva_t addr, void *val, unsigned int bytes,
5447 struct x86_exception *exception)
5449 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5452 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5453 * is returned, but our callers are not ready for that and they blindly
5454 * call kvm_inject_page_fault. Ensure that they at least do not leak
5455 * uninitialized kernel stack memory into cr2 and error code.
5457 memset(exception, 0, sizeof(*exception));
5458 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5461 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5463 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5464 gva_t addr, void *val, unsigned int bytes,
5465 struct x86_exception *exception, bool system)
5467 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5470 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5471 access |= PFERR_USER_MASK;
5473 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5476 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5477 unsigned long addr, void *val, unsigned int bytes)
5479 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5480 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5482 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5485 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5486 struct kvm_vcpu *vcpu, u32 access,
5487 struct x86_exception *exception)
5490 int r = X86EMUL_CONTINUE;
5493 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5496 unsigned offset = addr & (PAGE_SIZE-1);
5497 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5500 if (gpa == UNMAPPED_GVA)
5501 return X86EMUL_PROPAGATE_FAULT;
5502 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5504 r = X86EMUL_IO_NEEDED;
5516 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5517 unsigned int bytes, struct x86_exception *exception,
5520 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5521 u32 access = PFERR_WRITE_MASK;
5523 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5524 access |= PFERR_USER_MASK;
5526 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5530 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5531 unsigned int bytes, struct x86_exception *exception)
5533 /* kvm_write_guest_virt_system can pull in tons of pages. */
5534 vcpu->arch.l1tf_flush_l1d = true;
5537 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5538 * is returned, but our callers are not ready for that and they blindly
5539 * call kvm_inject_page_fault. Ensure that they at least do not leak
5540 * uninitialized kernel stack memory into cr2 and error code.
5542 memset(exception, 0, sizeof(*exception));
5543 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5544 PFERR_WRITE_MASK, exception);
5546 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5548 int handle_ud(struct kvm_vcpu *vcpu)
5550 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5551 int emul_type = EMULTYPE_TRAP_UD;
5552 char sig[5]; /* ud2; .ascii "kvm" */
5553 struct x86_exception e;
5555 if (force_emulation_prefix &&
5556 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5557 sig, sizeof(sig), &e) == 0 &&
5558 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5559 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5560 emul_type = EMULTYPE_TRAP_UD_FORCED;
5563 return kvm_emulate_instruction(vcpu, emul_type);
5565 EXPORT_SYMBOL_GPL(handle_ud);
5567 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5568 gpa_t gpa, bool write)
5570 /* For APIC access vmexit */
5571 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5574 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5575 trace_vcpu_match_mmio(gva, gpa, write, true);
5582 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5583 gpa_t *gpa, struct x86_exception *exception,
5586 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5587 | (write ? PFERR_WRITE_MASK : 0);
5590 * currently PKRU is only applied to ept enabled guest so
5591 * there is no pkey in EPT page table for L1 guest or EPT
5592 * shadow page table for L2 guest.
5594 if (vcpu_match_mmio_gva(vcpu, gva)
5595 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5596 vcpu->arch.mmio_access, 0, access)) {
5597 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5598 (gva & (PAGE_SIZE - 1));
5599 trace_vcpu_match_mmio(gva, *gpa, write, false);
5603 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5605 if (*gpa == UNMAPPED_GVA)
5608 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5611 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5612 const void *val, int bytes)
5616 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5619 kvm_page_track_write(vcpu, gpa, val, bytes);
5623 struct read_write_emulator_ops {
5624 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5626 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5627 void *val, int bytes);
5628 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5629 int bytes, void *val);
5630 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5631 void *val, int bytes);
5635 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5637 if (vcpu->mmio_read_completed) {
5638 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5639 vcpu->mmio_fragments[0].gpa, val);
5640 vcpu->mmio_read_completed = 0;
5647 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5648 void *val, int bytes)
5650 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5653 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5654 void *val, int bytes)
5656 return emulator_write_phys(vcpu, gpa, val, bytes);
5659 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5661 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5662 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5665 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5666 void *val, int bytes)
5668 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5669 return X86EMUL_IO_NEEDED;
5672 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5673 void *val, int bytes)
5675 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5677 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5678 return X86EMUL_CONTINUE;
5681 static const struct read_write_emulator_ops read_emultor = {
5682 .read_write_prepare = read_prepare,
5683 .read_write_emulate = read_emulate,
5684 .read_write_mmio = vcpu_mmio_read,
5685 .read_write_exit_mmio = read_exit_mmio,
5688 static const struct read_write_emulator_ops write_emultor = {
5689 .read_write_emulate = write_emulate,
5690 .read_write_mmio = write_mmio,
5691 .read_write_exit_mmio = write_exit_mmio,
5695 static int emulator_read_write_onepage(unsigned long addr, void *val,
5697 struct x86_exception *exception,
5698 struct kvm_vcpu *vcpu,
5699 const struct read_write_emulator_ops *ops)
5703 bool write = ops->write;
5704 struct kvm_mmio_fragment *frag;
5705 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
5708 * If the exit was due to a NPF we may already have a GPA.
5709 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5710 * Note, this cannot be used on string operations since string
5711 * operation using rep will only have the initial GPA from the NPF
5714 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
5715 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
5716 gpa = ctxt->gpa_val;
5717 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5719 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5721 return X86EMUL_PROPAGATE_FAULT;
5724 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5725 return X86EMUL_CONTINUE;
5728 * Is this MMIO handled locally?
5730 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5731 if (handled == bytes)
5732 return X86EMUL_CONTINUE;
5738 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5739 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5743 return X86EMUL_CONTINUE;
5746 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5748 void *val, unsigned int bytes,
5749 struct x86_exception *exception,
5750 const struct read_write_emulator_ops *ops)
5752 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5756 if (ops->read_write_prepare &&
5757 ops->read_write_prepare(vcpu, val, bytes))
5758 return X86EMUL_CONTINUE;
5760 vcpu->mmio_nr_fragments = 0;
5762 /* Crossing a page boundary? */
5763 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5766 now = -addr & ~PAGE_MASK;
5767 rc = emulator_read_write_onepage(addr, val, now, exception,
5770 if (rc != X86EMUL_CONTINUE)
5773 if (ctxt->mode != X86EMUL_MODE_PROT64)
5779 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5781 if (rc != X86EMUL_CONTINUE)
5784 if (!vcpu->mmio_nr_fragments)
5787 gpa = vcpu->mmio_fragments[0].gpa;
5789 vcpu->mmio_needed = 1;
5790 vcpu->mmio_cur_fragment = 0;
5792 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5793 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5794 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5795 vcpu->run->mmio.phys_addr = gpa;
5797 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5800 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5804 struct x86_exception *exception)
5806 return emulator_read_write(ctxt, addr, val, bytes,
5807 exception, &read_emultor);
5810 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5814 struct x86_exception *exception)
5816 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5817 exception, &write_emultor);
5820 #define CMPXCHG_TYPE(t, ptr, old, new) \
5821 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5823 #ifdef CONFIG_X86_64
5824 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5826 # define CMPXCHG64(ptr, old, new) \
5827 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5830 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5835 struct x86_exception *exception)
5837 struct kvm_host_map map;
5838 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5843 /* guests cmpxchg8b have to be emulated atomically */
5844 if (bytes > 8 || (bytes & (bytes - 1)))
5847 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5849 if (gpa == UNMAPPED_GVA ||
5850 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5853 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5856 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5859 kaddr = map.hva + offset_in_page(gpa);
5863 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5866 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5869 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5872 exchanged = CMPXCHG64(kaddr, old, new);
5878 kvm_vcpu_unmap(vcpu, &map, true);
5881 return X86EMUL_CMPXCHG_FAILED;
5883 kvm_page_track_write(vcpu, gpa, new, bytes);
5885 return X86EMUL_CONTINUE;
5888 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5890 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5893 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5897 for (i = 0; i < vcpu->arch.pio.count; i++) {
5898 if (vcpu->arch.pio.in)
5899 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5900 vcpu->arch.pio.size, pd);
5902 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5903 vcpu->arch.pio.port, vcpu->arch.pio.size,
5907 pd += vcpu->arch.pio.size;
5912 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5913 unsigned short port, void *val,
5914 unsigned int count, bool in)
5916 vcpu->arch.pio.port = port;
5917 vcpu->arch.pio.in = in;
5918 vcpu->arch.pio.count = count;
5919 vcpu->arch.pio.size = size;
5921 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5922 vcpu->arch.pio.count = 0;
5926 vcpu->run->exit_reason = KVM_EXIT_IO;
5927 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5928 vcpu->run->io.size = size;
5929 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5930 vcpu->run->io.count = count;
5931 vcpu->run->io.port = port;
5936 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
5937 unsigned short port, void *val, unsigned int count)
5941 if (vcpu->arch.pio.count)
5944 memset(vcpu->arch.pio_data, 0, size * count);
5946 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5949 memcpy(val, vcpu->arch.pio_data, size * count);
5950 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5951 vcpu->arch.pio.count = 0;
5958 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5959 int size, unsigned short port, void *val,
5962 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
5966 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
5967 unsigned short port, const void *val,
5970 memcpy(vcpu->arch.pio_data, val, size * count);
5971 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5972 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5975 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5976 int size, unsigned short port,
5977 const void *val, unsigned int count)
5979 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
5982 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5984 return kvm_x86_ops->get_segment_base(vcpu, seg);
5987 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5989 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5992 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
5994 if (!need_emulate_wbinvd(vcpu))
5995 return X86EMUL_CONTINUE;
5997 if (kvm_x86_ops->has_wbinvd_exit()) {
5998 int cpu = get_cpu();
6000 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6001 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6002 wbinvd_ipi, NULL, 1);
6004 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6007 return X86EMUL_CONTINUE;
6010 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6012 kvm_emulate_wbinvd_noskip(vcpu);
6013 return kvm_skip_emulated_instruction(vcpu);
6015 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6019 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6021 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6024 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6025 unsigned long *dest)
6027 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6030 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6031 unsigned long value)
6034 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6037 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6039 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6042 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6044 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6045 unsigned long value;
6049 value = kvm_read_cr0(vcpu);
6052 value = vcpu->arch.cr2;
6055 value = kvm_read_cr3(vcpu);
6058 value = kvm_read_cr4(vcpu);
6061 value = kvm_get_cr8(vcpu);
6064 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6071 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6073 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6078 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6081 vcpu->arch.cr2 = val;
6084 res = kvm_set_cr3(vcpu, val);
6087 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6090 res = kvm_set_cr8(vcpu, val);
6093 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6100 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6102 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
6105 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6107 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
6110 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6112 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
6115 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6117 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6120 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6122 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6125 static unsigned long emulator_get_cached_segment_base(
6126 struct x86_emulate_ctxt *ctxt, int seg)
6128 return get_segment_base(emul_to_vcpu(ctxt), seg);
6131 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6132 struct desc_struct *desc, u32 *base3,
6135 struct kvm_segment var;
6137 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6138 *selector = var.selector;
6141 memset(desc, 0, sizeof(*desc));
6149 set_desc_limit(desc, var.limit);
6150 set_desc_base(desc, (unsigned long)var.base);
6151 #ifdef CONFIG_X86_64
6153 *base3 = var.base >> 32;
6155 desc->type = var.type;
6157 desc->dpl = var.dpl;
6158 desc->p = var.present;
6159 desc->avl = var.avl;
6167 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6168 struct desc_struct *desc, u32 base3,
6171 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6172 struct kvm_segment var;
6174 var.selector = selector;
6175 var.base = get_desc_base(desc);
6176 #ifdef CONFIG_X86_64
6177 var.base |= ((u64)base3) << 32;
6179 var.limit = get_desc_limit(desc);
6181 var.limit = (var.limit << 12) | 0xfff;
6182 var.type = desc->type;
6183 var.dpl = desc->dpl;
6188 var.avl = desc->avl;
6189 var.present = desc->p;
6190 var.unusable = !var.present;
6193 kvm_set_segment(vcpu, &var, seg);
6197 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6198 u32 msr_index, u64 *pdata)
6200 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6203 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6204 u32 msr_index, u64 data)
6206 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6209 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6211 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6213 return vcpu->arch.smbase;
6216 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6218 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6220 vcpu->arch.smbase = smbase;
6223 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6226 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6229 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6230 u32 pmc, u64 *pdata)
6232 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6235 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6237 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6240 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6241 struct x86_instruction_info *info,
6242 enum x86_intercept_stage stage)
6244 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage,
6248 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6249 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6252 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6255 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6257 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6260 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6262 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6265 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6267 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6270 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6272 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6275 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6277 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6280 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6282 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6285 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6287 return emul_to_vcpu(ctxt)->arch.hflags;
6290 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6292 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6295 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6296 const char *smstate)
6298 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6301 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6303 kvm_smm_changed(emul_to_vcpu(ctxt));
6306 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6308 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6311 static const struct x86_emulate_ops emulate_ops = {
6312 .read_gpr = emulator_read_gpr,
6313 .write_gpr = emulator_write_gpr,
6314 .read_std = emulator_read_std,
6315 .write_std = emulator_write_std,
6316 .read_phys = kvm_read_guest_phys_system,
6317 .fetch = kvm_fetch_guest_virt,
6318 .read_emulated = emulator_read_emulated,
6319 .write_emulated = emulator_write_emulated,
6320 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6321 .invlpg = emulator_invlpg,
6322 .pio_in_emulated = emulator_pio_in_emulated,
6323 .pio_out_emulated = emulator_pio_out_emulated,
6324 .get_segment = emulator_get_segment,
6325 .set_segment = emulator_set_segment,
6326 .get_cached_segment_base = emulator_get_cached_segment_base,
6327 .get_gdt = emulator_get_gdt,
6328 .get_idt = emulator_get_idt,
6329 .set_gdt = emulator_set_gdt,
6330 .set_idt = emulator_set_idt,
6331 .get_cr = emulator_get_cr,
6332 .set_cr = emulator_set_cr,
6333 .cpl = emulator_get_cpl,
6334 .get_dr = emulator_get_dr,
6335 .set_dr = emulator_set_dr,
6336 .get_smbase = emulator_get_smbase,
6337 .set_smbase = emulator_set_smbase,
6338 .set_msr = emulator_set_msr,
6339 .get_msr = emulator_get_msr,
6340 .check_pmc = emulator_check_pmc,
6341 .read_pmc = emulator_read_pmc,
6342 .halt = emulator_halt,
6343 .wbinvd = emulator_wbinvd,
6344 .fix_hypercall = emulator_fix_hypercall,
6345 .intercept = emulator_intercept,
6346 .get_cpuid = emulator_get_cpuid,
6347 .guest_has_long_mode = emulator_guest_has_long_mode,
6348 .guest_has_movbe = emulator_guest_has_movbe,
6349 .guest_has_fxsr = emulator_guest_has_fxsr,
6350 .set_nmi_mask = emulator_set_nmi_mask,
6351 .get_hflags = emulator_get_hflags,
6352 .set_hflags = emulator_set_hflags,
6353 .pre_leave_smm = emulator_pre_leave_smm,
6354 .post_leave_smm = emulator_post_leave_smm,
6355 .set_xcr = emulator_set_xcr,
6358 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6360 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
6362 * an sti; sti; sequence only disable interrupts for the first
6363 * instruction. So, if the last instruction, be it emulated or
6364 * not, left the system with the INT_STI flag enabled, it
6365 * means that the last instruction is an sti. We should not
6366 * leave the flag on in this case. The same goes for mov ss
6368 if (int_shadow & mask)
6370 if (unlikely(int_shadow || mask)) {
6371 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6373 kvm_make_request(KVM_REQ_EVENT, vcpu);
6377 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6379 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6380 if (ctxt->exception.vector == PF_VECTOR)
6381 return kvm_propagate_fault(vcpu, &ctxt->exception);
6383 if (ctxt->exception.error_code_valid)
6384 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6385 ctxt->exception.error_code);
6387 kvm_queue_exception(vcpu, ctxt->exception.vector);
6391 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6393 struct x86_emulate_ctxt *ctxt;
6395 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6397 pr_err("kvm: failed to allocate vcpu's emulator\n");
6402 ctxt->ops = &emulate_ops;
6403 vcpu->arch.emulate_ctxt = ctxt;
6408 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6410 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6413 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6415 ctxt->gpa_available = false;
6416 ctxt->eflags = kvm_get_rflags(vcpu);
6417 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6419 ctxt->eip = kvm_rip_read(vcpu);
6420 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6421 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6422 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6423 cs_db ? X86EMUL_MODE_PROT32 :
6424 X86EMUL_MODE_PROT16;
6425 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6426 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6427 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6429 init_decode_cache(ctxt);
6430 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6433 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6435 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6438 init_emulate_ctxt(vcpu);
6442 ctxt->_eip = ctxt->eip + inc_eip;
6443 ret = emulate_int_real(ctxt, irq);
6445 if (ret != X86EMUL_CONTINUE) {
6446 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6448 ctxt->eip = ctxt->_eip;
6449 kvm_rip_write(vcpu, ctxt->eip);
6450 kvm_set_rflags(vcpu, ctxt->eflags);
6453 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6455 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6457 ++vcpu->stat.insn_emulation_fail;
6458 trace_kvm_emulate_insn_failed(vcpu);
6460 if (emulation_type & EMULTYPE_VMWARE_GP) {
6461 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6465 if (emulation_type & EMULTYPE_SKIP) {
6466 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6467 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6468 vcpu->run->internal.ndata = 0;
6472 kvm_queue_exception(vcpu, UD_VECTOR);
6474 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
6475 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6476 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6477 vcpu->run->internal.ndata = 0;
6484 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6485 bool write_fault_to_shadow_pgtable,
6488 gpa_t gpa = cr2_or_gpa;
6491 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6494 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6495 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6498 if (!vcpu->arch.mmu->direct_map) {
6500 * Write permission should be allowed since only
6501 * write access need to be emulated.
6503 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6506 * If the mapping is invalid in guest, let cpu retry
6507 * it to generate fault.
6509 if (gpa == UNMAPPED_GVA)
6514 * Do not retry the unhandleable instruction if it faults on the
6515 * readonly host memory, otherwise it will goto a infinite loop:
6516 * retry instruction -> write #PF -> emulation fail -> retry
6517 * instruction -> ...
6519 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6522 * If the instruction failed on the error pfn, it can not be fixed,
6523 * report the error to userspace.
6525 if (is_error_noslot_pfn(pfn))
6528 kvm_release_pfn_clean(pfn);
6530 /* The instructions are well-emulated on direct mmu. */
6531 if (vcpu->arch.mmu->direct_map) {
6532 unsigned int indirect_shadow_pages;
6534 spin_lock(&vcpu->kvm->mmu_lock);
6535 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6536 spin_unlock(&vcpu->kvm->mmu_lock);
6538 if (indirect_shadow_pages)
6539 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6545 * if emulation was due to access to shadowed page table
6546 * and it failed try to unshadow page and re-enter the
6547 * guest to let CPU execute the instruction.
6549 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6552 * If the access faults on its page table, it can not
6553 * be fixed by unprotecting shadow page and it should
6554 * be reported to userspace.
6556 return !write_fault_to_shadow_pgtable;
6559 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6560 gpa_t cr2_or_gpa, int emulation_type)
6562 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6563 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6565 last_retry_eip = vcpu->arch.last_retry_eip;
6566 last_retry_addr = vcpu->arch.last_retry_addr;
6569 * If the emulation is caused by #PF and it is non-page_table
6570 * writing instruction, it means the VM-EXIT is caused by shadow
6571 * page protected, we can zap the shadow page and retry this
6572 * instruction directly.
6574 * Note: if the guest uses a non-page-table modifying instruction
6575 * on the PDE that points to the instruction, then we will unmap
6576 * the instruction and go to an infinite loop. So, we cache the
6577 * last retried eip and the last fault address, if we meet the eip
6578 * and the address again, we can break out of the potential infinite
6581 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6583 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6586 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6587 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6590 if (x86_page_table_writing_insn(ctxt))
6593 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6596 vcpu->arch.last_retry_eip = ctxt->eip;
6597 vcpu->arch.last_retry_addr = cr2_or_gpa;
6599 if (!vcpu->arch.mmu->direct_map)
6600 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6602 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6607 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6608 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6610 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6612 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6613 /* This is a good place to trace that we are exiting SMM. */
6614 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6616 /* Process a latched INIT or SMI, if any. */
6617 kvm_make_request(KVM_REQ_EVENT, vcpu);
6620 kvm_mmu_reset_context(vcpu);
6623 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6632 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6633 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6638 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6640 struct kvm_run *kvm_run = vcpu->run;
6642 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6643 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6644 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6645 kvm_run->debug.arch.exception = DB_VECTOR;
6646 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6649 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6653 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6655 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6658 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6663 * rflags is the old, "raw" value of the flags. The new value has
6664 * not been saved yet.
6666 * This is correct even for TF set by the guest, because "the
6667 * processor will not generate this exception after the instruction
6668 * that sets the TF flag".
6670 if (unlikely(rflags & X86_EFLAGS_TF))
6671 r = kvm_vcpu_do_singlestep(vcpu);
6674 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6676 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6678 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6679 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6680 struct kvm_run *kvm_run = vcpu->run;
6681 unsigned long eip = kvm_get_linear_rip(vcpu);
6682 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6683 vcpu->arch.guest_debug_dr7,
6687 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6688 kvm_run->debug.arch.pc = eip;
6689 kvm_run->debug.arch.exception = DB_VECTOR;
6690 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6696 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6697 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6698 unsigned long eip = kvm_get_linear_rip(vcpu);
6699 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6704 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6705 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6706 kvm_queue_exception(vcpu, DB_VECTOR);
6715 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6717 switch (ctxt->opcode_len) {
6724 case 0xe6: /* OUT */
6728 case 0x6c: /* INS */
6730 case 0x6e: /* OUTS */
6737 case 0x33: /* RDPMC */
6746 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6747 int emulation_type, void *insn, int insn_len)
6750 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6751 bool writeback = true;
6752 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6754 vcpu->arch.l1tf_flush_l1d = true;
6757 * Clear write_fault_to_shadow_pgtable here to ensure it is
6760 vcpu->arch.write_fault_to_shadow_pgtable = false;
6761 kvm_clear_exception_queue(vcpu);
6763 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6764 init_emulate_ctxt(vcpu);
6767 * We will reenter on the same instruction since
6768 * we do not set complete_userspace_io. This does not
6769 * handle watchpoints yet, those would be handled in
6772 if (!(emulation_type & EMULTYPE_SKIP) &&
6773 kvm_vcpu_check_breakpoint(vcpu, &r))
6776 ctxt->interruptibility = 0;
6777 ctxt->have_exception = false;
6778 ctxt->exception.vector = -1;
6779 ctxt->perm_ok = false;
6781 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6783 r = x86_decode_insn(ctxt, insn, insn_len);
6785 trace_kvm_emulate_insn_start(vcpu);
6786 ++vcpu->stat.insn_emulation;
6787 if (r != EMULATION_OK) {
6788 if ((emulation_type & EMULTYPE_TRAP_UD) ||
6789 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6790 kvm_queue_exception(vcpu, UD_VECTOR);
6793 if (reexecute_instruction(vcpu, cr2_or_gpa,
6797 if (ctxt->have_exception) {
6799 * #UD should result in just EMULATION_FAILED, and trap-like
6800 * exception should not be encountered during decode.
6802 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6803 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6804 inject_emulated_exception(vcpu);
6807 return handle_emulation_failure(vcpu, emulation_type);
6811 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6812 !is_vmware_backdoor_opcode(ctxt)) {
6813 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6818 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6819 * for kvm_skip_emulated_instruction(). The caller is responsible for
6820 * updating interruptibility state and injecting single-step #DBs.
6822 if (emulation_type & EMULTYPE_SKIP) {
6823 kvm_rip_write(vcpu, ctxt->_eip);
6824 if (ctxt->eflags & X86_EFLAGS_RF)
6825 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6829 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6832 /* this is needed for vmware backdoor interface to work since it
6833 changes registers values during IO operation */
6834 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6835 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6836 emulator_invalidate_register_cache(ctxt);
6840 if (emulation_type & EMULTYPE_PF) {
6841 /* Save the faulting GPA (cr2) in the address field */
6842 ctxt->exception.address = cr2_or_gpa;
6844 /* With shadow page tables, cr2 contains a GVA or nGPA. */
6845 if (vcpu->arch.mmu->direct_map) {
6846 ctxt->gpa_available = true;
6847 ctxt->gpa_val = cr2_or_gpa;
6850 /* Sanitize the address out of an abundance of paranoia. */
6851 ctxt->exception.address = 0;
6854 r = x86_emulate_insn(ctxt);
6856 if (r == EMULATION_INTERCEPTED)
6859 if (r == EMULATION_FAILED) {
6860 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
6864 return handle_emulation_failure(vcpu, emulation_type);
6867 if (ctxt->have_exception) {
6869 if (inject_emulated_exception(vcpu))
6871 } else if (vcpu->arch.pio.count) {
6872 if (!vcpu->arch.pio.in) {
6873 /* FIXME: return into emulator if single-stepping. */
6874 vcpu->arch.pio.count = 0;
6877 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6880 } else if (vcpu->mmio_needed) {
6881 ++vcpu->stat.mmio_exits;
6883 if (!vcpu->mmio_is_write)
6886 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6887 } else if (r == EMULATION_RESTART)
6893 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6894 toggle_interruptibility(vcpu, ctxt->interruptibility);
6895 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6896 if (!ctxt->have_exception ||
6897 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6898 kvm_rip_write(vcpu, ctxt->eip);
6900 r = kvm_vcpu_do_singlestep(vcpu);
6901 if (kvm_x86_ops->update_emulated_instruction)
6902 kvm_x86_ops->update_emulated_instruction(vcpu);
6903 __kvm_set_rflags(vcpu, ctxt->eflags);
6907 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6908 * do nothing, and it will be requested again as soon as
6909 * the shadow expires. But we still need to check here,
6910 * because POPF has no interrupt shadow.
6912 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6913 kvm_make_request(KVM_REQ_EVENT, vcpu);
6915 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6920 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6922 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6924 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6926 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6927 void *insn, int insn_len)
6929 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6931 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6933 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6935 vcpu->arch.pio.count = 0;
6939 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6941 vcpu->arch.pio.count = 0;
6943 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6946 return kvm_skip_emulated_instruction(vcpu);
6949 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6950 unsigned short port)
6952 unsigned long val = kvm_rax_read(vcpu);
6953 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
6959 * Workaround userspace that relies on old KVM behavior of %rip being
6960 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6963 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6964 vcpu->arch.complete_userspace_io =
6965 complete_fast_pio_out_port_0x7e;
6966 kvm_skip_emulated_instruction(vcpu);
6968 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6969 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6974 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6978 /* We should only ever be called with arch.pio.count equal to 1 */
6979 BUG_ON(vcpu->arch.pio.count != 1);
6981 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6982 vcpu->arch.pio.count = 0;
6986 /* For size less than 4 we merge, else we zero extend */
6987 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6990 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
6991 * the copy and tracing
6993 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
6994 kvm_rax_write(vcpu, val);
6996 return kvm_skip_emulated_instruction(vcpu);
6999 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7000 unsigned short port)
7005 /* For size less than 4 we merge, else we zero extend */
7006 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7008 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7010 kvm_rax_write(vcpu, val);
7014 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7015 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7020 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7025 ret = kvm_fast_pio_in(vcpu, size, port);
7027 ret = kvm_fast_pio_out(vcpu, size, port);
7028 return ret && kvm_skip_emulated_instruction(vcpu);
7030 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7032 static int kvmclock_cpu_down_prep(unsigned int cpu)
7034 __this_cpu_write(cpu_tsc_khz, 0);
7038 static void tsc_khz_changed(void *data)
7040 struct cpufreq_freqs *freq = data;
7041 unsigned long khz = 0;
7045 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7046 khz = cpufreq_quick_get(raw_smp_processor_id());
7049 __this_cpu_write(cpu_tsc_khz, khz);
7052 #ifdef CONFIG_X86_64
7053 static void kvm_hyperv_tsc_notifier(void)
7056 struct kvm_vcpu *vcpu;
7059 mutex_lock(&kvm_lock);
7060 list_for_each_entry(kvm, &vm_list, vm_list)
7061 kvm_make_mclock_inprogress_request(kvm);
7063 hyperv_stop_tsc_emulation();
7065 /* TSC frequency always matches when on Hyper-V */
7066 for_each_present_cpu(cpu)
7067 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7068 kvm_max_guest_tsc_khz = tsc_khz;
7070 list_for_each_entry(kvm, &vm_list, vm_list) {
7071 struct kvm_arch *ka = &kvm->arch;
7073 spin_lock(&ka->pvclock_gtod_sync_lock);
7075 pvclock_update_vm_gtod_copy(kvm);
7077 kvm_for_each_vcpu(cpu, vcpu, kvm)
7078 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7080 kvm_for_each_vcpu(cpu, vcpu, kvm)
7081 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7083 spin_unlock(&ka->pvclock_gtod_sync_lock);
7085 mutex_unlock(&kvm_lock);
7089 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7092 struct kvm_vcpu *vcpu;
7093 int i, send_ipi = 0;
7096 * We allow guests to temporarily run on slowing clocks,
7097 * provided we notify them after, or to run on accelerating
7098 * clocks, provided we notify them before. Thus time never
7101 * However, we have a problem. We can't atomically update
7102 * the frequency of a given CPU from this function; it is
7103 * merely a notifier, which can be called from any CPU.
7104 * Changing the TSC frequency at arbitrary points in time
7105 * requires a recomputation of local variables related to
7106 * the TSC for each VCPU. We must flag these local variables
7107 * to be updated and be sure the update takes place with the
7108 * new frequency before any guests proceed.
7110 * Unfortunately, the combination of hotplug CPU and frequency
7111 * change creates an intractable locking scenario; the order
7112 * of when these callouts happen is undefined with respect to
7113 * CPU hotplug, and they can race with each other. As such,
7114 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7115 * undefined; you can actually have a CPU frequency change take
7116 * place in between the computation of X and the setting of the
7117 * variable. To protect against this problem, all updates of
7118 * the per_cpu tsc_khz variable are done in an interrupt
7119 * protected IPI, and all callers wishing to update the value
7120 * must wait for a synchronous IPI to complete (which is trivial
7121 * if the caller is on the CPU already). This establishes the
7122 * necessary total order on variable updates.
7124 * Note that because a guest time update may take place
7125 * anytime after the setting of the VCPU's request bit, the
7126 * correct TSC value must be set before the request. However,
7127 * to ensure the update actually makes it to any guest which
7128 * starts running in hardware virtualization between the set
7129 * and the acquisition of the spinlock, we must also ping the
7130 * CPU after setting the request bit.
7134 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7136 mutex_lock(&kvm_lock);
7137 list_for_each_entry(kvm, &vm_list, vm_list) {
7138 kvm_for_each_vcpu(i, vcpu, kvm) {
7139 if (vcpu->cpu != cpu)
7141 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7142 if (vcpu->cpu != raw_smp_processor_id())
7146 mutex_unlock(&kvm_lock);
7148 if (freq->old < freq->new && send_ipi) {
7150 * We upscale the frequency. Must make the guest
7151 * doesn't see old kvmclock values while running with
7152 * the new frequency, otherwise we risk the guest sees
7153 * time go backwards.
7155 * In case we update the frequency for another cpu
7156 * (which might be in guest context) send an interrupt
7157 * to kick the cpu out of guest context. Next time
7158 * guest context is entered kvmclock will be updated,
7159 * so the guest will not see stale values.
7161 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7165 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7168 struct cpufreq_freqs *freq = data;
7171 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7173 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7176 for_each_cpu(cpu, freq->policy->cpus)
7177 __kvmclock_cpufreq_notifier(freq, cpu);
7182 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7183 .notifier_call = kvmclock_cpufreq_notifier
7186 static int kvmclock_cpu_online(unsigned int cpu)
7188 tsc_khz_changed(NULL);
7192 static void kvm_timer_init(void)
7194 max_tsc_khz = tsc_khz;
7196 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7197 #ifdef CONFIG_CPU_FREQ
7198 struct cpufreq_policy *policy;
7202 policy = cpufreq_cpu_get(cpu);
7203 if (policy && policy->cpuinfo.max_freq)
7204 max_tsc_khz = policy->cpuinfo.max_freq;
7206 cpufreq_cpu_put(policy);
7208 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7209 CPUFREQ_TRANSITION_NOTIFIER);
7212 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7213 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7216 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7217 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7219 int kvm_is_in_guest(void)
7221 return __this_cpu_read(current_vcpu) != NULL;
7224 static int kvm_is_user_mode(void)
7228 if (__this_cpu_read(current_vcpu))
7229 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
7231 return user_mode != 0;
7234 static unsigned long kvm_get_guest_ip(void)
7236 unsigned long ip = 0;
7238 if (__this_cpu_read(current_vcpu))
7239 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7244 static void kvm_handle_intel_pt_intr(void)
7246 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7248 kvm_make_request(KVM_REQ_PMI, vcpu);
7249 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7250 (unsigned long *)&vcpu->arch.pmu.global_status);
7253 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7254 .is_in_guest = kvm_is_in_guest,
7255 .is_user_mode = kvm_is_user_mode,
7256 .get_guest_ip = kvm_get_guest_ip,
7257 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7260 #ifdef CONFIG_X86_64
7261 static void pvclock_gtod_update_fn(struct work_struct *work)
7265 struct kvm_vcpu *vcpu;
7268 mutex_lock(&kvm_lock);
7269 list_for_each_entry(kvm, &vm_list, vm_list)
7270 kvm_for_each_vcpu(i, vcpu, kvm)
7271 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7272 atomic_set(&kvm_guest_has_master_clock, 0);
7273 mutex_unlock(&kvm_lock);
7276 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7279 * Notification about pvclock gtod data update.
7281 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7284 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7285 struct timekeeper *tk = priv;
7287 update_pvclock_gtod(tk);
7289 /* disable master clock if host does not trust, or does not
7290 * use, TSC based clocksource.
7292 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7293 atomic_read(&kvm_guest_has_master_clock) != 0)
7294 queue_work(system_long_wq, &pvclock_gtod_work);
7299 static struct notifier_block pvclock_gtod_notifier = {
7300 .notifier_call = pvclock_gtod_notify,
7304 int kvm_arch_init(void *opaque)
7307 struct kvm_x86_ops *ops = opaque;
7310 printk(KERN_ERR "kvm: already loaded the other module\n");
7315 if (!ops->cpu_has_kvm_support()) {
7316 pr_err_ratelimited("kvm: no hardware support\n");
7320 if (ops->disabled_by_bios()) {
7321 pr_err_ratelimited("kvm: disabled by bios\n");
7327 * KVM explicitly assumes that the guest has an FPU and
7328 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7329 * vCPU's FPU state as a fxregs_state struct.
7331 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7332 printk(KERN_ERR "kvm: inadequate fpu\n");
7338 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7339 __alignof__(struct fpu), SLAB_ACCOUNT,
7341 if (!x86_fpu_cache) {
7342 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7346 x86_emulator_cache = kvm_alloc_emulator_cache();
7347 if (!x86_emulator_cache) {
7348 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7349 goto out_free_x86_fpu_cache;
7352 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7354 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7355 goto out_free_x86_emulator_cache;
7358 r = kvm_mmu_module_init();
7360 goto out_free_percpu;
7364 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7365 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7366 PT_PRESENT_MASK, 0, sme_me_mask);
7369 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7371 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7372 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7373 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7377 if (pi_inject_timer == -1)
7378 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7379 #ifdef CONFIG_X86_64
7380 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7382 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7383 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7389 free_percpu(shared_msrs);
7390 out_free_x86_emulator_cache:
7391 kmem_cache_destroy(x86_emulator_cache);
7392 out_free_x86_fpu_cache:
7393 kmem_cache_destroy(x86_fpu_cache);
7398 void kvm_arch_exit(void)
7400 #ifdef CONFIG_X86_64
7401 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7402 clear_hv_tscchange_cb();
7405 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7407 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7408 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7409 CPUFREQ_TRANSITION_NOTIFIER);
7410 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7411 #ifdef CONFIG_X86_64
7412 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7415 kvm_mmu_module_exit();
7416 free_percpu(shared_msrs);
7417 kmem_cache_destroy(x86_fpu_cache);
7420 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7422 ++vcpu->stat.halt_exits;
7423 if (lapic_in_kernel(vcpu)) {
7424 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7427 vcpu->run->exit_reason = KVM_EXIT_HLT;
7431 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7433 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7435 int ret = kvm_skip_emulated_instruction(vcpu);
7437 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7438 * KVM_EXIT_DEBUG here.
7440 return kvm_vcpu_halt(vcpu) && ret;
7442 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7444 #ifdef CONFIG_X86_64
7445 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7446 unsigned long clock_type)
7448 struct kvm_clock_pairing clock_pairing;
7449 struct timespec64 ts;
7453 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7454 return -KVM_EOPNOTSUPP;
7456 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7457 return -KVM_EOPNOTSUPP;
7459 clock_pairing.sec = ts.tv_sec;
7460 clock_pairing.nsec = ts.tv_nsec;
7461 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7462 clock_pairing.flags = 0;
7463 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7466 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7467 sizeof(struct kvm_clock_pairing)))
7475 * kvm_pv_kick_cpu_op: Kick a vcpu.
7477 * @apicid - apicid of vcpu to be kicked.
7479 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7481 struct kvm_lapic_irq lapic_irq;
7483 lapic_irq.shorthand = APIC_DEST_NOSHORT;
7484 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7485 lapic_irq.level = 0;
7486 lapic_irq.dest_id = apicid;
7487 lapic_irq.msi_redir_hint = false;
7489 lapic_irq.delivery_mode = APIC_DM_REMRD;
7490 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7493 bool kvm_apicv_activated(struct kvm *kvm)
7495 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7497 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7499 void kvm_apicv_init(struct kvm *kvm, bool enable)
7502 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7503 &kvm->arch.apicv_inhibit_reasons);
7505 set_bit(APICV_INHIBIT_REASON_DISABLE,
7506 &kvm->arch.apicv_inhibit_reasons);
7508 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7510 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7512 struct kvm_vcpu *target = NULL;
7513 struct kvm_apic_map *map;
7516 map = rcu_dereference(kvm->arch.apic_map);
7518 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7519 target = map->phys_map[dest_id]->vcpu;
7523 if (target && READ_ONCE(target->ready))
7524 kvm_vcpu_yield_to(target);
7527 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7529 unsigned long nr, a0, a1, a2, a3, ret;
7532 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7533 return kvm_hv_hypercall(vcpu);
7535 nr = kvm_rax_read(vcpu);
7536 a0 = kvm_rbx_read(vcpu);
7537 a1 = kvm_rcx_read(vcpu);
7538 a2 = kvm_rdx_read(vcpu);
7539 a3 = kvm_rsi_read(vcpu);
7541 trace_kvm_hypercall(nr, a0, a1, a2, a3);
7543 op_64_bit = is_64_bit_mode(vcpu);
7552 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7558 case KVM_HC_VAPIC_POLL_IRQ:
7561 case KVM_HC_KICK_CPU:
7562 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7563 kvm_sched_yield(vcpu->kvm, a1);
7566 #ifdef CONFIG_X86_64
7567 case KVM_HC_CLOCK_PAIRING:
7568 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7571 case KVM_HC_SEND_IPI:
7572 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7574 case KVM_HC_SCHED_YIELD:
7575 kvm_sched_yield(vcpu->kvm, a0);
7585 kvm_rax_write(vcpu, ret);
7587 ++vcpu->stat.hypercalls;
7588 return kvm_skip_emulated_instruction(vcpu);
7590 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7592 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7594 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7595 char instruction[3];
7596 unsigned long rip = kvm_rip_read(vcpu);
7598 kvm_x86_ops->patch_hypercall(vcpu, instruction);
7600 return emulator_write_emulated(ctxt, rip, instruction, 3,
7604 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7606 return vcpu->run->request_interrupt_window &&
7607 likely(!pic_in_kernel(vcpu->kvm));
7610 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7612 struct kvm_run *kvm_run = vcpu->run;
7614 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7615 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7616 kvm_run->cr8 = kvm_get_cr8(vcpu);
7617 kvm_run->apic_base = kvm_get_apic_base(vcpu);
7618 kvm_run->ready_for_interrupt_injection =
7619 pic_in_kernel(vcpu->kvm) ||
7620 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7623 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7627 if (!kvm_x86_ops->update_cr8_intercept)
7630 if (!lapic_in_kernel(vcpu))
7633 if (vcpu->arch.apicv_active)
7636 if (!vcpu->arch.apic->vapic_addr)
7637 max_irr = kvm_lapic_find_highest_irr(vcpu);
7644 tpr = kvm_lapic_get_cr8(vcpu);
7646 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7649 static int inject_pending_event(struct kvm_vcpu *vcpu)
7653 /* try to reinject previous events if any */
7655 if (vcpu->arch.exception.injected)
7656 kvm_x86_ops->queue_exception(vcpu);
7658 * Do not inject an NMI or interrupt if there is a pending
7659 * exception. Exceptions and interrupts are recognized at
7660 * instruction boundaries, i.e. the start of an instruction.
7661 * Trap-like exceptions, e.g. #DB, have higher priority than
7662 * NMIs and interrupts, i.e. traps are recognized before an
7663 * NMI/interrupt that's pending on the same instruction.
7664 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7665 * priority, but are only generated (pended) during instruction
7666 * execution, i.e. a pending fault-like exception means the
7667 * fault occurred on the *previous* instruction and must be
7668 * serviced prior to recognizing any new events in order to
7669 * fully complete the previous instruction.
7671 else if (!vcpu->arch.exception.pending) {
7672 if (vcpu->arch.nmi_injected)
7673 kvm_x86_ops->set_nmi(vcpu);
7674 else if (vcpu->arch.interrupt.injected)
7675 kvm_x86_ops->set_irq(vcpu);
7679 * Call check_nested_events() even if we reinjected a previous event
7680 * in order for caller to determine if it should require immediate-exit
7681 * from L2 to L1 due to pending L1 events which require exit
7684 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7685 r = kvm_x86_ops->check_nested_events(vcpu);
7690 /* try to inject new event if pending */
7691 if (vcpu->arch.exception.pending) {
7692 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7693 vcpu->arch.exception.has_error_code,
7694 vcpu->arch.exception.error_code);
7696 WARN_ON_ONCE(vcpu->arch.exception.injected);
7697 vcpu->arch.exception.pending = false;
7698 vcpu->arch.exception.injected = true;
7700 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7701 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7704 if (vcpu->arch.exception.nr == DB_VECTOR) {
7706 * This code assumes that nSVM doesn't use
7707 * check_nested_events(). If it does, the
7708 * DR6/DR7 changes should happen before L1
7709 * gets a #VMEXIT for an intercepted #DB in
7710 * L2. (Under VMX, on the other hand, the
7711 * DR6/DR7 changes should not happen in the
7712 * event of a VM-exit to L1 for an intercepted
7715 kvm_deliver_exception_payload(vcpu);
7716 if (vcpu->arch.dr7 & DR7_GD) {
7717 vcpu->arch.dr7 &= ~DR7_GD;
7718 kvm_update_dr7(vcpu);
7722 kvm_x86_ops->queue_exception(vcpu);
7725 /* Don't consider new event if we re-injected an event */
7726 if (kvm_event_needs_reinjection(vcpu))
7729 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7730 kvm_x86_ops->smi_allowed(vcpu)) {
7731 vcpu->arch.smi_pending = false;
7732 ++vcpu->arch.smi_count;
7734 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
7735 --vcpu->arch.nmi_pending;
7736 vcpu->arch.nmi_injected = true;
7737 kvm_x86_ops->set_nmi(vcpu);
7738 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7740 * Because interrupts can be injected asynchronously, we are
7741 * calling check_nested_events again here to avoid a race condition.
7742 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7743 * proposal and current concerns. Perhaps we should be setting
7744 * KVM_REQ_EVENT only on certain events and not unconditionally?
7746 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7747 r = kvm_x86_ops->check_nested_events(vcpu);
7751 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
7752 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7754 kvm_x86_ops->set_irq(vcpu);
7761 static void process_nmi(struct kvm_vcpu *vcpu)
7766 * x86 is limited to one NMI running, and one NMI pending after it.
7767 * If an NMI is already in progress, limit further NMIs to just one.
7768 * Otherwise, allow two (and we'll inject the first one immediately).
7770 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7773 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7774 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7775 kvm_make_request(KVM_REQ_EVENT, vcpu);
7778 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7781 flags |= seg->g << 23;
7782 flags |= seg->db << 22;
7783 flags |= seg->l << 21;
7784 flags |= seg->avl << 20;
7785 flags |= seg->present << 15;
7786 flags |= seg->dpl << 13;
7787 flags |= seg->s << 12;
7788 flags |= seg->type << 8;
7792 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7794 struct kvm_segment seg;
7797 kvm_get_segment(vcpu, &seg, n);
7798 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7801 offset = 0x7f84 + n * 12;
7803 offset = 0x7f2c + (n - 3) * 12;
7805 put_smstate(u32, buf, offset + 8, seg.base);
7806 put_smstate(u32, buf, offset + 4, seg.limit);
7807 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7810 #ifdef CONFIG_X86_64
7811 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7813 struct kvm_segment seg;
7817 kvm_get_segment(vcpu, &seg, n);
7818 offset = 0x7e00 + n * 16;
7820 flags = enter_smm_get_segment_flags(&seg) >> 8;
7821 put_smstate(u16, buf, offset, seg.selector);
7822 put_smstate(u16, buf, offset + 2, flags);
7823 put_smstate(u32, buf, offset + 4, seg.limit);
7824 put_smstate(u64, buf, offset + 8, seg.base);
7828 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7831 struct kvm_segment seg;
7835 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7836 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7837 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7838 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7840 for (i = 0; i < 8; i++)
7841 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7843 kvm_get_dr(vcpu, 6, &val);
7844 put_smstate(u32, buf, 0x7fcc, (u32)val);
7845 kvm_get_dr(vcpu, 7, &val);
7846 put_smstate(u32, buf, 0x7fc8, (u32)val);
7848 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7849 put_smstate(u32, buf, 0x7fc4, seg.selector);
7850 put_smstate(u32, buf, 0x7f64, seg.base);
7851 put_smstate(u32, buf, 0x7f60, seg.limit);
7852 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7854 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7855 put_smstate(u32, buf, 0x7fc0, seg.selector);
7856 put_smstate(u32, buf, 0x7f80, seg.base);
7857 put_smstate(u32, buf, 0x7f7c, seg.limit);
7858 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7860 kvm_x86_ops->get_gdt(vcpu, &dt);
7861 put_smstate(u32, buf, 0x7f74, dt.address);
7862 put_smstate(u32, buf, 0x7f70, dt.size);
7864 kvm_x86_ops->get_idt(vcpu, &dt);
7865 put_smstate(u32, buf, 0x7f58, dt.address);
7866 put_smstate(u32, buf, 0x7f54, dt.size);
7868 for (i = 0; i < 6; i++)
7869 enter_smm_save_seg_32(vcpu, buf, i);
7871 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7874 put_smstate(u32, buf, 0x7efc, 0x00020000);
7875 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7878 #ifdef CONFIG_X86_64
7879 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7882 struct kvm_segment seg;
7886 for (i = 0; i < 16; i++)
7887 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7889 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7890 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7892 kvm_get_dr(vcpu, 6, &val);
7893 put_smstate(u64, buf, 0x7f68, val);
7894 kvm_get_dr(vcpu, 7, &val);
7895 put_smstate(u64, buf, 0x7f60, val);
7897 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7898 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7899 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7901 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7904 put_smstate(u32, buf, 0x7efc, 0x00020064);
7906 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7908 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7909 put_smstate(u16, buf, 0x7e90, seg.selector);
7910 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7911 put_smstate(u32, buf, 0x7e94, seg.limit);
7912 put_smstate(u64, buf, 0x7e98, seg.base);
7914 kvm_x86_ops->get_idt(vcpu, &dt);
7915 put_smstate(u32, buf, 0x7e84, dt.size);
7916 put_smstate(u64, buf, 0x7e88, dt.address);
7918 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7919 put_smstate(u16, buf, 0x7e70, seg.selector);
7920 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7921 put_smstate(u32, buf, 0x7e74, seg.limit);
7922 put_smstate(u64, buf, 0x7e78, seg.base);
7924 kvm_x86_ops->get_gdt(vcpu, &dt);
7925 put_smstate(u32, buf, 0x7e64, dt.size);
7926 put_smstate(u64, buf, 0x7e68, dt.address);
7928 for (i = 0; i < 6; i++)
7929 enter_smm_save_seg_64(vcpu, buf, i);
7933 static void enter_smm(struct kvm_vcpu *vcpu)
7935 struct kvm_segment cs, ds;
7940 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7941 memset(buf, 0, 512);
7942 #ifdef CONFIG_X86_64
7943 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7944 enter_smm_save_state_64(vcpu, buf);
7947 enter_smm_save_state_32(vcpu, buf);
7950 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7951 * vCPU state (e.g. leave guest mode) after we've saved the state into
7952 * the SMM state-save area.
7954 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7956 vcpu->arch.hflags |= HF_SMM_MASK;
7957 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7959 if (kvm_x86_ops->get_nmi_mask(vcpu))
7960 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7962 kvm_x86_ops->set_nmi_mask(vcpu, true);
7964 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7965 kvm_rip_write(vcpu, 0x8000);
7967 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7968 kvm_x86_ops->set_cr0(vcpu, cr0);
7969 vcpu->arch.cr0 = cr0;
7971 kvm_x86_ops->set_cr4(vcpu, 0);
7973 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7974 dt.address = dt.size = 0;
7975 kvm_x86_ops->set_idt(vcpu, &dt);
7977 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7979 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7980 cs.base = vcpu->arch.smbase;
7985 cs.limit = ds.limit = 0xffffffff;
7986 cs.type = ds.type = 0x3;
7987 cs.dpl = ds.dpl = 0;
7992 cs.avl = ds.avl = 0;
7993 cs.present = ds.present = 1;
7994 cs.unusable = ds.unusable = 0;
7995 cs.padding = ds.padding = 0;
7997 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7998 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7999 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8000 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8001 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8002 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8004 #ifdef CONFIG_X86_64
8005 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8006 kvm_x86_ops->set_efer(vcpu, 0);
8009 kvm_update_cpuid(vcpu);
8010 kvm_mmu_reset_context(vcpu);
8013 static void process_smi(struct kvm_vcpu *vcpu)
8015 vcpu->arch.smi_pending = true;
8016 kvm_make_request(KVM_REQ_EVENT, vcpu);
8019 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8020 unsigned long *vcpu_bitmap)
8024 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8026 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8029 free_cpumask_var(cpus);
8032 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8034 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8037 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8039 if (!lapic_in_kernel(vcpu))
8042 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8043 kvm_apic_update_apicv(vcpu);
8044 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
8046 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8049 * NOTE: Do not hold any lock prior to calling this.
8051 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8052 * locked, because it calls __x86_set_memory_region() which does
8053 * synchronize_srcu(&kvm->srcu).
8055 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8057 unsigned long old, new, expected;
8059 if (!kvm_x86_ops->check_apicv_inhibit_reasons ||
8060 !kvm_x86_ops->check_apicv_inhibit_reasons(bit))
8063 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8065 expected = new = old;
8067 __clear_bit(bit, &new);
8069 __set_bit(bit, &new);
8072 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8073 } while (old != expected);
8078 trace_kvm_apicv_update_request(activate, bit);
8079 if (kvm_x86_ops->pre_update_apicv_exec_ctrl)
8080 kvm_x86_ops->pre_update_apicv_exec_ctrl(kvm, activate);
8081 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
8083 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8085 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8087 if (!kvm_apic_present(vcpu))
8090 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8092 if (irqchip_split(vcpu->kvm))
8093 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8095 if (vcpu->arch.apicv_active)
8096 kvm_x86_ops->sync_pir_to_irr(vcpu);
8097 if (ioapic_in_kernel(vcpu->kvm))
8098 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8101 if (is_guest_mode(vcpu))
8102 vcpu->arch.load_eoi_exitmap_pending = true;
8104 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8107 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8109 u64 eoi_exit_bitmap[4];
8111 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8114 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8115 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8116 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8119 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8120 unsigned long start, unsigned long end,
8123 unsigned long apic_address;
8126 * The physical address of apic access page is stored in the VMCS.
8127 * Update it when it becomes invalid.
8129 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8130 if (start <= apic_address && apic_address < end)
8131 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8136 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8138 struct page *page = NULL;
8140 if (!lapic_in_kernel(vcpu))
8143 if (!kvm_x86_ops->set_apic_access_page_addr)
8146 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8147 if (is_error_page(page))
8149 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
8152 * Do not pin apic access page in memory, the MMU notifier
8153 * will call us again if it is migrated or swapped out.
8158 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8160 smp_send_reschedule(vcpu->cpu);
8162 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8165 * Returns 1 to let vcpu_run() continue the guest execution loop without
8166 * exiting to the userspace. Otherwise, the value will be returned to the
8169 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8173 dm_request_for_irq_injection(vcpu) &&
8174 kvm_cpu_accept_dm_intr(vcpu);
8175 enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE;
8177 bool req_immediate_exit = false;
8179 if (kvm_request_pending(vcpu)) {
8180 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8181 if (unlikely(!kvm_x86_ops->get_vmcs12_pages(vcpu))) {
8186 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8187 kvm_mmu_unload(vcpu);
8188 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8189 __kvm_migrate_timers(vcpu);
8190 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8191 kvm_gen_update_masterclock(vcpu->kvm);
8192 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8193 kvm_gen_kvmclock_update(vcpu);
8194 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8195 r = kvm_guest_time_update(vcpu);
8199 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8200 kvm_mmu_sync_roots(vcpu);
8201 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8202 kvm_mmu_load_pgd(vcpu);
8203 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
8204 kvm_vcpu_flush_tlb(vcpu, true);
8205 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8206 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8210 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8211 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8212 vcpu->mmio_needed = 0;
8216 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8217 /* Page is swapped out. Do synthetic halt */
8218 vcpu->arch.apf.halted = true;
8222 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8223 record_steal_time(vcpu);
8224 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8226 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8228 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8229 kvm_pmu_handle_event(vcpu);
8230 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8231 kvm_pmu_deliver_pmi(vcpu);
8232 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8233 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8234 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8235 vcpu->arch.ioapic_handled_vectors)) {
8236 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8237 vcpu->run->eoi.vector =
8238 vcpu->arch.pending_ioapic_eoi;
8243 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8244 vcpu_scan_ioapic(vcpu);
8245 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8246 vcpu_load_eoi_exitmap(vcpu);
8247 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8248 kvm_vcpu_reload_apic_access_page(vcpu);
8249 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8250 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8251 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8255 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8256 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8257 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8261 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8262 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8263 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8269 * KVM_REQ_HV_STIMER has to be processed after
8270 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8271 * depend on the guest clock being up-to-date
8273 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8274 kvm_hv_process_stimers(vcpu);
8275 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8276 kvm_vcpu_update_apicv(vcpu);
8279 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8280 ++vcpu->stat.req_event;
8281 kvm_apic_accept_events(vcpu);
8282 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8287 if (inject_pending_event(vcpu) != 0)
8288 req_immediate_exit = true;
8290 /* Enable SMI/NMI/IRQ window open exits if needed.
8292 * SMIs have three cases:
8293 * 1) They can be nested, and then there is nothing to
8294 * do here because RSM will cause a vmexit anyway.
8295 * 2) There is an ISA-specific reason why SMI cannot be
8296 * injected, and the moment when this changes can be
8298 * 3) Or the SMI can be pending because
8299 * inject_pending_event has completed the injection
8300 * of an IRQ or NMI from the previous vmexit, and
8301 * then we request an immediate exit to inject the
8304 if (vcpu->arch.smi_pending && !is_smm(vcpu))
8305 if (!kvm_x86_ops->enable_smi_window(vcpu))
8306 req_immediate_exit = true;
8307 if (vcpu->arch.nmi_pending)
8308 kvm_x86_ops->enable_nmi_window(vcpu);
8309 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8310 kvm_x86_ops->enable_irq_window(vcpu);
8311 WARN_ON(vcpu->arch.exception.pending);
8314 if (kvm_lapic_enabled(vcpu)) {
8315 update_cr8_intercept(vcpu);
8316 kvm_lapic_sync_to_vapic(vcpu);
8320 r = kvm_mmu_reload(vcpu);
8322 goto cancel_injection;
8327 kvm_x86_ops->prepare_guest_switch(vcpu);
8330 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8331 * IPI are then delayed after guest entry, which ensures that they
8332 * result in virtual interrupt delivery.
8334 local_irq_disable();
8335 vcpu->mode = IN_GUEST_MODE;
8337 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8340 * 1) We should set ->mode before checking ->requests. Please see
8341 * the comment in kvm_vcpu_exiting_guest_mode().
8343 * 2) For APICv, we should set ->mode before checking PID.ON. This
8344 * pairs with the memory barrier implicit in pi_test_and_set_on
8345 * (see vmx_deliver_posted_interrupt).
8347 * 3) This also orders the write to mode from any reads to the page
8348 * tables done while the VCPU is running. Please see the comment
8349 * in kvm_flush_remote_tlbs.
8351 smp_mb__after_srcu_read_unlock();
8354 * This handles the case where a posted interrupt was
8355 * notified with kvm_vcpu_kick.
8357 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8358 kvm_x86_ops->sync_pir_to_irr(vcpu);
8360 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8361 || need_resched() || signal_pending(current)) {
8362 vcpu->mode = OUTSIDE_GUEST_MODE;
8366 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8368 goto cancel_injection;
8371 if (req_immediate_exit) {
8372 kvm_make_request(KVM_REQ_EVENT, vcpu);
8373 kvm_x86_ops->request_immediate_exit(vcpu);
8376 trace_kvm_entry(vcpu->vcpu_id);
8377 guest_enter_irqoff();
8379 fpregs_assert_state_consistent();
8380 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8381 switch_fpu_return();
8383 if (unlikely(vcpu->arch.switch_db_regs)) {
8385 set_debugreg(vcpu->arch.eff_db[0], 0);
8386 set_debugreg(vcpu->arch.eff_db[1], 1);
8387 set_debugreg(vcpu->arch.eff_db[2], 2);
8388 set_debugreg(vcpu->arch.eff_db[3], 3);
8389 set_debugreg(vcpu->arch.dr6, 6);
8390 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8393 kvm_x86_ops->run(vcpu);
8396 * Do this here before restoring debug registers on the host. And
8397 * since we do this before handling the vmexit, a DR access vmexit
8398 * can (a) read the correct value of the debug registers, (b) set
8399 * KVM_DEBUGREG_WONT_EXIT again.
8401 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8402 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8403 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
8404 kvm_update_dr0123(vcpu);
8405 kvm_update_dr6(vcpu);
8406 kvm_update_dr7(vcpu);
8407 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8411 * If the guest has used debug registers, at least dr7
8412 * will be disabled while returning to the host.
8413 * If we don't have active breakpoints in the host, we don't
8414 * care about the messed up debug address registers. But if
8415 * we have some of them active, restore the old state.
8417 if (hw_breakpoint_active())
8418 hw_breakpoint_restore();
8420 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8422 vcpu->mode = OUTSIDE_GUEST_MODE;
8425 kvm_x86_ops->handle_exit_irqoff(vcpu, &exit_fastpath);
8428 * Consume any pending interrupts, including the possible source of
8429 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8430 * An instruction is required after local_irq_enable() to fully unblock
8431 * interrupts on processors that implement an interrupt shadow, the
8432 * stat.exits increment will do nicely.
8434 kvm_before_interrupt(vcpu);
8437 local_irq_disable();
8438 kvm_after_interrupt(vcpu);
8440 guest_exit_irqoff();
8441 if (lapic_in_kernel(vcpu)) {
8442 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8443 if (delta != S64_MIN) {
8444 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8445 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8452 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8455 * Profile KVM exit RIPs:
8457 if (unlikely(prof_on == KVM_PROFILING)) {
8458 unsigned long rip = kvm_rip_read(vcpu);
8459 profile_hit(KVM_PROFILING, (void *)rip);
8462 if (unlikely(vcpu->arch.tsc_always_catchup))
8463 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8465 if (vcpu->arch.apic_attention)
8466 kvm_lapic_sync_from_vapic(vcpu);
8468 r = kvm_x86_ops->handle_exit(vcpu, exit_fastpath);
8472 kvm_x86_ops->cancel_injection(vcpu);
8473 if (unlikely(vcpu->arch.apic_attention))
8474 kvm_lapic_sync_from_vapic(vcpu);
8479 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8481 if (!kvm_arch_vcpu_runnable(vcpu) &&
8482 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
8483 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8484 kvm_vcpu_block(vcpu);
8485 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8487 if (kvm_x86_ops->post_block)
8488 kvm_x86_ops->post_block(vcpu);
8490 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8494 kvm_apic_accept_events(vcpu);
8495 switch(vcpu->arch.mp_state) {
8496 case KVM_MP_STATE_HALTED:
8497 vcpu->arch.pv.pv_unhalted = false;
8498 vcpu->arch.mp_state =
8499 KVM_MP_STATE_RUNNABLE;
8501 case KVM_MP_STATE_RUNNABLE:
8502 vcpu->arch.apf.halted = false;
8504 case KVM_MP_STATE_INIT_RECEIVED:
8512 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8514 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8515 kvm_x86_ops->check_nested_events(vcpu);
8517 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8518 !vcpu->arch.apf.halted);
8521 static int vcpu_run(struct kvm_vcpu *vcpu)
8524 struct kvm *kvm = vcpu->kvm;
8526 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8527 vcpu->arch.l1tf_flush_l1d = true;
8530 if (kvm_vcpu_running(vcpu)) {
8531 r = vcpu_enter_guest(vcpu);
8533 r = vcpu_block(kvm, vcpu);
8539 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8540 if (kvm_cpu_has_pending_timer(vcpu))
8541 kvm_inject_pending_timer_irqs(vcpu);
8543 if (dm_request_for_irq_injection(vcpu) &&
8544 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8546 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8547 ++vcpu->stat.request_irq_exits;
8551 kvm_check_async_pf_completion(vcpu);
8553 if (signal_pending(current)) {
8555 vcpu->run->exit_reason = KVM_EXIT_INTR;
8556 ++vcpu->stat.signal_exits;
8559 if (need_resched()) {
8560 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8562 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8566 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8571 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8575 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8576 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8577 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8581 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8583 BUG_ON(!vcpu->arch.pio.count);
8585 return complete_emulated_io(vcpu);
8589 * Implements the following, as a state machine:
8593 * for each mmio piece in the fragment
8601 * for each mmio piece in the fragment
8606 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8608 struct kvm_run *run = vcpu->run;
8609 struct kvm_mmio_fragment *frag;
8612 BUG_ON(!vcpu->mmio_needed);
8614 /* Complete previous fragment */
8615 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8616 len = min(8u, frag->len);
8617 if (!vcpu->mmio_is_write)
8618 memcpy(frag->data, run->mmio.data, len);
8620 if (frag->len <= 8) {
8621 /* Switch to the next fragment. */
8623 vcpu->mmio_cur_fragment++;
8625 /* Go forward to the next mmio piece. */
8631 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8632 vcpu->mmio_needed = 0;
8634 /* FIXME: return into emulator if single-stepping. */
8635 if (vcpu->mmio_is_write)
8637 vcpu->mmio_read_completed = 1;
8638 return complete_emulated_io(vcpu);
8641 run->exit_reason = KVM_EXIT_MMIO;
8642 run->mmio.phys_addr = frag->gpa;
8643 if (vcpu->mmio_is_write)
8644 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8645 run->mmio.len = min(8u, frag->len);
8646 run->mmio.is_write = vcpu->mmio_is_write;
8647 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8651 static void kvm_save_current_fpu(struct fpu *fpu)
8654 * If the target FPU state is not resident in the CPU registers, just
8655 * memcpy() from current, else save CPU state directly to the target.
8657 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8658 memcpy(&fpu->state, ¤t->thread.fpu.state,
8659 fpu_kernel_xstate_size);
8661 copy_fpregs_to_fpstate(fpu);
8664 /* Swap (qemu) user FPU context for the guest FPU context. */
8665 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8669 kvm_save_current_fpu(vcpu->arch.user_fpu);
8671 /* PKRU is separately restored in kvm_x86_ops->run. */
8672 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8673 ~XFEATURE_MASK_PKRU);
8675 fpregs_mark_activate();
8681 /* When vcpu_run ends, restore user space FPU context. */
8682 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8686 kvm_save_current_fpu(vcpu->arch.guest_fpu);
8688 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8690 fpregs_mark_activate();
8693 ++vcpu->stat.fpu_reload;
8697 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8702 kvm_sigset_activate(vcpu);
8703 kvm_load_guest_fpu(vcpu);
8705 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8706 if (kvm_run->immediate_exit) {
8710 kvm_vcpu_block(vcpu);
8711 kvm_apic_accept_events(vcpu);
8712 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8714 if (signal_pending(current)) {
8716 vcpu->run->exit_reason = KVM_EXIT_INTR;
8717 ++vcpu->stat.signal_exits;
8722 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8727 if (vcpu->run->kvm_dirty_regs) {
8728 r = sync_regs(vcpu);
8733 /* re-sync apic's tpr */
8734 if (!lapic_in_kernel(vcpu)) {
8735 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8741 if (unlikely(vcpu->arch.complete_userspace_io)) {
8742 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8743 vcpu->arch.complete_userspace_io = NULL;
8748 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8750 if (kvm_run->immediate_exit)
8756 kvm_put_guest_fpu(vcpu);
8757 if (vcpu->run->kvm_valid_regs)
8759 post_kvm_run_save(vcpu);
8760 kvm_sigset_deactivate(vcpu);
8766 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8768 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8770 * We are here if userspace calls get_regs() in the middle of
8771 * instruction emulation. Registers state needs to be copied
8772 * back from emulation context to vcpu. Userspace shouldn't do
8773 * that usually, but some bad designed PV devices (vmware
8774 * backdoor interface) need this to work
8776 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
8777 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8779 regs->rax = kvm_rax_read(vcpu);
8780 regs->rbx = kvm_rbx_read(vcpu);
8781 regs->rcx = kvm_rcx_read(vcpu);
8782 regs->rdx = kvm_rdx_read(vcpu);
8783 regs->rsi = kvm_rsi_read(vcpu);
8784 regs->rdi = kvm_rdi_read(vcpu);
8785 regs->rsp = kvm_rsp_read(vcpu);
8786 regs->rbp = kvm_rbp_read(vcpu);
8787 #ifdef CONFIG_X86_64
8788 regs->r8 = kvm_r8_read(vcpu);
8789 regs->r9 = kvm_r9_read(vcpu);
8790 regs->r10 = kvm_r10_read(vcpu);
8791 regs->r11 = kvm_r11_read(vcpu);
8792 regs->r12 = kvm_r12_read(vcpu);
8793 regs->r13 = kvm_r13_read(vcpu);
8794 regs->r14 = kvm_r14_read(vcpu);
8795 regs->r15 = kvm_r15_read(vcpu);
8798 regs->rip = kvm_rip_read(vcpu);
8799 regs->rflags = kvm_get_rflags(vcpu);
8802 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8805 __get_regs(vcpu, regs);
8810 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8812 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8813 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8815 kvm_rax_write(vcpu, regs->rax);
8816 kvm_rbx_write(vcpu, regs->rbx);
8817 kvm_rcx_write(vcpu, regs->rcx);
8818 kvm_rdx_write(vcpu, regs->rdx);
8819 kvm_rsi_write(vcpu, regs->rsi);
8820 kvm_rdi_write(vcpu, regs->rdi);
8821 kvm_rsp_write(vcpu, regs->rsp);
8822 kvm_rbp_write(vcpu, regs->rbp);
8823 #ifdef CONFIG_X86_64
8824 kvm_r8_write(vcpu, regs->r8);
8825 kvm_r9_write(vcpu, regs->r9);
8826 kvm_r10_write(vcpu, regs->r10);
8827 kvm_r11_write(vcpu, regs->r11);
8828 kvm_r12_write(vcpu, regs->r12);
8829 kvm_r13_write(vcpu, regs->r13);
8830 kvm_r14_write(vcpu, regs->r14);
8831 kvm_r15_write(vcpu, regs->r15);
8834 kvm_rip_write(vcpu, regs->rip);
8835 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8837 vcpu->arch.exception.pending = false;
8839 kvm_make_request(KVM_REQ_EVENT, vcpu);
8842 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8845 __set_regs(vcpu, regs);
8850 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8852 struct kvm_segment cs;
8854 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8858 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8860 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8864 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8865 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8866 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8867 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8868 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8869 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8871 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8872 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8874 kvm_x86_ops->get_idt(vcpu, &dt);
8875 sregs->idt.limit = dt.size;
8876 sregs->idt.base = dt.address;
8877 kvm_x86_ops->get_gdt(vcpu, &dt);
8878 sregs->gdt.limit = dt.size;
8879 sregs->gdt.base = dt.address;
8881 sregs->cr0 = kvm_read_cr0(vcpu);
8882 sregs->cr2 = vcpu->arch.cr2;
8883 sregs->cr3 = kvm_read_cr3(vcpu);
8884 sregs->cr4 = kvm_read_cr4(vcpu);
8885 sregs->cr8 = kvm_get_cr8(vcpu);
8886 sregs->efer = vcpu->arch.efer;
8887 sregs->apic_base = kvm_get_apic_base(vcpu);
8889 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8891 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8892 set_bit(vcpu->arch.interrupt.nr,
8893 (unsigned long *)sregs->interrupt_bitmap);
8896 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8897 struct kvm_sregs *sregs)
8900 __get_sregs(vcpu, sregs);
8905 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8906 struct kvm_mp_state *mp_state)
8909 if (kvm_mpx_supported())
8910 kvm_load_guest_fpu(vcpu);
8912 kvm_apic_accept_events(vcpu);
8913 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8914 vcpu->arch.pv.pv_unhalted)
8915 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8917 mp_state->mp_state = vcpu->arch.mp_state;
8919 if (kvm_mpx_supported())
8920 kvm_put_guest_fpu(vcpu);
8925 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8926 struct kvm_mp_state *mp_state)
8932 if (!lapic_in_kernel(vcpu) &&
8933 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8937 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8938 * INIT state; latched init should be reported using
8939 * KVM_SET_VCPU_EVENTS, so reject it here.
8941 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
8942 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8943 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8946 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8947 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8948 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8950 vcpu->arch.mp_state = mp_state->mp_state;
8951 kvm_make_request(KVM_REQ_EVENT, vcpu);
8959 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8960 int reason, bool has_error_code, u32 error_code)
8962 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8965 init_emulate_ctxt(vcpu);
8967 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8968 has_error_code, error_code);
8970 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8971 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8972 vcpu->run->internal.ndata = 0;
8976 kvm_rip_write(vcpu, ctxt->eip);
8977 kvm_set_rflags(vcpu, ctxt->eflags);
8980 EXPORT_SYMBOL_GPL(kvm_task_switch);
8982 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8984 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8986 * When EFER.LME and CR0.PG are set, the processor is in
8987 * 64-bit mode (though maybe in a 32-bit code segment).
8988 * CR4.PAE and EFER.LMA must be set.
8990 if (!(sregs->cr4 & X86_CR4_PAE)
8991 || !(sregs->efer & EFER_LMA))
8995 * Not in 64-bit mode: EFER.LMA is clear and the code
8996 * segment cannot be 64-bit.
8998 if (sregs->efer & EFER_LMA || sregs->cs.l)
9002 return kvm_valid_cr4(vcpu, sregs->cr4);
9005 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9007 struct msr_data apic_base_msr;
9008 int mmu_reset_needed = 0;
9009 int cpuid_update_needed = 0;
9010 int pending_vec, max_bits, idx;
9014 if (kvm_valid_sregs(vcpu, sregs))
9017 apic_base_msr.data = sregs->apic_base;
9018 apic_base_msr.host_initiated = true;
9019 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9022 dt.size = sregs->idt.limit;
9023 dt.address = sregs->idt.base;
9024 kvm_x86_ops->set_idt(vcpu, &dt);
9025 dt.size = sregs->gdt.limit;
9026 dt.address = sregs->gdt.base;
9027 kvm_x86_ops->set_gdt(vcpu, &dt);
9029 vcpu->arch.cr2 = sregs->cr2;
9030 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9031 vcpu->arch.cr3 = sregs->cr3;
9032 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9034 kvm_set_cr8(vcpu, sregs->cr8);
9036 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9037 kvm_x86_ops->set_efer(vcpu, sregs->efer);
9039 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9040 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
9041 vcpu->arch.cr0 = sregs->cr0;
9043 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9044 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9045 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9046 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
9047 if (cpuid_update_needed)
9048 kvm_update_cpuid(vcpu);
9050 idx = srcu_read_lock(&vcpu->kvm->srcu);
9051 if (is_pae_paging(vcpu)) {
9052 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9053 mmu_reset_needed = 1;
9055 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9057 if (mmu_reset_needed)
9058 kvm_mmu_reset_context(vcpu);
9060 max_bits = KVM_NR_INTERRUPTS;
9061 pending_vec = find_first_bit(
9062 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9063 if (pending_vec < max_bits) {
9064 kvm_queue_interrupt(vcpu, pending_vec, false);
9065 pr_debug("Set back pending irq %d\n", pending_vec);
9068 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9069 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9070 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9071 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9072 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9073 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9075 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9076 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9078 update_cr8_intercept(vcpu);
9080 /* Older userspace won't unhalt the vcpu on reset. */
9081 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9082 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9084 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9086 kvm_make_request(KVM_REQ_EVENT, vcpu);
9093 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9094 struct kvm_sregs *sregs)
9099 ret = __set_sregs(vcpu, sregs);
9104 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9105 struct kvm_guest_debug *dbg)
9107 unsigned long rflags;
9112 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9114 if (vcpu->arch.exception.pending)
9116 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9117 kvm_queue_exception(vcpu, DB_VECTOR);
9119 kvm_queue_exception(vcpu, BP_VECTOR);
9123 * Read rflags as long as potentially injected trace flags are still
9126 rflags = kvm_get_rflags(vcpu);
9128 vcpu->guest_debug = dbg->control;
9129 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9130 vcpu->guest_debug = 0;
9132 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9133 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9134 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9135 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9137 for (i = 0; i < KVM_NR_DB_REGS; i++)
9138 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9140 kvm_update_dr7(vcpu);
9142 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9143 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9144 get_segment_base(vcpu, VCPU_SREG_CS);
9147 * Trigger an rflags update that will inject or remove the trace
9150 kvm_set_rflags(vcpu, rflags);
9152 kvm_x86_ops->update_bp_intercept(vcpu);
9162 * Translate a guest virtual address to a guest physical address.
9164 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9165 struct kvm_translation *tr)
9167 unsigned long vaddr = tr->linear_address;
9173 idx = srcu_read_lock(&vcpu->kvm->srcu);
9174 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9175 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9176 tr->physical_address = gpa;
9177 tr->valid = gpa != UNMAPPED_GVA;
9185 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9187 struct fxregs_state *fxsave;
9191 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9192 memcpy(fpu->fpr, fxsave->st_space, 128);
9193 fpu->fcw = fxsave->cwd;
9194 fpu->fsw = fxsave->swd;
9195 fpu->ftwx = fxsave->twd;
9196 fpu->last_opcode = fxsave->fop;
9197 fpu->last_ip = fxsave->rip;
9198 fpu->last_dp = fxsave->rdp;
9199 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9205 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9207 struct fxregs_state *fxsave;
9211 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9213 memcpy(fxsave->st_space, fpu->fpr, 128);
9214 fxsave->cwd = fpu->fcw;
9215 fxsave->swd = fpu->fsw;
9216 fxsave->twd = fpu->ftwx;
9217 fxsave->fop = fpu->last_opcode;
9218 fxsave->rip = fpu->last_ip;
9219 fxsave->rdp = fpu->last_dp;
9220 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9226 static void store_regs(struct kvm_vcpu *vcpu)
9228 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9230 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9231 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9233 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9234 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9236 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9237 kvm_vcpu_ioctl_x86_get_vcpu_events(
9238 vcpu, &vcpu->run->s.regs.events);
9241 static int sync_regs(struct kvm_vcpu *vcpu)
9243 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9246 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9247 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9248 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9250 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9251 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9253 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9255 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9256 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9257 vcpu, &vcpu->run->s.regs.events))
9259 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9265 static void fx_init(struct kvm_vcpu *vcpu)
9267 fpstate_init(&vcpu->arch.guest_fpu->state);
9268 if (boot_cpu_has(X86_FEATURE_XSAVES))
9269 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9270 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9273 * Ensure guest xcr0 is valid for loading
9275 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9277 vcpu->arch.cr0 |= X86_CR0_ET;
9280 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9282 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9283 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9284 "guest TSC will not be reliable\n");
9289 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9294 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9295 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9297 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9299 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9301 r = kvm_mmu_create(vcpu);
9305 if (irqchip_in_kernel(vcpu->kvm)) {
9306 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9308 goto fail_mmu_destroy;
9309 if (kvm_apicv_activated(vcpu->kvm))
9310 vcpu->arch.apicv_active = true;
9312 static_key_slow_inc(&kvm_no_apic_vcpu);
9316 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9318 goto fail_free_lapic;
9319 vcpu->arch.pio_data = page_address(page);
9321 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9322 GFP_KERNEL_ACCOUNT);
9323 if (!vcpu->arch.mce_banks)
9324 goto fail_free_pio_data;
9325 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9327 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9328 GFP_KERNEL_ACCOUNT))
9329 goto fail_free_mce_banks;
9331 if (!alloc_emulate_ctxt(vcpu))
9332 goto free_wbinvd_dirty_mask;
9334 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9335 GFP_KERNEL_ACCOUNT);
9336 if (!vcpu->arch.user_fpu) {
9337 pr_err("kvm: failed to allocate userspace's fpu\n");
9338 goto free_emulate_ctxt;
9341 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9342 GFP_KERNEL_ACCOUNT);
9343 if (!vcpu->arch.guest_fpu) {
9344 pr_err("kvm: failed to allocate vcpu's fpu\n");
9349 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9351 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9353 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9355 kvm_async_pf_hash_reset(vcpu);
9358 vcpu->arch.pending_external_vector = -1;
9359 vcpu->arch.preempted_in_kernel = false;
9361 kvm_hv_vcpu_init(vcpu);
9363 r = kvm_x86_ops->vcpu_create(vcpu);
9365 goto free_guest_fpu;
9367 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9368 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9369 kvm_vcpu_mtrr_init(vcpu);
9371 kvm_vcpu_reset(vcpu, false);
9372 kvm_init_mmu(vcpu, false);
9377 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9379 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9381 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9382 free_wbinvd_dirty_mask:
9383 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9384 fail_free_mce_banks:
9385 kfree(vcpu->arch.mce_banks);
9387 free_page((unsigned long)vcpu->arch.pio_data);
9389 kvm_free_lapic(vcpu);
9391 kvm_mmu_destroy(vcpu);
9395 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9397 struct msr_data msr;
9398 struct kvm *kvm = vcpu->kvm;
9400 kvm_hv_vcpu_postcreate(vcpu);
9402 if (mutex_lock_killable(&vcpu->mutex))
9406 msr.index = MSR_IA32_TSC;
9407 msr.host_initiated = true;
9408 kvm_write_tsc(vcpu, &msr);
9411 /* poll control enabled by default */
9412 vcpu->arch.msr_kvm_poll_control = 1;
9414 mutex_unlock(&vcpu->mutex);
9416 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9417 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9418 KVMCLOCK_SYNC_PERIOD);
9421 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9423 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9426 kvm_release_pfn(cache->pfn, cache->dirty, cache);
9428 kvmclock_reset(vcpu);
9430 kvm_x86_ops->vcpu_free(vcpu);
9432 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9433 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9434 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9435 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9437 kvm_hv_vcpu_uninit(vcpu);
9438 kvm_pmu_destroy(vcpu);
9439 kfree(vcpu->arch.mce_banks);
9440 kvm_free_lapic(vcpu);
9441 idx = srcu_read_lock(&vcpu->kvm->srcu);
9442 kvm_mmu_destroy(vcpu);
9443 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9444 free_page((unsigned long)vcpu->arch.pio_data);
9445 if (!lapic_in_kernel(vcpu))
9446 static_key_slow_dec(&kvm_no_apic_vcpu);
9449 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9451 kvm_lapic_reset(vcpu, init_event);
9453 vcpu->arch.hflags = 0;
9455 vcpu->arch.smi_pending = 0;
9456 vcpu->arch.smi_count = 0;
9457 atomic_set(&vcpu->arch.nmi_queued, 0);
9458 vcpu->arch.nmi_pending = 0;
9459 vcpu->arch.nmi_injected = false;
9460 kvm_clear_interrupt_queue(vcpu);
9461 kvm_clear_exception_queue(vcpu);
9463 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9464 kvm_update_dr0123(vcpu);
9465 vcpu->arch.dr6 = DR6_INIT;
9466 kvm_update_dr6(vcpu);
9467 vcpu->arch.dr7 = DR7_FIXED_1;
9468 kvm_update_dr7(vcpu);
9472 kvm_make_request(KVM_REQ_EVENT, vcpu);
9473 vcpu->arch.apf.msr_val = 0;
9474 vcpu->arch.st.msr_val = 0;
9476 kvmclock_reset(vcpu);
9478 kvm_clear_async_pf_completion_queue(vcpu);
9479 kvm_async_pf_hash_reset(vcpu);
9480 vcpu->arch.apf.halted = false;
9482 if (kvm_mpx_supported()) {
9483 void *mpx_state_buffer;
9486 * To avoid have the INIT path from kvm_apic_has_events() that be
9487 * called with loaded FPU and does not let userspace fix the state.
9490 kvm_put_guest_fpu(vcpu);
9491 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9493 if (mpx_state_buffer)
9494 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9495 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9497 if (mpx_state_buffer)
9498 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9500 kvm_load_guest_fpu(vcpu);
9504 kvm_pmu_reset(vcpu);
9505 vcpu->arch.smbase = 0x30000;
9507 vcpu->arch.msr_misc_features_enables = 0;
9509 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9512 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9513 vcpu->arch.regs_avail = ~0;
9514 vcpu->arch.regs_dirty = ~0;
9516 vcpu->arch.ia32_xss = 0;
9518 kvm_x86_ops->vcpu_reset(vcpu, init_event);
9521 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9523 struct kvm_segment cs;
9525 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9526 cs.selector = vector << 8;
9527 cs.base = vector << 12;
9528 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9529 kvm_rip_write(vcpu, 0);
9532 int kvm_arch_hardware_enable(void)
9535 struct kvm_vcpu *vcpu;
9540 bool stable, backwards_tsc = false;
9542 kvm_shared_msr_cpu_online();
9543 ret = kvm_x86_ops->hardware_enable();
9547 local_tsc = rdtsc();
9548 stable = !kvm_check_tsc_unstable();
9549 list_for_each_entry(kvm, &vm_list, vm_list) {
9550 kvm_for_each_vcpu(i, vcpu, kvm) {
9551 if (!stable && vcpu->cpu == smp_processor_id())
9552 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9553 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9554 backwards_tsc = true;
9555 if (vcpu->arch.last_host_tsc > max_tsc)
9556 max_tsc = vcpu->arch.last_host_tsc;
9562 * Sometimes, even reliable TSCs go backwards. This happens on
9563 * platforms that reset TSC during suspend or hibernate actions, but
9564 * maintain synchronization. We must compensate. Fortunately, we can
9565 * detect that condition here, which happens early in CPU bringup,
9566 * before any KVM threads can be running. Unfortunately, we can't
9567 * bring the TSCs fully up to date with real time, as we aren't yet far
9568 * enough into CPU bringup that we know how much real time has actually
9569 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9570 * variables that haven't been updated yet.
9572 * So we simply find the maximum observed TSC above, then record the
9573 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9574 * the adjustment will be applied. Note that we accumulate
9575 * adjustments, in case multiple suspend cycles happen before some VCPU
9576 * gets a chance to run again. In the event that no KVM threads get a
9577 * chance to run, we will miss the entire elapsed period, as we'll have
9578 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9579 * loose cycle time. This isn't too big a deal, since the loss will be
9580 * uniform across all VCPUs (not to mention the scenario is extremely
9581 * unlikely). It is possible that a second hibernate recovery happens
9582 * much faster than a first, causing the observed TSC here to be
9583 * smaller; this would require additional padding adjustment, which is
9584 * why we set last_host_tsc to the local tsc observed here.
9586 * N.B. - this code below runs only on platforms with reliable TSC,
9587 * as that is the only way backwards_tsc is set above. Also note
9588 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9589 * have the same delta_cyc adjustment applied if backwards_tsc
9590 * is detected. Note further, this adjustment is only done once,
9591 * as we reset last_host_tsc on all VCPUs to stop this from being
9592 * called multiple times (one for each physical CPU bringup).
9594 * Platforms with unreliable TSCs don't have to deal with this, they
9595 * will be compensated by the logic in vcpu_load, which sets the TSC to
9596 * catchup mode. This will catchup all VCPUs to real time, but cannot
9597 * guarantee that they stay in perfect synchronization.
9599 if (backwards_tsc) {
9600 u64 delta_cyc = max_tsc - local_tsc;
9601 list_for_each_entry(kvm, &vm_list, vm_list) {
9602 kvm->arch.backwards_tsc_observed = true;
9603 kvm_for_each_vcpu(i, vcpu, kvm) {
9604 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9605 vcpu->arch.last_host_tsc = local_tsc;
9606 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9610 * We have to disable TSC offset matching.. if you were
9611 * booting a VM while issuing an S4 host suspend....
9612 * you may have some problem. Solving this issue is
9613 * left as an exercise to the reader.
9615 kvm->arch.last_tsc_nsec = 0;
9616 kvm->arch.last_tsc_write = 0;
9623 void kvm_arch_hardware_disable(void)
9625 kvm_x86_ops->hardware_disable();
9626 drop_user_return_notifiers();
9629 int kvm_arch_hardware_setup(void)
9633 rdmsrl_safe(MSR_EFER, &host_efer);
9635 if (boot_cpu_has(X86_FEATURE_XSAVES))
9636 rdmsrl(MSR_IA32_XSS, host_xss);
9638 r = kvm_x86_ops->hardware_setup();
9642 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9645 cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data);
9647 if (kvm_has_tsc_control) {
9649 * Make sure the user can only configure tsc_khz values that
9650 * fit into a signed integer.
9651 * A min value is not calculated because it will always
9652 * be 1 on all machines.
9654 u64 max = min(0x7fffffffULL,
9655 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9656 kvm_max_guest_tsc_khz = max;
9658 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9661 kvm_init_msr_list();
9665 void kvm_arch_hardware_unsetup(void)
9667 kvm_x86_ops->hardware_unsetup();
9670 int kvm_arch_check_processor_compat(void)
9672 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9674 WARN_ON(!irqs_disabled());
9676 if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits)
9679 return kvm_x86_ops->check_processor_compatibility();
9682 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9684 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9686 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9688 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9690 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9693 struct static_key kvm_no_apic_vcpu __read_mostly;
9694 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9696 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9698 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9700 vcpu->arch.l1tf_flush_l1d = true;
9701 if (pmu->version && unlikely(pmu->event_count)) {
9702 pmu->need_cleanup = true;
9703 kvm_make_request(KVM_REQ_PMU, vcpu);
9705 kvm_x86_ops->sched_in(vcpu, cpu);
9708 void kvm_arch_free_vm(struct kvm *kvm)
9710 kfree(kvm->arch.hyperv.hv_pa_pg);
9715 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9720 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9721 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9722 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9723 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9724 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9725 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9727 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9728 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9729 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9730 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9731 &kvm->arch.irq_sources_bitmap);
9733 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9734 mutex_init(&kvm->arch.apic_map_lock);
9735 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9737 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9738 pvclock_update_vm_gtod_copy(kvm);
9740 kvm->arch.guest_can_read_msr_platform_info = true;
9742 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9743 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9745 kvm_hv_init_vm(kvm);
9746 kvm_page_track_init(kvm);
9747 kvm_mmu_init_vm(kvm);
9749 return kvm_x86_ops->vm_init(kvm);
9752 int kvm_arch_post_init_vm(struct kvm *kvm)
9754 return kvm_mmu_post_init_vm(kvm);
9757 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9760 kvm_mmu_unload(vcpu);
9764 static void kvm_free_vcpus(struct kvm *kvm)
9767 struct kvm_vcpu *vcpu;
9770 * Unpin any mmu pages first.
9772 kvm_for_each_vcpu(i, vcpu, kvm) {
9773 kvm_clear_async_pf_completion_queue(vcpu);
9774 kvm_unload_vcpu_mmu(vcpu);
9776 kvm_for_each_vcpu(i, vcpu, kvm)
9777 kvm_vcpu_destroy(vcpu);
9779 mutex_lock(&kvm->lock);
9780 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9781 kvm->vcpus[i] = NULL;
9783 atomic_set(&kvm->online_vcpus, 0);
9784 mutex_unlock(&kvm->lock);
9787 void kvm_arch_sync_events(struct kvm *kvm)
9789 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9790 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9794 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9797 unsigned long hva, uninitialized_var(old_npages);
9798 struct kvm_memslots *slots = kvm_memslots(kvm);
9799 struct kvm_memory_slot *slot;
9801 /* Called with kvm->slots_lock held. */
9802 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9805 slot = id_to_memslot(slots, id);
9807 if (slot && slot->npages)
9811 * MAP_SHARED to prevent internal slot pages from being moved
9814 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9815 MAP_SHARED | MAP_ANONYMOUS, 0);
9816 if (IS_ERR((void *)hva))
9817 return PTR_ERR((void *)hva);
9819 if (!slot || !slot->npages)
9823 * Stuff a non-canonical value to catch use-after-delete. This
9824 * ends up being 0 on 32-bit KVM, but there's no better
9827 hva = (unsigned long)(0xdeadull << 48);
9828 old_npages = slot->npages;
9831 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9832 struct kvm_userspace_memory_region m;
9834 m.slot = id | (i << 16);
9836 m.guest_phys_addr = gpa;
9837 m.userspace_addr = hva;
9838 m.memory_size = size;
9839 r = __kvm_set_memory_region(kvm, &m);
9845 vm_munmap(hva, old_npages * PAGE_SIZE);
9849 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9851 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9853 kvm_mmu_pre_destroy_vm(kvm);
9856 void kvm_arch_destroy_vm(struct kvm *kvm)
9858 if (current->mm == kvm->mm) {
9860 * Free memory regions allocated on behalf of userspace,
9861 * unless the the memory map has changed due to process exit
9864 mutex_lock(&kvm->slots_lock);
9865 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9867 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
9869 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9870 mutex_unlock(&kvm->slots_lock);
9872 if (kvm_x86_ops->vm_destroy)
9873 kvm_x86_ops->vm_destroy(kvm);
9874 kvm_pic_destroy(kvm);
9875 kvm_ioapic_destroy(kvm);
9876 kvm_free_vcpus(kvm);
9877 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9878 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9879 kvm_mmu_uninit_vm(kvm);
9880 kvm_page_track_cleanup(kvm);
9881 kvm_hv_destroy_vm(kvm);
9884 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
9888 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9889 kvfree(slot->arch.rmap[i]);
9890 slot->arch.rmap[i] = NULL;
9895 kvfree(slot->arch.lpage_info[i - 1]);
9896 slot->arch.lpage_info[i - 1] = NULL;
9899 kvm_page_track_free_memslot(slot);
9902 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
9903 unsigned long npages)
9908 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
9909 * old arrays will be freed by __kvm_set_memory_region() if installing
9910 * the new memslot is successful.
9912 memset(&slot->arch, 0, sizeof(slot->arch));
9914 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9915 struct kvm_lpage_info *linfo;
9920 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9921 slot->base_gfn, level) + 1;
9923 slot->arch.rmap[i] =
9924 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9925 GFP_KERNEL_ACCOUNT);
9926 if (!slot->arch.rmap[i])
9931 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9935 slot->arch.lpage_info[i - 1] = linfo;
9937 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9938 linfo[0].disallow_lpage = 1;
9939 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9940 linfo[lpages - 1].disallow_lpage = 1;
9941 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9943 * If the gfn and userspace address are not aligned wrt each
9944 * other, disable large page support for this slot.
9946 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
9949 for (j = 0; j < lpages; ++j)
9950 linfo[j].disallow_lpage = 1;
9954 if (kvm_page_track_create_memslot(slot, npages))
9960 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9961 kvfree(slot->arch.rmap[i]);
9962 slot->arch.rmap[i] = NULL;
9966 kvfree(slot->arch.lpage_info[i - 1]);
9967 slot->arch.lpage_info[i - 1] = NULL;
9972 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9974 struct kvm_vcpu *vcpu;
9978 * memslots->generation has been incremented.
9979 * mmio generation may have reached its maximum value.
9981 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9983 /* Force re-initialization of steal_time cache */
9984 kvm_for_each_vcpu(i, vcpu, kvm)
9985 kvm_vcpu_kick(vcpu);
9988 int kvm_arch_prepare_memory_region(struct kvm *kvm,
9989 struct kvm_memory_slot *memslot,
9990 const struct kvm_userspace_memory_region *mem,
9991 enum kvm_mr_change change)
9993 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
9994 return kvm_alloc_memslot_metadata(memslot,
9995 mem->memory_size >> PAGE_SHIFT);
9999 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10000 struct kvm_memory_slot *new)
10002 /* Still write protect RO slot */
10003 if (new->flags & KVM_MEM_READONLY) {
10004 kvm_mmu_slot_remove_write_access(kvm, new, PT_PAGE_TABLE_LEVEL);
10009 * Call kvm_x86_ops dirty logging hooks when they are valid.
10011 * kvm_x86_ops->slot_disable_log_dirty is called when:
10013 * - KVM_MR_CREATE with dirty logging is disabled
10014 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
10016 * The reason is, in case of PML, we need to set D-bit for any slots
10017 * with dirty logging disabled in order to eliminate unnecessary GPA
10018 * logging in PML buffer (and potential PML buffer full VMEXIT). This
10019 * guarantees leaving PML enabled during guest's lifetime won't have
10020 * any additional overhead from PML when guest is running with dirty
10021 * logging disabled for memory slots.
10023 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
10024 * to dirty logging mode.
10026 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
10028 * In case of write protect:
10030 * Write protect all pages for dirty logging.
10032 * All the sptes including the large sptes which point to this
10033 * slot are set to readonly. We can not create any new large
10034 * spte on this slot until the end of the logging.
10036 * See the comments in fast_page_fault().
10038 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10039 if (kvm_x86_ops->slot_enable_log_dirty) {
10040 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
10043 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10044 PT_DIRECTORY_LEVEL : PT_PAGE_TABLE_LEVEL;
10047 * If we're with initial-all-set, we don't need
10048 * to write protect any small page because
10049 * they're reported as dirty already. However
10050 * we still need to write-protect huge pages
10051 * so that the page split can happen lazily on
10052 * the first write to the huge page.
10054 kvm_mmu_slot_remove_write_access(kvm, new, level);
10057 if (kvm_x86_ops->slot_disable_log_dirty)
10058 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
10062 void kvm_arch_commit_memory_region(struct kvm *kvm,
10063 const struct kvm_userspace_memory_region *mem,
10064 struct kvm_memory_slot *old,
10065 const struct kvm_memory_slot *new,
10066 enum kvm_mr_change change)
10068 if (!kvm->arch.n_requested_mmu_pages)
10069 kvm_mmu_change_mmu_pages(kvm,
10070 kvm_mmu_calculate_default_mmu_pages(kvm));
10073 * Dirty logging tracks sptes in 4k granularity, meaning that large
10074 * sptes have to be split. If live migration is successful, the guest
10075 * in the source machine will be destroyed and large sptes will be
10076 * created in the destination. However, if the guest continues to run
10077 * in the source machine (for example if live migration fails), small
10078 * sptes will remain around and cause bad performance.
10080 * Scan sptes if dirty logging has been stopped, dropping those
10081 * which can be collapsed into a single large-page spte. Later
10082 * page faults will create the large-page sptes.
10084 * There is no need to do this in any of the following cases:
10085 * CREATE: No dirty mappings will already exist.
10086 * MOVE/DELETE: The old mappings will already have been cleaned up by
10087 * kvm_arch_flush_shadow_memslot()
10089 if (change == KVM_MR_FLAGS_ONLY &&
10090 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10091 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10092 kvm_mmu_zap_collapsible_sptes(kvm, new);
10095 * Set up write protection and/or dirty logging for the new slot.
10097 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
10098 * been zapped so no dirty logging staff is needed for old slot. For
10099 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
10100 * new and it's also covered when dealing with the new slot.
10102 * FIXME: const-ify all uses of struct kvm_memory_slot.
10104 if (change != KVM_MR_DELETE)
10105 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
10107 /* Free the arrays associated with the old memslot. */
10108 if (change == KVM_MR_MOVE)
10109 kvm_arch_free_memslot(kvm, old);
10112 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10114 kvm_mmu_zap_all(kvm);
10117 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10118 struct kvm_memory_slot *slot)
10120 kvm_page_track_flush_slot(kvm, slot);
10123 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10125 return (is_guest_mode(vcpu) &&
10126 kvm_x86_ops->guest_apic_has_interrupt &&
10127 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
10130 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10132 if (!list_empty_careful(&vcpu->async_pf.done))
10135 if (kvm_apic_has_events(vcpu))
10138 if (vcpu->arch.pv.pv_unhalted)
10141 if (vcpu->arch.exception.pending)
10144 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10145 (vcpu->arch.nmi_pending &&
10146 kvm_x86_ops->nmi_allowed(vcpu)))
10149 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10150 (vcpu->arch.smi_pending && !is_smm(vcpu)))
10153 if (kvm_arch_interrupt_allowed(vcpu) &&
10154 (kvm_cpu_has_interrupt(vcpu) ||
10155 kvm_guest_apic_has_interrupt(vcpu)))
10158 if (kvm_hv_has_stimer_pending(vcpu))
10164 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10166 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10169 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10171 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10174 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10175 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10176 kvm_test_request(KVM_REQ_EVENT, vcpu))
10179 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
10185 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10187 return vcpu->arch.preempted_in_kernel;
10190 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10192 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10195 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10197 return kvm_x86_ops->interrupt_allowed(vcpu);
10200 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10202 if (is_64_bit_mode(vcpu))
10203 return kvm_rip_read(vcpu);
10204 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10205 kvm_rip_read(vcpu));
10207 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10209 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10211 return kvm_get_linear_rip(vcpu) == linear_rip;
10213 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10215 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10217 unsigned long rflags;
10219 rflags = kvm_x86_ops->get_rflags(vcpu);
10220 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10221 rflags &= ~X86_EFLAGS_TF;
10224 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10226 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10228 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10229 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10230 rflags |= X86_EFLAGS_TF;
10231 kvm_x86_ops->set_rflags(vcpu, rflags);
10234 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10236 __kvm_set_rflags(vcpu, rflags);
10237 kvm_make_request(KVM_REQ_EVENT, vcpu);
10239 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10241 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10245 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10249 r = kvm_mmu_reload(vcpu);
10253 if (!vcpu->arch.mmu->direct_map &&
10254 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10257 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10260 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10262 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10265 static inline u32 kvm_async_pf_next_probe(u32 key)
10267 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10270 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10272 u32 key = kvm_async_pf_hash_fn(gfn);
10274 while (vcpu->arch.apf.gfns[key] != ~0)
10275 key = kvm_async_pf_next_probe(key);
10277 vcpu->arch.apf.gfns[key] = gfn;
10280 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10283 u32 key = kvm_async_pf_hash_fn(gfn);
10285 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
10286 (vcpu->arch.apf.gfns[key] != gfn &&
10287 vcpu->arch.apf.gfns[key] != ~0); i++)
10288 key = kvm_async_pf_next_probe(key);
10293 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10295 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10298 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10302 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10304 vcpu->arch.apf.gfns[i] = ~0;
10306 j = kvm_async_pf_next_probe(j);
10307 if (vcpu->arch.apf.gfns[j] == ~0)
10309 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10311 * k lies cyclically in ]i,j]
10313 * |....j i.k.| or |.k..j i...|
10315 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10316 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10321 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10324 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10328 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10331 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10335 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10337 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10340 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10341 (vcpu->arch.apf.send_user_only &&
10342 kvm_x86_ops->get_cpl(vcpu) == 0))
10348 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10350 if (unlikely(!lapic_in_kernel(vcpu) ||
10351 kvm_event_needs_reinjection(vcpu) ||
10352 vcpu->arch.exception.pending))
10355 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10359 * If interrupts are off we cannot even use an artificial
10362 return kvm_x86_ops->interrupt_allowed(vcpu);
10365 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10366 struct kvm_async_pf *work)
10368 struct x86_exception fault;
10370 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10371 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10373 if (kvm_can_deliver_async_pf(vcpu) &&
10374 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10375 fault.vector = PF_VECTOR;
10376 fault.error_code_valid = true;
10377 fault.error_code = 0;
10378 fault.nested_page_fault = false;
10379 fault.address = work->arch.token;
10380 fault.async_page_fault = true;
10381 kvm_inject_page_fault(vcpu, &fault);
10384 * It is not possible to deliver a paravirtualized asynchronous
10385 * page fault, but putting the guest in an artificial halt state
10386 * can be beneficial nevertheless: if an interrupt arrives, we
10387 * can deliver it timely and perhaps the guest will schedule
10388 * another process. When the instruction that triggered a page
10389 * fault is retried, hopefully the page will be ready in the host.
10391 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10395 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10396 struct kvm_async_pf *work)
10398 struct x86_exception fault;
10401 if (work->wakeup_all)
10402 work->arch.token = ~0; /* broadcast wakeup */
10404 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10405 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10407 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10408 !apf_get_user(vcpu, &val)) {
10409 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10410 vcpu->arch.exception.pending &&
10411 vcpu->arch.exception.nr == PF_VECTOR &&
10412 !apf_put_user(vcpu, 0)) {
10413 vcpu->arch.exception.injected = false;
10414 vcpu->arch.exception.pending = false;
10415 vcpu->arch.exception.nr = 0;
10416 vcpu->arch.exception.has_error_code = false;
10417 vcpu->arch.exception.error_code = 0;
10418 vcpu->arch.exception.has_payload = false;
10419 vcpu->arch.exception.payload = 0;
10420 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10421 fault.vector = PF_VECTOR;
10422 fault.error_code_valid = true;
10423 fault.error_code = 0;
10424 fault.nested_page_fault = false;
10425 fault.address = work->arch.token;
10426 fault.async_page_fault = true;
10427 kvm_inject_page_fault(vcpu, &fault);
10430 vcpu->arch.apf.halted = false;
10431 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10434 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10436 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10439 return kvm_can_do_async_pf(vcpu);
10442 void kvm_arch_start_assignment(struct kvm *kvm)
10444 atomic_inc(&kvm->arch.assigned_device_count);
10446 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10448 void kvm_arch_end_assignment(struct kvm *kvm)
10450 atomic_dec(&kvm->arch.assigned_device_count);
10452 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10454 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10456 return atomic_read(&kvm->arch.assigned_device_count);
10458 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10460 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10462 atomic_inc(&kvm->arch.noncoherent_dma_count);
10464 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10466 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10468 atomic_dec(&kvm->arch.noncoherent_dma_count);
10470 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10472 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10474 return atomic_read(&kvm->arch.noncoherent_dma_count);
10476 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10478 bool kvm_arch_has_irq_bypass(void)
10483 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10484 struct irq_bypass_producer *prod)
10486 struct kvm_kernel_irqfd *irqfd =
10487 container_of(cons, struct kvm_kernel_irqfd, consumer);
10489 irqfd->producer = prod;
10491 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10492 prod->irq, irqfd->gsi, 1);
10495 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10496 struct irq_bypass_producer *prod)
10499 struct kvm_kernel_irqfd *irqfd =
10500 container_of(cons, struct kvm_kernel_irqfd, consumer);
10502 WARN_ON(irqfd->producer != prod);
10503 irqfd->producer = NULL;
10506 * When producer of consumer is unregistered, we change back to
10507 * remapped mode, so we can re-use the current implementation
10508 * when the irq is masked/disabled or the consumer side (KVM
10509 * int this case doesn't want to receive the interrupts.
10511 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10513 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10514 " fails: %d\n", irqfd->consumer.token, ret);
10517 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10518 uint32_t guest_irq, bool set)
10520 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10523 bool kvm_vector_hashing_enabled(void)
10525 return vector_hashing;
10528 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10530 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10532 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10534 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10536 uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10538 /* The STIBP bit doesn't fault even if it's not advertised */
10539 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10540 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10541 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10542 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10543 !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10544 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10546 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10547 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10548 bits &= ~SPEC_CTRL_SSBD;
10549 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10550 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10551 bits &= ~SPEC_CTRL_SSBD;
10555 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
10557 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10558 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10559 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10560 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10561 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10562 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10563 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10564 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10565 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10566 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10567 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10568 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10569 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10570 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
10578 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);