arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45
  46 #include "trace.h"
  47
  48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  49 #define __ex_clear(x, reg) \
  50         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  51
  52 MODULE_AUTHOR("Qumranet");
  53 MODULE_LICENSE("GPL");
  54
  55 static const struct x86_cpu_id vmx_cpu_id[] = {
  56         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  57         {}
  58 };
  59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  60
  61 static bool __read_mostly enable_vpid = 1;
  62 module_param_named(vpid, enable_vpid, bool, 0444);
  63
  64 static bool __read_mostly flexpriority_enabled = 1;
  65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  66
  67 static bool __read_mostly enable_ept = 1;
  68 module_param_named(ept, enable_ept, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_unrestricted_guest = 1;
  71 module_param_named(unrestricted_guest,
  72                         enable_unrestricted_guest, bool, S_IRUGO);
  73
  74 static bool __read_mostly emulate_invalid_guest_state = 0;
  75 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  76
  77 static bool __read_mostly vmm_exclusive = 1;
  78 module_param(vmm_exclusive, bool, S_IRUGO);
  79
  80 static bool __read_mostly fasteoi = 1;
  81 module_param(fasteoi, bool, S_IRUGO);
  82
  83 /*
  84  * If nested=1, nested virtualization is supported, i.e., guests may use
  85  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  86  * use VMX instructions.
  87  */
  88 static bool __read_mostly nested = 0;
  89 module_param(nested, bool, S_IRUGO);
  90
  91 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  92         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  93 #define KVM_GUEST_CR0_MASK                                              \
  94         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  95 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  96         (X86_CR0_WP | X86_CR0_NE)
  97 #define KVM_VM_CR0_ALWAYS_ON                                            \
  98         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  99 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 100         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 101          | X86_CR4_OSXMMEXCPT)
 102
 103 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 104 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 105
 106 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 107
 108 /*
 109  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 110  * ple_gap:    upper bound on the amount of time between two successive
 111  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 112  *             According to test, this time is usually smaller than 128 cycles.
 113  * ple_window: upper bound on the amount of time a guest is allowed to execute
 114  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 115  *             less than 2^12 cycles
 116  * Time is measured based on a counter that runs at the same rate as the TSC,
 117  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 118  */
 119 #define KVM_VMX_DEFAULT_PLE_GAP    128
 120 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 121 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 122 module_param(ple_gap, int, S_IRUGO);
 123
 124 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 125 module_param(ple_window, int, S_IRUGO);
 126
 127 #define NR_AUTOLOAD_MSRS 8
 128 #define VMCS02_POOL_SIZE 1
 129
 130 struct vmcs {
 131         u32 revision_id;
 132         u32 abort;
 133         char data[0];
 134 };
 135
 136 /*
 137  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 138  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 139  * loaded on this CPU (so we can clear them if the CPU goes down).
 140  */
 141 struct loaded_vmcs {
 142         struct vmcs *vmcs;
 143         int cpu;
 144         int launched;
 145         struct list_head loaded_vmcss_on_cpu_link;
 146 };
 147
 148 struct shared_msr_entry {
 149         unsigned index;
 150         u64 data;
 151         u64 mask;
 152 };
 153
 154 /*
 155  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 156  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 157  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 158  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 159  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 160  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 161  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 162  * underlying hardware which will be used to run L2.
 163  * This structure is packed to ensure that its layout is identical across
 164  * machines (necessary for live migration).
 165  * If there are changes in this struct, VMCS12_REVISION must be changed.
 166  */
 167 typedef u64 natural_width;
 168 struct __packed vmcs12 {
 169         /* According to the Intel spec, a VMCS region must start with the
 170          * following two fields. Then follow implementation-specific data.
 171          */
 172         u32 revision_id;
 173         u32 abort;
 174
 175         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 176         u32 padding[7]; /* room for future expansion */
 177
 178         u64 io_bitmap_a;
 179         u64 io_bitmap_b;
 180         u64 msr_bitmap;
 181         u64 vm_exit_msr_store_addr;
 182         u64 vm_exit_msr_load_addr;
 183         u64 vm_entry_msr_load_addr;
 184         u64 tsc_offset;
 185         u64 virtual_apic_page_addr;
 186         u64 apic_access_addr;
 187         u64 ept_pointer;
 188         u64 guest_physical_address;
 189         u64 vmcs_link_pointer;
 190         u64 guest_ia32_debugctl;
 191         u64 guest_ia32_pat;
 192         u64 guest_ia32_efer;
 193         u64 guest_ia32_perf_global_ctrl;
 194         u64 guest_pdptr0;
 195         u64 guest_pdptr1;
 196         u64 guest_pdptr2;
 197         u64 guest_pdptr3;
 198         u64 host_ia32_pat;
 199         u64 host_ia32_efer;
 200         u64 host_ia32_perf_global_ctrl;
 201         u64 padding64[8]; /* room for future expansion */
 202         /*
 203          * To allow migration of L1 (complete with its L2 guests) between
 204          * machines of different natural widths (32 or 64 bit), we cannot have
 205          * unsigned long fields with no explict size. We use u64 (aliased
 206          * natural_width) instead. Luckily, x86 is little-endian.
 207          */
 208         natural_width cr0_guest_host_mask;
 209         natural_width cr4_guest_host_mask;
 210         natural_width cr0_read_shadow;
 211         natural_width cr4_read_shadow;
 212         natural_width cr3_target_value0;
 213         natural_width cr3_target_value1;
 214         natural_width cr3_target_value2;
 215         natural_width cr3_target_value3;
 216         natural_width exit_qualification;
 217         natural_width guest_linear_address;
 218         natural_width guest_cr0;
 219         natural_width guest_cr3;
 220         natural_width guest_cr4;
 221         natural_width guest_es_base;
 222         natural_width guest_cs_base;
 223         natural_width guest_ss_base;
 224         natural_width guest_ds_base;
 225         natural_width guest_fs_base;
 226         natural_width guest_gs_base;
 227         natural_width guest_ldtr_base;
 228         natural_width guest_tr_base;
 229         natural_width guest_gdtr_base;
 230         natural_width guest_idtr_base;
 231         natural_width guest_dr7;
 232         natural_width guest_rsp;
 233         natural_width guest_rip;
 234         natural_width guest_rflags;
 235         natural_width guest_pending_dbg_exceptions;
 236         natural_width guest_sysenter_esp;
 237         natural_width guest_sysenter_eip;
 238         natural_width host_cr0;
 239         natural_width host_cr3;
 240         natural_width host_cr4;
 241         natural_width host_fs_base;
 242         natural_width host_gs_base;
 243         natural_width host_tr_base;
 244         natural_width host_gdtr_base;
 245         natural_width host_idtr_base;
 246         natural_width host_ia32_sysenter_esp;
 247         natural_width host_ia32_sysenter_eip;
 248         natural_width host_rsp;
 249         natural_width host_rip;
 250         natural_width paddingl[8]; /* room for future expansion */
 251         u32 pin_based_vm_exec_control;
 252         u32 cpu_based_vm_exec_control;
 253         u32 exception_bitmap;
 254         u32 page_fault_error_code_mask;
 255         u32 page_fault_error_code_match;
 256         u32 cr3_target_count;
 257         u32 vm_exit_controls;
 258         u32 vm_exit_msr_store_count;
 259         u32 vm_exit_msr_load_count;
 260         u32 vm_entry_controls;
 261         u32 vm_entry_msr_load_count;
 262         u32 vm_entry_intr_info_field;
 263         u32 vm_entry_exception_error_code;
 264         u32 vm_entry_instruction_len;
 265         u32 tpr_threshold;
 266         u32 secondary_vm_exec_control;
 267         u32 vm_instruction_error;
 268         u32 vm_exit_reason;
 269         u32 vm_exit_intr_info;
 270         u32 vm_exit_intr_error_code;
 271         u32 idt_vectoring_info_field;
 272         u32 idt_vectoring_error_code;
 273         u32 vm_exit_instruction_len;
 274         u32 vmx_instruction_info;
 275         u32 guest_es_limit;
 276         u32 guest_cs_limit;
 277         u32 guest_ss_limit;
 278         u32 guest_ds_limit;
 279         u32 guest_fs_limit;
 280         u32 guest_gs_limit;
 281         u32 guest_ldtr_limit;
 282         u32 guest_tr_limit;
 283         u32 guest_gdtr_limit;
 284         u32 guest_idtr_limit;
 285         u32 guest_es_ar_bytes;
 286         u32 guest_cs_ar_bytes;
 287         u32 guest_ss_ar_bytes;
 288         u32 guest_ds_ar_bytes;
 289         u32 guest_fs_ar_bytes;
 290         u32 guest_gs_ar_bytes;
 291         u32 guest_ldtr_ar_bytes;
 292         u32 guest_tr_ar_bytes;
 293         u32 guest_interruptibility_info;
 294         u32 guest_activity_state;
 295         u32 guest_sysenter_cs;
 296         u32 host_ia32_sysenter_cs;
 297         u32 padding32[8]; /* room for future expansion */
 298         u16 virtual_processor_id;
 299         u16 guest_es_selector;
 300         u16 guest_cs_selector;
 301         u16 guest_ss_selector;
 302         u16 guest_ds_selector;
 303         u16 guest_fs_selector;
 304         u16 guest_gs_selector;
 305         u16 guest_ldtr_selector;
 306         u16 guest_tr_selector;
 307         u16 host_es_selector;
 308         u16 host_cs_selector;
 309         u16 host_ss_selector;
 310         u16 host_ds_selector;
 311         u16 host_fs_selector;
 312         u16 host_gs_selector;
 313         u16 host_tr_selector;
 314 };
 315
 316 /*
 317  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 318  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 319  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 320  */
 321 #define VMCS12_REVISION 0x11e57ed0
 322
 323 /*
 324  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 325  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 326  * current implementation, 4K are reserved to avoid future complications.
 327  */
 328 #define VMCS12_SIZE 0x1000
 329
 330 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 331 struct vmcs02_list {
 332         struct list_head list;
 333         gpa_t vmptr;
 334         struct loaded_vmcs vmcs02;
 335 };
 336
 337 /*
 338  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 339  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 340  */
 341 struct nested_vmx {
 342         /* Has the level1 guest done vmxon? */
 343         bool vmxon;
 344
 345         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 346         gpa_t current_vmptr;
 347         /* The host-usable pointer to the above */
 348         struct page *current_vmcs12_page;
 349         struct vmcs12 *current_vmcs12;
 350
 351         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 352         struct list_head vmcs02_pool;
 353         int vmcs02_num;
 354         u64 vmcs01_tsc_offset;
 355         /* L2 must run next, and mustn't decide to exit to L1. */
 356         bool nested_run_pending;
 357         /*
 358          * Guest pages referred to in vmcs02 with host-physical pointers, so
 359          * we must keep them pinned while L2 runs.
 360          */
 361         struct page *apic_access_page;
 362 };
 363
 364 struct vcpu_vmx {
 365         struct kvm_vcpu       vcpu;
 366         unsigned long         host_rsp;
 367         u8                    fail;
 368         u8                    cpl;
 369         bool                  nmi_known_unmasked;
 370         u32                   exit_intr_info;
 371         u32                   idt_vectoring_info;
 372         ulong                 rflags;
 373         struct shared_msr_entry *guest_msrs;
 374         int                   nmsrs;
 375         int                   save_nmsrs;
 376 #ifdef CONFIG_X86_64
 377         u64                   msr_host_kernel_gs_base;
 378         u64                   msr_guest_kernel_gs_base;
 379 #endif
 380         /*
 381          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 382          * non-nested (L1) guest, it always points to vmcs01. For a nested
 383          * guest (L2), it points to a different VMCS.
 384          */
 385         struct loaded_vmcs    vmcs01;
 386         struct loaded_vmcs   *loaded_vmcs;
 387         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 388         struct msr_autoload {
 389                 unsigned nr;
 390                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 391                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 392         } msr_autoload;
 393         struct {
 394                 int           loaded;
 395                 u16           fs_sel, gs_sel, ldt_sel;
 396                 int           gs_ldt_reload_needed;
 397                 int           fs_reload_needed;
 398         } host_state;
 399         struct {
 400                 int vm86_active;
 401                 ulong save_rflags;
 402                 struct kvm_save_segment {
 403                         u16 selector;
 404                         unsigned long base;
 405                         u32 limit;
 406                         u32 ar;
 407                 } tr, es, ds, fs, gs;
 408         } rmode;
 409         struct {
 410                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 411                 struct kvm_save_segment seg[8];
 412         } segment_cache;
 413         int vpid;
 414         bool emulation_required;
 415
 416         /* Support for vnmi-less CPUs */
 417         int soft_vnmi_blocked;
 418         ktime_t entry_time;
 419         s64 vnmi_blocked_time;
 420         u32 exit_reason;
 421
 422         bool rdtscp_enabled;
 423
 424         /* Support for a guest hypervisor (nested VMX) */
 425         struct nested_vmx nested;
 426 };
 427
 428 enum segment_cache_field {
 429         SEG_FIELD_SEL = 0,
 430         SEG_FIELD_BASE = 1,
 431         SEG_FIELD_LIMIT = 2,
 432         SEG_FIELD_AR = 3,
 433
 434         SEG_FIELD_NR = 4
 435 };
 436
 437 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 438 {
 439         return container_of(vcpu, struct vcpu_vmx, vcpu);
 440 }
 441
 442 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 443 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 444 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 445                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 446
 447 static unsigned short vmcs_field_to_offset_table[] = {
 448         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 449         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 450         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 451         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 452         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 453         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 454         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 455         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 456         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 457         FIELD(HOST_ES_SELECTOR, host_es_selector),
 458         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 459         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 460         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 461         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 462         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 463         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 464         FIELD64(IO_BITMAP_A, io_bitmap_a),
 465         FIELD64(IO_BITMAP_B, io_bitmap_b),
 466         FIELD64(MSR_BITMAP, msr_bitmap),
 467         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 468         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 469         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 470         FIELD64(TSC_OFFSET, tsc_offset),
 471         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 472         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 473         FIELD64(EPT_POINTER, ept_pointer),
 474         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 475         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 476         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 477         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 478         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 479         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 480         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 481         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 482         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 483         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 484         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 485         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 486         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 487         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 488         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 489         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 490         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 491         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 492         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 493         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 494         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 495         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 496         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 497         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 498         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 499         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 500         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 501         FIELD(TPR_THRESHOLD, tpr_threshold),
 502         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 503         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 504         FIELD(VM_EXIT_REASON, vm_exit_reason),
 505         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 506         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 507         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 508         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 509         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 510         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 511         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 512         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 513         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 514         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 515         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 516         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 517         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 518         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 519         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 520         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 521         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 522         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 523         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 524         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 525         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 526         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 527         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 528         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 529         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 530         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 531         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 532         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 533         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 534         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 535         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 536         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 537         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 538         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 539         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 540         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 541         FIELD(EXIT_QUALIFICATION, exit_qualification),
 542         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 543         FIELD(GUEST_CR0, guest_cr0),
 544         FIELD(GUEST_CR3, guest_cr3),
 545         FIELD(GUEST_CR4, guest_cr4),
 546         FIELD(GUEST_ES_BASE, guest_es_base),
 547         FIELD(GUEST_CS_BASE, guest_cs_base),
 548         FIELD(GUEST_SS_BASE, guest_ss_base),
 549         FIELD(GUEST_DS_BASE, guest_ds_base),
 550         FIELD(GUEST_FS_BASE, guest_fs_base),
 551         FIELD(GUEST_GS_BASE, guest_gs_base),
 552         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 553         FIELD(GUEST_TR_BASE, guest_tr_base),
 554         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 555         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 556         FIELD(GUEST_DR7, guest_dr7),
 557         FIELD(GUEST_RSP, guest_rsp),
 558         FIELD(GUEST_RIP, guest_rip),
 559         FIELD(GUEST_RFLAGS, guest_rflags),
 560         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 561         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 562         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 563         FIELD(HOST_CR0, host_cr0),
 564         FIELD(HOST_CR3, host_cr3),
 565         FIELD(HOST_CR4, host_cr4),
 566         FIELD(HOST_FS_BASE, host_fs_base),
 567         FIELD(HOST_GS_BASE, host_gs_base),
 568         FIELD(HOST_TR_BASE, host_tr_base),
 569         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 570         FIELD(HOST_IDTR_BASE, host_idtr_base),
 571         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 572         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 573         FIELD(HOST_RSP, host_rsp),
 574         FIELD(HOST_RIP, host_rip),
 575 };
 576 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 577
 578 static inline short vmcs_field_to_offset(unsigned long field)
 579 {
 580         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 581                 return -1;
 582         return vmcs_field_to_offset_table[field];
 583 }
 584
 585 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 586 {
 587         return to_vmx(vcpu)->nested.current_vmcs12;
 588 }
 589
 590 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 591 {
 592         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 593         if (is_error_page(page)) {
 594                 kvm_release_page_clean(page);
 595                 return NULL;
 596         }
 597         return page;
 598 }
 599
 600 static void nested_release_page(struct page *page)
 601 {
 602         kvm_release_page_dirty(page);
 603 }
 604
 605 static void nested_release_page_clean(struct page *page)
 606 {
 607         kvm_release_page_clean(page);
 608 }
 609
 610 static u64 construct_eptp(unsigned long root_hpa);
 611 static void kvm_cpu_vmxon(u64 addr);
 612 static void kvm_cpu_vmxoff(void);
 613 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 614 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 615
 616 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 617 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 618 /*
 619  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 620  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 621  */
 622 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 623 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 624
 625 static unsigned long *vmx_io_bitmap_a;
 626 static unsigned long *vmx_io_bitmap_b;
 627 static unsigned long *vmx_msr_bitmap_legacy;
 628 static unsigned long *vmx_msr_bitmap_longmode;
 629
 630 static bool cpu_has_load_ia32_efer;
 631 static bool cpu_has_load_perf_global_ctrl;
 632
 633 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 634 static DEFINE_SPINLOCK(vmx_vpid_lock);
 635
 636 static struct vmcs_config {
 637         int size;
 638         int order;
 639         u32 revision_id;
 640         u32 pin_based_exec_ctrl;
 641         u32 cpu_based_exec_ctrl;
 642         u32 cpu_based_2nd_exec_ctrl;
 643         u32 vmexit_ctrl;
 644         u32 vmentry_ctrl;
 645 } vmcs_config;
 646
 647 static struct vmx_capability {
 648         u32 ept;
 649         u32 vpid;
 650 } vmx_capability;
 651
 652 #define VMX_SEGMENT_FIELD(seg)                                  \
 653         [VCPU_SREG_##seg] = {                                   \
 654                 .selector = GUEST_##seg##_SELECTOR,             \
 655                 .base = GUEST_##seg##_BASE,                     \
 656                 .limit = GUEST_##seg##_LIMIT,                   \
 657                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 658         }
 659
 660 static struct kvm_vmx_segment_field {
 661         unsigned selector;
 662         unsigned base;
 663         unsigned limit;
 664         unsigned ar_bytes;
 665 } kvm_vmx_segment_fields[] = {
 666         VMX_SEGMENT_FIELD(CS),
 667         VMX_SEGMENT_FIELD(DS),
 668         VMX_SEGMENT_FIELD(ES),
 669         VMX_SEGMENT_FIELD(FS),
 670         VMX_SEGMENT_FIELD(GS),
 671         VMX_SEGMENT_FIELD(SS),
 672         VMX_SEGMENT_FIELD(TR),
 673         VMX_SEGMENT_FIELD(LDTR),
 674 };
 675
 676 static u64 host_efer;
 677
 678 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 679
 680 /*
 681  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 682  * away by decrementing the array size.
 683  */
 684 static const u32 vmx_msr_index[] = {
 685 #ifdef CONFIG_X86_64
 686         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 687 #endif
 688         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 689 };
 690 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 691
 692 static inline bool is_page_fault(u32 intr_info)
 693 {
 694         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 695                              INTR_INFO_VALID_MASK)) ==
 696                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 697 }
 698
 699 static inline bool is_no_device(u32 intr_info)
 700 {
 701         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 702                              INTR_INFO_VALID_MASK)) ==
 703                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 704 }
 705
 706 static inline bool is_invalid_opcode(u32 intr_info)
 707 {
 708         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 709                              INTR_INFO_VALID_MASK)) ==
 710                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 711 }
 712
 713 static inline bool is_external_interrupt(u32 intr_info)
 714 {
 715         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 716                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 717 }
 718
 719 static inline bool is_machine_check(u32 intr_info)
 720 {
 721         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 722                              INTR_INFO_VALID_MASK)) ==
 723                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 724 }
 725
 726 static inline bool cpu_has_vmx_msr_bitmap(void)
 727 {
 728         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 729 }
 730
 731 static inline bool cpu_has_vmx_tpr_shadow(void)
 732 {
 733         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 734 }
 735
 736 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 737 {
 738         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 739 }
 740
 741 static inline bool cpu_has_secondary_exec_ctrls(void)
 742 {
 743         return vmcs_config.cpu_based_exec_ctrl &
 744                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 745 }
 746
 747 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 748 {
 749         return vmcs_config.cpu_based_2nd_exec_ctrl &
 750                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 751 }
 752
 753 static inline bool cpu_has_vmx_flexpriority(void)
 754 {
 755         return cpu_has_vmx_tpr_shadow() &&
 756                 cpu_has_vmx_virtualize_apic_accesses();
 757 }
 758
 759 static inline bool cpu_has_vmx_ept_execute_only(void)
 760 {
 761         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 762 }
 763
 764 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 765 {
 766         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 767 }
 768
 769 static inline bool cpu_has_vmx_eptp_writeback(void)
 770 {
 771         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 772 }
 773
 774 static inline bool cpu_has_vmx_ept_2m_page(void)
 775 {
 776         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 777 }
 778
 779 static inline bool cpu_has_vmx_ept_1g_page(void)
 780 {
 781         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 782 }
 783
 784 static inline bool cpu_has_vmx_ept_4levels(void)
 785 {
 786         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 787 }
 788
 789 static inline bool cpu_has_vmx_invept_individual_addr(void)
 790 {
 791         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 792 }
 793
 794 static inline bool cpu_has_vmx_invept_context(void)
 795 {
 796         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 797 }
 798
 799 static inline bool cpu_has_vmx_invept_global(void)
 800 {
 801         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 802 }
 803
 804 static inline bool cpu_has_vmx_invvpid_single(void)
 805 {
 806         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 807 }
 808
 809 static inline bool cpu_has_vmx_invvpid_global(void)
 810 {
 811         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 812 }
 813
 814 static inline bool cpu_has_vmx_ept(void)
 815 {
 816         return vmcs_config.cpu_based_2nd_exec_ctrl &
 817                 SECONDARY_EXEC_ENABLE_EPT;
 818 }
 819
 820 static inline bool cpu_has_vmx_unrestricted_guest(void)
 821 {
 822         return vmcs_config.cpu_based_2nd_exec_ctrl &
 823                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 824 }
 825
 826 static inline bool cpu_has_vmx_ple(void)
 827 {
 828         return vmcs_config.cpu_based_2nd_exec_ctrl &
 829                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 830 }
 831
 832 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 833 {
 834         return flexpriority_enabled && irqchip_in_kernel(kvm);
 835 }
 836
 837 static inline bool cpu_has_vmx_vpid(void)
 838 {
 839         return vmcs_config.cpu_based_2nd_exec_ctrl &
 840                 SECONDARY_EXEC_ENABLE_VPID;
 841 }
 842
 843 static inline bool cpu_has_vmx_rdtscp(void)
 844 {
 845         return vmcs_config.cpu_based_2nd_exec_ctrl &
 846                 SECONDARY_EXEC_RDTSCP;
 847 }
 848
 849 static inline bool cpu_has_virtual_nmis(void)
 850 {
 851         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 852 }
 853
 854 static inline bool cpu_has_vmx_wbinvd_exit(void)
 855 {
 856         return vmcs_config.cpu_based_2nd_exec_ctrl &
 857                 SECONDARY_EXEC_WBINVD_EXITING;
 858 }
 859
 860 static inline bool report_flexpriority(void)
 861 {
 862         return flexpriority_enabled;
 863 }
 864
 865 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 866 {
 867         return vmcs12->cpu_based_vm_exec_control & bit;
 868 }
 869
 870 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 871 {
 872         return (vmcs12->cpu_based_vm_exec_control &
 873                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 874                 (vmcs12->secondary_vm_exec_control & bit);
 875 }
 876
 877 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 878         struct kvm_vcpu *vcpu)
 879 {
 880         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 881 }
 882
 883 static inline bool is_exception(u32 intr_info)
 884 {
 885         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 886                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 887 }
 888
 889 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 890 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 891                         struct vmcs12 *vmcs12,
 892                         u32 reason, unsigned long qualification);
 893
 894 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 895 {
 896         int i;
 897
 898         for (i = 0; i < vmx->nmsrs; ++i)
 899                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 900                         return i;
 901         return -1;
 902 }
 903
 904 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 905 {
 906     struct {
 907         u64 vpid : 16;
 908         u64 rsvd : 48;
 909         u64 gva;
 910     } operand = { vpid, 0, gva };
 911
 912     asm volatile (__ex(ASM_VMX_INVVPID)
 913                   /* CF==1 or ZF==1 --> rc = -1 */
 914                   "; ja 1f ; ud2 ; 1:"
 915                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 916 }
 917
 918 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 919 {
 920         struct {
 921                 u64 eptp, gpa;
 922         } operand = {eptp, gpa};
 923
 924         asm volatile (__ex(ASM_VMX_INVEPT)
 925                         /* CF==1 or ZF==1 --> rc = -1 */
 926                         "; ja 1f ; ud2 ; 1:\n"
 927                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 928 }
 929
 930 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 931 {
 932         int i;
 933
 934         i = __find_msr_index(vmx, msr);
 935         if (i >= 0)
 936                 return &vmx->guest_msrs[i];
 937         return NULL;
 938 }
 939
 940 static void vmcs_clear(struct vmcs *vmcs)
 941 {
 942         u64 phys_addr = __pa(vmcs);
 943         u8 error;
 944
 945         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 946                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 947                       : "cc", "memory");
 948         if (error)
 949                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 950                        vmcs, phys_addr);
 951 }
 952
 953 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 954 {
 955         vmcs_clear(loaded_vmcs->vmcs);
 956         loaded_vmcs->cpu = -1;
 957         loaded_vmcs->launched = 0;
 958 }
 959
 960 static void vmcs_load(struct vmcs *vmcs)
 961 {
 962         u64 phys_addr = __pa(vmcs);
 963         u8 error;
 964
 965         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 966                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 967                         : "cc", "memory");
 968         if (error)
 969                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 970                        vmcs, phys_addr);
 971 }
 972
 973 static void __loaded_vmcs_clear(void *arg)
 974 {
 975         struct loaded_vmcs *loaded_vmcs = arg;
 976         int cpu = raw_smp_processor_id();
 977
 978         if (loaded_vmcs->cpu != cpu)
 979                 return; /* vcpu migration can race with cpu offline */
 980         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 981                 per_cpu(current_vmcs, cpu) = NULL;
 982         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 983         loaded_vmcs_init(loaded_vmcs);
 984 }
 985
 986 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 987 {
 988         if (loaded_vmcs->cpu != -1)
 989                 smp_call_function_single(
 990                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 991 }
 992
 993 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 994 {
 995         if (vmx->vpid == 0)
 996                 return;
 997
 998         if (cpu_has_vmx_invvpid_single())
 999                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1000 }
1001
1002 static inline void vpid_sync_vcpu_global(void)
1003 {
1004         if (cpu_has_vmx_invvpid_global())
1005                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1006 }
1007
1008 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1009 {
1010         if (cpu_has_vmx_invvpid_single())
1011                 vpid_sync_vcpu_single(vmx);
1012         else
1013                 vpid_sync_vcpu_global();
1014 }
1015
1016 static inline void ept_sync_global(void)
1017 {
1018         if (cpu_has_vmx_invept_global())
1019                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1020 }
1021
1022 static inline void ept_sync_context(u64 eptp)
1023 {
1024         if (enable_ept) {
1025                 if (cpu_has_vmx_invept_context())
1026                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1027                 else
1028                         ept_sync_global();
1029         }
1030 }
1031
1032 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1033 {
1034         if (enable_ept) {
1035                 if (cpu_has_vmx_invept_individual_addr())
1036                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1037                                         eptp, gpa);
1038                 else
1039                         ept_sync_context(eptp);
1040         }
1041 }
1042
1043 static __always_inline unsigned long vmcs_readl(unsigned long field)
1044 {
1045         unsigned long value;
1046
1047         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1048                       : "=a"(value) : "d"(field) : "cc");
1049         return value;
1050 }
1051
1052 static __always_inline u16 vmcs_read16(unsigned long field)
1053 {
1054         return vmcs_readl(field);
1055 }
1056
1057 static __always_inline u32 vmcs_read32(unsigned long field)
1058 {
1059         return vmcs_readl(field);
1060 }
1061
1062 static __always_inline u64 vmcs_read64(unsigned long field)
1063 {
1064 #ifdef CONFIG_X86_64
1065         return vmcs_readl(field);
1066 #else
1067         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1068 #endif
1069 }
1070
1071 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1072 {
1073         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1074                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1075         dump_stack();
1076 }
1077
1078 static void vmcs_writel(unsigned long field, unsigned long value)
1079 {
1080         u8 error;
1081
1082         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1083                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1084         if (unlikely(error))
1085                 vmwrite_error(field, value);
1086 }
1087
1088 static void vmcs_write16(unsigned long field, u16 value)
1089 {
1090         vmcs_writel(field, value);
1091 }
1092
1093 static void vmcs_write32(unsigned long field, u32 value)
1094 {
1095         vmcs_writel(field, value);
1096 }
1097
1098 static void vmcs_write64(unsigned long field, u64 value)
1099 {
1100         vmcs_writel(field, value);
1101 #ifndef CONFIG_X86_64
1102         asm volatile ("");
1103         vmcs_writel(field+1, value >> 32);
1104 #endif
1105 }
1106
1107 static void vmcs_clear_bits(unsigned long field, u32 mask)
1108 {
1109         vmcs_writel(field, vmcs_readl(field) & ~mask);
1110 }
1111
1112 static void vmcs_set_bits(unsigned long field, u32 mask)
1113 {
1114         vmcs_writel(field, vmcs_readl(field) | mask);
1115 }
1116
1117 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1118 {
1119         vmx->segment_cache.bitmask = 0;
1120 }
1121
1122 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1123                                        unsigned field)
1124 {
1125         bool ret;
1126         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1127
1128         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1129                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1130                 vmx->segment_cache.bitmask = 0;
1131         }
1132         ret = vmx->segment_cache.bitmask & mask;
1133         vmx->segment_cache.bitmask |= mask;
1134         return ret;
1135 }
1136
1137 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1138 {
1139         u16 *p = &vmx->segment_cache.seg[seg].selector;
1140
1141         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1142                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1143         return *p;
1144 }
1145
1146 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1147 {
1148         ulong *p = &vmx->segment_cache.seg[seg].base;
1149
1150         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1151                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1152         return *p;
1153 }
1154
1155 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1156 {
1157         u32 *p = &vmx->segment_cache.seg[seg].limit;
1158
1159         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1160                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1161         return *p;
1162 }
1163
1164 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1165 {
1166         u32 *p = &vmx->segment_cache.seg[seg].ar;
1167
1168         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1169                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1170         return *p;
1171 }
1172
1173 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1174 {
1175         u32 eb;
1176
1177         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1178              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1179         if ((vcpu->guest_debug &
1180              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1181             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1182                 eb |= 1u << BP_VECTOR;
1183         if (to_vmx(vcpu)->rmode.vm86_active)
1184                 eb = ~0;
1185         if (enable_ept)
1186                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1187         if (vcpu->fpu_active)
1188                 eb &= ~(1u << NM_VECTOR);
1189
1190         /* When we are running a nested L2 guest and L1 specified for it a
1191          * certain exception bitmap, we must trap the same exceptions and pass
1192          * them to L1. When running L2, we will only handle the exceptions
1193          * specified above if L1 did not want them.
1194          */
1195         if (is_guest_mode(vcpu))
1196                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1197
1198         vmcs_write32(EXCEPTION_BITMAP, eb);
1199 }
1200
1201 static void clear_atomic_switch_msr_special(unsigned long entry,
1202                 unsigned long exit)
1203 {
1204         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1205         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1206 }
1207
1208 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1209 {
1210         unsigned i;
1211         struct msr_autoload *m = &vmx->msr_autoload;
1212
1213         switch (msr) {
1214         case MSR_EFER:
1215                 if (cpu_has_load_ia32_efer) {
1216                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1217                                         VM_EXIT_LOAD_IA32_EFER);
1218                         return;
1219                 }
1220                 break;
1221         case MSR_CORE_PERF_GLOBAL_CTRL:
1222                 if (cpu_has_load_perf_global_ctrl) {
1223                         clear_atomic_switch_msr_special(
1224                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1225                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1226                         return;
1227                 }
1228                 break;
1229         }
1230
1231         for (i = 0; i < m->nr; ++i)
1232                 if (m->guest[i].index == msr)
1233                         break;
1234
1235         if (i == m->nr)
1236                 return;
1237         --m->nr;
1238         m->guest[i] = m->guest[m->nr];
1239         m->host[i] = m->host[m->nr];
1240         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1241         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1242 }
1243
1244 static void add_atomic_switch_msr_special(unsigned long entry,
1245                 unsigned long exit, unsigned long guest_val_vmcs,
1246                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1247 {
1248         vmcs_write64(guest_val_vmcs, guest_val);
1249         vmcs_write64(host_val_vmcs, host_val);
1250         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1251         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1252 }
1253
1254 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1255                                   u64 guest_val, u64 host_val)
1256 {
1257         unsigned i;
1258         struct msr_autoload *m = &vmx->msr_autoload;
1259
1260         switch (msr) {
1261         case MSR_EFER:
1262                 if (cpu_has_load_ia32_efer) {
1263                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1264                                         VM_EXIT_LOAD_IA32_EFER,
1265                                         GUEST_IA32_EFER,
1266                                         HOST_IA32_EFER,
1267                                         guest_val, host_val);
1268                         return;
1269                 }
1270                 break;
1271         case MSR_CORE_PERF_GLOBAL_CTRL:
1272                 if (cpu_has_load_perf_global_ctrl) {
1273                         add_atomic_switch_msr_special(
1274                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1275                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1276                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1277                                         HOST_IA32_PERF_GLOBAL_CTRL,
1278                                         guest_val, host_val);
1279                         return;
1280                 }
1281                 break;
1282         }
1283
1284         for (i = 0; i < m->nr; ++i)
1285                 if (m->guest[i].index == msr)
1286                         break;
1287
1288         if (i == NR_AUTOLOAD_MSRS) {
1289                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1290                                 "Can't add msr %x\n", msr);
1291                 return;
1292         } else if (i == m->nr) {
1293                 ++m->nr;
1294                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1295                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1296         }
1297
1298         m->guest[i].index = msr;
1299         m->guest[i].value = guest_val;
1300         m->host[i].index = msr;
1301         m->host[i].value = host_val;
1302 }
1303
1304 static void reload_tss(void)
1305 {
1306         /*
1307          * VT restores TR but not its size.  Useless.
1308          */
1309         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1310         struct desc_struct *descs;
1311
1312         descs = (void *)gdt->address;
1313         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1314         load_TR_desc();
1315 }
1316
1317 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1318 {
1319         u64 guest_efer;
1320         u64 ignore_bits;
1321
1322         guest_efer = vmx->vcpu.arch.efer;
1323
1324         /*
1325          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1326          * outside long mode
1327          */
1328         ignore_bits = EFER_NX | EFER_SCE;
1329 #ifdef CONFIG_X86_64
1330         ignore_bits |= EFER_LMA | EFER_LME;
1331         /* SCE is meaningful only in long mode on Intel */
1332         if (guest_efer & EFER_LMA)
1333                 ignore_bits &= ~(u64)EFER_SCE;
1334 #endif
1335         guest_efer &= ~ignore_bits;
1336         guest_efer |= host_efer & ignore_bits;
1337         vmx->guest_msrs[efer_offset].data = guest_efer;
1338         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1339
1340         clear_atomic_switch_msr(vmx, MSR_EFER);
1341         /* On ept, can't emulate nx, and must switch nx atomically */
1342         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1343                 guest_efer = vmx->vcpu.arch.efer;
1344                 if (!(guest_efer & EFER_LMA))
1345                         guest_efer &= ~EFER_LME;
1346                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1347                 return false;
1348         }
1349
1350         return true;
1351 }
1352
1353 static unsigned long segment_base(u16 selector)
1354 {
1355         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1356         struct desc_struct *d;
1357         unsigned long table_base;
1358         unsigned long v;
1359
1360         if (!(selector & ~3))
1361                 return 0;
1362
1363         table_base = gdt->address;
1364
1365         if (selector & 4) {           /* from ldt */
1366                 u16 ldt_selector = kvm_read_ldt();
1367
1368                 if (!(ldt_selector & ~3))
1369                         return 0;
1370
1371                 table_base = segment_base(ldt_selector);
1372         }
1373         d = (struct desc_struct *)(table_base + (selector & ~7));
1374         v = get_desc_base(d);
1375 #ifdef CONFIG_X86_64
1376        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1377                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1378 #endif
1379         return v;
1380 }
1381
1382 static inline unsigned long kvm_read_tr_base(void)
1383 {
1384         u16 tr;
1385         asm("str %0" : "=g"(tr));
1386         return segment_base(tr);
1387 }
1388
1389 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1390 {
1391         struct vcpu_vmx *vmx = to_vmx(vcpu);
1392         int i;
1393
1394         if (vmx->host_state.loaded)
1395                 return;
1396
1397         vmx->host_state.loaded = 1;
1398         /*
1399          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1400          * allow segment selectors with cpl > 0 or ti == 1.
1401          */
1402         vmx->host_state.ldt_sel = kvm_read_ldt();
1403         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1404         savesegment(fs, vmx->host_state.fs_sel);
1405         if (!(vmx->host_state.fs_sel & 7)) {
1406                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1407                 vmx->host_state.fs_reload_needed = 0;
1408         } else {
1409                 vmcs_write16(HOST_FS_SELECTOR, 0);
1410                 vmx->host_state.fs_reload_needed = 1;
1411         }
1412         savesegment(gs, vmx->host_state.gs_sel);
1413         if (!(vmx->host_state.gs_sel & 7))
1414                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1415         else {
1416                 vmcs_write16(HOST_GS_SELECTOR, 0);
1417                 vmx->host_state.gs_ldt_reload_needed = 1;
1418         }
1419
1420 #ifdef CONFIG_X86_64
1421         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1422         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1423 #else
1424         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1425         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1426 #endif
1427
1428 #ifdef CONFIG_X86_64
1429         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1430         if (is_long_mode(&vmx->vcpu))
1431                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1432 #endif
1433         for (i = 0; i < vmx->save_nmsrs; ++i)
1434                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1435                                    vmx->guest_msrs[i].data,
1436                                    vmx->guest_msrs[i].mask);
1437 }
1438
1439 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1440 {
1441         if (!vmx->host_state.loaded)
1442                 return;
1443
1444         ++vmx->vcpu.stat.host_state_reload;
1445         vmx->host_state.loaded = 0;
1446 #ifdef CONFIG_X86_64
1447         if (is_long_mode(&vmx->vcpu))
1448                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1449 #endif
1450         if (vmx->host_state.gs_ldt_reload_needed) {
1451                 kvm_load_ldt(vmx->host_state.ldt_sel);
1452 #ifdef CONFIG_X86_64
1453                 load_gs_index(vmx->host_state.gs_sel);
1454 #else
1455                 loadsegment(gs, vmx->host_state.gs_sel);
1456 #endif
1457         }
1458         if (vmx->host_state.fs_reload_needed)
1459                 loadsegment(fs, vmx->host_state.fs_sel);
1460         reload_tss();
1461 #ifdef CONFIG_X86_64
1462         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1463 #endif
1464         if (user_has_fpu())
1465                 clts();
1466         load_gdt(&__get_cpu_var(host_gdt));
1467 }
1468
1469 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1470 {
1471         preempt_disable();
1472         __vmx_load_host_state(vmx);
1473         preempt_enable();
1474 }
1475
1476 /*
1477  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1478  * vcpu mutex is already taken.
1479  */
1480 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1481 {
1482         struct vcpu_vmx *vmx = to_vmx(vcpu);
1483         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1484
1485         if (!vmm_exclusive)
1486                 kvm_cpu_vmxon(phys_addr);
1487         else if (vmx->loaded_vmcs->cpu != cpu)
1488                 loaded_vmcs_clear(vmx->loaded_vmcs);
1489
1490         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1491                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1492                 vmcs_load(vmx->loaded_vmcs->vmcs);
1493         }
1494
1495         if (vmx->loaded_vmcs->cpu != cpu) {
1496                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1497                 unsigned long sysenter_esp;
1498
1499                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1500                 local_irq_disable();
1501                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1502                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1503                 local_irq_enable();
1504
1505                 /*
1506                  * Linux uses per-cpu TSS and GDT, so set these when switching
1507                  * processors.
1508                  */
1509                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1510                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1511
1512                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1513                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1514                 vmx->loaded_vmcs->cpu = cpu;
1515         }
1516 }
1517
1518 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1519 {
1520         __vmx_load_host_state(to_vmx(vcpu));
1521         if (!vmm_exclusive) {
1522                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1523                 vcpu->cpu = -1;
1524                 kvm_cpu_vmxoff();
1525         }
1526 }
1527
1528 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1529 {
1530         ulong cr0;
1531
1532         if (vcpu->fpu_active)
1533                 return;
1534         vcpu->fpu_active = 1;
1535         cr0 = vmcs_readl(GUEST_CR0);
1536         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1537         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1538         vmcs_writel(GUEST_CR0, cr0);
1539         update_exception_bitmap(vcpu);
1540         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1541         if (is_guest_mode(vcpu))
1542                 vcpu->arch.cr0_guest_owned_bits &=
1543                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1544         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1545 }
1546
1547 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1548
1549 /*
1550  * Return the cr0 value that a nested guest would read. This is a combination
1551  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1552  * its hypervisor (cr0_read_shadow).
1553  */
1554 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1555 {
1556         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1557                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1558 }
1559 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1560 {
1561         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1562                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1563 }
1564
1565 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1566 {
1567         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1568          * set this *before* calling this function.
1569          */
1570         vmx_decache_cr0_guest_bits(vcpu);
1571         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1572         update_exception_bitmap(vcpu);
1573         vcpu->arch.cr0_guest_owned_bits = 0;
1574         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1575         if (is_guest_mode(vcpu)) {
1576                 /*
1577                  * L1's specified read shadow might not contain the TS bit,
1578                  * so now that we turned on shadowing of this bit, we need to
1579                  * set this bit of the shadow. Like in nested_vmx_run we need
1580                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1581                  * up-to-date here because we just decached cr0.TS (and we'll
1582                  * only update vmcs12->guest_cr0 on nested exit).
1583                  */
1584                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1585                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1586                         (vcpu->arch.cr0 & X86_CR0_TS);
1587                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1588         } else
1589                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1590 }
1591
1592 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1593 {
1594         unsigned long rflags, save_rflags;
1595
1596         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1597                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1598                 rflags = vmcs_readl(GUEST_RFLAGS);
1599                 if (to_vmx(vcpu)->rmode.vm86_active) {
1600                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1601                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1602                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1603                 }
1604                 to_vmx(vcpu)->rflags = rflags;
1605         }
1606         return to_vmx(vcpu)->rflags;
1607 }
1608
1609 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1610 {
1611         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1612         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1613         to_vmx(vcpu)->rflags = rflags;
1614         if (to_vmx(vcpu)->rmode.vm86_active) {
1615                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1616                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1617         }
1618         vmcs_writel(GUEST_RFLAGS, rflags);
1619 }
1620
1621 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1622 {
1623         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1624         int ret = 0;
1625
1626         if (interruptibility & GUEST_INTR_STATE_STI)
1627                 ret |= KVM_X86_SHADOW_INT_STI;
1628         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1629                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1630
1631         return ret & mask;
1632 }
1633
1634 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1635 {
1636         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1637         u32 interruptibility = interruptibility_old;
1638
1639         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1640
1641         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1642                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1643         else if (mask & KVM_X86_SHADOW_INT_STI)
1644                 interruptibility |= GUEST_INTR_STATE_STI;
1645
1646         if ((interruptibility != interruptibility_old))
1647                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1648 }
1649
1650 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1651 {
1652         unsigned long rip;
1653
1654         rip = kvm_rip_read(vcpu);
1655         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1656         kvm_rip_write(vcpu, rip);
1657
1658         /* skipping an emulated instruction also counts */
1659         vmx_set_interrupt_shadow(vcpu, 0);
1660 }
1661
1662 /*
1663  * KVM wants to inject page-faults which it got to the guest. This function
1664  * checks whether in a nested guest, we need to inject them to L1 or L2.
1665  * This function assumes it is called with the exit reason in vmcs02 being
1666  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1667  * is running).
1668  */
1669 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1670 {
1671         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1672
1673         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1674         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1675                 return 0;
1676
1677         nested_vmx_vmexit(vcpu);
1678         return 1;
1679 }
1680
1681 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1682                                 bool has_error_code, u32 error_code,
1683                                 bool reinject)
1684 {
1685         struct vcpu_vmx *vmx = to_vmx(vcpu);
1686         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1687
1688         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1689                 nested_pf_handled(vcpu))
1690                 return;
1691
1692         if (has_error_code) {
1693                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1694                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1695         }
1696
1697         if (vmx->rmode.vm86_active) {
1698                 int inc_eip = 0;
1699                 if (kvm_exception_is_soft(nr))
1700                         inc_eip = vcpu->arch.event_exit_inst_len;
1701                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1702                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1703                 return;
1704         }
1705
1706         if (kvm_exception_is_soft(nr)) {
1707                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1708                              vmx->vcpu.arch.event_exit_inst_len);
1709                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1710         } else
1711                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1712
1713         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1714 }
1715
1716 static bool vmx_rdtscp_supported(void)
1717 {
1718         return cpu_has_vmx_rdtscp();
1719 }
1720
1721 /*
1722  * Swap MSR entry in host/guest MSR entry array.
1723  */
1724 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1725 {
1726         struct shared_msr_entry tmp;
1727
1728         tmp = vmx->guest_msrs[to];
1729         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1730         vmx->guest_msrs[from] = tmp;
1731 }
1732
1733 /*
1734  * Set up the vmcs to automatically save and restore system
1735  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1736  * mode, as fiddling with msrs is very expensive.
1737  */
1738 static void setup_msrs(struct vcpu_vmx *vmx)
1739 {
1740         int save_nmsrs, index;
1741         unsigned long *msr_bitmap;
1742
1743         save_nmsrs = 0;
1744 #ifdef CONFIG_X86_64
1745         if (is_long_mode(&vmx->vcpu)) {
1746                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1747                 if (index >= 0)
1748                         move_msr_up(vmx, index, save_nmsrs++);
1749                 index = __find_msr_index(vmx, MSR_LSTAR);
1750                 if (index >= 0)
1751                         move_msr_up(vmx, index, save_nmsrs++);
1752                 index = __find_msr_index(vmx, MSR_CSTAR);
1753                 if (index >= 0)
1754                         move_msr_up(vmx, index, save_nmsrs++);
1755                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1756                 if (index >= 0 && vmx->rdtscp_enabled)
1757                         move_msr_up(vmx, index, save_nmsrs++);
1758                 /*
1759                  * MSR_STAR is only needed on long mode guests, and only
1760                  * if efer.sce is enabled.
1761                  */
1762                 index = __find_msr_index(vmx, MSR_STAR);
1763                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1764                         move_msr_up(vmx, index, save_nmsrs++);
1765         }
1766 #endif
1767         index = __find_msr_index(vmx, MSR_EFER);
1768         if (index >= 0 && update_transition_efer(vmx, index))
1769                 move_msr_up(vmx, index, save_nmsrs++);
1770
1771         vmx->save_nmsrs = save_nmsrs;
1772
1773         if (cpu_has_vmx_msr_bitmap()) {
1774                 if (is_long_mode(&vmx->vcpu))
1775                         msr_bitmap = vmx_msr_bitmap_longmode;
1776                 else
1777                         msr_bitmap = vmx_msr_bitmap_legacy;
1778
1779                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1780         }
1781 }
1782
1783 /*
1784  * reads and returns guest's timestamp counter "register"
1785  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1786  */
1787 static u64 guest_read_tsc(void)
1788 {
1789         u64 host_tsc, tsc_offset;
1790
1791         rdtscll(host_tsc);
1792         tsc_offset = vmcs_read64(TSC_OFFSET);
1793         return host_tsc + tsc_offset;
1794 }
1795
1796 /*
1797  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1798  * counter, even if a nested guest (L2) is currently running.
1799  */
1800 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1801 {
1802         u64 host_tsc, tsc_offset;
1803
1804         rdtscll(host_tsc);
1805         tsc_offset = is_guest_mode(vcpu) ?
1806                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1807                 vmcs_read64(TSC_OFFSET);
1808         return host_tsc + tsc_offset;
1809 }
1810
1811 /*
1812  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1813  * software catchup for faster rates on slower CPUs.
1814  */
1815 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1816 {
1817         if (!scale)
1818                 return;
1819
1820         if (user_tsc_khz > tsc_khz) {
1821                 vcpu->arch.tsc_catchup = 1;
1822                 vcpu->arch.tsc_always_catchup = 1;
1823         } else
1824                 WARN(1, "user requested TSC rate below hardware speed\n");
1825 }
1826
1827 /*
1828  * writes 'offset' into guest's timestamp counter offset register
1829  */
1830 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1831 {
1832         if (is_guest_mode(vcpu)) {
1833                 /*
1834                  * We're here if L1 chose not to trap WRMSR to TSC. According
1835                  * to the spec, this should set L1's TSC; The offset that L1
1836                  * set for L2 remains unchanged, and still needs to be added
1837                  * to the newly set TSC to get L2's TSC.
1838                  */
1839                 struct vmcs12 *vmcs12;
1840                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1841                 /* recalculate vmcs02.TSC_OFFSET: */
1842                 vmcs12 = get_vmcs12(vcpu);
1843                 vmcs_write64(TSC_OFFSET, offset +
1844                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1845                          vmcs12->tsc_offset : 0));
1846         } else {
1847                 vmcs_write64(TSC_OFFSET, offset);
1848         }
1849 }
1850
1851 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1852 {
1853         u64 offset = vmcs_read64(TSC_OFFSET);
1854         vmcs_write64(TSC_OFFSET, offset + adjustment);
1855         if (is_guest_mode(vcpu)) {
1856                 /* Even when running L2, the adjustment needs to apply to L1 */
1857                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1858         }
1859 }
1860
1861 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1862 {
1863         return target_tsc - native_read_tsc();
1864 }
1865
1866 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1867 {
1868         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1869         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1870 }
1871
1872 /*
1873  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1874  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1875  * all guests if the "nested" module option is off, and can also be disabled
1876  * for a single guest by disabling its VMX cpuid bit.
1877  */
1878 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1879 {
1880         return nested && guest_cpuid_has_vmx(vcpu);
1881 }
1882
1883 /*
1884  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1885  * returned for the various VMX controls MSRs when nested VMX is enabled.
1886  * The same values should also be used to verify that vmcs12 control fields are
1887  * valid during nested entry from L1 to L2.
1888  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1889  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1890  * bit in the high half is on if the corresponding bit in the control field
1891  * may be on. See also vmx_control_verify().
1892  * TODO: allow these variables to be modified (downgraded) by module options
1893  * or other means.
1894  */
1895 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1896 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1897 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1898 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1899 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1900 static __init void nested_vmx_setup_ctls_msrs(void)
1901 {
1902         /*
1903          * Note that as a general rule, the high half of the MSRs (bits in
1904          * the control fields which may be 1) should be initialized by the
1905          * intersection of the underlying hardware's MSR (i.e., features which
1906          * can be supported) and the list of features we want to expose -
1907          * because they are known to be properly supported in our code.
1908          * Also, usually, the low half of the MSRs (bits which must be 1) can
1909          * be set to 0, meaning that L1 may turn off any of these bits. The
1910          * reason is that if one of these bits is necessary, it will appear
1911          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1912          * fields of vmcs01 and vmcs02, will turn these bits off - and
1913          * nested_vmx_exit_handled() will not pass related exits to L1.
1914          * These rules have exceptions below.
1915          */
1916
1917         /* pin-based controls */
1918         /*
1919          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1920          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1921          */
1922         nested_vmx_pinbased_ctls_low = 0x16 ;
1923         nested_vmx_pinbased_ctls_high = 0x16 |
1924                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1925                 PIN_BASED_VIRTUAL_NMIS;
1926
1927         /* exit controls */
1928         nested_vmx_exit_ctls_low = 0;
1929         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1930 #ifdef CONFIG_X86_64
1931         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1932 #else
1933         nested_vmx_exit_ctls_high = 0;
1934 #endif
1935
1936         /* entry controls */
1937         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1938                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1939         nested_vmx_entry_ctls_low = 0;
1940         nested_vmx_entry_ctls_high &=
1941                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1942
1943         /* cpu-based controls */
1944         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1945                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1946         nested_vmx_procbased_ctls_low = 0;
1947         nested_vmx_procbased_ctls_high &=
1948                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1949                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1950                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1951                 CPU_BASED_CR3_STORE_EXITING |
1952 #ifdef CONFIG_X86_64
1953                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1954 #endif
1955                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1956                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1957                 CPU_BASED_RDPMC_EXITING |
1958                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1959         /*
1960          * We can allow some features even when not supported by the
1961          * hardware. For example, L1 can specify an MSR bitmap - and we
1962          * can use it to avoid exits to L1 - even when L0 runs L2
1963          * without MSR bitmaps.
1964          */
1965         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1966
1967         /* secondary cpu-based controls */
1968         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1969                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1970         nested_vmx_secondary_ctls_low = 0;
1971         nested_vmx_secondary_ctls_high &=
1972                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1973 }
1974
1975 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1976 {
1977         /*
1978          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1979          */
1980         return ((control & high) | low) == control;
1981 }
1982
1983 static inline u64 vmx_control_msr(u32 low, u32 high)
1984 {
1985         return low | ((u64)high << 32);
1986 }
1987
1988 /*
1989  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1990  * also let it use VMX-specific MSRs.
1991  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1992  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1993  * like all other MSRs).
1994  */
1995 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1996 {
1997         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1998                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1999                 /*
2000                  * According to the spec, processors which do not support VMX
2001                  * should throw a #GP(0) when VMX capability MSRs are read.
2002                  */
2003                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2004                 return 1;
2005         }
2006
2007         switch (msr_index) {
2008         case MSR_IA32_FEATURE_CONTROL:
2009                 *pdata = 0;
2010                 break;
2011         case MSR_IA32_VMX_BASIC:
2012                 /*
2013                  * This MSR reports some information about VMX support. We
2014                  * should return information about the VMX we emulate for the
2015                  * guest, and the VMCS structure we give it - not about the
2016                  * VMX support of the underlying hardware.
2017                  */
2018                 *pdata = VMCS12_REVISION |
2019                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2020                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2021                 break;
2022         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2023         case MSR_IA32_VMX_PINBASED_CTLS:
2024                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2025                                         nested_vmx_pinbased_ctls_high);
2026                 break;
2027         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2028         case MSR_IA32_VMX_PROCBASED_CTLS:
2029                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2030                                         nested_vmx_procbased_ctls_high);
2031                 break;
2032         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2033         case MSR_IA32_VMX_EXIT_CTLS:
2034                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2035                                         nested_vmx_exit_ctls_high);
2036                 break;
2037         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2038         case MSR_IA32_VMX_ENTRY_CTLS:
2039                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2040                                         nested_vmx_entry_ctls_high);
2041                 break;
2042         case MSR_IA32_VMX_MISC:
2043                 *pdata = 0;
2044                 break;
2045         /*
2046          * These MSRs specify bits which the guest must keep fixed (on or off)
2047          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2048          * We picked the standard core2 setting.
2049          */
2050 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2051 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2052         case MSR_IA32_VMX_CR0_FIXED0:
2053                 *pdata = VMXON_CR0_ALWAYSON;
2054                 break;
2055         case MSR_IA32_VMX_CR0_FIXED1:
2056                 *pdata = -1ULL;
2057                 break;
2058         case MSR_IA32_VMX_CR4_FIXED0:
2059                 *pdata = VMXON_CR4_ALWAYSON;
2060                 break;
2061         case MSR_IA32_VMX_CR4_FIXED1:
2062                 *pdata = -1ULL;
2063                 break;
2064         case MSR_IA32_VMX_VMCS_ENUM:
2065                 *pdata = 0x1f;
2066                 break;
2067         case MSR_IA32_VMX_PROCBASED_CTLS2:
2068                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2069                                         nested_vmx_secondary_ctls_high);
2070                 break;
2071         case MSR_IA32_VMX_EPT_VPID_CAP:
2072                 /* Currently, no nested ept or nested vpid */
2073                 *pdata = 0;
2074                 break;
2075         default:
2076                 return 0;
2077         }
2078
2079         return 1;
2080 }
2081
2082 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2083 {
2084         if (!nested_vmx_allowed(vcpu))
2085                 return 0;
2086
2087         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2088                 /* TODO: the right thing. */
2089                 return 1;
2090         /*
2091          * No need to treat VMX capability MSRs specially: If we don't handle
2092          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2093          */
2094         return 0;
2095 }
2096
2097 /*
2098  * Reads an msr value (of 'msr_index') into 'pdata'.
2099  * Returns 0 on success, non-0 otherwise.
2100  * Assumes vcpu_load() was already called.
2101  */
2102 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2103 {
2104         u64 data;
2105         struct shared_msr_entry *msr;
2106
2107         if (!pdata) {
2108                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2109                 return -EINVAL;
2110         }
2111
2112         switch (msr_index) {
2113 #ifdef CONFIG_X86_64
2114         case MSR_FS_BASE:
2115                 data = vmcs_readl(GUEST_FS_BASE);
2116                 break;
2117         case MSR_GS_BASE:
2118                 data = vmcs_readl(GUEST_GS_BASE);
2119                 break;
2120         case MSR_KERNEL_GS_BASE:
2121                 vmx_load_host_state(to_vmx(vcpu));
2122                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2123                 break;
2124 #endif
2125         case MSR_EFER:
2126                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2127         case MSR_IA32_TSC:
2128                 data = guest_read_tsc();
2129                 break;
2130         case MSR_IA32_SYSENTER_CS:
2131                 data = vmcs_read32(GUEST_SYSENTER_CS);
2132                 break;
2133         case MSR_IA32_SYSENTER_EIP:
2134                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2135                 break;
2136         case MSR_IA32_SYSENTER_ESP:
2137                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2138                 break;
2139         case MSR_TSC_AUX:
2140                 if (!to_vmx(vcpu)->rdtscp_enabled)
2141                         return 1;
2142                 /* Otherwise falls through */
2143         default:
2144                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2145                         return 0;
2146                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2147                 if (msr) {
2148                         data = msr->data;
2149                         break;
2150                 }
2151                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2152         }
2153
2154         *pdata = data;
2155         return 0;
2156 }
2157
2158 /*
2159  * Writes msr value into into the appropriate "register".
2160  * Returns 0 on success, non-0 otherwise.
2161  * Assumes vcpu_load() was already called.
2162  */
2163 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2164 {
2165         struct vcpu_vmx *vmx = to_vmx(vcpu);
2166         struct shared_msr_entry *msr;
2167         int ret = 0;
2168
2169         switch (msr_index) {
2170         case MSR_EFER:
2171                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2172                 break;
2173 #ifdef CONFIG_X86_64
2174         case MSR_FS_BASE:
2175                 vmx_segment_cache_clear(vmx);
2176                 vmcs_writel(GUEST_FS_BASE, data);
2177                 break;
2178         case MSR_GS_BASE:
2179                 vmx_segment_cache_clear(vmx);
2180                 vmcs_writel(GUEST_GS_BASE, data);
2181                 break;
2182         case MSR_KERNEL_GS_BASE:
2183                 vmx_load_host_state(vmx);
2184                 vmx->msr_guest_kernel_gs_base = data;
2185                 break;
2186 #endif
2187         case MSR_IA32_SYSENTER_CS:
2188                 vmcs_write32(GUEST_SYSENTER_CS, data);
2189                 break;
2190         case MSR_IA32_SYSENTER_EIP:
2191                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2192                 break;
2193         case MSR_IA32_SYSENTER_ESP:
2194                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2195                 break;
2196         case MSR_IA32_TSC:
2197                 kvm_write_tsc(vcpu, data);
2198                 break;
2199         case MSR_IA32_CR_PAT:
2200                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2201                         vmcs_write64(GUEST_IA32_PAT, data);
2202                         vcpu->arch.pat = data;
2203                         break;
2204                 }
2205                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2206                 break;
2207         case MSR_TSC_AUX:
2208                 if (!vmx->rdtscp_enabled)
2209                         return 1;
2210                 /* Check reserved bit, higher 32 bits should be zero */
2211                 if ((data >> 32) != 0)
2212                         return 1;
2213                 /* Otherwise falls through */
2214         default:
2215                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2216                         break;
2217                 msr = find_msr_entry(vmx, msr_index);
2218                 if (msr) {
2219                         msr->data = data;
2220                         if (msr - vmx->guest_msrs < vmx->save_nmsrs)
2221                                 kvm_set_shared_msr(msr->index, msr->data,
2222                                                    msr->mask);
2223                         break;
2224                 }
2225                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2226         }
2227
2228         return ret;
2229 }
2230
2231 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2232 {
2233         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2234         switch (reg) {
2235         case VCPU_REGS_RSP:
2236                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2237                 break;
2238         case VCPU_REGS_RIP:
2239                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2240                 break;
2241         case VCPU_EXREG_PDPTR:
2242                 if (enable_ept)
2243                         ept_save_pdptrs(vcpu);
2244                 break;
2245         default:
2246                 break;
2247         }
2248 }
2249
2250 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2251 {
2252         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2253                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2254         else
2255                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2256
2257         update_exception_bitmap(vcpu);
2258 }
2259
2260 static __init int cpu_has_kvm_support(void)
2261 {
2262         return cpu_has_vmx();
2263 }
2264
2265 static __init int vmx_disabled_by_bios(void)
2266 {
2267         u64 msr;
2268
2269         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2270         if (msr & FEATURE_CONTROL_LOCKED) {
2271                 /* launched w/ TXT and VMX disabled */
2272                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2273                         && tboot_enabled())
2274                         return 1;
2275                 /* launched w/o TXT and VMX only enabled w/ TXT */
2276                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2277                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2278                         && !tboot_enabled()) {
2279                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2280                                 "activate TXT before enabling KVM\n");
2281                         return 1;
2282                 }
2283                 /* launched w/o TXT and VMX disabled */
2284                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2285                         && !tboot_enabled())
2286                         return 1;
2287         }
2288
2289         return 0;
2290 }
2291
2292 static void kvm_cpu_vmxon(u64 addr)
2293 {
2294         asm volatile (ASM_VMX_VMXON_RAX
2295                         : : "a"(&addr), "m"(addr)
2296                         : "memory", "cc");
2297 }
2298
2299 static int hardware_enable(void *garbage)
2300 {
2301         int cpu = raw_smp_processor_id();
2302         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2303         u64 old, test_bits;
2304
2305         if (read_cr4() & X86_CR4_VMXE)
2306                 return -EBUSY;
2307
2308         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2309         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2310
2311         test_bits = FEATURE_CONTROL_LOCKED;
2312         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2313         if (tboot_enabled())
2314                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2315
2316         if ((old & test_bits) != test_bits) {
2317                 /* enable and lock */
2318                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2319         }
2320         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2321
2322         if (vmm_exclusive) {
2323                 kvm_cpu_vmxon(phys_addr);
2324                 ept_sync_global();
2325         }
2326
2327         store_gdt(&__get_cpu_var(host_gdt));
2328
2329         return 0;
2330 }
2331
2332 static void vmclear_local_loaded_vmcss(void)
2333 {
2334         int cpu = raw_smp_processor_id();
2335         struct loaded_vmcs *v, *n;
2336
2337         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2338                                  loaded_vmcss_on_cpu_link)
2339                 __loaded_vmcs_clear(v);
2340 }
2341
2342
2343 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2344  * tricks.
2345  */
2346 static void kvm_cpu_vmxoff(void)
2347 {
2348         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2349 }
2350
2351 static void hardware_disable(void *garbage)
2352 {
2353         if (vmm_exclusive) {
2354                 vmclear_local_loaded_vmcss();
2355                 kvm_cpu_vmxoff();
2356         }
2357         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2358 }
2359
2360 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2361                                       u32 msr, u32 *result)
2362 {
2363         u32 vmx_msr_low, vmx_msr_high;
2364         u32 ctl = ctl_min | ctl_opt;
2365
2366         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2367
2368         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2369         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2370
2371         /* Ensure minimum (required) set of control bits are supported. */
2372         if (ctl_min & ~ctl)
2373                 return -EIO;
2374
2375         *result = ctl;
2376         return 0;
2377 }
2378
2379 static __init bool allow_1_setting(u32 msr, u32 ctl)
2380 {
2381         u32 vmx_msr_low, vmx_msr_high;
2382
2383         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2384         return vmx_msr_high & ctl;
2385 }
2386
2387 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2388 {
2389         u32 vmx_msr_low, vmx_msr_high;
2390         u32 min, opt, min2, opt2;
2391         u32 _pin_based_exec_control = 0;
2392         u32 _cpu_based_exec_control = 0;
2393         u32 _cpu_based_2nd_exec_control = 0;
2394         u32 _vmexit_control = 0;
2395         u32 _vmentry_control = 0;
2396
2397         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2398         opt = PIN_BASED_VIRTUAL_NMIS;
2399         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2400                                 &_pin_based_exec_control) < 0)
2401                 return -EIO;
2402
2403         min = CPU_BASED_HLT_EXITING |
2404 #ifdef CONFIG_X86_64
2405               CPU_BASED_CR8_LOAD_EXITING |
2406               CPU_BASED_CR8_STORE_EXITING |
2407 #endif
2408               CPU_BASED_CR3_LOAD_EXITING |
2409               CPU_BASED_CR3_STORE_EXITING |
2410               CPU_BASED_USE_IO_BITMAPS |
2411               CPU_BASED_MOV_DR_EXITING |
2412               CPU_BASED_USE_TSC_OFFSETING |
2413               CPU_BASED_MWAIT_EXITING |
2414               CPU_BASED_MONITOR_EXITING |
2415               CPU_BASED_INVLPG_EXITING |
2416               CPU_BASED_RDPMC_EXITING;
2417
2418         opt = CPU_BASED_TPR_SHADOW |
2419               CPU_BASED_USE_MSR_BITMAPS |
2420               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2421         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2422                                 &_cpu_based_exec_control) < 0)
2423                 return -EIO;
2424 #ifdef CONFIG_X86_64
2425         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2426                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2427                                            ~CPU_BASED_CR8_STORE_EXITING;
2428 #endif
2429         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2430                 min2 = 0;
2431                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2432                         SECONDARY_EXEC_WBINVD_EXITING |
2433                         SECONDARY_EXEC_ENABLE_VPID |
2434                         SECONDARY_EXEC_ENABLE_EPT |
2435                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2436                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2437                         SECONDARY_EXEC_RDTSCP;
2438                 if (adjust_vmx_controls(min2, opt2,
2439                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2440                                         &_cpu_based_2nd_exec_control) < 0)
2441                         return -EIO;
2442         }
2443 #ifndef CONFIG_X86_64
2444         if (!(_cpu_based_2nd_exec_control &
2445                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2446                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2447 #endif
2448         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2449                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2450                    enabled */
2451                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2452                                              CPU_BASED_CR3_STORE_EXITING |
2453                                              CPU_BASED_INVLPG_EXITING);
2454                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2455                       vmx_capability.ept, vmx_capability.vpid);
2456         }
2457
2458         min = 0;
2459 #ifdef CONFIG_X86_64
2460         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2461 #endif
2462         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2463         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2464                                 &_vmexit_control) < 0)
2465                 return -EIO;
2466
2467         min = 0;
2468         opt = VM_ENTRY_LOAD_IA32_PAT;
2469         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2470                                 &_vmentry_control) < 0)
2471                 return -EIO;
2472
2473         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2474
2475         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2476         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2477                 return -EIO;
2478
2479 #ifdef CONFIG_X86_64
2480         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2481         if (vmx_msr_high & (1u<<16))
2482                 return -EIO;
2483 #endif
2484
2485         /* Require Write-Back (WB) memory type for VMCS accesses. */
2486         if (((vmx_msr_high >> 18) & 15) != 6)
2487                 return -EIO;
2488
2489         vmcs_conf->size = vmx_msr_high & 0x1fff;
2490         vmcs_conf->order = get_order(vmcs_config.size);
2491         vmcs_conf->revision_id = vmx_msr_low;
2492
2493         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2494         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2495         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2496         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2497         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2498
2499         cpu_has_load_ia32_efer =
2500                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2501                                 VM_ENTRY_LOAD_IA32_EFER)
2502                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2503                                    VM_EXIT_LOAD_IA32_EFER);
2504
2505         cpu_has_load_perf_global_ctrl =
2506                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2507                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2508                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2509                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2510
2511         /*
2512          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2513          * but due to arrata below it can't be used. Workaround is to use
2514          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2515          *
2516          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2517          *
2518          * AAK155             (model 26)
2519          * AAP115             (model 30)
2520          * AAT100             (model 37)
2521          * BC86,AAY89,BD102   (model 44)
2522          * BA97               (model 46)
2523          *
2524          */
2525         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2526                 switch (boot_cpu_data.x86_model) {
2527                 case 26:
2528                 case 30:
2529                 case 37:
2530                 case 44:
2531                 case 46:
2532                         cpu_has_load_perf_global_ctrl = false;
2533                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2534                                         "does not work properly. Using workaround\n");
2535                         break;
2536                 default:
2537                         break;
2538                 }
2539         }
2540
2541         return 0;
2542 }
2543
2544 static struct vmcs *alloc_vmcs_cpu(int cpu)
2545 {
2546         int node = cpu_to_node(cpu);
2547         struct page *pages;
2548         struct vmcs *vmcs;
2549
2550         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2551         if (!pages)
2552                 return NULL;
2553         vmcs = page_address(pages);
2554         memset(vmcs, 0, vmcs_config.size);
2555         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2556         return vmcs;
2557 }
2558
2559 static struct vmcs *alloc_vmcs(void)
2560 {
2561         return alloc_vmcs_cpu(raw_smp_processor_id());
2562 }
2563
2564 static void free_vmcs(struct vmcs *vmcs)
2565 {
2566         free_pages((unsigned long)vmcs, vmcs_config.order);
2567 }
2568
2569 /*
2570  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2571  */
2572 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2573 {
2574         if (!loaded_vmcs->vmcs)
2575                 return;
2576         loaded_vmcs_clear(loaded_vmcs);
2577         free_vmcs(loaded_vmcs->vmcs);
2578         loaded_vmcs->vmcs = NULL;
2579 }
2580
2581 static void free_kvm_area(void)
2582 {
2583         int cpu;
2584
2585         for_each_possible_cpu(cpu) {
2586                 free_vmcs(per_cpu(vmxarea, cpu));
2587                 per_cpu(vmxarea, cpu) = NULL;
2588         }
2589 }
2590
2591 static __init int alloc_kvm_area(void)
2592 {
2593         int cpu;
2594
2595         for_each_possible_cpu(cpu) {
2596                 struct vmcs *vmcs;
2597
2598                 vmcs = alloc_vmcs_cpu(cpu);
2599                 if (!vmcs) {
2600                         free_kvm_area();
2601                         return -ENOMEM;
2602                 }
2603
2604                 per_cpu(vmxarea, cpu) = vmcs;
2605         }
2606         return 0;
2607 }
2608
2609 static __init int hardware_setup(void)
2610 {
2611         if (setup_vmcs_config(&vmcs_config) < 0)
2612                 return -EIO;
2613
2614         if (boot_cpu_has(X86_FEATURE_NX))
2615                 kvm_enable_efer_bits(EFER_NX);
2616
2617         if (!cpu_has_vmx_vpid())
2618                 enable_vpid = 0;
2619
2620         if (!cpu_has_vmx_ept() ||
2621             !cpu_has_vmx_ept_4levels()) {
2622                 enable_ept = 0;
2623                 enable_unrestricted_guest = 0;
2624         }
2625
2626         if (!cpu_has_vmx_unrestricted_guest())
2627                 enable_unrestricted_guest = 0;
2628
2629         if (!cpu_has_vmx_flexpriority())
2630                 flexpriority_enabled = 0;
2631
2632         if (!cpu_has_vmx_tpr_shadow())
2633                 kvm_x86_ops->update_cr8_intercept = NULL;
2634
2635         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2636                 kvm_disable_largepages();
2637
2638         if (!cpu_has_vmx_ple())
2639                 ple_gap = 0;
2640
2641         if (nested)
2642                 nested_vmx_setup_ctls_msrs();
2643
2644         return alloc_kvm_area();
2645 }
2646
2647 static __exit void hardware_unsetup(void)
2648 {
2649         free_kvm_area();
2650 }
2651
2652 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2653 {
2654         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2655
2656         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2657                 vmcs_write16(sf->selector, save->selector);
2658                 vmcs_writel(sf->base, save->base);
2659                 vmcs_write32(sf->limit, save->limit);
2660                 vmcs_write32(sf->ar_bytes, save->ar);
2661         } else {
2662                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2663                         << AR_DPL_SHIFT;
2664                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2665         }
2666 }
2667
2668 static void enter_pmode(struct kvm_vcpu *vcpu)
2669 {
2670         unsigned long flags;
2671         struct vcpu_vmx *vmx = to_vmx(vcpu);
2672
2673         vmx->emulation_required = 1;
2674         vmx->rmode.vm86_active = 0;
2675
2676         vmx_segment_cache_clear(vmx);
2677
2678         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2679         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2680         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2681         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2682
2683         flags = vmcs_readl(GUEST_RFLAGS);
2684         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2685         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2686         vmcs_writel(GUEST_RFLAGS, flags);
2687
2688         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2689                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2690
2691         update_exception_bitmap(vcpu);
2692
2693         if (emulate_invalid_guest_state)
2694                 return;
2695
2696         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2697         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2698         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2699         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2700
2701         vmx_segment_cache_clear(vmx);
2702
2703         vmcs_write16(GUEST_SS_SELECTOR, 0);
2704         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2705
2706         vmcs_write16(GUEST_CS_SELECTOR,
2707                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2708         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2709 }
2710
2711 static gva_t rmode_tss_base(struct kvm *kvm)
2712 {
2713         if (!kvm->arch.tss_addr) {
2714                 struct kvm_memslots *slots;
2715                 struct kvm_memory_slot *slot;
2716                 gfn_t base_gfn;
2717
2718                 slots = kvm_memslots(kvm);
2719                 slot = id_to_memslot(slots, 0);
2720                 base_gfn = slot->base_gfn + slot->npages - 3;
2721
2722                 return base_gfn << PAGE_SHIFT;
2723         }
2724         return kvm->arch.tss_addr;
2725 }
2726
2727 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2728 {
2729         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2730
2731         save->selector = vmcs_read16(sf->selector);
2732         save->base = vmcs_readl(sf->base);
2733         save->limit = vmcs_read32(sf->limit);
2734         save->ar = vmcs_read32(sf->ar_bytes);
2735         vmcs_write16(sf->selector, save->base >> 4);
2736         vmcs_write32(sf->base, save->base & 0xffff0);
2737         vmcs_write32(sf->limit, 0xffff);
2738         vmcs_write32(sf->ar_bytes, 0xf3);
2739         if (save->base & 0xf)
2740                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2741                             " aligned when entering protected mode (seg=%d)",
2742                             seg);
2743 }
2744
2745 static void enter_rmode(struct kvm_vcpu *vcpu)
2746 {
2747         unsigned long flags;
2748         struct vcpu_vmx *vmx = to_vmx(vcpu);
2749
2750         if (enable_unrestricted_guest)
2751                 return;
2752
2753         vmx->emulation_required = 1;
2754         vmx->rmode.vm86_active = 1;
2755
2756         /*
2757          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2758          * vcpu. Call it here with phys address pointing 16M below 4G.
2759          */
2760         if (!vcpu->kvm->arch.tss_addr) {
2761                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2762                              "called before entering vcpu\n");
2763                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2764                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2765                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2766         }
2767
2768         vmx_segment_cache_clear(vmx);
2769
2770         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2771         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2772         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2773
2774         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2775         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2776
2777         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2778         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2779
2780         flags = vmcs_readl(GUEST_RFLAGS);
2781         vmx->rmode.save_rflags = flags;
2782
2783         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2784
2785         vmcs_writel(GUEST_RFLAGS, flags);
2786         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2787         update_exception_bitmap(vcpu);
2788
2789         if (emulate_invalid_guest_state)
2790                 goto continue_rmode;
2791
2792         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2793         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2794         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2795
2796         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2797         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2798         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2799                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2800         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2801
2802         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2803         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2804         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2805         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2806
2807 continue_rmode:
2808         kvm_mmu_reset_context(vcpu);
2809 }
2810
2811 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2812 {
2813         struct vcpu_vmx *vmx = to_vmx(vcpu);
2814         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2815
2816         if (!msr)
2817                 return;
2818
2819         /*
2820          * Force kernel_gs_base reloading before EFER changes, as control
2821          * of this msr depends on is_long_mode().
2822          */
2823         vmx_load_host_state(to_vmx(vcpu));
2824         vcpu->arch.efer = efer;
2825         if (efer & EFER_LMA) {
2826                 vmcs_write32(VM_ENTRY_CONTROLS,
2827                              vmcs_read32(VM_ENTRY_CONTROLS) |
2828                              VM_ENTRY_IA32E_MODE);
2829                 msr->data = efer;
2830         } else {
2831                 vmcs_write32(VM_ENTRY_CONTROLS,
2832                              vmcs_read32(VM_ENTRY_CONTROLS) &
2833                              ~VM_ENTRY_IA32E_MODE);
2834
2835                 msr->data = efer & ~EFER_LME;
2836         }
2837         setup_msrs(vmx);
2838 }
2839
2840 #ifdef CONFIG_X86_64
2841
2842 static void enter_lmode(struct kvm_vcpu *vcpu)
2843 {
2844         u32 guest_tr_ar;
2845
2846         vmx_segment_cache_clear(to_vmx(vcpu));
2847
2848         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2849         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2850                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2851                                      __func__);
2852                 vmcs_write32(GUEST_TR_AR_BYTES,
2853                              (guest_tr_ar & ~AR_TYPE_MASK)
2854                              | AR_TYPE_BUSY_64_TSS);
2855         }
2856         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2857 }
2858
2859 static void exit_lmode(struct kvm_vcpu *vcpu)
2860 {
2861         vmcs_write32(VM_ENTRY_CONTROLS,
2862                      vmcs_read32(VM_ENTRY_CONTROLS)
2863                      & ~VM_ENTRY_IA32E_MODE);
2864         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2865 }
2866
2867 #endif
2868
2869 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2870 {
2871         vpid_sync_context(to_vmx(vcpu));
2872         if (enable_ept) {
2873                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2874                         return;
2875                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2876         }
2877 }
2878
2879 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2880 {
2881         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2882
2883         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2884         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2885 }
2886
2887 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2888 {
2889         if (enable_ept && is_paging(vcpu))
2890                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2891         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2892 }
2893
2894 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2895 {
2896         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2897
2898         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2899         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2900 }
2901
2902 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2903 {
2904         if (!test_bit(VCPU_EXREG_PDPTR,
2905                       (unsigned long *)&vcpu->arch.regs_dirty))
2906                 return;
2907
2908         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2909                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2910                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2911                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2912                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2913         }
2914 }
2915
2916 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2917 {
2918         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2919                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2920                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2921                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2922                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2923         }
2924
2925         __set_bit(VCPU_EXREG_PDPTR,
2926                   (unsigned long *)&vcpu->arch.regs_avail);
2927         __set_bit(VCPU_EXREG_PDPTR,
2928                   (unsigned long *)&vcpu->arch.regs_dirty);
2929 }
2930
2931 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2932
2933 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2934                                         unsigned long cr0,
2935                                         struct kvm_vcpu *vcpu)
2936 {
2937         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2938                 vmx_decache_cr3(vcpu);
2939         if (!(cr0 & X86_CR0_PG)) {
2940                 /* From paging/starting to nonpaging */
2941                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2942                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2943                              (CPU_BASED_CR3_LOAD_EXITING |
2944                               CPU_BASED_CR3_STORE_EXITING));
2945                 vcpu->arch.cr0 = cr0;
2946                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2947         } else if (!is_paging(vcpu)) {
2948                 /* From nonpaging to paging */
2949                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2950                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2951                              ~(CPU_BASED_CR3_LOAD_EXITING |
2952                                CPU_BASED_CR3_STORE_EXITING));
2953                 vcpu->arch.cr0 = cr0;
2954                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2955         }
2956
2957         if (!(cr0 & X86_CR0_WP))
2958                 *hw_cr0 &= ~X86_CR0_WP;
2959 }
2960
2961 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2962 {
2963         struct vcpu_vmx *vmx = to_vmx(vcpu);
2964         unsigned long hw_cr0;
2965
2966         if (enable_unrestricted_guest)
2967                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2968                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2969         else
2970                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2971
2972         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2973                 enter_pmode(vcpu);
2974
2975         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2976                 enter_rmode(vcpu);
2977
2978 #ifdef CONFIG_X86_64
2979         if (vcpu->arch.efer & EFER_LME) {
2980                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2981                         enter_lmode(vcpu);
2982                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2983                         exit_lmode(vcpu);
2984         }
2985 #endif
2986
2987         if (enable_ept)
2988                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2989
2990         if (!vcpu->fpu_active)
2991                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2992
2993         vmcs_writel(CR0_READ_SHADOW, cr0);
2994         vmcs_writel(GUEST_CR0, hw_cr0);
2995         vcpu->arch.cr0 = cr0;
2996         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2997 }
2998
2999 static u64 construct_eptp(unsigned long root_hpa)
3000 {
3001         u64 eptp;
3002
3003         /* TODO write the value reading from MSR */
3004         eptp = VMX_EPT_DEFAULT_MT |
3005                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3006         eptp |= (root_hpa & PAGE_MASK);
3007
3008         return eptp;
3009 }
3010
3011 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3012 {
3013         unsigned long guest_cr3;
3014         u64 eptp;
3015
3016         guest_cr3 = cr3;
3017         if (enable_ept) {
3018                 eptp = construct_eptp(cr3);
3019                 vmcs_write64(EPT_POINTER, eptp);
3020                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3021                         vcpu->kvm->arch.ept_identity_map_addr;
3022                 ept_load_pdptrs(vcpu);
3023         }
3024
3025         vmx_flush_tlb(vcpu);
3026         vmcs_writel(GUEST_CR3, guest_cr3);
3027 }
3028
3029 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3030 {
3031         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3032                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3033
3034         if (cr4 & X86_CR4_VMXE) {
3035                 /*
3036                  * To use VMXON (and later other VMX instructions), a guest
3037                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3038                  * So basically the check on whether to allow nested VMX
3039                  * is here.
3040                  */
3041                 if (!nested_vmx_allowed(vcpu))
3042                         return 1;
3043         } else if (to_vmx(vcpu)->nested.vmxon)
3044                 return 1;
3045
3046         vcpu->arch.cr4 = cr4;
3047         if (enable_ept) {
3048                 if (!is_paging(vcpu)) {
3049                         hw_cr4 &= ~X86_CR4_PAE;
3050                         hw_cr4 |= X86_CR4_PSE;
3051                 } else if (!(cr4 & X86_CR4_PAE)) {
3052                         hw_cr4 &= ~X86_CR4_PAE;
3053                 }
3054         }
3055
3056         vmcs_writel(CR4_READ_SHADOW, cr4);
3057         vmcs_writel(GUEST_CR4, hw_cr4);
3058         return 0;
3059 }
3060
3061 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3062                             struct kvm_segment *var, int seg)
3063 {
3064         struct vcpu_vmx *vmx = to_vmx(vcpu);
3065         struct kvm_save_segment *save;
3066         u32 ar;
3067
3068         if (vmx->rmode.vm86_active
3069             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3070                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3071                 || seg == VCPU_SREG_GS)
3072             && !emulate_invalid_guest_state) {
3073                 switch (seg) {
3074                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3075                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3076                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3077                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3078                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3079                 default: BUG();
3080                 }
3081                 var->selector = save->selector;
3082                 var->base = save->base;
3083                 var->limit = save->limit;
3084                 ar = save->ar;
3085                 if (seg == VCPU_SREG_TR
3086                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3087                         goto use_saved_rmode_seg;
3088         }
3089         var->base = vmx_read_guest_seg_base(vmx, seg);
3090         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3091         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3092         ar = vmx_read_guest_seg_ar(vmx, seg);
3093 use_saved_rmode_seg:
3094         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3095                 ar = 0;
3096         var->type = ar & 15;
3097         var->s = (ar >> 4) & 1;
3098         var->dpl = (ar >> 5) & 3;
3099         var->present = (ar >> 7) & 1;
3100         var->avl = (ar >> 12) & 1;
3101         var->l = (ar >> 13) & 1;
3102         var->db = (ar >> 14) & 1;
3103         var->g = (ar >> 15) & 1;
3104         var->unusable = (ar >> 16) & 1;
3105 }
3106
3107 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3108 {
3109         struct kvm_segment s;
3110
3111         if (to_vmx(vcpu)->rmode.vm86_active) {
3112                 vmx_get_segment(vcpu, &s, seg);
3113                 return s.base;
3114         }
3115         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3116 }
3117
3118 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3119 {
3120         if (!is_protmode(vcpu))
3121                 return 0;
3122
3123         if (!is_long_mode(vcpu)
3124             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3125                 return 3;
3126
3127         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3128 }
3129
3130 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3131 {
3132         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3133                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3134                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3135         }
3136         return to_vmx(vcpu)->cpl;
3137 }
3138
3139
3140 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3141 {
3142         u32 ar;
3143
3144         if (var->unusable)
3145                 ar = 1 << 16;
3146         else {
3147                 ar = var->type & 15;
3148                 ar |= (var->s & 1) << 4;
3149                 ar |= (var->dpl & 3) << 5;
3150                 ar |= (var->present & 1) << 7;
3151                 ar |= (var->avl & 1) << 12;
3152                 ar |= (var->l & 1) << 13;
3153                 ar |= (var->db & 1) << 14;
3154                 ar |= (var->g & 1) << 15;
3155         }
3156         if (ar == 0) /* a 0 value means unusable */
3157                 ar = AR_UNUSABLE_MASK;
3158
3159         return ar;
3160 }
3161
3162 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3163                             struct kvm_segment *var, int seg)
3164 {
3165         struct vcpu_vmx *vmx = to_vmx(vcpu);
3166         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3167         u32 ar;
3168
3169         vmx_segment_cache_clear(vmx);
3170
3171         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3172                 vmcs_write16(sf->selector, var->selector);
3173                 vmx->rmode.tr.selector = var->selector;
3174                 vmx->rmode.tr.base = var->base;
3175                 vmx->rmode.tr.limit = var->limit;
3176                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3177                 return;
3178         }
3179         vmcs_writel(sf->base, var->base);
3180         vmcs_write32(sf->limit, var->limit);
3181         vmcs_write16(sf->selector, var->selector);
3182         if (vmx->rmode.vm86_active && var->s) {
3183                 /*
3184                  * Hack real-mode segments into vm86 compatibility.
3185                  */
3186                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3187                         vmcs_writel(sf->base, 0xf0000);
3188                 ar = 0xf3;
3189         } else
3190                 ar = vmx_segment_access_rights(var);
3191
3192         /*
3193          *   Fix the "Accessed" bit in AR field of segment registers for older
3194          * qemu binaries.
3195          *   IA32 arch specifies that at the time of processor reset the
3196          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3197          * is setting it to 0 in the usedland code. This causes invalid guest
3198          * state vmexit when "unrestricted guest" mode is turned on.
3199          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3200          * tree. Newer qemu binaries with that qemu fix would not need this
3201          * kvm hack.
3202          */
3203         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3204                 ar |= 0x1; /* Accessed */
3205
3206         vmcs_write32(sf->ar_bytes, ar);
3207         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3208 }
3209
3210 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3211 {
3212         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3213
3214         *db = (ar >> 14) & 1;
3215         *l = (ar >> 13) & 1;
3216 }
3217
3218 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3219 {
3220         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3221         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3222 }
3223
3224 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3225 {
3226         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3227         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3228 }
3229
3230 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3231 {
3232         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3233         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3234 }
3235
3236 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3237 {
3238         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3239         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3240 }
3241
3242 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3243 {
3244         struct kvm_segment var;
3245         u32 ar;
3246
3247         vmx_get_segment(vcpu, &var, seg);
3248         ar = vmx_segment_access_rights(&var);
3249
3250         if (var.base != (var.selector << 4))
3251                 return false;
3252         if (var.limit != 0xffff)
3253                 return false;
3254         if (ar != 0xf3)
3255                 return false;
3256
3257         return true;
3258 }
3259
3260 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3261 {
3262         struct kvm_segment cs;
3263         unsigned int cs_rpl;
3264
3265         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3266         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3267
3268         if (cs.unusable)
3269                 return false;
3270         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3271                 return false;
3272         if (!cs.s)
3273                 return false;
3274         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3275                 if (cs.dpl > cs_rpl)
3276                         return false;
3277         } else {
3278                 if (cs.dpl != cs_rpl)
3279                         return false;
3280         }
3281         if (!cs.present)
3282                 return false;
3283
3284         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3285         return true;
3286 }
3287
3288 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3289 {
3290         struct kvm_segment ss;
3291         unsigned int ss_rpl;
3292
3293         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3294         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3295
3296         if (ss.unusable)
3297                 return true;
3298         if (ss.type != 3 && ss.type != 7)
3299                 return false;
3300         if (!ss.s)
3301                 return false;
3302         if (ss.dpl != ss_rpl) /* DPL != RPL */
3303                 return false;
3304         if (!ss.present)
3305                 return false;
3306
3307         return true;
3308 }
3309
3310 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3311 {
3312         struct kvm_segment var;
3313         unsigned int rpl;
3314
3315         vmx_get_segment(vcpu, &var, seg);
3316         rpl = var.selector & SELECTOR_RPL_MASK;
3317
3318         if (var.unusable)
3319                 return true;
3320         if (!var.s)
3321                 return false;
3322         if (!var.present)
3323                 return false;
3324         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3325                 if (var.dpl < rpl) /* DPL < RPL */
3326                         return false;
3327         }
3328
3329         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3330          * rights flags
3331          */
3332         return true;
3333 }
3334
3335 static bool tr_valid(struct kvm_vcpu *vcpu)
3336 {
3337         struct kvm_segment tr;
3338
3339         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3340
3341         if (tr.unusable)
3342                 return false;
3343         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3344                 return false;
3345         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3346                 return false;
3347         if (!tr.present)
3348                 return false;
3349
3350         return true;
3351 }
3352
3353 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3354 {
3355         struct kvm_segment ldtr;
3356
3357         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3358
3359         if (ldtr.unusable)
3360                 return true;
3361         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3362                 return false;
3363         if (ldtr.type != 2)
3364                 return false;
3365         if (!ldtr.present)
3366                 return false;
3367
3368         return true;
3369 }
3370
3371 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3372 {
3373         struct kvm_segment cs, ss;
3374
3375         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3376         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3377
3378         return ((cs.selector & SELECTOR_RPL_MASK) ==
3379                  (ss.selector & SELECTOR_RPL_MASK));
3380 }
3381
3382 /*
3383  * Check if guest state is valid. Returns true if valid, false if
3384  * not.
3385  * We assume that registers are always usable
3386  */
3387 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3388 {
3389         /* real mode guest state checks */
3390         if (!is_protmode(vcpu)) {
3391                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3392                         return false;
3393                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3394                         return false;
3395                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3396                         return false;
3397                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3398                         return false;
3399                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3400                         return false;
3401                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3402                         return false;
3403         } else {
3404         /* protected mode guest state checks */
3405                 if (!cs_ss_rpl_check(vcpu))
3406                         return false;
3407                 if (!code_segment_valid(vcpu))
3408                         return false;
3409                 if (!stack_segment_valid(vcpu))
3410                         return false;
3411                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3412                         return false;
3413                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3414                         return false;
3415                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3416                         return false;
3417                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3418                         return false;
3419                 if (!tr_valid(vcpu))
3420                         return false;
3421                 if (!ldtr_valid(vcpu))
3422                         return false;
3423         }
3424         /* TODO:
3425          * - Add checks on RIP
3426          * - Add checks on RFLAGS
3427          */
3428
3429         return true;
3430 }
3431
3432 static int init_rmode_tss(struct kvm *kvm)
3433 {
3434         gfn_t fn;
3435         u16 data = 0;
3436         int r, idx, ret = 0;
3437
3438         idx = srcu_read_lock(&kvm->srcu);
3439         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3440         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3441         if (r < 0)
3442                 goto out;
3443         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3444         r = kvm_write_guest_page(kvm, fn++, &data,
3445                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3446         if (r < 0)
3447                 goto out;
3448         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3449         if (r < 0)
3450                 goto out;
3451         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3452         if (r < 0)
3453                 goto out;
3454         data = ~0;
3455         r = kvm_write_guest_page(kvm, fn, &data,
3456                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3457                                  sizeof(u8));
3458         if (r < 0)
3459                 goto out;
3460
3461         ret = 1;
3462 out:
3463         srcu_read_unlock(&kvm->srcu, idx);
3464         return ret;
3465 }
3466
3467 static int init_rmode_identity_map(struct kvm *kvm)
3468 {
3469         int i, idx, r, ret;
3470         pfn_t identity_map_pfn;
3471         u32 tmp;
3472
3473         if (!enable_ept)
3474                 return 1;
3475         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3476                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3477                         "haven't been allocated!\n");
3478                 return 0;
3479         }
3480         if (likely(kvm->arch.ept_identity_pagetable_done))
3481                 return 1;
3482         ret = 0;
3483         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3484         idx = srcu_read_lock(&kvm->srcu);
3485         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3486         if (r < 0)
3487                 goto out;
3488         /* Set up identity-mapping pagetable for EPT in real mode */
3489         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3490                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3491                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3492                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3493                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3494                 if (r < 0)
3495                         goto out;
3496         }
3497         kvm->arch.ept_identity_pagetable_done = true;
3498         ret = 1;
3499 out:
3500         srcu_read_unlock(&kvm->srcu, idx);
3501         return ret;
3502 }
3503
3504 static void seg_setup(int seg)
3505 {
3506         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3507         unsigned int ar;
3508
3509         vmcs_write16(sf->selector, 0);
3510         vmcs_writel(sf->base, 0);
3511         vmcs_write32(sf->limit, 0xffff);
3512         if (enable_unrestricted_guest) {
3513                 ar = 0x93;
3514                 if (seg == VCPU_SREG_CS)
3515                         ar |= 0x08; /* code segment */
3516         } else
3517                 ar = 0xf3;
3518
3519         vmcs_write32(sf->ar_bytes, ar);
3520 }
3521
3522 static int alloc_apic_access_page(struct kvm *kvm)
3523 {
3524         struct kvm_userspace_memory_region kvm_userspace_mem;
3525         int r = 0;
3526
3527         mutex_lock(&kvm->slots_lock);
3528         if (kvm->arch.apic_access_page)
3529                 goto out;
3530         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3531         kvm_userspace_mem.flags = 0;
3532         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3533         kvm_userspace_mem.memory_size = PAGE_SIZE;
3534         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3535         if (r)
3536                 goto out;
3537
3538         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3539 out:
3540         mutex_unlock(&kvm->slots_lock);
3541         return r;
3542 }
3543
3544 static int alloc_identity_pagetable(struct kvm *kvm)
3545 {
3546         struct kvm_userspace_memory_region kvm_userspace_mem;
3547         int r = 0;
3548
3549         mutex_lock(&kvm->slots_lock);
3550         if (kvm->arch.ept_identity_pagetable)
3551                 goto out;
3552         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3553         kvm_userspace_mem.flags = 0;
3554         kvm_userspace_mem.guest_phys_addr =
3555                 kvm->arch.ept_identity_map_addr;
3556         kvm_userspace_mem.memory_size = PAGE_SIZE;
3557         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3558         if (r)
3559                 goto out;
3560
3561         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3562                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3563 out:
3564         mutex_unlock(&kvm->slots_lock);
3565         return r;
3566 }
3567
3568 static void allocate_vpid(struct vcpu_vmx *vmx)
3569 {
3570         int vpid;
3571
3572         vmx->vpid = 0;
3573         if (!enable_vpid)
3574                 return;
3575         spin_lock(&vmx_vpid_lock);
3576         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3577         if (vpid < VMX_NR_VPIDS) {
3578                 vmx->vpid = vpid;
3579                 __set_bit(vpid, vmx_vpid_bitmap);
3580         }
3581         spin_unlock(&vmx_vpid_lock);
3582 }
3583
3584 static void free_vpid(struct vcpu_vmx *vmx)
3585 {
3586         if (!enable_vpid)
3587                 return;
3588         spin_lock(&vmx_vpid_lock);
3589         if (vmx->vpid != 0)
3590                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3591         spin_unlock(&vmx_vpid_lock);
3592 }
3593
3594 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3595 {
3596         int f = sizeof(unsigned long);
3597
3598         if (!cpu_has_vmx_msr_bitmap())
3599                 return;
3600
3601         /*
3602          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3603          * have the write-low and read-high bitmap offsets the wrong way round.
3604          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3605          */
3606         if (msr <= 0x1fff) {
3607                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3608                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3609         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3610                 msr &= 0x1fff;
3611                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3612                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3613         }
3614 }
3615
3616 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3617 {
3618         if (!longmode_only)
3619                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3620         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3621 }
3622
3623 /*
3624  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3625  * will not change in the lifetime of the guest.
3626  * Note that host-state that does change is set elsewhere. E.g., host-state
3627  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3628  */
3629 static void vmx_set_constant_host_state(void)
3630 {
3631         u32 low32, high32;
3632         unsigned long tmpl;
3633         struct desc_ptr dt;
3634
3635         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3636         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3637         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3638
3639         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3640         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3641         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3642         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3643         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3644
3645         native_store_idt(&dt);
3646         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3647
3648         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3649         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3650
3651         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3652         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3653         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3654         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3655
3656         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3657                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3658                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3659         }
3660 }
3661
3662 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3663 {
3664         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3665         if (enable_ept)
3666                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3667         if (is_guest_mode(&vmx->vcpu))
3668                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3669                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3670         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3671 }
3672
3673 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3674 {
3675         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3676         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3677                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3678 #ifdef CONFIG_X86_64
3679                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3680                                 CPU_BASED_CR8_LOAD_EXITING;
3681 #endif
3682         }
3683         if (!enable_ept)
3684                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3685                                 CPU_BASED_CR3_LOAD_EXITING  |
3686                                 CPU_BASED_INVLPG_EXITING;
3687         return exec_control;
3688 }
3689
3690 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3691 {
3692         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3693         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3694                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3695         if (vmx->vpid == 0)
3696                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3697         if (!enable_ept) {
3698                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3699                 enable_unrestricted_guest = 0;
3700         }
3701         if (!enable_unrestricted_guest)
3702                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3703         if (!ple_gap)
3704                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3705         return exec_control;
3706 }
3707
3708 static void ept_set_mmio_spte_mask(void)
3709 {
3710         /*
3711          * EPT Misconfigurations can be generated if the value of bits 2:0
3712          * of an EPT paging-structure entry is 110b (write/execute).
3713          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3714          * spte.
3715          */
3716         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3717 }
3718
3719 /*
3720  * Sets up the vmcs for emulated real mode.
3721  */
3722 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3723 {
3724 #ifdef CONFIG_X86_64
3725         unsigned long a;
3726 #endif
3727         int i;
3728
3729         /* I/O */
3730         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3731         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3732
3733         if (cpu_has_vmx_msr_bitmap())
3734                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3735
3736         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3737
3738         /* Control */
3739         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3740                 vmcs_config.pin_based_exec_ctrl);
3741
3742         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3743
3744         if (cpu_has_secondary_exec_ctrls()) {
3745                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3746                                 vmx_secondary_exec_control(vmx));
3747         }
3748
3749         if (ple_gap) {
3750                 vmcs_write32(PLE_GAP, ple_gap);
3751                 vmcs_write32(PLE_WINDOW, ple_window);
3752         }
3753
3754         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3755         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3756         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3757
3758         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3759         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3760         vmx_set_constant_host_state();
3761 #ifdef CONFIG_X86_64
3762         rdmsrl(MSR_FS_BASE, a);
3763         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3764         rdmsrl(MSR_GS_BASE, a);
3765         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3766 #else
3767         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3768         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3769 #endif
3770
3771         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3772         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3773         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3774         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3775         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3776
3777         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3778                 u32 msr_low, msr_high;
3779                 u64 host_pat;
3780                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3781                 host_pat = msr_low | ((u64) msr_high << 32);
3782                 /* Write the default value follow host pat */
3783                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3784                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3785                 vmx->vcpu.arch.pat = host_pat;
3786         }
3787
3788         for (i = 0; i < NR_VMX_MSR; ++i) {
3789                 u32 index = vmx_msr_index[i];
3790                 u32 data_low, data_high;
3791                 int j = vmx->nmsrs;
3792
3793                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3794                         continue;
3795                 if (wrmsr_safe(index, data_low, data_high) < 0)
3796                         continue;
3797                 vmx->guest_msrs[j].index = i;
3798                 vmx->guest_msrs[j].data = 0;
3799                 vmx->guest_msrs[j].mask = -1ull;
3800                 ++vmx->nmsrs;
3801         }
3802
3803         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3804
3805         /* 22.2.1, 20.8.1 */
3806         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3807
3808         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3809         set_cr4_guest_host_mask(vmx);
3810
3811         kvm_write_tsc(&vmx->vcpu, 0);
3812
3813         return 0;
3814 }
3815
3816 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3817 {
3818         struct vcpu_vmx *vmx = to_vmx(vcpu);
3819         u64 msr;
3820         int ret;
3821
3822         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3823
3824         vmx->rmode.vm86_active = 0;
3825
3826         vmx->soft_vnmi_blocked = 0;
3827
3828         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3829         kvm_set_cr8(&vmx->vcpu, 0);
3830         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3831         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3832                 msr |= MSR_IA32_APICBASE_BSP;
3833         kvm_set_apic_base(&vmx->vcpu, msr);
3834
3835         ret = fx_init(&vmx->vcpu);
3836         if (ret != 0)
3837                 goto out;
3838
3839         vmx_segment_cache_clear(vmx);
3840
3841         seg_setup(VCPU_SREG_CS);
3842         /*
3843          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3844          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3845          */
3846         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3847                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3848                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3849         } else {
3850                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3851                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3852         }
3853
3854         seg_setup(VCPU_SREG_DS);
3855         seg_setup(VCPU_SREG_ES);
3856         seg_setup(VCPU_SREG_FS);
3857         seg_setup(VCPU_SREG_GS);
3858         seg_setup(VCPU_SREG_SS);
3859
3860         vmcs_write16(GUEST_TR_SELECTOR, 0);
3861         vmcs_writel(GUEST_TR_BASE, 0);
3862         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3863         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3864
3865         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3866         vmcs_writel(GUEST_LDTR_BASE, 0);
3867         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3868         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3869
3870         vmcs_write32(GUEST_SYSENTER_CS, 0);
3871         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3872         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3873
3874         vmcs_writel(GUEST_RFLAGS, 0x02);
3875         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3876                 kvm_rip_write(vcpu, 0xfff0);
3877         else
3878                 kvm_rip_write(vcpu, 0);
3879         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3880
3881         vmcs_writel(GUEST_DR7, 0x400);
3882
3883         vmcs_writel(GUEST_GDTR_BASE, 0);
3884         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3885
3886         vmcs_writel(GUEST_IDTR_BASE, 0);
3887         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3888
3889         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3890         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3891         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3892
3893         /* Special registers */
3894         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3895
3896         setup_msrs(vmx);
3897
3898         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3899
3900         if (cpu_has_vmx_tpr_shadow()) {
3901                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3902                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3903                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3904                                      __pa(vmx->vcpu.arch.apic->regs));
3905                 vmcs_write32(TPR_THRESHOLD, 0);
3906         }
3907
3908         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3909                 vmcs_write64(APIC_ACCESS_ADDR,
3910                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3911
3912         if (vmx->vpid != 0)
3913                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3914
3915         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3916         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3917         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3918         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3919         vmx_set_cr4(&vmx->vcpu, 0);
3920         vmx_set_efer(&vmx->vcpu, 0);
3921         vmx_fpu_activate(&vmx->vcpu);
3922         update_exception_bitmap(&vmx->vcpu);
3923
3924         vpid_sync_context(vmx);
3925
3926         ret = 0;
3927
3928         /* HACK: Don't enable emulation on guest boot/reset */
3929         vmx->emulation_required = 0;
3930
3931 out:
3932         return ret;
3933 }
3934
3935 /*
3936  * In nested virtualization, check if L1 asked to exit on external interrupts.
3937  * For most existing hypervisors, this will always return true.
3938  */
3939 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3940 {
3941         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3942                 PIN_BASED_EXT_INTR_MASK;
3943 }
3944
3945 static void enable_irq_window(struct kvm_vcpu *vcpu)
3946 {
3947         u32 cpu_based_vm_exec_control;
3948         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3949                 /*
3950                  * We get here if vmx_interrupt_allowed() said we can't
3951                  * inject to L1 now because L2 must run. Ask L2 to exit
3952                  * right after entry, so we can inject to L1 more promptly.
3953                  */
3954                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
3955                 return;
3956         }
3957
3958         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3959         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3960         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3961 }
3962
3963 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3964 {
3965         u32 cpu_based_vm_exec_control;
3966
3967         if (!cpu_has_virtual_nmis()) {
3968                 enable_irq_window(vcpu);
3969                 return;
3970         }
3971
3972         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3973                 enable_irq_window(vcpu);
3974                 return;
3975         }
3976         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3977         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3978         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3979 }
3980
3981 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3982 {
3983         struct vcpu_vmx *vmx = to_vmx(vcpu);
3984         uint32_t intr;
3985         int irq = vcpu->arch.interrupt.nr;
3986
3987         trace_kvm_inj_virq(irq);
3988
3989         ++vcpu->stat.irq_injections;
3990         if (vmx->rmode.vm86_active) {
3991                 int inc_eip = 0;
3992                 if (vcpu->arch.interrupt.soft)
3993                         inc_eip = vcpu->arch.event_exit_inst_len;
3994                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3995                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3996                 return;
3997         }
3998         intr = irq | INTR_INFO_VALID_MASK;
3999         if (vcpu->arch.interrupt.soft) {
4000                 intr |= INTR_TYPE_SOFT_INTR;
4001                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4002                              vmx->vcpu.arch.event_exit_inst_len);
4003         } else
4004                 intr |= INTR_TYPE_EXT_INTR;
4005         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4006 }
4007
4008 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4009 {
4010         struct vcpu_vmx *vmx = to_vmx(vcpu);
4011
4012         if (is_guest_mode(vcpu))
4013                 return;
4014
4015         if (!cpu_has_virtual_nmis()) {
4016                 /*
4017                  * Tracking the NMI-blocked state in software is built upon
4018                  * finding the next open IRQ window. This, in turn, depends on
4019                  * well-behaving guests: They have to keep IRQs disabled at
4020                  * least as long as the NMI handler runs. Otherwise we may
4021                  * cause NMI nesting, maybe breaking the guest. But as this is
4022                  * highly unlikely, we can live with the residual risk.
4023                  */
4024                 vmx->soft_vnmi_blocked = 1;
4025                 vmx->vnmi_blocked_time = 0;
4026         }
4027
4028         ++vcpu->stat.nmi_injections;
4029         vmx->nmi_known_unmasked = false;
4030         if (vmx->rmode.vm86_active) {
4031                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4032                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4033                 return;
4034         }
4035         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4036                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4037 }
4038
4039 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4040 {
4041         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4042                 return 0;
4043
4044         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4045                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4046                    | GUEST_INTR_STATE_NMI));
4047 }
4048
4049 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4050 {
4051         if (!cpu_has_virtual_nmis())
4052                 return to_vmx(vcpu)->soft_vnmi_blocked;
4053         if (to_vmx(vcpu)->nmi_known_unmasked)
4054                 return false;
4055         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4056 }
4057
4058 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4059 {
4060         struct vcpu_vmx *vmx = to_vmx(vcpu);
4061
4062         if (!cpu_has_virtual_nmis()) {
4063                 if (vmx->soft_vnmi_blocked != masked) {
4064                         vmx->soft_vnmi_blocked = masked;
4065                         vmx->vnmi_blocked_time = 0;
4066                 }
4067         } else {
4068                 vmx->nmi_known_unmasked = !masked;
4069                 if (masked)
4070                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4071                                       GUEST_INTR_STATE_NMI);
4072                 else
4073                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4074                                         GUEST_INTR_STATE_NMI);
4075         }
4076 }
4077
4078 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4079 {
4080         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4081                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4082                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4083                     (vmcs12->idt_vectoring_info_field &
4084                      VECTORING_INFO_VALID_MASK))
4085                         return 0;
4086                 nested_vmx_vmexit(vcpu);
4087                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4088                 vmcs12->vm_exit_intr_info = 0;
4089                 /* fall through to normal code, but now in L1, not L2 */
4090         }
4091
4092         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4093                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4094                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4095 }
4096
4097 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4098 {
4099         int ret;
4100         struct kvm_userspace_memory_region tss_mem = {
4101                 .slot = TSS_PRIVATE_MEMSLOT,
4102                 .guest_phys_addr = addr,
4103                 .memory_size = PAGE_SIZE * 3,
4104                 .flags = 0,
4105         };
4106
4107         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4108         if (ret)
4109                 return ret;
4110         kvm->arch.tss_addr = addr;
4111         if (!init_rmode_tss(kvm))
4112                 return  -ENOMEM;
4113
4114         return 0;
4115 }
4116
4117 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4118                                   int vec, u32 err_code)
4119 {
4120         /*
4121          * Instruction with address size override prefix opcode 0x67
4122          * Cause the #SS fault with 0 error code in VM86 mode.
4123          */
4124         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4125                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4126                         return 1;
4127         /*
4128          * Forward all other exceptions that are valid in real mode.
4129          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4130          *        the required debugging infrastructure rework.
4131          */
4132         switch (vec) {
4133         case DB_VECTOR:
4134                 if (vcpu->guest_debug &
4135                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4136                         return 0;
4137                 kvm_queue_exception(vcpu, vec);
4138                 return 1;
4139         case BP_VECTOR:
4140                 /*
4141                  * Update instruction length as we may reinject the exception
4142                  * from user space while in guest debugging mode.
4143                  */
4144                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4145                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4146                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4147                         return 0;
4148                 /* fall through */
4149         case DE_VECTOR:
4150         case OF_VECTOR:
4151         case BR_VECTOR:
4152         case UD_VECTOR:
4153         case DF_VECTOR:
4154         case SS_VECTOR:
4155         case GP_VECTOR:
4156         case MF_VECTOR:
4157                 kvm_queue_exception(vcpu, vec);
4158                 return 1;
4159         }
4160         return 0;
4161 }
4162
4163 /*
4164  * Trigger machine check on the host. We assume all the MSRs are already set up
4165  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4166  * We pass a fake environment to the machine check handler because we want
4167  * the guest to be always treated like user space, no matter what context
4168  * it used internally.
4169  */
4170 static void kvm_machine_check(void)
4171 {
4172 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4173         struct pt_regs regs = {
4174                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4175                 .flags = X86_EFLAGS_IF,
4176         };
4177
4178         do_machine_check(&regs, 0);
4179 #endif
4180 }
4181
4182 static int handle_machine_check(struct kvm_vcpu *vcpu)
4183 {
4184         /* already handled by vcpu_run */
4185         return 1;
4186 }
4187
4188 static int handle_exception(struct kvm_vcpu *vcpu)
4189 {
4190         struct vcpu_vmx *vmx = to_vmx(vcpu);
4191         struct kvm_run *kvm_run = vcpu->run;
4192         u32 intr_info, ex_no, error_code;
4193         unsigned long cr2, rip, dr6;
4194         u32 vect_info;
4195         enum emulation_result er;
4196
4197         vect_info = vmx->idt_vectoring_info;
4198         intr_info = vmx->exit_intr_info;
4199
4200         if (is_machine_check(intr_info))
4201                 return handle_machine_check(vcpu);
4202
4203         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4204             !is_page_fault(intr_info)) {
4205                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4206                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4207                 vcpu->run->internal.ndata = 2;
4208                 vcpu->run->internal.data[0] = vect_info;
4209                 vcpu->run->internal.data[1] = intr_info;
4210                 return 0;
4211         }
4212
4213         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4214                 return 1;  /* already handled by vmx_vcpu_run() */
4215
4216         if (is_no_device(intr_info)) {
4217                 vmx_fpu_activate(vcpu);
4218                 return 1;
4219         }
4220
4221         if (is_invalid_opcode(intr_info)) {
4222                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4223                 if (er != EMULATE_DONE)
4224                         kvm_queue_exception(vcpu, UD_VECTOR);
4225                 return 1;
4226         }
4227
4228         error_code = 0;
4229         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4230                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4231         if (is_page_fault(intr_info)) {
4232                 /* EPT won't cause page fault directly */
4233                 BUG_ON(enable_ept);
4234                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4235                 trace_kvm_page_fault(cr2, error_code);
4236
4237                 if (kvm_event_needs_reinjection(vcpu))
4238                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4239                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4240         }
4241
4242         if (vmx->rmode.vm86_active &&
4243             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4244                                                                 error_code)) {
4245                 if (vcpu->arch.halt_request) {
4246                         vcpu->arch.halt_request = 0;
4247                         return kvm_emulate_halt(vcpu);
4248                 }
4249                 return 1;
4250         }
4251
4252         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4253         switch (ex_no) {
4254         case DB_VECTOR:
4255                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4256                 if (!(vcpu->guest_debug &
4257                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4258                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4259                         kvm_queue_exception(vcpu, DB_VECTOR);
4260                         return 1;
4261                 }
4262                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4263                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4264                 /* fall through */
4265         case BP_VECTOR:
4266                 /*
4267                  * Update instruction length as we may reinject #BP from
4268                  * user space while in guest debugging mode. Reading it for
4269                  * #DB as well causes no harm, it is not used in that case.
4270                  */
4271                 vmx->vcpu.arch.event_exit_inst_len =
4272                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4273                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4274                 rip = kvm_rip_read(vcpu);
4275                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4276                 kvm_run->debug.arch.exception = ex_no;
4277                 break;
4278         default:
4279                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4280                 kvm_run->ex.exception = ex_no;
4281                 kvm_run->ex.error_code = error_code;
4282                 break;
4283         }
4284         return 0;
4285 }
4286
4287 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4288 {
4289         ++vcpu->stat.irq_exits;
4290         return 1;
4291 }
4292
4293 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4294 {
4295         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4296         return 0;
4297 }
4298
4299 static int handle_io(struct kvm_vcpu *vcpu)
4300 {
4301         unsigned long exit_qualification;
4302         int size, in, string;
4303         unsigned port;
4304
4305         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4306         string = (exit_qualification & 16) != 0;
4307         in = (exit_qualification & 8) != 0;
4308
4309         ++vcpu->stat.io_exits;
4310
4311         if (string || in)
4312                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4313
4314         port = exit_qualification >> 16;
4315         size = (exit_qualification & 7) + 1;
4316         skip_emulated_instruction(vcpu);
4317
4318         return kvm_fast_pio_out(vcpu, size, port);
4319 }
4320
4321 static void
4322 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4323 {
4324         /*
4325          * Patch in the VMCALL instruction:
4326          */
4327         hypercall[0] = 0x0f;
4328         hypercall[1] = 0x01;
4329         hypercall[2] = 0xc1;
4330 }
4331
4332 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4333 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4334 {
4335         if (to_vmx(vcpu)->nested.vmxon &&
4336             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4337                 return 1;
4338
4339         if (is_guest_mode(vcpu)) {
4340                 /*
4341                  * We get here when L2 changed cr0 in a way that did not change
4342                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4343                  * but did change L0 shadowed bits. This can currently happen
4344                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4345                  * loading) while pretending to allow the guest to change it.
4346                  */
4347                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4348                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4349                         return 1;
4350                 vmcs_writel(CR0_READ_SHADOW, val);
4351                 return 0;
4352         } else
4353                 return kvm_set_cr0(vcpu, val);
4354 }
4355
4356 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4357 {
4358         if (is_guest_mode(vcpu)) {
4359                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4360                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4361                         return 1;
4362                 vmcs_writel(CR4_READ_SHADOW, val);
4363                 return 0;
4364         } else
4365                 return kvm_set_cr4(vcpu, val);
4366 }
4367
4368 /* called to set cr0 as approriate for clts instruction exit. */
4369 static void handle_clts(struct kvm_vcpu *vcpu)
4370 {
4371         if (is_guest_mode(vcpu)) {
4372                 /*
4373                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4374                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4375                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4376                  */
4377                 vmcs_writel(CR0_READ_SHADOW,
4378                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4379                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4380         } else
4381                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4382 }
4383
4384 static int handle_cr(struct kvm_vcpu *vcpu)
4385 {
4386         unsigned long exit_qualification, val;
4387         int cr;
4388         int reg;
4389         int err;
4390
4391         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4392         cr = exit_qualification & 15;
4393         reg = (exit_qualification >> 8) & 15;
4394         switch ((exit_qualification >> 4) & 3) {
4395         case 0: /* mov to cr */
4396                 val = kvm_register_read(vcpu, reg);
4397                 trace_kvm_cr_write(cr, val);
4398                 switch (cr) {
4399                 case 0:
4400                         err = handle_set_cr0(vcpu, val);
4401                         kvm_complete_insn_gp(vcpu, err);
4402                         return 1;
4403                 case 3:
4404                         err = kvm_set_cr3(vcpu, val);
4405                         kvm_complete_insn_gp(vcpu, err);
4406                         return 1;
4407                 case 4:
4408                         err = handle_set_cr4(vcpu, val);
4409                         kvm_complete_insn_gp(vcpu, err);
4410                         return 1;
4411                 case 8: {
4412                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4413                                 u8 cr8 = kvm_register_read(vcpu, reg);
4414                                 err = kvm_set_cr8(vcpu, cr8);
4415                                 kvm_complete_insn_gp(vcpu, err);
4416                                 if (irqchip_in_kernel(vcpu->kvm))
4417                                         return 1;
4418                                 if (cr8_prev <= cr8)
4419                                         return 1;
4420                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4421                                 return 0;
4422                         }
4423                 };
4424                 break;
4425         case 2: /* clts */
4426                 handle_clts(vcpu);
4427                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4428                 skip_emulated_instruction(vcpu);
4429                 vmx_fpu_activate(vcpu);
4430                 return 1;
4431         case 1: /*mov from cr*/
4432                 switch (cr) {
4433                 case 3:
4434                         val = kvm_read_cr3(vcpu);
4435                         kvm_register_write(vcpu, reg, val);
4436                         trace_kvm_cr_read(cr, val);
4437                         skip_emulated_instruction(vcpu);
4438                         return 1;
4439                 case 8:
4440                         val = kvm_get_cr8(vcpu);
4441                         kvm_register_write(vcpu, reg, val);
4442                         trace_kvm_cr_read(cr, val);
4443                         skip_emulated_instruction(vcpu);
4444                         return 1;
4445                 }
4446                 break;
4447         case 3: /* lmsw */
4448                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4449                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4450                 kvm_lmsw(vcpu, val);
4451
4452                 skip_emulated_instruction(vcpu);
4453                 return 1;
4454         default:
4455                 break;
4456         }
4457         vcpu->run->exit_reason = 0;
4458         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4459                (int)(exit_qualification >> 4) & 3, cr);
4460         return 0;
4461 }
4462
4463 static int handle_dr(struct kvm_vcpu *vcpu)
4464 {
4465         unsigned long exit_qualification;
4466         int dr, reg;
4467
4468         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4469         if (!kvm_require_cpl(vcpu, 0))
4470                 return 1;
4471         dr = vmcs_readl(GUEST_DR7);
4472         if (dr & DR7_GD) {
4473                 /*
4474                  * As the vm-exit takes precedence over the debug trap, we
4475                  * need to emulate the latter, either for the host or the
4476                  * guest debugging itself.
4477                  */
4478                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4479                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4480                         vcpu->run->debug.arch.dr7 = dr;
4481                         vcpu->run->debug.arch.pc =
4482                                 vmcs_readl(GUEST_CS_BASE) +
4483                                 vmcs_readl(GUEST_RIP);
4484                         vcpu->run->debug.arch.exception = DB_VECTOR;
4485                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4486                         return 0;
4487                 } else {
4488                         vcpu->arch.dr7 &= ~DR7_GD;
4489                         vcpu->arch.dr6 |= DR6_BD;
4490                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4491                         kvm_queue_exception(vcpu, DB_VECTOR);
4492                         return 1;
4493                 }
4494         }
4495
4496         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4497         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4498         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4499         if (exit_qualification & TYPE_MOV_FROM_DR) {
4500                 unsigned long val;
4501                 if (!kvm_get_dr(vcpu, dr, &val))
4502                         kvm_register_write(vcpu, reg, val);
4503         } else
4504                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4505         skip_emulated_instruction(vcpu);
4506         return 1;
4507 }
4508
4509 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4510 {
4511         vmcs_writel(GUEST_DR7, val);
4512 }
4513
4514 static int handle_cpuid(struct kvm_vcpu *vcpu)
4515 {
4516         kvm_emulate_cpuid(vcpu);
4517         return 1;
4518 }
4519
4520 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4521 {
4522         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4523         u64 data;
4524
4525         if (vmx_get_msr(vcpu, ecx, &data)) {
4526                 trace_kvm_msr_read_ex(ecx);
4527                 kvm_inject_gp(vcpu, 0);
4528                 return 1;
4529         }
4530
4531         trace_kvm_msr_read(ecx, data);
4532
4533         /* FIXME: handling of bits 32:63 of rax, rdx */
4534         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4535         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4536         skip_emulated_instruction(vcpu);
4537         return 1;
4538 }
4539
4540 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4541 {
4542         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4543         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4544                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4545
4546         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4547                 trace_kvm_msr_write_ex(ecx, data);
4548                 kvm_inject_gp(vcpu, 0);
4549                 return 1;
4550         }
4551
4552         trace_kvm_msr_write(ecx, data);
4553         skip_emulated_instruction(vcpu);
4554         return 1;
4555 }
4556
4557 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4558 {
4559         kvm_make_request(KVM_REQ_EVENT, vcpu);
4560         return 1;
4561 }
4562
4563 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4564 {
4565         u32 cpu_based_vm_exec_control;
4566
4567         /* clear pending irq */
4568         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4569         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4570         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4571
4572         kvm_make_request(KVM_REQ_EVENT, vcpu);
4573
4574         ++vcpu->stat.irq_window_exits;
4575
4576         /*
4577          * If the user space waits to inject interrupts, exit as soon as
4578          * possible
4579          */
4580         if (!irqchip_in_kernel(vcpu->kvm) &&
4581             vcpu->run->request_interrupt_window &&
4582             !kvm_cpu_has_interrupt(vcpu)) {
4583                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4584                 return 0;
4585         }
4586         return 1;
4587 }
4588
4589 static int handle_halt(struct kvm_vcpu *vcpu)
4590 {
4591         skip_emulated_instruction(vcpu);
4592         return kvm_emulate_halt(vcpu);
4593 }
4594
4595 static int handle_vmcall(struct kvm_vcpu *vcpu)
4596 {
4597         skip_emulated_instruction(vcpu);
4598         kvm_emulate_hypercall(vcpu);
4599         return 1;
4600 }
4601
4602 static int handle_invd(struct kvm_vcpu *vcpu)
4603 {
4604         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4605 }
4606
4607 static int handle_invlpg(struct kvm_vcpu *vcpu)
4608 {
4609         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4610
4611         kvm_mmu_invlpg(vcpu, exit_qualification);
4612         skip_emulated_instruction(vcpu);
4613         return 1;
4614 }
4615
4616 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4617 {
4618         int err;
4619
4620         err = kvm_rdpmc(vcpu);
4621         kvm_complete_insn_gp(vcpu, err);
4622
4623         return 1;
4624 }
4625
4626 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4627 {
4628         skip_emulated_instruction(vcpu);
4629         kvm_emulate_wbinvd(vcpu);
4630         return 1;
4631 }
4632
4633 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4634 {
4635         u64 new_bv = kvm_read_edx_eax(vcpu);
4636         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4637
4638         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4639                 skip_emulated_instruction(vcpu);
4640         return 1;
4641 }
4642
4643 static int handle_apic_access(struct kvm_vcpu *vcpu)
4644 {
4645         if (likely(fasteoi)) {
4646                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4647                 int access_type, offset;
4648
4649                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4650                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4651                 /*
4652                  * Sane guest uses MOV to write EOI, with written value
4653                  * not cared. So make a short-circuit here by avoiding
4654                  * heavy instruction emulation.
4655                  */
4656                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4657                     (offset == APIC_EOI)) {
4658                         kvm_lapic_set_eoi(vcpu);
4659                         skip_emulated_instruction(vcpu);
4660                         return 1;
4661                 }
4662         }
4663         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4664 }
4665
4666 static int handle_task_switch(struct kvm_vcpu *vcpu)
4667 {
4668         struct vcpu_vmx *vmx = to_vmx(vcpu);
4669         unsigned long exit_qualification;
4670         bool has_error_code = false;
4671         u32 error_code = 0;
4672         u16 tss_selector;
4673         int reason, type, idt_v, idt_index;
4674
4675         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4676         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4677         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4678
4679         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4680
4681         reason = (u32)exit_qualification >> 30;
4682         if (reason == TASK_SWITCH_GATE && idt_v) {
4683                 switch (type) {
4684                 case INTR_TYPE_NMI_INTR:
4685                         vcpu->arch.nmi_injected = false;
4686                         vmx_set_nmi_mask(vcpu, true);
4687                         break;
4688                 case INTR_TYPE_EXT_INTR:
4689                 case INTR_TYPE_SOFT_INTR:
4690                         kvm_clear_interrupt_queue(vcpu);
4691                         break;
4692                 case INTR_TYPE_HARD_EXCEPTION:
4693                         if (vmx->idt_vectoring_info &
4694                             VECTORING_INFO_DELIVER_CODE_MASK) {
4695                                 has_error_code = true;
4696                                 error_code =
4697                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4698                         }
4699                         /* fall through */
4700                 case INTR_TYPE_SOFT_EXCEPTION:
4701                         kvm_clear_exception_queue(vcpu);
4702                         break;
4703                 default:
4704                         break;
4705                 }
4706         }
4707         tss_selector = exit_qualification;
4708
4709         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4710                        type != INTR_TYPE_EXT_INTR &&
4711                        type != INTR_TYPE_NMI_INTR))
4712                 skip_emulated_instruction(vcpu);
4713
4714         if (kvm_task_switch(vcpu, tss_selector,
4715                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4716                             has_error_code, error_code) == EMULATE_FAIL) {
4717                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4718                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4719                 vcpu->run->internal.ndata = 0;
4720                 return 0;
4721         }
4722
4723         /* clear all local breakpoint enable flags */
4724         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4725
4726         /*
4727          * TODO: What about debug traps on tss switch?
4728          *       Are we supposed to inject them and update dr6?
4729          */
4730
4731         return 1;
4732 }
4733
4734 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4735 {
4736         unsigned long exit_qualification;
4737         gpa_t gpa;
4738         int gla_validity;
4739
4740         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4741
4742         if (exit_qualification & (1 << 6)) {
4743                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4744                 return -EINVAL;
4745         }
4746
4747         gla_validity = (exit_qualification >> 7) & 0x3;
4748         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4749                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4750                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4751                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4752                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4753                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4754                         (long unsigned int)exit_qualification);
4755                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4756                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4757                 return 0;
4758         }
4759
4760         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4761         trace_kvm_page_fault(gpa, exit_qualification);
4762         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4763 }
4764
4765 static u64 ept_rsvd_mask(u64 spte, int level)
4766 {
4767         int i;
4768         u64 mask = 0;
4769
4770         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4771                 mask |= (1ULL << i);
4772
4773         if (level > 2)
4774                 /* bits 7:3 reserved */
4775                 mask |= 0xf8;
4776         else if (level == 2) {
4777                 if (spte & (1ULL << 7))
4778                         /* 2MB ref, bits 20:12 reserved */
4779                         mask |= 0x1ff000;
4780                 else
4781                         /* bits 6:3 reserved */
4782                         mask |= 0x78;
4783         }
4784
4785         return mask;
4786 }
4787
4788 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4789                                        int level)
4790 {
4791         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4792
4793         /* 010b (write-only) */
4794         WARN_ON((spte & 0x7) == 0x2);
4795
4796         /* 110b (write/execute) */
4797         WARN_ON((spte & 0x7) == 0x6);
4798
4799         /* 100b (execute-only) and value not supported by logical processor */
4800         if (!cpu_has_vmx_ept_execute_only())
4801                 WARN_ON((spte & 0x7) == 0x4);
4802
4803         /* not 000b */
4804         if ((spte & 0x7)) {
4805                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4806
4807                 if (rsvd_bits != 0) {
4808                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4809                                          __func__, rsvd_bits);
4810                         WARN_ON(1);
4811                 }
4812
4813                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4814                         u64 ept_mem_type = (spte & 0x38) >> 3;
4815
4816                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4817                             ept_mem_type == 7) {
4818                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4819                                                 __func__, ept_mem_type);
4820                                 WARN_ON(1);
4821                         }
4822                 }
4823         }
4824 }
4825
4826 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4827 {
4828         u64 sptes[4];
4829         int nr_sptes, i, ret;
4830         gpa_t gpa;
4831
4832         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4833
4834         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4835         if (likely(ret == 1))
4836                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4837                                               EMULATE_DONE;
4838         if (unlikely(!ret))
4839                 return 1;
4840
4841         /* It is the real ept misconfig */
4842         printk(KERN_ERR "EPT: Misconfiguration.\n");
4843         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4844
4845         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4846
4847         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4848                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4849
4850         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4851         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4852
4853         return 0;
4854 }
4855
4856 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4857 {
4858         u32 cpu_based_vm_exec_control;
4859
4860         /* clear pending NMI */
4861         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4862         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4863         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4864         ++vcpu->stat.nmi_window_exits;
4865         kvm_make_request(KVM_REQ_EVENT, vcpu);
4866
4867         return 1;
4868 }
4869
4870 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4871 {
4872         struct vcpu_vmx *vmx = to_vmx(vcpu);
4873         enum emulation_result err = EMULATE_DONE;
4874         int ret = 1;
4875         u32 cpu_exec_ctrl;
4876         bool intr_window_requested;
4877
4878         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4879         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4880
4881         while (!guest_state_valid(vcpu)) {
4882                 if (intr_window_requested
4883                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4884                         return handle_interrupt_window(&vmx->vcpu);
4885
4886                 err = emulate_instruction(vcpu, 0);
4887
4888                 if (err == EMULATE_DO_MMIO) {
4889                         ret = 0;
4890                         goto out;
4891                 }
4892
4893                 if (err != EMULATE_DONE)
4894                         return 0;
4895
4896                 if (signal_pending(current))
4897                         goto out;
4898                 if (need_resched())
4899                         schedule();
4900         }
4901
4902         vmx->emulation_required = 0;
4903 out:
4904         return ret;
4905 }
4906
4907 /*
4908  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4909  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4910  */
4911 static int handle_pause(struct kvm_vcpu *vcpu)
4912 {
4913         skip_emulated_instruction(vcpu);
4914         kvm_vcpu_on_spin(vcpu);
4915
4916         return 1;
4917 }
4918
4919 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4920 {
4921         kvm_queue_exception(vcpu, UD_VECTOR);
4922         return 1;
4923 }
4924
4925 /*
4926  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4927  * We could reuse a single VMCS for all the L2 guests, but we also want the
4928  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4929  * allows keeping them loaded on the processor, and in the future will allow
4930  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4931  * every entry if they never change.
4932  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4933  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4934  *
4935  * The following functions allocate and free a vmcs02 in this pool.
4936  */
4937
4938 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4939 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4940 {
4941         struct vmcs02_list *item;
4942         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4943                 if (item->vmptr == vmx->nested.current_vmptr) {
4944                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4945                         return &item->vmcs02;
4946                 }
4947
4948         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4949                 /* Recycle the least recently used VMCS. */
4950                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4951                         struct vmcs02_list, list);
4952                 item->vmptr = vmx->nested.current_vmptr;
4953                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4954                 return &item->vmcs02;
4955         }
4956
4957         /* Create a new VMCS */
4958         item = (struct vmcs02_list *)
4959                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4960         if (!item)
4961                 return NULL;
4962         item->vmcs02.vmcs = alloc_vmcs();
4963         if (!item->vmcs02.vmcs) {
4964                 kfree(item);
4965                 return NULL;
4966         }
4967         loaded_vmcs_init(&item->vmcs02);
4968         item->vmptr = vmx->nested.current_vmptr;
4969         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4970         vmx->nested.vmcs02_num++;
4971         return &item->vmcs02;
4972 }
4973
4974 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4975 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4976 {
4977         struct vmcs02_list *item;
4978         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4979                 if (item->vmptr == vmptr) {
4980                         free_loaded_vmcs(&item->vmcs02);
4981                         list_del(&item->list);
4982                         kfree(item);
4983                         vmx->nested.vmcs02_num--;
4984                         return;
4985                 }
4986 }
4987
4988 /*
4989  * Free all VMCSs saved for this vcpu, except the one pointed by
4990  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4991  * currently used, if running L2), and vmcs01 when running L2.
4992  */
4993 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4994 {
4995         struct vmcs02_list *item, *n;
4996         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4997                 if (vmx->loaded_vmcs != &item->vmcs02)
4998                         free_loaded_vmcs(&item->vmcs02);
4999                 list_del(&item->list);
5000                 kfree(item);
5001         }
5002         vmx->nested.vmcs02_num = 0;
5003
5004         if (vmx->loaded_vmcs != &vmx->vmcs01)
5005                 free_loaded_vmcs(&vmx->vmcs01);
5006 }
5007
5008 /*
5009  * Emulate the VMXON instruction.
5010  * Currently, we just remember that VMX is active, and do not save or even
5011  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5012  * do not currently need to store anything in that guest-allocated memory
5013  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5014  * argument is different from the VMXON pointer (which the spec says they do).
5015  */
5016 static int handle_vmon(struct kvm_vcpu *vcpu)
5017 {
5018         struct kvm_segment cs;
5019         struct vcpu_vmx *vmx = to_vmx(vcpu);
5020
5021         /* The Intel VMX Instruction Reference lists a bunch of bits that
5022          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5023          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5024          * Otherwise, we should fail with #UD. We test these now:
5025          */
5026         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5027             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5028             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5029                 kvm_queue_exception(vcpu, UD_VECTOR);
5030                 return 1;
5031         }
5032
5033         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5034         if (is_long_mode(vcpu) && !cs.l) {
5035                 kvm_queue_exception(vcpu, UD_VECTOR);
5036                 return 1;
5037         }
5038
5039         if (vmx_get_cpl(vcpu)) {
5040                 kvm_inject_gp(vcpu, 0);
5041                 return 1;
5042         }
5043
5044         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5045         vmx->nested.vmcs02_num = 0;
5046
5047         vmx->nested.vmxon = true;
5048
5049         skip_emulated_instruction(vcpu);
5050         return 1;
5051 }
5052
5053 /*
5054  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5055  * for running VMX instructions (except VMXON, whose prerequisites are
5056  * slightly different). It also specifies what exception to inject otherwise.
5057  */
5058 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5059 {
5060         struct kvm_segment cs;
5061         struct vcpu_vmx *vmx = to_vmx(vcpu);
5062
5063         if (!vmx->nested.vmxon) {
5064                 kvm_queue_exception(vcpu, UD_VECTOR);
5065                 return 0;
5066         }
5067
5068         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5069         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5070             (is_long_mode(vcpu) && !cs.l)) {
5071                 kvm_queue_exception(vcpu, UD_VECTOR);
5072                 return 0;
5073         }
5074
5075         if (vmx_get_cpl(vcpu)) {
5076                 kvm_inject_gp(vcpu, 0);
5077                 return 0;
5078         }
5079
5080         return 1;
5081 }
5082
5083 /*
5084  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5085  * just stops using VMX.
5086  */
5087 static void free_nested(struct vcpu_vmx *vmx)
5088 {
5089         if (!vmx->nested.vmxon)
5090                 return;
5091         vmx->nested.vmxon = false;
5092         if (vmx->nested.current_vmptr != -1ull) {
5093                 kunmap(vmx->nested.current_vmcs12_page);
5094                 nested_release_page(vmx->nested.current_vmcs12_page);
5095                 vmx->nested.current_vmptr = -1ull;
5096                 vmx->nested.current_vmcs12 = NULL;
5097         }
5098         /* Unpin physical memory we referred to in current vmcs02 */
5099         if (vmx->nested.apic_access_page) {
5100                 nested_release_page(vmx->nested.apic_access_page);
5101                 vmx->nested.apic_access_page = 0;
5102         }
5103
5104         nested_free_all_saved_vmcss(vmx);
5105 }
5106
5107 /* Emulate the VMXOFF instruction */
5108 static int handle_vmoff(struct kvm_vcpu *vcpu)
5109 {
5110         if (!nested_vmx_check_permission(vcpu))
5111                 return 1;
5112         free_nested(to_vmx(vcpu));
5113         skip_emulated_instruction(vcpu);
5114         return 1;
5115 }
5116
5117 /*
5118  * Decode the memory-address operand of a vmx instruction, as recorded on an
5119  * exit caused by such an instruction (run by a guest hypervisor).
5120  * On success, returns 0. When the operand is invalid, returns 1 and throws
5121  * #UD or #GP.
5122  */
5123 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5124                                  unsigned long exit_qualification,
5125                                  u32 vmx_instruction_info, gva_t *ret)
5126 {
5127         /*
5128          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5129          * Execution", on an exit, vmx_instruction_info holds most of the
5130          * addressing components of the operand. Only the displacement part
5131          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5132          * For how an actual address is calculated from all these components,
5133          * refer to Vol. 1, "Operand Addressing".
5134          */
5135         int  scaling = vmx_instruction_info & 3;
5136         int  addr_size = (vmx_instruction_info >> 7) & 7;
5137         bool is_reg = vmx_instruction_info & (1u << 10);
5138         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5139         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5140         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5141         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5142         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5143
5144         if (is_reg) {
5145                 kvm_queue_exception(vcpu, UD_VECTOR);
5146                 return 1;
5147         }
5148
5149         /* Addr = segment_base + offset */
5150         /* offset = base + [index * scale] + displacement */
5151         *ret = vmx_get_segment_base(vcpu, seg_reg);
5152         if (base_is_valid)
5153                 *ret += kvm_register_read(vcpu, base_reg);
5154         if (index_is_valid)
5155                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5156         *ret += exit_qualification; /* holds the displacement */
5157
5158         if (addr_size == 1) /* 32 bit */
5159                 *ret &= 0xffffffff;
5160
5161         /*
5162          * TODO: throw #GP (and return 1) in various cases that the VM*
5163          * instructions require it - e.g., offset beyond segment limit,
5164          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5165          * address, and so on. Currently these are not checked.
5166          */
5167         return 0;
5168 }
5169
5170 /*
5171  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5172  * set the success or error code of an emulated VMX instruction, as specified
5173  * by Vol 2B, VMX Instruction Reference, "Conventions".
5174  */
5175 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5176 {
5177         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5178                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5179                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5180 }
5181
5182 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5183 {
5184         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5185                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5186                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5187                         | X86_EFLAGS_CF);
5188 }
5189
5190 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5191                                         u32 vm_instruction_error)
5192 {
5193         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5194                 /*
5195                  * failValid writes the error number to the current VMCS, which
5196                  * can't be done there isn't a current VMCS.
5197                  */
5198                 nested_vmx_failInvalid(vcpu);
5199                 return;
5200         }
5201         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5202                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5203                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5204                         | X86_EFLAGS_ZF);
5205         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5206 }
5207
5208 /* Emulate the VMCLEAR instruction */
5209 static int handle_vmclear(struct kvm_vcpu *vcpu)
5210 {
5211         struct vcpu_vmx *vmx = to_vmx(vcpu);
5212         gva_t gva;
5213         gpa_t vmptr;
5214         struct vmcs12 *vmcs12;
5215         struct page *page;
5216         struct x86_exception e;
5217
5218         if (!nested_vmx_check_permission(vcpu))
5219                 return 1;
5220
5221         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5222                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5223                 return 1;
5224
5225         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5226                                 sizeof(vmptr), &e)) {
5227                 kvm_inject_page_fault(vcpu, &e);
5228                 return 1;
5229         }
5230
5231         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5232                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5233                 skip_emulated_instruction(vcpu);
5234                 return 1;
5235         }
5236
5237         if (vmptr == vmx->nested.current_vmptr) {
5238                 kunmap(vmx->nested.current_vmcs12_page);
5239                 nested_release_page(vmx->nested.current_vmcs12_page);
5240                 vmx->nested.current_vmptr = -1ull;
5241                 vmx->nested.current_vmcs12 = NULL;
5242         }
5243
5244         page = nested_get_page(vcpu, vmptr);
5245         if (page == NULL) {
5246                 /*
5247                  * For accurate processor emulation, VMCLEAR beyond available
5248                  * physical memory should do nothing at all. However, it is
5249                  * possible that a nested vmx bug, not a guest hypervisor bug,
5250                  * resulted in this case, so let's shut down before doing any
5251                  * more damage:
5252                  */
5253                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5254                 return 1;
5255         }
5256         vmcs12 = kmap(page);
5257         vmcs12->launch_state = 0;
5258         kunmap(page);
5259         nested_release_page(page);
5260
5261         nested_free_vmcs02(vmx, vmptr);
5262
5263         skip_emulated_instruction(vcpu);
5264         nested_vmx_succeed(vcpu);
5265         return 1;
5266 }
5267
5268 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5269
5270 /* Emulate the VMLAUNCH instruction */
5271 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5272 {
5273         return nested_vmx_run(vcpu, true);
5274 }
5275
5276 /* Emulate the VMRESUME instruction */
5277 static int handle_vmresume(struct kvm_vcpu *vcpu)
5278 {
5279
5280         return nested_vmx_run(vcpu, false);
5281 }
5282
5283 enum vmcs_field_type {
5284         VMCS_FIELD_TYPE_U16 = 0,
5285         VMCS_FIELD_TYPE_U64 = 1,
5286         VMCS_FIELD_TYPE_U32 = 2,
5287         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5288 };
5289
5290 static inline int vmcs_field_type(unsigned long field)
5291 {
5292         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5293                 return VMCS_FIELD_TYPE_U32;
5294         return (field >> 13) & 0x3 ;
5295 }
5296
5297 static inline int vmcs_field_readonly(unsigned long field)
5298 {
5299         return (((field >> 10) & 0x3) == 1);
5300 }
5301
5302 /*
5303  * Read a vmcs12 field. Since these can have varying lengths and we return
5304  * one type, we chose the biggest type (u64) and zero-extend the return value
5305  * to that size. Note that the caller, handle_vmread, might need to use only
5306  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5307  * 64-bit fields are to be returned).
5308  */
5309 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5310                                         unsigned long field, u64 *ret)
5311 {
5312         short offset = vmcs_field_to_offset(field);
5313         char *p;
5314
5315         if (offset < 0)
5316                 return 0;
5317
5318         p = ((char *)(get_vmcs12(vcpu))) + offset;
5319
5320         switch (vmcs_field_type(field)) {
5321         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5322                 *ret = *((natural_width *)p);
5323                 return 1;
5324         case VMCS_FIELD_TYPE_U16:
5325                 *ret = *((u16 *)p);
5326                 return 1;
5327         case VMCS_FIELD_TYPE_U32:
5328                 *ret = *((u32 *)p);
5329                 return 1;
5330         case VMCS_FIELD_TYPE_U64:
5331                 *ret = *((u64 *)p);
5332                 return 1;
5333         default:
5334                 return 0; /* can never happen. */
5335         }
5336 }
5337
5338 /*
5339  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5340  * used before) all generate the same failure when it is missing.
5341  */
5342 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5343 {
5344         struct vcpu_vmx *vmx = to_vmx(vcpu);
5345         if (vmx->nested.current_vmptr == -1ull) {
5346                 nested_vmx_failInvalid(vcpu);
5347                 skip_emulated_instruction(vcpu);
5348                 return 0;
5349         }
5350         return 1;
5351 }
5352
5353 static int handle_vmread(struct kvm_vcpu *vcpu)
5354 {
5355         unsigned long field;
5356         u64 field_value;
5357         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5358         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5359         gva_t gva = 0;
5360
5361         if (!nested_vmx_check_permission(vcpu) ||
5362             !nested_vmx_check_vmcs12(vcpu))
5363                 return 1;
5364
5365         /* Decode instruction info and find the field to read */
5366         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5367         /* Read the field, zero-extended to a u64 field_value */
5368         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5369                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5370                 skip_emulated_instruction(vcpu);
5371                 return 1;
5372         }
5373         /*
5374          * Now copy part of this value to register or memory, as requested.
5375          * Note that the number of bits actually copied is 32 or 64 depending
5376          * on the guest's mode (32 or 64 bit), not on the given field's length.
5377          */
5378         if (vmx_instruction_info & (1u << 10)) {
5379                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5380                         field_value);
5381         } else {
5382                 if (get_vmx_mem_address(vcpu, exit_qualification,
5383                                 vmx_instruction_info, &gva))
5384                         return 1;
5385                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5386                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5387                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5388         }
5389
5390         nested_vmx_succeed(vcpu);
5391         skip_emulated_instruction(vcpu);
5392         return 1;
5393 }
5394
5395
5396 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5397 {
5398         unsigned long field;
5399         gva_t gva;
5400         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5401         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5402         char *p;
5403         short offset;
5404         /* The value to write might be 32 or 64 bits, depending on L1's long
5405          * mode, and eventually we need to write that into a field of several
5406          * possible lengths. The code below first zero-extends the value to 64
5407          * bit (field_value), and then copies only the approriate number of
5408          * bits into the vmcs12 field.
5409          */
5410         u64 field_value = 0;
5411         struct x86_exception e;
5412
5413         if (!nested_vmx_check_permission(vcpu) ||
5414             !nested_vmx_check_vmcs12(vcpu))
5415                 return 1;
5416
5417         if (vmx_instruction_info & (1u << 10))
5418                 field_value = kvm_register_read(vcpu,
5419                         (((vmx_instruction_info) >> 3) & 0xf));
5420         else {
5421                 if (get_vmx_mem_address(vcpu, exit_qualification,
5422                                 vmx_instruction_info, &gva))
5423                         return 1;
5424                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5425                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5426                         kvm_inject_page_fault(vcpu, &e);
5427                         return 1;
5428                 }
5429         }
5430
5431
5432         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5433         if (vmcs_field_readonly(field)) {
5434                 nested_vmx_failValid(vcpu,
5435                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5436                 skip_emulated_instruction(vcpu);
5437                 return 1;
5438         }
5439
5440         offset = vmcs_field_to_offset(field);
5441         if (offset < 0) {
5442                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5443                 skip_emulated_instruction(vcpu);
5444                 return 1;
5445         }
5446         p = ((char *) get_vmcs12(vcpu)) + offset;
5447
5448         switch (vmcs_field_type(field)) {
5449         case VMCS_FIELD_TYPE_U16:
5450                 *(u16 *)p = field_value;
5451                 break;
5452         case VMCS_FIELD_TYPE_U32:
5453                 *(u32 *)p = field_value;
5454                 break;
5455         case VMCS_FIELD_TYPE_U64:
5456                 *(u64 *)p = field_value;
5457                 break;
5458         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5459                 *(natural_width *)p = field_value;
5460                 break;
5461         default:
5462                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5463                 skip_emulated_instruction(vcpu);
5464                 return 1;
5465         }
5466
5467         nested_vmx_succeed(vcpu);
5468         skip_emulated_instruction(vcpu);
5469         return 1;
5470 }
5471
5472 /* Emulate the VMPTRLD instruction */
5473 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5474 {
5475         struct vcpu_vmx *vmx = to_vmx(vcpu);
5476         gva_t gva;
5477         gpa_t vmptr;
5478         struct x86_exception e;
5479
5480         if (!nested_vmx_check_permission(vcpu))
5481                 return 1;
5482
5483         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5484                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5485                 return 1;
5486
5487         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5488                                 sizeof(vmptr), &e)) {
5489                 kvm_inject_page_fault(vcpu, &e);
5490                 return 1;
5491         }
5492
5493         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5494                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5495                 skip_emulated_instruction(vcpu);
5496                 return 1;
5497         }
5498
5499         if (vmx->nested.current_vmptr != vmptr) {
5500                 struct vmcs12 *new_vmcs12;
5501                 struct page *page;
5502                 page = nested_get_page(vcpu, vmptr);
5503                 if (page == NULL) {
5504                         nested_vmx_failInvalid(vcpu);
5505                         skip_emulated_instruction(vcpu);
5506                         return 1;
5507                 }
5508                 new_vmcs12 = kmap(page);
5509                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5510                         kunmap(page);
5511                         nested_release_page_clean(page);
5512                         nested_vmx_failValid(vcpu,
5513                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5514                         skip_emulated_instruction(vcpu);
5515                         return 1;
5516                 }
5517                 if (vmx->nested.current_vmptr != -1ull) {
5518                         kunmap(vmx->nested.current_vmcs12_page);
5519                         nested_release_page(vmx->nested.current_vmcs12_page);
5520                 }
5521
5522                 vmx->nested.current_vmptr = vmptr;
5523                 vmx->nested.current_vmcs12 = new_vmcs12;
5524                 vmx->nested.current_vmcs12_page = page;
5525         }
5526
5527         nested_vmx_succeed(vcpu);
5528         skip_emulated_instruction(vcpu);
5529         return 1;
5530 }
5531
5532 /* Emulate the VMPTRST instruction */
5533 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5534 {
5535         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5536         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5537         gva_t vmcs_gva;
5538         struct x86_exception e;
5539
5540         if (!nested_vmx_check_permission(vcpu))
5541                 return 1;
5542
5543         if (get_vmx_mem_address(vcpu, exit_qualification,
5544                         vmx_instruction_info, &vmcs_gva))
5545                 return 1;
5546         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5547         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5548                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5549                                  sizeof(u64), &e)) {
5550                 kvm_inject_page_fault(vcpu, &e);
5551                 return 1;
5552         }
5553         nested_vmx_succeed(vcpu);
5554         skip_emulated_instruction(vcpu);
5555         return 1;
5556 }
5557
5558 /*
5559  * The exit handlers return 1 if the exit was handled fully and guest execution
5560  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5561  * to be done to userspace and return 0.
5562  */
5563 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5564         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5565         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5566         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5567         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5568         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5569         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5570         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5571         [EXIT_REASON_CPUID]                   = handle_cpuid,
5572         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5573         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5574         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5575         [EXIT_REASON_HLT]                     = handle_halt,
5576         [EXIT_REASON_INVD]                    = handle_invd,
5577         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5578         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5579         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5580         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5581         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5582         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5583         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5584         [EXIT_REASON_VMREAD]                  = handle_vmread,
5585         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5586         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5587         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5588         [EXIT_REASON_VMON]                    = handle_vmon,
5589         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5590         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5591         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5592         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5593         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5594         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5595         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5596         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5597         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5598         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5599         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5600 };
5601
5602 static const int kvm_vmx_max_exit_handlers =
5603         ARRAY_SIZE(kvm_vmx_exit_handlers);
5604
5605 /*
5606  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5607  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5608  * disinterest in the current event (read or write a specific MSR) by using an
5609  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5610  */
5611 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5612         struct vmcs12 *vmcs12, u32 exit_reason)
5613 {
5614         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5615         gpa_t bitmap;
5616
5617         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5618                 return 1;
5619
5620         /*
5621          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5622          * for the four combinations of read/write and low/high MSR numbers.
5623          * First we need to figure out which of the four to use:
5624          */
5625         bitmap = vmcs12->msr_bitmap;
5626         if (exit_reason == EXIT_REASON_MSR_WRITE)
5627                 bitmap += 2048;
5628         if (msr_index >= 0xc0000000) {
5629                 msr_index -= 0xc0000000;
5630                 bitmap += 1024;
5631         }
5632
5633         /* Then read the msr_index'th bit from this bitmap: */
5634         if (msr_index < 1024*8) {
5635                 unsigned char b;
5636                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5637                 return 1 & (b >> (msr_index & 7));
5638         } else
5639                 return 1; /* let L1 handle the wrong parameter */
5640 }
5641
5642 /*
5643  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5644  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5645  * intercept (via guest_host_mask etc.) the current event.
5646  */
5647 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5648         struct vmcs12 *vmcs12)
5649 {
5650         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5651         int cr = exit_qualification & 15;
5652         int reg = (exit_qualification >> 8) & 15;
5653         unsigned long val = kvm_register_read(vcpu, reg);
5654
5655         switch ((exit_qualification >> 4) & 3) {
5656         case 0: /* mov to cr */
5657                 switch (cr) {
5658                 case 0:
5659                         if (vmcs12->cr0_guest_host_mask &
5660                             (val ^ vmcs12->cr0_read_shadow))
5661                                 return 1;
5662                         break;
5663                 case 3:
5664                         if ((vmcs12->cr3_target_count >= 1 &&
5665                                         vmcs12->cr3_target_value0 == val) ||
5666                                 (vmcs12->cr3_target_count >= 2 &&
5667                                         vmcs12->cr3_target_value1 == val) ||
5668                                 (vmcs12->cr3_target_count >= 3 &&
5669                                         vmcs12->cr3_target_value2 == val) ||
5670                                 (vmcs12->cr3_target_count >= 4 &&
5671                                         vmcs12->cr3_target_value3 == val))
5672                                 return 0;
5673                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5674                                 return 1;
5675                         break;
5676                 case 4:
5677                         if (vmcs12->cr4_guest_host_mask &
5678                             (vmcs12->cr4_read_shadow ^ val))
5679                                 return 1;
5680                         break;
5681                 case 8:
5682                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5683                                 return 1;
5684                         break;
5685                 }
5686                 break;
5687         case 2: /* clts */
5688                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5689                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5690                         return 1;
5691                 break;
5692         case 1: /* mov from cr */
5693                 switch (cr) {
5694                 case 3:
5695                         if (vmcs12->cpu_based_vm_exec_control &
5696                             CPU_BASED_CR3_STORE_EXITING)
5697                                 return 1;
5698                         break;
5699                 case 8:
5700                         if (vmcs12->cpu_based_vm_exec_control &
5701                             CPU_BASED_CR8_STORE_EXITING)
5702                                 return 1;
5703                         break;
5704                 }
5705                 break;
5706         case 3: /* lmsw */
5707                 /*
5708                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5709                  * cr0. Other attempted changes are ignored, with no exit.
5710                  */
5711                 if (vmcs12->cr0_guest_host_mask & 0xe &
5712                     (val ^ vmcs12->cr0_read_shadow))
5713                         return 1;
5714                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5715                     !(vmcs12->cr0_read_shadow & 0x1) &&
5716                     (val & 0x1))
5717                         return 1;
5718                 break;
5719         }
5720         return 0;
5721 }
5722
5723 /*
5724  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5725  * should handle it ourselves in L0 (and then continue L2). Only call this
5726  * when in is_guest_mode (L2).
5727  */
5728 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5729 {
5730         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5731         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5732         struct vcpu_vmx *vmx = to_vmx(vcpu);
5733         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5734
5735         if (vmx->nested.nested_run_pending)
5736                 return 0;
5737
5738         if (unlikely(vmx->fail)) {
5739                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5740                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5741                 return 1;
5742         }
5743
5744         switch (exit_reason) {
5745         case EXIT_REASON_EXCEPTION_NMI:
5746                 if (!is_exception(intr_info))
5747                         return 0;
5748                 else if (is_page_fault(intr_info))
5749                         return enable_ept;
5750                 return vmcs12->exception_bitmap &
5751                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5752         case EXIT_REASON_EXTERNAL_INTERRUPT:
5753                 return 0;
5754         case EXIT_REASON_TRIPLE_FAULT:
5755                 return 1;
5756         case EXIT_REASON_PENDING_INTERRUPT:
5757         case EXIT_REASON_NMI_WINDOW:
5758                 /*
5759                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5760                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5761                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5762                  * Same for NMI Window Exiting.
5763                  */
5764                 return 1;
5765         case EXIT_REASON_TASK_SWITCH:
5766                 return 1;
5767         case EXIT_REASON_CPUID:
5768                 return 1;
5769         case EXIT_REASON_HLT:
5770                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5771         case EXIT_REASON_INVD:
5772                 return 1;
5773         case EXIT_REASON_INVLPG:
5774                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5775         case EXIT_REASON_RDPMC:
5776                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5777         case EXIT_REASON_RDTSC:
5778                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5779         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5780         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5781         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5782         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5783         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5784                 /*
5785                  * VMX instructions trap unconditionally. This allows L1 to
5786                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5787                  */
5788                 return 1;
5789         case EXIT_REASON_CR_ACCESS:
5790                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5791         case EXIT_REASON_DR_ACCESS:
5792                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5793         case EXIT_REASON_IO_INSTRUCTION:
5794                 /* TODO: support IO bitmaps */
5795                 return 1;
5796         case EXIT_REASON_MSR_READ:
5797         case EXIT_REASON_MSR_WRITE:
5798                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5799         case EXIT_REASON_INVALID_STATE:
5800                 return 1;
5801         case EXIT_REASON_MWAIT_INSTRUCTION:
5802                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5803         case EXIT_REASON_MONITOR_INSTRUCTION:
5804                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5805         case EXIT_REASON_PAUSE_INSTRUCTION:
5806                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5807                         nested_cpu_has2(vmcs12,
5808                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5809         case EXIT_REASON_MCE_DURING_VMENTRY:
5810                 return 0;
5811         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5812                 return 1;
5813         case EXIT_REASON_APIC_ACCESS:
5814                 return nested_cpu_has2(vmcs12,
5815                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5816         case EXIT_REASON_EPT_VIOLATION:
5817         case EXIT_REASON_EPT_MISCONFIG:
5818                 return 0;
5819         case EXIT_REASON_WBINVD:
5820                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5821         case EXIT_REASON_XSETBV:
5822                 return 1;
5823         default:
5824                 return 1;
5825         }
5826 }
5827
5828 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5829 {
5830         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5831         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5832 }
5833
5834 /*
5835  * The guest has exited.  See if we can fix it or if we need userspace
5836  * assistance.
5837  */
5838 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5839 {
5840         struct vcpu_vmx *vmx = to_vmx(vcpu);
5841         u32 exit_reason = vmx->exit_reason;
5842         u32 vectoring_info = vmx->idt_vectoring_info;
5843
5844         /* If guest state is invalid, start emulating */
5845         if (vmx->emulation_required && emulate_invalid_guest_state)
5846                 return handle_invalid_guest_state(vcpu);
5847
5848         /*
5849          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5850          * we did not inject a still-pending event to L1 now because of
5851          * nested_run_pending, we need to re-enable this bit.
5852          */
5853         if (vmx->nested.nested_run_pending)
5854                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5855
5856         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5857             exit_reason == EXIT_REASON_VMRESUME))
5858                 vmx->nested.nested_run_pending = 1;
5859         else
5860                 vmx->nested.nested_run_pending = 0;
5861
5862         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5863                 nested_vmx_vmexit(vcpu);
5864                 return 1;
5865         }
5866
5867         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5868                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5869                 vcpu->run->fail_entry.hardware_entry_failure_reason
5870                         = exit_reason;
5871                 return 0;
5872         }
5873
5874         if (unlikely(vmx->fail)) {
5875                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5876                 vcpu->run->fail_entry.hardware_entry_failure_reason
5877                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5878                 return 0;
5879         }
5880
5881         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5882                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5883                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5884                         exit_reason != EXIT_REASON_TASK_SWITCH))
5885                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5886                        "(0x%x) and exit reason is 0x%x\n",
5887                        __func__, vectoring_info, exit_reason);
5888
5889         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5890             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5891                                         get_vmcs12(vcpu), vcpu)))) {
5892                 if (vmx_interrupt_allowed(vcpu)) {
5893                         vmx->soft_vnmi_blocked = 0;
5894                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5895                            vcpu->arch.nmi_pending) {
5896                         /*
5897                          * This CPU don't support us in finding the end of an
5898                          * NMI-blocked window if the guest runs with IRQs
5899                          * disabled. So we pull the trigger after 1 s of
5900                          * futile waiting, but inform the user about this.
5901                          */
5902                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5903                                "state on VCPU %d after 1 s timeout\n",
5904                                __func__, vcpu->vcpu_id);
5905                         vmx->soft_vnmi_blocked = 0;
5906                 }
5907         }
5908
5909         if (exit_reason < kvm_vmx_max_exit_handlers
5910             && kvm_vmx_exit_handlers[exit_reason])
5911                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5912         else {
5913                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5914                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5915         }
5916         return 0;
5917 }
5918
5919 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5920 {
5921         if (irr == -1 || tpr < irr) {
5922                 vmcs_write32(TPR_THRESHOLD, 0);
5923                 return;
5924         }
5925
5926         vmcs_write32(TPR_THRESHOLD, irr);
5927 }
5928
5929 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5930 {
5931         u32 exit_intr_info;
5932
5933         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5934               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5935                 return;
5936
5937         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5938         exit_intr_info = vmx->exit_intr_info;
5939
5940         /* Handle machine checks before interrupts are enabled */
5941         if (is_machine_check(exit_intr_info))
5942                 kvm_machine_check();
5943
5944         /* We need to handle NMIs before interrupts are enabled */
5945         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5946             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5947                 kvm_before_handle_nmi(&vmx->vcpu);
5948                 asm("int $2");
5949                 kvm_after_handle_nmi(&vmx->vcpu);
5950         }
5951 }
5952
5953 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5954 {
5955         u32 exit_intr_info;
5956         bool unblock_nmi;
5957         u8 vector;
5958         bool idtv_info_valid;
5959
5960         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5961
5962         if (cpu_has_virtual_nmis()) {
5963                 if (vmx->nmi_known_unmasked)
5964                         return;
5965                 /*
5966                  * Can't use vmx->exit_intr_info since we're not sure what
5967                  * the exit reason is.
5968                  */
5969                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5970                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5971                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5972                 /*
5973                  * SDM 3: 27.7.1.2 (September 2008)
5974                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5975                  * a guest IRET fault.
5976                  * SDM 3: 23.2.2 (September 2008)
5977                  * Bit 12 is undefined in any of the following cases:
5978                  *  If the VM exit sets the valid bit in the IDT-vectoring
5979                  *   information field.
5980                  *  If the VM exit is due to a double fault.
5981                  */
5982                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5983                     vector != DF_VECTOR && !idtv_info_valid)
5984                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5985                                       GUEST_INTR_STATE_NMI);
5986                 else
5987                         vmx->nmi_known_unmasked =
5988                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5989                                   & GUEST_INTR_STATE_NMI);
5990         } else if (unlikely(vmx->soft_vnmi_blocked))
5991                 vmx->vnmi_blocked_time +=
5992                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5993 }
5994
5995 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5996                                       u32 idt_vectoring_info,
5997                                       int instr_len_field,
5998                                       int error_code_field)
5999 {
6000         u8 vector;
6001         int type;
6002         bool idtv_info_valid;
6003
6004         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6005
6006         vmx->vcpu.arch.nmi_injected = false;
6007         kvm_clear_exception_queue(&vmx->vcpu);
6008         kvm_clear_interrupt_queue(&vmx->vcpu);
6009
6010         if (!idtv_info_valid)
6011                 return;
6012
6013         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6014
6015         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6016         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6017
6018         switch (type) {
6019         case INTR_TYPE_NMI_INTR:
6020                 vmx->vcpu.arch.nmi_injected = true;
6021                 /*
6022                  * SDM 3: 27.7.1.2 (September 2008)
6023                  * Clear bit "block by NMI" before VM entry if a NMI
6024                  * delivery faulted.
6025                  */
6026                 vmx_set_nmi_mask(&vmx->vcpu, false);
6027                 break;
6028         case INTR_TYPE_SOFT_EXCEPTION:
6029                 vmx->vcpu.arch.event_exit_inst_len =
6030                         vmcs_read32(instr_len_field);
6031                 /* fall through */
6032         case INTR_TYPE_HARD_EXCEPTION:
6033                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6034                         u32 err = vmcs_read32(error_code_field);
6035                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6036                 } else
6037                         kvm_queue_exception(&vmx->vcpu, vector);
6038                 break;
6039         case INTR_TYPE_SOFT_INTR:
6040                 vmx->vcpu.arch.event_exit_inst_len =
6041                         vmcs_read32(instr_len_field);
6042                 /* fall through */
6043         case INTR_TYPE_EXT_INTR:
6044                 kvm_queue_interrupt(&vmx->vcpu, vector,
6045                         type == INTR_TYPE_SOFT_INTR);
6046                 break;
6047         default:
6048                 break;
6049         }
6050 }
6051
6052 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6053 {
6054         if (is_guest_mode(&vmx->vcpu))
6055                 return;
6056         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6057                                   VM_EXIT_INSTRUCTION_LEN,
6058                                   IDT_VECTORING_ERROR_CODE);
6059 }
6060
6061 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6062 {
6063         if (is_guest_mode(vcpu))
6064                 return;
6065         __vmx_complete_interrupts(to_vmx(vcpu),
6066                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6067                                   VM_ENTRY_INSTRUCTION_LEN,
6068                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6069
6070         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6071 }
6072
6073 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6074 {
6075         int i, nr_msrs;
6076         struct perf_guest_switch_msr *msrs;
6077
6078         msrs = perf_guest_get_msrs(&nr_msrs);
6079
6080         if (!msrs)
6081                 return;
6082
6083         for (i = 0; i < nr_msrs; i++)
6084                 if (msrs[i].host == msrs[i].guest)
6085                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6086                 else
6087                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6088                                         msrs[i].host);
6089 }
6090
6091 #ifdef CONFIG_X86_64
6092 #define R "r"
6093 #define Q "q"
6094 #else
6095 #define R "e"
6096 #define Q "l"
6097 #endif
6098
6099 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6100 {
6101         struct vcpu_vmx *vmx = to_vmx(vcpu);
6102
6103         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6104                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6105                 if (vmcs12->idt_vectoring_info_field &
6106                                 VECTORING_INFO_VALID_MASK) {
6107                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6108                                 vmcs12->idt_vectoring_info_field);
6109                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6110                                 vmcs12->vm_exit_instruction_len);
6111                         if (vmcs12->idt_vectoring_info_field &
6112                                         VECTORING_INFO_DELIVER_CODE_MASK)
6113                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6114                                         vmcs12->idt_vectoring_error_code);
6115                 }
6116         }
6117
6118         /* Record the guest's net vcpu time for enforced NMI injections. */
6119         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6120                 vmx->entry_time = ktime_get();
6121
6122         /* Don't enter VMX if guest state is invalid, let the exit handler
6123            start emulation until we arrive back to a valid state */
6124         if (vmx->emulation_required && emulate_invalid_guest_state)
6125                 return;
6126
6127         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6128                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6129         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6130                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6131
6132         /* When single-stepping over STI and MOV SS, we must clear the
6133          * corresponding interruptibility bits in the guest state. Otherwise
6134          * vmentry fails as it then expects bit 14 (BS) in pending debug
6135          * exceptions being set, but that's not correct for the guest debugging
6136          * case. */
6137         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6138                 vmx_set_interrupt_shadow(vcpu, 0);
6139
6140         atomic_switch_perf_msrs(vmx);
6141
6142         vmx->__launched = vmx->loaded_vmcs->launched;
6143         asm(
6144                 /* Store host registers */
6145                 "push %%"R"dx; push %%"R"bp;"
6146                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6147                 "push %%"R"cx \n\t"
6148                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6149                 "je 1f \n\t"
6150                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6151                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6152                 "1: \n\t"
6153                 /* Reload cr2 if changed */
6154                 "mov %c[cr2](%0), %%"R"ax \n\t"
6155                 "mov %%cr2, %%"R"dx \n\t"
6156                 "cmp %%"R"ax, %%"R"dx \n\t"
6157                 "je 2f \n\t"
6158                 "mov %%"R"ax, %%cr2 \n\t"
6159                 "2: \n\t"
6160                 /* Check if vmlaunch of vmresume is needed */
6161                 "cmpl $0, %c[launched](%0) \n\t"
6162                 /* Load guest registers.  Don't clobber flags. */
6163                 "mov %c[rax](%0), %%"R"ax \n\t"
6164                 "mov %c[rbx](%0), %%"R"bx \n\t"
6165                 "mov %c[rdx](%0), %%"R"dx \n\t"
6166                 "mov %c[rsi](%0), %%"R"si \n\t"
6167                 "mov %c[rdi](%0), %%"R"di \n\t"
6168                 "mov %c[rbp](%0), %%"R"bp \n\t"
6169 #ifdef CONFIG_X86_64
6170                 "mov %c[r8](%0),  %%r8  \n\t"
6171                 "mov %c[r9](%0),  %%r9  \n\t"
6172                 "mov %c[r10](%0), %%r10 \n\t"
6173                 "mov %c[r11](%0), %%r11 \n\t"
6174                 "mov %c[r12](%0), %%r12 \n\t"
6175                 "mov %c[r13](%0), %%r13 \n\t"
6176                 "mov %c[r14](%0), %%r14 \n\t"
6177                 "mov %c[r15](%0), %%r15 \n\t"
6178 #endif
6179                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6180
6181                 /* Enter guest mode */
6182                 "jne .Llaunched \n\t"
6183                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6184                 "jmp .Lkvm_vmx_return \n\t"
6185                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6186                 ".Lkvm_vmx_return: "
6187                 /* Save guest registers, load host registers, keep flags */
6188                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6189                 "pop %0 \n\t"
6190                 "mov %%"R"ax, %c[rax](%0) \n\t"
6191                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6192                 "pop"Q" %c[rcx](%0) \n\t"
6193                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6194                 "mov %%"R"si, %c[rsi](%0) \n\t"
6195                 "mov %%"R"di, %c[rdi](%0) \n\t"
6196                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6197 #ifdef CONFIG_X86_64
6198                 "mov %%r8,  %c[r8](%0) \n\t"
6199                 "mov %%r9,  %c[r9](%0) \n\t"
6200                 "mov %%r10, %c[r10](%0) \n\t"
6201                 "mov %%r11, %c[r11](%0) \n\t"
6202                 "mov %%r12, %c[r12](%0) \n\t"
6203                 "mov %%r13, %c[r13](%0) \n\t"
6204                 "mov %%r14, %c[r14](%0) \n\t"
6205                 "mov %%r15, %c[r15](%0) \n\t"
6206 #endif
6207                 "mov %%cr2, %%"R"ax   \n\t"
6208                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6209
6210                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6211                 "setbe %c[fail](%0) \n\t"
6212               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6213                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6214                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6215                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6216                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6217                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6218                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6219                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6220                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6221                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6222                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6223 #ifdef CONFIG_X86_64
6224                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6225                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6226                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6227                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6228                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6229                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6230                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6231                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6232 #endif
6233                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6234                 [wordsize]"i"(sizeof(ulong))
6235               : "cc", "memory"
6236                 , R"ax", R"bx", R"di", R"si"
6237 #ifdef CONFIG_X86_64
6238                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6239 #endif
6240               );
6241
6242         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6243                                   | (1 << VCPU_EXREG_RFLAGS)
6244                                   | (1 << VCPU_EXREG_CPL)
6245                                   | (1 << VCPU_EXREG_PDPTR)
6246                                   | (1 << VCPU_EXREG_SEGMENTS)
6247                                   | (1 << VCPU_EXREG_CR3));
6248         vcpu->arch.regs_dirty = 0;
6249
6250         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6251
6252         if (is_guest_mode(vcpu)) {
6253                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6254                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6255                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6256                         vmcs12->idt_vectoring_error_code =
6257                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6258                         vmcs12->vm_exit_instruction_len =
6259                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6260                 }
6261         }
6262
6263         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6264         vmx->loaded_vmcs->launched = 1;
6265
6266         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6267         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6268
6269         vmx_complete_atomic_exit(vmx);
6270         vmx_recover_nmi_blocking(vmx);
6271         vmx_complete_interrupts(vmx);
6272 }
6273
6274 #undef R
6275 #undef Q
6276
6277 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6278 {
6279         struct vcpu_vmx *vmx = to_vmx(vcpu);
6280
6281         free_vpid(vmx);
6282         free_nested(vmx);
6283         free_loaded_vmcs(vmx->loaded_vmcs);
6284         kfree(vmx->guest_msrs);
6285         kvm_vcpu_uninit(vcpu);
6286         kmem_cache_free(kvm_vcpu_cache, vmx);
6287 }
6288
6289 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6290 {
6291         int err;
6292         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6293         int cpu;
6294
6295         if (!vmx)
6296                 return ERR_PTR(-ENOMEM);
6297
6298         allocate_vpid(vmx);
6299
6300         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6301         if (err)
6302                 goto free_vcpu;
6303
6304         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6305         err = -ENOMEM;
6306         if (!vmx->guest_msrs) {
6307                 goto uninit_vcpu;
6308         }
6309
6310         vmx->loaded_vmcs = &vmx->vmcs01;
6311         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6312         if (!vmx->loaded_vmcs->vmcs)
6313                 goto free_msrs;
6314         if (!vmm_exclusive)
6315                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6316         loaded_vmcs_init(vmx->loaded_vmcs);
6317         if (!vmm_exclusive)
6318                 kvm_cpu_vmxoff();
6319
6320         cpu = get_cpu();
6321         vmx_vcpu_load(&vmx->vcpu, cpu);
6322         vmx->vcpu.cpu = cpu;
6323         err = vmx_vcpu_setup(vmx);
6324         vmx_vcpu_put(&vmx->vcpu);
6325         put_cpu();
6326         if (err)
6327                 goto free_vmcs;
6328         if (vm_need_virtualize_apic_accesses(kvm))
6329                 err = alloc_apic_access_page(kvm);
6330                 if (err)
6331                         goto free_vmcs;
6332
6333         if (enable_ept) {
6334                 if (!kvm->arch.ept_identity_map_addr)
6335                         kvm->arch.ept_identity_map_addr =
6336                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6337                 err = -ENOMEM;
6338                 if (alloc_identity_pagetable(kvm) != 0)
6339                         goto free_vmcs;
6340                 if (!init_rmode_identity_map(kvm))
6341                         goto free_vmcs;
6342         }
6343
6344         vmx->nested.current_vmptr = -1ull;
6345         vmx->nested.current_vmcs12 = NULL;
6346
6347         return &vmx->vcpu;
6348
6349 free_vmcs:
6350         free_vmcs(vmx->loaded_vmcs->vmcs);
6351 free_msrs:
6352         kfree(vmx->guest_msrs);
6353 uninit_vcpu:
6354         kvm_vcpu_uninit(&vmx->vcpu);
6355 free_vcpu:
6356         free_vpid(vmx);
6357         kmem_cache_free(kvm_vcpu_cache, vmx);
6358         return ERR_PTR(err);
6359 }
6360
6361 static void __init vmx_check_processor_compat(void *rtn)
6362 {
6363         struct vmcs_config vmcs_conf;
6364
6365         *(int *)rtn = 0;
6366         if (setup_vmcs_config(&vmcs_conf) < 0)
6367                 *(int *)rtn = -EIO;
6368         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6369                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6370                                 smp_processor_id());
6371                 *(int *)rtn = -EIO;
6372         }
6373 }
6374
6375 static int get_ept_level(void)
6376 {
6377         return VMX_EPT_DEFAULT_GAW + 1;
6378 }
6379
6380 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6381 {
6382         u64 ret;
6383
6384         /* For VT-d and EPT combination
6385          * 1. MMIO: always map as UC
6386          * 2. EPT with VT-d:
6387          *   a. VT-d without snooping control feature: can't guarantee the
6388          *      result, try to trust guest.
6389          *   b. VT-d with snooping control feature: snooping control feature of
6390          *      VT-d engine can guarantee the cache correctness. Just set it
6391          *      to WB to keep consistent with host. So the same as item 3.
6392          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6393          *    consistent with host MTRR
6394          */
6395         if (is_mmio)
6396                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6397         else if (vcpu->kvm->arch.iommu_domain &&
6398                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6399                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6400                       VMX_EPT_MT_EPTE_SHIFT;
6401         else
6402                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6403                         | VMX_EPT_IPAT_BIT;
6404
6405         return ret;
6406 }
6407
6408 static int vmx_get_lpage_level(void)
6409 {
6410         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6411                 return PT_DIRECTORY_LEVEL;
6412         else
6413                 /* For shadow and EPT supported 1GB page */
6414                 return PT_PDPE_LEVEL;
6415 }
6416
6417 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6418 {
6419         struct kvm_cpuid_entry2 *best;
6420         struct vcpu_vmx *vmx = to_vmx(vcpu);
6421         u32 exec_control;
6422
6423         vmx->rdtscp_enabled = false;
6424         if (vmx_rdtscp_supported()) {
6425                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6426                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6427                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6428                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6429                                 vmx->rdtscp_enabled = true;
6430                         else {
6431                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6432                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6433                                                 exec_control);
6434                         }
6435                 }
6436         }
6437 }
6438
6439 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6440 {
6441         if (func == 1 && nested)
6442                 entry->ecx |= bit(X86_FEATURE_VMX);
6443 }
6444
6445 /*
6446  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6447  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6448  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6449  * guest in a way that will both be appropriate to L1's requests, and our
6450  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6451  * function also has additional necessary side-effects, like setting various
6452  * vcpu->arch fields.
6453  */
6454 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6455 {
6456         struct vcpu_vmx *vmx = to_vmx(vcpu);
6457         u32 exec_control;
6458
6459         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6460         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6461         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6462         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6463         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6464         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6465         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6466         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6467         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6468         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6469         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6470         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6471         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6472         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6473         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6474         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6475         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6476         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6477         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6478         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6479         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6480         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6481         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6482         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6483         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6484         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6485         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6486         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6487         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6488         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6489         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6490         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6491         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6492         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6493         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6494         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6495
6496         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6497         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6498                 vmcs12->vm_entry_intr_info_field);
6499         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6500                 vmcs12->vm_entry_exception_error_code);
6501         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6502                 vmcs12->vm_entry_instruction_len);
6503         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6504                 vmcs12->guest_interruptibility_info);
6505         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6506         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6507         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6508         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6509         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6510                 vmcs12->guest_pending_dbg_exceptions);
6511         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6512         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6513
6514         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6515
6516         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6517                 (vmcs_config.pin_based_exec_ctrl |
6518                  vmcs12->pin_based_vm_exec_control));
6519
6520         /*
6521          * Whether page-faults are trapped is determined by a combination of
6522          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6523          * If enable_ept, L0 doesn't care about page faults and we should
6524          * set all of these to L1's desires. However, if !enable_ept, L0 does
6525          * care about (at least some) page faults, and because it is not easy
6526          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6527          * to exit on each and every L2 page fault. This is done by setting
6528          * MASK=MATCH=0 and (see below) EB.PF=1.
6529          * Note that below we don't need special code to set EB.PF beyond the
6530          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6531          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6532          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6533          *
6534          * A problem with this approach (when !enable_ept) is that L1 may be
6535          * injected with more page faults than it asked for. This could have
6536          * caused problems, but in practice existing hypervisors don't care.
6537          * To fix this, we will need to emulate the PFEC checking (on the L1
6538          * page tables), using walk_addr(), when injecting PFs to L1.
6539          */
6540         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6541                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6542         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6543                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6544
6545         if (cpu_has_secondary_exec_ctrls()) {
6546                 u32 exec_control = vmx_secondary_exec_control(vmx);
6547                 if (!vmx->rdtscp_enabled)
6548                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6549                 /* Take the following fields only from vmcs12 */
6550                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6551                 if (nested_cpu_has(vmcs12,
6552                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6553                         exec_control |= vmcs12->secondary_vm_exec_control;
6554
6555                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6556                         /*
6557                          * Translate L1 physical address to host physical
6558                          * address for vmcs02. Keep the page pinned, so this
6559                          * physical address remains valid. We keep a reference
6560                          * to it so we can release it later.
6561                          */
6562                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6563                                 nested_release_page(vmx->nested.apic_access_page);
6564                         vmx->nested.apic_access_page =
6565                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6566                         /*
6567                          * If translation failed, no matter: This feature asks
6568                          * to exit when accessing the given address, and if it
6569                          * can never be accessed, this feature won't do
6570                          * anything anyway.
6571                          */
6572                         if (!vmx->nested.apic_access_page)
6573                                 exec_control &=
6574                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6575                         else
6576                                 vmcs_write64(APIC_ACCESS_ADDR,
6577                                   page_to_phys(vmx->nested.apic_access_page));
6578                 }
6579
6580                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6581         }
6582
6583
6584         /*
6585          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6586          * Some constant fields are set here by vmx_set_constant_host_state().
6587          * Other fields are different per CPU, and will be set later when
6588          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6589          */
6590         vmx_set_constant_host_state();
6591
6592         /*
6593          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6594          * entry, but only if the current (host) sp changed from the value
6595          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6596          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6597          * here we just force the write to happen on entry.
6598          */
6599         vmx->host_rsp = 0;
6600
6601         exec_control = vmx_exec_control(vmx); /* L0's desires */
6602         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6603         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6604         exec_control &= ~CPU_BASED_TPR_SHADOW;
6605         exec_control |= vmcs12->cpu_based_vm_exec_control;
6606         /*
6607          * Merging of IO and MSR bitmaps not currently supported.
6608          * Rather, exit every time.
6609          */
6610         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6611         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6612         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6613
6614         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6615
6616         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6617          * bitwise-or of what L1 wants to trap for L2, and what we want to
6618          * trap. Note that CR0.TS also needs updating - we do this later.
6619          */
6620         update_exception_bitmap(vcpu);
6621         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6622         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6623
6624         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6625         vmcs_write32(VM_EXIT_CONTROLS,
6626                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6627         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6628                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6629
6630         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6631                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6632         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6633                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6634
6635
6636         set_cr4_guest_host_mask(vmx);
6637
6638         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6639                 vmcs_write64(TSC_OFFSET,
6640                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6641         else
6642                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6643
6644         if (enable_vpid) {
6645                 /*
6646                  * Trivially support vpid by letting L2s share their parent
6647                  * L1's vpid. TODO: move to a more elaborate solution, giving
6648                  * each L2 its own vpid and exposing the vpid feature to L1.
6649                  */
6650                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6651                 vmx_flush_tlb(vcpu);
6652         }
6653
6654         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6655                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6656         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6657                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6658         else
6659                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6660         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6661         vmx_set_efer(vcpu, vcpu->arch.efer);
6662
6663         /*
6664          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6665          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6666          * The CR0_READ_SHADOW is what L2 should have expected to read given
6667          * the specifications by L1; It's not enough to take
6668          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6669          * have more bits than L1 expected.
6670          */
6671         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6672         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6673
6674         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6675         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6676
6677         /* shadow page tables on either EPT or shadow page tables */
6678         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6679         kvm_mmu_reset_context(vcpu);
6680
6681         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6682         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6683 }
6684
6685 /*
6686  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6687  * for running an L2 nested guest.
6688  */
6689 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6690 {
6691         struct vmcs12 *vmcs12;
6692         struct vcpu_vmx *vmx = to_vmx(vcpu);
6693         int cpu;
6694         struct loaded_vmcs *vmcs02;
6695
6696         if (!nested_vmx_check_permission(vcpu) ||
6697             !nested_vmx_check_vmcs12(vcpu))
6698                 return 1;
6699
6700         skip_emulated_instruction(vcpu);
6701         vmcs12 = get_vmcs12(vcpu);
6702
6703         /*
6704          * The nested entry process starts with enforcing various prerequisites
6705          * on vmcs12 as required by the Intel SDM, and act appropriately when
6706          * they fail: As the SDM explains, some conditions should cause the
6707          * instruction to fail, while others will cause the instruction to seem
6708          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6709          * To speed up the normal (success) code path, we should avoid checking
6710          * for misconfigurations which will anyway be caught by the processor
6711          * when using the merged vmcs02.
6712          */
6713         if (vmcs12->launch_state == launch) {
6714                 nested_vmx_failValid(vcpu,
6715                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6716                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6717                 return 1;
6718         }
6719
6720         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6721                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6722                 /*TODO: Also verify bits beyond physical address width are 0*/
6723                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6724                 return 1;
6725         }
6726
6727         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6728                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6729                 /*TODO: Also verify bits beyond physical address width are 0*/
6730                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6731                 return 1;
6732         }
6733
6734         if (vmcs12->vm_entry_msr_load_count > 0 ||
6735             vmcs12->vm_exit_msr_load_count > 0 ||
6736             vmcs12->vm_exit_msr_store_count > 0) {
6737                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6738                                     __func__);
6739                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6740                 return 1;
6741         }
6742
6743         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6744               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6745             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6746               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6747             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6748               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6749             !vmx_control_verify(vmcs12->vm_exit_controls,
6750               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6751             !vmx_control_verify(vmcs12->vm_entry_controls,
6752               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6753         {
6754                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6755                 return 1;
6756         }
6757
6758         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6759             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6760                 nested_vmx_failValid(vcpu,
6761                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6762                 return 1;
6763         }
6764
6765         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6766             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6767                 nested_vmx_entry_failure(vcpu, vmcs12,
6768                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6769                 return 1;
6770         }
6771         if (vmcs12->vmcs_link_pointer != -1ull) {
6772                 nested_vmx_entry_failure(vcpu, vmcs12,
6773                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6774                 return 1;
6775         }
6776
6777         /*
6778          * We're finally done with prerequisite checking, and can start with
6779          * the nested entry.
6780          */
6781
6782         vmcs02 = nested_get_current_vmcs02(vmx);
6783         if (!vmcs02)
6784                 return -ENOMEM;
6785
6786         enter_guest_mode(vcpu);
6787
6788         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6789
6790         cpu = get_cpu();
6791         vmx->loaded_vmcs = vmcs02;
6792         vmx_vcpu_put(vcpu);
6793         vmx_vcpu_load(vcpu, cpu);
6794         vcpu->cpu = cpu;
6795         put_cpu();
6796
6797         vmcs12->launch_state = 1;
6798
6799         prepare_vmcs02(vcpu, vmcs12);
6800
6801         /*
6802          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6803          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6804          * returned as far as L1 is concerned. It will only return (and set
6805          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6806          */
6807         return 1;
6808 }
6809
6810 /*
6811  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6812  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6813  * This function returns the new value we should put in vmcs12.guest_cr0.
6814  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6815  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6816  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6817  *     didn't trap the bit, because if L1 did, so would L0).
6818  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6819  *     been modified by L2, and L1 knows it. So just leave the old value of
6820  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6821  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6822  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6823  *     changed these bits, and therefore they need to be updated, but L0
6824  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6825  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6826  */
6827 static inline unsigned long
6828 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6829 {
6830         return
6831         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6832         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6833         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6834                         vcpu->arch.cr0_guest_owned_bits));
6835 }
6836
6837 static inline unsigned long
6838 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6839 {
6840         return
6841         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6842         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6843         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6844                         vcpu->arch.cr4_guest_owned_bits));
6845 }
6846
6847 /*
6848  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6849  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6850  * and this function updates it to reflect the changes to the guest state while
6851  * L2 was running (and perhaps made some exits which were handled directly by L0
6852  * without going back to L1), and to reflect the exit reason.
6853  * Note that we do not have to copy here all VMCS fields, just those that
6854  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6855  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6856  * which already writes to vmcs12 directly.
6857  */
6858 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6859 {
6860         /* update guest state fields: */
6861         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6862         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6863
6864         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6865         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6866         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6867         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6868
6869         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6870         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6871         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6872         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6873         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6874         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6875         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6876         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6877         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6878         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6879         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6880         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6881         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6882         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6883         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6884         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6885         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6886         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6887         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6888         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6889         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6890         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6891         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6892         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6893         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6894         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6895         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6896         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6897         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6898         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6899         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6900         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6901         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6902         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6903         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6904         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6905
6906         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6907         vmcs12->guest_interruptibility_info =
6908                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6909         vmcs12->guest_pending_dbg_exceptions =
6910                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6911
6912         /* TODO: These cannot have changed unless we have MSR bitmaps and
6913          * the relevant bit asks not to trap the change */
6914         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6915         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6916                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6917         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6918         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6919         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6920
6921         /* update exit information fields: */
6922
6923         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
6924         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6925
6926         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6927         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6928         vmcs12->idt_vectoring_info_field =
6929                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6930         vmcs12->idt_vectoring_error_code =
6931                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6932         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6933         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6934
6935         /* clear vm-entry fields which are to be cleared on exit */
6936         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6937                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6938 }
6939
6940 /*
6941  * A part of what we need to when the nested L2 guest exits and we want to
6942  * run its L1 parent, is to reset L1's guest state to the host state specified
6943  * in vmcs12.
6944  * This function is to be called not only on normal nested exit, but also on
6945  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6946  * Failures During or After Loading Guest State").
6947  * This function should be called when the active VMCS is L1's (vmcs01).
6948  */
6949 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6950 {
6951         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6952                 vcpu->arch.efer = vmcs12->host_ia32_efer;
6953         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6954                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6955         else
6956                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6957         vmx_set_efer(vcpu, vcpu->arch.efer);
6958
6959         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6960         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6961         /*
6962          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6963          * actually changed, because it depends on the current state of
6964          * fpu_active (which may have changed).
6965          * Note that vmx_set_cr0 refers to efer set above.
6966          */
6967         kvm_set_cr0(vcpu, vmcs12->host_cr0);
6968         /*
6969          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6970          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6971          * but we also need to update cr0_guest_host_mask and exception_bitmap.
6972          */
6973         update_exception_bitmap(vcpu);
6974         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6975         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6976
6977         /*
6978          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6979          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6980          */
6981         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6982         kvm_set_cr4(vcpu, vmcs12->host_cr4);
6983
6984         /* shadow page tables on either EPT or shadow page tables */
6985         kvm_set_cr3(vcpu, vmcs12->host_cr3);
6986         kvm_mmu_reset_context(vcpu);
6987
6988         if (enable_vpid) {
6989                 /*
6990                  * Trivially support vpid by letting L2s share their parent
6991                  * L1's vpid. TODO: move to a more elaborate solution, giving
6992                  * each L2 its own vpid and exposing the vpid feature to L1.
6993                  */
6994                 vmx_flush_tlb(vcpu);
6995         }
6996
6997
6998         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6999         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7000         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7001         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7002         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7003         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7004         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7005         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7006         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7007         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7008         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7009         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7010         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7011         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7012         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7013
7014         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7015                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7016         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7017                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7018                         vmcs12->host_ia32_perf_global_ctrl);
7019 }
7020
7021 /*
7022  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7023  * and modify vmcs12 to make it see what it would expect to see there if
7024  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7025  */
7026 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7027 {
7028         struct vcpu_vmx *vmx = to_vmx(vcpu);
7029         int cpu;
7030         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7031
7032         leave_guest_mode(vcpu);
7033         prepare_vmcs12(vcpu, vmcs12);
7034
7035         cpu = get_cpu();
7036         vmx->loaded_vmcs = &vmx->vmcs01;
7037         vmx_vcpu_put(vcpu);
7038         vmx_vcpu_load(vcpu, cpu);
7039         vcpu->cpu = cpu;
7040         put_cpu();
7041
7042         /* if no vmcs02 cache requested, remove the one we used */
7043         if (VMCS02_POOL_SIZE == 0)
7044                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7045
7046         load_vmcs12_host_state(vcpu, vmcs12);
7047
7048         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7049         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7050
7051         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7052         vmx->host_rsp = 0;
7053
7054         /* Unpin physical memory we referred to in vmcs02 */
7055         if (vmx->nested.apic_access_page) {
7056                 nested_release_page(vmx->nested.apic_access_page);
7057                 vmx->nested.apic_access_page = 0;
7058         }
7059
7060         /*
7061          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7062          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7063          * success or failure flag accordingly.
7064          */
7065         if (unlikely(vmx->fail)) {
7066                 vmx->fail = 0;
7067                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7068         } else
7069                 nested_vmx_succeed(vcpu);
7070 }
7071
7072 /*
7073  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7074  * 23.7 "VM-entry failures during or after loading guest state" (this also
7075  * lists the acceptable exit-reason and exit-qualification parameters).
7076  * It should only be called before L2 actually succeeded to run, and when
7077  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7078  */
7079 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7080                         struct vmcs12 *vmcs12,
7081                         u32 reason, unsigned long qualification)
7082 {
7083         load_vmcs12_host_state(vcpu, vmcs12);
7084         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7085         vmcs12->exit_qualification = qualification;
7086         nested_vmx_succeed(vcpu);
7087 }
7088
7089 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7090                                struct x86_instruction_info *info,
7091                                enum x86_intercept_stage stage)
7092 {
7093         return X86EMUL_CONTINUE;
7094 }
7095
7096 static struct kvm_x86_ops vmx_x86_ops = {
7097         .cpu_has_kvm_support = cpu_has_kvm_support,
7098         .disabled_by_bios = vmx_disabled_by_bios,
7099         .hardware_setup = hardware_setup,
7100         .hardware_unsetup = hardware_unsetup,
7101         .check_processor_compatibility = vmx_check_processor_compat,
7102         .hardware_enable = hardware_enable,
7103         .hardware_disable = hardware_disable,
7104         .cpu_has_accelerated_tpr = report_flexpriority,
7105
7106         .vcpu_create = vmx_create_vcpu,
7107         .vcpu_free = vmx_free_vcpu,
7108         .vcpu_reset = vmx_vcpu_reset,
7109
7110         .prepare_guest_switch = vmx_save_host_state,
7111         .vcpu_load = vmx_vcpu_load,
7112         .vcpu_put = vmx_vcpu_put,
7113
7114         .set_guest_debug = set_guest_debug,
7115         .get_msr = vmx_get_msr,
7116         .set_msr = vmx_set_msr,
7117         .get_segment_base = vmx_get_segment_base,
7118         .get_segment = vmx_get_segment,
7119         .set_segment = vmx_set_segment,
7120         .get_cpl = vmx_get_cpl,
7121         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7122         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7123         .decache_cr3 = vmx_decache_cr3,
7124         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7125         .set_cr0 = vmx_set_cr0,
7126         .set_cr3 = vmx_set_cr3,
7127         .set_cr4 = vmx_set_cr4,
7128         .set_efer = vmx_set_efer,
7129         .get_idt = vmx_get_idt,
7130         .set_idt = vmx_set_idt,
7131         .get_gdt = vmx_get_gdt,
7132         .set_gdt = vmx_set_gdt,
7133         .set_dr7 = vmx_set_dr7,
7134         .cache_reg = vmx_cache_reg,
7135         .get_rflags = vmx_get_rflags,
7136         .set_rflags = vmx_set_rflags,
7137         .fpu_activate = vmx_fpu_activate,
7138         .fpu_deactivate = vmx_fpu_deactivate,
7139
7140         .tlb_flush = vmx_flush_tlb,
7141
7142         .run = vmx_vcpu_run,
7143         .handle_exit = vmx_handle_exit,
7144         .skip_emulated_instruction = skip_emulated_instruction,
7145         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7146         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7147         .patch_hypercall = vmx_patch_hypercall,
7148         .set_irq = vmx_inject_irq,
7149         .set_nmi = vmx_inject_nmi,
7150         .queue_exception = vmx_queue_exception,
7151         .cancel_injection = vmx_cancel_injection,
7152         .interrupt_allowed = vmx_interrupt_allowed,
7153         .nmi_allowed = vmx_nmi_allowed,
7154         .get_nmi_mask = vmx_get_nmi_mask,
7155         .set_nmi_mask = vmx_set_nmi_mask,
7156         .enable_nmi_window = enable_nmi_window,
7157         .enable_irq_window = enable_irq_window,
7158         .update_cr8_intercept = update_cr8_intercept,
7159
7160         .set_tss_addr = vmx_set_tss_addr,
7161         .get_tdp_level = get_ept_level,
7162         .get_mt_mask = vmx_get_mt_mask,
7163
7164         .get_exit_info = vmx_get_exit_info,
7165
7166         .get_lpage_level = vmx_get_lpage_level,
7167
7168         .cpuid_update = vmx_cpuid_update,
7169
7170         .rdtscp_supported = vmx_rdtscp_supported,
7171
7172         .set_supported_cpuid = vmx_set_supported_cpuid,
7173
7174         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7175
7176         .set_tsc_khz = vmx_set_tsc_khz,
7177         .write_tsc_offset = vmx_write_tsc_offset,
7178         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7179         .compute_tsc_offset = vmx_compute_tsc_offset,
7180         .read_l1_tsc = vmx_read_l1_tsc,
7181
7182         .set_tdp_cr3 = vmx_set_cr3,
7183
7184         .check_intercept = vmx_check_intercept,
7185 };
7186
7187 static int __init vmx_init(void)
7188 {
7189         int r, i;
7190
7191         rdmsrl_safe(MSR_EFER, &host_efer);
7192
7193         for (i = 0; i < NR_VMX_MSR; ++i)
7194                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7195
7196         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7197         if (!vmx_io_bitmap_a)
7198                 return -ENOMEM;
7199
7200         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7201         if (!vmx_io_bitmap_b) {
7202                 r = -ENOMEM;
7203                 goto out;
7204         }
7205
7206         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7207         if (!vmx_msr_bitmap_legacy) {
7208                 r = -ENOMEM;
7209                 goto out1;
7210         }
7211
7212         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7213         if (!vmx_msr_bitmap_longmode) {
7214                 r = -ENOMEM;
7215                 goto out2;
7216         }
7217
7218         /*
7219          * Allow direct access to the PC debug port (it is often used for I/O
7220          * delays, but the vmexits simply slow things down).
7221          */
7222         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7223         clear_bit(0x80, vmx_io_bitmap_a);
7224
7225         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7226
7227         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7228         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7229
7230         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7231
7232         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7233                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7234         if (r)
7235                 goto out3;
7236
7237         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7238         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7239         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7240         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7241         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7242         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7243
7244         if (enable_ept) {
7245                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7246                                 VMX_EPT_EXECUTABLE_MASK);
7247                 ept_set_mmio_spte_mask();
7248                 kvm_enable_tdp();
7249         } else
7250                 kvm_disable_tdp();
7251
7252         return 0;
7253
7254 out3:
7255         free_page((unsigned long)vmx_msr_bitmap_longmode);
7256 out2:
7257         free_page((unsigned long)vmx_msr_bitmap_legacy);
7258 out1:
7259         free_page((unsigned long)vmx_io_bitmap_b);
7260 out:
7261         free_page((unsigned long)vmx_io_bitmap_a);
7262         return r;
7263 }
7264
7265 static void __exit vmx_exit(void)
7266 {
7267         free_page((unsigned long)vmx_msr_bitmap_legacy);
7268         free_page((unsigned long)vmx_msr_bitmap_longmode);
7269         free_page((unsigned long)vmx_io_bitmap_b);
7270         free_page((unsigned long)vmx_io_bitmap_a);
7271
7272         kvm_exit();
7273 }
7274
7275 module_init(vmx_init)
7276 module_exit(vmx_exit)