arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * Hyper-V requires all of these, so mark them as supported even though
 137  * they are just treated the same as all-context.
 138  */
 139 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 140         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 141         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 143         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 144
 145 /*
 146  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 147  * ple_gap:    upper bound on the amount of time between two successive
 148  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 149  *             According to test, this time is usually smaller than 128 cycles.
 150  * ple_window: upper bound on the amount of time a guest is allowed to execute
 151  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 152  *             less than 2^12 cycles
 153  * Time is measured based on a counter that runs at the same rate as the TSC,
 154  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 155  */
 156 #define KVM_VMX_DEFAULT_PLE_GAP           128
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 161                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 162
 163 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, int, S_IRUGO);
 165
 166 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, int, S_IRUGO);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, int, S_IRUGO);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, int, S_IRUGO);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 180 module_param(ple_window_max, int, S_IRUGO);
 181
 182 extern const ulong vmx_return;
 183
 184 #define NR_AUTOLOAD_MSRS 8
 185 #define VMCS02_POOL_SIZE 1
 186
 187 struct vmcs {
 188         u32 revision_id;
 189         u32 abort;
 190         char data[0];
 191 };
 192
 193 /*
 194  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 195  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 196  * loaded on this CPU (so we can clear them if the CPU goes down).
 197  */
 198 struct loaded_vmcs {
 199         struct vmcs *vmcs;
 200         struct vmcs *shadow_vmcs;
 201         int cpu;
 202         int launched;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 guest_ia32_debugctl;
 255         u64 guest_ia32_pat;
 256         u64 guest_ia32_efer;
 257         u64 guest_ia32_perf_global_ctrl;
 258         u64 guest_pdptr0;
 259         u64 guest_pdptr1;
 260         u64 guest_pdptr2;
 261         u64 guest_pdptr3;
 262         u64 guest_bndcfgs;
 263         u64 host_ia32_pat;
 264         u64 host_ia32_efer;
 265         u64 host_ia32_perf_global_ctrl;
 266         u64 padding64[8]; /* room for future expansion */
 267         /*
 268          * To allow migration of L1 (complete with its L2 guests) between
 269          * machines of different natural widths (32 or 64 bit), we cannot have
 270          * unsigned long fields with no explict size. We use u64 (aliased
 271          * natural_width) instead. Luckily, x86 is little-endian.
 272          */
 273         natural_width cr0_guest_host_mask;
 274         natural_width cr4_guest_host_mask;
 275         natural_width cr0_read_shadow;
 276         natural_width cr4_read_shadow;
 277         natural_width cr3_target_value0;
 278         natural_width cr3_target_value1;
 279         natural_width cr3_target_value2;
 280         natural_width cr3_target_value3;
 281         natural_width exit_qualification;
 282         natural_width guest_linear_address;
 283         natural_width guest_cr0;
 284         natural_width guest_cr3;
 285         natural_width guest_cr4;
 286         natural_width guest_es_base;
 287         natural_width guest_cs_base;
 288         natural_width guest_ss_base;
 289         natural_width guest_ds_base;
 290         natural_width guest_fs_base;
 291         natural_width guest_gs_base;
 292         natural_width guest_ldtr_base;
 293         natural_width guest_tr_base;
 294         natural_width guest_gdtr_base;
 295         natural_width guest_idtr_base;
 296         natural_width guest_dr7;
 297         natural_width guest_rsp;
 298         natural_width guest_rip;
 299         natural_width guest_rflags;
 300         natural_width guest_pending_dbg_exceptions;
 301         natural_width guest_sysenter_esp;
 302         natural_width guest_sysenter_eip;
 303         natural_width host_cr0;
 304         natural_width host_cr3;
 305         natural_width host_cr4;
 306         natural_width host_fs_base;
 307         natural_width host_gs_base;
 308         natural_width host_tr_base;
 309         natural_width host_gdtr_base;
 310         natural_width host_idtr_base;
 311         natural_width host_ia32_sysenter_esp;
 312         natural_width host_ia32_sysenter_eip;
 313         natural_width host_rsp;
 314         natural_width host_rip;
 315         natural_width paddingl[8]; /* room for future expansion */
 316         u32 pin_based_vm_exec_control;
 317         u32 cpu_based_vm_exec_control;
 318         u32 exception_bitmap;
 319         u32 page_fault_error_code_mask;
 320         u32 page_fault_error_code_match;
 321         u32 cr3_target_count;
 322         u32 vm_exit_controls;
 323         u32 vm_exit_msr_store_count;
 324         u32 vm_exit_msr_load_count;
 325         u32 vm_entry_controls;
 326         u32 vm_entry_msr_load_count;
 327         u32 vm_entry_intr_info_field;
 328         u32 vm_entry_exception_error_code;
 329         u32 vm_entry_instruction_len;
 330         u32 tpr_threshold;
 331         u32 secondary_vm_exec_control;
 332         u32 vm_instruction_error;
 333         u32 vm_exit_reason;
 334         u32 vm_exit_intr_info;
 335         u32 vm_exit_intr_error_code;
 336         u32 idt_vectoring_info_field;
 337         u32 idt_vectoring_error_code;
 338         u32 vm_exit_instruction_len;
 339         u32 vmx_instruction_info;
 340         u32 guest_es_limit;
 341         u32 guest_cs_limit;
 342         u32 guest_ss_limit;
 343         u32 guest_ds_limit;
 344         u32 guest_fs_limit;
 345         u32 guest_gs_limit;
 346         u32 guest_ldtr_limit;
 347         u32 guest_tr_limit;
 348         u32 guest_gdtr_limit;
 349         u32 guest_idtr_limit;
 350         u32 guest_es_ar_bytes;
 351         u32 guest_cs_ar_bytes;
 352         u32 guest_ss_ar_bytes;
 353         u32 guest_ds_ar_bytes;
 354         u32 guest_fs_ar_bytes;
 355         u32 guest_gs_ar_bytes;
 356         u32 guest_ldtr_ar_bytes;
 357         u32 guest_tr_ar_bytes;
 358         u32 guest_interruptibility_info;
 359         u32 guest_activity_state;
 360         u32 guest_sysenter_cs;
 361         u32 host_ia32_sysenter_cs;
 362         u32 vmx_preemption_timer_value;
 363         u32 padding32[7]; /* room for future expansion */
 364         u16 virtual_processor_id;
 365         u16 posted_intr_nv;
 366         u16 guest_es_selector;
 367         u16 guest_cs_selector;
 368         u16 guest_ss_selector;
 369         u16 guest_ds_selector;
 370         u16 guest_fs_selector;
 371         u16 guest_gs_selector;
 372         u16 guest_ldtr_selector;
 373         u16 guest_tr_selector;
 374         u16 guest_intr_status;
 375         u16 host_es_selector;
 376         u16 host_cs_selector;
 377         u16 host_ss_selector;
 378         u16 host_ds_selector;
 379         u16 host_fs_selector;
 380         u16 host_gs_selector;
 381         u16 host_tr_selector;
 382 };
 383
 384 /*
 385  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 386  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 387  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 388  */
 389 #define VMCS12_REVISION 0x11e57ed0
 390
 391 /*
 392  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 393  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 394  * current implementation, 4K are reserved to avoid future complications.
 395  */
 396 #define VMCS12_SIZE 0x1000
 397
 398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 399 struct vmcs02_list {
 400         struct list_head list;
 401         gpa_t vmptr;
 402         struct loaded_vmcs vmcs02;
 403 };
 404
 405 /*
 406  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 407  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 408  */
 409 struct nested_vmx {
 410         /* Has the level1 guest done vmxon? */
 411         bool vmxon;
 412         gpa_t vmxon_ptr;
 413
 414         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 415         gpa_t current_vmptr;
 416         /* The host-usable pointer to the above */
 417         struct page *current_vmcs12_page;
 418         struct vmcs12 *current_vmcs12;
 419         /*
 420          * Cache of the guest's VMCS, existing outside of guest memory.
 421          * Loaded from guest memory during VMPTRLD. Flushed to guest
 422          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 423          */
 424         struct vmcs12 *cached_vmcs12;
 425         /*
 426          * Indicates if the shadow vmcs must be updated with the
 427          * data hold by vmcs12
 428          */
 429         bool sync_shadow_vmcs;
 430
 431         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 432         struct list_head vmcs02_pool;
 433         int vmcs02_num;
 434         bool change_vmcs01_virtual_x2apic_mode;
 435         /* L2 must run next, and mustn't decide to exit to L1. */
 436         bool nested_run_pending;
 437         /*
 438          * Guest pages referred to in vmcs02 with host-physical pointers, so
 439          * we must keep them pinned while L2 runs.
 440          */
 441         struct page *apic_access_page;
 442         struct page *virtual_apic_page;
 443         struct page *pi_desc_page;
 444         struct pi_desc *pi_desc;
 445         bool pi_pending;
 446         u16 posted_intr_nv;
 447
 448         unsigned long *msr_bitmap;
 449
 450         struct hrtimer preemption_timer;
 451         bool preemption_timer_expired;
 452
 453         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 454         u64 vmcs01_debugctl;
 455
 456         u16 vpid02;
 457         u16 last_vpid;
 458
 459         /*
 460          * We only store the "true" versions of the VMX capability MSRs. We
 461          * generate the "non-true" versions by setting the must-be-1 bits
 462          * according to the SDM.
 463          */
 464         u32 nested_vmx_procbased_ctls_low;
 465         u32 nested_vmx_procbased_ctls_high;
 466         u32 nested_vmx_secondary_ctls_low;
 467         u32 nested_vmx_secondary_ctls_high;
 468         u32 nested_vmx_pinbased_ctls_low;
 469         u32 nested_vmx_pinbased_ctls_high;
 470         u32 nested_vmx_exit_ctls_low;
 471         u32 nested_vmx_exit_ctls_high;
 472         u32 nested_vmx_entry_ctls_low;
 473         u32 nested_vmx_entry_ctls_high;
 474         u32 nested_vmx_misc_low;
 475         u32 nested_vmx_misc_high;
 476         u32 nested_vmx_ept_caps;
 477         u32 nested_vmx_vpid_caps;
 478         u64 nested_vmx_basic;
 479         u64 nested_vmx_cr0_fixed0;
 480         u64 nested_vmx_cr0_fixed1;
 481         u64 nested_vmx_cr4_fixed0;
 482         u64 nested_vmx_cr4_fixed1;
 483         u64 nested_vmx_vmcs_enum;
 484 };
 485
 486 #define POSTED_INTR_ON  0
 487 #define POSTED_INTR_SN  1
 488
 489 /* Posted-Interrupt Descriptor */
 490 struct pi_desc {
 491         u32 pir[8];     /* Posted interrupt requested */
 492         union {
 493                 struct {
 494                                 /* bit 256 - Outstanding Notification */
 495                         u16     on      : 1,
 496                                 /* bit 257 - Suppress Notification */
 497                                 sn      : 1,
 498                                 /* bit 271:258 - Reserved */
 499                                 rsvd_1  : 14;
 500                                 /* bit 279:272 - Notification Vector */
 501                         u8      nv;
 502                                 /* bit 287:280 - Reserved */
 503                         u8      rsvd_2;
 504                                 /* bit 319:288 - Notification Destination */
 505                         u32     ndst;
 506                 };
 507                 u64 control;
 508         };
 509         u32 rsvd[6];
 510 } __aligned(64);
 511
 512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 513 {
 514         return test_and_set_bit(POSTED_INTR_ON,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 519 {
 520         return test_and_clear_bit(POSTED_INTR_ON,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 525 {
 526         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 527 }
 528
 529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 530 {
 531         return clear_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 static inline void pi_set_sn(struct pi_desc *pi_desc)
 536 {
 537         return set_bit(POSTED_INTR_SN,
 538                         (unsigned long *)&pi_desc->control);
 539 }
 540
 541 static inline void pi_clear_on(struct pi_desc *pi_desc)
 542 {
 543         clear_bit(POSTED_INTR_ON,
 544                   (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static inline int pi_test_on(struct pi_desc *pi_desc)
 548 {
 549         return test_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static inline int pi_test_sn(struct pi_desc *pi_desc)
 554 {
 555         return test_bit(POSTED_INTR_SN,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 struct vcpu_vmx {
 560         struct kvm_vcpu       vcpu;
 561         unsigned long         host_rsp;
 562         u8                    fail;
 563         bool                  nmi_known_unmasked;
 564         u32                   exit_intr_info;
 565         u32                   idt_vectoring_info;
 566         ulong                 rflags;
 567         struct shared_msr_entry *guest_msrs;
 568         int                   nmsrs;
 569         int                   save_nmsrs;
 570         unsigned long         host_idt_base;
 571 #ifdef CONFIG_X86_64
 572         u64                   msr_host_kernel_gs_base;
 573         u64                   msr_guest_kernel_gs_base;
 574 #endif
 575         u32 vm_entry_controls_shadow;
 576         u32 vm_exit_controls_shadow;
 577         /*
 578          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 579          * non-nested (L1) guest, it always points to vmcs01. For a nested
 580          * guest (L2), it points to a different VMCS.
 581          */
 582         struct loaded_vmcs    vmcs01;
 583         struct loaded_vmcs   *loaded_vmcs;
 584         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 585         struct msr_autoload {
 586                 unsigned nr;
 587                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 588                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 589         } msr_autoload;
 590         struct {
 591                 int           loaded;
 592                 u16           fs_sel, gs_sel, ldt_sel;
 593 #ifdef CONFIG_X86_64
 594                 u16           ds_sel, es_sel;
 595 #endif
 596                 int           gs_ldt_reload_needed;
 597                 int           fs_reload_needed;
 598                 u64           msr_host_bndcfgs;
 599                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 600         } host_state;
 601         struct {
 602                 int vm86_active;
 603                 ulong save_rflags;
 604                 struct kvm_segment segs[8];
 605         } rmode;
 606         struct {
 607                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 608                 struct kvm_save_segment {
 609                         u16 selector;
 610                         unsigned long base;
 611                         u32 limit;
 612                         u32 ar;
 613                 } seg[8];
 614         } segment_cache;
 615         int vpid;
 616         bool emulation_required;
 617
 618         /* Support for vnmi-less CPUs */
 619         int soft_vnmi_blocked;
 620         ktime_t entry_time;
 621         s64 vnmi_blocked_time;
 622         u32 exit_reason;
 623
 624         /* Posted interrupt descriptor */
 625         struct pi_desc pi_desc;
 626
 627         /* Support for a guest hypervisor (nested VMX) */
 628         struct nested_vmx nested;
 629
 630         /* Dynamic PLE window. */
 631         int ple_window;
 632         bool ple_window_dirty;
 633
 634         /* Support for PML */
 635 #define PML_ENTITY_NUM          512
 636         struct page *pml_pg;
 637
 638         /* apic deadline value in host tsc */
 639         u64 hv_deadline_tsc;
 640
 641         u64 current_tsc_ratio;
 642
 643         bool guest_pkru_valid;
 644         u32 guest_pkru;
 645         u32 host_pkru;
 646
 647         /*
 648          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 649          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 650          * in msr_ia32_feature_control_valid_bits.
 651          */
 652         u64 msr_ia32_feature_control;
 653         u64 msr_ia32_feature_control_valid_bits;
 654 };
 655
 656 enum segment_cache_field {
 657         SEG_FIELD_SEL = 0,
 658         SEG_FIELD_BASE = 1,
 659         SEG_FIELD_LIMIT = 2,
 660         SEG_FIELD_AR = 3,
 661
 662         SEG_FIELD_NR = 4
 663 };
 664
 665 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 666 {
 667         return container_of(vcpu, struct vcpu_vmx, vcpu);
 668 }
 669
 670 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 671 {
 672         return &(to_vmx(vcpu)->pi_desc);
 673 }
 674
 675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 676 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 677 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 678                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 679
 680
 681 static unsigned long shadow_read_only_fields[] = {
 682         /*
 683          * We do NOT shadow fields that are modified when L0
 684          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 685          * VMXON...) executed by L1.
 686          * For example, VM_INSTRUCTION_ERROR is read
 687          * by L1 if a vmx instruction fails (part of the error path).
 688          * Note the code assumes this logic. If for some reason
 689          * we start shadowing these fields then we need to
 690          * force a shadow sync when L0 emulates vmx instructions
 691          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 692          * by nested_vmx_failValid)
 693          */
 694         VM_EXIT_REASON,
 695         VM_EXIT_INTR_INFO,
 696         VM_EXIT_INSTRUCTION_LEN,
 697         IDT_VECTORING_INFO_FIELD,
 698         IDT_VECTORING_ERROR_CODE,
 699         VM_EXIT_INTR_ERROR_CODE,
 700         EXIT_QUALIFICATION,
 701         GUEST_LINEAR_ADDRESS,
 702         GUEST_PHYSICAL_ADDRESS
 703 };
 704 static int max_shadow_read_only_fields =
 705         ARRAY_SIZE(shadow_read_only_fields);
 706
 707 static unsigned long shadow_read_write_fields[] = {
 708         TPR_THRESHOLD,
 709         GUEST_RIP,
 710         GUEST_RSP,
 711         GUEST_CR0,
 712         GUEST_CR3,
 713         GUEST_CR4,
 714         GUEST_INTERRUPTIBILITY_INFO,
 715         GUEST_RFLAGS,
 716         GUEST_CS_SELECTOR,
 717         GUEST_CS_AR_BYTES,
 718         GUEST_CS_LIMIT,
 719         GUEST_CS_BASE,
 720         GUEST_ES_BASE,
 721         GUEST_BNDCFGS,
 722         CR0_GUEST_HOST_MASK,
 723         CR0_READ_SHADOW,
 724         CR4_READ_SHADOW,
 725         TSC_OFFSET,
 726         EXCEPTION_BITMAP,
 727         CPU_BASED_VM_EXEC_CONTROL,
 728         VM_ENTRY_EXCEPTION_ERROR_CODE,
 729         VM_ENTRY_INTR_INFO_FIELD,
 730         VM_ENTRY_INSTRUCTION_LEN,
 731         VM_ENTRY_EXCEPTION_ERROR_CODE,
 732         HOST_FS_BASE,
 733         HOST_GS_BASE,
 734         HOST_FS_SELECTOR,
 735         HOST_GS_SELECTOR
 736 };
 737 static int max_shadow_read_write_fields =
 738         ARRAY_SIZE(shadow_read_write_fields);
 739
 740 static const unsigned short vmcs_field_to_offset_table[] = {
 741         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 742         FIELD(POSTED_INTR_NV, posted_intr_nv),
 743         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 744         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 745         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 746         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 747         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 748         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 749         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 750         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 751         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 775         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 776         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 777         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 778         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 779         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 780         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 781         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 782         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 783         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 784         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 785         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 786         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 787         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 788         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 789         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 790         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 791         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 792         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 793         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 794         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 795         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 796         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 797         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 798         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 799         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 800         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 801         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 802         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 803         FIELD(TPR_THRESHOLD, tpr_threshold),
 804         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 805         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 806         FIELD(VM_EXIT_REASON, vm_exit_reason),
 807         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 808         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 809         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 810         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 811         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 812         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 813         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 814         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 815         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 816         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 817         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 818         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 819         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 820         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 821         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 822         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 823         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 824         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 825         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 826         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 827         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 828         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 829         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 830         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 831         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 832         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 833         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 834         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 835         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 836         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 837         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 838         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 839         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 840         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 841         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 842         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 843         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 844         FIELD(EXIT_QUALIFICATION, exit_qualification),
 845         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 846         FIELD(GUEST_CR0, guest_cr0),
 847         FIELD(GUEST_CR3, guest_cr3),
 848         FIELD(GUEST_CR4, guest_cr4),
 849         FIELD(GUEST_ES_BASE, guest_es_base),
 850         FIELD(GUEST_CS_BASE, guest_cs_base),
 851         FIELD(GUEST_SS_BASE, guest_ss_base),
 852         FIELD(GUEST_DS_BASE, guest_ds_base),
 853         FIELD(GUEST_FS_BASE, guest_fs_base),
 854         FIELD(GUEST_GS_BASE, guest_gs_base),
 855         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 856         FIELD(GUEST_TR_BASE, guest_tr_base),
 857         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 858         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 859         FIELD(GUEST_DR7, guest_dr7),
 860         FIELD(GUEST_RSP, guest_rsp),
 861         FIELD(GUEST_RIP, guest_rip),
 862         FIELD(GUEST_RFLAGS, guest_rflags),
 863         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 864         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 865         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 866         FIELD(HOST_CR0, host_cr0),
 867         FIELD(HOST_CR3, host_cr3),
 868         FIELD(HOST_CR4, host_cr4),
 869         FIELD(HOST_FS_BASE, host_fs_base),
 870         FIELD(HOST_GS_BASE, host_gs_base),
 871         FIELD(HOST_TR_BASE, host_tr_base),
 872         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 873         FIELD(HOST_IDTR_BASE, host_idtr_base),
 874         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 875         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 876         FIELD(HOST_RSP, host_rsp),
 877         FIELD(HOST_RIP, host_rip),
 878 };
 879
 880 static inline short vmcs_field_to_offset(unsigned long field)
 881 {
 882         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 883
 884         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 885             vmcs_field_to_offset_table[field] == 0)
 886                 return -ENOENT;
 887
 888         return vmcs_field_to_offset_table[field];
 889 }
 890
 891 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 892 {
 893         return to_vmx(vcpu)->nested.cached_vmcs12;
 894 }
 895
 896 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 897 {
 898         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 899         if (is_error_page(page))
 900                 return NULL;
 901
 902         return page;
 903 }
 904
 905 static void nested_release_page(struct page *page)
 906 {
 907         kvm_release_page_dirty(page);
 908 }
 909
 910 static void nested_release_page_clean(struct page *page)
 911 {
 912         kvm_release_page_clean(page);
 913 }
 914
 915 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 916 static u64 construct_eptp(unsigned long root_hpa);
 917 static void kvm_cpu_vmxon(u64 addr);
 918 static void kvm_cpu_vmxoff(void);
 919 static bool vmx_xsaves_supported(void);
 920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 922                             struct kvm_segment *var, int seg);
 923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 924                             struct kvm_segment *var, int seg);
 925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 929 static int alloc_identity_pagetable(struct kvm *kvm);
 930
 931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 933 /*
 934  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 935  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 936  */
 937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 938
 939 /*
 940  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 941  * can find which vCPU should be waken up.
 942  */
 943 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 944 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 945
 946 enum {
 947         VMX_IO_BITMAP_A,
 948         VMX_IO_BITMAP_B,
 949         VMX_MSR_BITMAP_LEGACY,
 950         VMX_MSR_BITMAP_LONGMODE,
 951         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 952         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 953         VMX_MSR_BITMAP_LEGACY_X2APIC,
 954         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 955         VMX_VMREAD_BITMAP,
 956         VMX_VMWRITE_BITMAP,
 957         VMX_BITMAP_NR
 958 };
 959
 960 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 961
 962 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 963 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 964 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 965 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 966 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 967 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 968 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 969 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 970 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 971 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 972
 973 static bool cpu_has_load_ia32_efer;
 974 static bool cpu_has_load_perf_global_ctrl;
 975
 976 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 977 static DEFINE_SPINLOCK(vmx_vpid_lock);
 978
 979 static struct vmcs_config {
 980         int size;
 981         int order;
 982         u32 basic_cap;
 983         u32 revision_id;
 984         u32 pin_based_exec_ctrl;
 985         u32 cpu_based_exec_ctrl;
 986         u32 cpu_based_2nd_exec_ctrl;
 987         u32 vmexit_ctrl;
 988         u32 vmentry_ctrl;
 989 } vmcs_config;
 990
 991 static struct vmx_capability {
 992         u32 ept;
 993         u32 vpid;
 994 } vmx_capability;
 995
 996 #define VMX_SEGMENT_FIELD(seg)                                  \
 997         [VCPU_SREG_##seg] = {                                   \
 998                 .selector = GUEST_##seg##_SELECTOR,             \
 999                 .base = GUEST_##seg##_BASE,                     \
1000                 .limit = GUEST_##seg##_LIMIT,                   \
1001                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1002         }
1003
1004 static const struct kvm_vmx_segment_field {
1005         unsigned selector;
1006         unsigned base;
1007         unsigned limit;
1008         unsigned ar_bytes;
1009 } kvm_vmx_segment_fields[] = {
1010         VMX_SEGMENT_FIELD(CS),
1011         VMX_SEGMENT_FIELD(DS),
1012         VMX_SEGMENT_FIELD(ES),
1013         VMX_SEGMENT_FIELD(FS),
1014         VMX_SEGMENT_FIELD(GS),
1015         VMX_SEGMENT_FIELD(SS),
1016         VMX_SEGMENT_FIELD(TR),
1017         VMX_SEGMENT_FIELD(LDTR),
1018 };
1019
1020 static u64 host_efer;
1021
1022 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1023
1024 /*
1025  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1026  * away by decrementing the array size.
1027  */
1028 static const u32 vmx_msr_index[] = {
1029 #ifdef CONFIG_X86_64
1030         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1031 #endif
1032         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1033 };
1034
1035 static inline bool is_exception_n(u32 intr_info, u8 vector)
1036 {
1037         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1038                              INTR_INFO_VALID_MASK)) ==
1039                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1040 }
1041
1042 static inline bool is_debug(u32 intr_info)
1043 {
1044         return is_exception_n(intr_info, DB_VECTOR);
1045 }
1046
1047 static inline bool is_breakpoint(u32 intr_info)
1048 {
1049         return is_exception_n(intr_info, BP_VECTOR);
1050 }
1051
1052 static inline bool is_page_fault(u32 intr_info)
1053 {
1054         return is_exception_n(intr_info, PF_VECTOR);
1055 }
1056
1057 static inline bool is_no_device(u32 intr_info)
1058 {
1059         return is_exception_n(intr_info, NM_VECTOR);
1060 }
1061
1062 static inline bool is_invalid_opcode(u32 intr_info)
1063 {
1064         return is_exception_n(intr_info, UD_VECTOR);
1065 }
1066
1067 static inline bool is_external_interrupt(u32 intr_info)
1068 {
1069         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1070                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1071 }
1072
1073 static inline bool is_machine_check(u32 intr_info)
1074 {
1075         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1076                              INTR_INFO_VALID_MASK)) ==
1077                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1078 }
1079
1080 static inline bool cpu_has_vmx_msr_bitmap(void)
1081 {
1082         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1083 }
1084
1085 static inline bool cpu_has_vmx_tpr_shadow(void)
1086 {
1087         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1088 }
1089
1090 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1091 {
1092         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1093 }
1094
1095 static inline bool cpu_has_secondary_exec_ctrls(void)
1096 {
1097         return vmcs_config.cpu_based_exec_ctrl &
1098                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1099 }
1100
1101 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1102 {
1103         return vmcs_config.cpu_based_2nd_exec_ctrl &
1104                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1105 }
1106
1107 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1108 {
1109         return vmcs_config.cpu_based_2nd_exec_ctrl &
1110                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1111 }
1112
1113 static inline bool cpu_has_vmx_apic_register_virt(void)
1114 {
1115         return vmcs_config.cpu_based_2nd_exec_ctrl &
1116                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1117 }
1118
1119 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1120 {
1121         return vmcs_config.cpu_based_2nd_exec_ctrl &
1122                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1123 }
1124
1125 /*
1126  * Comment's format: document - errata name - stepping - processor name.
1127  * Refer from
1128  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1129  */
1130 static u32 vmx_preemption_cpu_tfms[] = {
1131 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1132 0x000206E6,
1133 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1134 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1135 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1136 0x00020652,
1137 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1138 0x00020655,
1139 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1140 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1141 /*
1142  * 320767.pdf - AAP86  - B1 -
1143  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1144  */
1145 0x000106E5,
1146 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1147 0x000106A0,
1148 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1149 0x000106A1,
1150 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1151 0x000106A4,
1152  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1153  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1154  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1155 0x000106A5,
1156 };
1157
1158 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1159 {
1160         u32 eax = cpuid_eax(0x00000001), i;
1161
1162         /* Clear the reserved bits */
1163         eax &= ~(0x3U << 14 | 0xfU << 28);
1164         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1165                 if (eax == vmx_preemption_cpu_tfms[i])
1166                         return true;
1167
1168         return false;
1169 }
1170
1171 static inline bool cpu_has_vmx_preemption_timer(void)
1172 {
1173         return vmcs_config.pin_based_exec_ctrl &
1174                 PIN_BASED_VMX_PREEMPTION_TIMER;
1175 }
1176
1177 static inline bool cpu_has_vmx_posted_intr(void)
1178 {
1179         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1180                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1181 }
1182
1183 static inline bool cpu_has_vmx_apicv(void)
1184 {
1185         return cpu_has_vmx_apic_register_virt() &&
1186                 cpu_has_vmx_virtual_intr_delivery() &&
1187                 cpu_has_vmx_posted_intr();
1188 }
1189
1190 static inline bool cpu_has_vmx_flexpriority(void)
1191 {
1192         return cpu_has_vmx_tpr_shadow() &&
1193                 cpu_has_vmx_virtualize_apic_accesses();
1194 }
1195
1196 static inline bool cpu_has_vmx_ept_execute_only(void)
1197 {
1198         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1199 }
1200
1201 static inline bool cpu_has_vmx_ept_2m_page(void)
1202 {
1203         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1204 }
1205
1206 static inline bool cpu_has_vmx_ept_1g_page(void)
1207 {
1208         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1209 }
1210
1211 static inline bool cpu_has_vmx_ept_4levels(void)
1212 {
1213         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1214 }
1215
1216 static inline bool cpu_has_vmx_ept_ad_bits(void)
1217 {
1218         return vmx_capability.ept & VMX_EPT_AD_BIT;
1219 }
1220
1221 static inline bool cpu_has_vmx_invept_context(void)
1222 {
1223         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1224 }
1225
1226 static inline bool cpu_has_vmx_invept_global(void)
1227 {
1228         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1229 }
1230
1231 static inline bool cpu_has_vmx_invvpid_single(void)
1232 {
1233         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1234 }
1235
1236 static inline bool cpu_has_vmx_invvpid_global(void)
1237 {
1238         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1239 }
1240
1241 static inline bool cpu_has_vmx_invvpid(void)
1242 {
1243         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1244 }
1245
1246 static inline bool cpu_has_vmx_ept(void)
1247 {
1248         return vmcs_config.cpu_based_2nd_exec_ctrl &
1249                 SECONDARY_EXEC_ENABLE_EPT;
1250 }
1251
1252 static inline bool cpu_has_vmx_unrestricted_guest(void)
1253 {
1254         return vmcs_config.cpu_based_2nd_exec_ctrl &
1255                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1256 }
1257
1258 static inline bool cpu_has_vmx_ple(void)
1259 {
1260         return vmcs_config.cpu_based_2nd_exec_ctrl &
1261                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1262 }
1263
1264 static inline bool cpu_has_vmx_basic_inout(void)
1265 {
1266         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1267 }
1268
1269 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1270 {
1271         return flexpriority_enabled && lapic_in_kernel(vcpu);
1272 }
1273
1274 static inline bool cpu_has_vmx_vpid(void)
1275 {
1276         return vmcs_config.cpu_based_2nd_exec_ctrl &
1277                 SECONDARY_EXEC_ENABLE_VPID;
1278 }
1279
1280 static inline bool cpu_has_vmx_rdtscp(void)
1281 {
1282         return vmcs_config.cpu_based_2nd_exec_ctrl &
1283                 SECONDARY_EXEC_RDTSCP;
1284 }
1285
1286 static inline bool cpu_has_vmx_invpcid(void)
1287 {
1288         return vmcs_config.cpu_based_2nd_exec_ctrl &
1289                 SECONDARY_EXEC_ENABLE_INVPCID;
1290 }
1291
1292 static inline bool cpu_has_virtual_nmis(void)
1293 {
1294         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1295 }
1296
1297 static inline bool cpu_has_vmx_wbinvd_exit(void)
1298 {
1299         return vmcs_config.cpu_based_2nd_exec_ctrl &
1300                 SECONDARY_EXEC_WBINVD_EXITING;
1301 }
1302
1303 static inline bool cpu_has_vmx_shadow_vmcs(void)
1304 {
1305         u64 vmx_msr;
1306         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1307         /* check if the cpu supports writing r/o exit information fields */
1308         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1309                 return false;
1310
1311         return vmcs_config.cpu_based_2nd_exec_ctrl &
1312                 SECONDARY_EXEC_SHADOW_VMCS;
1313 }
1314
1315 static inline bool cpu_has_vmx_pml(void)
1316 {
1317         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1318 }
1319
1320 static inline bool cpu_has_vmx_tsc_scaling(void)
1321 {
1322         return vmcs_config.cpu_based_2nd_exec_ctrl &
1323                 SECONDARY_EXEC_TSC_SCALING;
1324 }
1325
1326 static inline bool report_flexpriority(void)
1327 {
1328         return flexpriority_enabled;
1329 }
1330
1331 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1332 {
1333         return vmcs12->cpu_based_vm_exec_control & bit;
1334 }
1335
1336 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1337 {
1338         return (vmcs12->cpu_based_vm_exec_control &
1339                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1340                 (vmcs12->secondary_vm_exec_control & bit);
1341 }
1342
1343 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1344 {
1345         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1346 }
1347
1348 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1349 {
1350         return vmcs12->pin_based_vm_exec_control &
1351                 PIN_BASED_VMX_PREEMPTION_TIMER;
1352 }
1353
1354 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1355 {
1356         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1357 }
1358
1359 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1360 {
1361         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1362                 vmx_xsaves_supported();
1363 }
1364
1365 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1366 {
1367         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1368 }
1369
1370 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1371 {
1372         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1373 }
1374
1375 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1376 {
1377         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1378 }
1379
1380 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1381 {
1382         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1383 }
1384
1385 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1386 {
1387         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1388 }
1389
1390 static inline bool is_nmi(u32 intr_info)
1391 {
1392         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1393                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1394 }
1395
1396 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1397                               u32 exit_intr_info,
1398                               unsigned long exit_qualification);
1399 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1400                         struct vmcs12 *vmcs12,
1401                         u32 reason, unsigned long qualification);
1402
1403 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1404 {
1405         int i;
1406
1407         for (i = 0; i < vmx->nmsrs; ++i)
1408                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1409                         return i;
1410         return -1;
1411 }
1412
1413 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1414 {
1415     struct {
1416         u64 vpid : 16;
1417         u64 rsvd : 48;
1418         u64 gva;
1419     } operand = { vpid, 0, gva };
1420
1421     asm volatile (__ex(ASM_VMX_INVVPID)
1422                   /* CF==1 or ZF==1 --> rc = -1 */
1423                   "; ja 1f ; ud2 ; 1:"
1424                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1425 }
1426
1427 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1428 {
1429         struct {
1430                 u64 eptp, gpa;
1431         } operand = {eptp, gpa};
1432
1433         asm volatile (__ex(ASM_VMX_INVEPT)
1434                         /* CF==1 or ZF==1 --> rc = -1 */
1435                         "; ja 1f ; ud2 ; 1:\n"
1436                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1437 }
1438
1439 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1440 {
1441         int i;
1442
1443         i = __find_msr_index(vmx, msr);
1444         if (i >= 0)
1445                 return &vmx->guest_msrs[i];
1446         return NULL;
1447 }
1448
1449 static void vmcs_clear(struct vmcs *vmcs)
1450 {
1451         u64 phys_addr = __pa(vmcs);
1452         u8 error;
1453
1454         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1455                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1456                       : "cc", "memory");
1457         if (error)
1458                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1459                        vmcs, phys_addr);
1460 }
1461
1462 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1463 {
1464         vmcs_clear(loaded_vmcs->vmcs);
1465         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1466                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1467         loaded_vmcs->cpu = -1;
1468         loaded_vmcs->launched = 0;
1469 }
1470
1471 static void vmcs_load(struct vmcs *vmcs)
1472 {
1473         u64 phys_addr = __pa(vmcs);
1474         u8 error;
1475
1476         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1477                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1478                         : "cc", "memory");
1479         if (error)
1480                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1481                        vmcs, phys_addr);
1482 }
1483
1484 #ifdef CONFIG_KEXEC_CORE
1485 /*
1486  * This bitmap is used to indicate whether the vmclear
1487  * operation is enabled on all cpus. All disabled by
1488  * default.
1489  */
1490 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1491
1492 static inline void crash_enable_local_vmclear(int cpu)
1493 {
1494         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1495 }
1496
1497 static inline void crash_disable_local_vmclear(int cpu)
1498 {
1499         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1500 }
1501
1502 static inline int crash_local_vmclear_enabled(int cpu)
1503 {
1504         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1505 }
1506
1507 static void crash_vmclear_local_loaded_vmcss(void)
1508 {
1509         int cpu = raw_smp_processor_id();
1510         struct loaded_vmcs *v;
1511
1512         if (!crash_local_vmclear_enabled(cpu))
1513                 return;
1514
1515         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1516                             loaded_vmcss_on_cpu_link)
1517                 vmcs_clear(v->vmcs);
1518 }
1519 #else
1520 static inline void crash_enable_local_vmclear(int cpu) { }
1521 static inline void crash_disable_local_vmclear(int cpu) { }
1522 #endif /* CONFIG_KEXEC_CORE */
1523
1524 static void __loaded_vmcs_clear(void *arg)
1525 {
1526         struct loaded_vmcs *loaded_vmcs = arg;
1527         int cpu = raw_smp_processor_id();
1528
1529         if (loaded_vmcs->cpu != cpu)
1530                 return; /* vcpu migration can race with cpu offline */
1531         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1532                 per_cpu(current_vmcs, cpu) = NULL;
1533         crash_disable_local_vmclear(cpu);
1534         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1535
1536         /*
1537          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1538          * is before setting loaded_vmcs->vcpu to -1 which is done in
1539          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1540          * then adds the vmcs into percpu list before it is deleted.
1541          */
1542         smp_wmb();
1543
1544         loaded_vmcs_init(loaded_vmcs);
1545         crash_enable_local_vmclear(cpu);
1546 }
1547
1548 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1549 {
1550         int cpu = loaded_vmcs->cpu;
1551
1552         if (cpu != -1)
1553                 smp_call_function_single(cpu,
1554                          __loaded_vmcs_clear, loaded_vmcs, 1);
1555 }
1556
1557 static inline void vpid_sync_vcpu_single(int vpid)
1558 {
1559         if (vpid == 0)
1560                 return;
1561
1562         if (cpu_has_vmx_invvpid_single())
1563                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1564 }
1565
1566 static inline void vpid_sync_vcpu_global(void)
1567 {
1568         if (cpu_has_vmx_invvpid_global())
1569                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1570 }
1571
1572 static inline void vpid_sync_context(int vpid)
1573 {
1574         if (cpu_has_vmx_invvpid_single())
1575                 vpid_sync_vcpu_single(vpid);
1576         else
1577                 vpid_sync_vcpu_global();
1578 }
1579
1580 static inline void ept_sync_global(void)
1581 {
1582         if (cpu_has_vmx_invept_global())
1583                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1584 }
1585
1586 static inline void ept_sync_context(u64 eptp)
1587 {
1588         if (enable_ept) {
1589                 if (cpu_has_vmx_invept_context())
1590                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1591                 else
1592                         ept_sync_global();
1593         }
1594 }
1595
1596 static __always_inline void vmcs_check16(unsigned long field)
1597 {
1598         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1599                          "16-bit accessor invalid for 64-bit field");
1600         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1601                          "16-bit accessor invalid for 64-bit high field");
1602         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1603                          "16-bit accessor invalid for 32-bit high field");
1604         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1605                          "16-bit accessor invalid for natural width field");
1606 }
1607
1608 static __always_inline void vmcs_check32(unsigned long field)
1609 {
1610         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1611                          "32-bit accessor invalid for 16-bit field");
1612         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1613                          "32-bit accessor invalid for natural width field");
1614 }
1615
1616 static __always_inline void vmcs_check64(unsigned long field)
1617 {
1618         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1619                          "64-bit accessor invalid for 16-bit field");
1620         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1621                          "64-bit accessor invalid for 64-bit high field");
1622         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1623                          "64-bit accessor invalid for 32-bit field");
1624         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1625                          "64-bit accessor invalid for natural width field");
1626 }
1627
1628 static __always_inline void vmcs_checkl(unsigned long field)
1629 {
1630         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1631                          "Natural width accessor invalid for 16-bit field");
1632         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1633                          "Natural width accessor invalid for 64-bit field");
1634         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1635                          "Natural width accessor invalid for 64-bit high field");
1636         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1637                          "Natural width accessor invalid for 32-bit field");
1638 }
1639
1640 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1641 {
1642         unsigned long value;
1643
1644         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1645                       : "=a"(value) : "d"(field) : "cc");
1646         return value;
1647 }
1648
1649 static __always_inline u16 vmcs_read16(unsigned long field)
1650 {
1651         vmcs_check16(field);
1652         return __vmcs_readl(field);
1653 }
1654
1655 static __always_inline u32 vmcs_read32(unsigned long field)
1656 {
1657         vmcs_check32(field);
1658         return __vmcs_readl(field);
1659 }
1660
1661 static __always_inline u64 vmcs_read64(unsigned long field)
1662 {
1663         vmcs_check64(field);
1664 #ifdef CONFIG_X86_64
1665         return __vmcs_readl(field);
1666 #else
1667         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1668 #endif
1669 }
1670
1671 static __always_inline unsigned long vmcs_readl(unsigned long field)
1672 {
1673         vmcs_checkl(field);
1674         return __vmcs_readl(field);
1675 }
1676
1677 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1678 {
1679         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1680                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1681         dump_stack();
1682 }
1683
1684 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1685 {
1686         u8 error;
1687
1688         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1689                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1690         if (unlikely(error))
1691                 vmwrite_error(field, value);
1692 }
1693
1694 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1695 {
1696         vmcs_check16(field);
1697         __vmcs_writel(field, value);
1698 }
1699
1700 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1701 {
1702         vmcs_check32(field);
1703         __vmcs_writel(field, value);
1704 }
1705
1706 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1707 {
1708         vmcs_check64(field);
1709         __vmcs_writel(field, value);
1710 #ifndef CONFIG_X86_64
1711         asm volatile ("");
1712         __vmcs_writel(field+1, value >> 32);
1713 #endif
1714 }
1715
1716 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1717 {
1718         vmcs_checkl(field);
1719         __vmcs_writel(field, value);
1720 }
1721
1722 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1723 {
1724         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1725                          "vmcs_clear_bits does not support 64-bit fields");
1726         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1727 }
1728
1729 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1730 {
1731         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1732                          "vmcs_set_bits does not support 64-bit fields");
1733         __vmcs_writel(field, __vmcs_readl(field) | mask);
1734 }
1735
1736 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1737 {
1738         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1739 }
1740
1741 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1742 {
1743         vmcs_write32(VM_ENTRY_CONTROLS, val);
1744         vmx->vm_entry_controls_shadow = val;
1745 }
1746
1747 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1748 {
1749         if (vmx->vm_entry_controls_shadow != val)
1750                 vm_entry_controls_init(vmx, val);
1751 }
1752
1753 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1754 {
1755         return vmx->vm_entry_controls_shadow;
1756 }
1757
1758
1759 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1760 {
1761         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1762 }
1763
1764 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1765 {
1766         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1767 }
1768
1769 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1770 {
1771         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1772 }
1773
1774 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1775 {
1776         vmcs_write32(VM_EXIT_CONTROLS, val);
1777         vmx->vm_exit_controls_shadow = val;
1778 }
1779
1780 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1781 {
1782         if (vmx->vm_exit_controls_shadow != val)
1783                 vm_exit_controls_init(vmx, val);
1784 }
1785
1786 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1787 {
1788         return vmx->vm_exit_controls_shadow;
1789 }
1790
1791
1792 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1793 {
1794         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1795 }
1796
1797 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1798 {
1799         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1800 }
1801
1802 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1803 {
1804         vmx->segment_cache.bitmask = 0;
1805 }
1806
1807 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1808                                        unsigned field)
1809 {
1810         bool ret;
1811         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1812
1813         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1814                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1815                 vmx->segment_cache.bitmask = 0;
1816         }
1817         ret = vmx->segment_cache.bitmask & mask;
1818         vmx->segment_cache.bitmask |= mask;
1819         return ret;
1820 }
1821
1822 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1823 {
1824         u16 *p = &vmx->segment_cache.seg[seg].selector;
1825
1826         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1827                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1828         return *p;
1829 }
1830
1831 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1832 {
1833         ulong *p = &vmx->segment_cache.seg[seg].base;
1834
1835         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1836                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1837         return *p;
1838 }
1839
1840 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1841 {
1842         u32 *p = &vmx->segment_cache.seg[seg].limit;
1843
1844         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1845                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1846         return *p;
1847 }
1848
1849 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1850 {
1851         u32 *p = &vmx->segment_cache.seg[seg].ar;
1852
1853         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1854                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1855         return *p;
1856 }
1857
1858 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1859 {
1860         u32 eb;
1861
1862         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1863              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1864         if ((vcpu->guest_debug &
1865              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1866             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1867                 eb |= 1u << BP_VECTOR;
1868         if (to_vmx(vcpu)->rmode.vm86_active)
1869                 eb = ~0;
1870         if (enable_ept)
1871                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1872
1873         /* When we are running a nested L2 guest and L1 specified for it a
1874          * certain exception bitmap, we must trap the same exceptions and pass
1875          * them to L1. When running L2, we will only handle the exceptions
1876          * specified above if L1 did not want them.
1877          */
1878         if (is_guest_mode(vcpu))
1879                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1880
1881         vmcs_write32(EXCEPTION_BITMAP, eb);
1882 }
1883
1884 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1885                 unsigned long entry, unsigned long exit)
1886 {
1887         vm_entry_controls_clearbit(vmx, entry);
1888         vm_exit_controls_clearbit(vmx, exit);
1889 }
1890
1891 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1892 {
1893         unsigned i;
1894         struct msr_autoload *m = &vmx->msr_autoload;
1895
1896         switch (msr) {
1897         case MSR_EFER:
1898                 if (cpu_has_load_ia32_efer) {
1899                         clear_atomic_switch_msr_special(vmx,
1900                                         VM_ENTRY_LOAD_IA32_EFER,
1901                                         VM_EXIT_LOAD_IA32_EFER);
1902                         return;
1903                 }
1904                 break;
1905         case MSR_CORE_PERF_GLOBAL_CTRL:
1906                 if (cpu_has_load_perf_global_ctrl) {
1907                         clear_atomic_switch_msr_special(vmx,
1908                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1909                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1910                         return;
1911                 }
1912                 break;
1913         }
1914
1915         for (i = 0; i < m->nr; ++i)
1916                 if (m->guest[i].index == msr)
1917                         break;
1918
1919         if (i == m->nr)
1920                 return;
1921         --m->nr;
1922         m->guest[i] = m->guest[m->nr];
1923         m->host[i] = m->host[m->nr];
1924         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1925         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1926 }
1927
1928 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1929                 unsigned long entry, unsigned long exit,
1930                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1931                 u64 guest_val, u64 host_val)
1932 {
1933         vmcs_write64(guest_val_vmcs, guest_val);
1934         vmcs_write64(host_val_vmcs, host_val);
1935         vm_entry_controls_setbit(vmx, entry);
1936         vm_exit_controls_setbit(vmx, exit);
1937 }
1938
1939 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1940                                   u64 guest_val, u64 host_val)
1941 {
1942         unsigned i;
1943         struct msr_autoload *m = &vmx->msr_autoload;
1944
1945         switch (msr) {
1946         case MSR_EFER:
1947                 if (cpu_has_load_ia32_efer) {
1948                         add_atomic_switch_msr_special(vmx,
1949                                         VM_ENTRY_LOAD_IA32_EFER,
1950                                         VM_EXIT_LOAD_IA32_EFER,
1951                                         GUEST_IA32_EFER,
1952                                         HOST_IA32_EFER,
1953                                         guest_val, host_val);
1954                         return;
1955                 }
1956                 break;
1957         case MSR_CORE_PERF_GLOBAL_CTRL:
1958                 if (cpu_has_load_perf_global_ctrl) {
1959                         add_atomic_switch_msr_special(vmx,
1960                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1961                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1962                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1963                                         HOST_IA32_PERF_GLOBAL_CTRL,
1964                                         guest_val, host_val);
1965                         return;
1966                 }
1967                 break;
1968         case MSR_IA32_PEBS_ENABLE:
1969                 /* PEBS needs a quiescent period after being disabled (to write
1970                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1971                  * provide that period, so a CPU could write host's record into
1972                  * guest's memory.
1973                  */
1974                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1975         }
1976
1977         for (i = 0; i < m->nr; ++i)
1978                 if (m->guest[i].index == msr)
1979                         break;
1980
1981         if (i == NR_AUTOLOAD_MSRS) {
1982                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1983                                 "Can't add msr %x\n", msr);
1984                 return;
1985         } else if (i == m->nr) {
1986                 ++m->nr;
1987                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1988                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1989         }
1990
1991         m->guest[i].index = msr;
1992         m->guest[i].value = guest_val;
1993         m->host[i].index = msr;
1994         m->host[i].value = host_val;
1995 }
1996
1997 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1998 {
1999         u64 guest_efer = vmx->vcpu.arch.efer;
2000         u64 ignore_bits = 0;
2001
2002         if (!enable_ept) {
2003                 /*
2004                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2005                  * host CPUID is more efficient than testing guest CPUID
2006                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2007                  */
2008                 if (boot_cpu_has(X86_FEATURE_SMEP))
2009                         guest_efer |= EFER_NX;
2010                 else if (!(guest_efer & EFER_NX))
2011                         ignore_bits |= EFER_NX;
2012         }
2013
2014         /*
2015          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2016          */
2017         ignore_bits |= EFER_SCE;
2018 #ifdef CONFIG_X86_64
2019         ignore_bits |= EFER_LMA | EFER_LME;
2020         /* SCE is meaningful only in long mode on Intel */
2021         if (guest_efer & EFER_LMA)
2022                 ignore_bits &= ~(u64)EFER_SCE;
2023 #endif
2024
2025         clear_atomic_switch_msr(vmx, MSR_EFER);
2026
2027         /*
2028          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2029          * On CPUs that support "load IA32_EFER", always switch EFER
2030          * atomically, since it's faster than switching it manually.
2031          */
2032         if (cpu_has_load_ia32_efer ||
2033             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2034                 if (!(guest_efer & EFER_LMA))
2035                         guest_efer &= ~EFER_LME;
2036                 if (guest_efer != host_efer)
2037                         add_atomic_switch_msr(vmx, MSR_EFER,
2038                                               guest_efer, host_efer);
2039                 return false;
2040         } else {
2041                 guest_efer &= ~ignore_bits;
2042                 guest_efer |= host_efer & ignore_bits;
2043
2044                 vmx->guest_msrs[efer_offset].data = guest_efer;
2045                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2046
2047                 return true;
2048         }
2049 }
2050
2051 #ifdef CONFIG_X86_32
2052 /*
2053  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2054  * VMCS rather than the segment table.  KVM uses this helper to figure
2055  * out the current bases to poke them into the VMCS before entry.
2056  */
2057 static unsigned long segment_base(u16 selector)
2058 {
2059         struct desc_struct *table;
2060         unsigned long v;
2061
2062         if (!(selector & ~SEGMENT_RPL_MASK))
2063                 return 0;
2064
2065         table = get_current_gdt_ro();
2066
2067         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2068                 u16 ldt_selector = kvm_read_ldt();
2069
2070                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2071                         return 0;
2072
2073                 table = (struct desc_struct *)segment_base(ldt_selector);
2074         }
2075         v = get_desc_base(&table[selector >> 3]);
2076         return v;
2077 }
2078 #endif
2079
2080 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2081 {
2082         struct vcpu_vmx *vmx = to_vmx(vcpu);
2083         int i;
2084
2085         if (vmx->host_state.loaded)
2086                 return;
2087
2088         vmx->host_state.loaded = 1;
2089         /*
2090          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2091          * allow segment selectors with cpl > 0 or ti == 1.
2092          */
2093         vmx->host_state.ldt_sel = kvm_read_ldt();
2094         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2095         savesegment(fs, vmx->host_state.fs_sel);
2096         if (!(vmx->host_state.fs_sel & 7)) {
2097                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2098                 vmx->host_state.fs_reload_needed = 0;
2099         } else {
2100                 vmcs_write16(HOST_FS_SELECTOR, 0);
2101                 vmx->host_state.fs_reload_needed = 1;
2102         }
2103         savesegment(gs, vmx->host_state.gs_sel);
2104         if (!(vmx->host_state.gs_sel & 7))
2105                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2106         else {
2107                 vmcs_write16(HOST_GS_SELECTOR, 0);
2108                 vmx->host_state.gs_ldt_reload_needed = 1;
2109         }
2110
2111 #ifdef CONFIG_X86_64
2112         savesegment(ds, vmx->host_state.ds_sel);
2113         savesegment(es, vmx->host_state.es_sel);
2114 #endif
2115
2116 #ifdef CONFIG_X86_64
2117         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2118         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2119 #else
2120         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2121         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2122 #endif
2123
2124 #ifdef CONFIG_X86_64
2125         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2126         if (is_long_mode(&vmx->vcpu))
2127                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2128 #endif
2129         if (boot_cpu_has(X86_FEATURE_MPX))
2130                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2131         for (i = 0; i < vmx->save_nmsrs; ++i)
2132                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2133                                    vmx->guest_msrs[i].data,
2134                                    vmx->guest_msrs[i].mask);
2135 }
2136
2137 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2138 {
2139         if (!vmx->host_state.loaded)
2140                 return;
2141
2142         ++vmx->vcpu.stat.host_state_reload;
2143         vmx->host_state.loaded = 0;
2144 #ifdef CONFIG_X86_64
2145         if (is_long_mode(&vmx->vcpu))
2146                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2147 #endif
2148         if (vmx->host_state.gs_ldt_reload_needed) {
2149                 kvm_load_ldt(vmx->host_state.ldt_sel);
2150 #ifdef CONFIG_X86_64
2151                 load_gs_index(vmx->host_state.gs_sel);
2152 #else
2153                 loadsegment(gs, vmx->host_state.gs_sel);
2154 #endif
2155         }
2156         if (vmx->host_state.fs_reload_needed)
2157                 loadsegment(fs, vmx->host_state.fs_sel);
2158 #ifdef CONFIG_X86_64
2159         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2160                 loadsegment(ds, vmx->host_state.ds_sel);
2161                 loadsegment(es, vmx->host_state.es_sel);
2162         }
2163 #endif
2164         invalidate_tss_limit();
2165 #ifdef CONFIG_X86_64
2166         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2167 #endif
2168         if (vmx->host_state.msr_host_bndcfgs)
2169                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2170         load_fixmap_gdt(raw_smp_processor_id());
2171 }
2172
2173 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2174 {
2175         preempt_disable();
2176         __vmx_load_host_state(vmx);
2177         preempt_enable();
2178 }
2179
2180 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2181 {
2182         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2183         struct pi_desc old, new;
2184         unsigned int dest;
2185
2186         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2187                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2188                 !kvm_vcpu_apicv_active(vcpu))
2189                 return;
2190
2191         do {
2192                 old.control = new.control = pi_desc->control;
2193
2194                 /*
2195                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2196                  * are two possible cases:
2197                  * 1. After running 'pre_block', context switch
2198                  *    happened. For this case, 'sn' was set in
2199                  *    vmx_vcpu_put(), so we need to clear it here.
2200                  * 2. After running 'pre_block', we were blocked,
2201                  *    and woken up by some other guy. For this case,
2202                  *    we don't need to do anything, 'pi_post_block'
2203                  *    will do everything for us. However, we cannot
2204                  *    check whether it is case #1 or case #2 here
2205                  *    (maybe, not needed), so we also clear sn here,
2206                  *    I think it is not a big deal.
2207                  */
2208                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2209                         if (vcpu->cpu != cpu) {
2210                                 dest = cpu_physical_id(cpu);
2211
2212                                 if (x2apic_enabled())
2213                                         new.ndst = dest;
2214                                 else
2215                                         new.ndst = (dest << 8) & 0xFF00;
2216                         }
2217
2218                         /* set 'NV' to 'notification vector' */
2219                         new.nv = POSTED_INTR_VECTOR;
2220                 }
2221
2222                 /* Allow posting non-urgent interrupts */
2223                 new.sn = 0;
2224         } while (cmpxchg(&pi_desc->control, old.control,
2225                         new.control) != old.control);
2226 }
2227
2228 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2229 {
2230         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2231         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2232 }
2233
2234 /*
2235  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2236  * vcpu mutex is already taken.
2237  */
2238 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2239 {
2240         struct vcpu_vmx *vmx = to_vmx(vcpu);
2241         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2242         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2243
2244         if (!vmm_exclusive)
2245                 kvm_cpu_vmxon(phys_addr);
2246         else if (!already_loaded)
2247                 loaded_vmcs_clear(vmx->loaded_vmcs);
2248
2249         if (!already_loaded) {
2250                 local_irq_disable();
2251                 crash_disable_local_vmclear(cpu);
2252
2253                 /*
2254                  * Read loaded_vmcs->cpu should be before fetching
2255                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2256                  * See the comments in __loaded_vmcs_clear().
2257                  */
2258                 smp_rmb();
2259
2260                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2261                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2262                 crash_enable_local_vmclear(cpu);
2263                 local_irq_enable();
2264         }
2265
2266         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2267                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2268                 vmcs_load(vmx->loaded_vmcs->vmcs);
2269         }
2270
2271         if (!already_loaded) {
2272                 void *gdt = get_current_gdt_ro();
2273                 unsigned long sysenter_esp;
2274
2275                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2276
2277                 /*
2278                  * Linux uses per-cpu TSS and GDT, so set these when switching
2279                  * processors.  See 22.2.4.
2280                  */
2281                 vmcs_writel(HOST_TR_BASE,
2282                             (unsigned long)this_cpu_ptr(&cpu_tss));
2283                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2284
2285                 /*
2286                  * VM exits change the host TR limit to 0x67 after a VM
2287                  * exit.  This is okay, since 0x67 covers everything except
2288                  * the IO bitmap and have have code to handle the IO bitmap
2289                  * being lost after a VM exit.
2290                  */
2291                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2292
2293                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2294                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2295
2296                 vmx->loaded_vmcs->cpu = cpu;
2297         }
2298
2299         /* Setup TSC multiplier */
2300         if (kvm_has_tsc_control &&
2301             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2302                 decache_tsc_multiplier(vmx);
2303
2304         vmx_vcpu_pi_load(vcpu, cpu);
2305         vmx->host_pkru = read_pkru();
2306 }
2307
2308 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2309 {
2310         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2311
2312         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2313                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2314                 !kvm_vcpu_apicv_active(vcpu))
2315                 return;
2316
2317         /* Set SN when the vCPU is preempted */
2318         if (vcpu->preempted)
2319                 pi_set_sn(pi_desc);
2320 }
2321
2322 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2323 {
2324         vmx_vcpu_pi_put(vcpu);
2325
2326         __vmx_load_host_state(to_vmx(vcpu));
2327         if (!vmm_exclusive) {
2328                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2329                 vcpu->cpu = -1;
2330                 kvm_cpu_vmxoff();
2331         }
2332 }
2333
2334 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2335
2336 /*
2337  * Return the cr0 value that a nested guest would read. This is a combination
2338  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2339  * its hypervisor (cr0_read_shadow).
2340  */
2341 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2342 {
2343         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2344                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2345 }
2346 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2347 {
2348         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2349                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2350 }
2351
2352 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2353 {
2354         unsigned long rflags, save_rflags;
2355
2356         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2357                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2358                 rflags = vmcs_readl(GUEST_RFLAGS);
2359                 if (to_vmx(vcpu)->rmode.vm86_active) {
2360                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2361                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2362                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2363                 }
2364                 to_vmx(vcpu)->rflags = rflags;
2365         }
2366         return to_vmx(vcpu)->rflags;
2367 }
2368
2369 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2370 {
2371         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2372         to_vmx(vcpu)->rflags = rflags;
2373         if (to_vmx(vcpu)->rmode.vm86_active) {
2374                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2375                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2376         }
2377         vmcs_writel(GUEST_RFLAGS, rflags);
2378 }
2379
2380 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2381 {
2382         return to_vmx(vcpu)->guest_pkru;
2383 }
2384
2385 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2386 {
2387         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2388         int ret = 0;
2389
2390         if (interruptibility & GUEST_INTR_STATE_STI)
2391                 ret |= KVM_X86_SHADOW_INT_STI;
2392         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2393                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2394
2395         return ret;
2396 }
2397
2398 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2399 {
2400         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2401         u32 interruptibility = interruptibility_old;
2402
2403         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2404
2405         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2406                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2407         else if (mask & KVM_X86_SHADOW_INT_STI)
2408                 interruptibility |= GUEST_INTR_STATE_STI;
2409
2410         if ((interruptibility != interruptibility_old))
2411                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2412 }
2413
2414 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2415 {
2416         unsigned long rip;
2417
2418         rip = kvm_rip_read(vcpu);
2419         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2420         kvm_rip_write(vcpu, rip);
2421
2422         /* skipping an emulated instruction also counts */
2423         vmx_set_interrupt_shadow(vcpu, 0);
2424 }
2425
2426 /*
2427  * KVM wants to inject page-faults which it got to the guest. This function
2428  * checks whether in a nested guest, we need to inject them to L1 or L2.
2429  */
2430 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2431 {
2432         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2433
2434         if (!(vmcs12->exception_bitmap & (1u << nr)))
2435                 return 0;
2436
2437         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2438                           vmcs_read32(VM_EXIT_INTR_INFO),
2439                           vmcs_readl(EXIT_QUALIFICATION));
2440         return 1;
2441 }
2442
2443 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2444                                 bool has_error_code, u32 error_code,
2445                                 bool reinject)
2446 {
2447         struct vcpu_vmx *vmx = to_vmx(vcpu);
2448         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2449
2450         if (!reinject && is_guest_mode(vcpu) &&
2451             nested_vmx_check_exception(vcpu, nr))
2452                 return;
2453
2454         if (has_error_code) {
2455                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2456                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2457         }
2458
2459         if (vmx->rmode.vm86_active) {
2460                 int inc_eip = 0;
2461                 if (kvm_exception_is_soft(nr))
2462                         inc_eip = vcpu->arch.event_exit_inst_len;
2463                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2464                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2465                 return;
2466         }
2467
2468         if (kvm_exception_is_soft(nr)) {
2469                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2470                              vmx->vcpu.arch.event_exit_inst_len);
2471                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2472         } else
2473                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2474
2475         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2476 }
2477
2478 static bool vmx_rdtscp_supported(void)
2479 {
2480         return cpu_has_vmx_rdtscp();
2481 }
2482
2483 static bool vmx_invpcid_supported(void)
2484 {
2485         return cpu_has_vmx_invpcid() && enable_ept;
2486 }
2487
2488 /*
2489  * Swap MSR entry in host/guest MSR entry array.
2490  */
2491 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2492 {
2493         struct shared_msr_entry tmp;
2494
2495         tmp = vmx->guest_msrs[to];
2496         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2497         vmx->guest_msrs[from] = tmp;
2498 }
2499
2500 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2501 {
2502         unsigned long *msr_bitmap;
2503
2504         if (is_guest_mode(vcpu))
2505                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2506         else if (cpu_has_secondary_exec_ctrls() &&
2507                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2508                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2509                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2510                         if (is_long_mode(vcpu))
2511                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2512                         else
2513                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2514                 } else {
2515                         if (is_long_mode(vcpu))
2516                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2517                         else
2518                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2519                 }
2520         } else {
2521                 if (is_long_mode(vcpu))
2522                         msr_bitmap = vmx_msr_bitmap_longmode;
2523                 else
2524                         msr_bitmap = vmx_msr_bitmap_legacy;
2525         }
2526
2527         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2528 }
2529
2530 /*
2531  * Set up the vmcs to automatically save and restore system
2532  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2533  * mode, as fiddling with msrs is very expensive.
2534  */
2535 static void setup_msrs(struct vcpu_vmx *vmx)
2536 {
2537         int save_nmsrs, index;
2538
2539         save_nmsrs = 0;
2540 #ifdef CONFIG_X86_64
2541         if (is_long_mode(&vmx->vcpu)) {
2542                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2543                 if (index >= 0)
2544                         move_msr_up(vmx, index, save_nmsrs++);
2545                 index = __find_msr_index(vmx, MSR_LSTAR);
2546                 if (index >= 0)
2547                         move_msr_up(vmx, index, save_nmsrs++);
2548                 index = __find_msr_index(vmx, MSR_CSTAR);
2549                 if (index >= 0)
2550                         move_msr_up(vmx, index, save_nmsrs++);
2551                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2552                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2553                         move_msr_up(vmx, index, save_nmsrs++);
2554                 /*
2555                  * MSR_STAR is only needed on long mode guests, and only
2556                  * if efer.sce is enabled.
2557                  */
2558                 index = __find_msr_index(vmx, MSR_STAR);
2559                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2560                         move_msr_up(vmx, index, save_nmsrs++);
2561         }
2562 #endif
2563         index = __find_msr_index(vmx, MSR_EFER);
2564         if (index >= 0 && update_transition_efer(vmx, index))
2565                 move_msr_up(vmx, index, save_nmsrs++);
2566
2567         vmx->save_nmsrs = save_nmsrs;
2568
2569         if (cpu_has_vmx_msr_bitmap())
2570                 vmx_set_msr_bitmap(&vmx->vcpu);
2571 }
2572
2573 /*
2574  * reads and returns guest's timestamp counter "register"
2575  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2576  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2577  */
2578 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2579 {
2580         u64 host_tsc, tsc_offset;
2581
2582         host_tsc = rdtsc();
2583         tsc_offset = vmcs_read64(TSC_OFFSET);
2584         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2585 }
2586
2587 /*
2588  * writes 'offset' into guest's timestamp counter offset register
2589  */
2590 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2591 {
2592         if (is_guest_mode(vcpu)) {
2593                 /*
2594                  * We're here if L1 chose not to trap WRMSR to TSC. According
2595                  * to the spec, this should set L1's TSC; The offset that L1
2596                  * set for L2 remains unchanged, and still needs to be added
2597                  * to the newly set TSC to get L2's TSC.
2598                  */
2599                 struct vmcs12 *vmcs12;
2600                 /* recalculate vmcs02.TSC_OFFSET: */
2601                 vmcs12 = get_vmcs12(vcpu);
2602                 vmcs_write64(TSC_OFFSET, offset +
2603                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2604                          vmcs12->tsc_offset : 0));
2605         } else {
2606                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2607                                            vmcs_read64(TSC_OFFSET), offset);
2608                 vmcs_write64(TSC_OFFSET, offset);
2609         }
2610 }
2611
2612 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2613 {
2614         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2615         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2616 }
2617
2618 /*
2619  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2620  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2621  * all guests if the "nested" module option is off, and can also be disabled
2622  * for a single guest by disabling its VMX cpuid bit.
2623  */
2624 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2625 {
2626         return nested && guest_cpuid_has_vmx(vcpu);
2627 }
2628
2629 /*
2630  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2631  * returned for the various VMX controls MSRs when nested VMX is enabled.
2632  * The same values should also be used to verify that vmcs12 control fields are
2633  * valid during nested entry from L1 to L2.
2634  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2635  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2636  * bit in the high half is on if the corresponding bit in the control field
2637  * may be on. See also vmx_control_verify().
2638  */
2639 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2640 {
2641         /*
2642          * Note that as a general rule, the high half of the MSRs (bits in
2643          * the control fields which may be 1) should be initialized by the
2644          * intersection of the underlying hardware's MSR (i.e., features which
2645          * can be supported) and the list of features we want to expose -
2646          * because they are known to be properly supported in our code.
2647          * Also, usually, the low half of the MSRs (bits which must be 1) can
2648          * be set to 0, meaning that L1 may turn off any of these bits. The
2649          * reason is that if one of these bits is necessary, it will appear
2650          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2651          * fields of vmcs01 and vmcs02, will turn these bits off - and
2652          * nested_vmx_exit_handled() will not pass related exits to L1.
2653          * These rules have exceptions below.
2654          */
2655
2656         /* pin-based controls */
2657         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2658                 vmx->nested.nested_vmx_pinbased_ctls_low,
2659                 vmx->nested.nested_vmx_pinbased_ctls_high);
2660         vmx->nested.nested_vmx_pinbased_ctls_low |=
2661                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2662         vmx->nested.nested_vmx_pinbased_ctls_high &=
2663                 PIN_BASED_EXT_INTR_MASK |
2664                 PIN_BASED_NMI_EXITING |
2665                 PIN_BASED_VIRTUAL_NMIS;
2666         vmx->nested.nested_vmx_pinbased_ctls_high |=
2667                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2668                 PIN_BASED_VMX_PREEMPTION_TIMER;
2669         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2670                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2671                         PIN_BASED_POSTED_INTR;
2672
2673         /* exit controls */
2674         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2675                 vmx->nested.nested_vmx_exit_ctls_low,
2676                 vmx->nested.nested_vmx_exit_ctls_high);
2677         vmx->nested.nested_vmx_exit_ctls_low =
2678                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2679
2680         vmx->nested.nested_vmx_exit_ctls_high &=
2681 #ifdef CONFIG_X86_64
2682                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2683 #endif
2684                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2685         vmx->nested.nested_vmx_exit_ctls_high |=
2686                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2687                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2688                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2689
2690         if (kvm_mpx_supported())
2691                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2692
2693         /* We support free control of debug control saving. */
2694         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2695
2696         /* entry controls */
2697         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2698                 vmx->nested.nested_vmx_entry_ctls_low,
2699                 vmx->nested.nested_vmx_entry_ctls_high);
2700         vmx->nested.nested_vmx_entry_ctls_low =
2701                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2702         vmx->nested.nested_vmx_entry_ctls_high &=
2703 #ifdef CONFIG_X86_64
2704                 VM_ENTRY_IA32E_MODE |
2705 #endif
2706                 VM_ENTRY_LOAD_IA32_PAT;
2707         vmx->nested.nested_vmx_entry_ctls_high |=
2708                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2709         if (kvm_mpx_supported())
2710                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2711
2712         /* We support free control of debug control loading. */
2713         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2714
2715         /* cpu-based controls */
2716         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2717                 vmx->nested.nested_vmx_procbased_ctls_low,
2718                 vmx->nested.nested_vmx_procbased_ctls_high);
2719         vmx->nested.nested_vmx_procbased_ctls_low =
2720                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2721         vmx->nested.nested_vmx_procbased_ctls_high &=
2722                 CPU_BASED_VIRTUAL_INTR_PENDING |
2723                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2724                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2725                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2726                 CPU_BASED_CR3_STORE_EXITING |
2727 #ifdef CONFIG_X86_64
2728                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2729 #endif
2730                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2731                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2732                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2733                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2734                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2735         /*
2736          * We can allow some features even when not supported by the
2737          * hardware. For example, L1 can specify an MSR bitmap - and we
2738          * can use it to avoid exits to L1 - even when L0 runs L2
2739          * without MSR bitmaps.
2740          */
2741         vmx->nested.nested_vmx_procbased_ctls_high |=
2742                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2743                 CPU_BASED_USE_MSR_BITMAPS;
2744
2745         /* We support free control of CR3 access interception. */
2746         vmx->nested.nested_vmx_procbased_ctls_low &=
2747                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2748
2749         /* secondary cpu-based controls */
2750         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2751                 vmx->nested.nested_vmx_secondary_ctls_low,
2752                 vmx->nested.nested_vmx_secondary_ctls_high);
2753         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2754         vmx->nested.nested_vmx_secondary_ctls_high &=
2755                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2756                 SECONDARY_EXEC_RDTSCP |
2757                 SECONDARY_EXEC_DESC |
2758                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2759                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2760                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2761                 SECONDARY_EXEC_WBINVD_EXITING |
2762                 SECONDARY_EXEC_XSAVES;
2763
2764         if (enable_ept) {
2765                 /* nested EPT: emulate EPT also to L1 */
2766                 vmx->nested.nested_vmx_secondary_ctls_high |=
2767                         SECONDARY_EXEC_ENABLE_EPT;
2768                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2769                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2770                          VMX_EPT_INVEPT_BIT;
2771                 if (cpu_has_vmx_ept_execute_only())
2772                         vmx->nested.nested_vmx_ept_caps |=
2773                                 VMX_EPT_EXECUTE_ONLY_BIT;
2774                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2775                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2776                         VMX_EPT_EXTENT_CONTEXT_BIT;
2777         } else
2778                 vmx->nested.nested_vmx_ept_caps = 0;
2779
2780         /*
2781          * Old versions of KVM use the single-context version without
2782          * checking for support, so declare that it is supported even
2783          * though it is treated as global context.  The alternative is
2784          * not failing the single-context invvpid, and it is worse.
2785          */
2786         if (enable_vpid) {
2787                 vmx->nested.nested_vmx_secondary_ctls_high |=
2788                         SECONDARY_EXEC_ENABLE_VPID;
2789                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2790                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2791         } else
2792                 vmx->nested.nested_vmx_vpid_caps = 0;
2793
2794         if (enable_unrestricted_guest)
2795                 vmx->nested.nested_vmx_secondary_ctls_high |=
2796                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2797
2798         /* miscellaneous data */
2799         rdmsr(MSR_IA32_VMX_MISC,
2800                 vmx->nested.nested_vmx_misc_low,
2801                 vmx->nested.nested_vmx_misc_high);
2802         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2803         vmx->nested.nested_vmx_misc_low |=
2804                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2805                 VMX_MISC_ACTIVITY_HLT;
2806         vmx->nested.nested_vmx_misc_high = 0;
2807
2808         /*
2809          * This MSR reports some information about VMX support. We
2810          * should return information about the VMX we emulate for the
2811          * guest, and the VMCS structure we give it - not about the
2812          * VMX support of the underlying hardware.
2813          */
2814         vmx->nested.nested_vmx_basic =
2815                 VMCS12_REVISION |
2816                 VMX_BASIC_TRUE_CTLS |
2817                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2818                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2819
2820         if (cpu_has_vmx_basic_inout())
2821                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2822
2823         /*
2824          * These MSRs specify bits which the guest must keep fixed on
2825          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2826          * We picked the standard core2 setting.
2827          */
2828 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2829 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2830         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2831         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2832
2833         /* These MSRs specify bits which the guest must keep fixed off. */
2834         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2835         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2836
2837         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2838         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2839 }
2840
2841 /*
2842  * if fixed0[i] == 1: val[i] must be 1
2843  * if fixed1[i] == 0: val[i] must be 0
2844  */
2845 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2846 {
2847         return ((val & fixed1) | fixed0) == val;
2848 }
2849
2850 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2851 {
2852         return fixed_bits_valid(control, low, high);
2853 }
2854
2855 static inline u64 vmx_control_msr(u32 low, u32 high)
2856 {
2857         return low | ((u64)high << 32);
2858 }
2859
2860 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2861 {
2862         superset &= mask;
2863         subset &= mask;
2864
2865         return (superset | subset) == superset;
2866 }
2867
2868 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2869 {
2870         const u64 feature_and_reserved =
2871                 /* feature (except bit 48; see below) */
2872                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2873                 /* reserved */
2874                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2875         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2876
2877         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2878                 return -EINVAL;
2879
2880         /*
2881          * KVM does not emulate a version of VMX that constrains physical
2882          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2883          */
2884         if (data & BIT_ULL(48))
2885                 return -EINVAL;
2886
2887         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2888             vmx_basic_vmcs_revision_id(data))
2889                 return -EINVAL;
2890
2891         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2892                 return -EINVAL;
2893
2894         vmx->nested.nested_vmx_basic = data;
2895         return 0;
2896 }
2897
2898 static int
2899 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2900 {
2901         u64 supported;
2902         u32 *lowp, *highp;
2903
2904         switch (msr_index) {
2905         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2906                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2907                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2908                 break;
2909         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2910                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2911                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2912                 break;
2913         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2914                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2915                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2916                 break;
2917         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2918                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2919                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2920                 break;
2921         case MSR_IA32_VMX_PROCBASED_CTLS2:
2922                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2923                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2924                 break;
2925         default:
2926                 BUG();
2927         }
2928
2929         supported = vmx_control_msr(*lowp, *highp);
2930
2931         /* Check must-be-1 bits are still 1. */
2932         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2933                 return -EINVAL;
2934
2935         /* Check must-be-0 bits are still 0. */
2936         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2937                 return -EINVAL;
2938
2939         *lowp = data;
2940         *highp = data >> 32;
2941         return 0;
2942 }
2943
2944 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2945 {
2946         const u64 feature_and_reserved_bits =
2947                 /* feature */
2948                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2949                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2950                 /* reserved */
2951                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2952         u64 vmx_misc;
2953
2954         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2955                                    vmx->nested.nested_vmx_misc_high);
2956
2957         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2958                 return -EINVAL;
2959
2960         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2961              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2962             vmx_misc_preemption_timer_rate(data) !=
2963             vmx_misc_preemption_timer_rate(vmx_misc))
2964                 return -EINVAL;
2965
2966         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2967                 return -EINVAL;
2968
2969         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2970                 return -EINVAL;
2971
2972         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2973                 return -EINVAL;
2974
2975         vmx->nested.nested_vmx_misc_low = data;
2976         vmx->nested.nested_vmx_misc_high = data >> 32;
2977         return 0;
2978 }
2979
2980 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2981 {
2982         u64 vmx_ept_vpid_cap;
2983
2984         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2985                                            vmx->nested.nested_vmx_vpid_caps);
2986
2987         /* Every bit is either reserved or a feature bit. */
2988         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2989                 return -EINVAL;
2990
2991         vmx->nested.nested_vmx_ept_caps = data;
2992         vmx->nested.nested_vmx_vpid_caps = data >> 32;
2993         return 0;
2994 }
2995
2996 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2997 {
2998         u64 *msr;
2999
3000         switch (msr_index) {
3001         case MSR_IA32_VMX_CR0_FIXED0:
3002                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3003                 break;
3004         case MSR_IA32_VMX_CR4_FIXED0:
3005                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3006                 break;
3007         default:
3008                 BUG();
3009         }
3010
3011         /*
3012          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3013          * must be 1 in the restored value.
3014          */
3015         if (!is_bitwise_subset(data, *msr, -1ULL))
3016                 return -EINVAL;
3017
3018         *msr = data;
3019         return 0;
3020 }
3021
3022 /*
3023  * Called when userspace is restoring VMX MSRs.
3024  *
3025  * Returns 0 on success, non-0 otherwise.
3026  */
3027 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3028 {
3029         struct vcpu_vmx *vmx = to_vmx(vcpu);
3030
3031         switch (msr_index) {
3032         case MSR_IA32_VMX_BASIC:
3033                 return vmx_restore_vmx_basic(vmx, data);
3034         case MSR_IA32_VMX_PINBASED_CTLS:
3035         case MSR_IA32_VMX_PROCBASED_CTLS:
3036         case MSR_IA32_VMX_EXIT_CTLS:
3037         case MSR_IA32_VMX_ENTRY_CTLS:
3038                 /*
3039                  * The "non-true" VMX capability MSRs are generated from the
3040                  * "true" MSRs, so we do not support restoring them directly.
3041                  *
3042                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3043                  * should restore the "true" MSRs with the must-be-1 bits
3044                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3045                  * DEFAULT SETTINGS".
3046                  */
3047                 return -EINVAL;
3048         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3049         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3050         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3051         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3052         case MSR_IA32_VMX_PROCBASED_CTLS2:
3053                 return vmx_restore_control_msr(vmx, msr_index, data);
3054         case MSR_IA32_VMX_MISC:
3055                 return vmx_restore_vmx_misc(vmx, data);
3056         case MSR_IA32_VMX_CR0_FIXED0:
3057         case MSR_IA32_VMX_CR4_FIXED0:
3058                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3059         case MSR_IA32_VMX_CR0_FIXED1:
3060         case MSR_IA32_VMX_CR4_FIXED1:
3061                 /*
3062                  * These MSRs are generated based on the vCPU's CPUID, so we
3063                  * do not support restoring them directly.
3064                  */
3065                 return -EINVAL;
3066         case MSR_IA32_VMX_EPT_VPID_CAP:
3067                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3068         case MSR_IA32_VMX_VMCS_ENUM:
3069                 vmx->nested.nested_vmx_vmcs_enum = data;
3070                 return 0;
3071         default:
3072                 /*
3073                  * The rest of the VMX capability MSRs do not support restore.
3074                  */
3075                 return -EINVAL;
3076         }
3077 }
3078
3079 /* Returns 0 on success, non-0 otherwise. */
3080 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3081 {
3082         struct vcpu_vmx *vmx = to_vmx(vcpu);
3083
3084         switch (msr_index) {
3085         case MSR_IA32_VMX_BASIC:
3086                 *pdata = vmx->nested.nested_vmx_basic;
3087                 break;
3088         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3089         case MSR_IA32_VMX_PINBASED_CTLS:
3090                 *pdata = vmx_control_msr(
3091                         vmx->nested.nested_vmx_pinbased_ctls_low,
3092                         vmx->nested.nested_vmx_pinbased_ctls_high);
3093                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3094                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3095                 break;
3096         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3097         case MSR_IA32_VMX_PROCBASED_CTLS:
3098                 *pdata = vmx_control_msr(
3099                         vmx->nested.nested_vmx_procbased_ctls_low,
3100                         vmx->nested.nested_vmx_procbased_ctls_high);
3101                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3102                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3103                 break;
3104         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3105         case MSR_IA32_VMX_EXIT_CTLS:
3106                 *pdata = vmx_control_msr(
3107                         vmx->nested.nested_vmx_exit_ctls_low,
3108                         vmx->nested.nested_vmx_exit_ctls_high);
3109                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3110                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3111                 break;
3112         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3113         case MSR_IA32_VMX_ENTRY_CTLS:
3114                 *pdata = vmx_control_msr(
3115                         vmx->nested.nested_vmx_entry_ctls_low,
3116                         vmx->nested.nested_vmx_entry_ctls_high);
3117                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3118                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3119                 break;
3120         case MSR_IA32_VMX_MISC:
3121                 *pdata = vmx_control_msr(
3122                         vmx->nested.nested_vmx_misc_low,
3123                         vmx->nested.nested_vmx_misc_high);
3124                 break;
3125         case MSR_IA32_VMX_CR0_FIXED0:
3126                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3127                 break;
3128         case MSR_IA32_VMX_CR0_FIXED1:
3129                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3130                 break;
3131         case MSR_IA32_VMX_CR4_FIXED0:
3132                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3133                 break;
3134         case MSR_IA32_VMX_CR4_FIXED1:
3135                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3136                 break;
3137         case MSR_IA32_VMX_VMCS_ENUM:
3138                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3139                 break;
3140         case MSR_IA32_VMX_PROCBASED_CTLS2:
3141                 *pdata = vmx_control_msr(
3142                         vmx->nested.nested_vmx_secondary_ctls_low,
3143                         vmx->nested.nested_vmx_secondary_ctls_high);
3144                 break;
3145         case MSR_IA32_VMX_EPT_VPID_CAP:
3146                 *pdata = vmx->nested.nested_vmx_ept_caps |
3147                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3148                 break;
3149         default:
3150                 return 1;
3151         }
3152
3153         return 0;
3154 }
3155
3156 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3157                                                  uint64_t val)
3158 {
3159         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3160
3161         return !(val & ~valid_bits);
3162 }
3163
3164 /*
3165  * Reads an msr value (of 'msr_index') into 'pdata'.
3166  * Returns 0 on success, non-0 otherwise.
3167  * Assumes vcpu_load() was already called.
3168  */
3169 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3170 {
3171         struct shared_msr_entry *msr;
3172
3173         switch (msr_info->index) {
3174 #ifdef CONFIG_X86_64
3175         case MSR_FS_BASE:
3176                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3177                 break;
3178         case MSR_GS_BASE:
3179                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3180                 break;
3181         case MSR_KERNEL_GS_BASE:
3182                 vmx_load_host_state(to_vmx(vcpu));
3183                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3184                 break;
3185 #endif
3186         case MSR_EFER:
3187                 return kvm_get_msr_common(vcpu, msr_info);
3188         case MSR_IA32_TSC:
3189                 msr_info->data = guest_read_tsc(vcpu);
3190                 break;
3191         case MSR_IA32_SYSENTER_CS:
3192                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3193                 break;
3194         case MSR_IA32_SYSENTER_EIP:
3195                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3196                 break;
3197         case MSR_IA32_SYSENTER_ESP:
3198                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3199                 break;
3200         case MSR_IA32_BNDCFGS:
3201                 if (!kvm_mpx_supported())
3202                         return 1;
3203                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3204                 break;
3205         case MSR_IA32_MCG_EXT_CTL:
3206                 if (!msr_info->host_initiated &&
3207                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3208                       FEATURE_CONTROL_LMCE))
3209                         return 1;
3210                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3211                 break;
3212         case MSR_IA32_FEATURE_CONTROL:
3213                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3214                 break;
3215         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3216                 if (!nested_vmx_allowed(vcpu))
3217                         return 1;
3218                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3219         case MSR_IA32_XSS:
3220                 if (!vmx_xsaves_supported())
3221                         return 1;
3222                 msr_info->data = vcpu->arch.ia32_xss;
3223                 break;
3224         case MSR_TSC_AUX:
3225                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3226                         return 1;
3227                 /* Otherwise falls through */
3228         default:
3229                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3230                 if (msr) {
3231                         msr_info->data = msr->data;
3232                         break;
3233                 }
3234                 return kvm_get_msr_common(vcpu, msr_info);
3235         }
3236
3237         return 0;
3238 }
3239
3240 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3241
3242 /*
3243  * Writes msr value into into the appropriate "register".
3244  * Returns 0 on success, non-0 otherwise.
3245  * Assumes vcpu_load() was already called.
3246  */
3247 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3248 {
3249         struct vcpu_vmx *vmx = to_vmx(vcpu);
3250         struct shared_msr_entry *msr;
3251         int ret = 0;
3252         u32 msr_index = msr_info->index;
3253         u64 data = msr_info->data;
3254
3255         switch (msr_index) {
3256         case MSR_EFER:
3257                 ret = kvm_set_msr_common(vcpu, msr_info);
3258                 break;
3259 #ifdef CONFIG_X86_64
3260         case MSR_FS_BASE:
3261                 vmx_segment_cache_clear(vmx);
3262                 vmcs_writel(GUEST_FS_BASE, data);
3263                 break;
3264         case MSR_GS_BASE:
3265                 vmx_segment_cache_clear(vmx);
3266                 vmcs_writel(GUEST_GS_BASE, data);
3267                 break;
3268         case MSR_KERNEL_GS_BASE:
3269                 vmx_load_host_state(vmx);
3270                 vmx->msr_guest_kernel_gs_base = data;
3271                 break;
3272 #endif
3273         case MSR_IA32_SYSENTER_CS:
3274                 vmcs_write32(GUEST_SYSENTER_CS, data);
3275                 break;
3276         case MSR_IA32_SYSENTER_EIP:
3277                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3278                 break;
3279         case MSR_IA32_SYSENTER_ESP:
3280                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3281                 break;
3282         case MSR_IA32_BNDCFGS:
3283                 if (!kvm_mpx_supported())
3284                         return 1;
3285                 vmcs_write64(GUEST_BNDCFGS, data);
3286                 break;
3287         case MSR_IA32_TSC:
3288                 kvm_write_tsc(vcpu, msr_info);
3289                 break;
3290         case MSR_IA32_CR_PAT:
3291                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3292                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3293                                 return 1;
3294                         vmcs_write64(GUEST_IA32_PAT, data);
3295                         vcpu->arch.pat = data;
3296                         break;
3297                 }
3298                 ret = kvm_set_msr_common(vcpu, msr_info);
3299                 break;
3300         case MSR_IA32_TSC_ADJUST:
3301                 ret = kvm_set_msr_common(vcpu, msr_info);
3302                 break;
3303         case MSR_IA32_MCG_EXT_CTL:
3304                 if ((!msr_info->host_initiated &&
3305                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3306                        FEATURE_CONTROL_LMCE)) ||
3307                     (data & ~MCG_EXT_CTL_LMCE_EN))
3308                         return 1;
3309                 vcpu->arch.mcg_ext_ctl = data;
3310                 break;
3311         case MSR_IA32_FEATURE_CONTROL:
3312                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3313                     (to_vmx(vcpu)->msr_ia32_feature_control &
3314                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3315                         return 1;
3316                 vmx->msr_ia32_feature_control = data;
3317                 if (msr_info->host_initiated && data == 0)
3318                         vmx_leave_nested(vcpu);
3319                 break;
3320         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3321                 if (!msr_info->host_initiated)
3322                         return 1; /* they are read-only */
3323                 if (!nested_vmx_allowed(vcpu))
3324                         return 1;
3325                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3326         case MSR_IA32_XSS:
3327                 if (!vmx_xsaves_supported())
3328                         return 1;
3329                 /*
3330                  * The only supported bit as of Skylake is bit 8, but
3331                  * it is not supported on KVM.
3332                  */
3333                 if (data != 0)
3334                         return 1;
3335                 vcpu->arch.ia32_xss = data;
3336                 if (vcpu->arch.ia32_xss != host_xss)
3337                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3338                                 vcpu->arch.ia32_xss, host_xss);
3339                 else
3340                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3341                 break;
3342         case MSR_TSC_AUX:
3343                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3344                         return 1;
3345                 /* Check reserved bit, higher 32 bits should be zero */
3346                 if ((data >> 32) != 0)
3347                         return 1;
3348                 /* Otherwise falls through */
3349         default:
3350                 msr = find_msr_entry(vmx, msr_index);
3351                 if (msr) {
3352                         u64 old_msr_data = msr->data;
3353                         msr->data = data;
3354                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3355                                 preempt_disable();
3356                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3357                                                          msr->mask);
3358                                 preempt_enable();
3359                                 if (ret)
3360                                         msr->data = old_msr_data;
3361                         }
3362                         break;
3363                 }
3364                 ret = kvm_set_msr_common(vcpu, msr_info);
3365         }
3366
3367         return ret;
3368 }
3369
3370 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3371 {
3372         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3373         switch (reg) {
3374         case VCPU_REGS_RSP:
3375                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3376                 break;
3377         case VCPU_REGS_RIP:
3378                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3379                 break;
3380         case VCPU_EXREG_PDPTR:
3381                 if (enable_ept)
3382                         ept_save_pdptrs(vcpu);
3383                 break;
3384         default:
3385                 break;
3386         }
3387 }
3388
3389 static __init int cpu_has_kvm_support(void)
3390 {
3391         return cpu_has_vmx();
3392 }
3393
3394 static __init int vmx_disabled_by_bios(void)
3395 {
3396         u64 msr;
3397
3398         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3399         if (msr & FEATURE_CONTROL_LOCKED) {
3400                 /* launched w/ TXT and VMX disabled */
3401                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3402                         && tboot_enabled())
3403                         return 1;
3404                 /* launched w/o TXT and VMX only enabled w/ TXT */
3405                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3406                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3407                         && !tboot_enabled()) {
3408                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3409                                 "activate TXT before enabling KVM\n");
3410                         return 1;
3411                 }
3412                 /* launched w/o TXT and VMX disabled */
3413                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3414                         && !tboot_enabled())
3415                         return 1;
3416         }
3417
3418         return 0;
3419 }
3420
3421 static void kvm_cpu_vmxon(u64 addr)
3422 {
3423         intel_pt_handle_vmx(1);
3424
3425         asm volatile (ASM_VMX_VMXON_RAX
3426                         : : "a"(&addr), "m"(addr)
3427                         : "memory", "cc");
3428 }
3429
3430 static int hardware_enable(void)
3431 {
3432         int cpu = raw_smp_processor_id();
3433         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3434         u64 old, test_bits;
3435
3436         if (cr4_read_shadow() & X86_CR4_VMXE)
3437                 return -EBUSY;
3438
3439         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3440         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3441         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3442
3443         /*
3444          * Now we can enable the vmclear operation in kdump
3445          * since the loaded_vmcss_on_cpu list on this cpu
3446          * has been initialized.
3447          *
3448          * Though the cpu is not in VMX operation now, there
3449          * is no problem to enable the vmclear operation
3450          * for the loaded_vmcss_on_cpu list is empty!
3451          */
3452         crash_enable_local_vmclear(cpu);
3453
3454         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3455
3456         test_bits = FEATURE_CONTROL_LOCKED;
3457         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3458         if (tboot_enabled())
3459                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3460
3461         if ((old & test_bits) != test_bits) {
3462                 /* enable and lock */
3463                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3464         }
3465         cr4_set_bits(X86_CR4_VMXE);
3466
3467         if (vmm_exclusive) {
3468                 kvm_cpu_vmxon(phys_addr);
3469                 ept_sync_global();
3470         }
3471
3472         return 0;
3473 }
3474
3475 static void vmclear_local_loaded_vmcss(void)
3476 {
3477         int cpu = raw_smp_processor_id();
3478         struct loaded_vmcs *v, *n;
3479
3480         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3481                                  loaded_vmcss_on_cpu_link)
3482                 __loaded_vmcs_clear(v);
3483 }
3484
3485
3486 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3487  * tricks.
3488  */
3489 static void kvm_cpu_vmxoff(void)
3490 {
3491         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3492
3493         intel_pt_handle_vmx(0);
3494 }
3495
3496 static void hardware_disable(void)
3497 {
3498         if (vmm_exclusive) {
3499                 vmclear_local_loaded_vmcss();
3500                 kvm_cpu_vmxoff();
3501         }
3502         cr4_clear_bits(X86_CR4_VMXE);
3503 }
3504
3505 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3506                                       u32 msr, u32 *result)
3507 {
3508         u32 vmx_msr_low, vmx_msr_high;
3509         u32 ctl = ctl_min | ctl_opt;
3510
3511         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3512
3513         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3514         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3515
3516         /* Ensure minimum (required) set of control bits are supported. */
3517         if (ctl_min & ~ctl)
3518                 return -EIO;
3519
3520         *result = ctl;
3521         return 0;
3522 }
3523
3524 static __init bool allow_1_setting(u32 msr, u32 ctl)
3525 {
3526         u32 vmx_msr_low, vmx_msr_high;
3527
3528         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3529         return vmx_msr_high & ctl;
3530 }
3531
3532 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3533 {
3534         u32 vmx_msr_low, vmx_msr_high;
3535         u32 min, opt, min2, opt2;
3536         u32 _pin_based_exec_control = 0;
3537         u32 _cpu_based_exec_control = 0;
3538         u32 _cpu_based_2nd_exec_control = 0;
3539         u32 _vmexit_control = 0;
3540         u32 _vmentry_control = 0;
3541
3542         min = CPU_BASED_HLT_EXITING |
3543 #ifdef CONFIG_X86_64
3544               CPU_BASED_CR8_LOAD_EXITING |
3545               CPU_BASED_CR8_STORE_EXITING |
3546 #endif
3547               CPU_BASED_CR3_LOAD_EXITING |
3548               CPU_BASED_CR3_STORE_EXITING |
3549               CPU_BASED_USE_IO_BITMAPS |
3550               CPU_BASED_MOV_DR_EXITING |
3551               CPU_BASED_USE_TSC_OFFSETING |
3552               CPU_BASED_MWAIT_EXITING |
3553               CPU_BASED_MONITOR_EXITING |
3554               CPU_BASED_INVLPG_EXITING |
3555               CPU_BASED_RDPMC_EXITING;
3556
3557         opt = CPU_BASED_TPR_SHADOW |
3558               CPU_BASED_USE_MSR_BITMAPS |
3559               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3560         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3561                                 &_cpu_based_exec_control) < 0)
3562                 return -EIO;
3563 #ifdef CONFIG_X86_64
3564         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3565                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3566                                            ~CPU_BASED_CR8_STORE_EXITING;
3567 #endif
3568         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3569                 min2 = 0;
3570                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3571                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3572                         SECONDARY_EXEC_WBINVD_EXITING |
3573                         SECONDARY_EXEC_ENABLE_VPID |
3574                         SECONDARY_EXEC_ENABLE_EPT |
3575                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3576                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3577                         SECONDARY_EXEC_RDTSCP |
3578                         SECONDARY_EXEC_ENABLE_INVPCID |
3579                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3580                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3581                         SECONDARY_EXEC_SHADOW_VMCS |
3582                         SECONDARY_EXEC_XSAVES |
3583                         SECONDARY_EXEC_ENABLE_PML |
3584                         SECONDARY_EXEC_TSC_SCALING;
3585                 if (adjust_vmx_controls(min2, opt2,
3586                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3587                                         &_cpu_based_2nd_exec_control) < 0)
3588                         return -EIO;
3589         }
3590 #ifndef CONFIG_X86_64
3591         if (!(_cpu_based_2nd_exec_control &
3592                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3593                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3594 #endif
3595
3596         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3597                 _cpu_based_2nd_exec_control &= ~(
3598                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3599                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3600                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3601
3602         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3603                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3604                    enabled */
3605                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3606                                              CPU_BASED_CR3_STORE_EXITING |
3607                                              CPU_BASED_INVLPG_EXITING);
3608                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3609                       vmx_capability.ept, vmx_capability.vpid);
3610         }
3611
3612         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3613 #ifdef CONFIG_X86_64
3614         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3615 #endif
3616         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3617                 VM_EXIT_CLEAR_BNDCFGS;
3618         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3619                                 &_vmexit_control) < 0)
3620                 return -EIO;
3621
3622         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3623         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3624                  PIN_BASED_VMX_PREEMPTION_TIMER;
3625         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3626                                 &_pin_based_exec_control) < 0)
3627                 return -EIO;
3628
3629         if (cpu_has_broken_vmx_preemption_timer())
3630                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3631         if (!(_cpu_based_2nd_exec_control &
3632                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3633                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3634
3635         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3636         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3637         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3638                                 &_vmentry_control) < 0)
3639                 return -EIO;
3640
3641         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3642
3643         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3644         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3645                 return -EIO;
3646
3647 #ifdef CONFIG_X86_64
3648         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3649         if (vmx_msr_high & (1u<<16))
3650                 return -EIO;
3651 #endif
3652
3653         /* Require Write-Back (WB) memory type for VMCS accesses. */
3654         if (((vmx_msr_high >> 18) & 15) != 6)
3655                 return -EIO;
3656
3657         vmcs_conf->size = vmx_msr_high & 0x1fff;
3658         vmcs_conf->order = get_order(vmcs_conf->size);
3659         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3660         vmcs_conf->revision_id = vmx_msr_low;
3661
3662         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3663         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3664         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3665         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3666         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3667
3668         cpu_has_load_ia32_efer =
3669                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3670                                 VM_ENTRY_LOAD_IA32_EFER)
3671                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3672                                    VM_EXIT_LOAD_IA32_EFER);
3673
3674         cpu_has_load_perf_global_ctrl =
3675                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3676                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3677                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3678                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3679
3680         /*
3681          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3682          * but due to errata below it can't be used. Workaround is to use
3683          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3684          *
3685          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3686          *
3687          * AAK155             (model 26)
3688          * AAP115             (model 30)
3689          * AAT100             (model 37)
3690          * BC86,AAY89,BD102   (model 44)
3691          * BA97               (model 46)
3692          *
3693          */
3694         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3695                 switch (boot_cpu_data.x86_model) {
3696                 case 26:
3697                 case 30:
3698                 case 37:
3699                 case 44:
3700                 case 46:
3701                         cpu_has_load_perf_global_ctrl = false;
3702                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3703                                         "does not work properly. Using workaround\n");
3704                         break;
3705                 default:
3706                         break;
3707                 }
3708         }
3709
3710         if (boot_cpu_has(X86_FEATURE_XSAVES))
3711                 rdmsrl(MSR_IA32_XSS, host_xss);
3712
3713         return 0;
3714 }
3715
3716 static struct vmcs *alloc_vmcs_cpu(int cpu)
3717 {
3718         int node = cpu_to_node(cpu);
3719         struct page *pages;
3720         struct vmcs *vmcs;
3721
3722         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3723         if (!pages)
3724                 return NULL;
3725         vmcs = page_address(pages);
3726         memset(vmcs, 0, vmcs_config.size);
3727         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3728         return vmcs;
3729 }
3730
3731 static struct vmcs *alloc_vmcs(void)
3732 {
3733         return alloc_vmcs_cpu(raw_smp_processor_id());
3734 }
3735
3736 static void free_vmcs(struct vmcs *vmcs)
3737 {
3738         free_pages((unsigned long)vmcs, vmcs_config.order);
3739 }
3740
3741 /*
3742  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3743  */
3744 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3745 {
3746         if (!loaded_vmcs->vmcs)
3747                 return;
3748         loaded_vmcs_clear(loaded_vmcs);
3749         free_vmcs(loaded_vmcs->vmcs);
3750         loaded_vmcs->vmcs = NULL;
3751         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3752 }
3753
3754 static void free_kvm_area(void)
3755 {
3756         int cpu;
3757
3758         for_each_possible_cpu(cpu) {
3759                 free_vmcs(per_cpu(vmxarea, cpu));
3760                 per_cpu(vmxarea, cpu) = NULL;
3761         }
3762 }
3763
3764 static void init_vmcs_shadow_fields(void)
3765 {
3766         int i, j;
3767
3768         /* No checks for read only fields yet */
3769
3770         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3771                 switch (shadow_read_write_fields[i]) {
3772                 case GUEST_BNDCFGS:
3773                         if (!kvm_mpx_supported())
3774                                 continue;
3775                         break;
3776                 default:
3777                         break;
3778                 }
3779
3780                 if (j < i)
3781                         shadow_read_write_fields[j] =
3782                                 shadow_read_write_fields[i];
3783                 j++;
3784         }
3785         max_shadow_read_write_fields = j;
3786
3787         /* shadowed fields guest access without vmexit */
3788         for (i = 0; i < max_shadow_read_write_fields; i++) {
3789                 clear_bit(shadow_read_write_fields[i],
3790                           vmx_vmwrite_bitmap);
3791                 clear_bit(shadow_read_write_fields[i],
3792                           vmx_vmread_bitmap);
3793         }
3794         for (i = 0; i < max_shadow_read_only_fields; i++)
3795                 clear_bit(shadow_read_only_fields[i],
3796                           vmx_vmread_bitmap);
3797 }
3798
3799 static __init int alloc_kvm_area(void)
3800 {
3801         int cpu;
3802
3803         for_each_possible_cpu(cpu) {
3804                 struct vmcs *vmcs;
3805
3806                 vmcs = alloc_vmcs_cpu(cpu);
3807                 if (!vmcs) {
3808                         free_kvm_area();
3809                         return -ENOMEM;
3810                 }
3811
3812                 per_cpu(vmxarea, cpu) = vmcs;
3813         }
3814         return 0;
3815 }
3816
3817 static bool emulation_required(struct kvm_vcpu *vcpu)
3818 {
3819         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3820 }
3821
3822 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3823                 struct kvm_segment *save)
3824 {
3825         if (!emulate_invalid_guest_state) {
3826                 /*
3827                  * CS and SS RPL should be equal during guest entry according
3828                  * to VMX spec, but in reality it is not always so. Since vcpu
3829                  * is in the middle of the transition from real mode to
3830                  * protected mode it is safe to assume that RPL 0 is a good
3831                  * default value.
3832                  */
3833                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3834                         save->selector &= ~SEGMENT_RPL_MASK;
3835                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3836                 save->s = 1;
3837         }
3838         vmx_set_segment(vcpu, save, seg);
3839 }
3840
3841 static void enter_pmode(struct kvm_vcpu *vcpu)
3842 {
3843         unsigned long flags;
3844         struct vcpu_vmx *vmx = to_vmx(vcpu);
3845
3846         /*
3847          * Update real mode segment cache. It may be not up-to-date if sement
3848          * register was written while vcpu was in a guest mode.
3849          */
3850         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3851         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3852         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3853         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3854         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3855         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3856
3857         vmx->rmode.vm86_active = 0;
3858
3859         vmx_segment_cache_clear(vmx);
3860
3861         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3862
3863         flags = vmcs_readl(GUEST_RFLAGS);
3864         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3865         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3866         vmcs_writel(GUEST_RFLAGS, flags);
3867
3868         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3869                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3870
3871         update_exception_bitmap(vcpu);
3872
3873         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3874         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3875         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3876         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3877         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3878         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3879 }
3880
3881 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3882 {
3883         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3884         struct kvm_segment var = *save;
3885
3886         var.dpl = 0x3;
3887         if (seg == VCPU_SREG_CS)
3888                 var.type = 0x3;
3889
3890         if (!emulate_invalid_guest_state) {
3891                 var.selector = var.base >> 4;
3892                 var.base = var.base & 0xffff0;
3893                 var.limit = 0xffff;
3894                 var.g = 0;
3895                 var.db = 0;
3896                 var.present = 1;
3897                 var.s = 1;
3898                 var.l = 0;
3899                 var.unusable = 0;
3900                 var.type = 0x3;
3901                 var.avl = 0;
3902                 if (save->base & 0xf)
3903                         printk_once(KERN_WARNING "kvm: segment base is not "
3904                                         "paragraph aligned when entering "
3905                                         "protected mode (seg=%d)", seg);
3906         }
3907
3908         vmcs_write16(sf->selector, var.selector);
3909         vmcs_writel(sf->base, var.base);
3910         vmcs_write32(sf->limit, var.limit);
3911         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3912 }
3913
3914 static void enter_rmode(struct kvm_vcpu *vcpu)
3915 {
3916         unsigned long flags;
3917         struct vcpu_vmx *vmx = to_vmx(vcpu);
3918
3919         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3920         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3921         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3922         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3923         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3924         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3925         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3926
3927         vmx->rmode.vm86_active = 1;
3928
3929         /*
3930          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3931          * vcpu. Warn the user that an update is overdue.
3932          */
3933         if (!vcpu->kvm->arch.tss_addr)
3934                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3935                              "called before entering vcpu\n");
3936
3937         vmx_segment_cache_clear(vmx);
3938
3939         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3940         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3941         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3942
3943         flags = vmcs_readl(GUEST_RFLAGS);
3944         vmx->rmode.save_rflags = flags;
3945
3946         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3947
3948         vmcs_writel(GUEST_RFLAGS, flags);
3949         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3950         update_exception_bitmap(vcpu);
3951
3952         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3953         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3954         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3955         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3956         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3957         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3958
3959         kvm_mmu_reset_context(vcpu);
3960 }
3961
3962 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3963 {
3964         struct vcpu_vmx *vmx = to_vmx(vcpu);
3965         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3966
3967         if (!msr)
3968                 return;
3969
3970         /*
3971          * Force kernel_gs_base reloading before EFER changes, as control
3972          * of this msr depends on is_long_mode().
3973          */
3974         vmx_load_host_state(to_vmx(vcpu));
3975         vcpu->arch.efer = efer;
3976         if (efer & EFER_LMA) {
3977                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3978                 msr->data = efer;
3979         } else {
3980                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3981
3982                 msr->data = efer & ~EFER_LME;
3983         }
3984         setup_msrs(vmx);
3985 }
3986
3987 #ifdef CONFIG_X86_64
3988
3989 static void enter_lmode(struct kvm_vcpu *vcpu)
3990 {
3991         u32 guest_tr_ar;
3992
3993         vmx_segment_cache_clear(to_vmx(vcpu));
3994
3995         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3996         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3997                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3998                                      __func__);
3999                 vmcs_write32(GUEST_TR_AR_BYTES,
4000                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4001                              | VMX_AR_TYPE_BUSY_64_TSS);
4002         }
4003         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4004 }
4005
4006 static void exit_lmode(struct kvm_vcpu *vcpu)
4007 {
4008         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4009         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4010 }
4011
4012 #endif
4013
4014 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4015 {
4016         vpid_sync_context(vpid);
4017         if (enable_ept) {
4018                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4019                         return;
4020                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4021         }
4022 }
4023
4024 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4025 {
4026         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4027 }
4028
4029 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4030 {
4031         if (enable_ept)
4032                 vmx_flush_tlb(vcpu);
4033 }
4034
4035 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4036 {
4037         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4038
4039         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4040         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4041 }
4042
4043 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4044 {
4045         if (enable_ept && is_paging(vcpu))
4046                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4047         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4048 }
4049
4050 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4051 {
4052         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4053
4054         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4055         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4056 }
4057
4058 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4059 {
4060         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4061
4062         if (!test_bit(VCPU_EXREG_PDPTR,
4063                       (unsigned long *)&vcpu->arch.regs_dirty))
4064                 return;
4065
4066         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4067                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4068                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4069                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4070                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4071         }
4072 }
4073
4074 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4075 {
4076         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4077
4078         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4079                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4080                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4081                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4082                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4083         }
4084
4085         __set_bit(VCPU_EXREG_PDPTR,
4086                   (unsigned long *)&vcpu->arch.regs_avail);
4087         __set_bit(VCPU_EXREG_PDPTR,
4088                   (unsigned long *)&vcpu->arch.regs_dirty);
4089 }
4090
4091 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4092 {
4093         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4094         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4095         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4096
4097         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4098                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4099             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4100                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4101
4102         return fixed_bits_valid(val, fixed0, fixed1);
4103 }
4104
4105 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4106 {
4107         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4108         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4109
4110         return fixed_bits_valid(val, fixed0, fixed1);
4111 }
4112
4113 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4114 {
4115         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4116         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4117
4118         return fixed_bits_valid(val, fixed0, fixed1);
4119 }
4120
4121 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4122 #define nested_guest_cr4_valid  nested_cr4_valid
4123 #define nested_host_cr4_valid   nested_cr4_valid
4124
4125 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4126
4127 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4128                                         unsigned long cr0,
4129                                         struct kvm_vcpu *vcpu)
4130 {
4131         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4132                 vmx_decache_cr3(vcpu);
4133         if (!(cr0 & X86_CR0_PG)) {
4134                 /* From paging/starting to nonpaging */
4135                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4136                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4137                              (CPU_BASED_CR3_LOAD_EXITING |
4138                               CPU_BASED_CR3_STORE_EXITING));
4139                 vcpu->arch.cr0 = cr0;
4140                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4141         } else if (!is_paging(vcpu)) {
4142                 /* From nonpaging to paging */
4143                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4144                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4145                              ~(CPU_BASED_CR3_LOAD_EXITING |
4146                                CPU_BASED_CR3_STORE_EXITING));
4147                 vcpu->arch.cr0 = cr0;
4148                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4149         }
4150
4151         if (!(cr0 & X86_CR0_WP))
4152                 *hw_cr0 &= ~X86_CR0_WP;
4153 }
4154
4155 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4156 {
4157         struct vcpu_vmx *vmx = to_vmx(vcpu);
4158         unsigned long hw_cr0;
4159
4160         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4161         if (enable_unrestricted_guest)
4162                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4163         else {
4164                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4165
4166                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4167                         enter_pmode(vcpu);
4168
4169                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4170                         enter_rmode(vcpu);
4171         }
4172
4173 #ifdef CONFIG_X86_64
4174         if (vcpu->arch.efer & EFER_LME) {
4175                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4176                         enter_lmode(vcpu);
4177                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4178                         exit_lmode(vcpu);
4179         }
4180 #endif
4181
4182         if (enable_ept)
4183                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4184
4185         vmcs_writel(CR0_READ_SHADOW, cr0);
4186         vmcs_writel(GUEST_CR0, hw_cr0);
4187         vcpu->arch.cr0 = cr0;
4188
4189         /* depends on vcpu->arch.cr0 to be set to a new value */
4190         vmx->emulation_required = emulation_required(vcpu);
4191 }
4192
4193 static u64 construct_eptp(unsigned long root_hpa)
4194 {
4195         u64 eptp;
4196
4197         /* TODO write the value reading from MSR */
4198         eptp = VMX_EPT_DEFAULT_MT |
4199                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4200         if (enable_ept_ad_bits)
4201                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4202         eptp |= (root_hpa & PAGE_MASK);
4203
4204         return eptp;
4205 }
4206
4207 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4208 {
4209         unsigned long guest_cr3;
4210         u64 eptp;
4211
4212         guest_cr3 = cr3;
4213         if (enable_ept) {
4214                 eptp = construct_eptp(cr3);
4215                 vmcs_write64(EPT_POINTER, eptp);
4216                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4217                         guest_cr3 = kvm_read_cr3(vcpu);
4218                 else
4219                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4220                 ept_load_pdptrs(vcpu);
4221         }
4222
4223         vmx_flush_tlb(vcpu);
4224         vmcs_writel(GUEST_CR3, guest_cr3);
4225 }
4226
4227 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4228 {
4229         /*
4230          * Pass through host's Machine Check Enable value to hw_cr4, which
4231          * is in force while we are in guest mode.  Do not let guests control
4232          * this bit, even if host CR4.MCE == 0.
4233          */
4234         unsigned long hw_cr4 =
4235                 (cr4_read_shadow() & X86_CR4_MCE) |
4236                 (cr4 & ~X86_CR4_MCE) |
4237                 (to_vmx(vcpu)->rmode.vm86_active ?
4238                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4239
4240         if (cr4 & X86_CR4_VMXE) {
4241                 /*
4242                  * To use VMXON (and later other VMX instructions), a guest
4243                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4244                  * So basically the check on whether to allow nested VMX
4245                  * is here.
4246                  */
4247                 if (!nested_vmx_allowed(vcpu))
4248                         return 1;
4249         }
4250
4251         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4252                 return 1;
4253
4254         vcpu->arch.cr4 = cr4;
4255         if (enable_ept) {
4256                 if (!is_paging(vcpu)) {
4257                         hw_cr4 &= ~X86_CR4_PAE;
4258                         hw_cr4 |= X86_CR4_PSE;
4259                 } else if (!(cr4 & X86_CR4_PAE)) {
4260                         hw_cr4 &= ~X86_CR4_PAE;
4261                 }
4262         }
4263
4264         if (!enable_unrestricted_guest && !is_paging(vcpu))
4265                 /*
4266                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4267                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4268                  * to be manually disabled when guest switches to non-paging
4269                  * mode.
4270                  *
4271                  * If !enable_unrestricted_guest, the CPU is always running
4272                  * with CR0.PG=1 and CR4 needs to be modified.
4273                  * If enable_unrestricted_guest, the CPU automatically
4274                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4275                  */
4276                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4277
4278         vmcs_writel(CR4_READ_SHADOW, cr4);
4279         vmcs_writel(GUEST_CR4, hw_cr4);
4280         return 0;
4281 }
4282
4283 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4284                             struct kvm_segment *var, int seg)
4285 {
4286         struct vcpu_vmx *vmx = to_vmx(vcpu);
4287         u32 ar;
4288
4289         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4290                 *var = vmx->rmode.segs[seg];
4291                 if (seg == VCPU_SREG_TR
4292                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4293                         return;
4294                 var->base = vmx_read_guest_seg_base(vmx, seg);
4295                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4296                 return;
4297         }
4298         var->base = vmx_read_guest_seg_base(vmx, seg);
4299         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4300         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4301         ar = vmx_read_guest_seg_ar(vmx, seg);
4302         var->unusable = (ar >> 16) & 1;
4303         var->type = ar & 15;
4304         var->s = (ar >> 4) & 1;
4305         var->dpl = (ar >> 5) & 3;
4306         /*
4307          * Some userspaces do not preserve unusable property. Since usable
4308          * segment has to be present according to VMX spec we can use present
4309          * property to amend userspace bug by making unusable segment always
4310          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4311          * segment as unusable.
4312          */
4313         var->present = !var->unusable;
4314         var->avl = (ar >> 12) & 1;
4315         var->l = (ar >> 13) & 1;
4316         var->db = (ar >> 14) & 1;
4317         var->g = (ar >> 15) & 1;
4318 }
4319
4320 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4321 {
4322         struct kvm_segment s;
4323
4324         if (to_vmx(vcpu)->rmode.vm86_active) {
4325                 vmx_get_segment(vcpu, &s, seg);
4326                 return s.base;
4327         }
4328         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4329 }
4330
4331 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4332 {
4333         struct vcpu_vmx *vmx = to_vmx(vcpu);
4334
4335         if (unlikely(vmx->rmode.vm86_active))
4336                 return 0;
4337         else {
4338                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4339                 return VMX_AR_DPL(ar);
4340         }
4341 }
4342
4343 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4344 {
4345         u32 ar;
4346
4347         if (var->unusable || !var->present)
4348                 ar = 1 << 16;
4349         else {
4350                 ar = var->type & 15;
4351                 ar |= (var->s & 1) << 4;
4352                 ar |= (var->dpl & 3) << 5;
4353                 ar |= (var->present & 1) << 7;
4354                 ar |= (var->avl & 1) << 12;
4355                 ar |= (var->l & 1) << 13;
4356                 ar |= (var->db & 1) << 14;
4357                 ar |= (var->g & 1) << 15;
4358         }
4359
4360         return ar;
4361 }
4362
4363 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4364                             struct kvm_segment *var, int seg)
4365 {
4366         struct vcpu_vmx *vmx = to_vmx(vcpu);
4367         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4368
4369         vmx_segment_cache_clear(vmx);
4370
4371         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4372                 vmx->rmode.segs[seg] = *var;
4373                 if (seg == VCPU_SREG_TR)
4374                         vmcs_write16(sf->selector, var->selector);
4375                 else if (var->s)
4376                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4377                 goto out;
4378         }
4379
4380         vmcs_writel(sf->base, var->base);
4381         vmcs_write32(sf->limit, var->limit);
4382         vmcs_write16(sf->selector, var->selector);
4383
4384         /*
4385          *   Fix the "Accessed" bit in AR field of segment registers for older
4386          * qemu binaries.
4387          *   IA32 arch specifies that at the time of processor reset the
4388          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4389          * is setting it to 0 in the userland code. This causes invalid guest
4390          * state vmexit when "unrestricted guest" mode is turned on.
4391          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4392          * tree. Newer qemu binaries with that qemu fix would not need this
4393          * kvm hack.
4394          */
4395         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4396                 var->type |= 0x1; /* Accessed */
4397
4398         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4399
4400 out:
4401         vmx->emulation_required = emulation_required(vcpu);
4402 }
4403
4404 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4405 {
4406         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4407
4408         *db = (ar >> 14) & 1;
4409         *l = (ar >> 13) & 1;
4410 }
4411
4412 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4413 {
4414         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4415         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4416 }
4417
4418 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4419 {
4420         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4421         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4422 }
4423
4424 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4425 {
4426         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4427         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4428 }
4429
4430 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4431 {
4432         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4433         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4434 }
4435
4436 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4437 {
4438         struct kvm_segment var;
4439         u32 ar;
4440
4441         vmx_get_segment(vcpu, &var, seg);
4442         var.dpl = 0x3;
4443         if (seg == VCPU_SREG_CS)
4444                 var.type = 0x3;
4445         ar = vmx_segment_access_rights(&var);
4446
4447         if (var.base != (var.selector << 4))
4448                 return false;
4449         if (var.limit != 0xffff)
4450                 return false;
4451         if (ar != 0xf3)
4452                 return false;
4453
4454         return true;
4455 }
4456
4457 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4458 {
4459         struct kvm_segment cs;
4460         unsigned int cs_rpl;
4461
4462         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4463         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4464
4465         if (cs.unusable)
4466                 return false;
4467         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4468                 return false;
4469         if (!cs.s)
4470                 return false;
4471         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4472                 if (cs.dpl > cs_rpl)
4473                         return false;
4474         } else {
4475                 if (cs.dpl != cs_rpl)
4476                         return false;
4477         }
4478         if (!cs.present)
4479                 return false;
4480
4481         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4482         return true;
4483 }
4484
4485 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4486 {
4487         struct kvm_segment ss;
4488         unsigned int ss_rpl;
4489
4490         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4491         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4492
4493         if (ss.unusable)
4494                 return true;
4495         if (ss.type != 3 && ss.type != 7)
4496                 return false;
4497         if (!ss.s)
4498                 return false;
4499         if (ss.dpl != ss_rpl) /* DPL != RPL */
4500                 return false;
4501         if (!ss.present)
4502                 return false;
4503
4504         return true;
4505 }
4506
4507 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4508 {
4509         struct kvm_segment var;
4510         unsigned int rpl;
4511
4512         vmx_get_segment(vcpu, &var, seg);
4513         rpl = var.selector & SEGMENT_RPL_MASK;
4514
4515         if (var.unusable)
4516                 return true;
4517         if (!var.s)
4518                 return false;
4519         if (!var.present)
4520                 return false;
4521         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4522                 if (var.dpl < rpl) /* DPL < RPL */
4523                         return false;
4524         }
4525
4526         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4527          * rights flags
4528          */
4529         return true;
4530 }
4531
4532 static bool tr_valid(struct kvm_vcpu *vcpu)
4533 {
4534         struct kvm_segment tr;
4535
4536         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4537
4538         if (tr.unusable)
4539                 return false;
4540         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4541                 return false;
4542         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4543                 return false;
4544         if (!tr.present)
4545                 return false;
4546
4547         return true;
4548 }
4549
4550 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4551 {
4552         struct kvm_segment ldtr;
4553
4554         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4555
4556         if (ldtr.unusable)
4557                 return true;
4558         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4559                 return false;
4560         if (ldtr.type != 2)
4561                 return false;
4562         if (!ldtr.present)
4563                 return false;
4564
4565         return true;
4566 }
4567
4568 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4569 {
4570         struct kvm_segment cs, ss;
4571
4572         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4573         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4574
4575         return ((cs.selector & SEGMENT_RPL_MASK) ==
4576                  (ss.selector & SEGMENT_RPL_MASK));
4577 }
4578
4579 /*
4580  * Check if guest state is valid. Returns true if valid, false if
4581  * not.
4582  * We assume that registers are always usable
4583  */
4584 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4585 {
4586         if (enable_unrestricted_guest)
4587                 return true;
4588
4589         /* real mode guest state checks */
4590         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4591                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4592                         return false;
4593                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4594                         return false;
4595                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4596                         return false;
4597                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4598                         return false;
4599                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4600                         return false;
4601                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4602                         return false;
4603         } else {
4604         /* protected mode guest state checks */
4605                 if (!cs_ss_rpl_check(vcpu))
4606                         return false;
4607                 if (!code_segment_valid(vcpu))
4608                         return false;
4609                 if (!stack_segment_valid(vcpu))
4610                         return false;
4611                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4612                         return false;
4613                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4614                         return false;
4615                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4616                         return false;
4617                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4618                         return false;
4619                 if (!tr_valid(vcpu))
4620                         return false;
4621                 if (!ldtr_valid(vcpu))
4622                         return false;
4623         }
4624         /* TODO:
4625          * - Add checks on RIP
4626          * - Add checks on RFLAGS
4627          */
4628
4629         return true;
4630 }
4631
4632 static int init_rmode_tss(struct kvm *kvm)
4633 {
4634         gfn_t fn;
4635         u16 data = 0;
4636         int idx, r;
4637
4638         idx = srcu_read_lock(&kvm->srcu);
4639         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4640         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4641         if (r < 0)
4642                 goto out;
4643         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4644         r = kvm_write_guest_page(kvm, fn++, &data,
4645                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4646         if (r < 0)
4647                 goto out;
4648         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4649         if (r < 0)
4650                 goto out;
4651         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4652         if (r < 0)
4653                 goto out;
4654         data = ~0;
4655         r = kvm_write_guest_page(kvm, fn, &data,
4656                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4657                                  sizeof(u8));
4658 out:
4659         srcu_read_unlock(&kvm->srcu, idx);
4660         return r;
4661 }
4662
4663 static int init_rmode_identity_map(struct kvm *kvm)
4664 {
4665         int i, idx, r = 0;
4666         kvm_pfn_t identity_map_pfn;
4667         u32 tmp;
4668
4669         if (!enable_ept)
4670                 return 0;
4671
4672         /* Protect kvm->arch.ept_identity_pagetable_done. */
4673         mutex_lock(&kvm->slots_lock);
4674
4675         if (likely(kvm->arch.ept_identity_pagetable_done))
4676                 goto out2;
4677
4678         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4679
4680         r = alloc_identity_pagetable(kvm);
4681         if (r < 0)
4682                 goto out2;
4683
4684         idx = srcu_read_lock(&kvm->srcu);
4685         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4686         if (r < 0)
4687                 goto out;
4688         /* Set up identity-mapping pagetable for EPT in real mode */
4689         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4690                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4691                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4692                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4693                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4694                 if (r < 0)
4695                         goto out;
4696         }
4697         kvm->arch.ept_identity_pagetable_done = true;
4698
4699 out:
4700         srcu_read_unlock(&kvm->srcu, idx);
4701
4702 out2:
4703         mutex_unlock(&kvm->slots_lock);
4704         return r;
4705 }
4706
4707 static void seg_setup(int seg)
4708 {
4709         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4710         unsigned int ar;
4711
4712         vmcs_write16(sf->selector, 0);
4713         vmcs_writel(sf->base, 0);
4714         vmcs_write32(sf->limit, 0xffff);
4715         ar = 0x93;
4716         if (seg == VCPU_SREG_CS)
4717                 ar |= 0x08; /* code segment */
4718
4719         vmcs_write32(sf->ar_bytes, ar);
4720 }
4721
4722 static int alloc_apic_access_page(struct kvm *kvm)
4723 {
4724         struct page *page;
4725         int r = 0;
4726
4727         mutex_lock(&kvm->slots_lock);
4728         if (kvm->arch.apic_access_page_done)
4729                 goto out;
4730         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4731                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4732         if (r)
4733                 goto out;
4734
4735         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4736         if (is_error_page(page)) {
4737                 r = -EFAULT;
4738                 goto out;
4739         }
4740
4741         /*
4742          * Do not pin the page in memory, so that memory hot-unplug
4743          * is able to migrate it.
4744          */
4745         put_page(page);
4746         kvm->arch.apic_access_page_done = true;
4747 out:
4748         mutex_unlock(&kvm->slots_lock);
4749         return r;
4750 }
4751
4752 static int alloc_identity_pagetable(struct kvm *kvm)
4753 {
4754         /* Called with kvm->slots_lock held. */
4755
4756         int r = 0;
4757
4758         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4759
4760         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4761                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4762
4763         return r;
4764 }
4765
4766 static int allocate_vpid(void)
4767 {
4768         int vpid;
4769
4770         if (!enable_vpid)
4771                 return 0;
4772         spin_lock(&vmx_vpid_lock);
4773         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4774         if (vpid < VMX_NR_VPIDS)
4775                 __set_bit(vpid, vmx_vpid_bitmap);
4776         else
4777                 vpid = 0;
4778         spin_unlock(&vmx_vpid_lock);
4779         return vpid;
4780 }
4781
4782 static void free_vpid(int vpid)
4783 {
4784         if (!enable_vpid || vpid == 0)
4785                 return;
4786         spin_lock(&vmx_vpid_lock);
4787         __clear_bit(vpid, vmx_vpid_bitmap);
4788         spin_unlock(&vmx_vpid_lock);
4789 }
4790
4791 #define MSR_TYPE_R      1
4792 #define MSR_TYPE_W      2
4793 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4794                                                 u32 msr, int type)
4795 {
4796         int f = sizeof(unsigned long);
4797
4798         if (!cpu_has_vmx_msr_bitmap())
4799                 return;
4800
4801         /*
4802          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4803          * have the write-low and read-high bitmap offsets the wrong way round.
4804          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4805          */
4806         if (msr <= 0x1fff) {
4807                 if (type & MSR_TYPE_R)
4808                         /* read-low */
4809                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4810
4811                 if (type & MSR_TYPE_W)
4812                         /* write-low */
4813                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4814
4815         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4816                 msr &= 0x1fff;
4817                 if (type & MSR_TYPE_R)
4818                         /* read-high */
4819                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4820
4821                 if (type & MSR_TYPE_W)
4822                         /* write-high */
4823                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4824
4825         }
4826 }
4827
4828 /*
4829  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4830  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4831  */
4832 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4833                                                unsigned long *msr_bitmap_nested,
4834                                                u32 msr, int type)
4835 {
4836         int f = sizeof(unsigned long);
4837
4838         if (!cpu_has_vmx_msr_bitmap()) {
4839                 WARN_ON(1);
4840                 return;
4841         }
4842
4843         /*
4844          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4845          * have the write-low and read-high bitmap offsets the wrong way round.
4846          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4847          */
4848         if (msr <= 0x1fff) {
4849                 if (type & MSR_TYPE_R &&
4850                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4851                         /* read-low */
4852                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4853
4854                 if (type & MSR_TYPE_W &&
4855                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4856                         /* write-low */
4857                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4858
4859         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4860                 msr &= 0x1fff;
4861                 if (type & MSR_TYPE_R &&
4862                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4863                         /* read-high */
4864                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4865
4866                 if (type & MSR_TYPE_W &&
4867                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4868                         /* write-high */
4869                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4870
4871         }
4872 }
4873
4874 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4875 {
4876         if (!longmode_only)
4877                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4878                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4879         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4880                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4881 }
4882
4883 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4884 {
4885         if (apicv_active) {
4886                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4887                                 msr, type);
4888                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4889                                 msr, type);
4890         } else {
4891                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4892                                 msr, type);
4893                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4894                                 msr, type);
4895         }
4896 }
4897
4898 static bool vmx_get_enable_apicv(void)
4899 {
4900         return enable_apicv;
4901 }
4902
4903 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4904 {
4905         struct vcpu_vmx *vmx = to_vmx(vcpu);
4906         int max_irr;
4907         void *vapic_page;
4908         u16 status;
4909
4910         if (vmx->nested.pi_desc &&
4911             vmx->nested.pi_pending) {
4912                 vmx->nested.pi_pending = false;
4913                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4914                         return;
4915
4916                 max_irr = find_last_bit(
4917                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4918
4919                 if (max_irr == 256)
4920                         return;
4921
4922                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4923                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4924                 kunmap(vmx->nested.virtual_apic_page);
4925
4926                 status = vmcs_read16(GUEST_INTR_STATUS);
4927                 if ((u8)max_irr > ((u8)status & 0xff)) {
4928                         status &= ~0xff;
4929                         status |= (u8)max_irr;
4930                         vmcs_write16(GUEST_INTR_STATUS, status);
4931                 }
4932         }
4933 }
4934
4935 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4936 {
4937 #ifdef CONFIG_SMP
4938         if (vcpu->mode == IN_GUEST_MODE) {
4939                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4940
4941                 /*
4942                  * Currently, we don't support urgent interrupt,
4943                  * all interrupts are recognized as non-urgent
4944                  * interrupt, so we cannot post interrupts when
4945                  * 'SN' is set.
4946                  *
4947                  * If the vcpu is in guest mode, it means it is
4948                  * running instead of being scheduled out and
4949                  * waiting in the run queue, and that's the only
4950                  * case when 'SN' is set currently, warning if
4951                  * 'SN' is set.
4952                  */
4953                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4954
4955                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4956                                 POSTED_INTR_VECTOR);
4957                 return true;
4958         }
4959 #endif
4960         return false;
4961 }
4962
4963 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4964                                                 int vector)
4965 {
4966         struct vcpu_vmx *vmx = to_vmx(vcpu);
4967
4968         if (is_guest_mode(vcpu) &&
4969             vector == vmx->nested.posted_intr_nv) {
4970                 /* the PIR and ON have been set by L1. */
4971                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4972                 /*
4973                  * If a posted intr is not recognized by hardware,
4974                  * we will accomplish it in the next vmentry.
4975                  */
4976                 vmx->nested.pi_pending = true;
4977                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4978                 return 0;
4979         }
4980         return -1;
4981 }
4982 /*
4983  * Send interrupt to vcpu via posted interrupt way.
4984  * 1. If target vcpu is running(non-root mode), send posted interrupt
4985  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4986  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4987  * interrupt from PIR in next vmentry.
4988  */
4989 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4990 {
4991         struct vcpu_vmx *vmx = to_vmx(vcpu);
4992         int r;
4993
4994         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4995         if (!r)
4996                 return;
4997
4998         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4999                 return;
5000
5001         /* If a previous notification has sent the IPI, nothing to do.  */
5002         if (pi_test_and_set_on(&vmx->pi_desc))
5003                 return;
5004
5005         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5006                 kvm_vcpu_kick(vcpu);
5007 }
5008
5009 /*
5010  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5011  * will not change in the lifetime of the guest.
5012  * Note that host-state that does change is set elsewhere. E.g., host-state
5013  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5014  */
5015 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5016 {
5017         u32 low32, high32;
5018         unsigned long tmpl;
5019         struct desc_ptr dt;
5020         unsigned long cr0, cr4;
5021
5022         cr0 = read_cr0();
5023         WARN_ON(cr0 & X86_CR0_TS);
5024         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5025         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
5026
5027         /* Save the most likely value for this task's CR4 in the VMCS. */
5028         cr4 = cr4_read_shadow();
5029         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5030         vmx->host_state.vmcs_host_cr4 = cr4;
5031
5032         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5033 #ifdef CONFIG_X86_64
5034         /*
5035          * Load null selectors, so we can avoid reloading them in
5036          * __vmx_load_host_state(), in case userspace uses the null selectors
5037          * too (the expected case).
5038          */
5039         vmcs_write16(HOST_DS_SELECTOR, 0);
5040         vmcs_write16(HOST_ES_SELECTOR, 0);
5041 #else
5042         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5043         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5044 #endif
5045         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5046         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5047
5048         native_store_idt(&dt);
5049         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5050         vmx->host_idt_base = dt.address;
5051
5052         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5053
5054         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5055         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5056         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5057         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5058
5059         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5060                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5061                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5062         }
5063 }
5064
5065 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5066 {
5067         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5068         if (enable_ept)
5069                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5070         if (is_guest_mode(&vmx->vcpu))
5071                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5072                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5073         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5074 }
5075
5076 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5077 {
5078         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5079
5080         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5081                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5082         /* Enable the preemption timer dynamically */
5083         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5084         return pin_based_exec_ctrl;
5085 }
5086
5087 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5088 {
5089         struct vcpu_vmx *vmx = to_vmx(vcpu);
5090
5091         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5092         if (cpu_has_secondary_exec_ctrls()) {
5093                 if (kvm_vcpu_apicv_active(vcpu))
5094                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5095                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5096                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5097                 else
5098                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5099                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5100                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5101         }
5102
5103         if (cpu_has_vmx_msr_bitmap())
5104                 vmx_set_msr_bitmap(vcpu);
5105 }
5106
5107 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5108 {
5109         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5110
5111         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5112                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5113
5114         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5115                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5116 #ifdef CONFIG_X86_64
5117                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5118                                 CPU_BASED_CR8_LOAD_EXITING;
5119 #endif
5120         }
5121         if (!enable_ept)
5122                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5123                                 CPU_BASED_CR3_LOAD_EXITING  |
5124                                 CPU_BASED_INVLPG_EXITING;
5125         return exec_control;
5126 }
5127
5128 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5129 {
5130         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5131         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5132                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5133         if (vmx->vpid == 0)
5134                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5135         if (!enable_ept) {
5136                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5137                 enable_unrestricted_guest = 0;
5138                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5139                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5140         }
5141         if (!enable_unrestricted_guest)
5142                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5143         if (!ple_gap)
5144                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5145         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5146                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5147                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5148         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5149         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5150            (handle_vmptrld).
5151            We can NOT enable shadow_vmcs here because we don't have yet
5152            a current VMCS12
5153         */
5154         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5155
5156         if (!enable_pml)
5157                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5158
5159         return exec_control;
5160 }
5161
5162 static void ept_set_mmio_spte_mask(void)
5163 {
5164         /*
5165          * EPT Misconfigurations can be generated if the value of bits 2:0
5166          * of an EPT paging-structure entry is 110b (write/execute).
5167          */
5168         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5169 }
5170
5171 #define VMX_XSS_EXIT_BITMAP 0
5172 /*
5173  * Sets up the vmcs for emulated real mode.
5174  */
5175 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5176 {
5177 #ifdef CONFIG_X86_64
5178         unsigned long a;
5179 #endif
5180         int i;
5181
5182         /* I/O */
5183         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5184         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5185
5186         if (enable_shadow_vmcs) {
5187                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5188                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5189         }
5190         if (cpu_has_vmx_msr_bitmap())
5191                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5192
5193         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5194
5195         /* Control */
5196         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5197         vmx->hv_deadline_tsc = -1;
5198
5199         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5200
5201         if (cpu_has_secondary_exec_ctrls()) {
5202                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5203                                 vmx_secondary_exec_control(vmx));
5204         }
5205
5206         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5207                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5208                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5209                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5210                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5211
5212                 vmcs_write16(GUEST_INTR_STATUS, 0);
5213
5214                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5215                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5216         }
5217
5218         if (ple_gap) {
5219                 vmcs_write32(PLE_GAP, ple_gap);
5220                 vmx->ple_window = ple_window;
5221                 vmx->ple_window_dirty = true;
5222         }
5223
5224         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5225         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5226         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5227
5228         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5229         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5230         vmx_set_constant_host_state(vmx);
5231 #ifdef CONFIG_X86_64
5232         rdmsrl(MSR_FS_BASE, a);
5233         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5234         rdmsrl(MSR_GS_BASE, a);
5235         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5236 #else
5237         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5238         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5239 #endif
5240
5241         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5242         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5243         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5244         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5245         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5246
5247         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5248                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5249
5250         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5251                 u32 index = vmx_msr_index[i];
5252                 u32 data_low, data_high;
5253                 int j = vmx->nmsrs;
5254
5255                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5256                         continue;
5257                 if (wrmsr_safe(index, data_low, data_high) < 0)
5258                         continue;
5259                 vmx->guest_msrs[j].index = i;
5260                 vmx->guest_msrs[j].data = 0;
5261                 vmx->guest_msrs[j].mask = -1ull;
5262                 ++vmx->nmsrs;
5263         }
5264
5265
5266         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5267
5268         /* 22.2.1, 20.8.1 */
5269         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5270
5271         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5272         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5273
5274         set_cr4_guest_host_mask(vmx);
5275
5276         if (vmx_xsaves_supported())
5277                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5278
5279         if (enable_pml) {
5280                 ASSERT(vmx->pml_pg);
5281                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5282                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5283         }
5284
5285         return 0;
5286 }
5287
5288 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5289 {
5290         struct vcpu_vmx *vmx = to_vmx(vcpu);
5291         struct msr_data apic_base_msr;
5292         u64 cr0;
5293
5294         vmx->rmode.vm86_active = 0;
5295
5296         vmx->soft_vnmi_blocked = 0;
5297
5298         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5299         kvm_set_cr8(vcpu, 0);
5300
5301         if (!init_event) {
5302                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5303                                      MSR_IA32_APICBASE_ENABLE;
5304                 if (kvm_vcpu_is_reset_bsp(vcpu))
5305                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5306                 apic_base_msr.host_initiated = true;
5307                 kvm_set_apic_base(vcpu, &apic_base_msr);
5308         }
5309
5310         vmx_segment_cache_clear(vmx);
5311
5312         seg_setup(VCPU_SREG_CS);
5313         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5314         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5315
5316         seg_setup(VCPU_SREG_DS);
5317         seg_setup(VCPU_SREG_ES);
5318         seg_setup(VCPU_SREG_FS);
5319         seg_setup(VCPU_SREG_GS);
5320         seg_setup(VCPU_SREG_SS);
5321
5322         vmcs_write16(GUEST_TR_SELECTOR, 0);
5323         vmcs_writel(GUEST_TR_BASE, 0);
5324         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5325         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5326
5327         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5328         vmcs_writel(GUEST_LDTR_BASE, 0);
5329         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5330         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5331
5332         if (!init_event) {
5333                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5334                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5335                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5336                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5337         }
5338
5339         vmcs_writel(GUEST_RFLAGS, 0x02);
5340         kvm_rip_write(vcpu, 0xfff0);
5341
5342         vmcs_writel(GUEST_GDTR_BASE, 0);
5343         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5344
5345         vmcs_writel(GUEST_IDTR_BASE, 0);
5346         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5347
5348         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5349         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5350         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5351
5352         setup_msrs(vmx);
5353
5354         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5355
5356         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5357                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5358                 if (cpu_need_tpr_shadow(vcpu))
5359                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5360                                      __pa(vcpu->arch.apic->regs));
5361                 vmcs_write32(TPR_THRESHOLD, 0);
5362         }
5363
5364         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5365
5366         if (kvm_vcpu_apicv_active(vcpu))
5367                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5368
5369         if (vmx->vpid != 0)
5370                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5371
5372         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5373         vmx->vcpu.arch.cr0 = cr0;
5374         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5375         vmx_set_cr4(vcpu, 0);
5376         vmx_set_efer(vcpu, 0);
5377
5378         update_exception_bitmap(vcpu);
5379
5380         vpid_sync_context(vmx->vpid);
5381 }
5382
5383 /*
5384  * In nested virtualization, check if L1 asked to exit on external interrupts.
5385  * For most existing hypervisors, this will always return true.
5386  */
5387 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5388 {
5389         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5390                 PIN_BASED_EXT_INTR_MASK;
5391 }
5392
5393 /*
5394  * In nested virtualization, check if L1 has set
5395  * VM_EXIT_ACK_INTR_ON_EXIT
5396  */
5397 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5398 {
5399         return get_vmcs12(vcpu)->vm_exit_controls &
5400                 VM_EXIT_ACK_INTR_ON_EXIT;
5401 }
5402
5403 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5404 {
5405         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5406                 PIN_BASED_NMI_EXITING;
5407 }
5408
5409 static void enable_irq_window(struct kvm_vcpu *vcpu)
5410 {
5411         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5412                       CPU_BASED_VIRTUAL_INTR_PENDING);
5413 }
5414
5415 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5416 {
5417         if (!cpu_has_virtual_nmis() ||
5418             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5419                 enable_irq_window(vcpu);
5420                 return;
5421         }
5422
5423         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5424                       CPU_BASED_VIRTUAL_NMI_PENDING);
5425 }
5426
5427 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5428 {
5429         struct vcpu_vmx *vmx = to_vmx(vcpu);
5430         uint32_t intr;
5431         int irq = vcpu->arch.interrupt.nr;
5432
5433         trace_kvm_inj_virq(irq);
5434
5435         ++vcpu->stat.irq_injections;
5436         if (vmx->rmode.vm86_active) {
5437                 int inc_eip = 0;
5438                 if (vcpu->arch.interrupt.soft)
5439                         inc_eip = vcpu->arch.event_exit_inst_len;
5440                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5441                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5442                 return;
5443         }
5444         intr = irq | INTR_INFO_VALID_MASK;
5445         if (vcpu->arch.interrupt.soft) {
5446                 intr |= INTR_TYPE_SOFT_INTR;
5447                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5448                              vmx->vcpu.arch.event_exit_inst_len);
5449         } else
5450                 intr |= INTR_TYPE_EXT_INTR;
5451         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5452 }
5453
5454 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5455 {
5456         struct vcpu_vmx *vmx = to_vmx(vcpu);
5457
5458         if (!is_guest_mode(vcpu)) {
5459                 if (!cpu_has_virtual_nmis()) {
5460                         /*
5461                          * Tracking the NMI-blocked state in software is built upon
5462                          * finding the next open IRQ window. This, in turn, depends on
5463                          * well-behaving guests: They have to keep IRQs disabled at
5464                          * least as long as the NMI handler runs. Otherwise we may
5465                          * cause NMI nesting, maybe breaking the guest. But as this is
5466                          * highly unlikely, we can live with the residual risk.
5467                          */
5468                         vmx->soft_vnmi_blocked = 1;
5469                         vmx->vnmi_blocked_time = 0;
5470                 }
5471
5472                 ++vcpu->stat.nmi_injections;
5473                 vmx->nmi_known_unmasked = false;
5474         }
5475
5476         if (vmx->rmode.vm86_active) {
5477                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5478                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5479                 return;
5480         }
5481
5482         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5483                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5484 }
5485
5486 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5487 {
5488         if (!cpu_has_virtual_nmis())
5489                 return to_vmx(vcpu)->soft_vnmi_blocked;
5490         if (to_vmx(vcpu)->nmi_known_unmasked)
5491                 return false;
5492         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5493 }
5494
5495 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5496 {
5497         struct vcpu_vmx *vmx = to_vmx(vcpu);
5498
5499         if (!cpu_has_virtual_nmis()) {
5500                 if (vmx->soft_vnmi_blocked != masked) {
5501                         vmx->soft_vnmi_blocked = masked;
5502                         vmx->vnmi_blocked_time = 0;
5503                 }
5504         } else {
5505                 vmx->nmi_known_unmasked = !masked;
5506                 if (masked)
5507                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5508                                       GUEST_INTR_STATE_NMI);
5509                 else
5510                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5511                                         GUEST_INTR_STATE_NMI);
5512         }
5513 }
5514
5515 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5516 {
5517         if (to_vmx(vcpu)->nested.nested_run_pending)
5518                 return 0;
5519
5520         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5521                 return 0;
5522
5523         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5524                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5525                    | GUEST_INTR_STATE_NMI));
5526 }
5527
5528 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5529 {
5530         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5531                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5532                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5533                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5534 }
5535
5536 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5537 {
5538         int ret;
5539
5540         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5541                                     PAGE_SIZE * 3);
5542         if (ret)
5543                 return ret;
5544         kvm->arch.tss_addr = addr;
5545         return init_rmode_tss(kvm);
5546 }
5547
5548 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5549 {
5550         switch (vec) {
5551         case BP_VECTOR:
5552                 /*
5553                  * Update instruction length as we may reinject the exception
5554                  * from user space while in guest debugging mode.
5555                  */
5556                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5557                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5558                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5559                         return false;
5560                 /* fall through */
5561         case DB_VECTOR:
5562                 if (vcpu->guest_debug &
5563                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5564                         return false;
5565                 /* fall through */
5566         case DE_VECTOR:
5567         case OF_VECTOR:
5568         case BR_VECTOR:
5569         case UD_VECTOR:
5570         case DF_VECTOR:
5571         case SS_VECTOR:
5572         case GP_VECTOR:
5573         case MF_VECTOR:
5574                 return true;
5575         break;
5576         }
5577         return false;
5578 }
5579
5580 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5581                                   int vec, u32 err_code)
5582 {
5583         /*
5584          * Instruction with address size override prefix opcode 0x67
5585          * Cause the #SS fault with 0 error code in VM86 mode.
5586          */
5587         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5588                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5589                         if (vcpu->arch.halt_request) {
5590                                 vcpu->arch.halt_request = 0;
5591                                 return kvm_vcpu_halt(vcpu);
5592                         }
5593                         return 1;
5594                 }
5595                 return 0;
5596         }
5597
5598         /*
5599          * Forward all other exceptions that are valid in real mode.
5600          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5601          *        the required debugging infrastructure rework.
5602          */
5603         kvm_queue_exception(vcpu, vec);
5604         return 1;
5605 }
5606
5607 /*
5608  * Trigger machine check on the host. We assume all the MSRs are already set up
5609  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5610  * We pass a fake environment to the machine check handler because we want
5611  * the guest to be always treated like user space, no matter what context
5612  * it used internally.
5613  */
5614 static void kvm_machine_check(void)
5615 {
5616 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5617         struct pt_regs regs = {
5618                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5619                 .flags = X86_EFLAGS_IF,
5620         };
5621
5622         do_machine_check(&regs, 0);
5623 #endif
5624 }
5625
5626 static int handle_machine_check(struct kvm_vcpu *vcpu)
5627 {
5628         /* already handled by vcpu_run */
5629         return 1;
5630 }
5631
5632 static int handle_exception(struct kvm_vcpu *vcpu)
5633 {
5634         struct vcpu_vmx *vmx = to_vmx(vcpu);
5635         struct kvm_run *kvm_run = vcpu->run;
5636         u32 intr_info, ex_no, error_code;
5637         unsigned long cr2, rip, dr6;
5638         u32 vect_info;
5639         enum emulation_result er;
5640
5641         vect_info = vmx->idt_vectoring_info;
5642         intr_info = vmx->exit_intr_info;
5643
5644         if (is_machine_check(intr_info))
5645                 return handle_machine_check(vcpu);
5646
5647         if (is_nmi(intr_info))
5648                 return 1;  /* already handled by vmx_vcpu_run() */
5649
5650         if (is_invalid_opcode(intr_info)) {
5651                 if (is_guest_mode(vcpu)) {
5652                         kvm_queue_exception(vcpu, UD_VECTOR);
5653                         return 1;
5654                 }
5655                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5656                 if (er != EMULATE_DONE)
5657                         kvm_queue_exception(vcpu, UD_VECTOR);
5658                 return 1;
5659         }
5660
5661         error_code = 0;
5662         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5663                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5664
5665         /*
5666          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5667          * MMIO, it is better to report an internal error.
5668          * See the comments in vmx_handle_exit.
5669          */
5670         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5671             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5672                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5673                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5674                 vcpu->run->internal.ndata = 3;
5675                 vcpu->run->internal.data[0] = vect_info;
5676                 vcpu->run->internal.data[1] = intr_info;
5677                 vcpu->run->internal.data[2] = error_code;
5678                 return 0;
5679         }
5680
5681         if (is_page_fault(intr_info)) {
5682                 /* EPT won't cause page fault directly */
5683                 BUG_ON(enable_ept);
5684                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5685                 trace_kvm_page_fault(cr2, error_code);
5686
5687                 if (kvm_event_needs_reinjection(vcpu))
5688                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5689                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5690         }
5691
5692         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5693
5694         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5695                 return handle_rmode_exception(vcpu, ex_no, error_code);
5696
5697         switch (ex_no) {
5698         case AC_VECTOR:
5699                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5700                 return 1;
5701         case DB_VECTOR:
5702                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5703                 if (!(vcpu->guest_debug &
5704                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5705                         vcpu->arch.dr6 &= ~15;
5706                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5707                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5708                                 skip_emulated_instruction(vcpu);
5709
5710                         kvm_queue_exception(vcpu, DB_VECTOR);
5711                         return 1;
5712                 }
5713                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5714                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5715                 /* fall through */
5716         case BP_VECTOR:
5717                 /*
5718                  * Update instruction length as we may reinject #BP from
5719                  * user space while in guest debugging mode. Reading it for
5720                  * #DB as well causes no harm, it is not used in that case.
5721                  */
5722                 vmx->vcpu.arch.event_exit_inst_len =
5723                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5724                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5725                 rip = kvm_rip_read(vcpu);
5726                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5727                 kvm_run->debug.arch.exception = ex_no;
5728                 break;
5729         default:
5730                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5731                 kvm_run->ex.exception = ex_no;
5732                 kvm_run->ex.error_code = error_code;
5733                 break;
5734         }
5735         return 0;
5736 }
5737
5738 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5739 {
5740         ++vcpu->stat.irq_exits;
5741         return 1;
5742 }
5743
5744 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5745 {
5746         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5747         return 0;
5748 }
5749
5750 static int handle_io(struct kvm_vcpu *vcpu)
5751 {
5752         unsigned long exit_qualification;
5753         int size, in, string, ret;
5754         unsigned port;
5755
5756         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5757         string = (exit_qualification & 16) != 0;
5758         in = (exit_qualification & 8) != 0;
5759
5760         ++vcpu->stat.io_exits;
5761
5762         if (string || in)
5763                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5764
5765         port = exit_qualification >> 16;
5766         size = (exit_qualification & 7) + 1;
5767
5768         ret = kvm_skip_emulated_instruction(vcpu);
5769
5770         /*
5771          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5772          * KVM_EXIT_DEBUG here.
5773          */
5774         return kvm_fast_pio_out(vcpu, size, port) && ret;
5775 }
5776
5777 static void
5778 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5779 {
5780         /*
5781          * Patch in the VMCALL instruction:
5782          */
5783         hypercall[0] = 0x0f;
5784         hypercall[1] = 0x01;
5785         hypercall[2] = 0xc1;
5786 }
5787
5788 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5789 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5790 {
5791         if (is_guest_mode(vcpu)) {
5792                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5793                 unsigned long orig_val = val;
5794
5795                 /*
5796                  * We get here when L2 changed cr0 in a way that did not change
5797                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5798                  * but did change L0 shadowed bits. So we first calculate the
5799                  * effective cr0 value that L1 would like to write into the
5800                  * hardware. It consists of the L2-owned bits from the new
5801                  * value combined with the L1-owned bits from L1's guest_cr0.
5802                  */
5803                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5804                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5805
5806                 if (!nested_guest_cr0_valid(vcpu, val))
5807                         return 1;
5808
5809                 if (kvm_set_cr0(vcpu, val))
5810                         return 1;
5811                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5812                 return 0;
5813         } else {
5814                 if (to_vmx(vcpu)->nested.vmxon &&
5815                     !nested_host_cr0_valid(vcpu, val))
5816                         return 1;
5817
5818                 return kvm_set_cr0(vcpu, val);
5819         }
5820 }
5821
5822 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5823 {
5824         if (is_guest_mode(vcpu)) {
5825                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5826                 unsigned long orig_val = val;
5827
5828                 /* analogously to handle_set_cr0 */
5829                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5830                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5831                 if (kvm_set_cr4(vcpu, val))
5832                         return 1;
5833                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5834                 return 0;
5835         } else
5836                 return kvm_set_cr4(vcpu, val);
5837 }
5838
5839 static int handle_cr(struct kvm_vcpu *vcpu)
5840 {
5841         unsigned long exit_qualification, val;
5842         int cr;
5843         int reg;
5844         int err;
5845         int ret;
5846
5847         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5848         cr = exit_qualification & 15;
5849         reg = (exit_qualification >> 8) & 15;
5850         switch ((exit_qualification >> 4) & 3) {
5851         case 0: /* mov to cr */
5852                 val = kvm_register_readl(vcpu, reg);
5853                 trace_kvm_cr_write(cr, val);
5854                 switch (cr) {
5855                 case 0:
5856                         err = handle_set_cr0(vcpu, val);
5857                         return kvm_complete_insn_gp(vcpu, err);
5858                 case 3:
5859                         err = kvm_set_cr3(vcpu, val);
5860                         return kvm_complete_insn_gp(vcpu, err);
5861                 case 4:
5862                         err = handle_set_cr4(vcpu, val);
5863                         return kvm_complete_insn_gp(vcpu, err);
5864                 case 8: {
5865                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5866                                 u8 cr8 = (u8)val;
5867                                 err = kvm_set_cr8(vcpu, cr8);
5868                                 ret = kvm_complete_insn_gp(vcpu, err);
5869                                 if (lapic_in_kernel(vcpu))
5870                                         return ret;
5871                                 if (cr8_prev <= cr8)
5872                                         return ret;
5873                                 /*
5874                                  * TODO: we might be squashing a
5875                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5876                                  * KVM_EXIT_DEBUG here.
5877                                  */
5878                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5879                                 return 0;
5880                         }
5881                 }
5882                 break;
5883         case 2: /* clts */
5884                 WARN_ONCE(1, "Guest should always own CR0.TS");
5885                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5886                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5887                 return kvm_skip_emulated_instruction(vcpu);
5888         case 1: /*mov from cr*/
5889                 switch (cr) {
5890                 case 3:
5891                         val = kvm_read_cr3(vcpu);
5892                         kvm_register_write(vcpu, reg, val);
5893                         trace_kvm_cr_read(cr, val);
5894                         return kvm_skip_emulated_instruction(vcpu);
5895                 case 8:
5896                         val = kvm_get_cr8(vcpu);
5897                         kvm_register_write(vcpu, reg, val);
5898                         trace_kvm_cr_read(cr, val);
5899                         return kvm_skip_emulated_instruction(vcpu);
5900                 }
5901                 break;
5902         case 3: /* lmsw */
5903                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5904                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5905                 kvm_lmsw(vcpu, val);
5906
5907                 return kvm_skip_emulated_instruction(vcpu);
5908         default:
5909                 break;
5910         }
5911         vcpu->run->exit_reason = 0;
5912         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5913                (int)(exit_qualification >> 4) & 3, cr);
5914         return 0;
5915 }
5916
5917 static int handle_dr(struct kvm_vcpu *vcpu)
5918 {
5919         unsigned long exit_qualification;
5920         int dr, dr7, reg;
5921
5922         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5923         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5924
5925         /* First, if DR does not exist, trigger UD */
5926         if (!kvm_require_dr(vcpu, dr))
5927                 return 1;
5928
5929         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5930         if (!kvm_require_cpl(vcpu, 0))
5931                 return 1;
5932         dr7 = vmcs_readl(GUEST_DR7);
5933         if (dr7 & DR7_GD) {
5934                 /*
5935                  * As the vm-exit takes precedence over the debug trap, we
5936                  * need to emulate the latter, either for the host or the
5937                  * guest debugging itself.
5938                  */
5939                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5940                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5941                         vcpu->run->debug.arch.dr7 = dr7;
5942                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5943                         vcpu->run->debug.arch.exception = DB_VECTOR;
5944                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5945                         return 0;
5946                 } else {
5947                         vcpu->arch.dr6 &= ~15;
5948                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5949                         kvm_queue_exception(vcpu, DB_VECTOR);
5950                         return 1;
5951                 }
5952         }
5953
5954         if (vcpu->guest_debug == 0) {
5955                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5956                                 CPU_BASED_MOV_DR_EXITING);
5957
5958                 /*
5959                  * No more DR vmexits; force a reload of the debug registers
5960                  * and reenter on this instruction.  The next vmexit will
5961                  * retrieve the full state of the debug registers.
5962                  */
5963                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5964                 return 1;
5965         }
5966
5967         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5968         if (exit_qualification & TYPE_MOV_FROM_DR) {
5969                 unsigned long val;
5970
5971                 if (kvm_get_dr(vcpu, dr, &val))
5972                         return 1;
5973                 kvm_register_write(vcpu, reg, val);
5974         } else
5975                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5976                         return 1;
5977
5978         return kvm_skip_emulated_instruction(vcpu);
5979 }
5980
5981 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5982 {
5983         return vcpu->arch.dr6;
5984 }
5985
5986 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5987 {
5988 }
5989
5990 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5991 {
5992         get_debugreg(vcpu->arch.db[0], 0);
5993         get_debugreg(vcpu->arch.db[1], 1);
5994         get_debugreg(vcpu->arch.db[2], 2);
5995         get_debugreg(vcpu->arch.db[3], 3);
5996         get_debugreg(vcpu->arch.dr6, 6);
5997         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5998
5999         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6000         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6001 }
6002
6003 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6004 {
6005         vmcs_writel(GUEST_DR7, val);
6006 }
6007
6008 static int handle_cpuid(struct kvm_vcpu *vcpu)
6009 {
6010         return kvm_emulate_cpuid(vcpu);
6011 }
6012
6013 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6014 {
6015         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6016         struct msr_data msr_info;
6017
6018         msr_info.index = ecx;
6019         msr_info.host_initiated = false;
6020         if (vmx_get_msr(vcpu, &msr_info)) {
6021                 trace_kvm_msr_read_ex(ecx);
6022                 kvm_inject_gp(vcpu, 0);
6023                 return 1;
6024         }
6025
6026         trace_kvm_msr_read(ecx, msr_info.data);
6027
6028         /* FIXME: handling of bits 32:63 of rax, rdx */
6029         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6030         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6031         return kvm_skip_emulated_instruction(vcpu);
6032 }
6033
6034 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6035 {
6036         struct msr_data msr;
6037         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6038         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6039                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6040
6041         msr.data = data;
6042         msr.index = ecx;
6043         msr.host_initiated = false;
6044         if (kvm_set_msr(vcpu, &msr) != 0) {
6045                 trace_kvm_msr_write_ex(ecx, data);
6046                 kvm_inject_gp(vcpu, 0);
6047                 return 1;
6048         }
6049
6050         trace_kvm_msr_write(ecx, data);
6051         return kvm_skip_emulated_instruction(vcpu);
6052 }
6053
6054 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6055 {
6056         kvm_apic_update_ppr(vcpu);
6057         return 1;
6058 }
6059
6060 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6061 {
6062         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6063                         CPU_BASED_VIRTUAL_INTR_PENDING);
6064
6065         kvm_make_request(KVM_REQ_EVENT, vcpu);
6066
6067         ++vcpu->stat.irq_window_exits;
6068         return 1;
6069 }
6070
6071 static int handle_halt(struct kvm_vcpu *vcpu)
6072 {
6073         return kvm_emulate_halt(vcpu);
6074 }
6075
6076 static int handle_vmcall(struct kvm_vcpu *vcpu)
6077 {
6078         return kvm_emulate_hypercall(vcpu);
6079 }
6080
6081 static int handle_invd(struct kvm_vcpu *vcpu)
6082 {
6083         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6084 }
6085
6086 static int handle_invlpg(struct kvm_vcpu *vcpu)
6087 {
6088         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6089
6090         kvm_mmu_invlpg(vcpu, exit_qualification);
6091         return kvm_skip_emulated_instruction(vcpu);
6092 }
6093
6094 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6095 {
6096         int err;
6097
6098         err = kvm_rdpmc(vcpu);
6099         return kvm_complete_insn_gp(vcpu, err);
6100 }
6101
6102 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6103 {
6104         return kvm_emulate_wbinvd(vcpu);
6105 }
6106
6107 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6108 {
6109         u64 new_bv = kvm_read_edx_eax(vcpu);
6110         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6111
6112         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6113                 return kvm_skip_emulated_instruction(vcpu);
6114         return 1;
6115 }
6116
6117 static int handle_xsaves(struct kvm_vcpu *vcpu)
6118 {
6119         kvm_skip_emulated_instruction(vcpu);
6120         WARN(1, "this should never happen\n");
6121         return 1;
6122 }
6123
6124 static int handle_xrstors(struct kvm_vcpu *vcpu)
6125 {
6126         kvm_skip_emulated_instruction(vcpu);
6127         WARN(1, "this should never happen\n");
6128         return 1;
6129 }
6130
6131 static int handle_apic_access(struct kvm_vcpu *vcpu)
6132 {
6133         if (likely(fasteoi)) {
6134                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6135                 int access_type, offset;
6136
6137                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6138                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6139                 /*
6140                  * Sane guest uses MOV to write EOI, with written value
6141                  * not cared. So make a short-circuit here by avoiding
6142                  * heavy instruction emulation.
6143                  */
6144                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6145                     (offset == APIC_EOI)) {
6146                         kvm_lapic_set_eoi(vcpu);
6147                         return kvm_skip_emulated_instruction(vcpu);
6148                 }
6149         }
6150         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6151 }
6152
6153 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6154 {
6155         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6156         int vector = exit_qualification & 0xff;
6157
6158         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6159         kvm_apic_set_eoi_accelerated(vcpu, vector);
6160         return 1;
6161 }
6162
6163 static int handle_apic_write(struct kvm_vcpu *vcpu)
6164 {
6165         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6166         u32 offset = exit_qualification & 0xfff;
6167
6168         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6169         kvm_apic_write_nodecode(vcpu, offset);
6170         return 1;
6171 }
6172
6173 static int handle_task_switch(struct kvm_vcpu *vcpu)
6174 {
6175         struct vcpu_vmx *vmx = to_vmx(vcpu);
6176         unsigned long exit_qualification;
6177         bool has_error_code = false;
6178         u32 error_code = 0;
6179         u16 tss_selector;
6180         int reason, type, idt_v, idt_index;
6181
6182         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6183         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6184         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6185
6186         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6187
6188         reason = (u32)exit_qualification >> 30;
6189         if (reason == TASK_SWITCH_GATE && idt_v) {
6190                 switch (type) {
6191                 case INTR_TYPE_NMI_INTR:
6192                         vcpu->arch.nmi_injected = false;
6193                         vmx_set_nmi_mask(vcpu, true);
6194                         break;
6195                 case INTR_TYPE_EXT_INTR:
6196                 case INTR_TYPE_SOFT_INTR:
6197                         kvm_clear_interrupt_queue(vcpu);
6198                         break;
6199                 case INTR_TYPE_HARD_EXCEPTION:
6200                         if (vmx->idt_vectoring_info &
6201                             VECTORING_INFO_DELIVER_CODE_MASK) {
6202                                 has_error_code = true;
6203                                 error_code =
6204                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6205                         }
6206                         /* fall through */
6207                 case INTR_TYPE_SOFT_EXCEPTION:
6208                         kvm_clear_exception_queue(vcpu);
6209                         break;
6210                 default:
6211                         break;
6212                 }
6213         }
6214         tss_selector = exit_qualification;
6215
6216         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6217                        type != INTR_TYPE_EXT_INTR &&
6218                        type != INTR_TYPE_NMI_INTR))
6219                 skip_emulated_instruction(vcpu);
6220
6221         if (kvm_task_switch(vcpu, tss_selector,
6222                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6223                             has_error_code, error_code) == EMULATE_FAIL) {
6224                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6225                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6226                 vcpu->run->internal.ndata = 0;
6227                 return 0;
6228         }
6229
6230         /*
6231          * TODO: What about debug traps on tss switch?
6232          *       Are we supposed to inject them and update dr6?
6233          */
6234
6235         return 1;
6236 }
6237
6238 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6239 {
6240         unsigned long exit_qualification;
6241         gpa_t gpa;
6242         u32 error_code;
6243         int gla_validity;
6244
6245         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6246
6247         gla_validity = (exit_qualification >> 7) & 0x3;
6248         if (gla_validity == 0x2) {
6249                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6250                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6251                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6252                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6253                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6254                         (long unsigned int)exit_qualification);
6255                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6256                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6257                 return 0;
6258         }
6259
6260         /*
6261          * EPT violation happened while executing iret from NMI,
6262          * "blocked by NMI" bit has to be set before next VM entry.
6263          * There are errata that may cause this bit to not be set:
6264          * AAK134, BY25.
6265          */
6266         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6267                         cpu_has_virtual_nmis() &&
6268                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6269                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6270
6271         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6272         trace_kvm_page_fault(gpa, exit_qualification);
6273
6274         /* Is it a read fault? */
6275         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6276                      ? PFERR_USER_MASK : 0;
6277         /* Is it a write fault? */
6278         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6279                       ? PFERR_WRITE_MASK : 0;
6280         /* Is it a fetch fault? */
6281         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6282                       ? PFERR_FETCH_MASK : 0;
6283         /* ept page table entry is present? */
6284         error_code |= (exit_qualification &
6285                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6286                         EPT_VIOLATION_EXECUTABLE))
6287                       ? PFERR_PRESENT_MASK : 0;
6288
6289         vcpu->arch.gpa_available = true;
6290         vcpu->arch.exit_qualification = exit_qualification;
6291
6292         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6293 }
6294
6295 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6296 {
6297         int ret;
6298         gpa_t gpa;
6299
6300         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6301         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6302                 trace_kvm_fast_mmio(gpa);
6303                 return kvm_skip_emulated_instruction(vcpu);
6304         }
6305
6306         ret = handle_mmio_page_fault(vcpu, gpa, true);
6307         vcpu->arch.gpa_available = true;
6308         if (likely(ret == RET_MMIO_PF_EMULATE))
6309                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6310                                               EMULATE_DONE;
6311
6312         if (unlikely(ret == RET_MMIO_PF_INVALID))
6313                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6314
6315         if (unlikely(ret == RET_MMIO_PF_RETRY))
6316                 return 1;
6317
6318         /* It is the real ept misconfig */
6319         WARN_ON(1);
6320
6321         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6322         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6323
6324         return 0;
6325 }
6326
6327 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6328 {
6329         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6330                         CPU_BASED_VIRTUAL_NMI_PENDING);
6331         ++vcpu->stat.nmi_window_exits;
6332         kvm_make_request(KVM_REQ_EVENT, vcpu);
6333
6334         return 1;
6335 }
6336
6337 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6338 {
6339         struct vcpu_vmx *vmx = to_vmx(vcpu);
6340         enum emulation_result err = EMULATE_DONE;
6341         int ret = 1;
6342         u32 cpu_exec_ctrl;
6343         bool intr_window_requested;
6344         unsigned count = 130;
6345
6346         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6347         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6348
6349         while (vmx->emulation_required && count-- != 0) {
6350                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6351                         return handle_interrupt_window(&vmx->vcpu);
6352
6353                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6354                         return 1;
6355
6356                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6357
6358                 if (err == EMULATE_USER_EXIT) {
6359                         ++vcpu->stat.mmio_exits;
6360                         ret = 0;
6361                         goto out;
6362                 }
6363
6364                 if (err != EMULATE_DONE) {
6365                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6366                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6367                         vcpu->run->internal.ndata = 0;
6368                         return 0;
6369                 }
6370
6371                 if (vcpu->arch.halt_request) {
6372                         vcpu->arch.halt_request = 0;
6373                         ret = kvm_vcpu_halt(vcpu);
6374                         goto out;
6375                 }
6376
6377                 if (signal_pending(current))
6378                         goto out;
6379                 if (need_resched())
6380                         schedule();
6381         }
6382
6383 out:
6384         return ret;
6385 }
6386
6387 static int __grow_ple_window(int val)
6388 {
6389         if (ple_window_grow < 1)
6390                 return ple_window;
6391
6392         val = min(val, ple_window_actual_max);
6393
6394         if (ple_window_grow < ple_window)
6395                 val *= ple_window_grow;
6396         else
6397                 val += ple_window_grow;
6398
6399         return val;
6400 }
6401
6402 static int __shrink_ple_window(int val, int modifier, int minimum)
6403 {
6404         if (modifier < 1)
6405                 return ple_window;
6406
6407         if (modifier < ple_window)
6408                 val /= modifier;
6409         else
6410                 val -= modifier;
6411
6412         return max(val, minimum);
6413 }
6414
6415 static void grow_ple_window(struct kvm_vcpu *vcpu)
6416 {
6417         struct vcpu_vmx *vmx = to_vmx(vcpu);
6418         int old = vmx->ple_window;
6419
6420         vmx->ple_window = __grow_ple_window(old);
6421
6422         if (vmx->ple_window != old)
6423                 vmx->ple_window_dirty = true;
6424
6425         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6426 }
6427
6428 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6429 {
6430         struct vcpu_vmx *vmx = to_vmx(vcpu);
6431         int old = vmx->ple_window;
6432
6433         vmx->ple_window = __shrink_ple_window(old,
6434                                               ple_window_shrink, ple_window);
6435
6436         if (vmx->ple_window != old)
6437                 vmx->ple_window_dirty = true;
6438
6439         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6440 }
6441
6442 /*
6443  * ple_window_actual_max is computed to be one grow_ple_window() below
6444  * ple_window_max. (See __grow_ple_window for the reason.)
6445  * This prevents overflows, because ple_window_max is int.
6446  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6447  * this process.
6448  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6449  */
6450 static void update_ple_window_actual_max(void)
6451 {
6452         ple_window_actual_max =
6453                         __shrink_ple_window(max(ple_window_max, ple_window),
6454                                             ple_window_grow, INT_MIN);
6455 }
6456
6457 /*
6458  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6459  */
6460 static void wakeup_handler(void)
6461 {
6462         struct kvm_vcpu *vcpu;
6463         int cpu = smp_processor_id();
6464
6465         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6466         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6467                         blocked_vcpu_list) {
6468                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6469
6470                 if (pi_test_on(pi_desc) == 1)
6471                         kvm_vcpu_kick(vcpu);
6472         }
6473         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6474 }
6475
6476 void vmx_enable_tdp(void)
6477 {
6478         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6479                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6480                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6481                 0ull, VMX_EPT_EXECUTABLE_MASK,
6482                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6483                 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6484
6485         ept_set_mmio_spte_mask();
6486         kvm_enable_tdp();
6487 }
6488
6489 static __init int hardware_setup(void)
6490 {
6491         int r = -ENOMEM, i, msr;
6492
6493         rdmsrl_safe(MSR_EFER, &host_efer);
6494
6495         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6496                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6497
6498         for (i = 0; i < VMX_BITMAP_NR; i++) {
6499                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6500                 if (!vmx_bitmap[i])
6501                         goto out;
6502         }
6503
6504         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6505         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6506         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6507
6508         /*
6509          * Allow direct access to the PC debug port (it is often used for I/O
6510          * delays, but the vmexits simply slow things down).
6511          */
6512         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6513         clear_bit(0x80, vmx_io_bitmap_a);
6514
6515         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6516
6517         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6518         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6519
6520         if (setup_vmcs_config(&vmcs_config) < 0) {
6521                 r = -EIO;
6522                 goto out;
6523         }
6524
6525         if (boot_cpu_has(X86_FEATURE_NX))
6526                 kvm_enable_efer_bits(EFER_NX);
6527
6528         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6529                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6530                 enable_vpid = 0;
6531
6532         if (!cpu_has_vmx_shadow_vmcs())
6533                 enable_shadow_vmcs = 0;
6534         if (enable_shadow_vmcs)
6535                 init_vmcs_shadow_fields();
6536
6537         if (!cpu_has_vmx_ept() ||
6538             !cpu_has_vmx_ept_4levels()) {
6539                 enable_ept = 0;
6540                 enable_unrestricted_guest = 0;
6541                 enable_ept_ad_bits = 0;
6542         }
6543
6544         if (!cpu_has_vmx_ept_ad_bits())
6545                 enable_ept_ad_bits = 0;
6546
6547         if (!cpu_has_vmx_unrestricted_guest())
6548                 enable_unrestricted_guest = 0;
6549
6550         if (!cpu_has_vmx_flexpriority())
6551                 flexpriority_enabled = 0;
6552
6553         /*
6554          * set_apic_access_page_addr() is used to reload apic access
6555          * page upon invalidation.  No need to do anything if not
6556          * using the APIC_ACCESS_ADDR VMCS field.
6557          */
6558         if (!flexpriority_enabled)
6559                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6560
6561         if (!cpu_has_vmx_tpr_shadow())
6562                 kvm_x86_ops->update_cr8_intercept = NULL;
6563
6564         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6565                 kvm_disable_largepages();
6566
6567         if (!cpu_has_vmx_ple())
6568                 ple_gap = 0;
6569
6570         if (!cpu_has_vmx_apicv()) {
6571                 enable_apicv = 0;
6572                 kvm_x86_ops->sync_pir_to_irr = NULL;
6573         }
6574
6575         if (cpu_has_vmx_tsc_scaling()) {
6576                 kvm_has_tsc_control = true;
6577                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6578                 kvm_tsc_scaling_ratio_frac_bits = 48;
6579         }
6580
6581         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6582         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6583         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6584         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6585         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6586         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6587         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6588
6589         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6590                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6591         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6592                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6593         memcpy(vmx_msr_bitmap_legacy_x2apic,
6594                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6595         memcpy(vmx_msr_bitmap_longmode_x2apic,
6596                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6597
6598         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6599
6600         for (msr = 0x800; msr <= 0x8ff; msr++) {
6601                 if (msr == 0x839 /* TMCCT */)
6602                         continue;
6603                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6604         }
6605
6606         /*
6607          * TPR reads and writes can be virtualized even if virtual interrupt
6608          * delivery is not in use.
6609          */
6610         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6611         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6612
6613         /* EOI */
6614         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6615         /* SELF-IPI */
6616         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6617
6618         if (enable_ept)
6619                 vmx_enable_tdp();
6620         else
6621                 kvm_disable_tdp();
6622
6623         update_ple_window_actual_max();
6624
6625         /*
6626          * Only enable PML when hardware supports PML feature, and both EPT
6627          * and EPT A/D bit features are enabled -- PML depends on them to work.
6628          */
6629         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6630                 enable_pml = 0;
6631
6632         if (!enable_pml) {
6633                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6634                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6635                 kvm_x86_ops->flush_log_dirty = NULL;
6636                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6637         }
6638
6639         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6640                 u64 vmx_msr;
6641
6642                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6643                 cpu_preemption_timer_multi =
6644                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6645         } else {
6646                 kvm_x86_ops->set_hv_timer = NULL;
6647                 kvm_x86_ops->cancel_hv_timer = NULL;
6648         }
6649
6650         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6651
6652         kvm_mce_cap_supported |= MCG_LMCE_P;
6653
6654         return alloc_kvm_area();
6655
6656 out:
6657         for (i = 0; i < VMX_BITMAP_NR; i++)
6658                 free_page((unsigned long)vmx_bitmap[i]);
6659
6660     return r;
6661 }
6662
6663 static __exit void hardware_unsetup(void)
6664 {
6665         int i;
6666
6667         for (i = 0; i < VMX_BITMAP_NR; i++)
6668                 free_page((unsigned long)vmx_bitmap[i]);
6669
6670         free_kvm_area();
6671 }
6672
6673 /*
6674  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6675  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6676  */
6677 static int handle_pause(struct kvm_vcpu *vcpu)
6678 {
6679         if (ple_gap)
6680                 grow_ple_window(vcpu);
6681
6682         kvm_vcpu_on_spin(vcpu);
6683         return kvm_skip_emulated_instruction(vcpu);
6684 }
6685
6686 static int handle_nop(struct kvm_vcpu *vcpu)
6687 {
6688         return kvm_skip_emulated_instruction(vcpu);
6689 }
6690
6691 static int handle_mwait(struct kvm_vcpu *vcpu)
6692 {
6693         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6694         return handle_nop(vcpu);
6695 }
6696
6697 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6698 {
6699         return 1;
6700 }
6701
6702 static int handle_monitor(struct kvm_vcpu *vcpu)
6703 {
6704         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6705         return handle_nop(vcpu);
6706 }
6707
6708 /*
6709  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6710  * We could reuse a single VMCS for all the L2 guests, but we also want the
6711  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6712  * allows keeping them loaded on the processor, and in the future will allow
6713  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6714  * every entry if they never change.
6715  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6716  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6717  *
6718  * The following functions allocate and free a vmcs02 in this pool.
6719  */
6720
6721 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6722 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6723 {
6724         struct vmcs02_list *item;
6725         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6726                 if (item->vmptr == vmx->nested.current_vmptr) {
6727                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6728                         return &item->vmcs02;
6729                 }
6730
6731         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6732                 /* Recycle the least recently used VMCS. */
6733                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6734                                        struct vmcs02_list, list);
6735                 item->vmptr = vmx->nested.current_vmptr;
6736                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6737                 return &item->vmcs02;
6738         }
6739
6740         /* Create a new VMCS */
6741         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6742         if (!item)
6743                 return NULL;
6744         item->vmcs02.vmcs = alloc_vmcs();
6745         item->vmcs02.shadow_vmcs = NULL;
6746         if (!item->vmcs02.vmcs) {
6747                 kfree(item);
6748                 return NULL;
6749         }
6750         loaded_vmcs_init(&item->vmcs02);
6751         item->vmptr = vmx->nested.current_vmptr;
6752         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6753         vmx->nested.vmcs02_num++;
6754         return &item->vmcs02;
6755 }
6756
6757 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6758 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6759 {
6760         struct vmcs02_list *item;
6761         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6762                 if (item->vmptr == vmptr) {
6763                         free_loaded_vmcs(&item->vmcs02);
6764                         list_del(&item->list);
6765                         kfree(item);
6766                         vmx->nested.vmcs02_num--;
6767                         return;
6768                 }
6769 }
6770
6771 /*
6772  * Free all VMCSs saved for this vcpu, except the one pointed by
6773  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6774  * must be &vmx->vmcs01.
6775  */
6776 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6777 {
6778         struct vmcs02_list *item, *n;
6779
6780         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6781         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6782                 /*
6783                  * Something will leak if the above WARN triggers.  Better than
6784                  * a use-after-free.
6785                  */
6786                 if (vmx->loaded_vmcs == &item->vmcs02)
6787                         continue;
6788
6789                 free_loaded_vmcs(&item->vmcs02);
6790                 list_del(&item->list);
6791                 kfree(item);
6792                 vmx->nested.vmcs02_num--;
6793         }
6794 }
6795
6796 /*
6797  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6798  * set the success or error code of an emulated VMX instruction, as specified
6799  * by Vol 2B, VMX Instruction Reference, "Conventions".
6800  */
6801 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6802 {
6803         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6804                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6805                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6806 }
6807
6808 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6809 {
6810         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6811                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6812                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6813                         | X86_EFLAGS_CF);
6814 }
6815
6816 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6817                                         u32 vm_instruction_error)
6818 {
6819         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6820                 /*
6821                  * failValid writes the error number to the current VMCS, which
6822                  * can't be done there isn't a current VMCS.
6823                  */
6824                 nested_vmx_failInvalid(vcpu);
6825                 return;
6826         }
6827         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6828                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6829                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6830                         | X86_EFLAGS_ZF);
6831         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6832         /*
6833          * We don't need to force a shadow sync because
6834          * VM_INSTRUCTION_ERROR is not shadowed
6835          */
6836 }
6837
6838 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6839 {
6840         /* TODO: not to reset guest simply here. */
6841         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6842         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6843 }
6844
6845 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6846 {
6847         struct vcpu_vmx *vmx =
6848                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6849
6850         vmx->nested.preemption_timer_expired = true;
6851         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6852         kvm_vcpu_kick(&vmx->vcpu);
6853
6854         return HRTIMER_NORESTART;
6855 }
6856
6857 /*
6858  * Decode the memory-address operand of a vmx instruction, as recorded on an
6859  * exit caused by such an instruction (run by a guest hypervisor).
6860  * On success, returns 0. When the operand is invalid, returns 1 and throws
6861  * #UD or #GP.
6862  */
6863 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6864                                  unsigned long exit_qualification,
6865                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6866 {
6867         gva_t off;
6868         bool exn;
6869         struct kvm_segment s;
6870
6871         /*
6872          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6873          * Execution", on an exit, vmx_instruction_info holds most of the
6874          * addressing components of the operand. Only the displacement part
6875          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6876          * For how an actual address is calculated from all these components,
6877          * refer to Vol. 1, "Operand Addressing".
6878          */
6879         int  scaling = vmx_instruction_info & 3;
6880         int  addr_size = (vmx_instruction_info >> 7) & 7;
6881         bool is_reg = vmx_instruction_info & (1u << 10);
6882         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6883         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6884         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6885         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6886         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6887
6888         if (is_reg) {
6889                 kvm_queue_exception(vcpu, UD_VECTOR);
6890                 return 1;
6891         }
6892
6893         /* Addr = segment_base + offset */
6894         /* offset = base + [index * scale] + displacement */
6895         off = exit_qualification; /* holds the displacement */
6896         if (base_is_valid)
6897                 off += kvm_register_read(vcpu, base_reg);
6898         if (index_is_valid)
6899                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6900         vmx_get_segment(vcpu, &s, seg_reg);
6901         *ret = s.base + off;
6902
6903         if (addr_size == 1) /* 32 bit */
6904                 *ret &= 0xffffffff;
6905
6906         /* Checks for #GP/#SS exceptions. */
6907         exn = false;
6908         if (is_long_mode(vcpu)) {
6909                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6910                  * non-canonical form. This is the only check on the memory
6911                  * destination for long mode!
6912                  */
6913                 exn = is_noncanonical_address(*ret);
6914         } else if (is_protmode(vcpu)) {
6915                 /* Protected mode: apply checks for segment validity in the
6916                  * following order:
6917                  * - segment type check (#GP(0) may be thrown)
6918                  * - usability check (#GP(0)/#SS(0))
6919                  * - limit check (#GP(0)/#SS(0))
6920                  */
6921                 if (wr)
6922                         /* #GP(0) if the destination operand is located in a
6923                          * read-only data segment or any code segment.
6924                          */
6925                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6926                 else
6927                         /* #GP(0) if the source operand is located in an
6928                          * execute-only code segment
6929                          */
6930                         exn = ((s.type & 0xa) == 8);
6931                 if (exn) {
6932                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6933                         return 1;
6934                 }
6935                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6936                  */
6937                 exn = (s.unusable != 0);
6938                 /* Protected mode: #GP(0)/#SS(0) if the memory
6939                  * operand is outside the segment limit.
6940                  */
6941                 exn = exn || (off + sizeof(u64) > s.limit);
6942         }
6943         if (exn) {
6944                 kvm_queue_exception_e(vcpu,
6945                                       seg_reg == VCPU_SREG_SS ?
6946                                                 SS_VECTOR : GP_VECTOR,
6947                                       0);
6948                 return 1;
6949         }
6950
6951         return 0;
6952 }
6953
6954 /*
6955  * This function performs the various checks including
6956  * - if it's 4KB aligned
6957  * - No bits beyond the physical address width are set
6958  * - Returns 0 on success or else 1
6959  * (Intel SDM Section 30.3)
6960  */
6961 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6962                                   gpa_t *vmpointer)
6963 {
6964         gva_t gva;
6965         gpa_t vmptr;
6966         struct x86_exception e;
6967         struct page *page;
6968         struct vcpu_vmx *vmx = to_vmx(vcpu);
6969         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6970
6971         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6972                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6973                 return 1;
6974
6975         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6976                                 sizeof(vmptr), &e)) {
6977                 kvm_inject_page_fault(vcpu, &e);
6978                 return 1;
6979         }
6980
6981         switch (exit_reason) {
6982         case EXIT_REASON_VMON:
6983                 /*
6984                  * SDM 3: 24.11.5
6985                  * The first 4 bytes of VMXON region contain the supported
6986                  * VMCS revision identifier
6987                  *
6988                  * Note - IA32_VMX_BASIC[48] will never be 1
6989                  * for the nested case;
6990                  * which replaces physical address width with 32
6991                  *
6992                  */
6993                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6994                         nested_vmx_failInvalid(vcpu);
6995                         return kvm_skip_emulated_instruction(vcpu);
6996                 }
6997
6998                 page = nested_get_page(vcpu, vmptr);
6999                 if (page == NULL) {
7000                         nested_vmx_failInvalid(vcpu);
7001                         return kvm_skip_emulated_instruction(vcpu);
7002                 }
7003                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7004                         kunmap(page);
7005                         nested_release_page_clean(page);
7006                         nested_vmx_failInvalid(vcpu);
7007                         return kvm_skip_emulated_instruction(vcpu);
7008                 }
7009                 kunmap(page);
7010                 nested_release_page_clean(page);
7011                 vmx->nested.vmxon_ptr = vmptr;
7012                 break;
7013         case EXIT_REASON_VMCLEAR:
7014                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7015                         nested_vmx_failValid(vcpu,
7016                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
7017                         return kvm_skip_emulated_instruction(vcpu);
7018                 }
7019
7020                 if (vmptr == vmx->nested.vmxon_ptr) {
7021                         nested_vmx_failValid(vcpu,
7022                                              VMXERR_VMCLEAR_VMXON_POINTER);
7023                         return kvm_skip_emulated_instruction(vcpu);
7024                 }
7025                 break;
7026         case EXIT_REASON_VMPTRLD:
7027                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7028                         nested_vmx_failValid(vcpu,
7029                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
7030                         return kvm_skip_emulated_instruction(vcpu);
7031                 }
7032
7033                 if (vmptr == vmx->nested.vmxon_ptr) {
7034                         nested_vmx_failValid(vcpu,
7035                                              VMXERR_VMPTRLD_VMXON_POINTER);
7036                         return kvm_skip_emulated_instruction(vcpu);
7037                 }
7038                 break;
7039         default:
7040                 return 1; /* shouldn't happen */
7041         }
7042
7043         if (vmpointer)
7044                 *vmpointer = vmptr;
7045         return 0;
7046 }
7047
7048 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7049 {
7050         struct vcpu_vmx *vmx = to_vmx(vcpu);
7051         struct vmcs *shadow_vmcs;
7052
7053         if (cpu_has_vmx_msr_bitmap()) {
7054                 vmx->nested.msr_bitmap =
7055                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7056                 if (!vmx->nested.msr_bitmap)
7057                         goto out_msr_bitmap;
7058         }
7059
7060         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7061         if (!vmx->nested.cached_vmcs12)
7062                 goto out_cached_vmcs12;
7063
7064         if (enable_shadow_vmcs) {
7065                 shadow_vmcs = alloc_vmcs();
7066                 if (!shadow_vmcs)
7067                         goto out_shadow_vmcs;
7068                 /* mark vmcs as shadow */
7069                 shadow_vmcs->revision_id |= (1u << 31);
7070                 /* init shadow vmcs */
7071                 vmcs_clear(shadow_vmcs);
7072                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7073         }
7074
7075         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7076         vmx->nested.vmcs02_num = 0;
7077
7078         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7079                      HRTIMER_MODE_REL_PINNED);
7080         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7081
7082         vmx->nested.vmxon = true;
7083         return 0;
7084
7085 out_shadow_vmcs:
7086         kfree(vmx->nested.cached_vmcs12);
7087
7088 out_cached_vmcs12:
7089         free_page((unsigned long)vmx->nested.msr_bitmap);
7090
7091 out_msr_bitmap:
7092         return -ENOMEM;
7093 }
7094
7095 /*
7096  * Emulate the VMXON instruction.
7097  * Currently, we just remember that VMX is active, and do not save or even
7098  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7099  * do not currently need to store anything in that guest-allocated memory
7100  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7101  * argument is different from the VMXON pointer (which the spec says they do).
7102  */
7103 static int handle_vmon(struct kvm_vcpu *vcpu)
7104 {
7105         int ret;
7106         struct kvm_segment cs;
7107         struct vcpu_vmx *vmx = to_vmx(vcpu);
7108         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7109                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7110
7111         /* The Intel VMX Instruction Reference lists a bunch of bits that
7112          * are prerequisite to running VMXON, most notably cr4.VMXE must be
7113          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7114          * Otherwise, we should fail with #UD. We test these now:
7115          */
7116         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7117             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7118             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7119                 kvm_queue_exception(vcpu, UD_VECTOR);
7120                 return 1;
7121         }
7122
7123         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7124         if (is_long_mode(vcpu) && !cs.l) {
7125                 kvm_queue_exception(vcpu, UD_VECTOR);
7126                 return 1;
7127         }
7128
7129         if (vmx_get_cpl(vcpu)) {
7130                 kvm_inject_gp(vcpu, 0);
7131                 return 1;
7132         }
7133
7134         if (vmx->nested.vmxon) {
7135                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7136                 return kvm_skip_emulated_instruction(vcpu);
7137         }
7138
7139         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7140                         != VMXON_NEEDED_FEATURES) {
7141                 kvm_inject_gp(vcpu, 0);
7142                 return 1;
7143         }
7144
7145         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7146                 return 1;
7147
7148         ret = enter_vmx_operation(vcpu);
7149         if (ret)
7150                 return ret;
7151
7152         nested_vmx_succeed(vcpu);
7153         return kvm_skip_emulated_instruction(vcpu);
7154 }
7155
7156 /*
7157  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7158  * for running VMX instructions (except VMXON, whose prerequisites are
7159  * slightly different). It also specifies what exception to inject otherwise.
7160  */
7161 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7162 {
7163         struct kvm_segment cs;
7164         struct vcpu_vmx *vmx = to_vmx(vcpu);
7165
7166         if (!vmx->nested.vmxon) {
7167                 kvm_queue_exception(vcpu, UD_VECTOR);
7168                 return 0;
7169         }
7170
7171         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7172         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7173             (is_long_mode(vcpu) && !cs.l)) {
7174                 kvm_queue_exception(vcpu, UD_VECTOR);
7175                 return 0;
7176         }
7177
7178         if (vmx_get_cpl(vcpu)) {
7179                 kvm_inject_gp(vcpu, 0);
7180                 return 0;
7181         }
7182
7183         return 1;
7184 }
7185
7186 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7187 {
7188         if (vmx->nested.current_vmptr == -1ull)
7189                 return;
7190
7191         /* current_vmptr and current_vmcs12 are always set/reset together */
7192         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7193                 return;
7194
7195         if (enable_shadow_vmcs) {
7196                 /* copy to memory all shadowed fields in case
7197                    they were modified */
7198                 copy_shadow_to_vmcs12(vmx);
7199                 vmx->nested.sync_shadow_vmcs = false;
7200                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7201                                 SECONDARY_EXEC_SHADOW_VMCS);
7202                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7203         }
7204         vmx->nested.posted_intr_nv = -1;
7205
7206         /* Flush VMCS12 to guest memory */
7207         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7208                VMCS12_SIZE);
7209
7210         kunmap(vmx->nested.current_vmcs12_page);
7211         nested_release_page(vmx->nested.current_vmcs12_page);
7212         vmx->nested.current_vmptr = -1ull;
7213         vmx->nested.current_vmcs12 = NULL;
7214 }
7215
7216 /*
7217  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7218  * just stops using VMX.
7219  */
7220 static void free_nested(struct vcpu_vmx *vmx)
7221 {
7222         if (!vmx->nested.vmxon)
7223                 return;
7224
7225         vmx->nested.vmxon = false;
7226         free_vpid(vmx->nested.vpid02);
7227         nested_release_vmcs12(vmx);
7228         if (vmx->nested.msr_bitmap) {
7229                 free_page((unsigned long)vmx->nested.msr_bitmap);
7230                 vmx->nested.msr_bitmap = NULL;
7231         }
7232         if (enable_shadow_vmcs) {
7233                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7234                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7235                 vmx->vmcs01.shadow_vmcs = NULL;
7236         }
7237         kfree(vmx->nested.cached_vmcs12);
7238         /* Unpin physical memory we referred to in current vmcs02 */
7239         if (vmx->nested.apic_access_page) {
7240                 nested_release_page(vmx->nested.apic_access_page);
7241                 vmx->nested.apic_access_page = NULL;
7242         }
7243         if (vmx->nested.virtual_apic_page) {
7244                 nested_release_page(vmx->nested.virtual_apic_page);
7245                 vmx->nested.virtual_apic_page = NULL;
7246         }
7247         if (vmx->nested.pi_desc_page) {
7248                 kunmap(vmx->nested.pi_desc_page);
7249                 nested_release_page(vmx->nested.pi_desc_page);
7250                 vmx->nested.pi_desc_page = NULL;
7251                 vmx->nested.pi_desc = NULL;
7252         }
7253
7254         nested_free_all_saved_vmcss(vmx);
7255 }
7256
7257 /* Emulate the VMXOFF instruction */
7258 static int handle_vmoff(struct kvm_vcpu *vcpu)
7259 {
7260         if (!nested_vmx_check_permission(vcpu))
7261                 return 1;
7262         free_nested(to_vmx(vcpu));
7263         nested_vmx_succeed(vcpu);
7264         return kvm_skip_emulated_instruction(vcpu);
7265 }
7266
7267 /* Emulate the VMCLEAR instruction */
7268 static int handle_vmclear(struct kvm_vcpu *vcpu)
7269 {
7270         struct vcpu_vmx *vmx = to_vmx(vcpu);
7271         u32 zero = 0;
7272         gpa_t vmptr;
7273
7274         if (!nested_vmx_check_permission(vcpu))
7275                 return 1;
7276
7277         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7278                 return 1;
7279
7280         if (vmptr == vmx->nested.current_vmptr)
7281                 nested_release_vmcs12(vmx);
7282
7283         kvm_vcpu_write_guest(vcpu,
7284                         vmptr + offsetof(struct vmcs12, launch_state),
7285                         &zero, sizeof(zero));
7286
7287         nested_free_vmcs02(vmx, vmptr);
7288
7289         nested_vmx_succeed(vcpu);
7290         return kvm_skip_emulated_instruction(vcpu);
7291 }
7292
7293 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7294
7295 /* Emulate the VMLAUNCH instruction */
7296 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7297 {
7298         return nested_vmx_run(vcpu, true);
7299 }
7300
7301 /* Emulate the VMRESUME instruction */
7302 static int handle_vmresume(struct kvm_vcpu *vcpu)
7303 {
7304
7305         return nested_vmx_run(vcpu, false);
7306 }
7307
7308 enum vmcs_field_type {
7309         VMCS_FIELD_TYPE_U16 = 0,
7310         VMCS_FIELD_TYPE_U64 = 1,
7311         VMCS_FIELD_TYPE_U32 = 2,
7312         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7313 };
7314
7315 static inline int vmcs_field_type(unsigned long field)
7316 {
7317         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7318                 return VMCS_FIELD_TYPE_U32;
7319         return (field >> 13) & 0x3 ;
7320 }
7321
7322 static inline int vmcs_field_readonly(unsigned long field)
7323 {
7324         return (((field >> 10) & 0x3) == 1);
7325 }
7326
7327 /*
7328  * Read a vmcs12 field. Since these can have varying lengths and we return
7329  * one type, we chose the biggest type (u64) and zero-extend the return value
7330  * to that size. Note that the caller, handle_vmread, might need to use only
7331  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7332  * 64-bit fields are to be returned).
7333  */
7334 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7335                                   unsigned long field, u64 *ret)
7336 {
7337         short offset = vmcs_field_to_offset(field);
7338         char *p;
7339
7340         if (offset < 0)
7341                 return offset;
7342
7343         p = ((char *)(get_vmcs12(vcpu))) + offset;
7344
7345         switch (vmcs_field_type(field)) {
7346         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7347                 *ret = *((natural_width *)p);
7348                 return 0;
7349         case VMCS_FIELD_TYPE_U16:
7350                 *ret = *((u16 *)p);
7351                 return 0;
7352         case VMCS_FIELD_TYPE_U32:
7353                 *ret = *((u32 *)p);
7354                 return 0;
7355         case VMCS_FIELD_TYPE_U64:
7356                 *ret = *((u64 *)p);
7357                 return 0;
7358         default:
7359                 WARN_ON(1);
7360                 return -ENOENT;
7361         }
7362 }
7363
7364
7365 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7366                                    unsigned long field, u64 field_value){
7367         short offset = vmcs_field_to_offset(field);
7368         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7369         if (offset < 0)
7370                 return offset;
7371
7372         switch (vmcs_field_type(field)) {
7373         case VMCS_FIELD_TYPE_U16:
7374                 *(u16 *)p = field_value;
7375                 return 0;
7376         case VMCS_FIELD_TYPE_U32:
7377                 *(u32 *)p = field_value;
7378                 return 0;
7379         case VMCS_FIELD_TYPE_U64:
7380                 *(u64 *)p = field_value;
7381                 return 0;
7382         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7383                 *(natural_width *)p = field_value;
7384                 return 0;
7385         default:
7386                 WARN_ON(1);
7387                 return -ENOENT;
7388         }
7389
7390 }
7391
7392 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7393 {
7394         int i;
7395         unsigned long field;
7396         u64 field_value;
7397         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7398         const unsigned long *fields = shadow_read_write_fields;
7399         const int num_fields = max_shadow_read_write_fields;
7400
7401         preempt_disable();
7402
7403         vmcs_load(shadow_vmcs);
7404
7405         for (i = 0; i < num_fields; i++) {
7406                 field = fields[i];
7407                 switch (vmcs_field_type(field)) {
7408                 case VMCS_FIELD_TYPE_U16:
7409                         field_value = vmcs_read16(field);
7410                         break;
7411                 case VMCS_FIELD_TYPE_U32:
7412                         field_value = vmcs_read32(field);
7413                         break;
7414                 case VMCS_FIELD_TYPE_U64:
7415                         field_value = vmcs_read64(field);
7416                         break;
7417                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7418                         field_value = vmcs_readl(field);
7419                         break;
7420                 default:
7421                         WARN_ON(1);
7422                         continue;
7423                 }
7424                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7425         }
7426
7427         vmcs_clear(shadow_vmcs);
7428         vmcs_load(vmx->loaded_vmcs->vmcs);
7429
7430         preempt_enable();
7431 }
7432
7433 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7434 {
7435         const unsigned long *fields[] = {
7436                 shadow_read_write_fields,
7437                 shadow_read_only_fields
7438         };
7439         const int max_fields[] = {
7440                 max_shadow_read_write_fields,
7441                 max_shadow_read_only_fields
7442         };
7443         int i, q;
7444         unsigned long field;
7445         u64 field_value = 0;
7446         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7447
7448         vmcs_load(shadow_vmcs);
7449
7450         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7451                 for (i = 0; i < max_fields[q]; i++) {
7452                         field = fields[q][i];
7453                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7454
7455                         switch (vmcs_field_type(field)) {
7456                         case VMCS_FIELD_TYPE_U16:
7457                                 vmcs_write16(field, (u16)field_value);
7458                                 break;
7459                         case VMCS_FIELD_TYPE_U32:
7460                                 vmcs_write32(field, (u32)field_value);
7461                                 break;
7462                         case VMCS_FIELD_TYPE_U64:
7463                                 vmcs_write64(field, (u64)field_value);
7464                                 break;
7465                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7466                                 vmcs_writel(field, (long)field_value);
7467                                 break;
7468                         default:
7469                                 WARN_ON(1);
7470                                 break;
7471                         }
7472                 }
7473         }
7474
7475         vmcs_clear(shadow_vmcs);
7476         vmcs_load(vmx->loaded_vmcs->vmcs);
7477 }
7478
7479 /*
7480  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7481  * used before) all generate the same failure when it is missing.
7482  */
7483 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7484 {
7485         struct vcpu_vmx *vmx = to_vmx(vcpu);
7486         if (vmx->nested.current_vmptr == -1ull) {
7487                 nested_vmx_failInvalid(vcpu);
7488                 return 0;
7489         }
7490         return 1;
7491 }
7492
7493 static int handle_vmread(struct kvm_vcpu *vcpu)
7494 {
7495         unsigned long field;
7496         u64 field_value;
7497         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7498         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7499         gva_t gva = 0;
7500
7501         if (!nested_vmx_check_permission(vcpu))
7502                 return 1;
7503
7504         if (!nested_vmx_check_vmcs12(vcpu))
7505                 return kvm_skip_emulated_instruction(vcpu);
7506
7507         /* Decode instruction info and find the field to read */
7508         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7509         /* Read the field, zero-extended to a u64 field_value */
7510         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7511                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7512                 return kvm_skip_emulated_instruction(vcpu);
7513         }
7514         /*
7515          * Now copy part of this value to register or memory, as requested.
7516          * Note that the number of bits actually copied is 32 or 64 depending
7517          * on the guest's mode (32 or 64 bit), not on the given field's length.
7518          */
7519         if (vmx_instruction_info & (1u << 10)) {
7520                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7521                         field_value);
7522         } else {
7523                 if (get_vmx_mem_address(vcpu, exit_qualification,
7524                                 vmx_instruction_info, true, &gva))
7525                         return 1;
7526                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7527                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7528                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7529         }
7530
7531         nested_vmx_succeed(vcpu);
7532         return kvm_skip_emulated_instruction(vcpu);
7533 }
7534
7535
7536 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7537 {
7538         unsigned long field;
7539         gva_t gva;
7540         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7541         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7542         /* The value to write might be 32 or 64 bits, depending on L1's long
7543          * mode, and eventually we need to write that into a field of several
7544          * possible lengths. The code below first zero-extends the value to 64
7545          * bit (field_value), and then copies only the appropriate number of
7546          * bits into the vmcs12 field.
7547          */
7548         u64 field_value = 0;
7549         struct x86_exception e;
7550
7551         if (!nested_vmx_check_permission(vcpu))
7552                 return 1;
7553
7554         if (!nested_vmx_check_vmcs12(vcpu))
7555                 return kvm_skip_emulated_instruction(vcpu);
7556
7557         if (vmx_instruction_info & (1u << 10))
7558                 field_value = kvm_register_readl(vcpu,
7559                         (((vmx_instruction_info) >> 3) & 0xf));
7560         else {
7561                 if (get_vmx_mem_address(vcpu, exit_qualification,
7562                                 vmx_instruction_info, false, &gva))
7563                         return 1;
7564                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7565                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7566                         kvm_inject_page_fault(vcpu, &e);
7567                         return 1;
7568                 }
7569         }
7570
7571
7572         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7573         if (vmcs_field_readonly(field)) {
7574                 nested_vmx_failValid(vcpu,
7575                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7576                 return kvm_skip_emulated_instruction(vcpu);
7577         }
7578
7579         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7580                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7581                 return kvm_skip_emulated_instruction(vcpu);
7582         }
7583
7584         nested_vmx_succeed(vcpu);
7585         return kvm_skip_emulated_instruction(vcpu);
7586 }
7587
7588 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7589 {
7590         vmx->nested.current_vmptr = vmptr;
7591         if (enable_shadow_vmcs) {
7592                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7593                               SECONDARY_EXEC_SHADOW_VMCS);
7594                 vmcs_write64(VMCS_LINK_POINTER,
7595                              __pa(vmx->vmcs01.shadow_vmcs));
7596                 vmx->nested.sync_shadow_vmcs = true;
7597         }
7598 }
7599
7600 /* Emulate the VMPTRLD instruction */
7601 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7602 {
7603         struct vcpu_vmx *vmx = to_vmx(vcpu);
7604         gpa_t vmptr;
7605
7606         if (!nested_vmx_check_permission(vcpu))
7607                 return 1;
7608
7609         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7610                 return 1;
7611
7612         if (vmx->nested.current_vmptr != vmptr) {
7613                 struct vmcs12 *new_vmcs12;
7614                 struct page *page;
7615                 page = nested_get_page(vcpu, vmptr);
7616                 if (page == NULL) {
7617                         nested_vmx_failInvalid(vcpu);
7618                         return kvm_skip_emulated_instruction(vcpu);
7619                 }
7620                 new_vmcs12 = kmap(page);
7621                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7622                         kunmap(page);
7623                         nested_release_page_clean(page);
7624                         nested_vmx_failValid(vcpu,
7625                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7626                         return kvm_skip_emulated_instruction(vcpu);
7627                 }
7628
7629                 nested_release_vmcs12(vmx);
7630                 vmx->nested.current_vmcs12 = new_vmcs12;
7631                 vmx->nested.current_vmcs12_page = page;
7632                 /*
7633                  * Load VMCS12 from guest memory since it is not already
7634                  * cached.
7635                  */
7636                 memcpy(vmx->nested.cached_vmcs12,
7637                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7638                 set_current_vmptr(vmx, vmptr);
7639         }
7640
7641         nested_vmx_succeed(vcpu);
7642         return kvm_skip_emulated_instruction(vcpu);
7643 }
7644
7645 /* Emulate the VMPTRST instruction */
7646 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7647 {
7648         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7649         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7650         gva_t vmcs_gva;
7651         struct x86_exception e;
7652
7653         if (!nested_vmx_check_permission(vcpu))
7654                 return 1;
7655
7656         if (get_vmx_mem_address(vcpu, exit_qualification,
7657                         vmx_instruction_info, true, &vmcs_gva))
7658                 return 1;
7659         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7660         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7661                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7662                                  sizeof(u64), &e)) {
7663                 kvm_inject_page_fault(vcpu, &e);
7664                 return 1;
7665         }
7666         nested_vmx_succeed(vcpu);
7667         return kvm_skip_emulated_instruction(vcpu);
7668 }
7669
7670 /* Emulate the INVEPT instruction */
7671 static int handle_invept(struct kvm_vcpu *vcpu)
7672 {
7673         struct vcpu_vmx *vmx = to_vmx(vcpu);
7674         u32 vmx_instruction_info, types;
7675         unsigned long type;
7676         gva_t gva;
7677         struct x86_exception e;
7678         struct {
7679                 u64 eptp, gpa;
7680         } operand;
7681
7682         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7683               SECONDARY_EXEC_ENABLE_EPT) ||
7684             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7685                 kvm_queue_exception(vcpu, UD_VECTOR);
7686                 return 1;
7687         }
7688
7689         if (!nested_vmx_check_permission(vcpu))
7690                 return 1;
7691
7692         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7693                 kvm_queue_exception(vcpu, UD_VECTOR);
7694                 return 1;
7695         }
7696
7697         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7698         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7699
7700         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7701
7702         if (type >= 32 || !(types & (1 << type))) {
7703                 nested_vmx_failValid(vcpu,
7704                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7705                 return kvm_skip_emulated_instruction(vcpu);
7706         }
7707
7708         /* According to the Intel VMX instruction reference, the memory
7709          * operand is read even if it isn't needed (e.g., for type==global)
7710          */
7711         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7712                         vmx_instruction_info, false, &gva))
7713                 return 1;
7714         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7715                                 sizeof(operand), &e)) {
7716                 kvm_inject_page_fault(vcpu, &e);
7717                 return 1;
7718         }
7719
7720         switch (type) {
7721         case VMX_EPT_EXTENT_GLOBAL:
7722         /*
7723          * TODO: track mappings and invalidate
7724          * single context requests appropriately
7725          */
7726         case VMX_EPT_EXTENT_CONTEXT:
7727                 kvm_mmu_sync_roots(vcpu);
7728                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7729                 nested_vmx_succeed(vcpu);
7730                 break;
7731         default:
7732                 BUG_ON(1);
7733                 break;
7734         }
7735
7736         return kvm_skip_emulated_instruction(vcpu);
7737 }
7738
7739 static int handle_invvpid(struct kvm_vcpu *vcpu)
7740 {
7741         struct vcpu_vmx *vmx = to_vmx(vcpu);
7742         u32 vmx_instruction_info;
7743         unsigned long type, types;
7744         gva_t gva;
7745         struct x86_exception e;
7746         int vpid;
7747
7748         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7749               SECONDARY_EXEC_ENABLE_VPID) ||
7750                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7751                 kvm_queue_exception(vcpu, UD_VECTOR);
7752                 return 1;
7753         }
7754
7755         if (!nested_vmx_check_permission(vcpu))
7756                 return 1;
7757
7758         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7759         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7760
7761         types = (vmx->nested.nested_vmx_vpid_caps &
7762                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7763
7764         if (type >= 32 || !(types & (1 << type))) {
7765                 nested_vmx_failValid(vcpu,
7766                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7767                 return kvm_skip_emulated_instruction(vcpu);
7768         }
7769
7770         /* according to the intel vmx instruction reference, the memory
7771          * operand is read even if it isn't needed (e.g., for type==global)
7772          */
7773         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7774                         vmx_instruction_info, false, &gva))
7775                 return 1;
7776         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7777                                 sizeof(u32), &e)) {
7778                 kvm_inject_page_fault(vcpu, &e);
7779                 return 1;
7780         }
7781
7782         switch (type) {
7783         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7784         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7785         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7786                 if (!vpid) {
7787                         nested_vmx_failValid(vcpu,
7788                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7789                         return kvm_skip_emulated_instruction(vcpu);
7790                 }
7791                 break;
7792         case VMX_VPID_EXTENT_ALL_CONTEXT:
7793                 break;
7794         default:
7795                 WARN_ON_ONCE(1);
7796                 return kvm_skip_emulated_instruction(vcpu);
7797         }
7798
7799         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7800         nested_vmx_succeed(vcpu);
7801
7802         return kvm_skip_emulated_instruction(vcpu);
7803 }
7804
7805 static int handle_pml_full(struct kvm_vcpu *vcpu)
7806 {
7807         unsigned long exit_qualification;
7808
7809         trace_kvm_pml_full(vcpu->vcpu_id);
7810
7811         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7812
7813         /*
7814          * PML buffer FULL happened while executing iret from NMI,
7815          * "blocked by NMI" bit has to be set before next VM entry.
7816          */
7817         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7818                         cpu_has_virtual_nmis() &&
7819                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7820                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7821                                 GUEST_INTR_STATE_NMI);
7822
7823         /*
7824          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7825          * here.., and there's no userspace involvement needed for PML.
7826          */
7827         return 1;
7828 }
7829
7830 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7831 {
7832         kvm_lapic_expired_hv_timer(vcpu);
7833         return 1;
7834 }
7835
7836 /*
7837  * The exit handlers return 1 if the exit was handled fully and guest execution
7838  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7839  * to be done to userspace and return 0.
7840  */
7841 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7842         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7843         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7844         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7845         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7846         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7847         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7848         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7849         [EXIT_REASON_CPUID]                   = handle_cpuid,
7850         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7851         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7852         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7853         [EXIT_REASON_HLT]                     = handle_halt,
7854         [EXIT_REASON_INVD]                    = handle_invd,
7855         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7856         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7857         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7858         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7859         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7860         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7861         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7862         [EXIT_REASON_VMREAD]                  = handle_vmread,
7863         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7864         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7865         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7866         [EXIT_REASON_VMON]                    = handle_vmon,
7867         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7868         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7869         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7870         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7871         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7872         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7873         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7874         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7875         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7876         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7877         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7878         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7879         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7880         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7881         [EXIT_REASON_INVEPT]                  = handle_invept,
7882         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7883         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7884         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7885         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7886         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7887 };
7888
7889 static const int kvm_vmx_max_exit_handlers =
7890         ARRAY_SIZE(kvm_vmx_exit_handlers);
7891
7892 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7893                                        struct vmcs12 *vmcs12)
7894 {
7895         unsigned long exit_qualification;
7896         gpa_t bitmap, last_bitmap;
7897         unsigned int port;
7898         int size;
7899         u8 b;
7900
7901         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7902                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7903
7904         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7905
7906         port = exit_qualification >> 16;
7907         size = (exit_qualification & 7) + 1;
7908
7909         last_bitmap = (gpa_t)-1;
7910         b = -1;
7911
7912         while (size > 0) {
7913                 if (port < 0x8000)
7914                         bitmap = vmcs12->io_bitmap_a;
7915                 else if (port < 0x10000)
7916                         bitmap = vmcs12->io_bitmap_b;
7917                 else
7918                         return true;
7919                 bitmap += (port & 0x7fff) / 8;
7920
7921                 if (last_bitmap != bitmap)
7922                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7923                                 return true;
7924                 if (b & (1 << (port & 7)))
7925                         return true;
7926
7927                 port++;
7928                 size--;
7929                 last_bitmap = bitmap;
7930         }
7931
7932         return false;
7933 }
7934
7935 /*
7936  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7937  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7938  * disinterest in the current event (read or write a specific MSR) by using an
7939  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7940  */
7941 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7942         struct vmcs12 *vmcs12, u32 exit_reason)
7943 {
7944         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7945         gpa_t bitmap;
7946
7947         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7948                 return true;
7949
7950         /*
7951          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7952          * for the four combinations of read/write and low/high MSR numbers.
7953          * First we need to figure out which of the four to use:
7954          */
7955         bitmap = vmcs12->msr_bitmap;
7956         if (exit_reason == EXIT_REASON_MSR_WRITE)
7957                 bitmap += 2048;
7958         if (msr_index >= 0xc0000000) {
7959                 msr_index -= 0xc0000000;
7960                 bitmap += 1024;
7961         }
7962
7963         /* Then read the msr_index'th bit from this bitmap: */
7964         if (msr_index < 1024*8) {
7965                 unsigned char b;
7966                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7967                         return true;
7968                 return 1 & (b >> (msr_index & 7));
7969         } else
7970                 return true; /* let L1 handle the wrong parameter */
7971 }
7972
7973 /*
7974  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7975  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7976  * intercept (via guest_host_mask etc.) the current event.
7977  */
7978 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7979         struct vmcs12 *vmcs12)
7980 {
7981         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7982         int cr = exit_qualification & 15;
7983         int reg = (exit_qualification >> 8) & 15;
7984         unsigned long val = kvm_register_readl(vcpu, reg);
7985
7986         switch ((exit_qualification >> 4) & 3) {
7987         case 0: /* mov to cr */
7988                 switch (cr) {
7989                 case 0:
7990                         if (vmcs12->cr0_guest_host_mask &
7991                             (val ^ vmcs12->cr0_read_shadow))
7992                                 return true;
7993                         break;
7994                 case 3:
7995                         if ((vmcs12->cr3_target_count >= 1 &&
7996                                         vmcs12->cr3_target_value0 == val) ||
7997                                 (vmcs12->cr3_target_count >= 2 &&
7998                                         vmcs12->cr3_target_value1 == val) ||
7999                                 (vmcs12->cr3_target_count >= 3 &&
8000                                         vmcs12->cr3_target_value2 == val) ||
8001                                 (vmcs12->cr3_target_count >= 4 &&
8002                                         vmcs12->cr3_target_value3 == val))
8003                                 return false;
8004                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8005                                 return true;
8006                         break;
8007                 case 4:
8008                         if (vmcs12->cr4_guest_host_mask &
8009                             (vmcs12->cr4_read_shadow ^ val))
8010                                 return true;
8011                         break;
8012                 case 8:
8013                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8014                                 return true;
8015                         break;
8016                 }
8017                 break;
8018         case 2: /* clts */
8019                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8020                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8021                         return true;
8022                 break;
8023         case 1: /* mov from cr */
8024                 switch (cr) {
8025                 case 3:
8026                         if (vmcs12->cpu_based_vm_exec_control &
8027                             CPU_BASED_CR3_STORE_EXITING)
8028                                 return true;
8029                         break;
8030                 case 8:
8031                         if (vmcs12->cpu_based_vm_exec_control &
8032                             CPU_BASED_CR8_STORE_EXITING)
8033                                 return true;
8034                         break;
8035                 }
8036                 break;
8037         case 3: /* lmsw */
8038                 /*
8039                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8040                  * cr0. Other attempted changes are ignored, with no exit.
8041                  */
8042                 if (vmcs12->cr0_guest_host_mask & 0xe &
8043                     (val ^ vmcs12->cr0_read_shadow))
8044                         return true;
8045                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8046                     !(vmcs12->cr0_read_shadow & 0x1) &&
8047                     (val & 0x1))
8048                         return true;
8049                 break;
8050         }
8051         return false;
8052 }
8053
8054 /*
8055  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8056  * should handle it ourselves in L0 (and then continue L2). Only call this
8057  * when in is_guest_mode (L2).
8058  */
8059 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8060 {
8061         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8062         struct vcpu_vmx *vmx = to_vmx(vcpu);
8063         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8064         u32 exit_reason = vmx->exit_reason;
8065
8066         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8067                                 vmcs_readl(EXIT_QUALIFICATION),
8068                                 vmx->idt_vectoring_info,
8069                                 intr_info,
8070                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8071                                 KVM_ISA_VMX);
8072
8073         if (vmx->nested.nested_run_pending)
8074                 return false;
8075
8076         if (unlikely(vmx->fail)) {
8077                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8078                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8079                 return true;
8080         }
8081
8082         switch (exit_reason) {
8083         case EXIT_REASON_EXCEPTION_NMI:
8084                 if (is_nmi(intr_info))
8085                         return false;
8086                 else if (is_page_fault(intr_info))
8087                         return enable_ept;
8088                 else if (is_no_device(intr_info) &&
8089                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8090                         return false;
8091                 else if (is_debug(intr_info) &&
8092                          vcpu->guest_debug &
8093                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8094                         return false;
8095                 else if (is_breakpoint(intr_info) &&
8096                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8097                         return false;
8098                 return vmcs12->exception_bitmap &
8099                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8100         case EXIT_REASON_EXTERNAL_INTERRUPT:
8101                 return false;
8102         case EXIT_REASON_TRIPLE_FAULT:
8103                 return true;
8104         case EXIT_REASON_PENDING_INTERRUPT:
8105                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8106         case EXIT_REASON_NMI_WINDOW:
8107                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8108         case EXIT_REASON_TASK_SWITCH:
8109                 return true;
8110         case EXIT_REASON_CPUID:
8111                 return true;
8112         case EXIT_REASON_HLT:
8113                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8114         case EXIT_REASON_INVD:
8115                 return true;
8116         case EXIT_REASON_INVLPG:
8117                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8118         case EXIT_REASON_RDPMC:
8119                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8120         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8121                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8122         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8123         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8124         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8125         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8126         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8127         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8128                 /*
8129                  * VMX instructions trap unconditionally. This allows L1 to
8130                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8131                  */
8132                 return true;
8133         case EXIT_REASON_CR_ACCESS:
8134                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8135         case EXIT_REASON_DR_ACCESS:
8136                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8137         case EXIT_REASON_IO_INSTRUCTION:
8138                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8139         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8140                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8141         case EXIT_REASON_MSR_READ:
8142         case EXIT_REASON_MSR_WRITE:
8143                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8144         case EXIT_REASON_INVALID_STATE:
8145                 return true;
8146         case EXIT_REASON_MWAIT_INSTRUCTION:
8147                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8148         case EXIT_REASON_MONITOR_TRAP_FLAG:
8149                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8150         case EXIT_REASON_MONITOR_INSTRUCTION:
8151                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8152         case EXIT_REASON_PAUSE_INSTRUCTION:
8153                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8154                         nested_cpu_has2(vmcs12,
8155                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8156         case EXIT_REASON_MCE_DURING_VMENTRY:
8157                 return false;
8158         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8159                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8160         case EXIT_REASON_APIC_ACCESS:
8161                 return nested_cpu_has2(vmcs12,
8162                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8163         case EXIT_REASON_APIC_WRITE:
8164         case EXIT_REASON_EOI_INDUCED:
8165                 /* apic_write and eoi_induced should exit unconditionally. */
8166                 return true;
8167         case EXIT_REASON_EPT_VIOLATION:
8168                 /*
8169                  * L0 always deals with the EPT violation. If nested EPT is
8170                  * used, and the nested mmu code discovers that the address is
8171                  * missing in the guest EPT table (EPT12), the EPT violation
8172                  * will be injected with nested_ept_inject_page_fault()
8173                  */
8174                 return false;
8175         case EXIT_REASON_EPT_MISCONFIG:
8176                 /*
8177                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8178                  * table (shadow on EPT) or a merged EPT table that L0 built
8179                  * (EPT on EPT). So any problems with the structure of the
8180                  * table is L0's fault.
8181                  */
8182                 return false;
8183         case EXIT_REASON_WBINVD:
8184                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8185         case EXIT_REASON_XSETBV:
8186                 return true;
8187         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8188                 /*
8189                  * This should never happen, since it is not possible to
8190                  * set XSS to a non-zero value---neither in L1 nor in L2.
8191                  * If if it were, XSS would have to be checked against
8192                  * the XSS exit bitmap in vmcs12.
8193                  */
8194                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8195         case EXIT_REASON_PREEMPTION_TIMER:
8196                 return false;
8197         case EXIT_REASON_PML_FULL:
8198                 /* We don't expose PML support to L1. */
8199                 return false;
8200         default:
8201                 return true;
8202         }
8203 }
8204
8205 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8206 {
8207         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8208         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8209 }
8210
8211 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8212 {
8213         if (vmx->pml_pg) {
8214                 __free_page(vmx->pml_pg);
8215                 vmx->pml_pg = NULL;
8216         }
8217 }
8218
8219 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8220 {
8221         struct vcpu_vmx *vmx = to_vmx(vcpu);
8222         u64 *pml_buf;
8223         u16 pml_idx;
8224
8225         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8226
8227         /* Do nothing if PML buffer is empty */
8228         if (pml_idx == (PML_ENTITY_NUM - 1))
8229                 return;
8230
8231         /* PML index always points to next available PML buffer entity */
8232         if (pml_idx >= PML_ENTITY_NUM)
8233                 pml_idx = 0;
8234         else
8235                 pml_idx++;
8236
8237         pml_buf = page_address(vmx->pml_pg);
8238         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8239                 u64 gpa;
8240
8241                 gpa = pml_buf[pml_idx];
8242                 WARN_ON(gpa & (PAGE_SIZE - 1));
8243                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8244         }
8245
8246         /* reset PML index */
8247         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8248 }
8249
8250 /*
8251  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8252  * Called before reporting dirty_bitmap to userspace.
8253  */
8254 static void kvm_flush_pml_buffers(struct kvm *kvm)
8255 {
8256         int i;
8257         struct kvm_vcpu *vcpu;
8258         /*
8259          * We only need to kick vcpu out of guest mode here, as PML buffer
8260          * is flushed at beginning of all VMEXITs, and it's obvious that only
8261          * vcpus running in guest are possible to have unflushed GPAs in PML
8262          * buffer.
8263          */
8264         kvm_for_each_vcpu(i, vcpu, kvm)
8265                 kvm_vcpu_kick(vcpu);
8266 }
8267
8268 static void vmx_dump_sel(char *name, uint32_t sel)
8269 {
8270         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8271                name, vmcs_read16(sel),
8272                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8273                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8274                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8275 }
8276
8277 static void vmx_dump_dtsel(char *name, uint32_t limit)
8278 {
8279         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8280                name, vmcs_read32(limit),
8281                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8282 }
8283
8284 static void dump_vmcs(void)
8285 {
8286         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8287         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8288         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8289         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8290         u32 secondary_exec_control = 0;
8291         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8292         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8293         int i, n;
8294
8295         if (cpu_has_secondary_exec_ctrls())
8296                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8297
8298         pr_err("*** Guest State ***\n");
8299         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8300                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8301                vmcs_readl(CR0_GUEST_HOST_MASK));
8302         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8303                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8304         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8305         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8306             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8307         {
8308                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8309                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8310                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8311                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8312         }
8313         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8314                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8315         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8316                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8317         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8318                vmcs_readl(GUEST_SYSENTER_ESP),
8319                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8320         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8321         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8322         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8323         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8324         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8325         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8326         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8327         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8328         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8329         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8330         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8331             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8332                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8333                        efer, vmcs_read64(GUEST_IA32_PAT));
8334         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8335                vmcs_read64(GUEST_IA32_DEBUGCTL),
8336                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8337         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8338                 pr_err("PerfGlobCtl = 0x%016llx\n",
8339                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8340         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8341                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8342         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8343                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8344                vmcs_read32(GUEST_ACTIVITY_STATE));
8345         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8346                 pr_err("InterruptStatus = %04x\n",
8347                        vmcs_read16(GUEST_INTR_STATUS));
8348
8349         pr_err("*** Host State ***\n");
8350         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8351                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8352         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8353                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8354                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8355                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8356                vmcs_read16(HOST_TR_SELECTOR));
8357         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8358                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8359                vmcs_readl(HOST_TR_BASE));
8360         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8361                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8362         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8363                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8364                vmcs_readl(HOST_CR4));
8365         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8366                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8367                vmcs_read32(HOST_IA32_SYSENTER_CS),
8368                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8369         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8370                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8371                        vmcs_read64(HOST_IA32_EFER),
8372                        vmcs_read64(HOST_IA32_PAT));
8373         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8374                 pr_err("PerfGlobCtl = 0x%016llx\n",
8375                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8376
8377         pr_err("*** Control State ***\n");
8378         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8379                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8380         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8381         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8382                vmcs_read32(EXCEPTION_BITMAP),
8383                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8384                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8385         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8386                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8387                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8388                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8389         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8390                vmcs_read32(VM_EXIT_INTR_INFO),
8391                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8392                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8393         pr_err("        reason=%08x qualification=%016lx\n",
8394                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8395         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8396                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8397                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8398         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8399         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8400                 pr_err("TSC Multiplier = 0x%016llx\n",
8401                        vmcs_read64(TSC_MULTIPLIER));
8402         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8403                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8404         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8405                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8406         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8407                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8408         n = vmcs_read32(CR3_TARGET_COUNT);
8409         for (i = 0; i + 1 < n; i += 4)
8410                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8411                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8412                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8413         if (i < n)
8414                 pr_err("CR3 target%u=%016lx\n",
8415                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8416         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8417                 pr_err("PLE Gap=%08x Window=%08x\n",
8418                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8419         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8420                 pr_err("Virtual processor ID = 0x%04x\n",
8421                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8422 }
8423
8424 /*
8425  * The guest has exited.  See if we can fix it or if we need userspace
8426  * assistance.
8427  */
8428 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8429 {
8430         struct vcpu_vmx *vmx = to_vmx(vcpu);
8431         u32 exit_reason = vmx->exit_reason;
8432         u32 vectoring_info = vmx->idt_vectoring_info;
8433
8434         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8435         vcpu->arch.gpa_available = false;
8436
8437         /*
8438          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8439          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8440          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8441          * mode as if vcpus is in root mode, the PML buffer must has been
8442          * flushed already.
8443          */
8444         if (enable_pml)
8445                 vmx_flush_pml_buffer(vcpu);
8446
8447         /* If guest state is invalid, start emulating */
8448         if (vmx->emulation_required)
8449                 return handle_invalid_guest_state(vcpu);
8450
8451         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8452                 nested_vmx_vmexit(vcpu, exit_reason,
8453                                   vmcs_read32(VM_EXIT_INTR_INFO),
8454                                   vmcs_readl(EXIT_QUALIFICATION));
8455                 return 1;
8456         }
8457
8458         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8459                 dump_vmcs();
8460                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8461                 vcpu->run->fail_entry.hardware_entry_failure_reason
8462                         = exit_reason;
8463                 return 0;
8464         }
8465
8466         if (unlikely(vmx->fail)) {
8467                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8468                 vcpu->run->fail_entry.hardware_entry_failure_reason
8469                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8470                 return 0;
8471         }
8472
8473         /*
8474          * Note:
8475          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8476          * delivery event since it indicates guest is accessing MMIO.
8477          * The vm-exit can be triggered again after return to guest that
8478          * will cause infinite loop.
8479          */
8480         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8481                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8482                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8483                         exit_reason != EXIT_REASON_PML_FULL &&
8484                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8485                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8486                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8487                 vcpu->run->internal.ndata = 2;
8488                 vcpu->run->internal.data[0] = vectoring_info;
8489                 vcpu->run->internal.data[1] = exit_reason;
8490                 return 0;
8491         }
8492
8493         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8494             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8495                                         get_vmcs12(vcpu))))) {
8496                 if (vmx_interrupt_allowed(vcpu)) {
8497                         vmx->soft_vnmi_blocked = 0;
8498                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8499                            vcpu->arch.nmi_pending) {
8500                         /*
8501                          * This CPU don't support us in finding the end of an
8502                          * NMI-blocked window if the guest runs with IRQs
8503                          * disabled. So we pull the trigger after 1 s of
8504                          * futile waiting, but inform the user about this.
8505                          */
8506                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8507                                "state on VCPU %d after 1 s timeout\n",
8508                                __func__, vcpu->vcpu_id);
8509                         vmx->soft_vnmi_blocked = 0;
8510                 }
8511         }
8512
8513         if (exit_reason < kvm_vmx_max_exit_handlers
8514             && kvm_vmx_exit_handlers[exit_reason])
8515                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8516         else {
8517                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8518                                 exit_reason);
8519                 kvm_queue_exception(vcpu, UD_VECTOR);
8520                 return 1;
8521         }
8522 }
8523
8524 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8525 {
8526         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8527
8528         if (is_guest_mode(vcpu) &&
8529                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8530                 return;
8531
8532         if (irr == -1 || tpr < irr) {
8533                 vmcs_write32(TPR_THRESHOLD, 0);
8534                 return;
8535         }
8536
8537         vmcs_write32(TPR_THRESHOLD, irr);
8538 }
8539
8540 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8541 {
8542         u32 sec_exec_control;
8543
8544         /* Postpone execution until vmcs01 is the current VMCS. */
8545         if (is_guest_mode(vcpu)) {
8546                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8547                 return;
8548         }
8549
8550         if (!cpu_has_vmx_virtualize_x2apic_mode())
8551                 return;
8552
8553         if (!cpu_need_tpr_shadow(vcpu))
8554                 return;
8555
8556         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8557
8558         if (set) {
8559                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8560                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8561         } else {
8562                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8563                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8564                 vmx_flush_tlb_ept_only(vcpu);
8565         }
8566         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8567
8568         vmx_set_msr_bitmap(vcpu);
8569 }
8570
8571 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8572 {
8573         struct vcpu_vmx *vmx = to_vmx(vcpu);
8574
8575         /*
8576          * Currently we do not handle the nested case where L2 has an
8577          * APIC access page of its own; that page is still pinned.
8578          * Hence, we skip the case where the VCPU is in guest mode _and_
8579          * L1 prepared an APIC access page for L2.
8580          *
8581          * For the case where L1 and L2 share the same APIC access page
8582          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8583          * in the vmcs12), this function will only update either the vmcs01
8584          * or the vmcs02.  If the former, the vmcs02 will be updated by
8585          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8586          * the next L2->L1 exit.
8587          */
8588         if (!is_guest_mode(vcpu) ||
8589             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8590                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8591                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8592                 vmx_flush_tlb_ept_only(vcpu);
8593         }
8594 }
8595
8596 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8597 {
8598         u16 status;
8599         u8 old;
8600
8601         if (max_isr == -1)
8602                 max_isr = 0;
8603
8604         status = vmcs_read16(GUEST_INTR_STATUS);
8605         old = status >> 8;
8606         if (max_isr != old) {
8607                 status &= 0xff;
8608                 status |= max_isr << 8;
8609                 vmcs_write16(GUEST_INTR_STATUS, status);
8610         }
8611 }
8612
8613 static void vmx_set_rvi(int vector)
8614 {
8615         u16 status;
8616         u8 old;
8617
8618         if (vector == -1)
8619                 vector = 0;
8620
8621         status = vmcs_read16(GUEST_INTR_STATUS);
8622         old = (u8)status & 0xff;
8623         if ((u8)vector != old) {
8624                 status &= ~0xff;
8625                 status |= (u8)vector;
8626                 vmcs_write16(GUEST_INTR_STATUS, status);
8627         }
8628 }
8629
8630 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8631 {
8632         if (!is_guest_mode(vcpu)) {
8633                 vmx_set_rvi(max_irr);
8634                 return;
8635         }
8636
8637         if (max_irr == -1)
8638                 return;
8639
8640         /*
8641          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8642          * handles it.
8643          */
8644         if (nested_exit_on_intr(vcpu))
8645                 return;
8646
8647         /*
8648          * Else, fall back to pre-APICv interrupt injection since L2
8649          * is run without virtual interrupt delivery.
8650          */
8651         if (!kvm_event_needs_reinjection(vcpu) &&
8652             vmx_interrupt_allowed(vcpu)) {
8653                 kvm_queue_interrupt(vcpu, max_irr, false);
8654                 vmx_inject_irq(vcpu);
8655         }
8656 }
8657
8658 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8659 {
8660         struct vcpu_vmx *vmx = to_vmx(vcpu);
8661         int max_irr;
8662
8663         WARN_ON(!vcpu->arch.apicv_active);
8664         if (pi_test_on(&vmx->pi_desc)) {
8665                 pi_clear_on(&vmx->pi_desc);
8666                 /*
8667                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8668                  * But on x86 this is just a compiler barrier anyway.
8669                  */
8670                 smp_mb__after_atomic();
8671                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8672         } else {
8673                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8674         }
8675         vmx_hwapic_irr_update(vcpu, max_irr);
8676         return max_irr;
8677 }
8678
8679 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8680 {
8681         if (!kvm_vcpu_apicv_active(vcpu))
8682                 return;
8683
8684         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8685         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8686         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8687         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8688 }
8689
8690 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8691 {
8692         struct vcpu_vmx *vmx = to_vmx(vcpu);
8693
8694         pi_clear_on(&vmx->pi_desc);
8695         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8696 }
8697
8698 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8699 {
8700         u32 exit_intr_info;
8701
8702         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8703               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8704                 return;
8705
8706         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8707         exit_intr_info = vmx->exit_intr_info;
8708
8709         /* Handle machine checks before interrupts are enabled */
8710         if (is_machine_check(exit_intr_info))
8711                 kvm_machine_check();
8712
8713         /* We need to handle NMIs before interrupts are enabled */
8714         if (is_nmi(exit_intr_info)) {
8715                 kvm_before_handle_nmi(&vmx->vcpu);
8716                 asm("int $2");
8717                 kvm_after_handle_nmi(&vmx->vcpu);
8718         }
8719 }
8720
8721 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8722 {
8723         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8724         register void *__sp asm(_ASM_SP);
8725
8726         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8727                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8728                 unsigned int vector;
8729                 unsigned long entry;
8730                 gate_desc *desc;
8731                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8732 #ifdef CONFIG_X86_64
8733                 unsigned long tmp;
8734 #endif
8735
8736                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8737                 desc = (gate_desc *)vmx->host_idt_base + vector;
8738                 entry = gate_offset(*desc);
8739                 asm volatile(
8740 #ifdef CONFIG_X86_64
8741                         "mov %%" _ASM_SP ", %[sp]\n\t"
8742                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8743                         "push $%c[ss]\n\t"
8744                         "push %[sp]\n\t"
8745 #endif
8746                         "pushf\n\t"
8747                         __ASM_SIZE(push) " $%c[cs]\n\t"
8748                         "call *%[entry]\n\t"
8749                         :
8750 #ifdef CONFIG_X86_64
8751                         [sp]"=&r"(tmp),
8752 #endif
8753                         "+r"(__sp)
8754                         :
8755                         [entry]"r"(entry),
8756                         [ss]"i"(__KERNEL_DS),
8757                         [cs]"i"(__KERNEL_CS)
8758                         );
8759         }
8760 }
8761
8762 static bool vmx_has_high_real_mode_segbase(void)
8763 {
8764         return enable_unrestricted_guest || emulate_invalid_guest_state;
8765 }
8766
8767 static bool vmx_mpx_supported(void)
8768 {
8769         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8770                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8771 }
8772
8773 static bool vmx_xsaves_supported(void)
8774 {
8775         return vmcs_config.cpu_based_2nd_exec_ctrl &
8776                 SECONDARY_EXEC_XSAVES;
8777 }
8778
8779 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8780 {
8781         u32 exit_intr_info;
8782         bool unblock_nmi;
8783         u8 vector;
8784         bool idtv_info_valid;
8785
8786         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8787
8788         if (cpu_has_virtual_nmis()) {
8789                 if (vmx->nmi_known_unmasked)
8790                         return;
8791                 /*
8792                  * Can't use vmx->exit_intr_info since we're not sure what
8793                  * the exit reason is.
8794                  */
8795                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8796                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8797                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8798                 /*
8799                  * SDM 3: 27.7.1.2 (September 2008)
8800                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8801                  * a guest IRET fault.
8802                  * SDM 3: 23.2.2 (September 2008)
8803                  * Bit 12 is undefined in any of the following cases:
8804                  *  If the VM exit sets the valid bit in the IDT-vectoring
8805                  *   information field.
8806                  *  If the VM exit is due to a double fault.
8807                  */
8808                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8809                     vector != DF_VECTOR && !idtv_info_valid)
8810                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8811                                       GUEST_INTR_STATE_NMI);
8812                 else
8813                         vmx->nmi_known_unmasked =
8814                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8815                                   & GUEST_INTR_STATE_NMI);
8816         } else if (unlikely(vmx->soft_vnmi_blocked))
8817                 vmx->vnmi_blocked_time +=
8818                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8819 }
8820
8821 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8822                                       u32 idt_vectoring_info,
8823                                       int instr_len_field,
8824                                       int error_code_field)
8825 {
8826         u8 vector;
8827         int type;
8828         bool idtv_info_valid;
8829
8830         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8831
8832         vcpu->arch.nmi_injected = false;
8833         kvm_clear_exception_queue(vcpu);
8834         kvm_clear_interrupt_queue(vcpu);
8835
8836         if (!idtv_info_valid)
8837                 return;
8838
8839         kvm_make_request(KVM_REQ_EVENT, vcpu);
8840
8841         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8842         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8843
8844         switch (type) {
8845         case INTR_TYPE_NMI_INTR:
8846                 vcpu->arch.nmi_injected = true;
8847                 /*
8848                  * SDM 3: 27.7.1.2 (September 2008)
8849                  * Clear bit "block by NMI" before VM entry if a NMI
8850                  * delivery faulted.
8851                  */
8852                 vmx_set_nmi_mask(vcpu, false);
8853                 break;
8854         case INTR_TYPE_SOFT_EXCEPTION:
8855                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8856                 /* fall through */
8857         case INTR_TYPE_HARD_EXCEPTION:
8858                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8859                         u32 err = vmcs_read32(error_code_field);
8860                         kvm_requeue_exception_e(vcpu, vector, err);
8861                 } else
8862                         kvm_requeue_exception(vcpu, vector);
8863                 break;
8864         case INTR_TYPE_SOFT_INTR:
8865                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8866                 /* fall through */
8867         case INTR_TYPE_EXT_INTR:
8868                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8869                 break;
8870         default:
8871                 break;
8872         }
8873 }
8874
8875 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8876 {
8877         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8878                                   VM_EXIT_INSTRUCTION_LEN,
8879                                   IDT_VECTORING_ERROR_CODE);
8880 }
8881
8882 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8883 {
8884         __vmx_complete_interrupts(vcpu,
8885                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8886                                   VM_ENTRY_INSTRUCTION_LEN,
8887                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8888
8889         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8890 }
8891
8892 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8893 {
8894         int i, nr_msrs;
8895         struct perf_guest_switch_msr *msrs;
8896
8897         msrs = perf_guest_get_msrs(&nr_msrs);
8898
8899         if (!msrs)
8900                 return;
8901
8902         for (i = 0; i < nr_msrs; i++)
8903                 if (msrs[i].host == msrs[i].guest)
8904                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8905                 else
8906                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8907                                         msrs[i].host);
8908 }
8909
8910 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8911 {
8912         struct vcpu_vmx *vmx = to_vmx(vcpu);
8913         u64 tscl;
8914         u32 delta_tsc;
8915
8916         if (vmx->hv_deadline_tsc == -1)
8917                 return;
8918
8919         tscl = rdtsc();
8920         if (vmx->hv_deadline_tsc > tscl)
8921                 /* sure to be 32 bit only because checked on set_hv_timer */
8922                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8923                         cpu_preemption_timer_multi);
8924         else
8925                 delta_tsc = 0;
8926
8927         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8928 }
8929
8930 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8931 {
8932         struct vcpu_vmx *vmx = to_vmx(vcpu);
8933         unsigned long debugctlmsr, cr4;
8934
8935         /* Record the guest's net vcpu time for enforced NMI injections. */
8936         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8937                 vmx->entry_time = ktime_get();
8938
8939         /* Don't enter VMX if guest state is invalid, let the exit handler
8940            start emulation until we arrive back to a valid state */
8941         if (vmx->emulation_required)
8942                 return;
8943
8944         if (vmx->ple_window_dirty) {
8945                 vmx->ple_window_dirty = false;
8946                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8947         }
8948
8949         if (vmx->nested.sync_shadow_vmcs) {
8950                 copy_vmcs12_to_shadow(vmx);
8951                 vmx->nested.sync_shadow_vmcs = false;
8952         }
8953
8954         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8955                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8956         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8957                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8958
8959         cr4 = cr4_read_shadow();
8960         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8961                 vmcs_writel(HOST_CR4, cr4);
8962                 vmx->host_state.vmcs_host_cr4 = cr4;
8963         }
8964
8965         /* When single-stepping over STI and MOV SS, we must clear the
8966          * corresponding interruptibility bits in the guest state. Otherwise
8967          * vmentry fails as it then expects bit 14 (BS) in pending debug
8968          * exceptions being set, but that's not correct for the guest debugging
8969          * case. */
8970         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8971                 vmx_set_interrupt_shadow(vcpu, 0);
8972
8973         if (vmx->guest_pkru_valid)
8974                 __write_pkru(vmx->guest_pkru);
8975
8976         atomic_switch_perf_msrs(vmx);
8977         debugctlmsr = get_debugctlmsr();
8978
8979         vmx_arm_hv_timer(vcpu);
8980
8981         vmx->__launched = vmx->loaded_vmcs->launched;
8982         asm(
8983                 /* Store host registers */
8984                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8985                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8986                 "push %%" _ASM_CX " \n\t"
8987                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8988                 "je 1f \n\t"
8989                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8990                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8991                 "1: \n\t"
8992                 /* Reload cr2 if changed */
8993                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8994                 "mov %%cr2, %%" _ASM_DX " \n\t"
8995                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8996                 "je 2f \n\t"
8997                 "mov %%" _ASM_AX", %%cr2 \n\t"
8998                 "2: \n\t"
8999                 /* Check if vmlaunch of vmresume is needed */
9000                 "cmpl $0, %c[launched](%0) \n\t"
9001                 /* Load guest registers.  Don't clobber flags. */
9002                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9003                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9004                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9005                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9006                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9007                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9008 #ifdef CONFIG_X86_64
9009                 "mov %c[r8](%0),  %%r8  \n\t"
9010                 "mov %c[r9](%0),  %%r9  \n\t"
9011                 "mov %c[r10](%0), %%r10 \n\t"
9012                 "mov %c[r11](%0), %%r11 \n\t"
9013                 "mov %c[r12](%0), %%r12 \n\t"
9014                 "mov %c[r13](%0), %%r13 \n\t"
9015                 "mov %c[r14](%0), %%r14 \n\t"
9016                 "mov %c[r15](%0), %%r15 \n\t"
9017 #endif
9018                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9019
9020                 /* Enter guest mode */
9021                 "jne 1f \n\t"
9022                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9023                 "jmp 2f \n\t"
9024                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9025                 "2: "
9026                 /* Save guest registers, load host registers, keep flags */
9027                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9028                 "pop %0 \n\t"
9029                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9030                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9031                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9032                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9033                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9034                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9035                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9036 #ifdef CONFIG_X86_64
9037                 "mov %%r8,  %c[r8](%0) \n\t"
9038                 "mov %%r9,  %c[r9](%0) \n\t"
9039                 "mov %%r10, %c[r10](%0) \n\t"
9040                 "mov %%r11, %c[r11](%0) \n\t"
9041                 "mov %%r12, %c[r12](%0) \n\t"
9042                 "mov %%r13, %c[r13](%0) \n\t"
9043                 "mov %%r14, %c[r14](%0) \n\t"
9044                 "mov %%r15, %c[r15](%0) \n\t"
9045 #endif
9046                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9047                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9048
9049                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9050                 "setbe %c[fail](%0) \n\t"
9051                 ".pushsection .rodata \n\t"
9052                 ".global vmx_return \n\t"
9053                 "vmx_return: " _ASM_PTR " 2b \n\t"
9054                 ".popsection"
9055               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9056                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9057                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9058                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9059                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9060                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9061                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9062                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9063                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9064                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9065                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9066 #ifdef CONFIG_X86_64
9067                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9068                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9069                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9070                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9071                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9072                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9073                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9074                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9075 #endif
9076                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9077                 [wordsize]"i"(sizeof(ulong))
9078               : "cc", "memory"
9079 #ifdef CONFIG_X86_64
9080                 , "rax", "rbx", "rdi", "rsi"
9081                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9082 #else
9083                 , "eax", "ebx", "edi", "esi"
9084 #endif
9085               );
9086
9087         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9088         if (debugctlmsr)
9089                 update_debugctlmsr(debugctlmsr);
9090
9091 #ifndef CONFIG_X86_64
9092         /*
9093          * The sysexit path does not restore ds/es, so we must set them to
9094          * a reasonable value ourselves.
9095          *
9096          * We can't defer this to vmx_load_host_state() since that function
9097          * may be executed in interrupt context, which saves and restore segments
9098          * around it, nullifying its effect.
9099          */
9100         loadsegment(ds, __USER_DS);
9101         loadsegment(es, __USER_DS);
9102 #endif
9103
9104         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9105                                   | (1 << VCPU_EXREG_RFLAGS)
9106                                   | (1 << VCPU_EXREG_PDPTR)
9107                                   | (1 << VCPU_EXREG_SEGMENTS)
9108                                   | (1 << VCPU_EXREG_CR3));
9109         vcpu->arch.regs_dirty = 0;
9110
9111         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9112
9113         vmx->loaded_vmcs->launched = 1;
9114
9115         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9116
9117         /*
9118          * eager fpu is enabled if PKEY is supported and CR4 is switched
9119          * back on host, so it is safe to read guest PKRU from current
9120          * XSAVE.
9121          */
9122         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9123                 vmx->guest_pkru = __read_pkru();
9124                 if (vmx->guest_pkru != vmx->host_pkru) {
9125                         vmx->guest_pkru_valid = true;
9126                         __write_pkru(vmx->host_pkru);
9127                 } else
9128                         vmx->guest_pkru_valid = false;
9129         }
9130
9131         /*
9132          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9133          * we did not inject a still-pending event to L1 now because of
9134          * nested_run_pending, we need to re-enable this bit.
9135          */
9136         if (vmx->nested.nested_run_pending)
9137                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9138
9139         vmx->nested.nested_run_pending = 0;
9140
9141         vmx_complete_atomic_exit(vmx);
9142         vmx_recover_nmi_blocking(vmx);
9143         vmx_complete_interrupts(vmx);
9144 }
9145
9146 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9147 {
9148         struct vcpu_vmx *vmx = to_vmx(vcpu);
9149         int cpu;
9150
9151         if (vmx->loaded_vmcs == &vmx->vmcs01)
9152                 return;
9153
9154         cpu = get_cpu();
9155         vmx->loaded_vmcs = &vmx->vmcs01;
9156         vmx_vcpu_put(vcpu);
9157         vmx_vcpu_load(vcpu, cpu);
9158         vcpu->cpu = cpu;
9159         put_cpu();
9160 }
9161
9162 /*
9163  * Ensure that the current vmcs of the logical processor is the
9164  * vmcs01 of the vcpu before calling free_nested().
9165  */
9166 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9167 {
9168        struct vcpu_vmx *vmx = to_vmx(vcpu);
9169        int r;
9170
9171        r = vcpu_load(vcpu);
9172        BUG_ON(r);
9173        vmx_load_vmcs01(vcpu);
9174        free_nested(vmx);
9175        vcpu_put(vcpu);
9176 }
9177
9178 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9179 {
9180         struct vcpu_vmx *vmx = to_vmx(vcpu);
9181
9182         if (enable_pml)
9183                 vmx_destroy_pml_buffer(vmx);
9184         free_vpid(vmx->vpid);
9185         leave_guest_mode(vcpu);
9186         vmx_free_vcpu_nested(vcpu);
9187         free_loaded_vmcs(vmx->loaded_vmcs);
9188         kfree(vmx->guest_msrs);
9189         kvm_vcpu_uninit(vcpu);
9190         kmem_cache_free(kvm_vcpu_cache, vmx);
9191 }
9192
9193 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9194 {
9195         int err;
9196         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9197         int cpu;
9198
9199         if (!vmx)
9200                 return ERR_PTR(-ENOMEM);
9201
9202         vmx->vpid = allocate_vpid();
9203
9204         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9205         if (err)
9206                 goto free_vcpu;
9207
9208         err = -ENOMEM;
9209
9210         /*
9211          * If PML is turned on, failure on enabling PML just results in failure
9212          * of creating the vcpu, therefore we can simplify PML logic (by
9213          * avoiding dealing with cases, such as enabling PML partially on vcpus
9214          * for the guest, etc.
9215          */
9216         if (enable_pml) {
9217                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9218                 if (!vmx->pml_pg)
9219                         goto uninit_vcpu;
9220         }
9221
9222         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9223         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9224                      > PAGE_SIZE);
9225
9226         if (!vmx->guest_msrs)
9227                 goto free_pml;
9228
9229         vmx->loaded_vmcs = &vmx->vmcs01;
9230         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9231         vmx->loaded_vmcs->shadow_vmcs = NULL;
9232         if (!vmx->loaded_vmcs->vmcs)
9233                 goto free_msrs;
9234         if (!vmm_exclusive)
9235                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9236         loaded_vmcs_init(vmx->loaded_vmcs);
9237         if (!vmm_exclusive)
9238                 kvm_cpu_vmxoff();
9239
9240         cpu = get_cpu();
9241         vmx_vcpu_load(&vmx->vcpu, cpu);
9242         vmx->vcpu.cpu = cpu;
9243         err = vmx_vcpu_setup(vmx);
9244         vmx_vcpu_put(&vmx->vcpu);
9245         put_cpu();
9246         if (err)
9247                 goto free_vmcs;
9248         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9249                 err = alloc_apic_access_page(kvm);
9250                 if (err)
9251                         goto free_vmcs;
9252         }
9253
9254         if (enable_ept) {
9255                 if (!kvm->arch.ept_identity_map_addr)
9256                         kvm->arch.ept_identity_map_addr =
9257                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9258                 err = init_rmode_identity_map(kvm);
9259                 if (err)
9260                         goto free_vmcs;
9261         }
9262
9263         if (nested) {
9264                 nested_vmx_setup_ctls_msrs(vmx);
9265                 vmx->nested.vpid02 = allocate_vpid();
9266         }
9267
9268         vmx->nested.posted_intr_nv = -1;
9269         vmx->nested.current_vmptr = -1ull;
9270         vmx->nested.current_vmcs12 = NULL;
9271
9272         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9273
9274         return &vmx->vcpu;
9275
9276 free_vmcs:
9277         free_vpid(vmx->nested.vpid02);
9278         free_loaded_vmcs(vmx->loaded_vmcs);
9279 free_msrs:
9280         kfree(vmx->guest_msrs);
9281 free_pml:
9282         vmx_destroy_pml_buffer(vmx);
9283 uninit_vcpu:
9284         kvm_vcpu_uninit(&vmx->vcpu);
9285 free_vcpu:
9286         free_vpid(vmx->vpid);
9287         kmem_cache_free(kvm_vcpu_cache, vmx);
9288         return ERR_PTR(err);
9289 }
9290
9291 static void __init vmx_check_processor_compat(void *rtn)
9292 {
9293         struct vmcs_config vmcs_conf;
9294
9295         *(int *)rtn = 0;
9296         if (setup_vmcs_config(&vmcs_conf) < 0)
9297                 *(int *)rtn = -EIO;
9298         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9299                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9300                                 smp_processor_id());
9301                 *(int *)rtn = -EIO;
9302         }
9303 }
9304
9305 static int get_ept_level(void)
9306 {
9307         return VMX_EPT_DEFAULT_GAW + 1;
9308 }
9309
9310 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9311 {
9312         u8 cache;
9313         u64 ipat = 0;
9314
9315         /* For VT-d and EPT combination
9316          * 1. MMIO: always map as UC
9317          * 2. EPT with VT-d:
9318          *   a. VT-d without snooping control feature: can't guarantee the
9319          *      result, try to trust guest.
9320          *   b. VT-d with snooping control feature: snooping control feature of
9321          *      VT-d engine can guarantee the cache correctness. Just set it
9322          *      to WB to keep consistent with host. So the same as item 3.
9323          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9324          *    consistent with host MTRR
9325          */
9326         if (is_mmio) {
9327                 cache = MTRR_TYPE_UNCACHABLE;
9328                 goto exit;
9329         }
9330
9331         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9332                 ipat = VMX_EPT_IPAT_BIT;
9333                 cache = MTRR_TYPE_WRBACK;
9334                 goto exit;
9335         }
9336
9337         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9338                 ipat = VMX_EPT_IPAT_BIT;
9339                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9340                         cache = MTRR_TYPE_WRBACK;
9341                 else
9342                         cache = MTRR_TYPE_UNCACHABLE;
9343                 goto exit;
9344         }
9345
9346         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9347
9348 exit:
9349         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9350 }
9351
9352 static int vmx_get_lpage_level(void)
9353 {
9354         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9355                 return PT_DIRECTORY_LEVEL;
9356         else
9357                 /* For shadow and EPT supported 1GB page */
9358                 return PT_PDPE_LEVEL;
9359 }
9360
9361 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9362 {
9363         /*
9364          * These bits in the secondary execution controls field
9365          * are dynamic, the others are mostly based on the hypervisor
9366          * architecture and the guest's CPUID.  Do not touch the
9367          * dynamic bits.
9368          */
9369         u32 mask =
9370                 SECONDARY_EXEC_SHADOW_VMCS |
9371                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9372                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9373
9374         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9375
9376         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9377                      (new_ctl & ~mask) | (cur_ctl & mask));
9378 }
9379
9380 /*
9381  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9382  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9383  */
9384 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9385 {
9386         struct vcpu_vmx *vmx = to_vmx(vcpu);
9387         struct kvm_cpuid_entry2 *entry;
9388
9389         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9390         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9391
9392 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9393         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9394                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9395 } while (0)
9396
9397         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9398         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9399         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9400         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9401         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9402         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9403         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9404         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9405         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9406         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9407         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9408         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9409         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9410         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9411         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9412
9413         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9414         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9415         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9416         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9417         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9418         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9419         cr4_fixed1_update(bit(11),            ecx, bit(2));
9420
9421 #undef cr4_fixed1_update
9422 }
9423
9424 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9425 {
9426         struct kvm_cpuid_entry2 *best;
9427         struct vcpu_vmx *vmx = to_vmx(vcpu);
9428         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9429
9430         if (vmx_rdtscp_supported()) {
9431                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9432                 if (!rdtscp_enabled)
9433                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9434
9435                 if (nested) {
9436                         if (rdtscp_enabled)
9437                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9438                                         SECONDARY_EXEC_RDTSCP;
9439                         else
9440                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9441                                         ~SECONDARY_EXEC_RDTSCP;
9442                 }
9443         }
9444
9445         /* Exposing INVPCID only when PCID is exposed */
9446         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9447         if (vmx_invpcid_supported() &&
9448             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9449             !guest_cpuid_has_pcid(vcpu))) {
9450                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9451
9452                 if (best)
9453                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9454         }
9455
9456         if (cpu_has_secondary_exec_ctrls())
9457                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9458
9459         if (nested_vmx_allowed(vcpu))
9460                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9461                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9462         else
9463                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9464                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9465
9466         if (nested_vmx_allowed(vcpu))
9467                 nested_vmx_cr_fixed1_bits_update(vcpu);
9468 }
9469
9470 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9471 {
9472         if (func == 1 && nested)
9473                 entry->ecx |= bit(X86_FEATURE_VMX);
9474 }
9475
9476 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9477                 struct x86_exception *fault)
9478 {
9479         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9480         u32 exit_reason;
9481
9482         if (fault->error_code & PFERR_RSVD_MASK)
9483                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9484         else
9485                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9486         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9487         vmcs12->guest_physical_address = fault->address;
9488 }
9489
9490 /* Callbacks for nested_ept_init_mmu_context: */
9491
9492 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9493 {
9494         /* return the page table to be shadowed - in our case, EPT12 */
9495         return get_vmcs12(vcpu)->ept_pointer;
9496 }
9497
9498 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9499 {
9500         WARN_ON(mmu_is_nested(vcpu));
9501         kvm_init_shadow_ept_mmu(vcpu,
9502                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9503                         VMX_EPT_EXECUTE_ONLY_BIT);
9504         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9505         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9506         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9507
9508         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9509 }
9510
9511 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9512 {
9513         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9514 }
9515
9516 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9517                                             u16 error_code)
9518 {
9519         bool inequality, bit;
9520
9521         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9522         inequality =
9523                 (error_code & vmcs12->page_fault_error_code_mask) !=
9524                  vmcs12->page_fault_error_code_match;
9525         return inequality ^ bit;
9526 }
9527
9528 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9529                 struct x86_exception *fault)
9530 {
9531         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9532
9533         WARN_ON(!is_guest_mode(vcpu));
9534
9535         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9536                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9537                                   vmcs_read32(VM_EXIT_INTR_INFO),
9538                                   vmcs_readl(EXIT_QUALIFICATION));
9539         else
9540                 kvm_inject_page_fault(vcpu, fault);
9541 }
9542
9543 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9544                                                struct vmcs12 *vmcs12);
9545
9546 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9547                                         struct vmcs12 *vmcs12)
9548 {
9549         struct vcpu_vmx *vmx = to_vmx(vcpu);
9550         u64 hpa;
9551
9552         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9553                 /*
9554                  * Translate L1 physical address to host physical
9555                  * address for vmcs02. Keep the page pinned, so this
9556                  * physical address remains valid. We keep a reference
9557                  * to it so we can release it later.
9558                  */
9559                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9560                         nested_release_page(vmx->nested.apic_access_page);
9561                 vmx->nested.apic_access_page =
9562                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9563                 /*
9564                  * If translation failed, no matter: This feature asks
9565                  * to exit when accessing the given address, and if it
9566                  * can never be accessed, this feature won't do
9567                  * anything anyway.
9568                  */
9569                 if (vmx->nested.apic_access_page) {
9570                         hpa = page_to_phys(vmx->nested.apic_access_page);
9571                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9572                 } else {
9573                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9574                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9575                 }
9576         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9577                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9578                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9579                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9580                 kvm_vcpu_reload_apic_access_page(vcpu);
9581         }
9582
9583         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9584                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9585                         nested_release_page(vmx->nested.virtual_apic_page);
9586                 vmx->nested.virtual_apic_page =
9587                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9588
9589                 /*
9590                  * If translation failed, VM entry will fail because
9591                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9592                  * Failing the vm entry is _not_ what the processor
9593                  * does but it's basically the only possibility we
9594                  * have.  We could still enter the guest if CR8 load
9595                  * exits are enabled, CR8 store exits are enabled, and
9596                  * virtualize APIC access is disabled; in this case
9597                  * the processor would never use the TPR shadow and we
9598                  * could simply clear the bit from the execution
9599                  * control.  But such a configuration is useless, so
9600                  * let's keep the code simple.
9601                  */
9602                 if (vmx->nested.virtual_apic_page) {
9603                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9604                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9605                 }
9606         }
9607
9608         if (nested_cpu_has_posted_intr(vmcs12)) {
9609                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9610                         kunmap(vmx->nested.pi_desc_page);
9611                         nested_release_page(vmx->nested.pi_desc_page);
9612                 }
9613                 vmx->nested.pi_desc_page =
9614                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9615                 vmx->nested.pi_desc =
9616                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9617                 if (!vmx->nested.pi_desc) {
9618                         nested_release_page_clean(vmx->nested.pi_desc_page);
9619                         return;
9620                 }
9621                 vmx->nested.pi_desc =
9622                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9623                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9624                         (PAGE_SIZE - 1)));
9625                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9626                         page_to_phys(vmx->nested.pi_desc_page) +
9627                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9628                         (PAGE_SIZE - 1)));
9629         }
9630         if (cpu_has_vmx_msr_bitmap() &&
9631             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9632             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9633                 ;
9634         else
9635                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9636                                 CPU_BASED_USE_MSR_BITMAPS);
9637 }
9638
9639 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9640 {
9641         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9642         struct vcpu_vmx *vmx = to_vmx(vcpu);
9643
9644         if (vcpu->arch.virtual_tsc_khz == 0)
9645                 return;
9646
9647         /* Make sure short timeouts reliably trigger an immediate vmexit.
9648          * hrtimer_start does not guarantee this. */
9649         if (preemption_timeout <= 1) {
9650                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9651                 return;
9652         }
9653
9654         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9655         preemption_timeout *= 1000000;
9656         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9657         hrtimer_start(&vmx->nested.preemption_timer,
9658                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9659 }
9660
9661 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9662                                                 struct vmcs12 *vmcs12)
9663 {
9664         int maxphyaddr;
9665         u64 addr;
9666
9667         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9668                 return 0;
9669
9670         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9671                 WARN_ON(1);
9672                 return -EINVAL;
9673         }
9674         maxphyaddr = cpuid_maxphyaddr(vcpu);
9675
9676         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9677            ((addr + PAGE_SIZE) >> maxphyaddr))
9678                 return -EINVAL;
9679
9680         return 0;
9681 }
9682
9683 /*
9684  * Merge L0's and L1's MSR bitmap, return false to indicate that
9685  * we do not use the hardware.
9686  */
9687 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9688                                                struct vmcs12 *vmcs12)
9689 {
9690         int msr;
9691         struct page *page;
9692         unsigned long *msr_bitmap_l1;
9693         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9694
9695         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9696         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9697                 return false;
9698
9699         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9700         if (!page)
9701                 return false;
9702         msr_bitmap_l1 = (unsigned long *)kmap(page);
9703
9704         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9705
9706         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9707                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9708                         for (msr = 0x800; msr <= 0x8ff; msr++)
9709                                 nested_vmx_disable_intercept_for_msr(
9710                                         msr_bitmap_l1, msr_bitmap_l0,
9711                                         msr, MSR_TYPE_R);
9712
9713                 nested_vmx_disable_intercept_for_msr(
9714                                 msr_bitmap_l1, msr_bitmap_l0,
9715                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9716                                 MSR_TYPE_R | MSR_TYPE_W);
9717
9718                 if (nested_cpu_has_vid(vmcs12)) {
9719                         nested_vmx_disable_intercept_for_msr(
9720                                 msr_bitmap_l1, msr_bitmap_l0,
9721                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9722                                 MSR_TYPE_W);
9723                         nested_vmx_disable_intercept_for_msr(
9724                                 msr_bitmap_l1, msr_bitmap_l0,
9725                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9726                                 MSR_TYPE_W);
9727                 }
9728         }
9729         kunmap(page);
9730         nested_release_page_clean(page);
9731
9732         return true;
9733 }
9734
9735 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9736                                            struct vmcs12 *vmcs12)
9737 {
9738         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9739             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9740             !nested_cpu_has_vid(vmcs12) &&
9741             !nested_cpu_has_posted_intr(vmcs12))
9742                 return 0;
9743
9744         /*
9745          * If virtualize x2apic mode is enabled,
9746          * virtualize apic access must be disabled.
9747          */
9748         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9749             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9750                 return -EINVAL;
9751
9752         /*
9753          * If virtual interrupt delivery is enabled,
9754          * we must exit on external interrupts.
9755          */
9756         if (nested_cpu_has_vid(vmcs12) &&
9757            !nested_exit_on_intr(vcpu))
9758                 return -EINVAL;
9759
9760         /*
9761          * bits 15:8 should be zero in posted_intr_nv,
9762          * the descriptor address has been already checked
9763          * in nested_get_vmcs12_pages.
9764          */
9765         if (nested_cpu_has_posted_intr(vmcs12) &&
9766            (!nested_cpu_has_vid(vmcs12) ||
9767             !nested_exit_intr_ack_set(vcpu) ||
9768             vmcs12->posted_intr_nv & 0xff00))
9769                 return -EINVAL;
9770
9771         /* tpr shadow is needed by all apicv features. */
9772         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9773                 return -EINVAL;
9774
9775         return 0;
9776 }
9777
9778 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9779                                        unsigned long count_field,
9780                                        unsigned long addr_field)
9781 {
9782         int maxphyaddr;
9783         u64 count, addr;
9784
9785         if (vmcs12_read_any(vcpu, count_field, &count) ||
9786             vmcs12_read_any(vcpu, addr_field, &addr)) {
9787                 WARN_ON(1);
9788                 return -EINVAL;
9789         }
9790         if (count == 0)
9791                 return 0;
9792         maxphyaddr = cpuid_maxphyaddr(vcpu);
9793         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9794             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9795                 pr_debug_ratelimited(
9796                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9797                         addr_field, maxphyaddr, count, addr);
9798                 return -EINVAL;
9799         }
9800         return 0;
9801 }
9802
9803 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9804                                                 struct vmcs12 *vmcs12)
9805 {
9806         if (vmcs12->vm_exit_msr_load_count == 0 &&
9807             vmcs12->vm_exit_msr_store_count == 0 &&
9808             vmcs12->vm_entry_msr_load_count == 0)
9809                 return 0; /* Fast path */
9810         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9811                                         VM_EXIT_MSR_LOAD_ADDR) ||
9812             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9813                                         VM_EXIT_MSR_STORE_ADDR) ||
9814             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9815                                         VM_ENTRY_MSR_LOAD_ADDR))
9816                 return -EINVAL;
9817         return 0;
9818 }
9819
9820 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9821                                        struct vmx_msr_entry *e)
9822 {
9823         /* x2APIC MSR accesses are not allowed */
9824         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9825                 return -EINVAL;
9826         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9827             e->index == MSR_IA32_UCODE_REV)
9828                 return -EINVAL;
9829         if (e->reserved != 0)
9830                 return -EINVAL;
9831         return 0;
9832 }
9833
9834 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9835                                      struct vmx_msr_entry *e)
9836 {
9837         if (e->index == MSR_FS_BASE ||
9838             e->index == MSR_GS_BASE ||
9839             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9840             nested_vmx_msr_check_common(vcpu, e))
9841                 return -EINVAL;
9842         return 0;
9843 }
9844
9845 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9846                                       struct vmx_msr_entry *e)
9847 {
9848         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9849             nested_vmx_msr_check_common(vcpu, e))
9850                 return -EINVAL;
9851         return 0;
9852 }
9853
9854 /*
9855  * Load guest's/host's msr at nested entry/exit.
9856  * return 0 for success, entry index for failure.
9857  */
9858 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9859 {
9860         u32 i;
9861         struct vmx_msr_entry e;
9862         struct msr_data msr;
9863
9864         msr.host_initiated = false;
9865         for (i = 0; i < count; i++) {
9866                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9867                                         &e, sizeof(e))) {
9868                         pr_debug_ratelimited(
9869                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9870                                 __func__, i, gpa + i * sizeof(e));
9871                         goto fail;
9872                 }
9873                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9874                         pr_debug_ratelimited(
9875                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9876                                 __func__, i, e.index, e.reserved);
9877                         goto fail;
9878                 }
9879                 msr.index = e.index;
9880                 msr.data = e.value;
9881                 if (kvm_set_msr(vcpu, &msr)) {
9882                         pr_debug_ratelimited(
9883                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9884                                 __func__, i, e.index, e.value);
9885                         goto fail;
9886                 }
9887         }
9888         return 0;
9889 fail:
9890         return i + 1;
9891 }
9892
9893 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9894 {
9895         u32 i;
9896         struct vmx_msr_entry e;
9897
9898         for (i = 0; i < count; i++) {
9899                 struct msr_data msr_info;
9900                 if (kvm_vcpu_read_guest(vcpu,
9901                                         gpa + i * sizeof(e),
9902                                         &e, 2 * sizeof(u32))) {
9903                         pr_debug_ratelimited(
9904                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9905                                 __func__, i, gpa + i * sizeof(e));
9906                         return -EINVAL;
9907                 }
9908                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9909                         pr_debug_ratelimited(
9910                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9911                                 __func__, i, e.index, e.reserved);
9912                         return -EINVAL;
9913                 }
9914                 msr_info.host_initiated = false;
9915                 msr_info.index = e.index;
9916                 if (kvm_get_msr(vcpu, &msr_info)) {
9917                         pr_debug_ratelimited(
9918                                 "%s cannot read MSR (%u, 0x%x)\n",
9919                                 __func__, i, e.index);
9920                         return -EINVAL;
9921                 }
9922                 if (kvm_vcpu_write_guest(vcpu,
9923                                          gpa + i * sizeof(e) +
9924                                              offsetof(struct vmx_msr_entry, value),
9925                                          &msr_info.data, sizeof(msr_info.data))) {
9926                         pr_debug_ratelimited(
9927                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9928                                 __func__, i, e.index, msr_info.data);
9929                         return -EINVAL;
9930                 }
9931         }
9932         return 0;
9933 }
9934
9935 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9936 {
9937         unsigned long invalid_mask;
9938
9939         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9940         return (val & invalid_mask) == 0;
9941 }
9942
9943 /*
9944  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9945  * emulating VM entry into a guest with EPT enabled.
9946  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9947  * is assigned to entry_failure_code on failure.
9948  */
9949 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9950                                u32 *entry_failure_code)
9951 {
9952         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9953                 if (!nested_cr3_valid(vcpu, cr3)) {
9954                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9955                         return 1;
9956                 }
9957
9958                 /*
9959                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9960                  * must not be dereferenced.
9961                  */
9962                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9963                     !nested_ept) {
9964                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9965                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9966                                 return 1;
9967                         }
9968                 }
9969
9970                 vcpu->arch.cr3 = cr3;
9971                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9972         }
9973
9974         kvm_mmu_reset_context(vcpu);
9975         return 0;
9976 }
9977
9978 /*
9979  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9980  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9981  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9982  * guest in a way that will both be appropriate to L1's requests, and our
9983  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9984  * function also has additional necessary side-effects, like setting various
9985  * vcpu->arch fields.
9986  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9987  * is assigned to entry_failure_code on failure.
9988  */
9989 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9990                           bool from_vmentry, u32 *entry_failure_code)
9991 {
9992         struct vcpu_vmx *vmx = to_vmx(vcpu);
9993         u32 exec_control;
9994
9995         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9996         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9997         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9998         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9999         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10000         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10001         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10002         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10003         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10004         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10005         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10006         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10007         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10008         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10009         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10010         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10011         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10012         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10013         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10014         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10015         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10016         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10017         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10018         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10019         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10020         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10021         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10022         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10023         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10024         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10025         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10026         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10027         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10028         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10029         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10030         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10031
10032         if (from_vmentry &&
10033             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10034                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10035                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10036         } else {
10037                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10038                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10039         }
10040         if (from_vmentry) {
10041                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10042                              vmcs12->vm_entry_intr_info_field);
10043                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10044                              vmcs12->vm_entry_exception_error_code);
10045                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10046                              vmcs12->vm_entry_instruction_len);
10047                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10048                              vmcs12->guest_interruptibility_info);
10049         } else {
10050                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10051         }
10052         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10053         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10054         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10055                 vmcs12->guest_pending_dbg_exceptions);
10056         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10057         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10058
10059         if (nested_cpu_has_xsaves(vmcs12))
10060                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10061         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10062
10063         exec_control = vmcs12->pin_based_vm_exec_control;
10064
10065         /* Preemption timer setting is only taken from vmcs01.  */
10066         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10067         exec_control |= vmcs_config.pin_based_exec_ctrl;
10068         if (vmx->hv_deadline_tsc == -1)
10069                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10070
10071         /* Posted interrupts setting is only taken from vmcs12.  */
10072         if (nested_cpu_has_posted_intr(vmcs12)) {
10073                 /*
10074                  * Note that we use L0's vector here and in
10075                  * vmx_deliver_nested_posted_interrupt.
10076                  */
10077                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10078                 vmx->nested.pi_pending = false;
10079                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10080         } else {
10081                 exec_control &= ~PIN_BASED_POSTED_INTR;
10082         }
10083
10084         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10085
10086         vmx->nested.preemption_timer_expired = false;
10087         if (nested_cpu_has_preemption_timer(vmcs12))
10088                 vmx_start_preemption_timer(vcpu);
10089
10090         /*
10091          * Whether page-faults are trapped is determined by a combination of
10092          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10093          * If enable_ept, L0 doesn't care about page faults and we should
10094          * set all of these to L1's desires. However, if !enable_ept, L0 does
10095          * care about (at least some) page faults, and because it is not easy
10096          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10097          * to exit on each and every L2 page fault. This is done by setting
10098          * MASK=MATCH=0 and (see below) EB.PF=1.
10099          * Note that below we don't need special code to set EB.PF beyond the
10100          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10101          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10102          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10103          *
10104          * A problem with this approach (when !enable_ept) is that L1 may be
10105          * injected with more page faults than it asked for. This could have
10106          * caused problems, but in practice existing hypervisors don't care.
10107          * To fix this, we will need to emulate the PFEC checking (on the L1
10108          * page tables), using walk_addr(), when injecting PFs to L1.
10109          */
10110         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10111                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10112         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10113                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10114
10115         if (cpu_has_secondary_exec_ctrls()) {
10116                 exec_control = vmx_secondary_exec_control(vmx);
10117
10118                 /* Take the following fields only from vmcs12 */
10119                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10120                                   SECONDARY_EXEC_RDTSCP |
10121                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10122                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10123                 if (nested_cpu_has(vmcs12,
10124                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10125                         exec_control |= vmcs12->secondary_vm_exec_control;
10126
10127                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10128                         vmcs_write64(EOI_EXIT_BITMAP0,
10129                                 vmcs12->eoi_exit_bitmap0);
10130                         vmcs_write64(EOI_EXIT_BITMAP1,
10131                                 vmcs12->eoi_exit_bitmap1);
10132                         vmcs_write64(EOI_EXIT_BITMAP2,
10133                                 vmcs12->eoi_exit_bitmap2);
10134                         vmcs_write64(EOI_EXIT_BITMAP3,
10135                                 vmcs12->eoi_exit_bitmap3);
10136                         vmcs_write16(GUEST_INTR_STATUS,
10137                                 vmcs12->guest_intr_status);
10138                 }
10139
10140                 /*
10141                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10142                  * nested_get_vmcs12_pages will either fix it up or
10143                  * remove the VM execution control.
10144                  */
10145                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10146                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10147
10148                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10149         }
10150
10151
10152         /*
10153          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10154          * Some constant fields are set here by vmx_set_constant_host_state().
10155          * Other fields are different per CPU, and will be set later when
10156          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10157          */
10158         vmx_set_constant_host_state(vmx);
10159
10160         /*
10161          * Set the MSR load/store lists to match L0's settings.
10162          */
10163         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10164         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10165         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10166         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10167         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10168
10169         /*
10170          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10171          * entry, but only if the current (host) sp changed from the value
10172          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10173          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10174          * here we just force the write to happen on entry.
10175          */
10176         vmx->host_rsp = 0;
10177
10178         exec_control = vmx_exec_control(vmx); /* L0's desires */
10179         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10180         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10181         exec_control &= ~CPU_BASED_TPR_SHADOW;
10182         exec_control |= vmcs12->cpu_based_vm_exec_control;
10183
10184         /*
10185          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10186          * nested_get_vmcs12_pages can't fix it up, the illegal value
10187          * will result in a VM entry failure.
10188          */
10189         if (exec_control & CPU_BASED_TPR_SHADOW) {
10190                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10191                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10192         }
10193
10194         /*
10195          * Merging of IO bitmap not currently supported.
10196          * Rather, exit every time.
10197          */
10198         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10199         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10200
10201         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10202
10203         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10204          * bitwise-or of what L1 wants to trap for L2, and what we want to
10205          * trap. Note that CR0.TS also needs updating - we do this later.
10206          */
10207         update_exception_bitmap(vcpu);
10208         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10209         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10210
10211         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10212          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10213          * bits are further modified by vmx_set_efer() below.
10214          */
10215         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10216
10217         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10218          * emulated by vmx_set_efer(), below.
10219          */
10220         vm_entry_controls_init(vmx,
10221                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10222                         ~VM_ENTRY_IA32E_MODE) |
10223                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10224
10225         if (from_vmentry &&
10226             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10227                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10228                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10229         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10230                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10231         }
10232
10233         set_cr4_guest_host_mask(vmx);
10234
10235         if (from_vmentry &&
10236             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10237                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10238
10239         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10240                 vmcs_write64(TSC_OFFSET,
10241                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10242         else
10243                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10244         if (kvm_has_tsc_control)
10245                 decache_tsc_multiplier(vmx);
10246
10247         if (enable_vpid) {
10248                 /*
10249                  * There is no direct mapping between vpid02 and vpid12, the
10250                  * vpid02 is per-vCPU for L0 and reused while the value of
10251                  * vpid12 is changed w/ one invvpid during nested vmentry.
10252                  * The vpid12 is allocated by L1 for L2, so it will not
10253                  * influence global bitmap(for vpid01 and vpid02 allocation)
10254                  * even if spawn a lot of nested vCPUs.
10255                  */
10256                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10257                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10258                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10259                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10260                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10261                         }
10262                 } else {
10263                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10264                         vmx_flush_tlb(vcpu);
10265                 }
10266
10267         }
10268
10269         if (enable_pml) {
10270                 /*
10271                  * Conceptually we want to copy the PML address and index from
10272                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10273                  * since we always flush the log on each vmexit, this happens
10274                  * to be equivalent to simply resetting the fields in vmcs02.
10275                  */
10276                 ASSERT(vmx->pml_pg);
10277                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10278                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10279         }
10280
10281         if (nested_cpu_has_ept(vmcs12)) {
10282                 kvm_mmu_unload(vcpu);
10283                 nested_ept_init_mmu_context(vcpu);
10284         } else if (nested_cpu_has2(vmcs12,
10285                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10286                 vmx_flush_tlb_ept_only(vcpu);
10287         }
10288
10289         /*
10290          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10291          * bits which we consider mandatory enabled.
10292          * The CR0_READ_SHADOW is what L2 should have expected to read given
10293          * the specifications by L1; It's not enough to take
10294          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10295          * have more bits than L1 expected.
10296          */
10297         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10298         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10299
10300         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10301         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10302
10303         if (from_vmentry &&
10304             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10305                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10306         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10307                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10308         else
10309                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10310         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10311         vmx_set_efer(vcpu, vcpu->arch.efer);
10312
10313         /* Shadow page tables on either EPT or shadow page tables. */
10314         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10315                                 entry_failure_code))
10316                 return 1;
10317
10318         if (!enable_ept)
10319                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10320
10321         /*
10322          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10323          */
10324         if (enable_ept) {
10325                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10326                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10327                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10328                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10329         }
10330
10331         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10332         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10333         return 0;
10334 }
10335
10336 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10337 {
10338         struct vcpu_vmx *vmx = to_vmx(vcpu);
10339
10340         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10341             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10342                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10343
10344         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10345                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10346
10347         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10348                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10349
10350         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10351                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10352
10353         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10354                                 vmx->nested.nested_vmx_procbased_ctls_low,
10355                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10356             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10357                                 vmx->nested.nested_vmx_secondary_ctls_low,
10358                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10359             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10360                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10361                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10362             !vmx_control_verify(vmcs12->vm_exit_controls,
10363                                 vmx->nested.nested_vmx_exit_ctls_low,
10364                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10365             !vmx_control_verify(vmcs12->vm_entry_controls,
10366                                 vmx->nested.nested_vmx_entry_ctls_low,
10367                                 vmx->nested.nested_vmx_entry_ctls_high))
10368                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10369
10370         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10371             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10372             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10373                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10374
10375         return 0;
10376 }
10377
10378 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10379                                   u32 *exit_qual)
10380 {
10381         bool ia32e;
10382
10383         *exit_qual = ENTRY_FAIL_DEFAULT;
10384
10385         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10386             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10387                 return 1;
10388
10389         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10390             vmcs12->vmcs_link_pointer != -1ull) {
10391                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10392                 return 1;
10393         }
10394
10395         /*
10396          * If the load IA32_EFER VM-entry control is 1, the following checks
10397          * are performed on the field for the IA32_EFER MSR:
10398          * - Bits reserved in the IA32_EFER MSR must be 0.
10399          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10400          *   the IA-32e mode guest VM-exit control. It must also be identical
10401          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10402          *   CR0.PG) is 1.
10403          */
10404         if (to_vmx(vcpu)->nested.nested_run_pending &&
10405             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10406                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10407                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10408                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10409                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10410                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10411                         return 1;
10412         }
10413
10414         /*
10415          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10416          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10417          * the values of the LMA and LME bits in the field must each be that of
10418          * the host address-space size VM-exit control.
10419          */
10420         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10421                 ia32e = (vmcs12->vm_exit_controls &
10422                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10423                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10424                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10425                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10426                         return 1;
10427         }
10428
10429         return 0;
10430 }
10431
10432 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10433 {
10434         struct vcpu_vmx *vmx = to_vmx(vcpu);
10435         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10436         struct loaded_vmcs *vmcs02;
10437         int cpu;
10438         u32 msr_entry_idx;
10439         u32 exit_qual;
10440
10441         vmcs02 = nested_get_current_vmcs02(vmx);
10442         if (!vmcs02)
10443                 return -ENOMEM;
10444
10445         enter_guest_mode(vcpu);
10446
10447         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10448                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10449
10450         cpu = get_cpu();
10451         vmx->loaded_vmcs = vmcs02;
10452         vmx_vcpu_put(vcpu);
10453         vmx_vcpu_load(vcpu, cpu);
10454         vcpu->cpu = cpu;
10455         put_cpu();
10456
10457         vmx_segment_cache_clear(vmx);
10458
10459         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10460                 leave_guest_mode(vcpu);
10461                 vmx_load_vmcs01(vcpu);
10462                 nested_vmx_entry_failure(vcpu, vmcs12,
10463                                          EXIT_REASON_INVALID_STATE, exit_qual);
10464                 return 1;
10465         }
10466
10467         nested_get_vmcs12_pages(vcpu, vmcs12);
10468
10469         msr_entry_idx = nested_vmx_load_msr(vcpu,
10470                                             vmcs12->vm_entry_msr_load_addr,
10471                                             vmcs12->vm_entry_msr_load_count);
10472         if (msr_entry_idx) {
10473                 leave_guest_mode(vcpu);
10474                 vmx_load_vmcs01(vcpu);
10475                 nested_vmx_entry_failure(vcpu, vmcs12,
10476                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10477                 return 1;
10478         }
10479
10480         vmcs12->launch_state = 1;
10481
10482         /*
10483          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10484          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10485          * returned as far as L1 is concerned. It will only return (and set
10486          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10487          */
10488         return 0;
10489 }
10490
10491 /*
10492  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10493  * for running an L2 nested guest.
10494  */
10495 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10496 {
10497         struct vmcs12 *vmcs12;
10498         struct vcpu_vmx *vmx = to_vmx(vcpu);
10499         u32 exit_qual;
10500         int ret;
10501
10502         if (!nested_vmx_check_permission(vcpu))
10503                 return 1;
10504
10505         if (!nested_vmx_check_vmcs12(vcpu))
10506                 goto out;
10507
10508         vmcs12 = get_vmcs12(vcpu);
10509
10510         if (enable_shadow_vmcs)
10511                 copy_shadow_to_vmcs12(vmx);
10512
10513         /*
10514          * The nested entry process starts with enforcing various prerequisites
10515          * on vmcs12 as required by the Intel SDM, and act appropriately when
10516          * they fail: As the SDM explains, some conditions should cause the
10517          * instruction to fail, while others will cause the instruction to seem
10518          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10519          * To speed up the normal (success) code path, we should avoid checking
10520          * for misconfigurations which will anyway be caught by the processor
10521          * when using the merged vmcs02.
10522          */
10523         if (vmcs12->launch_state == launch) {
10524                 nested_vmx_failValid(vcpu,
10525                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10526                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10527                 goto out;
10528         }
10529
10530         ret = check_vmentry_prereqs(vcpu, vmcs12);
10531         if (ret) {
10532                 nested_vmx_failValid(vcpu, ret);
10533                 goto out;
10534         }
10535
10536         /*
10537          * After this point, the trap flag no longer triggers a singlestep trap
10538          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10539          * This is not 100% correct; for performance reasons, we delegate most
10540          * of the checks on host state to the processor.  If those fail,
10541          * the singlestep trap is missed.
10542          */
10543         skip_emulated_instruction(vcpu);
10544
10545         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10546         if (ret) {
10547                 nested_vmx_entry_failure(vcpu, vmcs12,
10548                                          EXIT_REASON_INVALID_STATE, exit_qual);
10549                 return 1;
10550         }
10551
10552         /*
10553          * We're finally done with prerequisite checking, and can start with
10554          * the nested entry.
10555          */
10556
10557         ret = enter_vmx_non_root_mode(vcpu, true);
10558         if (ret)
10559                 return ret;
10560
10561         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10562                 return kvm_vcpu_halt(vcpu);
10563
10564         vmx->nested.nested_run_pending = 1;
10565
10566         return 1;
10567
10568 out:
10569         return kvm_skip_emulated_instruction(vcpu);
10570 }
10571
10572 /*
10573  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10574  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10575  * This function returns the new value we should put in vmcs12.guest_cr0.
10576  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10577  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10578  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10579  *     didn't trap the bit, because if L1 did, so would L0).
10580  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10581  *     been modified by L2, and L1 knows it. So just leave the old value of
10582  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10583  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10584  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10585  *     changed these bits, and therefore they need to be updated, but L0
10586  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10587  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10588  */
10589 static inline unsigned long
10590 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10591 {
10592         return
10593         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10594         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10595         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10596                         vcpu->arch.cr0_guest_owned_bits));
10597 }
10598
10599 static inline unsigned long
10600 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10601 {
10602         return
10603         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10604         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10605         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10606                         vcpu->arch.cr4_guest_owned_bits));
10607 }
10608
10609 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10610                                        struct vmcs12 *vmcs12)
10611 {
10612         u32 idt_vectoring;
10613         unsigned int nr;
10614
10615         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10616                 nr = vcpu->arch.exception.nr;
10617                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10618
10619                 if (kvm_exception_is_soft(nr)) {
10620                         vmcs12->vm_exit_instruction_len =
10621                                 vcpu->arch.event_exit_inst_len;
10622                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10623                 } else
10624                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10625
10626                 if (vcpu->arch.exception.has_error_code) {
10627                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10628                         vmcs12->idt_vectoring_error_code =
10629                                 vcpu->arch.exception.error_code;
10630                 }
10631
10632                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10633         } else if (vcpu->arch.nmi_injected) {
10634                 vmcs12->idt_vectoring_info_field =
10635                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10636         } else if (vcpu->arch.interrupt.pending) {
10637                 nr = vcpu->arch.interrupt.nr;
10638                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10639
10640                 if (vcpu->arch.interrupt.soft) {
10641                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10642                         vmcs12->vm_entry_instruction_len =
10643                                 vcpu->arch.event_exit_inst_len;
10644                 } else
10645                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10646
10647                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10648         }
10649 }
10650
10651 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10652 {
10653         struct vcpu_vmx *vmx = to_vmx(vcpu);
10654
10655         if (vcpu->arch.exception.pending ||
10656                 vcpu->arch.nmi_injected ||
10657                 vcpu->arch.interrupt.pending)
10658                 return -EBUSY;
10659
10660         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10661             vmx->nested.preemption_timer_expired) {
10662                 if (vmx->nested.nested_run_pending)
10663                         return -EBUSY;
10664                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10665                 return 0;
10666         }
10667
10668         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10669                 if (vmx->nested.nested_run_pending)
10670                         return -EBUSY;
10671                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10672                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10673                                   INTR_INFO_VALID_MASK, 0);
10674                 /*
10675                  * The NMI-triggered VM exit counts as injection:
10676                  * clear this one and block further NMIs.
10677                  */
10678                 vcpu->arch.nmi_pending = 0;
10679                 vmx_set_nmi_mask(vcpu, true);
10680                 return 0;
10681         }
10682
10683         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10684             nested_exit_on_intr(vcpu)) {
10685                 if (vmx->nested.nested_run_pending)
10686                         return -EBUSY;
10687                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10688                 return 0;
10689         }
10690
10691         vmx_complete_nested_posted_interrupt(vcpu);
10692         return 0;
10693 }
10694
10695 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10696 {
10697         ktime_t remaining =
10698                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10699         u64 value;
10700
10701         if (ktime_to_ns(remaining) <= 0)
10702                 return 0;
10703
10704         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10705         do_div(value, 1000000);
10706         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10707 }
10708
10709 /*
10710  * Update the guest state fields of vmcs12 to reflect changes that
10711  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10712  * VM-entry controls is also updated, since this is really a guest
10713  * state bit.)
10714  */
10715 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10716 {
10717         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10718         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10719
10720         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10721         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10722         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10723
10724         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10725         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10726         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10727         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10728         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10729         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10730         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10731         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10732         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10733         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10734         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10735         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10736         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10737         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10738         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10739         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10740         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10741         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10742         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10743         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10744         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10745         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10746         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10747         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10748         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10749         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10750         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10751         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10752         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10753         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10754         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10755         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10756         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10757         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10758         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10759         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10760
10761         vmcs12->guest_interruptibility_info =
10762                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10763         vmcs12->guest_pending_dbg_exceptions =
10764                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10765         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10766                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10767         else
10768                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10769
10770         if (nested_cpu_has_preemption_timer(vmcs12)) {
10771                 if (vmcs12->vm_exit_controls &
10772                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10773                         vmcs12->vmx_preemption_timer_value =
10774                                 vmx_get_preemption_timer_value(vcpu);
10775                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10776         }
10777
10778         /*
10779          * In some cases (usually, nested EPT), L2 is allowed to change its
10780          * own CR3 without exiting. If it has changed it, we must keep it.
10781          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10782          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10783          *
10784          * Additionally, restore L2's PDPTR to vmcs12.
10785          */
10786         if (enable_ept) {
10787                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10788                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10789                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10790                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10791                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10792         }
10793
10794         if (nested_cpu_has_ept(vmcs12))
10795                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10796
10797         if (nested_cpu_has_vid(vmcs12))
10798                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10799
10800         vmcs12->vm_entry_controls =
10801                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10802                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10803
10804         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10805                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10806                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10807         }
10808
10809         /* TODO: These cannot have changed unless we have MSR bitmaps and
10810          * the relevant bit asks not to trap the change */
10811         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10812                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10813         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10814                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10815         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10816         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10817         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10818         if (kvm_mpx_supported())
10819                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10820         if (nested_cpu_has_xsaves(vmcs12))
10821                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10822 }
10823
10824 /*
10825  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10826  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10827  * and this function updates it to reflect the changes to the guest state while
10828  * L2 was running (and perhaps made some exits which were handled directly by L0
10829  * without going back to L1), and to reflect the exit reason.
10830  * Note that we do not have to copy here all VMCS fields, just those that
10831  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10832  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10833  * which already writes to vmcs12 directly.
10834  */
10835 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10836                            u32 exit_reason, u32 exit_intr_info,
10837                            unsigned long exit_qualification)
10838 {
10839         /* update guest state fields: */
10840         sync_vmcs12(vcpu, vmcs12);
10841
10842         /* update exit information fields: */
10843
10844         vmcs12->vm_exit_reason = exit_reason;
10845         vmcs12->exit_qualification = exit_qualification;
10846
10847         vmcs12->vm_exit_intr_info = exit_intr_info;
10848         if ((vmcs12->vm_exit_intr_info &
10849              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10850             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10851                 vmcs12->vm_exit_intr_error_code =
10852                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10853         vmcs12->idt_vectoring_info_field = 0;
10854         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10855         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10856
10857         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10858                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10859                  * instead of reading the real value. */
10860                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10861
10862                 /*
10863                  * Transfer the event that L0 or L1 may wanted to inject into
10864                  * L2 to IDT_VECTORING_INFO_FIELD.
10865                  */
10866                 vmcs12_save_pending_event(vcpu, vmcs12);
10867         }
10868
10869         /*
10870          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10871          * preserved above and would only end up incorrectly in L1.
10872          */
10873         vcpu->arch.nmi_injected = false;
10874         kvm_clear_exception_queue(vcpu);
10875         kvm_clear_interrupt_queue(vcpu);
10876 }
10877
10878 /*
10879  * A part of what we need to when the nested L2 guest exits and we want to
10880  * run its L1 parent, is to reset L1's guest state to the host state specified
10881  * in vmcs12.
10882  * This function is to be called not only on normal nested exit, but also on
10883  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10884  * Failures During or After Loading Guest State").
10885  * This function should be called when the active VMCS is L1's (vmcs01).
10886  */
10887 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10888                                    struct vmcs12 *vmcs12)
10889 {
10890         struct kvm_segment seg;
10891         u32 entry_failure_code;
10892
10893         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10894                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10895         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10896                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10897         else
10898                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10899         vmx_set_efer(vcpu, vcpu->arch.efer);
10900
10901         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10902         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10903         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10904         /*
10905          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10906          * actually changed, because vmx_set_cr0 refers to efer set above.
10907          *
10908          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10909          * (KVM doesn't change it);
10910          */
10911         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10912         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10913
10914         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10915         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10916         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10917
10918         nested_ept_uninit_mmu_context(vcpu);
10919
10920         /*
10921          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10922          * couldn't have changed.
10923          */
10924         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10925                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10926
10927         if (!enable_ept)
10928                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10929
10930         if (enable_vpid) {
10931                 /*
10932                  * Trivially support vpid by letting L2s share their parent
10933                  * L1's vpid. TODO: move to a more elaborate solution, giving
10934                  * each L2 its own vpid and exposing the vpid feature to L1.
10935                  */
10936                 vmx_flush_tlb(vcpu);
10937         }
10938
10939
10940         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10941         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10942         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10943         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10944         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10945
10946         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10947         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10948                 vmcs_write64(GUEST_BNDCFGS, 0);
10949
10950         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10951                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10952                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10953         }
10954         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10955                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10956                         vmcs12->host_ia32_perf_global_ctrl);
10957
10958         /* Set L1 segment info according to Intel SDM
10959             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10960         seg = (struct kvm_segment) {
10961                 .base = 0,
10962                 .limit = 0xFFFFFFFF,
10963                 .selector = vmcs12->host_cs_selector,
10964                 .type = 11,
10965                 .present = 1,
10966                 .s = 1,
10967                 .g = 1
10968         };
10969         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10970                 seg.l = 1;
10971         else
10972                 seg.db = 1;
10973         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10974         seg = (struct kvm_segment) {
10975                 .base = 0,
10976                 .limit = 0xFFFFFFFF,
10977                 .type = 3,
10978                 .present = 1,
10979                 .s = 1,
10980                 .db = 1,
10981                 .g = 1
10982         };
10983         seg.selector = vmcs12->host_ds_selector;
10984         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10985         seg.selector = vmcs12->host_es_selector;
10986         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10987         seg.selector = vmcs12->host_ss_selector;
10988         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10989         seg.selector = vmcs12->host_fs_selector;
10990         seg.base = vmcs12->host_fs_base;
10991         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10992         seg.selector = vmcs12->host_gs_selector;
10993         seg.base = vmcs12->host_gs_base;
10994         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10995         seg = (struct kvm_segment) {
10996                 .base = vmcs12->host_tr_base,
10997                 .limit = 0x67,
10998                 .selector = vmcs12->host_tr_selector,
10999                 .type = 11,
11000                 .present = 1
11001         };
11002         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11003
11004         kvm_set_dr(vcpu, 7, 0x400);
11005         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11006
11007         if (cpu_has_vmx_msr_bitmap())
11008                 vmx_set_msr_bitmap(vcpu);
11009
11010         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11011                                 vmcs12->vm_exit_msr_load_count))
11012                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11013 }
11014
11015 /*
11016  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11017  * and modify vmcs12 to make it see what it would expect to see there if
11018  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11019  */
11020 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11021                               u32 exit_intr_info,
11022                               unsigned long exit_qualification)
11023 {
11024         struct vcpu_vmx *vmx = to_vmx(vcpu);
11025         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11026         u32 vm_inst_error = 0;
11027
11028         /* trying to cancel vmlaunch/vmresume is a bug */
11029         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11030
11031         leave_guest_mode(vcpu);
11032         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11033                        exit_qualification);
11034
11035         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11036                                  vmcs12->vm_exit_msr_store_count))
11037                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11038
11039         if (unlikely(vmx->fail))
11040                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11041
11042         vmx_load_vmcs01(vcpu);
11043
11044         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11045             && nested_exit_intr_ack_set(vcpu)) {
11046                 int irq = kvm_cpu_get_interrupt(vcpu);
11047                 WARN_ON(irq < 0);
11048                 vmcs12->vm_exit_intr_info = irq |
11049                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11050         }
11051
11052         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11053                                        vmcs12->exit_qualification,
11054                                        vmcs12->idt_vectoring_info_field,
11055                                        vmcs12->vm_exit_intr_info,
11056                                        vmcs12->vm_exit_intr_error_code,
11057                                        KVM_ISA_VMX);
11058
11059         vm_entry_controls_reset_shadow(vmx);
11060         vm_exit_controls_reset_shadow(vmx);
11061         vmx_segment_cache_clear(vmx);
11062
11063         /* if no vmcs02 cache requested, remove the one we used */
11064         if (VMCS02_POOL_SIZE == 0)
11065                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11066
11067         load_vmcs12_host_state(vcpu, vmcs12);
11068
11069         /* Update any VMCS fields that might have changed while L2 ran */
11070         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11071         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11072         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11073         if (vmx->hv_deadline_tsc == -1)
11074                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11075                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11076         else
11077                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11078                               PIN_BASED_VMX_PREEMPTION_TIMER);
11079         if (kvm_has_tsc_control)
11080                 decache_tsc_multiplier(vmx);
11081
11082         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11083                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11084                 vmx_set_virtual_x2apic_mode(vcpu,
11085                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11086         } else if (!nested_cpu_has_ept(vmcs12) &&
11087                    nested_cpu_has2(vmcs12,
11088                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11089                 vmx_flush_tlb_ept_only(vcpu);
11090         }
11091
11092         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11093         vmx->host_rsp = 0;
11094
11095         /* Unpin physical memory we referred to in vmcs02 */
11096         if (vmx->nested.apic_access_page) {
11097                 nested_release_page(vmx->nested.apic_access_page);
11098                 vmx->nested.apic_access_page = NULL;
11099         }
11100         if (vmx->nested.virtual_apic_page) {
11101                 nested_release_page(vmx->nested.virtual_apic_page);
11102                 vmx->nested.virtual_apic_page = NULL;
11103         }
11104         if (vmx->nested.pi_desc_page) {
11105                 kunmap(vmx->nested.pi_desc_page);
11106                 nested_release_page(vmx->nested.pi_desc_page);
11107                 vmx->nested.pi_desc_page = NULL;
11108                 vmx->nested.pi_desc = NULL;
11109         }
11110
11111         /*
11112          * We are now running in L2, mmu_notifier will force to reload the
11113          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11114          */
11115         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11116
11117         /*
11118          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11119          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11120          * success or failure flag accordingly.
11121          */
11122         if (unlikely(vmx->fail)) {
11123                 vmx->fail = 0;
11124                 nested_vmx_failValid(vcpu, vm_inst_error);
11125         } else
11126                 nested_vmx_succeed(vcpu);
11127         if (enable_shadow_vmcs)
11128                 vmx->nested.sync_shadow_vmcs = true;
11129
11130         /* in case we halted in L2 */
11131         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11132 }
11133
11134 /*
11135  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11136  */
11137 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11138 {
11139         if (is_guest_mode(vcpu)) {
11140                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11141                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11142         }
11143         free_nested(to_vmx(vcpu));
11144 }
11145
11146 /*
11147  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11148  * 23.7 "VM-entry failures during or after loading guest state" (this also
11149  * lists the acceptable exit-reason and exit-qualification parameters).
11150  * It should only be called before L2 actually succeeded to run, and when
11151  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11152  */
11153 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11154                         struct vmcs12 *vmcs12,
11155                         u32 reason, unsigned long qualification)
11156 {
11157         load_vmcs12_host_state(vcpu, vmcs12);
11158         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11159         vmcs12->exit_qualification = qualification;
11160         nested_vmx_succeed(vcpu);
11161         if (enable_shadow_vmcs)
11162                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11163 }
11164
11165 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11166                                struct x86_instruction_info *info,
11167                                enum x86_intercept_stage stage)
11168 {
11169         return X86EMUL_CONTINUE;
11170 }
11171
11172 #ifdef CONFIG_X86_64
11173 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11174 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11175                                   u64 divisor, u64 *result)
11176 {
11177         u64 low = a << shift, high = a >> (64 - shift);
11178
11179         /* To avoid the overflow on divq */
11180         if (high >= divisor)
11181                 return 1;
11182
11183         /* Low hold the result, high hold rem which is discarded */
11184         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11185             "rm" (divisor), "0" (low), "1" (high));
11186         *result = low;
11187
11188         return 0;
11189 }
11190
11191 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11192 {
11193         struct vcpu_vmx *vmx = to_vmx(vcpu);
11194         u64 tscl = rdtsc();
11195         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11196         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11197
11198         /* Convert to host delta tsc if tsc scaling is enabled */
11199         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11200                         u64_shl_div_u64(delta_tsc,
11201                                 kvm_tsc_scaling_ratio_frac_bits,
11202                                 vcpu->arch.tsc_scaling_ratio,
11203                                 &delta_tsc))
11204                 return -ERANGE;
11205
11206         /*
11207          * If the delta tsc can't fit in the 32 bit after the multi shift,
11208          * we can't use the preemption timer.
11209          * It's possible that it fits on later vmentries, but checking
11210          * on every vmentry is costly so we just use an hrtimer.
11211          */
11212         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11213                 return -ERANGE;
11214
11215         vmx->hv_deadline_tsc = tscl + delta_tsc;
11216         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11217                         PIN_BASED_VMX_PREEMPTION_TIMER);
11218         return 0;
11219 }
11220
11221 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11222 {
11223         struct vcpu_vmx *vmx = to_vmx(vcpu);
11224         vmx->hv_deadline_tsc = -1;
11225         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11226                         PIN_BASED_VMX_PREEMPTION_TIMER);
11227 }
11228 #endif
11229
11230 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11231 {
11232         if (ple_gap)
11233                 shrink_ple_window(vcpu);
11234 }
11235
11236 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11237                                      struct kvm_memory_slot *slot)
11238 {
11239         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11240         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11241 }
11242
11243 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11244                                        struct kvm_memory_slot *slot)
11245 {
11246         kvm_mmu_slot_set_dirty(kvm, slot);
11247 }
11248
11249 static void vmx_flush_log_dirty(struct kvm *kvm)
11250 {
11251         kvm_flush_pml_buffers(kvm);
11252 }
11253
11254 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11255                                            struct kvm_memory_slot *memslot,
11256                                            gfn_t offset, unsigned long mask)
11257 {
11258         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11259 }
11260
11261 /*
11262  * This routine does the following things for vCPU which is going
11263  * to be blocked if VT-d PI is enabled.
11264  * - Store the vCPU to the wakeup list, so when interrupts happen
11265  *   we can find the right vCPU to wake up.
11266  * - Change the Posted-interrupt descriptor as below:
11267  *      'NDST' <-- vcpu->pre_pcpu
11268  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11269  * - If 'ON' is set during this process, which means at least one
11270  *   interrupt is posted for this vCPU, we cannot block it, in
11271  *   this case, return 1, otherwise, return 0.
11272  *
11273  */
11274 static int pi_pre_block(struct kvm_vcpu *vcpu)
11275 {
11276         unsigned long flags;
11277         unsigned int dest;
11278         struct pi_desc old, new;
11279         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11280
11281         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11282                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11283                 !kvm_vcpu_apicv_active(vcpu))
11284                 return 0;
11285
11286         vcpu->pre_pcpu = vcpu->cpu;
11287         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11288                           vcpu->pre_pcpu), flags);
11289         list_add_tail(&vcpu->blocked_vcpu_list,
11290                       &per_cpu(blocked_vcpu_on_cpu,
11291                       vcpu->pre_pcpu));
11292         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11293                                vcpu->pre_pcpu), flags);
11294
11295         do {
11296                 old.control = new.control = pi_desc->control;
11297
11298                 /*
11299                  * We should not block the vCPU if
11300                  * an interrupt is posted for it.
11301                  */
11302                 if (pi_test_on(pi_desc) == 1) {
11303                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11304                                           vcpu->pre_pcpu), flags);
11305                         list_del(&vcpu->blocked_vcpu_list);
11306                         spin_unlock_irqrestore(
11307                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11308                                         vcpu->pre_pcpu), flags);
11309                         vcpu->pre_pcpu = -1;
11310
11311                         return 1;
11312                 }
11313
11314                 WARN((pi_desc->sn == 1),
11315                      "Warning: SN field of posted-interrupts "
11316                      "is set before blocking\n");
11317
11318                 /*
11319                  * Since vCPU can be preempted during this process,
11320                  * vcpu->cpu could be different with pre_pcpu, we
11321                  * need to set pre_pcpu as the destination of wakeup
11322                  * notification event, then we can find the right vCPU
11323                  * to wakeup in wakeup handler if interrupts happen
11324                  * when the vCPU is in blocked state.
11325                  */
11326                 dest = cpu_physical_id(vcpu->pre_pcpu);
11327
11328                 if (x2apic_enabled())
11329                         new.ndst = dest;
11330                 else
11331                         new.ndst = (dest << 8) & 0xFF00;
11332
11333                 /* set 'NV' to 'wakeup vector' */
11334                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11335         } while (cmpxchg(&pi_desc->control, old.control,
11336                         new.control) != old.control);
11337
11338         return 0;
11339 }
11340
11341 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11342 {
11343         if (pi_pre_block(vcpu))
11344                 return 1;
11345
11346         if (kvm_lapic_hv_timer_in_use(vcpu))
11347                 kvm_lapic_switch_to_sw_timer(vcpu);
11348
11349         return 0;
11350 }
11351
11352 static void pi_post_block(struct kvm_vcpu *vcpu)
11353 {
11354         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11355         struct pi_desc old, new;
11356         unsigned int dest;
11357         unsigned long flags;
11358
11359         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11360                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11361                 !kvm_vcpu_apicv_active(vcpu))
11362                 return;
11363
11364         do {
11365                 old.control = new.control = pi_desc->control;
11366
11367                 dest = cpu_physical_id(vcpu->cpu);
11368
11369                 if (x2apic_enabled())
11370                         new.ndst = dest;
11371                 else
11372                         new.ndst = (dest << 8) & 0xFF00;
11373
11374                 /* Allow posting non-urgent interrupts */
11375                 new.sn = 0;
11376
11377                 /* set 'NV' to 'notification vector' */
11378                 new.nv = POSTED_INTR_VECTOR;
11379         } while (cmpxchg(&pi_desc->control, old.control,
11380                         new.control) != old.control);
11381
11382         if(vcpu->pre_pcpu != -1) {
11383                 spin_lock_irqsave(
11384                         &per_cpu(blocked_vcpu_on_cpu_lock,
11385                         vcpu->pre_pcpu), flags);
11386                 list_del(&vcpu->blocked_vcpu_list);
11387                 spin_unlock_irqrestore(
11388                         &per_cpu(blocked_vcpu_on_cpu_lock,
11389                         vcpu->pre_pcpu), flags);
11390                 vcpu->pre_pcpu = -1;
11391         }
11392 }
11393
11394 static void vmx_post_block(struct kvm_vcpu *vcpu)
11395 {
11396         if (kvm_x86_ops->set_hv_timer)
11397                 kvm_lapic_switch_to_hv_timer(vcpu);
11398
11399         pi_post_block(vcpu);
11400 }
11401
11402 /*
11403  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11404  *
11405  * @kvm: kvm
11406  * @host_irq: host irq of the interrupt
11407  * @guest_irq: gsi of the interrupt
11408  * @set: set or unset PI
11409  * returns 0 on success, < 0 on failure
11410  */
11411 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11412                               uint32_t guest_irq, bool set)
11413 {
11414         struct kvm_kernel_irq_routing_entry *e;
11415         struct kvm_irq_routing_table *irq_rt;
11416         struct kvm_lapic_irq irq;
11417         struct kvm_vcpu *vcpu;
11418         struct vcpu_data vcpu_info;
11419         int idx, ret = -EINVAL;
11420
11421         if (!kvm_arch_has_assigned_device(kvm) ||
11422                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11423                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11424                 return 0;
11425
11426         idx = srcu_read_lock(&kvm->irq_srcu);
11427         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11428         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11429
11430         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11431                 if (e->type != KVM_IRQ_ROUTING_MSI)
11432                         continue;
11433                 /*
11434                  * VT-d PI cannot support posting multicast/broadcast
11435                  * interrupts to a vCPU, we still use interrupt remapping
11436                  * for these kind of interrupts.
11437                  *
11438                  * For lowest-priority interrupts, we only support
11439                  * those with single CPU as the destination, e.g. user
11440                  * configures the interrupts via /proc/irq or uses
11441                  * irqbalance to make the interrupts single-CPU.
11442                  *
11443                  * We will support full lowest-priority interrupt later.
11444                  */
11445
11446                 kvm_set_msi_irq(kvm, e, &irq);
11447                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11448                         /*
11449                          * Make sure the IRTE is in remapped mode if
11450                          * we don't handle it in posted mode.
11451                          */
11452                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11453                         if (ret < 0) {
11454                                 printk(KERN_INFO
11455                                    "failed to back to remapped mode, irq: %u\n",
11456                                    host_irq);
11457                                 goto out;
11458                         }
11459
11460                         continue;
11461                 }
11462
11463                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11464                 vcpu_info.vector = irq.vector;
11465
11466                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11467                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11468
11469                 if (set)
11470                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11471                 else {
11472                         /* suppress notification event before unposting */
11473                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11474                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11475                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11476                 }
11477
11478                 if (ret < 0) {
11479                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11480                                         __func__);
11481                         goto out;
11482                 }
11483         }
11484
11485         ret = 0;
11486 out:
11487         srcu_read_unlock(&kvm->irq_srcu, idx);
11488         return ret;
11489 }
11490
11491 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11492 {
11493         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11494                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11495                         FEATURE_CONTROL_LMCE;
11496         else
11497                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11498                         ~FEATURE_CONTROL_LMCE;
11499 }
11500
11501 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11502         .cpu_has_kvm_support = cpu_has_kvm_support,
11503         .disabled_by_bios = vmx_disabled_by_bios,
11504         .hardware_setup = hardware_setup,
11505         .hardware_unsetup = hardware_unsetup,
11506         .check_processor_compatibility = vmx_check_processor_compat,
11507         .hardware_enable = hardware_enable,
11508         .hardware_disable = hardware_disable,
11509         .cpu_has_accelerated_tpr = report_flexpriority,
11510         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11511
11512         .vcpu_create = vmx_create_vcpu,
11513         .vcpu_free = vmx_free_vcpu,
11514         .vcpu_reset = vmx_vcpu_reset,
11515
11516         .prepare_guest_switch = vmx_save_host_state,
11517         .vcpu_load = vmx_vcpu_load,
11518         .vcpu_put = vmx_vcpu_put,
11519
11520         .update_bp_intercept = update_exception_bitmap,
11521         .get_msr = vmx_get_msr,
11522         .set_msr = vmx_set_msr,
11523         .get_segment_base = vmx_get_segment_base,
11524         .get_segment = vmx_get_segment,
11525         .set_segment = vmx_set_segment,
11526         .get_cpl = vmx_get_cpl,
11527         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11528         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11529         .decache_cr3 = vmx_decache_cr3,
11530         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11531         .set_cr0 = vmx_set_cr0,
11532         .set_cr3 = vmx_set_cr3,
11533         .set_cr4 = vmx_set_cr4,
11534         .set_efer = vmx_set_efer,
11535         .get_idt = vmx_get_idt,
11536         .set_idt = vmx_set_idt,
11537         .get_gdt = vmx_get_gdt,
11538         .set_gdt = vmx_set_gdt,
11539         .get_dr6 = vmx_get_dr6,
11540         .set_dr6 = vmx_set_dr6,
11541         .set_dr7 = vmx_set_dr7,
11542         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11543         .cache_reg = vmx_cache_reg,
11544         .get_rflags = vmx_get_rflags,
11545         .set_rflags = vmx_set_rflags,
11546
11547         .get_pkru = vmx_get_pkru,
11548
11549         .tlb_flush = vmx_flush_tlb,
11550
11551         .run = vmx_vcpu_run,
11552         .handle_exit = vmx_handle_exit,
11553         .skip_emulated_instruction = skip_emulated_instruction,
11554         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11555         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11556         .patch_hypercall = vmx_patch_hypercall,
11557         .set_irq = vmx_inject_irq,
11558         .set_nmi = vmx_inject_nmi,
11559         .queue_exception = vmx_queue_exception,
11560         .cancel_injection = vmx_cancel_injection,
11561         .interrupt_allowed = vmx_interrupt_allowed,
11562         .nmi_allowed = vmx_nmi_allowed,
11563         .get_nmi_mask = vmx_get_nmi_mask,
11564         .set_nmi_mask = vmx_set_nmi_mask,
11565         .enable_nmi_window = enable_nmi_window,
11566         .enable_irq_window = enable_irq_window,
11567         .update_cr8_intercept = update_cr8_intercept,
11568         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11569         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11570         .get_enable_apicv = vmx_get_enable_apicv,
11571         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11572         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11573         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11574         .hwapic_irr_update = vmx_hwapic_irr_update,
11575         .hwapic_isr_update = vmx_hwapic_isr_update,
11576         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11577         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11578
11579         .set_tss_addr = vmx_set_tss_addr,
11580         .get_tdp_level = get_ept_level,
11581         .get_mt_mask = vmx_get_mt_mask,
11582
11583         .get_exit_info = vmx_get_exit_info,
11584
11585         .get_lpage_level = vmx_get_lpage_level,
11586
11587         .cpuid_update = vmx_cpuid_update,
11588
11589         .rdtscp_supported = vmx_rdtscp_supported,
11590         .invpcid_supported = vmx_invpcid_supported,
11591
11592         .set_supported_cpuid = vmx_set_supported_cpuid,
11593
11594         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11595
11596         .write_tsc_offset = vmx_write_tsc_offset,
11597
11598         .set_tdp_cr3 = vmx_set_cr3,
11599
11600         .check_intercept = vmx_check_intercept,
11601         .handle_external_intr = vmx_handle_external_intr,
11602         .mpx_supported = vmx_mpx_supported,
11603         .xsaves_supported = vmx_xsaves_supported,
11604
11605         .check_nested_events = vmx_check_nested_events,
11606
11607         .sched_in = vmx_sched_in,
11608
11609         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11610         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11611         .flush_log_dirty = vmx_flush_log_dirty,
11612         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11613
11614         .pre_block = vmx_pre_block,
11615         .post_block = vmx_post_block,
11616
11617         .pmu_ops = &intel_pmu_ops,
11618
11619         .update_pi_irte = vmx_update_pi_irte,
11620
11621 #ifdef CONFIG_X86_64
11622         .set_hv_timer = vmx_set_hv_timer,
11623         .cancel_hv_timer = vmx_cancel_hv_timer,
11624 #endif
11625
11626         .setup_mce = vmx_setup_mce,
11627 };
11628
11629 static int __init vmx_init(void)
11630 {
11631         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11632                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11633         if (r)
11634                 return r;
11635
11636 #ifdef CONFIG_KEXEC_CORE
11637         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11638                            crash_vmclear_local_loaded_vmcss);
11639 #endif
11640
11641         return 0;
11642 }
11643
11644 static void __exit vmx_exit(void)
11645 {
11646 #ifdef CONFIG_KEXEC_CORE
11647         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11648         synchronize_rcu();
11649 #endif
11650
11651         kvm_exit();
11652 }
11653
11654 module_init(vmx_init)
11655 module_exit(vmx_exit)