2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX),
66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
68 static bool __read_mostly enable_vpid = 1;
69 module_param_named(vpid, enable_vpid, bool, 0444);
71 static bool __read_mostly flexpriority_enabled = 1;
72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
74 static bool __read_mostly enable_ept = 1;
75 module_param_named(ept, enable_ept, bool, S_IRUGO);
77 static bool __read_mostly enable_unrestricted_guest = 1;
78 module_param_named(unrestricted_guest,
79 enable_unrestricted_guest, bool, S_IRUGO);
81 static bool __read_mostly enable_ept_ad_bits = 1;
82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
84 static bool __read_mostly emulate_invalid_guest_state = true;
85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
87 static bool __read_mostly fasteoi = 1;
88 module_param(fasteoi, bool, S_IRUGO);
90 static bool __read_mostly enable_apicv = 1;
91 module_param(enable_apicv, bool, S_IRUGO);
93 static bool __read_mostly enable_shadow_vmcs = 1;
94 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
100 static bool __read_mostly nested = 0;
101 module_param(nested, bool, S_IRUGO);
103 static u64 __read_mostly host_xss;
105 static bool __read_mostly enable_pml = 1;
106 module_param_named(pml, enable_pml, bool, S_IRUGO);
108 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
110 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
111 static int __read_mostly cpu_preemption_timer_multi;
112 static bool __read_mostly enable_preemption_timer = 1;
114 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
117 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
118 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
119 #define KVM_VM_CR0_ALWAYS_ON \
120 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
121 #define KVM_CR4_GUEST_OWNED_BITS \
122 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
123 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
125 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
126 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
128 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
130 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
133 * Hyper-V requires all of these, so mark them as supported even though
134 * they are just treated the same as all-context.
136 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
137 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
138 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
139 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
140 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
143 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
144 * ple_gap: upper bound on the amount of time between two successive
145 * executions of PAUSE in a loop. Also indicate if ple enabled.
146 * According to test, this time is usually smaller than 128 cycles.
147 * ple_window: upper bound on the amount of time a guest is allowed to execute
148 * in a PAUSE loop. Tests indicate that most spinlocks are held for
149 * less than 2^12 cycles
150 * Time is measured based on a counter that runs at the same rate as the TSC,
151 * refer SDM volume 3b section 21.6.13 & 22.1.3.
153 #define KVM_VMX_DEFAULT_PLE_GAP 128
154 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
155 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
156 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
158 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
160 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
161 module_param(ple_gap, int, S_IRUGO);
163 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
164 module_param(ple_window, int, S_IRUGO);
166 /* Default doubles per-vcpu window every exit. */
167 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
168 module_param(ple_window_grow, int, S_IRUGO);
170 /* Default resets per-vcpu window every exit to ple_window. */
171 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
172 module_param(ple_window_shrink, int, S_IRUGO);
174 /* Default is to compute the maximum so we can never overflow. */
175 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
176 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
177 module_param(ple_window_max, int, S_IRUGO);
179 extern const ulong vmx_return;
181 #define NR_AUTOLOAD_MSRS 8
182 #define VMCS02_POOL_SIZE 1
191 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
192 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
193 * loaded on this CPU (so we can clear them if the CPU goes down).
197 struct vmcs *shadow_vmcs;
200 struct list_head loaded_vmcss_on_cpu_link;
203 struct shared_msr_entry {
210 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
211 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
212 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
213 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
214 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
215 * More than one of these structures may exist, if L1 runs multiple L2 guests.
216 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
217 * underlying hardware which will be used to run L2.
218 * This structure is packed to ensure that its layout is identical across
219 * machines (necessary for live migration).
220 * If there are changes in this struct, VMCS12_REVISION must be changed.
222 typedef u64 natural_width;
223 struct __packed vmcs12 {
224 /* According to the Intel spec, a VMCS region must start with the
225 * following two fields. Then follow implementation-specific data.
230 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
231 u32 padding[7]; /* room for future expansion */
236 u64 vm_exit_msr_store_addr;
237 u64 vm_exit_msr_load_addr;
238 u64 vm_entry_msr_load_addr;
240 u64 virtual_apic_page_addr;
241 u64 apic_access_addr;
242 u64 posted_intr_desc_addr;
244 u64 eoi_exit_bitmap0;
245 u64 eoi_exit_bitmap1;
246 u64 eoi_exit_bitmap2;
247 u64 eoi_exit_bitmap3;
249 u64 guest_physical_address;
250 u64 vmcs_link_pointer;
251 u64 guest_ia32_debugctl;
254 u64 guest_ia32_perf_global_ctrl;
262 u64 host_ia32_perf_global_ctrl;
263 u64 padding64[8]; /* room for future expansion */
265 * To allow migration of L1 (complete with its L2 guests) between
266 * machines of different natural widths (32 or 64 bit), we cannot have
267 * unsigned long fields with no explict size. We use u64 (aliased
268 * natural_width) instead. Luckily, x86 is little-endian.
270 natural_width cr0_guest_host_mask;
271 natural_width cr4_guest_host_mask;
272 natural_width cr0_read_shadow;
273 natural_width cr4_read_shadow;
274 natural_width cr3_target_value0;
275 natural_width cr3_target_value1;
276 natural_width cr3_target_value2;
277 natural_width cr3_target_value3;
278 natural_width exit_qualification;
279 natural_width guest_linear_address;
280 natural_width guest_cr0;
281 natural_width guest_cr3;
282 natural_width guest_cr4;
283 natural_width guest_es_base;
284 natural_width guest_cs_base;
285 natural_width guest_ss_base;
286 natural_width guest_ds_base;
287 natural_width guest_fs_base;
288 natural_width guest_gs_base;
289 natural_width guest_ldtr_base;
290 natural_width guest_tr_base;
291 natural_width guest_gdtr_base;
292 natural_width guest_idtr_base;
293 natural_width guest_dr7;
294 natural_width guest_rsp;
295 natural_width guest_rip;
296 natural_width guest_rflags;
297 natural_width guest_pending_dbg_exceptions;
298 natural_width guest_sysenter_esp;
299 natural_width guest_sysenter_eip;
300 natural_width host_cr0;
301 natural_width host_cr3;
302 natural_width host_cr4;
303 natural_width host_fs_base;
304 natural_width host_gs_base;
305 natural_width host_tr_base;
306 natural_width host_gdtr_base;
307 natural_width host_idtr_base;
308 natural_width host_ia32_sysenter_esp;
309 natural_width host_ia32_sysenter_eip;
310 natural_width host_rsp;
311 natural_width host_rip;
312 natural_width paddingl[8]; /* room for future expansion */
313 u32 pin_based_vm_exec_control;
314 u32 cpu_based_vm_exec_control;
315 u32 exception_bitmap;
316 u32 page_fault_error_code_mask;
317 u32 page_fault_error_code_match;
318 u32 cr3_target_count;
319 u32 vm_exit_controls;
320 u32 vm_exit_msr_store_count;
321 u32 vm_exit_msr_load_count;
322 u32 vm_entry_controls;
323 u32 vm_entry_msr_load_count;
324 u32 vm_entry_intr_info_field;
325 u32 vm_entry_exception_error_code;
326 u32 vm_entry_instruction_len;
328 u32 secondary_vm_exec_control;
329 u32 vm_instruction_error;
331 u32 vm_exit_intr_info;
332 u32 vm_exit_intr_error_code;
333 u32 idt_vectoring_info_field;
334 u32 idt_vectoring_error_code;
335 u32 vm_exit_instruction_len;
336 u32 vmx_instruction_info;
343 u32 guest_ldtr_limit;
345 u32 guest_gdtr_limit;
346 u32 guest_idtr_limit;
347 u32 guest_es_ar_bytes;
348 u32 guest_cs_ar_bytes;
349 u32 guest_ss_ar_bytes;
350 u32 guest_ds_ar_bytes;
351 u32 guest_fs_ar_bytes;
352 u32 guest_gs_ar_bytes;
353 u32 guest_ldtr_ar_bytes;
354 u32 guest_tr_ar_bytes;
355 u32 guest_interruptibility_info;
356 u32 guest_activity_state;
357 u32 guest_sysenter_cs;
358 u32 host_ia32_sysenter_cs;
359 u32 vmx_preemption_timer_value;
360 u32 padding32[7]; /* room for future expansion */
361 u16 virtual_processor_id;
363 u16 guest_es_selector;
364 u16 guest_cs_selector;
365 u16 guest_ss_selector;
366 u16 guest_ds_selector;
367 u16 guest_fs_selector;
368 u16 guest_gs_selector;
369 u16 guest_ldtr_selector;
370 u16 guest_tr_selector;
371 u16 guest_intr_status;
372 u16 host_es_selector;
373 u16 host_cs_selector;
374 u16 host_ss_selector;
375 u16 host_ds_selector;
376 u16 host_fs_selector;
377 u16 host_gs_selector;
378 u16 host_tr_selector;
382 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
383 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
384 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
386 #define VMCS12_REVISION 0x11e57ed0
389 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
390 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
391 * current implementation, 4K are reserved to avoid future complications.
393 #define VMCS12_SIZE 0x1000
395 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
397 struct list_head list;
399 struct loaded_vmcs vmcs02;
403 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
404 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
407 /* Has the level1 guest done vmxon? */
411 /* The guest-physical address of the current VMCS L1 keeps for L2 */
413 /* The host-usable pointer to the above */
414 struct page *current_vmcs12_page;
415 struct vmcs12 *current_vmcs12;
417 * Cache of the guest's VMCS, existing outside of guest memory.
418 * Loaded from guest memory during VMPTRLD. Flushed to guest
419 * memory during VMXOFF, VMCLEAR, VMPTRLD.
421 struct vmcs12 *cached_vmcs12;
423 * Indicates if the shadow vmcs must be updated with the
424 * data hold by vmcs12
426 bool sync_shadow_vmcs;
428 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
429 struct list_head vmcs02_pool;
431 bool change_vmcs01_virtual_x2apic_mode;
432 /* L2 must run next, and mustn't decide to exit to L1. */
433 bool nested_run_pending;
435 * Guest pages referred to in vmcs02 with host-physical pointers, so
436 * we must keep them pinned while L2 runs.
438 struct page *apic_access_page;
439 struct page *virtual_apic_page;
440 struct page *pi_desc_page;
441 struct pi_desc *pi_desc;
445 unsigned long *msr_bitmap;
447 struct hrtimer preemption_timer;
448 bool preemption_timer_expired;
450 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
457 * We only store the "true" versions of the VMX capability MSRs. We
458 * generate the "non-true" versions by setting the must-be-1 bits
459 * according to the SDM.
461 u32 nested_vmx_procbased_ctls_low;
462 u32 nested_vmx_procbased_ctls_high;
463 u32 nested_vmx_secondary_ctls_low;
464 u32 nested_vmx_secondary_ctls_high;
465 u32 nested_vmx_pinbased_ctls_low;
466 u32 nested_vmx_pinbased_ctls_high;
467 u32 nested_vmx_exit_ctls_low;
468 u32 nested_vmx_exit_ctls_high;
469 u32 nested_vmx_entry_ctls_low;
470 u32 nested_vmx_entry_ctls_high;
471 u32 nested_vmx_misc_low;
472 u32 nested_vmx_misc_high;
473 u32 nested_vmx_ept_caps;
474 u32 nested_vmx_vpid_caps;
475 u64 nested_vmx_basic;
476 u64 nested_vmx_cr0_fixed0;
477 u64 nested_vmx_cr0_fixed1;
478 u64 nested_vmx_cr4_fixed0;
479 u64 nested_vmx_cr4_fixed1;
480 u64 nested_vmx_vmcs_enum;
483 #define POSTED_INTR_ON 0
484 #define POSTED_INTR_SN 1
486 /* Posted-Interrupt Descriptor */
488 u32 pir[8]; /* Posted interrupt requested */
491 /* bit 256 - Outstanding Notification */
493 /* bit 257 - Suppress Notification */
495 /* bit 271:258 - Reserved */
497 /* bit 279:272 - Notification Vector */
499 /* bit 287:280 - Reserved */
501 /* bit 319:288 - Notification Destination */
509 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
511 return test_and_set_bit(POSTED_INTR_ON,
512 (unsigned long *)&pi_desc->control);
515 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
517 return test_and_clear_bit(POSTED_INTR_ON,
518 (unsigned long *)&pi_desc->control);
521 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
523 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
526 static inline void pi_clear_sn(struct pi_desc *pi_desc)
528 return clear_bit(POSTED_INTR_SN,
529 (unsigned long *)&pi_desc->control);
532 static inline void pi_set_sn(struct pi_desc *pi_desc)
534 return set_bit(POSTED_INTR_SN,
535 (unsigned long *)&pi_desc->control);
538 static inline void pi_clear_on(struct pi_desc *pi_desc)
540 clear_bit(POSTED_INTR_ON,
541 (unsigned long *)&pi_desc->control);
544 static inline int pi_test_on(struct pi_desc *pi_desc)
546 return test_bit(POSTED_INTR_ON,
547 (unsigned long *)&pi_desc->control);
550 static inline int pi_test_sn(struct pi_desc *pi_desc)
552 return test_bit(POSTED_INTR_SN,
553 (unsigned long *)&pi_desc->control);
557 struct kvm_vcpu vcpu;
558 unsigned long host_rsp;
560 bool nmi_known_unmasked;
562 u32 idt_vectoring_info;
564 struct shared_msr_entry *guest_msrs;
567 unsigned long host_idt_base;
569 u64 msr_host_kernel_gs_base;
570 u64 msr_guest_kernel_gs_base;
572 u32 vm_entry_controls_shadow;
573 u32 vm_exit_controls_shadow;
575 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
576 * non-nested (L1) guest, it always points to vmcs01. For a nested
577 * guest (L2), it points to a different VMCS.
579 struct loaded_vmcs vmcs01;
580 struct loaded_vmcs *loaded_vmcs;
581 bool __launched; /* temporary, used in vmx_vcpu_run */
582 struct msr_autoload {
584 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
585 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
589 u16 fs_sel, gs_sel, ldt_sel;
593 int gs_ldt_reload_needed;
594 int fs_reload_needed;
595 u64 msr_host_bndcfgs;
596 unsigned long vmcs_host_cr4; /* May not match real cr4 */
601 struct kvm_segment segs[8];
604 u32 bitmask; /* 4 bits per segment (1 bit per field) */
605 struct kvm_save_segment {
613 bool emulation_required;
617 /* Posted interrupt descriptor */
618 struct pi_desc pi_desc;
620 /* Support for a guest hypervisor (nested VMX) */
621 struct nested_vmx nested;
623 /* Dynamic PLE window. */
625 bool ple_window_dirty;
627 /* Support for PML */
628 #define PML_ENTITY_NUM 512
631 /* apic deadline value in host tsc */
634 u64 current_tsc_ratio;
636 bool guest_pkru_valid;
641 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
642 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
643 * in msr_ia32_feature_control_valid_bits.
645 u64 msr_ia32_feature_control;
646 u64 msr_ia32_feature_control_valid_bits;
649 enum segment_cache_field {
658 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
660 return container_of(vcpu, struct vcpu_vmx, vcpu);
663 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
665 return &(to_vmx(vcpu)->pi_desc);
668 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
669 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
670 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
671 [number##_HIGH] = VMCS12_OFFSET(name)+4
674 static unsigned long shadow_read_only_fields[] = {
676 * We do NOT shadow fields that are modified when L0
677 * traps and emulates any vmx instruction (e.g. VMPTRLD,
678 * VMXON...) executed by L1.
679 * For example, VM_INSTRUCTION_ERROR is read
680 * by L1 if a vmx instruction fails (part of the error path).
681 * Note the code assumes this logic. If for some reason
682 * we start shadowing these fields then we need to
683 * force a shadow sync when L0 emulates vmx instructions
684 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
685 * by nested_vmx_failValid)
689 VM_EXIT_INSTRUCTION_LEN,
690 IDT_VECTORING_INFO_FIELD,
691 IDT_VECTORING_ERROR_CODE,
692 VM_EXIT_INTR_ERROR_CODE,
694 GUEST_LINEAR_ADDRESS,
695 GUEST_PHYSICAL_ADDRESS
697 static int max_shadow_read_only_fields =
698 ARRAY_SIZE(shadow_read_only_fields);
700 static unsigned long shadow_read_write_fields[] = {
707 GUEST_INTERRUPTIBILITY_INFO,
720 CPU_BASED_VM_EXEC_CONTROL,
721 VM_ENTRY_EXCEPTION_ERROR_CODE,
722 VM_ENTRY_INTR_INFO_FIELD,
723 VM_ENTRY_INSTRUCTION_LEN,
724 VM_ENTRY_EXCEPTION_ERROR_CODE,
730 static int max_shadow_read_write_fields =
731 ARRAY_SIZE(shadow_read_write_fields);
733 static const unsigned short vmcs_field_to_offset_table[] = {
734 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
735 FIELD(POSTED_INTR_NV, posted_intr_nv),
736 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
737 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
738 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
739 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
740 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
741 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
742 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
743 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
744 FIELD(GUEST_INTR_STATUS, guest_intr_status),
745 FIELD(HOST_ES_SELECTOR, host_es_selector),
746 FIELD(HOST_CS_SELECTOR, host_cs_selector),
747 FIELD(HOST_SS_SELECTOR, host_ss_selector),
748 FIELD(HOST_DS_SELECTOR, host_ds_selector),
749 FIELD(HOST_FS_SELECTOR, host_fs_selector),
750 FIELD(HOST_GS_SELECTOR, host_gs_selector),
751 FIELD(HOST_TR_SELECTOR, host_tr_selector),
752 FIELD64(IO_BITMAP_A, io_bitmap_a),
753 FIELD64(IO_BITMAP_B, io_bitmap_b),
754 FIELD64(MSR_BITMAP, msr_bitmap),
755 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
756 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
757 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
758 FIELD64(TSC_OFFSET, tsc_offset),
759 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
760 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
761 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
762 FIELD64(EPT_POINTER, ept_pointer),
763 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
764 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
765 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
766 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
767 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
768 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
769 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
770 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
771 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
772 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
773 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
774 FIELD64(GUEST_PDPTR0, guest_pdptr0),
775 FIELD64(GUEST_PDPTR1, guest_pdptr1),
776 FIELD64(GUEST_PDPTR2, guest_pdptr2),
777 FIELD64(GUEST_PDPTR3, guest_pdptr3),
778 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
779 FIELD64(HOST_IA32_PAT, host_ia32_pat),
780 FIELD64(HOST_IA32_EFER, host_ia32_efer),
781 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
782 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
783 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
784 FIELD(EXCEPTION_BITMAP, exception_bitmap),
785 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
786 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
787 FIELD(CR3_TARGET_COUNT, cr3_target_count),
788 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
789 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
790 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
791 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
792 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
793 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
794 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
795 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
796 FIELD(TPR_THRESHOLD, tpr_threshold),
797 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
798 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
799 FIELD(VM_EXIT_REASON, vm_exit_reason),
800 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
801 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
802 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
803 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
804 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
805 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
806 FIELD(GUEST_ES_LIMIT, guest_es_limit),
807 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
808 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
809 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
810 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
811 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
812 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
813 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
814 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
815 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
816 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
817 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
818 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
819 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
820 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
821 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
822 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
823 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
824 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
825 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
826 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
827 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
828 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
829 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
830 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
831 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
832 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
833 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
834 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
835 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
836 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
837 FIELD(EXIT_QUALIFICATION, exit_qualification),
838 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
839 FIELD(GUEST_CR0, guest_cr0),
840 FIELD(GUEST_CR3, guest_cr3),
841 FIELD(GUEST_CR4, guest_cr4),
842 FIELD(GUEST_ES_BASE, guest_es_base),
843 FIELD(GUEST_CS_BASE, guest_cs_base),
844 FIELD(GUEST_SS_BASE, guest_ss_base),
845 FIELD(GUEST_DS_BASE, guest_ds_base),
846 FIELD(GUEST_FS_BASE, guest_fs_base),
847 FIELD(GUEST_GS_BASE, guest_gs_base),
848 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
849 FIELD(GUEST_TR_BASE, guest_tr_base),
850 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
851 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
852 FIELD(GUEST_DR7, guest_dr7),
853 FIELD(GUEST_RSP, guest_rsp),
854 FIELD(GUEST_RIP, guest_rip),
855 FIELD(GUEST_RFLAGS, guest_rflags),
856 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
857 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
858 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
859 FIELD(HOST_CR0, host_cr0),
860 FIELD(HOST_CR3, host_cr3),
861 FIELD(HOST_CR4, host_cr4),
862 FIELD(HOST_FS_BASE, host_fs_base),
863 FIELD(HOST_GS_BASE, host_gs_base),
864 FIELD(HOST_TR_BASE, host_tr_base),
865 FIELD(HOST_GDTR_BASE, host_gdtr_base),
866 FIELD(HOST_IDTR_BASE, host_idtr_base),
867 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
868 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
869 FIELD(HOST_RSP, host_rsp),
870 FIELD(HOST_RIP, host_rip),
873 static inline short vmcs_field_to_offset(unsigned long field)
875 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
877 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
878 vmcs_field_to_offset_table[field] == 0)
881 return vmcs_field_to_offset_table[field];
884 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
886 return to_vmx(vcpu)->nested.cached_vmcs12;
889 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
891 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
892 if (is_error_page(page))
898 static void nested_release_page(struct page *page)
900 kvm_release_page_dirty(page);
903 static void nested_release_page_clean(struct page *page)
905 kvm_release_page_clean(page);
908 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
909 static u64 construct_eptp(unsigned long root_hpa);
910 static bool vmx_xsaves_supported(void);
911 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
912 static void vmx_set_segment(struct kvm_vcpu *vcpu,
913 struct kvm_segment *var, int seg);
914 static void vmx_get_segment(struct kvm_vcpu *vcpu,
915 struct kvm_segment *var, int seg);
916 static bool guest_state_valid(struct kvm_vcpu *vcpu);
917 static u32 vmx_segment_access_rights(struct kvm_segment *var);
918 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
919 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
920 static int alloc_identity_pagetable(struct kvm *kvm);
922 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
923 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
925 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
926 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
928 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
929 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
932 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
933 * can find which vCPU should be waken up.
935 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
936 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
941 VMX_MSR_BITMAP_LEGACY,
942 VMX_MSR_BITMAP_LONGMODE,
943 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
944 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
945 VMX_MSR_BITMAP_LEGACY_X2APIC,
946 VMX_MSR_BITMAP_LONGMODE_X2APIC,
952 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
954 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
955 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
956 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
957 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
958 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
959 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
960 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
961 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
962 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
963 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
965 static bool cpu_has_load_ia32_efer;
966 static bool cpu_has_load_perf_global_ctrl;
968 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
969 static DEFINE_SPINLOCK(vmx_vpid_lock);
971 static struct vmcs_config {
976 u32 pin_based_exec_ctrl;
977 u32 cpu_based_exec_ctrl;
978 u32 cpu_based_2nd_exec_ctrl;
983 static struct vmx_capability {
988 #define VMX_SEGMENT_FIELD(seg) \
989 [VCPU_SREG_##seg] = { \
990 .selector = GUEST_##seg##_SELECTOR, \
991 .base = GUEST_##seg##_BASE, \
992 .limit = GUEST_##seg##_LIMIT, \
993 .ar_bytes = GUEST_##seg##_AR_BYTES, \
996 static const struct kvm_vmx_segment_field {
1001 } kvm_vmx_segment_fields[] = {
1002 VMX_SEGMENT_FIELD(CS),
1003 VMX_SEGMENT_FIELD(DS),
1004 VMX_SEGMENT_FIELD(ES),
1005 VMX_SEGMENT_FIELD(FS),
1006 VMX_SEGMENT_FIELD(GS),
1007 VMX_SEGMENT_FIELD(SS),
1008 VMX_SEGMENT_FIELD(TR),
1009 VMX_SEGMENT_FIELD(LDTR),
1012 static u64 host_efer;
1014 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1017 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1018 * away by decrementing the array size.
1020 static const u32 vmx_msr_index[] = {
1021 #ifdef CONFIG_X86_64
1022 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1024 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1027 static inline bool is_exception_n(u32 intr_info, u8 vector)
1029 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1030 INTR_INFO_VALID_MASK)) ==
1031 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1034 static inline bool is_debug(u32 intr_info)
1036 return is_exception_n(intr_info, DB_VECTOR);
1039 static inline bool is_breakpoint(u32 intr_info)
1041 return is_exception_n(intr_info, BP_VECTOR);
1044 static inline bool is_page_fault(u32 intr_info)
1046 return is_exception_n(intr_info, PF_VECTOR);
1049 static inline bool is_no_device(u32 intr_info)
1051 return is_exception_n(intr_info, NM_VECTOR);
1054 static inline bool is_invalid_opcode(u32 intr_info)
1056 return is_exception_n(intr_info, UD_VECTOR);
1059 static inline bool is_external_interrupt(u32 intr_info)
1061 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1062 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1065 static inline bool is_machine_check(u32 intr_info)
1067 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1068 INTR_INFO_VALID_MASK)) ==
1069 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1072 static inline bool cpu_has_vmx_msr_bitmap(void)
1074 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1077 static inline bool cpu_has_vmx_tpr_shadow(void)
1079 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1082 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1084 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1087 static inline bool cpu_has_secondary_exec_ctrls(void)
1089 return vmcs_config.cpu_based_exec_ctrl &
1090 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1093 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1095 return vmcs_config.cpu_based_2nd_exec_ctrl &
1096 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1099 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1101 return vmcs_config.cpu_based_2nd_exec_ctrl &
1102 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1105 static inline bool cpu_has_vmx_apic_register_virt(void)
1107 return vmcs_config.cpu_based_2nd_exec_ctrl &
1108 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1111 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1113 return vmcs_config.cpu_based_2nd_exec_ctrl &
1114 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1118 * Comment's format: document - errata name - stepping - processor name.
1120 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1122 static u32 vmx_preemption_cpu_tfms[] = {
1123 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1125 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1126 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1127 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1129 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1131 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1132 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1134 * 320767.pdf - AAP86 - B1 -
1135 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1138 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1140 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1142 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1144 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1145 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1146 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1150 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1152 u32 eax = cpuid_eax(0x00000001), i;
1154 /* Clear the reserved bits */
1155 eax &= ~(0x3U << 14 | 0xfU << 28);
1156 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1157 if (eax == vmx_preemption_cpu_tfms[i])
1163 static inline bool cpu_has_vmx_preemption_timer(void)
1165 return vmcs_config.pin_based_exec_ctrl &
1166 PIN_BASED_VMX_PREEMPTION_TIMER;
1169 static inline bool cpu_has_vmx_posted_intr(void)
1171 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1172 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1175 static inline bool cpu_has_vmx_apicv(void)
1177 return cpu_has_vmx_apic_register_virt() &&
1178 cpu_has_vmx_virtual_intr_delivery() &&
1179 cpu_has_vmx_posted_intr();
1182 static inline bool cpu_has_vmx_flexpriority(void)
1184 return cpu_has_vmx_tpr_shadow() &&
1185 cpu_has_vmx_virtualize_apic_accesses();
1188 static inline bool cpu_has_vmx_ept_execute_only(void)
1190 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1193 static inline bool cpu_has_vmx_ept_2m_page(void)
1195 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1198 static inline bool cpu_has_vmx_ept_1g_page(void)
1200 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1203 static inline bool cpu_has_vmx_ept_4levels(void)
1205 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1208 static inline bool cpu_has_vmx_ept_ad_bits(void)
1210 return vmx_capability.ept & VMX_EPT_AD_BIT;
1213 static inline bool cpu_has_vmx_invept_context(void)
1215 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1218 static inline bool cpu_has_vmx_invept_global(void)
1220 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1223 static inline bool cpu_has_vmx_invvpid_single(void)
1225 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1228 static inline bool cpu_has_vmx_invvpid_global(void)
1230 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1233 static inline bool cpu_has_vmx_invvpid(void)
1235 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1238 static inline bool cpu_has_vmx_ept(void)
1240 return vmcs_config.cpu_based_2nd_exec_ctrl &
1241 SECONDARY_EXEC_ENABLE_EPT;
1244 static inline bool cpu_has_vmx_unrestricted_guest(void)
1246 return vmcs_config.cpu_based_2nd_exec_ctrl &
1247 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1250 static inline bool cpu_has_vmx_ple(void)
1252 return vmcs_config.cpu_based_2nd_exec_ctrl &
1253 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1256 static inline bool cpu_has_vmx_basic_inout(void)
1258 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1261 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1263 return flexpriority_enabled && lapic_in_kernel(vcpu);
1266 static inline bool cpu_has_vmx_vpid(void)
1268 return vmcs_config.cpu_based_2nd_exec_ctrl &
1269 SECONDARY_EXEC_ENABLE_VPID;
1272 static inline bool cpu_has_vmx_rdtscp(void)
1274 return vmcs_config.cpu_based_2nd_exec_ctrl &
1275 SECONDARY_EXEC_RDTSCP;
1278 static inline bool cpu_has_vmx_invpcid(void)
1280 return vmcs_config.cpu_based_2nd_exec_ctrl &
1281 SECONDARY_EXEC_ENABLE_INVPCID;
1284 static inline bool cpu_has_vmx_wbinvd_exit(void)
1286 return vmcs_config.cpu_based_2nd_exec_ctrl &
1287 SECONDARY_EXEC_WBINVD_EXITING;
1290 static inline bool cpu_has_vmx_shadow_vmcs(void)
1293 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1294 /* check if the cpu supports writing r/o exit information fields */
1295 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1298 return vmcs_config.cpu_based_2nd_exec_ctrl &
1299 SECONDARY_EXEC_SHADOW_VMCS;
1302 static inline bool cpu_has_vmx_pml(void)
1304 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1307 static inline bool cpu_has_vmx_tsc_scaling(void)
1309 return vmcs_config.cpu_based_2nd_exec_ctrl &
1310 SECONDARY_EXEC_TSC_SCALING;
1313 static inline bool report_flexpriority(void)
1315 return flexpriority_enabled;
1318 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1320 return vmcs12->cpu_based_vm_exec_control & bit;
1323 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1325 return (vmcs12->cpu_based_vm_exec_control &
1326 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1327 (vmcs12->secondary_vm_exec_control & bit);
1330 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1332 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1335 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1337 return vmcs12->pin_based_vm_exec_control &
1338 PIN_BASED_VMX_PREEMPTION_TIMER;
1341 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1343 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1346 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1348 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1349 vmx_xsaves_supported();
1352 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1354 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1357 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1359 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1362 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1364 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1367 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1369 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1372 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1374 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1377 static inline bool is_nmi(u32 intr_info)
1379 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1380 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1383 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1385 unsigned long exit_qualification);
1386 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1387 struct vmcs12 *vmcs12,
1388 u32 reason, unsigned long qualification);
1390 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1394 for (i = 0; i < vmx->nmsrs; ++i)
1395 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1400 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1406 } operand = { vpid, 0, gva };
1408 asm volatile (__ex(ASM_VMX_INVVPID)
1409 /* CF==1 or ZF==1 --> rc = -1 */
1410 "; ja 1f ; ud2 ; 1:"
1411 : : "a"(&operand), "c"(ext) : "cc", "memory");
1414 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1418 } operand = {eptp, gpa};
1420 asm volatile (__ex(ASM_VMX_INVEPT)
1421 /* CF==1 or ZF==1 --> rc = -1 */
1422 "; ja 1f ; ud2 ; 1:\n"
1423 : : "a" (&operand), "c" (ext) : "cc", "memory");
1426 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1430 i = __find_msr_index(vmx, msr);
1432 return &vmx->guest_msrs[i];
1436 static void vmcs_clear(struct vmcs *vmcs)
1438 u64 phys_addr = __pa(vmcs);
1441 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1442 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1445 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1449 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1451 vmcs_clear(loaded_vmcs->vmcs);
1452 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1453 vmcs_clear(loaded_vmcs->shadow_vmcs);
1454 loaded_vmcs->cpu = -1;
1455 loaded_vmcs->launched = 0;
1458 static void vmcs_load(struct vmcs *vmcs)
1460 u64 phys_addr = __pa(vmcs);
1463 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1464 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1467 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1471 #ifdef CONFIG_KEXEC_CORE
1473 * This bitmap is used to indicate whether the vmclear
1474 * operation is enabled on all cpus. All disabled by
1477 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1479 static inline void crash_enable_local_vmclear(int cpu)
1481 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1484 static inline void crash_disable_local_vmclear(int cpu)
1486 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1489 static inline int crash_local_vmclear_enabled(int cpu)
1491 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1494 static void crash_vmclear_local_loaded_vmcss(void)
1496 int cpu = raw_smp_processor_id();
1497 struct loaded_vmcs *v;
1499 if (!crash_local_vmclear_enabled(cpu))
1502 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1503 loaded_vmcss_on_cpu_link)
1504 vmcs_clear(v->vmcs);
1507 static inline void crash_enable_local_vmclear(int cpu) { }
1508 static inline void crash_disable_local_vmclear(int cpu) { }
1509 #endif /* CONFIG_KEXEC_CORE */
1511 static void __loaded_vmcs_clear(void *arg)
1513 struct loaded_vmcs *loaded_vmcs = arg;
1514 int cpu = raw_smp_processor_id();
1516 if (loaded_vmcs->cpu != cpu)
1517 return; /* vcpu migration can race with cpu offline */
1518 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1519 per_cpu(current_vmcs, cpu) = NULL;
1520 crash_disable_local_vmclear(cpu);
1521 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1524 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1525 * is before setting loaded_vmcs->vcpu to -1 which is done in
1526 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1527 * then adds the vmcs into percpu list before it is deleted.
1531 loaded_vmcs_init(loaded_vmcs);
1532 crash_enable_local_vmclear(cpu);
1535 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1537 int cpu = loaded_vmcs->cpu;
1540 smp_call_function_single(cpu,
1541 __loaded_vmcs_clear, loaded_vmcs, 1);
1544 static inline void vpid_sync_vcpu_single(int vpid)
1549 if (cpu_has_vmx_invvpid_single())
1550 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1553 static inline void vpid_sync_vcpu_global(void)
1555 if (cpu_has_vmx_invvpid_global())
1556 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1559 static inline void vpid_sync_context(int vpid)
1561 if (cpu_has_vmx_invvpid_single())
1562 vpid_sync_vcpu_single(vpid);
1564 vpid_sync_vcpu_global();
1567 static inline void ept_sync_global(void)
1569 if (cpu_has_vmx_invept_global())
1570 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1573 static inline void ept_sync_context(u64 eptp)
1576 if (cpu_has_vmx_invept_context())
1577 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1583 static __always_inline void vmcs_check16(unsigned long field)
1585 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1586 "16-bit accessor invalid for 64-bit field");
1587 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1588 "16-bit accessor invalid for 64-bit high field");
1589 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1590 "16-bit accessor invalid for 32-bit high field");
1591 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1592 "16-bit accessor invalid for natural width field");
1595 static __always_inline void vmcs_check32(unsigned long field)
1597 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1598 "32-bit accessor invalid for 16-bit field");
1599 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1600 "32-bit accessor invalid for natural width field");
1603 static __always_inline void vmcs_check64(unsigned long field)
1605 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1606 "64-bit accessor invalid for 16-bit field");
1607 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1608 "64-bit accessor invalid for 64-bit high field");
1609 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1610 "64-bit accessor invalid for 32-bit field");
1611 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1612 "64-bit accessor invalid for natural width field");
1615 static __always_inline void vmcs_checkl(unsigned long field)
1617 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1618 "Natural width accessor invalid for 16-bit field");
1619 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1620 "Natural width accessor invalid for 64-bit field");
1621 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1622 "Natural width accessor invalid for 64-bit high field");
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1624 "Natural width accessor invalid for 32-bit field");
1627 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1629 unsigned long value;
1631 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1632 : "=a"(value) : "d"(field) : "cc");
1636 static __always_inline u16 vmcs_read16(unsigned long field)
1638 vmcs_check16(field);
1639 return __vmcs_readl(field);
1642 static __always_inline u32 vmcs_read32(unsigned long field)
1644 vmcs_check32(field);
1645 return __vmcs_readl(field);
1648 static __always_inline u64 vmcs_read64(unsigned long field)
1650 vmcs_check64(field);
1651 #ifdef CONFIG_X86_64
1652 return __vmcs_readl(field);
1654 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1658 static __always_inline unsigned long vmcs_readl(unsigned long field)
1661 return __vmcs_readl(field);
1664 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1666 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1667 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1671 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1675 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1676 : "=q"(error) : "a"(value), "d"(field) : "cc");
1677 if (unlikely(error))
1678 vmwrite_error(field, value);
1681 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1683 vmcs_check16(field);
1684 __vmcs_writel(field, value);
1687 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1689 vmcs_check32(field);
1690 __vmcs_writel(field, value);
1693 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1695 vmcs_check64(field);
1696 __vmcs_writel(field, value);
1697 #ifndef CONFIG_X86_64
1699 __vmcs_writel(field+1, value >> 32);
1703 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1706 __vmcs_writel(field, value);
1709 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1711 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1712 "vmcs_clear_bits does not support 64-bit fields");
1713 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1716 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1718 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1719 "vmcs_set_bits does not support 64-bit fields");
1720 __vmcs_writel(field, __vmcs_readl(field) | mask);
1723 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1725 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1728 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1730 vmcs_write32(VM_ENTRY_CONTROLS, val);
1731 vmx->vm_entry_controls_shadow = val;
1734 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1736 if (vmx->vm_entry_controls_shadow != val)
1737 vm_entry_controls_init(vmx, val);
1740 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1742 return vmx->vm_entry_controls_shadow;
1746 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1748 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1751 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1753 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1756 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1758 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1761 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1763 vmcs_write32(VM_EXIT_CONTROLS, val);
1764 vmx->vm_exit_controls_shadow = val;
1767 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1769 if (vmx->vm_exit_controls_shadow != val)
1770 vm_exit_controls_init(vmx, val);
1773 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1775 return vmx->vm_exit_controls_shadow;
1779 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1781 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1784 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1786 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1789 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1791 vmx->segment_cache.bitmask = 0;
1794 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1798 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1800 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1801 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1802 vmx->segment_cache.bitmask = 0;
1804 ret = vmx->segment_cache.bitmask & mask;
1805 vmx->segment_cache.bitmask |= mask;
1809 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1811 u16 *p = &vmx->segment_cache.seg[seg].selector;
1813 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1814 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1818 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1820 ulong *p = &vmx->segment_cache.seg[seg].base;
1822 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1823 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1827 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1829 u32 *p = &vmx->segment_cache.seg[seg].limit;
1831 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1832 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1836 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1838 u32 *p = &vmx->segment_cache.seg[seg].ar;
1840 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1841 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1845 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1849 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1850 (1u << DB_VECTOR) | (1u << AC_VECTOR);
1851 if ((vcpu->guest_debug &
1852 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1853 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1854 eb |= 1u << BP_VECTOR;
1855 if (to_vmx(vcpu)->rmode.vm86_active)
1858 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1860 /* When we are running a nested L2 guest and L1 specified for it a
1861 * certain exception bitmap, we must trap the same exceptions and pass
1862 * them to L1. When running L2, we will only handle the exceptions
1863 * specified above if L1 did not want them.
1865 if (is_guest_mode(vcpu))
1866 eb |= get_vmcs12(vcpu)->exception_bitmap;
1868 vmcs_write32(EXCEPTION_BITMAP, eb);
1871 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1872 unsigned long entry, unsigned long exit)
1874 vm_entry_controls_clearbit(vmx, entry);
1875 vm_exit_controls_clearbit(vmx, exit);
1878 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1881 struct msr_autoload *m = &vmx->msr_autoload;
1885 if (cpu_has_load_ia32_efer) {
1886 clear_atomic_switch_msr_special(vmx,
1887 VM_ENTRY_LOAD_IA32_EFER,
1888 VM_EXIT_LOAD_IA32_EFER);
1892 case MSR_CORE_PERF_GLOBAL_CTRL:
1893 if (cpu_has_load_perf_global_ctrl) {
1894 clear_atomic_switch_msr_special(vmx,
1895 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1896 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1902 for (i = 0; i < m->nr; ++i)
1903 if (m->guest[i].index == msr)
1909 m->guest[i] = m->guest[m->nr];
1910 m->host[i] = m->host[m->nr];
1911 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1912 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1915 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1916 unsigned long entry, unsigned long exit,
1917 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1918 u64 guest_val, u64 host_val)
1920 vmcs_write64(guest_val_vmcs, guest_val);
1921 vmcs_write64(host_val_vmcs, host_val);
1922 vm_entry_controls_setbit(vmx, entry);
1923 vm_exit_controls_setbit(vmx, exit);
1926 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1927 u64 guest_val, u64 host_val)
1930 struct msr_autoload *m = &vmx->msr_autoload;
1934 if (cpu_has_load_ia32_efer) {
1935 add_atomic_switch_msr_special(vmx,
1936 VM_ENTRY_LOAD_IA32_EFER,
1937 VM_EXIT_LOAD_IA32_EFER,
1940 guest_val, host_val);
1944 case MSR_CORE_PERF_GLOBAL_CTRL:
1945 if (cpu_has_load_perf_global_ctrl) {
1946 add_atomic_switch_msr_special(vmx,
1947 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1948 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1949 GUEST_IA32_PERF_GLOBAL_CTRL,
1950 HOST_IA32_PERF_GLOBAL_CTRL,
1951 guest_val, host_val);
1955 case MSR_IA32_PEBS_ENABLE:
1956 /* PEBS needs a quiescent period after being disabled (to write
1957 * a record). Disabling PEBS through VMX MSR swapping doesn't
1958 * provide that period, so a CPU could write host's record into
1961 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1964 for (i = 0; i < m->nr; ++i)
1965 if (m->guest[i].index == msr)
1968 if (i == NR_AUTOLOAD_MSRS) {
1969 printk_once(KERN_WARNING "Not enough msr switch entries. "
1970 "Can't add msr %x\n", msr);
1972 } else if (i == m->nr) {
1974 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1975 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1978 m->guest[i].index = msr;
1979 m->guest[i].value = guest_val;
1980 m->host[i].index = msr;
1981 m->host[i].value = host_val;
1984 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1986 u64 guest_efer = vmx->vcpu.arch.efer;
1987 u64 ignore_bits = 0;
1991 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1992 * host CPUID is more efficient than testing guest CPUID
1993 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1995 if (boot_cpu_has(X86_FEATURE_SMEP))
1996 guest_efer |= EFER_NX;
1997 else if (!(guest_efer & EFER_NX))
1998 ignore_bits |= EFER_NX;
2002 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2004 ignore_bits |= EFER_SCE;
2005 #ifdef CONFIG_X86_64
2006 ignore_bits |= EFER_LMA | EFER_LME;
2007 /* SCE is meaningful only in long mode on Intel */
2008 if (guest_efer & EFER_LMA)
2009 ignore_bits &= ~(u64)EFER_SCE;
2012 clear_atomic_switch_msr(vmx, MSR_EFER);
2015 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2016 * On CPUs that support "load IA32_EFER", always switch EFER
2017 * atomically, since it's faster than switching it manually.
2019 if (cpu_has_load_ia32_efer ||
2020 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2021 if (!(guest_efer & EFER_LMA))
2022 guest_efer &= ~EFER_LME;
2023 if (guest_efer != host_efer)
2024 add_atomic_switch_msr(vmx, MSR_EFER,
2025 guest_efer, host_efer);
2028 guest_efer &= ~ignore_bits;
2029 guest_efer |= host_efer & ignore_bits;
2031 vmx->guest_msrs[efer_offset].data = guest_efer;
2032 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2038 #ifdef CONFIG_X86_32
2040 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2041 * VMCS rather than the segment table. KVM uses this helper to figure
2042 * out the current bases to poke them into the VMCS before entry.
2044 static unsigned long segment_base(u16 selector)
2046 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2047 struct desc_struct *table;
2050 if (!(selector & ~SEGMENT_RPL_MASK))
2053 table = (struct desc_struct *)gdt->address;
2055 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2056 u16 ldt_selector = kvm_read_ldt();
2058 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2061 table = (struct desc_struct *)segment_base(ldt_selector);
2063 v = get_desc_base(&table[selector >> 3]);
2068 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2070 struct vcpu_vmx *vmx = to_vmx(vcpu);
2073 if (vmx->host_state.loaded)
2076 vmx->host_state.loaded = 1;
2078 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2079 * allow segment selectors with cpl > 0 or ti == 1.
2081 vmx->host_state.ldt_sel = kvm_read_ldt();
2082 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2083 savesegment(fs, vmx->host_state.fs_sel);
2084 if (!(vmx->host_state.fs_sel & 7)) {
2085 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2086 vmx->host_state.fs_reload_needed = 0;
2088 vmcs_write16(HOST_FS_SELECTOR, 0);
2089 vmx->host_state.fs_reload_needed = 1;
2091 savesegment(gs, vmx->host_state.gs_sel);
2092 if (!(vmx->host_state.gs_sel & 7))
2093 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2095 vmcs_write16(HOST_GS_SELECTOR, 0);
2096 vmx->host_state.gs_ldt_reload_needed = 1;
2099 #ifdef CONFIG_X86_64
2100 savesegment(ds, vmx->host_state.ds_sel);
2101 savesegment(es, vmx->host_state.es_sel);
2104 #ifdef CONFIG_X86_64
2105 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2106 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2108 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2109 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2112 #ifdef CONFIG_X86_64
2113 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2114 if (is_long_mode(&vmx->vcpu))
2115 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2117 if (boot_cpu_has(X86_FEATURE_MPX))
2118 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2119 for (i = 0; i < vmx->save_nmsrs; ++i)
2120 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2121 vmx->guest_msrs[i].data,
2122 vmx->guest_msrs[i].mask);
2125 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2127 if (!vmx->host_state.loaded)
2130 ++vmx->vcpu.stat.host_state_reload;
2131 vmx->host_state.loaded = 0;
2132 #ifdef CONFIG_X86_64
2133 if (is_long_mode(&vmx->vcpu))
2134 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2136 if (vmx->host_state.gs_ldt_reload_needed) {
2137 kvm_load_ldt(vmx->host_state.ldt_sel);
2138 #ifdef CONFIG_X86_64
2139 load_gs_index(vmx->host_state.gs_sel);
2141 loadsegment(gs, vmx->host_state.gs_sel);
2144 if (vmx->host_state.fs_reload_needed)
2145 loadsegment(fs, vmx->host_state.fs_sel);
2146 #ifdef CONFIG_X86_64
2147 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2148 loadsegment(ds, vmx->host_state.ds_sel);
2149 loadsegment(es, vmx->host_state.es_sel);
2152 invalidate_tss_limit();
2153 #ifdef CONFIG_X86_64
2154 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2156 if (vmx->host_state.msr_host_bndcfgs)
2157 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2158 load_gdt(this_cpu_ptr(&host_gdt));
2161 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2164 __vmx_load_host_state(vmx);
2168 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2170 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2171 struct pi_desc old, new;
2174 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2175 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2176 !kvm_vcpu_apicv_active(vcpu))
2180 old.control = new.control = pi_desc->control;
2183 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2184 * are two possible cases:
2185 * 1. After running 'pre_block', context switch
2186 * happened. For this case, 'sn' was set in
2187 * vmx_vcpu_put(), so we need to clear it here.
2188 * 2. After running 'pre_block', we were blocked,
2189 * and woken up by some other guy. For this case,
2190 * we don't need to do anything, 'pi_post_block'
2191 * will do everything for us. However, we cannot
2192 * check whether it is case #1 or case #2 here
2193 * (maybe, not needed), so we also clear sn here,
2194 * I think it is not a big deal.
2196 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2197 if (vcpu->cpu != cpu) {
2198 dest = cpu_physical_id(cpu);
2200 if (x2apic_enabled())
2203 new.ndst = (dest << 8) & 0xFF00;
2206 /* set 'NV' to 'notification vector' */
2207 new.nv = POSTED_INTR_VECTOR;
2210 /* Allow posting non-urgent interrupts */
2212 } while (cmpxchg(&pi_desc->control, old.control,
2213 new.control) != old.control);
2216 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2218 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2219 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2223 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2224 * vcpu mutex is already taken.
2226 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2228 struct vcpu_vmx *vmx = to_vmx(vcpu);
2229 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2231 if (!already_loaded) {
2232 loaded_vmcs_clear(vmx->loaded_vmcs);
2233 local_irq_disable();
2234 crash_disable_local_vmclear(cpu);
2237 * Read loaded_vmcs->cpu should be before fetching
2238 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2239 * See the comments in __loaded_vmcs_clear().
2243 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2244 &per_cpu(loaded_vmcss_on_cpu, cpu));
2245 crash_enable_local_vmclear(cpu);
2249 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2250 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2251 vmcs_load(vmx->loaded_vmcs->vmcs);
2254 if (!already_loaded) {
2255 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2256 unsigned long sysenter_esp;
2258 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2261 * Linux uses per-cpu TSS and GDT, so set these when switching
2262 * processors. See 22.2.4.
2264 vmcs_writel(HOST_TR_BASE,
2265 (unsigned long)this_cpu_ptr(&cpu_tss));
2266 vmcs_writel(HOST_GDTR_BASE, gdt->address);
2269 * VM exits change the host TR limit to 0x67 after a VM
2270 * exit. This is okay, since 0x67 covers everything except
2271 * the IO bitmap and have have code to handle the IO bitmap
2272 * being lost after a VM exit.
2274 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2276 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2277 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2279 vmx->loaded_vmcs->cpu = cpu;
2282 /* Setup TSC multiplier */
2283 if (kvm_has_tsc_control &&
2284 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2285 decache_tsc_multiplier(vmx);
2287 vmx_vcpu_pi_load(vcpu, cpu);
2288 vmx->host_pkru = read_pkru();
2291 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2293 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2295 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2296 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2297 !kvm_vcpu_apicv_active(vcpu))
2300 /* Set SN when the vCPU is preempted */
2301 if (vcpu->preempted)
2305 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2307 vmx_vcpu_pi_put(vcpu);
2309 __vmx_load_host_state(to_vmx(vcpu));
2312 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2315 * Return the cr0 value that a nested guest would read. This is a combination
2316 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2317 * its hypervisor (cr0_read_shadow).
2319 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2321 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2322 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2324 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2326 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2327 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2330 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2332 unsigned long rflags, save_rflags;
2334 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2335 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2336 rflags = vmcs_readl(GUEST_RFLAGS);
2337 if (to_vmx(vcpu)->rmode.vm86_active) {
2338 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2339 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2340 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2342 to_vmx(vcpu)->rflags = rflags;
2344 return to_vmx(vcpu)->rflags;
2347 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2349 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2350 to_vmx(vcpu)->rflags = rflags;
2351 if (to_vmx(vcpu)->rmode.vm86_active) {
2352 to_vmx(vcpu)->rmode.save_rflags = rflags;
2353 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2355 vmcs_writel(GUEST_RFLAGS, rflags);
2358 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2360 return to_vmx(vcpu)->guest_pkru;
2363 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2365 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2368 if (interruptibility & GUEST_INTR_STATE_STI)
2369 ret |= KVM_X86_SHADOW_INT_STI;
2370 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2371 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2376 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2378 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2379 u32 interruptibility = interruptibility_old;
2381 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2383 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2384 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2385 else if (mask & KVM_X86_SHADOW_INT_STI)
2386 interruptibility |= GUEST_INTR_STATE_STI;
2388 if ((interruptibility != interruptibility_old))
2389 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2392 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2396 rip = kvm_rip_read(vcpu);
2397 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2398 kvm_rip_write(vcpu, rip);
2400 /* skipping an emulated instruction also counts */
2401 vmx_set_interrupt_shadow(vcpu, 0);
2405 * KVM wants to inject page-faults which it got to the guest. This function
2406 * checks whether in a nested guest, we need to inject them to L1 or L2.
2408 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2410 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2412 if (!(vmcs12->exception_bitmap & (1u << nr)))
2415 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2416 vmcs_read32(VM_EXIT_INTR_INFO),
2417 vmcs_readl(EXIT_QUALIFICATION));
2421 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2422 bool has_error_code, u32 error_code,
2425 struct vcpu_vmx *vmx = to_vmx(vcpu);
2426 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2428 if (!reinject && is_guest_mode(vcpu) &&
2429 nested_vmx_check_exception(vcpu, nr))
2432 if (has_error_code) {
2433 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2434 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2437 if (vmx->rmode.vm86_active) {
2439 if (kvm_exception_is_soft(nr))
2440 inc_eip = vcpu->arch.event_exit_inst_len;
2441 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2442 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2446 if (kvm_exception_is_soft(nr)) {
2447 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2448 vmx->vcpu.arch.event_exit_inst_len);
2449 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2451 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2453 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2456 static bool vmx_rdtscp_supported(void)
2458 return cpu_has_vmx_rdtscp();
2461 static bool vmx_invpcid_supported(void)
2463 return cpu_has_vmx_invpcid() && enable_ept;
2467 * Swap MSR entry in host/guest MSR entry array.
2469 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2471 struct shared_msr_entry tmp;
2473 tmp = vmx->guest_msrs[to];
2474 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2475 vmx->guest_msrs[from] = tmp;
2478 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2480 unsigned long *msr_bitmap;
2482 if (is_guest_mode(vcpu))
2483 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2484 else if (cpu_has_secondary_exec_ctrls() &&
2485 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2486 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2487 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2488 if (is_long_mode(vcpu))
2489 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2491 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2493 if (is_long_mode(vcpu))
2494 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2496 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2499 if (is_long_mode(vcpu))
2500 msr_bitmap = vmx_msr_bitmap_longmode;
2502 msr_bitmap = vmx_msr_bitmap_legacy;
2505 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2509 * Set up the vmcs to automatically save and restore system
2510 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2511 * mode, as fiddling with msrs is very expensive.
2513 static void setup_msrs(struct vcpu_vmx *vmx)
2515 int save_nmsrs, index;
2518 #ifdef CONFIG_X86_64
2519 if (is_long_mode(&vmx->vcpu)) {
2520 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2522 move_msr_up(vmx, index, save_nmsrs++);
2523 index = __find_msr_index(vmx, MSR_LSTAR);
2525 move_msr_up(vmx, index, save_nmsrs++);
2526 index = __find_msr_index(vmx, MSR_CSTAR);
2528 move_msr_up(vmx, index, save_nmsrs++);
2529 index = __find_msr_index(vmx, MSR_TSC_AUX);
2530 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2531 move_msr_up(vmx, index, save_nmsrs++);
2533 * MSR_STAR is only needed on long mode guests, and only
2534 * if efer.sce is enabled.
2536 index = __find_msr_index(vmx, MSR_STAR);
2537 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2538 move_msr_up(vmx, index, save_nmsrs++);
2541 index = __find_msr_index(vmx, MSR_EFER);
2542 if (index >= 0 && update_transition_efer(vmx, index))
2543 move_msr_up(vmx, index, save_nmsrs++);
2545 vmx->save_nmsrs = save_nmsrs;
2547 if (cpu_has_vmx_msr_bitmap())
2548 vmx_set_msr_bitmap(&vmx->vcpu);
2552 * reads and returns guest's timestamp counter "register"
2553 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2554 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2556 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2558 u64 host_tsc, tsc_offset;
2561 tsc_offset = vmcs_read64(TSC_OFFSET);
2562 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2566 * writes 'offset' into guest's timestamp counter offset register
2568 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2570 if (is_guest_mode(vcpu)) {
2572 * We're here if L1 chose not to trap WRMSR to TSC. According
2573 * to the spec, this should set L1's TSC; The offset that L1
2574 * set for L2 remains unchanged, and still needs to be added
2575 * to the newly set TSC to get L2's TSC.
2577 struct vmcs12 *vmcs12;
2578 /* recalculate vmcs02.TSC_OFFSET: */
2579 vmcs12 = get_vmcs12(vcpu);
2580 vmcs_write64(TSC_OFFSET, offset +
2581 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2582 vmcs12->tsc_offset : 0));
2584 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2585 vmcs_read64(TSC_OFFSET), offset);
2586 vmcs_write64(TSC_OFFSET, offset);
2590 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2592 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2593 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2597 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2598 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2599 * all guests if the "nested" module option is off, and can also be disabled
2600 * for a single guest by disabling its VMX cpuid bit.
2602 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2604 return nested && guest_cpuid_has_vmx(vcpu);
2608 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2609 * returned for the various VMX controls MSRs when nested VMX is enabled.
2610 * The same values should also be used to verify that vmcs12 control fields are
2611 * valid during nested entry from L1 to L2.
2612 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2613 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2614 * bit in the high half is on if the corresponding bit in the control field
2615 * may be on. See also vmx_control_verify().
2617 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2620 * Note that as a general rule, the high half of the MSRs (bits in
2621 * the control fields which may be 1) should be initialized by the
2622 * intersection of the underlying hardware's MSR (i.e., features which
2623 * can be supported) and the list of features we want to expose -
2624 * because they are known to be properly supported in our code.
2625 * Also, usually, the low half of the MSRs (bits which must be 1) can
2626 * be set to 0, meaning that L1 may turn off any of these bits. The
2627 * reason is that if one of these bits is necessary, it will appear
2628 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2629 * fields of vmcs01 and vmcs02, will turn these bits off - and
2630 * nested_vmx_exit_handled() will not pass related exits to L1.
2631 * These rules have exceptions below.
2634 /* pin-based controls */
2635 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2636 vmx->nested.nested_vmx_pinbased_ctls_low,
2637 vmx->nested.nested_vmx_pinbased_ctls_high);
2638 vmx->nested.nested_vmx_pinbased_ctls_low |=
2639 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2640 vmx->nested.nested_vmx_pinbased_ctls_high &=
2641 PIN_BASED_EXT_INTR_MASK |
2642 PIN_BASED_NMI_EXITING |
2643 PIN_BASED_VIRTUAL_NMIS;
2644 vmx->nested.nested_vmx_pinbased_ctls_high |=
2645 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2646 PIN_BASED_VMX_PREEMPTION_TIMER;
2647 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2648 vmx->nested.nested_vmx_pinbased_ctls_high |=
2649 PIN_BASED_POSTED_INTR;
2652 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2653 vmx->nested.nested_vmx_exit_ctls_low,
2654 vmx->nested.nested_vmx_exit_ctls_high);
2655 vmx->nested.nested_vmx_exit_ctls_low =
2656 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2658 vmx->nested.nested_vmx_exit_ctls_high &=
2659 #ifdef CONFIG_X86_64
2660 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2662 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2663 vmx->nested.nested_vmx_exit_ctls_high |=
2664 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2665 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2666 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2668 if (kvm_mpx_supported())
2669 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2671 /* We support free control of debug control saving. */
2672 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2674 /* entry controls */
2675 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2676 vmx->nested.nested_vmx_entry_ctls_low,
2677 vmx->nested.nested_vmx_entry_ctls_high);
2678 vmx->nested.nested_vmx_entry_ctls_low =
2679 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2680 vmx->nested.nested_vmx_entry_ctls_high &=
2681 #ifdef CONFIG_X86_64
2682 VM_ENTRY_IA32E_MODE |
2684 VM_ENTRY_LOAD_IA32_PAT;
2685 vmx->nested.nested_vmx_entry_ctls_high |=
2686 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2687 if (kvm_mpx_supported())
2688 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2690 /* We support free control of debug control loading. */
2691 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2693 /* cpu-based controls */
2694 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2695 vmx->nested.nested_vmx_procbased_ctls_low,
2696 vmx->nested.nested_vmx_procbased_ctls_high);
2697 vmx->nested.nested_vmx_procbased_ctls_low =
2698 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2699 vmx->nested.nested_vmx_procbased_ctls_high &=
2700 CPU_BASED_VIRTUAL_INTR_PENDING |
2701 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2702 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2703 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2704 CPU_BASED_CR3_STORE_EXITING |
2705 #ifdef CONFIG_X86_64
2706 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2708 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2709 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2710 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2711 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2712 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2714 * We can allow some features even when not supported by the
2715 * hardware. For example, L1 can specify an MSR bitmap - and we
2716 * can use it to avoid exits to L1 - even when L0 runs L2
2717 * without MSR bitmaps.
2719 vmx->nested.nested_vmx_procbased_ctls_high |=
2720 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2721 CPU_BASED_USE_MSR_BITMAPS;
2723 /* We support free control of CR3 access interception. */
2724 vmx->nested.nested_vmx_procbased_ctls_low &=
2725 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2727 /* secondary cpu-based controls */
2728 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2729 vmx->nested.nested_vmx_secondary_ctls_low,
2730 vmx->nested.nested_vmx_secondary_ctls_high);
2731 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2732 vmx->nested.nested_vmx_secondary_ctls_high &=
2733 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
2734 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2735 SECONDARY_EXEC_RDTSCP |
2736 SECONDARY_EXEC_DESC |
2737 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2738 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2739 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2740 SECONDARY_EXEC_WBINVD_EXITING |
2741 SECONDARY_EXEC_XSAVES;
2744 /* nested EPT: emulate EPT also to L1 */
2745 vmx->nested.nested_vmx_secondary_ctls_high |=
2746 SECONDARY_EXEC_ENABLE_EPT;
2747 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2748 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2749 if (cpu_has_vmx_ept_execute_only())
2750 vmx->nested.nested_vmx_ept_caps |=
2751 VMX_EPT_EXECUTE_ONLY_BIT;
2752 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2753 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2754 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2755 VMX_EPT_1GB_PAGE_BIT;
2756 if (enable_ept_ad_bits)
2757 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2759 vmx->nested.nested_vmx_ept_caps = 0;
2762 * Old versions of KVM use the single-context version without
2763 * checking for support, so declare that it is supported even
2764 * though it is treated as global context. The alternative is
2765 * not failing the single-context invvpid, and it is worse.
2768 vmx->nested.nested_vmx_secondary_ctls_high |=
2769 SECONDARY_EXEC_ENABLE_VPID;
2770 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2771 VMX_VPID_EXTENT_SUPPORTED_MASK;
2773 vmx->nested.nested_vmx_vpid_caps = 0;
2775 if (enable_unrestricted_guest)
2776 vmx->nested.nested_vmx_secondary_ctls_high |=
2777 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2779 /* miscellaneous data */
2780 rdmsr(MSR_IA32_VMX_MISC,
2781 vmx->nested.nested_vmx_misc_low,
2782 vmx->nested.nested_vmx_misc_high);
2783 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2784 vmx->nested.nested_vmx_misc_low |=
2785 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2786 VMX_MISC_ACTIVITY_HLT;
2787 vmx->nested.nested_vmx_misc_high = 0;
2790 * This MSR reports some information about VMX support. We
2791 * should return information about the VMX we emulate for the
2792 * guest, and the VMCS structure we give it - not about the
2793 * VMX support of the underlying hardware.
2795 vmx->nested.nested_vmx_basic =
2797 VMX_BASIC_TRUE_CTLS |
2798 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2799 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2801 if (cpu_has_vmx_basic_inout())
2802 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2805 * These MSRs specify bits which the guest must keep fixed on
2806 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2807 * We picked the standard core2 setting.
2809 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2810 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2811 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2812 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2814 /* These MSRs specify bits which the guest must keep fixed off. */
2815 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2816 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2818 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2819 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2823 * if fixed0[i] == 1: val[i] must be 1
2824 * if fixed1[i] == 0: val[i] must be 0
2826 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2828 return ((val & fixed1) | fixed0) == val;
2831 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2833 return fixed_bits_valid(control, low, high);
2836 static inline u64 vmx_control_msr(u32 low, u32 high)
2838 return low | ((u64)high << 32);
2841 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2846 return (superset | subset) == superset;
2849 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2851 const u64 feature_and_reserved =
2852 /* feature (except bit 48; see below) */
2853 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2855 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2856 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2858 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2862 * KVM does not emulate a version of VMX that constrains physical
2863 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2865 if (data & BIT_ULL(48))
2868 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2869 vmx_basic_vmcs_revision_id(data))
2872 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2875 vmx->nested.nested_vmx_basic = data;
2880 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2885 switch (msr_index) {
2886 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2887 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2888 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2890 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2891 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2892 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2894 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2895 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2896 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2898 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2899 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2900 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2902 case MSR_IA32_VMX_PROCBASED_CTLS2:
2903 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2904 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2910 supported = vmx_control_msr(*lowp, *highp);
2912 /* Check must-be-1 bits are still 1. */
2913 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2916 /* Check must-be-0 bits are still 0. */
2917 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2921 *highp = data >> 32;
2925 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2927 const u64 feature_and_reserved_bits =
2929 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2930 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2932 GENMASK_ULL(13, 9) | BIT_ULL(31);
2935 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2936 vmx->nested.nested_vmx_misc_high);
2938 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2941 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2942 PIN_BASED_VMX_PREEMPTION_TIMER) &&
2943 vmx_misc_preemption_timer_rate(data) !=
2944 vmx_misc_preemption_timer_rate(vmx_misc))
2947 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2950 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2953 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2956 vmx->nested.nested_vmx_misc_low = data;
2957 vmx->nested.nested_vmx_misc_high = data >> 32;
2961 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2963 u64 vmx_ept_vpid_cap;
2965 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2966 vmx->nested.nested_vmx_vpid_caps);
2968 /* Every bit is either reserved or a feature bit. */
2969 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2972 vmx->nested.nested_vmx_ept_caps = data;
2973 vmx->nested.nested_vmx_vpid_caps = data >> 32;
2977 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2981 switch (msr_index) {
2982 case MSR_IA32_VMX_CR0_FIXED0:
2983 msr = &vmx->nested.nested_vmx_cr0_fixed0;
2985 case MSR_IA32_VMX_CR4_FIXED0:
2986 msr = &vmx->nested.nested_vmx_cr4_fixed0;
2993 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
2994 * must be 1 in the restored value.
2996 if (!is_bitwise_subset(data, *msr, -1ULL))
3004 * Called when userspace is restoring VMX MSRs.
3006 * Returns 0 on success, non-0 otherwise.
3008 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3010 struct vcpu_vmx *vmx = to_vmx(vcpu);
3012 switch (msr_index) {
3013 case MSR_IA32_VMX_BASIC:
3014 return vmx_restore_vmx_basic(vmx, data);
3015 case MSR_IA32_VMX_PINBASED_CTLS:
3016 case MSR_IA32_VMX_PROCBASED_CTLS:
3017 case MSR_IA32_VMX_EXIT_CTLS:
3018 case MSR_IA32_VMX_ENTRY_CTLS:
3020 * The "non-true" VMX capability MSRs are generated from the
3021 * "true" MSRs, so we do not support restoring them directly.
3023 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3024 * should restore the "true" MSRs with the must-be-1 bits
3025 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3026 * DEFAULT SETTINGS".
3029 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3030 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3031 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3032 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3033 case MSR_IA32_VMX_PROCBASED_CTLS2:
3034 return vmx_restore_control_msr(vmx, msr_index, data);
3035 case MSR_IA32_VMX_MISC:
3036 return vmx_restore_vmx_misc(vmx, data);
3037 case MSR_IA32_VMX_CR0_FIXED0:
3038 case MSR_IA32_VMX_CR4_FIXED0:
3039 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3040 case MSR_IA32_VMX_CR0_FIXED1:
3041 case MSR_IA32_VMX_CR4_FIXED1:
3043 * These MSRs are generated based on the vCPU's CPUID, so we
3044 * do not support restoring them directly.
3047 case MSR_IA32_VMX_EPT_VPID_CAP:
3048 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3049 case MSR_IA32_VMX_VMCS_ENUM:
3050 vmx->nested.nested_vmx_vmcs_enum = data;
3054 * The rest of the VMX capability MSRs do not support restore.
3060 /* Returns 0 on success, non-0 otherwise. */
3061 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3063 struct vcpu_vmx *vmx = to_vmx(vcpu);
3065 switch (msr_index) {
3066 case MSR_IA32_VMX_BASIC:
3067 *pdata = vmx->nested.nested_vmx_basic;
3069 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3070 case MSR_IA32_VMX_PINBASED_CTLS:
3071 *pdata = vmx_control_msr(
3072 vmx->nested.nested_vmx_pinbased_ctls_low,
3073 vmx->nested.nested_vmx_pinbased_ctls_high);
3074 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3075 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3077 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3078 case MSR_IA32_VMX_PROCBASED_CTLS:
3079 *pdata = vmx_control_msr(
3080 vmx->nested.nested_vmx_procbased_ctls_low,
3081 vmx->nested.nested_vmx_procbased_ctls_high);
3082 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3083 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3085 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3086 case MSR_IA32_VMX_EXIT_CTLS:
3087 *pdata = vmx_control_msr(
3088 vmx->nested.nested_vmx_exit_ctls_low,
3089 vmx->nested.nested_vmx_exit_ctls_high);
3090 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3091 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3093 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3094 case MSR_IA32_VMX_ENTRY_CTLS:
3095 *pdata = vmx_control_msr(
3096 vmx->nested.nested_vmx_entry_ctls_low,
3097 vmx->nested.nested_vmx_entry_ctls_high);
3098 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3099 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3101 case MSR_IA32_VMX_MISC:
3102 *pdata = vmx_control_msr(
3103 vmx->nested.nested_vmx_misc_low,
3104 vmx->nested.nested_vmx_misc_high);
3106 case MSR_IA32_VMX_CR0_FIXED0:
3107 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3109 case MSR_IA32_VMX_CR0_FIXED1:
3110 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3112 case MSR_IA32_VMX_CR4_FIXED0:
3113 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3115 case MSR_IA32_VMX_CR4_FIXED1:
3116 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3118 case MSR_IA32_VMX_VMCS_ENUM:
3119 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3121 case MSR_IA32_VMX_PROCBASED_CTLS2:
3122 *pdata = vmx_control_msr(
3123 vmx->nested.nested_vmx_secondary_ctls_low,
3124 vmx->nested.nested_vmx_secondary_ctls_high);
3126 case MSR_IA32_VMX_EPT_VPID_CAP:
3127 *pdata = vmx->nested.nested_vmx_ept_caps |
3128 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3137 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3140 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3142 return !(val & ~valid_bits);
3146 * Reads an msr value (of 'msr_index') into 'pdata'.
3147 * Returns 0 on success, non-0 otherwise.
3148 * Assumes vcpu_load() was already called.
3150 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3152 struct shared_msr_entry *msr;
3154 switch (msr_info->index) {
3155 #ifdef CONFIG_X86_64
3157 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3160 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3162 case MSR_KERNEL_GS_BASE:
3163 vmx_load_host_state(to_vmx(vcpu));
3164 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3168 return kvm_get_msr_common(vcpu, msr_info);
3170 msr_info->data = guest_read_tsc(vcpu);
3172 case MSR_IA32_SYSENTER_CS:
3173 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3175 case MSR_IA32_SYSENTER_EIP:
3176 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3178 case MSR_IA32_SYSENTER_ESP:
3179 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3181 case MSR_IA32_BNDCFGS:
3182 if (!kvm_mpx_supported())
3184 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3186 case MSR_IA32_MCG_EXT_CTL:
3187 if (!msr_info->host_initiated &&
3188 !(to_vmx(vcpu)->msr_ia32_feature_control &
3189 FEATURE_CONTROL_LMCE))
3191 msr_info->data = vcpu->arch.mcg_ext_ctl;
3193 case MSR_IA32_FEATURE_CONTROL:
3194 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3196 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3197 if (!nested_vmx_allowed(vcpu))
3199 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3201 if (!vmx_xsaves_supported())
3203 msr_info->data = vcpu->arch.ia32_xss;
3206 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3208 /* Otherwise falls through */
3210 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3212 msr_info->data = msr->data;
3215 return kvm_get_msr_common(vcpu, msr_info);
3221 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3224 * Writes msr value into into the appropriate "register".
3225 * Returns 0 on success, non-0 otherwise.
3226 * Assumes vcpu_load() was already called.
3228 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3230 struct vcpu_vmx *vmx = to_vmx(vcpu);
3231 struct shared_msr_entry *msr;
3233 u32 msr_index = msr_info->index;
3234 u64 data = msr_info->data;
3236 switch (msr_index) {
3238 ret = kvm_set_msr_common(vcpu, msr_info);
3240 #ifdef CONFIG_X86_64
3242 vmx_segment_cache_clear(vmx);
3243 vmcs_writel(GUEST_FS_BASE, data);
3246 vmx_segment_cache_clear(vmx);
3247 vmcs_writel(GUEST_GS_BASE, data);
3249 case MSR_KERNEL_GS_BASE:
3250 vmx_load_host_state(vmx);
3251 vmx->msr_guest_kernel_gs_base = data;
3254 case MSR_IA32_SYSENTER_CS:
3255 vmcs_write32(GUEST_SYSENTER_CS, data);
3257 case MSR_IA32_SYSENTER_EIP:
3258 vmcs_writel(GUEST_SYSENTER_EIP, data);
3260 case MSR_IA32_SYSENTER_ESP:
3261 vmcs_writel(GUEST_SYSENTER_ESP, data);
3263 case MSR_IA32_BNDCFGS:
3264 if (!kvm_mpx_supported())
3266 vmcs_write64(GUEST_BNDCFGS, data);
3269 kvm_write_tsc(vcpu, msr_info);
3271 case MSR_IA32_CR_PAT:
3272 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3273 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3275 vmcs_write64(GUEST_IA32_PAT, data);
3276 vcpu->arch.pat = data;
3279 ret = kvm_set_msr_common(vcpu, msr_info);
3281 case MSR_IA32_TSC_ADJUST:
3282 ret = kvm_set_msr_common(vcpu, msr_info);
3284 case MSR_IA32_MCG_EXT_CTL:
3285 if ((!msr_info->host_initiated &&
3286 !(to_vmx(vcpu)->msr_ia32_feature_control &
3287 FEATURE_CONTROL_LMCE)) ||
3288 (data & ~MCG_EXT_CTL_LMCE_EN))
3290 vcpu->arch.mcg_ext_ctl = data;
3292 case MSR_IA32_FEATURE_CONTROL:
3293 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3294 (to_vmx(vcpu)->msr_ia32_feature_control &
3295 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3297 vmx->msr_ia32_feature_control = data;
3298 if (msr_info->host_initiated && data == 0)
3299 vmx_leave_nested(vcpu);
3301 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3302 if (!msr_info->host_initiated)
3303 return 1; /* they are read-only */
3304 if (!nested_vmx_allowed(vcpu))
3306 return vmx_set_vmx_msr(vcpu, msr_index, data);
3308 if (!vmx_xsaves_supported())
3311 * The only supported bit as of Skylake is bit 8, but
3312 * it is not supported on KVM.
3316 vcpu->arch.ia32_xss = data;
3317 if (vcpu->arch.ia32_xss != host_xss)
3318 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3319 vcpu->arch.ia32_xss, host_xss);
3321 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3324 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3326 /* Check reserved bit, higher 32 bits should be zero */
3327 if ((data >> 32) != 0)
3329 /* Otherwise falls through */
3331 msr = find_msr_entry(vmx, msr_index);
3333 u64 old_msr_data = msr->data;
3335 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3337 ret = kvm_set_shared_msr(msr->index, msr->data,
3341 msr->data = old_msr_data;
3345 ret = kvm_set_msr_common(vcpu, msr_info);
3351 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3353 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3356 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3359 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3361 case VCPU_EXREG_PDPTR:
3363 ept_save_pdptrs(vcpu);
3370 static __init int cpu_has_kvm_support(void)
3372 return cpu_has_vmx();
3375 static __init int vmx_disabled_by_bios(void)
3379 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3380 if (msr & FEATURE_CONTROL_LOCKED) {
3381 /* launched w/ TXT and VMX disabled */
3382 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3385 /* launched w/o TXT and VMX only enabled w/ TXT */
3386 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3387 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3388 && !tboot_enabled()) {
3389 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3390 "activate TXT before enabling KVM\n");
3393 /* launched w/o TXT and VMX disabled */
3394 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3395 && !tboot_enabled())
3402 static void kvm_cpu_vmxon(u64 addr)
3404 cr4_set_bits(X86_CR4_VMXE);
3405 intel_pt_handle_vmx(1);
3407 asm volatile (ASM_VMX_VMXON_RAX
3408 : : "a"(&addr), "m"(addr)
3412 static int hardware_enable(void)
3414 int cpu = raw_smp_processor_id();
3415 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3418 if (cr4_read_shadow() & X86_CR4_VMXE)
3421 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3422 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3423 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3426 * Now we can enable the vmclear operation in kdump
3427 * since the loaded_vmcss_on_cpu list on this cpu
3428 * has been initialized.
3430 * Though the cpu is not in VMX operation now, there
3431 * is no problem to enable the vmclear operation
3432 * for the loaded_vmcss_on_cpu list is empty!
3434 crash_enable_local_vmclear(cpu);
3436 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3438 test_bits = FEATURE_CONTROL_LOCKED;
3439 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3440 if (tboot_enabled())
3441 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3443 if ((old & test_bits) != test_bits) {
3444 /* enable and lock */
3445 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3447 kvm_cpu_vmxon(phys_addr);
3450 native_store_gdt(this_cpu_ptr(&host_gdt));
3455 static void vmclear_local_loaded_vmcss(void)
3457 int cpu = raw_smp_processor_id();
3458 struct loaded_vmcs *v, *n;
3460 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3461 loaded_vmcss_on_cpu_link)
3462 __loaded_vmcs_clear(v);
3466 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3469 static void kvm_cpu_vmxoff(void)
3471 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3473 intel_pt_handle_vmx(0);
3474 cr4_clear_bits(X86_CR4_VMXE);
3477 static void hardware_disable(void)
3479 vmclear_local_loaded_vmcss();
3483 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3484 u32 msr, u32 *result)
3486 u32 vmx_msr_low, vmx_msr_high;
3487 u32 ctl = ctl_min | ctl_opt;
3489 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3491 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3492 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3494 /* Ensure minimum (required) set of control bits are supported. */
3502 static __init bool allow_1_setting(u32 msr, u32 ctl)
3504 u32 vmx_msr_low, vmx_msr_high;
3506 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3507 return vmx_msr_high & ctl;
3510 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3512 u32 vmx_msr_low, vmx_msr_high;
3513 u32 min, opt, min2, opt2;
3514 u32 _pin_based_exec_control = 0;
3515 u32 _cpu_based_exec_control = 0;
3516 u32 _cpu_based_2nd_exec_control = 0;
3517 u32 _vmexit_control = 0;
3518 u32 _vmentry_control = 0;
3520 min = CPU_BASED_HLT_EXITING |
3521 #ifdef CONFIG_X86_64
3522 CPU_BASED_CR8_LOAD_EXITING |
3523 CPU_BASED_CR8_STORE_EXITING |
3525 CPU_BASED_CR3_LOAD_EXITING |
3526 CPU_BASED_CR3_STORE_EXITING |
3527 CPU_BASED_USE_IO_BITMAPS |
3528 CPU_BASED_MOV_DR_EXITING |
3529 CPU_BASED_USE_TSC_OFFSETING |
3530 CPU_BASED_INVLPG_EXITING |
3531 CPU_BASED_RDPMC_EXITING;
3533 if (!kvm_mwait_in_guest())
3534 min |= CPU_BASED_MWAIT_EXITING |
3535 CPU_BASED_MONITOR_EXITING;
3537 opt = CPU_BASED_TPR_SHADOW |
3538 CPU_BASED_USE_MSR_BITMAPS |
3539 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3540 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3541 &_cpu_based_exec_control) < 0)
3543 #ifdef CONFIG_X86_64
3544 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3545 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3546 ~CPU_BASED_CR8_STORE_EXITING;
3548 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3550 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3551 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3552 SECONDARY_EXEC_WBINVD_EXITING |
3553 SECONDARY_EXEC_ENABLE_VPID |
3554 SECONDARY_EXEC_ENABLE_EPT |
3555 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3556 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3557 SECONDARY_EXEC_RDTSCP |
3558 SECONDARY_EXEC_ENABLE_INVPCID |
3559 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3560 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3561 SECONDARY_EXEC_SHADOW_VMCS |
3562 SECONDARY_EXEC_XSAVES |
3563 SECONDARY_EXEC_ENABLE_PML |
3564 SECONDARY_EXEC_TSC_SCALING;
3565 if (adjust_vmx_controls(min2, opt2,
3566 MSR_IA32_VMX_PROCBASED_CTLS2,
3567 &_cpu_based_2nd_exec_control) < 0)
3570 #ifndef CONFIG_X86_64
3571 if (!(_cpu_based_2nd_exec_control &
3572 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3573 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3576 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3577 _cpu_based_2nd_exec_control &= ~(
3578 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3579 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3580 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3582 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3583 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3585 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3586 CPU_BASED_CR3_STORE_EXITING |
3587 CPU_BASED_INVLPG_EXITING);
3588 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3589 vmx_capability.ept, vmx_capability.vpid);
3592 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3593 #ifdef CONFIG_X86_64
3594 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3596 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3597 VM_EXIT_CLEAR_BNDCFGS;
3598 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3599 &_vmexit_control) < 0)
3602 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3603 PIN_BASED_VIRTUAL_NMIS;
3604 opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3605 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3606 &_pin_based_exec_control) < 0)
3609 if (cpu_has_broken_vmx_preemption_timer())
3610 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3611 if (!(_cpu_based_2nd_exec_control &
3612 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3613 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3615 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3616 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3617 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3618 &_vmentry_control) < 0)
3621 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3623 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3624 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3627 #ifdef CONFIG_X86_64
3628 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3629 if (vmx_msr_high & (1u<<16))
3633 /* Require Write-Back (WB) memory type for VMCS accesses. */
3634 if (((vmx_msr_high >> 18) & 15) != 6)
3637 vmcs_conf->size = vmx_msr_high & 0x1fff;
3638 vmcs_conf->order = get_order(vmcs_conf->size);
3639 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3640 vmcs_conf->revision_id = vmx_msr_low;
3642 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3643 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3644 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3645 vmcs_conf->vmexit_ctrl = _vmexit_control;
3646 vmcs_conf->vmentry_ctrl = _vmentry_control;
3648 cpu_has_load_ia32_efer =
3649 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3650 VM_ENTRY_LOAD_IA32_EFER)
3651 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3652 VM_EXIT_LOAD_IA32_EFER);
3654 cpu_has_load_perf_global_ctrl =
3655 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3656 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3657 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3658 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3661 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3662 * but due to errata below it can't be used. Workaround is to use
3663 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3665 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3670 * BC86,AAY89,BD102 (model 44)
3674 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3675 switch (boot_cpu_data.x86_model) {
3681 cpu_has_load_perf_global_ctrl = false;
3682 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3683 "does not work properly. Using workaround\n");
3690 if (boot_cpu_has(X86_FEATURE_XSAVES))
3691 rdmsrl(MSR_IA32_XSS, host_xss);
3696 static struct vmcs *alloc_vmcs_cpu(int cpu)
3698 int node = cpu_to_node(cpu);
3702 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3705 vmcs = page_address(pages);
3706 memset(vmcs, 0, vmcs_config.size);
3707 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3711 static struct vmcs *alloc_vmcs(void)
3713 return alloc_vmcs_cpu(raw_smp_processor_id());
3716 static void free_vmcs(struct vmcs *vmcs)
3718 free_pages((unsigned long)vmcs, vmcs_config.order);
3722 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3724 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3726 if (!loaded_vmcs->vmcs)
3728 loaded_vmcs_clear(loaded_vmcs);
3729 free_vmcs(loaded_vmcs->vmcs);
3730 loaded_vmcs->vmcs = NULL;
3731 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3734 static void free_kvm_area(void)
3738 for_each_possible_cpu(cpu) {
3739 free_vmcs(per_cpu(vmxarea, cpu));
3740 per_cpu(vmxarea, cpu) = NULL;
3744 static void init_vmcs_shadow_fields(void)
3748 /* No checks for read only fields yet */
3750 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3751 switch (shadow_read_write_fields[i]) {
3753 if (!kvm_mpx_supported())
3761 shadow_read_write_fields[j] =
3762 shadow_read_write_fields[i];
3765 max_shadow_read_write_fields = j;
3767 /* shadowed fields guest access without vmexit */
3768 for (i = 0; i < max_shadow_read_write_fields; i++) {
3769 clear_bit(shadow_read_write_fields[i],
3770 vmx_vmwrite_bitmap);
3771 clear_bit(shadow_read_write_fields[i],
3774 for (i = 0; i < max_shadow_read_only_fields; i++)
3775 clear_bit(shadow_read_only_fields[i],
3779 static __init int alloc_kvm_area(void)
3783 for_each_possible_cpu(cpu) {
3786 vmcs = alloc_vmcs_cpu(cpu);
3792 per_cpu(vmxarea, cpu) = vmcs;
3797 static bool emulation_required(struct kvm_vcpu *vcpu)
3799 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3802 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3803 struct kvm_segment *save)
3805 if (!emulate_invalid_guest_state) {
3807 * CS and SS RPL should be equal during guest entry according
3808 * to VMX spec, but in reality it is not always so. Since vcpu
3809 * is in the middle of the transition from real mode to
3810 * protected mode it is safe to assume that RPL 0 is a good
3813 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3814 save->selector &= ~SEGMENT_RPL_MASK;
3815 save->dpl = save->selector & SEGMENT_RPL_MASK;
3818 vmx_set_segment(vcpu, save, seg);
3821 static void enter_pmode(struct kvm_vcpu *vcpu)
3823 unsigned long flags;
3824 struct vcpu_vmx *vmx = to_vmx(vcpu);
3827 * Update real mode segment cache. It may be not up-to-date if sement
3828 * register was written while vcpu was in a guest mode.
3830 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3831 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3832 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3833 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3834 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3835 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3837 vmx->rmode.vm86_active = 0;
3839 vmx_segment_cache_clear(vmx);
3841 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3843 flags = vmcs_readl(GUEST_RFLAGS);
3844 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3845 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3846 vmcs_writel(GUEST_RFLAGS, flags);
3848 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3849 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3851 update_exception_bitmap(vcpu);
3853 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3854 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3855 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3856 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3857 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3858 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3861 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3863 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3864 struct kvm_segment var = *save;
3867 if (seg == VCPU_SREG_CS)
3870 if (!emulate_invalid_guest_state) {
3871 var.selector = var.base >> 4;
3872 var.base = var.base & 0xffff0;
3882 if (save->base & 0xf)
3883 printk_once(KERN_WARNING "kvm: segment base is not "
3884 "paragraph aligned when entering "
3885 "protected mode (seg=%d)", seg);
3888 vmcs_write16(sf->selector, var.selector);
3889 vmcs_writel(sf->base, var.base);
3890 vmcs_write32(sf->limit, var.limit);
3891 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3894 static void enter_rmode(struct kvm_vcpu *vcpu)
3896 unsigned long flags;
3897 struct vcpu_vmx *vmx = to_vmx(vcpu);
3899 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3900 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3901 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3902 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3903 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3904 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3905 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3907 vmx->rmode.vm86_active = 1;
3910 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3911 * vcpu. Warn the user that an update is overdue.
3913 if (!vcpu->kvm->arch.tss_addr)
3914 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3915 "called before entering vcpu\n");
3917 vmx_segment_cache_clear(vmx);
3919 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3920 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3921 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3923 flags = vmcs_readl(GUEST_RFLAGS);
3924 vmx->rmode.save_rflags = flags;
3926 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3928 vmcs_writel(GUEST_RFLAGS, flags);
3929 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3930 update_exception_bitmap(vcpu);
3932 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3933 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3934 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3935 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3936 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3937 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3939 kvm_mmu_reset_context(vcpu);
3942 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3944 struct vcpu_vmx *vmx = to_vmx(vcpu);
3945 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3951 * Force kernel_gs_base reloading before EFER changes, as control
3952 * of this msr depends on is_long_mode().
3954 vmx_load_host_state(to_vmx(vcpu));
3955 vcpu->arch.efer = efer;
3956 if (efer & EFER_LMA) {
3957 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3960 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3962 msr->data = efer & ~EFER_LME;
3967 #ifdef CONFIG_X86_64
3969 static void enter_lmode(struct kvm_vcpu *vcpu)
3973 vmx_segment_cache_clear(to_vmx(vcpu));
3975 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3976 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3977 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3979 vmcs_write32(GUEST_TR_AR_BYTES,
3980 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3981 | VMX_AR_TYPE_BUSY_64_TSS);
3983 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3986 static void exit_lmode(struct kvm_vcpu *vcpu)
3988 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3989 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3994 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3997 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3999 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4001 vpid_sync_context(vpid);
4005 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4007 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4010 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4013 vmx_flush_tlb(vcpu);
4016 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4018 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4020 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4021 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4024 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4026 if (enable_ept && is_paging(vcpu))
4027 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4028 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4031 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4033 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4035 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4036 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4039 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4041 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4043 if (!test_bit(VCPU_EXREG_PDPTR,
4044 (unsigned long *)&vcpu->arch.regs_dirty))
4047 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4048 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4049 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4050 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4051 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4055 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4057 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4059 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4060 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4061 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4062 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4063 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4066 __set_bit(VCPU_EXREG_PDPTR,
4067 (unsigned long *)&vcpu->arch.regs_avail);
4068 __set_bit(VCPU_EXREG_PDPTR,
4069 (unsigned long *)&vcpu->arch.regs_dirty);
4072 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4074 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4075 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4076 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4078 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4079 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4080 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4081 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4083 return fixed_bits_valid(val, fixed0, fixed1);
4086 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4088 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4089 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4091 return fixed_bits_valid(val, fixed0, fixed1);
4094 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4096 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4097 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4099 return fixed_bits_valid(val, fixed0, fixed1);
4102 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4103 #define nested_guest_cr4_valid nested_cr4_valid
4104 #define nested_host_cr4_valid nested_cr4_valid
4106 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4108 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4110 struct kvm_vcpu *vcpu)
4112 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4113 vmx_decache_cr3(vcpu);
4114 if (!(cr0 & X86_CR0_PG)) {
4115 /* From paging/starting to nonpaging */
4116 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4117 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4118 (CPU_BASED_CR3_LOAD_EXITING |
4119 CPU_BASED_CR3_STORE_EXITING));
4120 vcpu->arch.cr0 = cr0;
4121 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4122 } else if (!is_paging(vcpu)) {
4123 /* From nonpaging to paging */
4124 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4125 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4126 ~(CPU_BASED_CR3_LOAD_EXITING |
4127 CPU_BASED_CR3_STORE_EXITING));
4128 vcpu->arch.cr0 = cr0;
4129 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4132 if (!(cr0 & X86_CR0_WP))
4133 *hw_cr0 &= ~X86_CR0_WP;
4136 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4138 struct vcpu_vmx *vmx = to_vmx(vcpu);
4139 unsigned long hw_cr0;
4141 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4142 if (enable_unrestricted_guest)
4143 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4145 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4147 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4150 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4154 #ifdef CONFIG_X86_64
4155 if (vcpu->arch.efer & EFER_LME) {
4156 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4158 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4164 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4166 vmcs_writel(CR0_READ_SHADOW, cr0);
4167 vmcs_writel(GUEST_CR0, hw_cr0);
4168 vcpu->arch.cr0 = cr0;
4170 /* depends on vcpu->arch.cr0 to be set to a new value */
4171 vmx->emulation_required = emulation_required(vcpu);
4174 static u64 construct_eptp(unsigned long root_hpa)
4178 /* TODO write the value reading from MSR */
4179 eptp = VMX_EPT_DEFAULT_MT |
4180 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4181 if (enable_ept_ad_bits)
4182 eptp |= VMX_EPT_AD_ENABLE_BIT;
4183 eptp |= (root_hpa & PAGE_MASK);
4188 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4190 unsigned long guest_cr3;
4195 eptp = construct_eptp(cr3);
4196 vmcs_write64(EPT_POINTER, eptp);
4197 if (is_paging(vcpu) || is_guest_mode(vcpu))
4198 guest_cr3 = kvm_read_cr3(vcpu);
4200 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4201 ept_load_pdptrs(vcpu);
4204 vmx_flush_tlb(vcpu);
4205 vmcs_writel(GUEST_CR3, guest_cr3);
4208 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4211 * Pass through host's Machine Check Enable value to hw_cr4, which
4212 * is in force while we are in guest mode. Do not let guests control
4213 * this bit, even if host CR4.MCE == 0.
4215 unsigned long hw_cr4 =
4216 (cr4_read_shadow() & X86_CR4_MCE) |
4217 (cr4 & ~X86_CR4_MCE) |
4218 (to_vmx(vcpu)->rmode.vm86_active ?
4219 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4221 if (cr4 & X86_CR4_VMXE) {
4223 * To use VMXON (and later other VMX instructions), a guest
4224 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4225 * So basically the check on whether to allow nested VMX
4228 if (!nested_vmx_allowed(vcpu))
4232 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4235 vcpu->arch.cr4 = cr4;
4237 if (!is_paging(vcpu)) {
4238 hw_cr4 &= ~X86_CR4_PAE;
4239 hw_cr4 |= X86_CR4_PSE;
4240 } else if (!(cr4 & X86_CR4_PAE)) {
4241 hw_cr4 &= ~X86_CR4_PAE;
4245 if (!enable_unrestricted_guest && !is_paging(vcpu))
4247 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4248 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4249 * to be manually disabled when guest switches to non-paging
4252 * If !enable_unrestricted_guest, the CPU is always running
4253 * with CR0.PG=1 and CR4 needs to be modified.
4254 * If enable_unrestricted_guest, the CPU automatically
4255 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4257 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4259 vmcs_writel(CR4_READ_SHADOW, cr4);
4260 vmcs_writel(GUEST_CR4, hw_cr4);
4264 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4265 struct kvm_segment *var, int seg)
4267 struct vcpu_vmx *vmx = to_vmx(vcpu);
4270 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4271 *var = vmx->rmode.segs[seg];
4272 if (seg == VCPU_SREG_TR
4273 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4275 var->base = vmx_read_guest_seg_base(vmx, seg);
4276 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4279 var->base = vmx_read_guest_seg_base(vmx, seg);
4280 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4281 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4282 ar = vmx_read_guest_seg_ar(vmx, seg);
4283 var->unusable = (ar >> 16) & 1;
4284 var->type = ar & 15;
4285 var->s = (ar >> 4) & 1;
4286 var->dpl = (ar >> 5) & 3;
4288 * Some userspaces do not preserve unusable property. Since usable
4289 * segment has to be present according to VMX spec we can use present
4290 * property to amend userspace bug by making unusable segment always
4291 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4292 * segment as unusable.
4294 var->present = !var->unusable;
4295 var->avl = (ar >> 12) & 1;
4296 var->l = (ar >> 13) & 1;
4297 var->db = (ar >> 14) & 1;
4298 var->g = (ar >> 15) & 1;
4301 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4303 struct kvm_segment s;
4305 if (to_vmx(vcpu)->rmode.vm86_active) {
4306 vmx_get_segment(vcpu, &s, seg);
4309 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4312 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4314 struct vcpu_vmx *vmx = to_vmx(vcpu);
4316 if (unlikely(vmx->rmode.vm86_active))
4319 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4320 return VMX_AR_DPL(ar);
4324 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4328 if (var->unusable || !var->present)
4331 ar = var->type & 15;
4332 ar |= (var->s & 1) << 4;
4333 ar |= (var->dpl & 3) << 5;
4334 ar |= (var->present & 1) << 7;
4335 ar |= (var->avl & 1) << 12;
4336 ar |= (var->l & 1) << 13;
4337 ar |= (var->db & 1) << 14;
4338 ar |= (var->g & 1) << 15;
4344 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4345 struct kvm_segment *var, int seg)
4347 struct vcpu_vmx *vmx = to_vmx(vcpu);
4348 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4350 vmx_segment_cache_clear(vmx);
4352 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4353 vmx->rmode.segs[seg] = *var;
4354 if (seg == VCPU_SREG_TR)
4355 vmcs_write16(sf->selector, var->selector);
4357 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4361 vmcs_writel(sf->base, var->base);
4362 vmcs_write32(sf->limit, var->limit);
4363 vmcs_write16(sf->selector, var->selector);
4366 * Fix the "Accessed" bit in AR field of segment registers for older
4368 * IA32 arch specifies that at the time of processor reset the
4369 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4370 * is setting it to 0 in the userland code. This causes invalid guest
4371 * state vmexit when "unrestricted guest" mode is turned on.
4372 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4373 * tree. Newer qemu binaries with that qemu fix would not need this
4376 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4377 var->type |= 0x1; /* Accessed */
4379 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4382 vmx->emulation_required = emulation_required(vcpu);
4385 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4387 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4389 *db = (ar >> 14) & 1;
4390 *l = (ar >> 13) & 1;
4393 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4395 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4396 dt->address = vmcs_readl(GUEST_IDTR_BASE);
4399 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4401 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4402 vmcs_writel(GUEST_IDTR_BASE, dt->address);
4405 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4407 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4408 dt->address = vmcs_readl(GUEST_GDTR_BASE);
4411 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4413 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4414 vmcs_writel(GUEST_GDTR_BASE, dt->address);
4417 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4419 struct kvm_segment var;
4422 vmx_get_segment(vcpu, &var, seg);
4424 if (seg == VCPU_SREG_CS)
4426 ar = vmx_segment_access_rights(&var);
4428 if (var.base != (var.selector << 4))
4430 if (var.limit != 0xffff)
4438 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4440 struct kvm_segment cs;
4441 unsigned int cs_rpl;
4443 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4444 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4448 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4452 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4453 if (cs.dpl > cs_rpl)
4456 if (cs.dpl != cs_rpl)
4462 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4466 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4468 struct kvm_segment ss;
4469 unsigned int ss_rpl;
4471 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4472 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4476 if (ss.type != 3 && ss.type != 7)
4480 if (ss.dpl != ss_rpl) /* DPL != RPL */
4488 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4490 struct kvm_segment var;
4493 vmx_get_segment(vcpu, &var, seg);
4494 rpl = var.selector & SEGMENT_RPL_MASK;
4502 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4503 if (var.dpl < rpl) /* DPL < RPL */
4507 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4513 static bool tr_valid(struct kvm_vcpu *vcpu)
4515 struct kvm_segment tr;
4517 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4521 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4523 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4531 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4533 struct kvm_segment ldtr;
4535 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4539 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4549 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4551 struct kvm_segment cs, ss;
4553 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4554 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4556 return ((cs.selector & SEGMENT_RPL_MASK) ==
4557 (ss.selector & SEGMENT_RPL_MASK));
4561 * Check if guest state is valid. Returns true if valid, false if
4563 * We assume that registers are always usable
4565 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4567 if (enable_unrestricted_guest)
4570 /* real mode guest state checks */
4571 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4572 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4574 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4576 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4578 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4580 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4582 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4585 /* protected mode guest state checks */
4586 if (!cs_ss_rpl_check(vcpu))
4588 if (!code_segment_valid(vcpu))
4590 if (!stack_segment_valid(vcpu))
4592 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4594 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4596 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4598 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4600 if (!tr_valid(vcpu))
4602 if (!ldtr_valid(vcpu))
4606 * - Add checks on RIP
4607 * - Add checks on RFLAGS
4613 static int init_rmode_tss(struct kvm *kvm)
4619 idx = srcu_read_lock(&kvm->srcu);
4620 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4621 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4624 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4625 r = kvm_write_guest_page(kvm, fn++, &data,
4626 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4629 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4632 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4636 r = kvm_write_guest_page(kvm, fn, &data,
4637 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4640 srcu_read_unlock(&kvm->srcu, idx);
4644 static int init_rmode_identity_map(struct kvm *kvm)
4647 kvm_pfn_t identity_map_pfn;
4653 /* Protect kvm->arch.ept_identity_pagetable_done. */
4654 mutex_lock(&kvm->slots_lock);
4656 if (likely(kvm->arch.ept_identity_pagetable_done))
4659 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4661 r = alloc_identity_pagetable(kvm);
4665 idx = srcu_read_lock(&kvm->srcu);
4666 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4669 /* Set up identity-mapping pagetable for EPT in real mode */
4670 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4671 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4672 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4673 r = kvm_write_guest_page(kvm, identity_map_pfn,
4674 &tmp, i * sizeof(tmp), sizeof(tmp));
4678 kvm->arch.ept_identity_pagetable_done = true;
4681 srcu_read_unlock(&kvm->srcu, idx);
4684 mutex_unlock(&kvm->slots_lock);
4688 static void seg_setup(int seg)
4690 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4693 vmcs_write16(sf->selector, 0);
4694 vmcs_writel(sf->base, 0);
4695 vmcs_write32(sf->limit, 0xffff);
4697 if (seg == VCPU_SREG_CS)
4698 ar |= 0x08; /* code segment */
4700 vmcs_write32(sf->ar_bytes, ar);
4703 static int alloc_apic_access_page(struct kvm *kvm)
4708 mutex_lock(&kvm->slots_lock);
4709 if (kvm->arch.apic_access_page_done)
4711 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4712 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4716 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4717 if (is_error_page(page)) {
4723 * Do not pin the page in memory, so that memory hot-unplug
4724 * is able to migrate it.
4727 kvm->arch.apic_access_page_done = true;
4729 mutex_unlock(&kvm->slots_lock);
4733 static int alloc_identity_pagetable(struct kvm *kvm)
4735 /* Called with kvm->slots_lock held. */
4739 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4741 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4742 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4747 static int allocate_vpid(void)
4753 spin_lock(&vmx_vpid_lock);
4754 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4755 if (vpid < VMX_NR_VPIDS)
4756 __set_bit(vpid, vmx_vpid_bitmap);
4759 spin_unlock(&vmx_vpid_lock);
4763 static void free_vpid(int vpid)
4765 if (!enable_vpid || vpid == 0)
4767 spin_lock(&vmx_vpid_lock);
4768 __clear_bit(vpid, vmx_vpid_bitmap);
4769 spin_unlock(&vmx_vpid_lock);
4772 #define MSR_TYPE_R 1
4773 #define MSR_TYPE_W 2
4774 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4777 int f = sizeof(unsigned long);
4779 if (!cpu_has_vmx_msr_bitmap())
4783 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4784 * have the write-low and read-high bitmap offsets the wrong way round.
4785 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4787 if (msr <= 0x1fff) {
4788 if (type & MSR_TYPE_R)
4790 __clear_bit(msr, msr_bitmap + 0x000 / f);
4792 if (type & MSR_TYPE_W)
4794 __clear_bit(msr, msr_bitmap + 0x800 / f);
4796 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4798 if (type & MSR_TYPE_R)
4800 __clear_bit(msr, msr_bitmap + 0x400 / f);
4802 if (type & MSR_TYPE_W)
4804 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4810 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4811 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4813 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4814 unsigned long *msr_bitmap_nested,
4817 int f = sizeof(unsigned long);
4819 if (!cpu_has_vmx_msr_bitmap()) {
4825 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4826 * have the write-low and read-high bitmap offsets the wrong way round.
4827 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4829 if (msr <= 0x1fff) {
4830 if (type & MSR_TYPE_R &&
4831 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4833 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4835 if (type & MSR_TYPE_W &&
4836 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4838 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4840 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4842 if (type & MSR_TYPE_R &&
4843 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4845 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4847 if (type & MSR_TYPE_W &&
4848 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4850 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4855 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4858 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4859 msr, MSR_TYPE_R | MSR_TYPE_W);
4860 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4861 msr, MSR_TYPE_R | MSR_TYPE_W);
4864 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4867 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4869 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4872 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4874 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4879 static bool vmx_get_enable_apicv(void)
4881 return enable_apicv;
4884 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4886 struct vcpu_vmx *vmx = to_vmx(vcpu);
4891 if (vmx->nested.pi_desc &&
4892 vmx->nested.pi_pending) {
4893 vmx->nested.pi_pending = false;
4894 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4897 max_irr = find_last_bit(
4898 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4903 vapic_page = kmap(vmx->nested.virtual_apic_page);
4904 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4905 kunmap(vmx->nested.virtual_apic_page);
4907 status = vmcs_read16(GUEST_INTR_STATUS);
4908 if ((u8)max_irr > ((u8)status & 0xff)) {
4910 status |= (u8)max_irr;
4911 vmcs_write16(GUEST_INTR_STATUS, status);
4916 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4919 if (vcpu->mode == IN_GUEST_MODE) {
4920 struct vcpu_vmx *vmx = to_vmx(vcpu);
4923 * Currently, we don't support urgent interrupt,
4924 * all interrupts are recognized as non-urgent
4925 * interrupt, so we cannot post interrupts when
4928 * If the vcpu is in guest mode, it means it is
4929 * running instead of being scheduled out and
4930 * waiting in the run queue, and that's the only
4931 * case when 'SN' is set currently, warning if
4934 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4936 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4937 POSTED_INTR_VECTOR);
4944 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4947 struct vcpu_vmx *vmx = to_vmx(vcpu);
4949 if (is_guest_mode(vcpu) &&
4950 vector == vmx->nested.posted_intr_nv) {
4951 /* the PIR and ON have been set by L1. */
4952 kvm_vcpu_trigger_posted_interrupt(vcpu);
4954 * If a posted intr is not recognized by hardware,
4955 * we will accomplish it in the next vmentry.
4957 vmx->nested.pi_pending = true;
4958 kvm_make_request(KVM_REQ_EVENT, vcpu);
4964 * Send interrupt to vcpu via posted interrupt way.
4965 * 1. If target vcpu is running(non-root mode), send posted interrupt
4966 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4967 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4968 * interrupt from PIR in next vmentry.
4970 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4972 struct vcpu_vmx *vmx = to_vmx(vcpu);
4975 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4979 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4982 /* If a previous notification has sent the IPI, nothing to do. */
4983 if (pi_test_and_set_on(&vmx->pi_desc))
4986 if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
4987 kvm_vcpu_kick(vcpu);
4991 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4992 * will not change in the lifetime of the guest.
4993 * Note that host-state that does change is set elsewhere. E.g., host-state
4994 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4996 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5001 unsigned long cr0, cr4;
5004 WARN_ON(cr0 & X86_CR0_TS);
5005 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
5006 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
5008 /* Save the most likely value for this task's CR4 in the VMCS. */
5009 cr4 = cr4_read_shadow();
5010 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5011 vmx->host_state.vmcs_host_cr4 = cr4;
5013 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
5014 #ifdef CONFIG_X86_64
5016 * Load null selectors, so we can avoid reloading them in
5017 * __vmx_load_host_state(), in case userspace uses the null selectors
5018 * too (the expected case).
5020 vmcs_write16(HOST_DS_SELECTOR, 0);
5021 vmcs_write16(HOST_ES_SELECTOR, 0);
5023 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5024 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5026 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5027 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5029 native_store_idt(&dt);
5030 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
5031 vmx->host_idt_base = dt.address;
5033 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5035 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5036 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5037 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5038 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5040 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5041 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5042 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5046 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5048 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5050 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5051 if (is_guest_mode(&vmx->vcpu))
5052 vmx->vcpu.arch.cr4_guest_owned_bits &=
5053 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5054 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5057 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5059 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5061 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5062 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5063 /* Enable the preemption timer dynamically */
5064 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5065 return pin_based_exec_ctrl;
5068 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5070 struct vcpu_vmx *vmx = to_vmx(vcpu);
5072 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5073 if (cpu_has_secondary_exec_ctrls()) {
5074 if (kvm_vcpu_apicv_active(vcpu))
5075 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5076 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5077 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5079 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5080 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5081 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5084 if (cpu_has_vmx_msr_bitmap())
5085 vmx_set_msr_bitmap(vcpu);
5088 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5090 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5092 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5093 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5095 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5096 exec_control &= ~CPU_BASED_TPR_SHADOW;
5097 #ifdef CONFIG_X86_64
5098 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5099 CPU_BASED_CR8_LOAD_EXITING;
5103 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5104 CPU_BASED_CR3_LOAD_EXITING |
5105 CPU_BASED_INVLPG_EXITING;
5106 return exec_control;
5109 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5111 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5112 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5113 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5115 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5117 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5118 enable_unrestricted_guest = 0;
5119 /* Enable INVPCID for non-ept guests may cause performance regression. */
5120 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5122 if (!enable_unrestricted_guest)
5123 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5125 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5126 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5127 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5128 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5129 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5130 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5132 We can NOT enable shadow_vmcs here because we don't have yet
5135 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5138 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5140 return exec_control;
5143 static void ept_set_mmio_spte_mask(void)
5146 * EPT Misconfigurations can be generated if the value of bits 2:0
5147 * of an EPT paging-structure entry is 110b (write/execute).
5149 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5152 #define VMX_XSS_EXIT_BITMAP 0
5154 * Sets up the vmcs for emulated real mode.
5156 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5158 #ifdef CONFIG_X86_64
5164 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5165 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5167 if (enable_shadow_vmcs) {
5168 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5169 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5171 if (cpu_has_vmx_msr_bitmap())
5172 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5174 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5177 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5178 vmx->hv_deadline_tsc = -1;
5180 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5182 if (cpu_has_secondary_exec_ctrls()) {
5183 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5184 vmx_secondary_exec_control(vmx));
5187 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5188 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5189 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5190 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5191 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5193 vmcs_write16(GUEST_INTR_STATUS, 0);
5195 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5196 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5200 vmcs_write32(PLE_GAP, ple_gap);
5201 vmx->ple_window = ple_window;
5202 vmx->ple_window_dirty = true;
5205 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5206 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5207 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5209 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5210 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
5211 vmx_set_constant_host_state(vmx);
5212 #ifdef CONFIG_X86_64
5213 rdmsrl(MSR_FS_BASE, a);
5214 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5215 rdmsrl(MSR_GS_BASE, a);
5216 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5218 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5219 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5222 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5223 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5224 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5225 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5226 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5228 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5229 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5231 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5232 u32 index = vmx_msr_index[i];
5233 u32 data_low, data_high;
5236 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5238 if (wrmsr_safe(index, data_low, data_high) < 0)
5240 vmx->guest_msrs[j].index = i;
5241 vmx->guest_msrs[j].data = 0;
5242 vmx->guest_msrs[j].mask = -1ull;
5247 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5249 /* 22.2.1, 20.8.1 */
5250 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5252 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5253 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5255 set_cr4_guest_host_mask(vmx);
5257 if (vmx_xsaves_supported())
5258 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5261 ASSERT(vmx->pml_pg);
5262 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5263 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5269 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5271 struct vcpu_vmx *vmx = to_vmx(vcpu);
5272 struct msr_data apic_base_msr;
5275 vmx->rmode.vm86_active = 0;
5277 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5278 kvm_set_cr8(vcpu, 0);
5281 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5282 MSR_IA32_APICBASE_ENABLE;
5283 if (kvm_vcpu_is_reset_bsp(vcpu))
5284 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5285 apic_base_msr.host_initiated = true;
5286 kvm_set_apic_base(vcpu, &apic_base_msr);
5289 vmx_segment_cache_clear(vmx);
5291 seg_setup(VCPU_SREG_CS);
5292 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5293 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5295 seg_setup(VCPU_SREG_DS);
5296 seg_setup(VCPU_SREG_ES);
5297 seg_setup(VCPU_SREG_FS);
5298 seg_setup(VCPU_SREG_GS);
5299 seg_setup(VCPU_SREG_SS);
5301 vmcs_write16(GUEST_TR_SELECTOR, 0);
5302 vmcs_writel(GUEST_TR_BASE, 0);
5303 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5304 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5306 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5307 vmcs_writel(GUEST_LDTR_BASE, 0);
5308 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5309 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5312 vmcs_write32(GUEST_SYSENTER_CS, 0);
5313 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5314 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5315 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5318 vmcs_writel(GUEST_RFLAGS, 0x02);
5319 kvm_rip_write(vcpu, 0xfff0);
5321 vmcs_writel(GUEST_GDTR_BASE, 0);
5322 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5324 vmcs_writel(GUEST_IDTR_BASE, 0);
5325 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5327 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5328 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5329 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5333 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5335 if (cpu_has_vmx_tpr_shadow() && !init_event) {
5336 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5337 if (cpu_need_tpr_shadow(vcpu))
5338 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5339 __pa(vcpu->arch.apic->regs));
5340 vmcs_write32(TPR_THRESHOLD, 0);
5343 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5345 if (kvm_vcpu_apicv_active(vcpu))
5346 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5349 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5351 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5352 vmx->vcpu.arch.cr0 = cr0;
5353 vmx_set_cr0(vcpu, cr0); /* enter rmode */
5354 vmx_set_cr4(vcpu, 0);
5355 vmx_set_efer(vcpu, 0);
5357 update_exception_bitmap(vcpu);
5359 vpid_sync_context(vmx->vpid);
5363 * In nested virtualization, check if L1 asked to exit on external interrupts.
5364 * For most existing hypervisors, this will always return true.
5366 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5368 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5369 PIN_BASED_EXT_INTR_MASK;
5373 * In nested virtualization, check if L1 has set
5374 * VM_EXIT_ACK_INTR_ON_EXIT
5376 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5378 return get_vmcs12(vcpu)->vm_exit_controls &
5379 VM_EXIT_ACK_INTR_ON_EXIT;
5382 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5384 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5385 PIN_BASED_NMI_EXITING;
5388 static void enable_irq_window(struct kvm_vcpu *vcpu)
5390 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5391 CPU_BASED_VIRTUAL_INTR_PENDING);
5394 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5396 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5397 enable_irq_window(vcpu);
5401 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5402 CPU_BASED_VIRTUAL_NMI_PENDING);
5405 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5407 struct vcpu_vmx *vmx = to_vmx(vcpu);
5409 int irq = vcpu->arch.interrupt.nr;
5411 trace_kvm_inj_virq(irq);
5413 ++vcpu->stat.irq_injections;
5414 if (vmx->rmode.vm86_active) {
5416 if (vcpu->arch.interrupt.soft)
5417 inc_eip = vcpu->arch.event_exit_inst_len;
5418 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5419 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5422 intr = irq | INTR_INFO_VALID_MASK;
5423 if (vcpu->arch.interrupt.soft) {
5424 intr |= INTR_TYPE_SOFT_INTR;
5425 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5426 vmx->vcpu.arch.event_exit_inst_len);
5428 intr |= INTR_TYPE_EXT_INTR;
5429 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5432 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5434 struct vcpu_vmx *vmx = to_vmx(vcpu);
5436 if (!is_guest_mode(vcpu)) {
5437 ++vcpu->stat.nmi_injections;
5438 vmx->nmi_known_unmasked = false;
5441 if (vmx->rmode.vm86_active) {
5442 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5443 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5447 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5448 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5451 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5453 if (to_vmx(vcpu)->nmi_known_unmasked)
5455 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5458 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5460 struct vcpu_vmx *vmx = to_vmx(vcpu);
5462 vmx->nmi_known_unmasked = !masked;
5464 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5465 GUEST_INTR_STATE_NMI);
5467 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5468 GUEST_INTR_STATE_NMI);
5471 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5473 if (to_vmx(vcpu)->nested.nested_run_pending)
5476 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5477 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5478 | GUEST_INTR_STATE_NMI));
5481 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5483 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5484 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5485 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5486 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5489 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5493 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5497 kvm->arch.tss_addr = addr;
5498 return init_rmode_tss(kvm);
5501 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5506 * Update instruction length as we may reinject the exception
5507 * from user space while in guest debugging mode.
5509 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5510 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5511 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5515 if (vcpu->guest_debug &
5516 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5533 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5534 int vec, u32 err_code)
5537 * Instruction with address size override prefix opcode 0x67
5538 * Cause the #SS fault with 0 error code in VM86 mode.
5540 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5541 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5542 if (vcpu->arch.halt_request) {
5543 vcpu->arch.halt_request = 0;
5544 return kvm_vcpu_halt(vcpu);
5552 * Forward all other exceptions that are valid in real mode.
5553 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5554 * the required debugging infrastructure rework.
5556 kvm_queue_exception(vcpu, vec);
5561 * Trigger machine check on the host. We assume all the MSRs are already set up
5562 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5563 * We pass a fake environment to the machine check handler because we want
5564 * the guest to be always treated like user space, no matter what context
5565 * it used internally.
5567 static void kvm_machine_check(void)
5569 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5570 struct pt_regs regs = {
5571 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5572 .flags = X86_EFLAGS_IF,
5575 do_machine_check(®s, 0);
5579 static int handle_machine_check(struct kvm_vcpu *vcpu)
5581 /* already handled by vcpu_run */
5585 static int handle_exception(struct kvm_vcpu *vcpu)
5587 struct vcpu_vmx *vmx = to_vmx(vcpu);
5588 struct kvm_run *kvm_run = vcpu->run;
5589 u32 intr_info, ex_no, error_code;
5590 unsigned long cr2, rip, dr6;
5592 enum emulation_result er;
5594 vect_info = vmx->idt_vectoring_info;
5595 intr_info = vmx->exit_intr_info;
5597 if (is_machine_check(intr_info))
5598 return handle_machine_check(vcpu);
5600 if (is_nmi(intr_info))
5601 return 1; /* already handled by vmx_vcpu_run() */
5603 if (is_invalid_opcode(intr_info)) {
5604 if (is_guest_mode(vcpu)) {
5605 kvm_queue_exception(vcpu, UD_VECTOR);
5608 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5609 if (er != EMULATE_DONE)
5610 kvm_queue_exception(vcpu, UD_VECTOR);
5615 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5616 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5619 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5620 * MMIO, it is better to report an internal error.
5621 * See the comments in vmx_handle_exit.
5623 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5624 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5625 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5626 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5627 vcpu->run->internal.ndata = 3;
5628 vcpu->run->internal.data[0] = vect_info;
5629 vcpu->run->internal.data[1] = intr_info;
5630 vcpu->run->internal.data[2] = error_code;
5634 if (is_page_fault(intr_info)) {
5635 /* EPT won't cause page fault directly */
5637 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5638 trace_kvm_page_fault(cr2, error_code);
5640 if (kvm_event_needs_reinjection(vcpu))
5641 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5642 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5645 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5647 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5648 return handle_rmode_exception(vcpu, ex_no, error_code);
5652 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5655 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5656 if (!(vcpu->guest_debug &
5657 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5658 vcpu->arch.dr6 &= ~15;
5659 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5660 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5661 skip_emulated_instruction(vcpu);
5663 kvm_queue_exception(vcpu, DB_VECTOR);
5666 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5667 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5671 * Update instruction length as we may reinject #BP from
5672 * user space while in guest debugging mode. Reading it for
5673 * #DB as well causes no harm, it is not used in that case.
5675 vmx->vcpu.arch.event_exit_inst_len =
5676 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5677 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5678 rip = kvm_rip_read(vcpu);
5679 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5680 kvm_run->debug.arch.exception = ex_no;
5683 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5684 kvm_run->ex.exception = ex_no;
5685 kvm_run->ex.error_code = error_code;
5691 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5693 ++vcpu->stat.irq_exits;
5697 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5699 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5703 static int handle_io(struct kvm_vcpu *vcpu)
5705 unsigned long exit_qualification;
5706 int size, in, string, ret;
5709 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5710 string = (exit_qualification & 16) != 0;
5711 in = (exit_qualification & 8) != 0;
5713 ++vcpu->stat.io_exits;
5716 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5718 port = exit_qualification >> 16;
5719 size = (exit_qualification & 7) + 1;
5721 ret = kvm_skip_emulated_instruction(vcpu);
5724 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5725 * KVM_EXIT_DEBUG here.
5727 return kvm_fast_pio_out(vcpu, size, port) && ret;
5731 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5734 * Patch in the VMCALL instruction:
5736 hypercall[0] = 0x0f;
5737 hypercall[1] = 0x01;
5738 hypercall[2] = 0xc1;
5741 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5742 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5744 if (is_guest_mode(vcpu)) {
5745 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5746 unsigned long orig_val = val;
5749 * We get here when L2 changed cr0 in a way that did not change
5750 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5751 * but did change L0 shadowed bits. So we first calculate the
5752 * effective cr0 value that L1 would like to write into the
5753 * hardware. It consists of the L2-owned bits from the new
5754 * value combined with the L1-owned bits from L1's guest_cr0.
5756 val = (val & ~vmcs12->cr0_guest_host_mask) |
5757 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5759 if (!nested_guest_cr0_valid(vcpu, val))
5762 if (kvm_set_cr0(vcpu, val))
5764 vmcs_writel(CR0_READ_SHADOW, orig_val);
5767 if (to_vmx(vcpu)->nested.vmxon &&
5768 !nested_host_cr0_valid(vcpu, val))
5771 return kvm_set_cr0(vcpu, val);
5775 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5777 if (is_guest_mode(vcpu)) {
5778 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5779 unsigned long orig_val = val;
5781 /* analogously to handle_set_cr0 */
5782 val = (val & ~vmcs12->cr4_guest_host_mask) |
5783 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5784 if (kvm_set_cr4(vcpu, val))
5786 vmcs_writel(CR4_READ_SHADOW, orig_val);
5789 return kvm_set_cr4(vcpu, val);
5792 static int handle_cr(struct kvm_vcpu *vcpu)
5794 unsigned long exit_qualification, val;
5800 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5801 cr = exit_qualification & 15;
5802 reg = (exit_qualification >> 8) & 15;
5803 switch ((exit_qualification >> 4) & 3) {
5804 case 0: /* mov to cr */
5805 val = kvm_register_readl(vcpu, reg);
5806 trace_kvm_cr_write(cr, val);
5809 err = handle_set_cr0(vcpu, val);
5810 return kvm_complete_insn_gp(vcpu, err);
5812 err = kvm_set_cr3(vcpu, val);
5813 return kvm_complete_insn_gp(vcpu, err);
5815 err = handle_set_cr4(vcpu, val);
5816 return kvm_complete_insn_gp(vcpu, err);
5818 u8 cr8_prev = kvm_get_cr8(vcpu);
5820 err = kvm_set_cr8(vcpu, cr8);
5821 ret = kvm_complete_insn_gp(vcpu, err);
5822 if (lapic_in_kernel(vcpu))
5824 if (cr8_prev <= cr8)
5827 * TODO: we might be squashing a
5828 * KVM_GUESTDBG_SINGLESTEP-triggered
5829 * KVM_EXIT_DEBUG here.
5831 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5837 WARN_ONCE(1, "Guest should always own CR0.TS");
5838 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5839 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5840 return kvm_skip_emulated_instruction(vcpu);
5841 case 1: /*mov from cr*/
5844 val = kvm_read_cr3(vcpu);
5845 kvm_register_write(vcpu, reg, val);
5846 trace_kvm_cr_read(cr, val);
5847 return kvm_skip_emulated_instruction(vcpu);
5849 val = kvm_get_cr8(vcpu);
5850 kvm_register_write(vcpu, reg, val);
5851 trace_kvm_cr_read(cr, val);
5852 return kvm_skip_emulated_instruction(vcpu);
5856 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5857 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5858 kvm_lmsw(vcpu, val);
5860 return kvm_skip_emulated_instruction(vcpu);
5864 vcpu->run->exit_reason = 0;
5865 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5866 (int)(exit_qualification >> 4) & 3, cr);
5870 static int handle_dr(struct kvm_vcpu *vcpu)
5872 unsigned long exit_qualification;
5875 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5876 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5878 /* First, if DR does not exist, trigger UD */
5879 if (!kvm_require_dr(vcpu, dr))
5882 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5883 if (!kvm_require_cpl(vcpu, 0))
5885 dr7 = vmcs_readl(GUEST_DR7);
5888 * As the vm-exit takes precedence over the debug trap, we
5889 * need to emulate the latter, either for the host or the
5890 * guest debugging itself.
5892 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5893 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5894 vcpu->run->debug.arch.dr7 = dr7;
5895 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5896 vcpu->run->debug.arch.exception = DB_VECTOR;
5897 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5900 vcpu->arch.dr6 &= ~15;
5901 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5902 kvm_queue_exception(vcpu, DB_VECTOR);
5907 if (vcpu->guest_debug == 0) {
5908 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5909 CPU_BASED_MOV_DR_EXITING);
5912 * No more DR vmexits; force a reload of the debug registers
5913 * and reenter on this instruction. The next vmexit will
5914 * retrieve the full state of the debug registers.
5916 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5920 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5921 if (exit_qualification & TYPE_MOV_FROM_DR) {
5924 if (kvm_get_dr(vcpu, dr, &val))
5926 kvm_register_write(vcpu, reg, val);
5928 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5931 return kvm_skip_emulated_instruction(vcpu);
5934 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5936 return vcpu->arch.dr6;
5939 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5943 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5945 get_debugreg(vcpu->arch.db[0], 0);
5946 get_debugreg(vcpu->arch.db[1], 1);
5947 get_debugreg(vcpu->arch.db[2], 2);
5948 get_debugreg(vcpu->arch.db[3], 3);
5949 get_debugreg(vcpu->arch.dr6, 6);
5950 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5952 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5953 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5956 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5958 vmcs_writel(GUEST_DR7, val);
5961 static int handle_cpuid(struct kvm_vcpu *vcpu)
5963 return kvm_emulate_cpuid(vcpu);
5966 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5968 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5969 struct msr_data msr_info;
5971 msr_info.index = ecx;
5972 msr_info.host_initiated = false;
5973 if (vmx_get_msr(vcpu, &msr_info)) {
5974 trace_kvm_msr_read_ex(ecx);
5975 kvm_inject_gp(vcpu, 0);
5979 trace_kvm_msr_read(ecx, msr_info.data);
5981 /* FIXME: handling of bits 32:63 of rax, rdx */
5982 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5983 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5984 return kvm_skip_emulated_instruction(vcpu);
5987 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5989 struct msr_data msr;
5990 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5991 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5992 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5996 msr.host_initiated = false;
5997 if (kvm_set_msr(vcpu, &msr) != 0) {
5998 trace_kvm_msr_write_ex(ecx, data);
5999 kvm_inject_gp(vcpu, 0);
6003 trace_kvm_msr_write(ecx, data);
6004 return kvm_skip_emulated_instruction(vcpu);
6007 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6009 kvm_apic_update_ppr(vcpu);
6013 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6015 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6016 CPU_BASED_VIRTUAL_INTR_PENDING);
6018 kvm_make_request(KVM_REQ_EVENT, vcpu);
6020 ++vcpu->stat.irq_window_exits;
6024 static int handle_halt(struct kvm_vcpu *vcpu)
6026 return kvm_emulate_halt(vcpu);
6029 static int handle_vmcall(struct kvm_vcpu *vcpu)
6031 return kvm_emulate_hypercall(vcpu);
6034 static int handle_invd(struct kvm_vcpu *vcpu)
6036 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6039 static int handle_invlpg(struct kvm_vcpu *vcpu)
6041 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6043 kvm_mmu_invlpg(vcpu, exit_qualification);
6044 return kvm_skip_emulated_instruction(vcpu);
6047 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6051 err = kvm_rdpmc(vcpu);
6052 return kvm_complete_insn_gp(vcpu, err);
6055 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6057 return kvm_emulate_wbinvd(vcpu);
6060 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6062 u64 new_bv = kvm_read_edx_eax(vcpu);
6063 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6065 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6066 return kvm_skip_emulated_instruction(vcpu);
6070 static int handle_xsaves(struct kvm_vcpu *vcpu)
6072 kvm_skip_emulated_instruction(vcpu);
6073 WARN(1, "this should never happen\n");
6077 static int handle_xrstors(struct kvm_vcpu *vcpu)
6079 kvm_skip_emulated_instruction(vcpu);
6080 WARN(1, "this should never happen\n");
6084 static int handle_apic_access(struct kvm_vcpu *vcpu)
6086 if (likely(fasteoi)) {
6087 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6088 int access_type, offset;
6090 access_type = exit_qualification & APIC_ACCESS_TYPE;
6091 offset = exit_qualification & APIC_ACCESS_OFFSET;
6093 * Sane guest uses MOV to write EOI, with written value
6094 * not cared. So make a short-circuit here by avoiding
6095 * heavy instruction emulation.
6097 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6098 (offset == APIC_EOI)) {
6099 kvm_lapic_set_eoi(vcpu);
6100 return kvm_skip_emulated_instruction(vcpu);
6103 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6106 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6108 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6109 int vector = exit_qualification & 0xff;
6111 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6112 kvm_apic_set_eoi_accelerated(vcpu, vector);
6116 static int handle_apic_write(struct kvm_vcpu *vcpu)
6118 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6119 u32 offset = exit_qualification & 0xfff;
6121 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6122 kvm_apic_write_nodecode(vcpu, offset);
6126 static int handle_task_switch(struct kvm_vcpu *vcpu)
6128 struct vcpu_vmx *vmx = to_vmx(vcpu);
6129 unsigned long exit_qualification;
6130 bool has_error_code = false;
6133 int reason, type, idt_v, idt_index;
6135 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6136 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6137 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6139 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6141 reason = (u32)exit_qualification >> 30;
6142 if (reason == TASK_SWITCH_GATE && idt_v) {
6144 case INTR_TYPE_NMI_INTR:
6145 vcpu->arch.nmi_injected = false;
6146 vmx_set_nmi_mask(vcpu, true);
6148 case INTR_TYPE_EXT_INTR:
6149 case INTR_TYPE_SOFT_INTR:
6150 kvm_clear_interrupt_queue(vcpu);
6152 case INTR_TYPE_HARD_EXCEPTION:
6153 if (vmx->idt_vectoring_info &
6154 VECTORING_INFO_DELIVER_CODE_MASK) {
6155 has_error_code = true;
6157 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6160 case INTR_TYPE_SOFT_EXCEPTION:
6161 kvm_clear_exception_queue(vcpu);
6167 tss_selector = exit_qualification;
6169 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6170 type != INTR_TYPE_EXT_INTR &&
6171 type != INTR_TYPE_NMI_INTR))
6172 skip_emulated_instruction(vcpu);
6174 if (kvm_task_switch(vcpu, tss_selector,
6175 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6176 has_error_code, error_code) == EMULATE_FAIL) {
6177 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6178 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6179 vcpu->run->internal.ndata = 0;
6184 * TODO: What about debug traps on tss switch?
6185 * Are we supposed to inject them and update dr6?
6191 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6193 unsigned long exit_qualification;
6197 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6199 if (is_guest_mode(vcpu)
6200 && !(exit_qualification & EPT_VIOLATION_GVA_TRANSLATED)) {
6202 * Fix up exit_qualification according to whether guest
6203 * page table accesses are reads or writes.
6205 u64 eptp = nested_ept_get_cr3(vcpu);
6206 if (!(eptp & VMX_EPT_AD_ENABLE_BIT))
6207 exit_qualification &= ~EPT_VIOLATION_ACC_WRITE;
6211 * EPT violation happened while executing iret from NMI,
6212 * "blocked by NMI" bit has to be set before next VM entry.
6213 * There are errata that may cause this bit to not be set:
6216 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6217 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6218 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6220 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6221 trace_kvm_page_fault(gpa, exit_qualification);
6223 /* Is it a read fault? */
6224 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6225 ? PFERR_USER_MASK : 0;
6226 /* Is it a write fault? */
6227 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6228 ? PFERR_WRITE_MASK : 0;
6229 /* Is it a fetch fault? */
6230 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6231 ? PFERR_FETCH_MASK : 0;
6232 /* ept page table entry is present? */
6233 error_code |= (exit_qualification &
6234 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6235 EPT_VIOLATION_EXECUTABLE))
6236 ? PFERR_PRESENT_MASK : 0;
6238 vcpu->arch.gpa_available = true;
6239 vcpu->arch.exit_qualification = exit_qualification;
6241 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6244 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6249 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6250 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6251 trace_kvm_fast_mmio(gpa);
6252 return kvm_skip_emulated_instruction(vcpu);
6255 ret = handle_mmio_page_fault(vcpu, gpa, true);
6256 vcpu->arch.gpa_available = true;
6257 if (likely(ret == RET_MMIO_PF_EMULATE))
6258 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6261 if (unlikely(ret == RET_MMIO_PF_INVALID))
6262 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6264 if (unlikely(ret == RET_MMIO_PF_RETRY))
6267 /* It is the real ept misconfig */
6270 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6271 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6276 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6278 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6279 CPU_BASED_VIRTUAL_NMI_PENDING);
6280 ++vcpu->stat.nmi_window_exits;
6281 kvm_make_request(KVM_REQ_EVENT, vcpu);
6286 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6288 struct vcpu_vmx *vmx = to_vmx(vcpu);
6289 enum emulation_result err = EMULATE_DONE;
6292 bool intr_window_requested;
6293 unsigned count = 130;
6295 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6296 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6298 while (vmx->emulation_required && count-- != 0) {
6299 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6300 return handle_interrupt_window(&vmx->vcpu);
6302 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6305 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6307 if (err == EMULATE_USER_EXIT) {
6308 ++vcpu->stat.mmio_exits;
6313 if (err != EMULATE_DONE) {
6314 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6315 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6316 vcpu->run->internal.ndata = 0;
6320 if (vcpu->arch.halt_request) {
6321 vcpu->arch.halt_request = 0;
6322 ret = kvm_vcpu_halt(vcpu);
6326 if (signal_pending(current))
6336 static int __grow_ple_window(int val)
6338 if (ple_window_grow < 1)
6341 val = min(val, ple_window_actual_max);
6343 if (ple_window_grow < ple_window)
6344 val *= ple_window_grow;
6346 val += ple_window_grow;
6351 static int __shrink_ple_window(int val, int modifier, int minimum)
6356 if (modifier < ple_window)
6361 return max(val, minimum);
6364 static void grow_ple_window(struct kvm_vcpu *vcpu)
6366 struct vcpu_vmx *vmx = to_vmx(vcpu);
6367 int old = vmx->ple_window;
6369 vmx->ple_window = __grow_ple_window(old);
6371 if (vmx->ple_window != old)
6372 vmx->ple_window_dirty = true;
6374 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6377 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6379 struct vcpu_vmx *vmx = to_vmx(vcpu);
6380 int old = vmx->ple_window;
6382 vmx->ple_window = __shrink_ple_window(old,
6383 ple_window_shrink, ple_window);
6385 if (vmx->ple_window != old)
6386 vmx->ple_window_dirty = true;
6388 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6392 * ple_window_actual_max is computed to be one grow_ple_window() below
6393 * ple_window_max. (See __grow_ple_window for the reason.)
6394 * This prevents overflows, because ple_window_max is int.
6395 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6397 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6399 static void update_ple_window_actual_max(void)
6401 ple_window_actual_max =
6402 __shrink_ple_window(max(ple_window_max, ple_window),
6403 ple_window_grow, INT_MIN);
6407 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6409 static void wakeup_handler(void)
6411 struct kvm_vcpu *vcpu;
6412 int cpu = smp_processor_id();
6414 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6415 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6416 blocked_vcpu_list) {
6417 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6419 if (pi_test_on(pi_desc) == 1)
6420 kvm_vcpu_kick(vcpu);
6422 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6425 void vmx_enable_tdp(void)
6427 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6428 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6429 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6430 0ull, VMX_EPT_EXECUTABLE_MASK,
6431 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6432 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6434 ept_set_mmio_spte_mask();
6438 static __init int hardware_setup(void)
6440 int r = -ENOMEM, i, msr;
6442 rdmsrl_safe(MSR_EFER, &host_efer);
6444 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6445 kvm_define_shared_msr(i, vmx_msr_index[i]);
6447 for (i = 0; i < VMX_BITMAP_NR; i++) {
6448 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6453 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6454 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6455 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6458 * Allow direct access to the PC debug port (it is often used for I/O
6459 * delays, but the vmexits simply slow things down).
6461 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6462 clear_bit(0x80, vmx_io_bitmap_a);
6464 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6466 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6467 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6469 if (setup_vmcs_config(&vmcs_config) < 0) {
6474 if (boot_cpu_has(X86_FEATURE_NX))
6475 kvm_enable_efer_bits(EFER_NX);
6477 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6478 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6481 if (!cpu_has_vmx_shadow_vmcs())
6482 enable_shadow_vmcs = 0;
6483 if (enable_shadow_vmcs)
6484 init_vmcs_shadow_fields();
6486 if (!cpu_has_vmx_ept() ||
6487 !cpu_has_vmx_ept_4levels()) {
6489 enable_unrestricted_guest = 0;
6490 enable_ept_ad_bits = 0;
6493 if (!cpu_has_vmx_ept_ad_bits())
6494 enable_ept_ad_bits = 0;
6496 if (!cpu_has_vmx_unrestricted_guest())
6497 enable_unrestricted_guest = 0;
6499 if (!cpu_has_vmx_flexpriority())
6500 flexpriority_enabled = 0;
6503 * set_apic_access_page_addr() is used to reload apic access
6504 * page upon invalidation. No need to do anything if not
6505 * using the APIC_ACCESS_ADDR VMCS field.
6507 if (!flexpriority_enabled)
6508 kvm_x86_ops->set_apic_access_page_addr = NULL;
6510 if (!cpu_has_vmx_tpr_shadow())
6511 kvm_x86_ops->update_cr8_intercept = NULL;
6513 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6514 kvm_disable_largepages();
6516 if (!cpu_has_vmx_ple())
6519 if (!cpu_has_vmx_apicv()) {
6521 kvm_x86_ops->sync_pir_to_irr = NULL;
6524 if (cpu_has_vmx_tsc_scaling()) {
6525 kvm_has_tsc_control = true;
6526 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6527 kvm_tsc_scaling_ratio_frac_bits = 48;
6530 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6531 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6532 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6533 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6534 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6535 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6536 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6538 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6539 vmx_msr_bitmap_legacy, PAGE_SIZE);
6540 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6541 vmx_msr_bitmap_longmode, PAGE_SIZE);
6542 memcpy(vmx_msr_bitmap_legacy_x2apic,
6543 vmx_msr_bitmap_legacy, PAGE_SIZE);
6544 memcpy(vmx_msr_bitmap_longmode_x2apic,
6545 vmx_msr_bitmap_longmode, PAGE_SIZE);
6547 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6549 for (msr = 0x800; msr <= 0x8ff; msr++) {
6550 if (msr == 0x839 /* TMCCT */)
6552 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6556 * TPR reads and writes can be virtualized even if virtual interrupt
6557 * delivery is not in use.
6559 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6560 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6563 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6565 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6572 update_ple_window_actual_max();
6575 * Only enable PML when hardware supports PML feature, and both EPT
6576 * and EPT A/D bit features are enabled -- PML depends on them to work.
6578 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6582 kvm_x86_ops->slot_enable_log_dirty = NULL;
6583 kvm_x86_ops->slot_disable_log_dirty = NULL;
6584 kvm_x86_ops->flush_log_dirty = NULL;
6585 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6588 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6591 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6592 cpu_preemption_timer_multi =
6593 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6595 kvm_x86_ops->set_hv_timer = NULL;
6596 kvm_x86_ops->cancel_hv_timer = NULL;
6599 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6601 kvm_mce_cap_supported |= MCG_LMCE_P;
6603 return alloc_kvm_area();
6606 for (i = 0; i < VMX_BITMAP_NR; i++)
6607 free_page((unsigned long)vmx_bitmap[i]);
6612 static __exit void hardware_unsetup(void)
6616 for (i = 0; i < VMX_BITMAP_NR; i++)
6617 free_page((unsigned long)vmx_bitmap[i]);
6623 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6624 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6626 static int handle_pause(struct kvm_vcpu *vcpu)
6629 grow_ple_window(vcpu);
6631 kvm_vcpu_on_spin(vcpu);
6632 return kvm_skip_emulated_instruction(vcpu);
6635 static int handle_nop(struct kvm_vcpu *vcpu)
6637 return kvm_skip_emulated_instruction(vcpu);
6640 static int handle_mwait(struct kvm_vcpu *vcpu)
6642 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6643 return handle_nop(vcpu);
6646 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6651 static int handle_monitor(struct kvm_vcpu *vcpu)
6653 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6654 return handle_nop(vcpu);
6658 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6659 * We could reuse a single VMCS for all the L2 guests, but we also want the
6660 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6661 * allows keeping them loaded on the processor, and in the future will allow
6662 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6663 * every entry if they never change.
6664 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6665 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6667 * The following functions allocate and free a vmcs02 in this pool.
6670 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6671 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6673 struct vmcs02_list *item;
6674 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6675 if (item->vmptr == vmx->nested.current_vmptr) {
6676 list_move(&item->list, &vmx->nested.vmcs02_pool);
6677 return &item->vmcs02;
6680 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6681 /* Recycle the least recently used VMCS. */
6682 item = list_last_entry(&vmx->nested.vmcs02_pool,
6683 struct vmcs02_list, list);
6684 item->vmptr = vmx->nested.current_vmptr;
6685 list_move(&item->list, &vmx->nested.vmcs02_pool);
6686 return &item->vmcs02;
6689 /* Create a new VMCS */
6690 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6693 item->vmcs02.vmcs = alloc_vmcs();
6694 item->vmcs02.shadow_vmcs = NULL;
6695 if (!item->vmcs02.vmcs) {
6699 loaded_vmcs_init(&item->vmcs02);
6700 item->vmptr = vmx->nested.current_vmptr;
6701 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6702 vmx->nested.vmcs02_num++;
6703 return &item->vmcs02;
6706 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6707 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6709 struct vmcs02_list *item;
6710 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6711 if (item->vmptr == vmptr) {
6712 free_loaded_vmcs(&item->vmcs02);
6713 list_del(&item->list);
6715 vmx->nested.vmcs02_num--;
6721 * Free all VMCSs saved for this vcpu, except the one pointed by
6722 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6723 * must be &vmx->vmcs01.
6725 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6727 struct vmcs02_list *item, *n;
6729 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6730 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6732 * Something will leak if the above WARN triggers. Better than
6735 if (vmx->loaded_vmcs == &item->vmcs02)
6738 free_loaded_vmcs(&item->vmcs02);
6739 list_del(&item->list);
6741 vmx->nested.vmcs02_num--;
6746 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6747 * set the success or error code of an emulated VMX instruction, as specified
6748 * by Vol 2B, VMX Instruction Reference, "Conventions".
6750 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6752 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6753 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6754 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6757 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6759 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6760 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6761 X86_EFLAGS_SF | X86_EFLAGS_OF))
6765 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6766 u32 vm_instruction_error)
6768 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6770 * failValid writes the error number to the current VMCS, which
6771 * can't be done there isn't a current VMCS.
6773 nested_vmx_failInvalid(vcpu);
6776 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6777 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6778 X86_EFLAGS_SF | X86_EFLAGS_OF))
6780 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6782 * We don't need to force a shadow sync because
6783 * VM_INSTRUCTION_ERROR is not shadowed
6787 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6789 /* TODO: not to reset guest simply here. */
6790 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6791 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6794 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6796 struct vcpu_vmx *vmx =
6797 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6799 vmx->nested.preemption_timer_expired = true;
6800 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6801 kvm_vcpu_kick(&vmx->vcpu);
6803 return HRTIMER_NORESTART;
6807 * Decode the memory-address operand of a vmx instruction, as recorded on an
6808 * exit caused by such an instruction (run by a guest hypervisor).
6809 * On success, returns 0. When the operand is invalid, returns 1 and throws
6812 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6813 unsigned long exit_qualification,
6814 u32 vmx_instruction_info, bool wr, gva_t *ret)
6818 struct kvm_segment s;
6821 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6822 * Execution", on an exit, vmx_instruction_info holds most of the
6823 * addressing components of the operand. Only the displacement part
6824 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6825 * For how an actual address is calculated from all these components,
6826 * refer to Vol. 1, "Operand Addressing".
6828 int scaling = vmx_instruction_info & 3;
6829 int addr_size = (vmx_instruction_info >> 7) & 7;
6830 bool is_reg = vmx_instruction_info & (1u << 10);
6831 int seg_reg = (vmx_instruction_info >> 15) & 7;
6832 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6833 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6834 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6835 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6838 kvm_queue_exception(vcpu, UD_VECTOR);
6842 /* Addr = segment_base + offset */
6843 /* offset = base + [index * scale] + displacement */
6844 off = exit_qualification; /* holds the displacement */
6846 off += kvm_register_read(vcpu, base_reg);
6848 off += kvm_register_read(vcpu, index_reg)<<scaling;
6849 vmx_get_segment(vcpu, &s, seg_reg);
6850 *ret = s.base + off;
6852 if (addr_size == 1) /* 32 bit */
6855 /* Checks for #GP/#SS exceptions. */
6857 if (is_long_mode(vcpu)) {
6858 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6859 * non-canonical form. This is the only check on the memory
6860 * destination for long mode!
6862 exn = is_noncanonical_address(*ret);
6863 } else if (is_protmode(vcpu)) {
6864 /* Protected mode: apply checks for segment validity in the
6866 * - segment type check (#GP(0) may be thrown)
6867 * - usability check (#GP(0)/#SS(0))
6868 * - limit check (#GP(0)/#SS(0))
6871 /* #GP(0) if the destination operand is located in a
6872 * read-only data segment or any code segment.
6874 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6876 /* #GP(0) if the source operand is located in an
6877 * execute-only code segment
6879 exn = ((s.type & 0xa) == 8);
6881 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6884 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6886 exn = (s.unusable != 0);
6887 /* Protected mode: #GP(0)/#SS(0) if the memory
6888 * operand is outside the segment limit.
6890 exn = exn || (off + sizeof(u64) > s.limit);
6893 kvm_queue_exception_e(vcpu,
6894 seg_reg == VCPU_SREG_SS ?
6895 SS_VECTOR : GP_VECTOR,
6904 * This function performs the various checks including
6905 * - if it's 4KB aligned
6906 * - No bits beyond the physical address width are set
6907 * - Returns 0 on success or else 1
6908 * (Intel SDM Section 30.3)
6910 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6915 struct x86_exception e;
6917 struct vcpu_vmx *vmx = to_vmx(vcpu);
6918 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6920 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6921 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6924 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6925 sizeof(vmptr), &e)) {
6926 kvm_inject_page_fault(vcpu, &e);
6930 switch (exit_reason) {
6931 case EXIT_REASON_VMON:
6934 * The first 4 bytes of VMXON region contain the supported
6935 * VMCS revision identifier
6937 * Note - IA32_VMX_BASIC[48] will never be 1
6938 * for the nested case;
6939 * which replaces physical address width with 32
6942 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6943 nested_vmx_failInvalid(vcpu);
6944 return kvm_skip_emulated_instruction(vcpu);
6947 page = nested_get_page(vcpu, vmptr);
6949 nested_vmx_failInvalid(vcpu);
6950 return kvm_skip_emulated_instruction(vcpu);
6952 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
6954 nested_release_page_clean(page);
6955 nested_vmx_failInvalid(vcpu);
6956 return kvm_skip_emulated_instruction(vcpu);
6959 nested_release_page_clean(page);
6960 vmx->nested.vmxon_ptr = vmptr;
6962 case EXIT_REASON_VMCLEAR:
6963 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6964 nested_vmx_failValid(vcpu,
6965 VMXERR_VMCLEAR_INVALID_ADDRESS);
6966 return kvm_skip_emulated_instruction(vcpu);
6969 if (vmptr == vmx->nested.vmxon_ptr) {
6970 nested_vmx_failValid(vcpu,
6971 VMXERR_VMCLEAR_VMXON_POINTER);
6972 return kvm_skip_emulated_instruction(vcpu);
6975 case EXIT_REASON_VMPTRLD:
6976 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6977 nested_vmx_failValid(vcpu,
6978 VMXERR_VMPTRLD_INVALID_ADDRESS);
6979 return kvm_skip_emulated_instruction(vcpu);
6982 if (vmptr == vmx->nested.vmxon_ptr) {
6983 nested_vmx_failValid(vcpu,
6984 VMXERR_VMPTRLD_VMXON_POINTER);
6985 return kvm_skip_emulated_instruction(vcpu);
6989 return 1; /* shouldn't happen */
6997 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
6999 struct vcpu_vmx *vmx = to_vmx(vcpu);
7000 struct vmcs *shadow_vmcs;
7002 if (cpu_has_vmx_msr_bitmap()) {
7003 vmx->nested.msr_bitmap =
7004 (unsigned long *)__get_free_page(GFP_KERNEL);
7005 if (!vmx->nested.msr_bitmap)
7006 goto out_msr_bitmap;
7009 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7010 if (!vmx->nested.cached_vmcs12)
7011 goto out_cached_vmcs12;
7013 if (enable_shadow_vmcs) {
7014 shadow_vmcs = alloc_vmcs();
7016 goto out_shadow_vmcs;
7017 /* mark vmcs as shadow */
7018 shadow_vmcs->revision_id |= (1u << 31);
7019 /* init shadow vmcs */
7020 vmcs_clear(shadow_vmcs);
7021 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7024 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7025 vmx->nested.vmcs02_num = 0;
7027 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7028 HRTIMER_MODE_REL_PINNED);
7029 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7031 vmx->nested.vmxon = true;
7035 kfree(vmx->nested.cached_vmcs12);
7038 free_page((unsigned long)vmx->nested.msr_bitmap);
7045 * Emulate the VMXON instruction.
7046 * Currently, we just remember that VMX is active, and do not save or even
7047 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7048 * do not currently need to store anything in that guest-allocated memory
7049 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7050 * argument is different from the VMXON pointer (which the spec says they do).
7052 static int handle_vmon(struct kvm_vcpu *vcpu)
7055 struct kvm_segment cs;
7056 struct vcpu_vmx *vmx = to_vmx(vcpu);
7057 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7058 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7060 /* The Intel VMX Instruction Reference lists a bunch of bits that
7061 * are prerequisite to running VMXON, most notably cr4.VMXE must be
7062 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7063 * Otherwise, we should fail with #UD. We test these now:
7065 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7066 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7067 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7068 kvm_queue_exception(vcpu, UD_VECTOR);
7072 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7073 if (is_long_mode(vcpu) && !cs.l) {
7074 kvm_queue_exception(vcpu, UD_VECTOR);
7078 if (vmx_get_cpl(vcpu)) {
7079 kvm_inject_gp(vcpu, 0);
7083 if (vmx->nested.vmxon) {
7084 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7085 return kvm_skip_emulated_instruction(vcpu);
7088 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7089 != VMXON_NEEDED_FEATURES) {
7090 kvm_inject_gp(vcpu, 0);
7094 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7097 ret = enter_vmx_operation(vcpu);
7101 nested_vmx_succeed(vcpu);
7102 return kvm_skip_emulated_instruction(vcpu);
7106 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7107 * for running VMX instructions (except VMXON, whose prerequisites are
7108 * slightly different). It also specifies what exception to inject otherwise.
7110 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7112 struct kvm_segment cs;
7113 struct vcpu_vmx *vmx = to_vmx(vcpu);
7115 if (!vmx->nested.vmxon) {
7116 kvm_queue_exception(vcpu, UD_VECTOR);
7120 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7121 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7122 (is_long_mode(vcpu) && !cs.l)) {
7123 kvm_queue_exception(vcpu, UD_VECTOR);
7127 if (vmx_get_cpl(vcpu)) {
7128 kvm_inject_gp(vcpu, 0);
7135 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7137 if (vmx->nested.current_vmptr == -1ull)
7140 /* current_vmptr and current_vmcs12 are always set/reset together */
7141 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7144 if (enable_shadow_vmcs) {
7145 /* copy to memory all shadowed fields in case
7146 they were modified */
7147 copy_shadow_to_vmcs12(vmx);
7148 vmx->nested.sync_shadow_vmcs = false;
7149 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7150 SECONDARY_EXEC_SHADOW_VMCS);
7151 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7153 vmx->nested.posted_intr_nv = -1;
7155 /* Flush VMCS12 to guest memory */
7156 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7159 kunmap(vmx->nested.current_vmcs12_page);
7160 nested_release_page(vmx->nested.current_vmcs12_page);
7161 vmx->nested.current_vmptr = -1ull;
7162 vmx->nested.current_vmcs12 = NULL;
7166 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7167 * just stops using VMX.
7169 static void free_nested(struct vcpu_vmx *vmx)
7171 if (!vmx->nested.vmxon)
7174 vmx->nested.vmxon = false;
7175 free_vpid(vmx->nested.vpid02);
7176 nested_release_vmcs12(vmx);
7177 if (vmx->nested.msr_bitmap) {
7178 free_page((unsigned long)vmx->nested.msr_bitmap);
7179 vmx->nested.msr_bitmap = NULL;
7181 if (enable_shadow_vmcs) {
7182 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7183 free_vmcs(vmx->vmcs01.shadow_vmcs);
7184 vmx->vmcs01.shadow_vmcs = NULL;
7186 kfree(vmx->nested.cached_vmcs12);
7187 /* Unpin physical memory we referred to in current vmcs02 */
7188 if (vmx->nested.apic_access_page) {
7189 nested_release_page(vmx->nested.apic_access_page);
7190 vmx->nested.apic_access_page = NULL;
7192 if (vmx->nested.virtual_apic_page) {
7193 nested_release_page(vmx->nested.virtual_apic_page);
7194 vmx->nested.virtual_apic_page = NULL;
7196 if (vmx->nested.pi_desc_page) {
7197 kunmap(vmx->nested.pi_desc_page);
7198 nested_release_page(vmx->nested.pi_desc_page);
7199 vmx->nested.pi_desc_page = NULL;
7200 vmx->nested.pi_desc = NULL;
7203 nested_free_all_saved_vmcss(vmx);
7206 /* Emulate the VMXOFF instruction */
7207 static int handle_vmoff(struct kvm_vcpu *vcpu)
7209 if (!nested_vmx_check_permission(vcpu))
7211 free_nested(to_vmx(vcpu));
7212 nested_vmx_succeed(vcpu);
7213 return kvm_skip_emulated_instruction(vcpu);
7216 /* Emulate the VMCLEAR instruction */
7217 static int handle_vmclear(struct kvm_vcpu *vcpu)
7219 struct vcpu_vmx *vmx = to_vmx(vcpu);
7223 if (!nested_vmx_check_permission(vcpu))
7226 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7229 if (vmptr == vmx->nested.current_vmptr)
7230 nested_release_vmcs12(vmx);
7232 kvm_vcpu_write_guest(vcpu,
7233 vmptr + offsetof(struct vmcs12, launch_state),
7234 &zero, sizeof(zero));
7236 nested_free_vmcs02(vmx, vmptr);
7238 nested_vmx_succeed(vcpu);
7239 return kvm_skip_emulated_instruction(vcpu);
7242 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7244 /* Emulate the VMLAUNCH instruction */
7245 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7247 return nested_vmx_run(vcpu, true);
7250 /* Emulate the VMRESUME instruction */
7251 static int handle_vmresume(struct kvm_vcpu *vcpu)
7254 return nested_vmx_run(vcpu, false);
7257 enum vmcs_field_type {
7258 VMCS_FIELD_TYPE_U16 = 0,
7259 VMCS_FIELD_TYPE_U64 = 1,
7260 VMCS_FIELD_TYPE_U32 = 2,
7261 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7264 static inline int vmcs_field_type(unsigned long field)
7266 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
7267 return VMCS_FIELD_TYPE_U32;
7268 return (field >> 13) & 0x3 ;
7271 static inline int vmcs_field_readonly(unsigned long field)
7273 return (((field >> 10) & 0x3) == 1);
7277 * Read a vmcs12 field. Since these can have varying lengths and we return
7278 * one type, we chose the biggest type (u64) and zero-extend the return value
7279 * to that size. Note that the caller, handle_vmread, might need to use only
7280 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7281 * 64-bit fields are to be returned).
7283 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7284 unsigned long field, u64 *ret)
7286 short offset = vmcs_field_to_offset(field);
7292 p = ((char *)(get_vmcs12(vcpu))) + offset;
7294 switch (vmcs_field_type(field)) {
7295 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7296 *ret = *((natural_width *)p);
7298 case VMCS_FIELD_TYPE_U16:
7301 case VMCS_FIELD_TYPE_U32:
7304 case VMCS_FIELD_TYPE_U64:
7314 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7315 unsigned long field, u64 field_value){
7316 short offset = vmcs_field_to_offset(field);
7317 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7321 switch (vmcs_field_type(field)) {
7322 case VMCS_FIELD_TYPE_U16:
7323 *(u16 *)p = field_value;
7325 case VMCS_FIELD_TYPE_U32:
7326 *(u32 *)p = field_value;
7328 case VMCS_FIELD_TYPE_U64:
7329 *(u64 *)p = field_value;
7331 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7332 *(natural_width *)p = field_value;
7341 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7344 unsigned long field;
7346 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7347 const unsigned long *fields = shadow_read_write_fields;
7348 const int num_fields = max_shadow_read_write_fields;
7352 vmcs_load(shadow_vmcs);
7354 for (i = 0; i < num_fields; i++) {
7356 switch (vmcs_field_type(field)) {
7357 case VMCS_FIELD_TYPE_U16:
7358 field_value = vmcs_read16(field);
7360 case VMCS_FIELD_TYPE_U32:
7361 field_value = vmcs_read32(field);
7363 case VMCS_FIELD_TYPE_U64:
7364 field_value = vmcs_read64(field);
7366 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7367 field_value = vmcs_readl(field);
7373 vmcs12_write_any(&vmx->vcpu, field, field_value);
7376 vmcs_clear(shadow_vmcs);
7377 vmcs_load(vmx->loaded_vmcs->vmcs);
7382 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7384 const unsigned long *fields[] = {
7385 shadow_read_write_fields,
7386 shadow_read_only_fields
7388 const int max_fields[] = {
7389 max_shadow_read_write_fields,
7390 max_shadow_read_only_fields
7393 unsigned long field;
7394 u64 field_value = 0;
7395 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7397 vmcs_load(shadow_vmcs);
7399 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7400 for (i = 0; i < max_fields[q]; i++) {
7401 field = fields[q][i];
7402 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7404 switch (vmcs_field_type(field)) {
7405 case VMCS_FIELD_TYPE_U16:
7406 vmcs_write16(field, (u16)field_value);
7408 case VMCS_FIELD_TYPE_U32:
7409 vmcs_write32(field, (u32)field_value);
7411 case VMCS_FIELD_TYPE_U64:
7412 vmcs_write64(field, (u64)field_value);
7414 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7415 vmcs_writel(field, (long)field_value);
7424 vmcs_clear(shadow_vmcs);
7425 vmcs_load(vmx->loaded_vmcs->vmcs);
7429 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7430 * used before) all generate the same failure when it is missing.
7432 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7434 struct vcpu_vmx *vmx = to_vmx(vcpu);
7435 if (vmx->nested.current_vmptr == -1ull) {
7436 nested_vmx_failInvalid(vcpu);
7442 static int handle_vmread(struct kvm_vcpu *vcpu)
7444 unsigned long field;
7446 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7447 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7450 if (!nested_vmx_check_permission(vcpu))
7453 if (!nested_vmx_check_vmcs12(vcpu))
7454 return kvm_skip_emulated_instruction(vcpu);
7456 /* Decode instruction info and find the field to read */
7457 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7458 /* Read the field, zero-extended to a u64 field_value */
7459 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7460 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7461 return kvm_skip_emulated_instruction(vcpu);
7464 * Now copy part of this value to register or memory, as requested.
7465 * Note that the number of bits actually copied is 32 or 64 depending
7466 * on the guest's mode (32 or 64 bit), not on the given field's length.
7468 if (vmx_instruction_info & (1u << 10)) {
7469 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7472 if (get_vmx_mem_address(vcpu, exit_qualification,
7473 vmx_instruction_info, true, &gva))
7475 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7476 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7477 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7480 nested_vmx_succeed(vcpu);
7481 return kvm_skip_emulated_instruction(vcpu);
7485 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7487 unsigned long field;
7489 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7490 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7491 /* The value to write might be 32 or 64 bits, depending on L1's long
7492 * mode, and eventually we need to write that into a field of several
7493 * possible lengths. The code below first zero-extends the value to 64
7494 * bit (field_value), and then copies only the appropriate number of
7495 * bits into the vmcs12 field.
7497 u64 field_value = 0;
7498 struct x86_exception e;
7500 if (!nested_vmx_check_permission(vcpu))
7503 if (!nested_vmx_check_vmcs12(vcpu))
7504 return kvm_skip_emulated_instruction(vcpu);
7506 if (vmx_instruction_info & (1u << 10))
7507 field_value = kvm_register_readl(vcpu,
7508 (((vmx_instruction_info) >> 3) & 0xf));
7510 if (get_vmx_mem_address(vcpu, exit_qualification,
7511 vmx_instruction_info, false, &gva))
7513 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7514 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7515 kvm_inject_page_fault(vcpu, &e);
7521 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7522 if (vmcs_field_readonly(field)) {
7523 nested_vmx_failValid(vcpu,
7524 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7525 return kvm_skip_emulated_instruction(vcpu);
7528 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7529 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7530 return kvm_skip_emulated_instruction(vcpu);
7533 nested_vmx_succeed(vcpu);
7534 return kvm_skip_emulated_instruction(vcpu);
7537 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7539 vmx->nested.current_vmptr = vmptr;
7540 if (enable_shadow_vmcs) {
7541 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7542 SECONDARY_EXEC_SHADOW_VMCS);
7543 vmcs_write64(VMCS_LINK_POINTER,
7544 __pa(vmx->vmcs01.shadow_vmcs));
7545 vmx->nested.sync_shadow_vmcs = true;
7549 /* Emulate the VMPTRLD instruction */
7550 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7552 struct vcpu_vmx *vmx = to_vmx(vcpu);
7555 if (!nested_vmx_check_permission(vcpu))
7558 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7561 if (vmx->nested.current_vmptr != vmptr) {
7562 struct vmcs12 *new_vmcs12;
7564 page = nested_get_page(vcpu, vmptr);
7566 nested_vmx_failInvalid(vcpu);
7567 return kvm_skip_emulated_instruction(vcpu);
7569 new_vmcs12 = kmap(page);
7570 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7572 nested_release_page_clean(page);
7573 nested_vmx_failValid(vcpu,
7574 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7575 return kvm_skip_emulated_instruction(vcpu);
7578 nested_release_vmcs12(vmx);
7579 vmx->nested.current_vmcs12 = new_vmcs12;
7580 vmx->nested.current_vmcs12_page = page;
7582 * Load VMCS12 from guest memory since it is not already
7585 memcpy(vmx->nested.cached_vmcs12,
7586 vmx->nested.current_vmcs12, VMCS12_SIZE);
7587 set_current_vmptr(vmx, vmptr);
7590 nested_vmx_succeed(vcpu);
7591 return kvm_skip_emulated_instruction(vcpu);
7594 /* Emulate the VMPTRST instruction */
7595 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7597 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7598 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7600 struct x86_exception e;
7602 if (!nested_vmx_check_permission(vcpu))
7605 if (get_vmx_mem_address(vcpu, exit_qualification,
7606 vmx_instruction_info, true, &vmcs_gva))
7608 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7609 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7610 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7612 kvm_inject_page_fault(vcpu, &e);
7615 nested_vmx_succeed(vcpu);
7616 return kvm_skip_emulated_instruction(vcpu);
7619 /* Emulate the INVEPT instruction */
7620 static int handle_invept(struct kvm_vcpu *vcpu)
7622 struct vcpu_vmx *vmx = to_vmx(vcpu);
7623 u32 vmx_instruction_info, types;
7626 struct x86_exception e;
7631 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7632 SECONDARY_EXEC_ENABLE_EPT) ||
7633 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7634 kvm_queue_exception(vcpu, UD_VECTOR);
7638 if (!nested_vmx_check_permission(vcpu))
7641 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7642 kvm_queue_exception(vcpu, UD_VECTOR);
7646 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7647 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7649 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7651 if (type >= 32 || !(types & (1 << type))) {
7652 nested_vmx_failValid(vcpu,
7653 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7654 return kvm_skip_emulated_instruction(vcpu);
7657 /* According to the Intel VMX instruction reference, the memory
7658 * operand is read even if it isn't needed (e.g., for type==global)
7660 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7661 vmx_instruction_info, false, &gva))
7663 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7664 sizeof(operand), &e)) {
7665 kvm_inject_page_fault(vcpu, &e);
7670 case VMX_EPT_EXTENT_GLOBAL:
7672 * TODO: track mappings and invalidate
7673 * single context requests appropriately
7675 case VMX_EPT_EXTENT_CONTEXT:
7676 kvm_mmu_sync_roots(vcpu);
7677 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7678 nested_vmx_succeed(vcpu);
7685 return kvm_skip_emulated_instruction(vcpu);
7688 static int handle_invvpid(struct kvm_vcpu *vcpu)
7690 struct vcpu_vmx *vmx = to_vmx(vcpu);
7691 u32 vmx_instruction_info;
7692 unsigned long type, types;
7694 struct x86_exception e;
7697 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7698 SECONDARY_EXEC_ENABLE_VPID) ||
7699 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7700 kvm_queue_exception(vcpu, UD_VECTOR);
7704 if (!nested_vmx_check_permission(vcpu))
7707 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7708 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7710 types = (vmx->nested.nested_vmx_vpid_caps &
7711 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7713 if (type >= 32 || !(types & (1 << type))) {
7714 nested_vmx_failValid(vcpu,
7715 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7716 return kvm_skip_emulated_instruction(vcpu);
7719 /* according to the intel vmx instruction reference, the memory
7720 * operand is read even if it isn't needed (e.g., for type==global)
7722 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7723 vmx_instruction_info, false, &gva))
7725 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7727 kvm_inject_page_fault(vcpu, &e);
7732 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7733 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7734 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7736 nested_vmx_failValid(vcpu,
7737 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7738 return kvm_skip_emulated_instruction(vcpu);
7741 case VMX_VPID_EXTENT_ALL_CONTEXT:
7745 return kvm_skip_emulated_instruction(vcpu);
7748 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7749 nested_vmx_succeed(vcpu);
7751 return kvm_skip_emulated_instruction(vcpu);
7754 static int handle_pml_full(struct kvm_vcpu *vcpu)
7756 unsigned long exit_qualification;
7758 trace_kvm_pml_full(vcpu->vcpu_id);
7760 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7763 * PML buffer FULL happened while executing iret from NMI,
7764 * "blocked by NMI" bit has to be set before next VM entry.
7766 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7767 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7768 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7769 GUEST_INTR_STATE_NMI);
7772 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7773 * here.., and there's no userspace involvement needed for PML.
7778 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7780 kvm_lapic_expired_hv_timer(vcpu);
7785 * The exit handlers return 1 if the exit was handled fully and guest execution
7786 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7787 * to be done to userspace and return 0.
7789 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7790 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7791 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7792 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7793 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7794 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7795 [EXIT_REASON_CR_ACCESS] = handle_cr,
7796 [EXIT_REASON_DR_ACCESS] = handle_dr,
7797 [EXIT_REASON_CPUID] = handle_cpuid,
7798 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7799 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7800 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7801 [EXIT_REASON_HLT] = handle_halt,
7802 [EXIT_REASON_INVD] = handle_invd,
7803 [EXIT_REASON_INVLPG] = handle_invlpg,
7804 [EXIT_REASON_RDPMC] = handle_rdpmc,
7805 [EXIT_REASON_VMCALL] = handle_vmcall,
7806 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7807 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7808 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7809 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7810 [EXIT_REASON_VMREAD] = handle_vmread,
7811 [EXIT_REASON_VMRESUME] = handle_vmresume,
7812 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7813 [EXIT_REASON_VMOFF] = handle_vmoff,
7814 [EXIT_REASON_VMON] = handle_vmon,
7815 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7816 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7817 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7818 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7819 [EXIT_REASON_WBINVD] = handle_wbinvd,
7820 [EXIT_REASON_XSETBV] = handle_xsetbv,
7821 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7822 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7823 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7824 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7825 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7826 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7827 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7828 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7829 [EXIT_REASON_INVEPT] = handle_invept,
7830 [EXIT_REASON_INVVPID] = handle_invvpid,
7831 [EXIT_REASON_XSAVES] = handle_xsaves,
7832 [EXIT_REASON_XRSTORS] = handle_xrstors,
7833 [EXIT_REASON_PML_FULL] = handle_pml_full,
7834 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
7837 static const int kvm_vmx_max_exit_handlers =
7838 ARRAY_SIZE(kvm_vmx_exit_handlers);
7840 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7841 struct vmcs12 *vmcs12)
7843 unsigned long exit_qualification;
7844 gpa_t bitmap, last_bitmap;
7849 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7850 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7852 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7854 port = exit_qualification >> 16;
7855 size = (exit_qualification & 7) + 1;
7857 last_bitmap = (gpa_t)-1;
7862 bitmap = vmcs12->io_bitmap_a;
7863 else if (port < 0x10000)
7864 bitmap = vmcs12->io_bitmap_b;
7867 bitmap += (port & 0x7fff) / 8;
7869 if (last_bitmap != bitmap)
7870 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7872 if (b & (1 << (port & 7)))
7877 last_bitmap = bitmap;
7884 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7885 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7886 * disinterest in the current event (read or write a specific MSR) by using an
7887 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7889 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7890 struct vmcs12 *vmcs12, u32 exit_reason)
7892 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7895 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7899 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7900 * for the four combinations of read/write and low/high MSR numbers.
7901 * First we need to figure out which of the four to use:
7903 bitmap = vmcs12->msr_bitmap;
7904 if (exit_reason == EXIT_REASON_MSR_WRITE)
7906 if (msr_index >= 0xc0000000) {
7907 msr_index -= 0xc0000000;
7911 /* Then read the msr_index'th bit from this bitmap: */
7912 if (msr_index < 1024*8) {
7914 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7916 return 1 & (b >> (msr_index & 7));
7918 return true; /* let L1 handle the wrong parameter */
7922 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7923 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7924 * intercept (via guest_host_mask etc.) the current event.
7926 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7927 struct vmcs12 *vmcs12)
7929 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7930 int cr = exit_qualification & 15;
7931 int reg = (exit_qualification >> 8) & 15;
7932 unsigned long val = kvm_register_readl(vcpu, reg);
7934 switch ((exit_qualification >> 4) & 3) {
7935 case 0: /* mov to cr */
7938 if (vmcs12->cr0_guest_host_mask &
7939 (val ^ vmcs12->cr0_read_shadow))
7943 if ((vmcs12->cr3_target_count >= 1 &&
7944 vmcs12->cr3_target_value0 == val) ||
7945 (vmcs12->cr3_target_count >= 2 &&
7946 vmcs12->cr3_target_value1 == val) ||
7947 (vmcs12->cr3_target_count >= 3 &&
7948 vmcs12->cr3_target_value2 == val) ||
7949 (vmcs12->cr3_target_count >= 4 &&
7950 vmcs12->cr3_target_value3 == val))
7952 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7956 if (vmcs12->cr4_guest_host_mask &
7957 (vmcs12->cr4_read_shadow ^ val))
7961 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7967 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7968 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7971 case 1: /* mov from cr */
7974 if (vmcs12->cpu_based_vm_exec_control &
7975 CPU_BASED_CR3_STORE_EXITING)
7979 if (vmcs12->cpu_based_vm_exec_control &
7980 CPU_BASED_CR8_STORE_EXITING)
7987 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7988 * cr0. Other attempted changes are ignored, with no exit.
7990 if (vmcs12->cr0_guest_host_mask & 0xe &
7991 (val ^ vmcs12->cr0_read_shadow))
7993 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7994 !(vmcs12->cr0_read_shadow & 0x1) &&
8003 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8004 * should handle it ourselves in L0 (and then continue L2). Only call this
8005 * when in is_guest_mode (L2).
8007 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8009 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8010 struct vcpu_vmx *vmx = to_vmx(vcpu);
8011 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8012 u32 exit_reason = vmx->exit_reason;
8014 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8015 vmcs_readl(EXIT_QUALIFICATION),
8016 vmx->idt_vectoring_info,
8018 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8021 if (vmx->nested.nested_run_pending)
8024 if (unlikely(vmx->fail)) {
8025 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8026 vmcs_read32(VM_INSTRUCTION_ERROR));
8030 switch (exit_reason) {
8031 case EXIT_REASON_EXCEPTION_NMI:
8032 if (is_nmi(intr_info))
8034 else if (is_page_fault(intr_info))
8036 else if (is_no_device(intr_info) &&
8037 !(vmcs12->guest_cr0 & X86_CR0_TS))
8039 else if (is_debug(intr_info) &&
8041 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8043 else if (is_breakpoint(intr_info) &&
8044 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8046 return vmcs12->exception_bitmap &
8047 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8048 case EXIT_REASON_EXTERNAL_INTERRUPT:
8050 case EXIT_REASON_TRIPLE_FAULT:
8052 case EXIT_REASON_PENDING_INTERRUPT:
8053 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8054 case EXIT_REASON_NMI_WINDOW:
8055 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8056 case EXIT_REASON_TASK_SWITCH:
8058 case EXIT_REASON_CPUID:
8060 case EXIT_REASON_HLT:
8061 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8062 case EXIT_REASON_INVD:
8064 case EXIT_REASON_INVLPG:
8065 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8066 case EXIT_REASON_RDPMC:
8067 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8068 case EXIT_REASON_RDRAND:
8069 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8070 case EXIT_REASON_RDSEED:
8071 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8072 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8073 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8074 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8075 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8076 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8077 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8078 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8079 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8081 * VMX instructions trap unconditionally. This allows L1 to
8082 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8085 case EXIT_REASON_CR_ACCESS:
8086 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8087 case EXIT_REASON_DR_ACCESS:
8088 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8089 case EXIT_REASON_IO_INSTRUCTION:
8090 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8091 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8092 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8093 case EXIT_REASON_MSR_READ:
8094 case EXIT_REASON_MSR_WRITE:
8095 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8096 case EXIT_REASON_INVALID_STATE:
8098 case EXIT_REASON_MWAIT_INSTRUCTION:
8099 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8100 case EXIT_REASON_MONITOR_TRAP_FLAG:
8101 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8102 case EXIT_REASON_MONITOR_INSTRUCTION:
8103 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8104 case EXIT_REASON_PAUSE_INSTRUCTION:
8105 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8106 nested_cpu_has2(vmcs12,
8107 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8108 case EXIT_REASON_MCE_DURING_VMENTRY:
8110 case EXIT_REASON_TPR_BELOW_THRESHOLD:
8111 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8112 case EXIT_REASON_APIC_ACCESS:
8113 return nested_cpu_has2(vmcs12,
8114 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8115 case EXIT_REASON_APIC_WRITE:
8116 case EXIT_REASON_EOI_INDUCED:
8117 /* apic_write and eoi_induced should exit unconditionally. */
8119 case EXIT_REASON_EPT_VIOLATION:
8121 * L0 always deals with the EPT violation. If nested EPT is
8122 * used, and the nested mmu code discovers that the address is
8123 * missing in the guest EPT table (EPT12), the EPT violation
8124 * will be injected with nested_ept_inject_page_fault()
8127 case EXIT_REASON_EPT_MISCONFIG:
8129 * L2 never uses directly L1's EPT, but rather L0's own EPT
8130 * table (shadow on EPT) or a merged EPT table that L0 built
8131 * (EPT on EPT). So any problems with the structure of the
8132 * table is L0's fault.
8135 case EXIT_REASON_WBINVD:
8136 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8137 case EXIT_REASON_XSETBV:
8139 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8141 * This should never happen, since it is not possible to
8142 * set XSS to a non-zero value---neither in L1 nor in L2.
8143 * If if it were, XSS would have to be checked against
8144 * the XSS exit bitmap in vmcs12.
8146 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8147 case EXIT_REASON_PREEMPTION_TIMER:
8154 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8156 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8157 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8160 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8163 __free_page(vmx->pml_pg);
8168 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8170 struct vcpu_vmx *vmx = to_vmx(vcpu);
8174 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8176 /* Do nothing if PML buffer is empty */
8177 if (pml_idx == (PML_ENTITY_NUM - 1))
8180 /* PML index always points to next available PML buffer entity */
8181 if (pml_idx >= PML_ENTITY_NUM)
8186 pml_buf = page_address(vmx->pml_pg);
8187 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8190 gpa = pml_buf[pml_idx];
8191 WARN_ON(gpa & (PAGE_SIZE - 1));
8192 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8195 /* reset PML index */
8196 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8200 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8201 * Called before reporting dirty_bitmap to userspace.
8203 static void kvm_flush_pml_buffers(struct kvm *kvm)
8206 struct kvm_vcpu *vcpu;
8208 * We only need to kick vcpu out of guest mode here, as PML buffer
8209 * is flushed at beginning of all VMEXITs, and it's obvious that only
8210 * vcpus running in guest are possible to have unflushed GPAs in PML
8213 kvm_for_each_vcpu(i, vcpu, kvm)
8214 kvm_vcpu_kick(vcpu);
8217 static void vmx_dump_sel(char *name, uint32_t sel)
8219 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8220 name, vmcs_read16(sel),
8221 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8222 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8223 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8226 static void vmx_dump_dtsel(char *name, uint32_t limit)
8228 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8229 name, vmcs_read32(limit),
8230 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8233 static void dump_vmcs(void)
8235 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8236 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8237 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8238 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8239 u32 secondary_exec_control = 0;
8240 unsigned long cr4 = vmcs_readl(GUEST_CR4);
8241 u64 efer = vmcs_read64(GUEST_IA32_EFER);
8244 if (cpu_has_secondary_exec_ctrls())
8245 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8247 pr_err("*** Guest State ***\n");
8248 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8249 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8250 vmcs_readl(CR0_GUEST_HOST_MASK));
8251 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8252 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8253 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8254 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8255 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8257 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8258 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8259 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8260 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8262 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8263 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8264 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8265 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8266 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8267 vmcs_readl(GUEST_SYSENTER_ESP),
8268 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8269 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8270 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8271 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8272 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8273 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8274 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8275 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8276 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8277 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8278 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8279 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8280 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8281 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8282 efer, vmcs_read64(GUEST_IA32_PAT));
8283 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8284 vmcs_read64(GUEST_IA32_DEBUGCTL),
8285 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8286 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8287 pr_err("PerfGlobCtl = 0x%016llx\n",
8288 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8289 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8290 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8291 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8292 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8293 vmcs_read32(GUEST_ACTIVITY_STATE));
8294 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8295 pr_err("InterruptStatus = %04x\n",
8296 vmcs_read16(GUEST_INTR_STATUS));
8298 pr_err("*** Host State ***\n");
8299 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8300 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8301 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8302 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8303 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8304 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8305 vmcs_read16(HOST_TR_SELECTOR));
8306 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8307 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8308 vmcs_readl(HOST_TR_BASE));
8309 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8310 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8311 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8312 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8313 vmcs_readl(HOST_CR4));
8314 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8315 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8316 vmcs_read32(HOST_IA32_SYSENTER_CS),
8317 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8318 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8319 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8320 vmcs_read64(HOST_IA32_EFER),
8321 vmcs_read64(HOST_IA32_PAT));
8322 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8323 pr_err("PerfGlobCtl = 0x%016llx\n",
8324 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8326 pr_err("*** Control State ***\n");
8327 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8328 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8329 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8330 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8331 vmcs_read32(EXCEPTION_BITMAP),
8332 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8333 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8334 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8335 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8336 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8337 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8338 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8339 vmcs_read32(VM_EXIT_INTR_INFO),
8340 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8341 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8342 pr_err(" reason=%08x qualification=%016lx\n",
8343 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8344 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8345 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8346 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8347 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8348 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8349 pr_err("TSC Multiplier = 0x%016llx\n",
8350 vmcs_read64(TSC_MULTIPLIER));
8351 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8352 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8353 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8354 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8355 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8356 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8357 n = vmcs_read32(CR3_TARGET_COUNT);
8358 for (i = 0; i + 1 < n; i += 4)
8359 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8360 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8361 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8363 pr_err("CR3 target%u=%016lx\n",
8364 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8365 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8366 pr_err("PLE Gap=%08x Window=%08x\n",
8367 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8368 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8369 pr_err("Virtual processor ID = 0x%04x\n",
8370 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8374 * The guest has exited. See if we can fix it or if we need userspace
8377 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8379 struct vcpu_vmx *vmx = to_vmx(vcpu);
8380 u32 exit_reason = vmx->exit_reason;
8381 u32 vectoring_info = vmx->idt_vectoring_info;
8383 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8384 vcpu->arch.gpa_available = false;
8387 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8388 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8389 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8390 * mode as if vcpus is in root mode, the PML buffer must has been
8394 vmx_flush_pml_buffer(vcpu);
8396 /* If guest state is invalid, start emulating */
8397 if (vmx->emulation_required)
8398 return handle_invalid_guest_state(vcpu);
8400 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8401 nested_vmx_vmexit(vcpu, exit_reason,
8402 vmcs_read32(VM_EXIT_INTR_INFO),
8403 vmcs_readl(EXIT_QUALIFICATION));
8407 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8409 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8410 vcpu->run->fail_entry.hardware_entry_failure_reason
8415 if (unlikely(vmx->fail)) {
8416 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8417 vcpu->run->fail_entry.hardware_entry_failure_reason
8418 = vmcs_read32(VM_INSTRUCTION_ERROR);
8424 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8425 * delivery event since it indicates guest is accessing MMIO.
8426 * The vm-exit can be triggered again after return to guest that
8427 * will cause infinite loop.
8429 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8430 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8431 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8432 exit_reason != EXIT_REASON_PML_FULL &&
8433 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8434 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8435 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8436 vcpu->run->internal.ndata = 2;
8437 vcpu->run->internal.data[0] = vectoring_info;
8438 vcpu->run->internal.data[1] = exit_reason;
8442 if (exit_reason < kvm_vmx_max_exit_handlers
8443 && kvm_vmx_exit_handlers[exit_reason])
8444 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8446 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8448 kvm_queue_exception(vcpu, UD_VECTOR);
8453 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8455 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8457 if (is_guest_mode(vcpu) &&
8458 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8461 if (irr == -1 || tpr < irr) {
8462 vmcs_write32(TPR_THRESHOLD, 0);
8466 vmcs_write32(TPR_THRESHOLD, irr);
8469 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8471 u32 sec_exec_control;
8473 /* Postpone execution until vmcs01 is the current VMCS. */
8474 if (is_guest_mode(vcpu)) {
8475 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8479 if (!cpu_has_vmx_virtualize_x2apic_mode())
8482 if (!cpu_need_tpr_shadow(vcpu))
8485 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8488 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8489 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8491 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8492 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8493 vmx_flush_tlb_ept_only(vcpu);
8495 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8497 vmx_set_msr_bitmap(vcpu);
8500 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8502 struct vcpu_vmx *vmx = to_vmx(vcpu);
8505 * Currently we do not handle the nested case where L2 has an
8506 * APIC access page of its own; that page is still pinned.
8507 * Hence, we skip the case where the VCPU is in guest mode _and_
8508 * L1 prepared an APIC access page for L2.
8510 * For the case where L1 and L2 share the same APIC access page
8511 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8512 * in the vmcs12), this function will only update either the vmcs01
8513 * or the vmcs02. If the former, the vmcs02 will be updated by
8514 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8515 * the next L2->L1 exit.
8517 if (!is_guest_mode(vcpu) ||
8518 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8519 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8520 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8521 vmx_flush_tlb_ept_only(vcpu);
8525 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8533 status = vmcs_read16(GUEST_INTR_STATUS);
8535 if (max_isr != old) {
8537 status |= max_isr << 8;
8538 vmcs_write16(GUEST_INTR_STATUS, status);
8542 static void vmx_set_rvi(int vector)
8550 status = vmcs_read16(GUEST_INTR_STATUS);
8551 old = (u8)status & 0xff;
8552 if ((u8)vector != old) {
8554 status |= (u8)vector;
8555 vmcs_write16(GUEST_INTR_STATUS, status);
8559 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8561 if (!is_guest_mode(vcpu)) {
8562 vmx_set_rvi(max_irr);
8570 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8573 if (nested_exit_on_intr(vcpu))
8577 * Else, fall back to pre-APICv interrupt injection since L2
8578 * is run without virtual interrupt delivery.
8580 if (!kvm_event_needs_reinjection(vcpu) &&
8581 vmx_interrupt_allowed(vcpu)) {
8582 kvm_queue_interrupt(vcpu, max_irr, false);
8583 vmx_inject_irq(vcpu);
8587 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8589 struct vcpu_vmx *vmx = to_vmx(vcpu);
8592 WARN_ON(!vcpu->arch.apicv_active);
8593 if (pi_test_on(&vmx->pi_desc)) {
8594 pi_clear_on(&vmx->pi_desc);
8596 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8597 * But on x86 this is just a compiler barrier anyway.
8599 smp_mb__after_atomic();
8600 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8602 max_irr = kvm_lapic_find_highest_irr(vcpu);
8604 vmx_hwapic_irr_update(vcpu, max_irr);
8608 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8610 if (!kvm_vcpu_apicv_active(vcpu))
8613 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8614 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8615 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8616 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8619 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8621 struct vcpu_vmx *vmx = to_vmx(vcpu);
8623 pi_clear_on(&vmx->pi_desc);
8624 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8627 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8631 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8632 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8635 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8636 exit_intr_info = vmx->exit_intr_info;
8638 /* Handle machine checks before interrupts are enabled */
8639 if (is_machine_check(exit_intr_info))
8640 kvm_machine_check();
8642 /* We need to handle NMIs before interrupts are enabled */
8643 if (is_nmi(exit_intr_info)) {
8644 kvm_before_handle_nmi(&vmx->vcpu);
8646 kvm_after_handle_nmi(&vmx->vcpu);
8650 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8652 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8653 register void *__sp asm(_ASM_SP);
8655 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8656 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8657 unsigned int vector;
8658 unsigned long entry;
8660 struct vcpu_vmx *vmx = to_vmx(vcpu);
8661 #ifdef CONFIG_X86_64
8665 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8666 desc = (gate_desc *)vmx->host_idt_base + vector;
8667 entry = gate_offset(*desc);
8669 #ifdef CONFIG_X86_64
8670 "mov %%" _ASM_SP ", %[sp]\n\t"
8671 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8676 __ASM_SIZE(push) " $%c[cs]\n\t"
8677 "call *%[entry]\n\t"
8679 #ifdef CONFIG_X86_64
8685 [ss]"i"(__KERNEL_DS),
8686 [cs]"i"(__KERNEL_CS)
8691 static bool vmx_has_high_real_mode_segbase(void)
8693 return enable_unrestricted_guest || emulate_invalid_guest_state;
8696 static bool vmx_mpx_supported(void)
8698 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8699 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8702 static bool vmx_xsaves_supported(void)
8704 return vmcs_config.cpu_based_2nd_exec_ctrl &
8705 SECONDARY_EXEC_XSAVES;
8708 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8713 bool idtv_info_valid;
8715 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8717 if (vmx->nmi_known_unmasked)
8720 * Can't use vmx->exit_intr_info since we're not sure what
8721 * the exit reason is.
8723 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8724 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8725 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8727 * SDM 3: 27.7.1.2 (September 2008)
8728 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8729 * a guest IRET fault.
8730 * SDM 3: 23.2.2 (September 2008)
8731 * Bit 12 is undefined in any of the following cases:
8732 * If the VM exit sets the valid bit in the IDT-vectoring
8733 * information field.
8734 * If the VM exit is due to a double fault.
8736 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8737 vector != DF_VECTOR && !idtv_info_valid)
8738 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8739 GUEST_INTR_STATE_NMI);
8741 vmx->nmi_known_unmasked =
8742 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8743 & GUEST_INTR_STATE_NMI);
8746 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8747 u32 idt_vectoring_info,
8748 int instr_len_field,
8749 int error_code_field)
8753 bool idtv_info_valid;
8755 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8757 vcpu->arch.nmi_injected = false;
8758 kvm_clear_exception_queue(vcpu);
8759 kvm_clear_interrupt_queue(vcpu);
8761 if (!idtv_info_valid)
8764 kvm_make_request(KVM_REQ_EVENT, vcpu);
8766 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8767 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8770 case INTR_TYPE_NMI_INTR:
8771 vcpu->arch.nmi_injected = true;
8773 * SDM 3: 27.7.1.2 (September 2008)
8774 * Clear bit "block by NMI" before VM entry if a NMI
8777 vmx_set_nmi_mask(vcpu, false);
8779 case INTR_TYPE_SOFT_EXCEPTION:
8780 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8782 case INTR_TYPE_HARD_EXCEPTION:
8783 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8784 u32 err = vmcs_read32(error_code_field);
8785 kvm_requeue_exception_e(vcpu, vector, err);
8787 kvm_requeue_exception(vcpu, vector);
8789 case INTR_TYPE_SOFT_INTR:
8790 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8792 case INTR_TYPE_EXT_INTR:
8793 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8800 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8802 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8803 VM_EXIT_INSTRUCTION_LEN,
8804 IDT_VECTORING_ERROR_CODE);
8807 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8809 __vmx_complete_interrupts(vcpu,
8810 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8811 VM_ENTRY_INSTRUCTION_LEN,
8812 VM_ENTRY_EXCEPTION_ERROR_CODE);
8814 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8817 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8820 struct perf_guest_switch_msr *msrs;
8822 msrs = perf_guest_get_msrs(&nr_msrs);
8827 for (i = 0; i < nr_msrs; i++)
8828 if (msrs[i].host == msrs[i].guest)
8829 clear_atomic_switch_msr(vmx, msrs[i].msr);
8831 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8835 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8837 struct vcpu_vmx *vmx = to_vmx(vcpu);
8841 if (vmx->hv_deadline_tsc == -1)
8845 if (vmx->hv_deadline_tsc > tscl)
8846 /* sure to be 32 bit only because checked on set_hv_timer */
8847 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8848 cpu_preemption_timer_multi);
8852 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8855 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8857 struct vcpu_vmx *vmx = to_vmx(vcpu);
8858 unsigned long debugctlmsr, cr4;
8860 /* Don't enter VMX if guest state is invalid, let the exit handler
8861 start emulation until we arrive back to a valid state */
8862 if (vmx->emulation_required)
8865 if (vmx->ple_window_dirty) {
8866 vmx->ple_window_dirty = false;
8867 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8870 if (vmx->nested.sync_shadow_vmcs) {
8871 copy_vmcs12_to_shadow(vmx);
8872 vmx->nested.sync_shadow_vmcs = false;
8875 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8876 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8877 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8878 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8880 cr4 = cr4_read_shadow();
8881 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8882 vmcs_writel(HOST_CR4, cr4);
8883 vmx->host_state.vmcs_host_cr4 = cr4;
8886 /* When single-stepping over STI and MOV SS, we must clear the
8887 * corresponding interruptibility bits in the guest state. Otherwise
8888 * vmentry fails as it then expects bit 14 (BS) in pending debug
8889 * exceptions being set, but that's not correct for the guest debugging
8891 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8892 vmx_set_interrupt_shadow(vcpu, 0);
8894 if (vmx->guest_pkru_valid)
8895 __write_pkru(vmx->guest_pkru);
8897 atomic_switch_perf_msrs(vmx);
8898 debugctlmsr = get_debugctlmsr();
8900 vmx_arm_hv_timer(vcpu);
8902 vmx->__launched = vmx->loaded_vmcs->launched;
8904 /* Store host registers */
8905 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8906 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8907 "push %%" _ASM_CX " \n\t"
8908 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8910 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8911 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8913 /* Reload cr2 if changed */
8914 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8915 "mov %%cr2, %%" _ASM_DX " \n\t"
8916 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8918 "mov %%" _ASM_AX", %%cr2 \n\t"
8920 /* Check if vmlaunch of vmresume is needed */
8921 "cmpl $0, %c[launched](%0) \n\t"
8922 /* Load guest registers. Don't clobber flags. */
8923 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8924 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8925 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8926 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8927 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8928 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8929 #ifdef CONFIG_X86_64
8930 "mov %c[r8](%0), %%r8 \n\t"
8931 "mov %c[r9](%0), %%r9 \n\t"
8932 "mov %c[r10](%0), %%r10 \n\t"
8933 "mov %c[r11](%0), %%r11 \n\t"
8934 "mov %c[r12](%0), %%r12 \n\t"
8935 "mov %c[r13](%0), %%r13 \n\t"
8936 "mov %c[r14](%0), %%r14 \n\t"
8937 "mov %c[r15](%0), %%r15 \n\t"
8939 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8941 /* Enter guest mode */
8943 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8945 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8947 /* Save guest registers, load host registers, keep flags */
8948 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8950 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8951 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8952 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8953 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8954 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8955 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8956 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8957 #ifdef CONFIG_X86_64
8958 "mov %%r8, %c[r8](%0) \n\t"
8959 "mov %%r9, %c[r9](%0) \n\t"
8960 "mov %%r10, %c[r10](%0) \n\t"
8961 "mov %%r11, %c[r11](%0) \n\t"
8962 "mov %%r12, %c[r12](%0) \n\t"
8963 "mov %%r13, %c[r13](%0) \n\t"
8964 "mov %%r14, %c[r14](%0) \n\t"
8965 "mov %%r15, %c[r15](%0) \n\t"
8967 "mov %%cr2, %%" _ASM_AX " \n\t"
8968 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8970 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8971 "setbe %c[fail](%0) \n\t"
8972 ".pushsection .rodata \n\t"
8973 ".global vmx_return \n\t"
8974 "vmx_return: " _ASM_PTR " 2b \n\t"
8976 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8977 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8978 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8979 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8980 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8981 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8982 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8983 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8984 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8985 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8986 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8987 #ifdef CONFIG_X86_64
8988 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8989 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8990 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8991 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8992 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8993 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8994 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8995 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8997 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8998 [wordsize]"i"(sizeof(ulong))
9000 #ifdef CONFIG_X86_64
9001 , "rax", "rbx", "rdi", "rsi"
9002 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9004 , "eax", "ebx", "edi", "esi"
9008 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9010 update_debugctlmsr(debugctlmsr);
9012 #ifndef CONFIG_X86_64
9014 * The sysexit path does not restore ds/es, so we must set them to
9015 * a reasonable value ourselves.
9017 * We can't defer this to vmx_load_host_state() since that function
9018 * may be executed in interrupt context, which saves and restore segments
9019 * around it, nullifying its effect.
9021 loadsegment(ds, __USER_DS);
9022 loadsegment(es, __USER_DS);
9025 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9026 | (1 << VCPU_EXREG_RFLAGS)
9027 | (1 << VCPU_EXREG_PDPTR)
9028 | (1 << VCPU_EXREG_SEGMENTS)
9029 | (1 << VCPU_EXREG_CR3));
9030 vcpu->arch.regs_dirty = 0;
9032 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9034 vmx->loaded_vmcs->launched = 1;
9036 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9039 * eager fpu is enabled if PKEY is supported and CR4 is switched
9040 * back on host, so it is safe to read guest PKRU from current
9043 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9044 vmx->guest_pkru = __read_pkru();
9045 if (vmx->guest_pkru != vmx->host_pkru) {
9046 vmx->guest_pkru_valid = true;
9047 __write_pkru(vmx->host_pkru);
9049 vmx->guest_pkru_valid = false;
9053 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9054 * we did not inject a still-pending event to L1 now because of
9055 * nested_run_pending, we need to re-enable this bit.
9057 if (vmx->nested.nested_run_pending)
9058 kvm_make_request(KVM_REQ_EVENT, vcpu);
9060 vmx->nested.nested_run_pending = 0;
9062 vmx_complete_atomic_exit(vmx);
9063 vmx_recover_nmi_blocking(vmx);
9064 vmx_complete_interrupts(vmx);
9067 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9069 struct vcpu_vmx *vmx = to_vmx(vcpu);
9072 if (vmx->loaded_vmcs == vmcs)
9076 vmx->loaded_vmcs = vmcs;
9078 vmx_vcpu_load(vcpu, cpu);
9084 * Ensure that the current vmcs of the logical processor is the
9085 * vmcs01 of the vcpu before calling free_nested().
9087 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9089 struct vcpu_vmx *vmx = to_vmx(vcpu);
9092 r = vcpu_load(vcpu);
9094 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9099 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9101 struct vcpu_vmx *vmx = to_vmx(vcpu);
9104 vmx_destroy_pml_buffer(vmx);
9105 free_vpid(vmx->vpid);
9106 leave_guest_mode(vcpu);
9107 vmx_free_vcpu_nested(vcpu);
9108 free_loaded_vmcs(vmx->loaded_vmcs);
9109 kfree(vmx->guest_msrs);
9110 kvm_vcpu_uninit(vcpu);
9111 kmem_cache_free(kvm_vcpu_cache, vmx);
9114 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9117 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9121 return ERR_PTR(-ENOMEM);
9123 vmx->vpid = allocate_vpid();
9125 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9132 * If PML is turned on, failure on enabling PML just results in failure
9133 * of creating the vcpu, therefore we can simplify PML logic (by
9134 * avoiding dealing with cases, such as enabling PML partially on vcpus
9135 * for the guest, etc.
9138 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9143 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9144 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9147 if (!vmx->guest_msrs)
9150 vmx->loaded_vmcs = &vmx->vmcs01;
9151 vmx->loaded_vmcs->vmcs = alloc_vmcs();
9152 vmx->loaded_vmcs->shadow_vmcs = NULL;
9153 if (!vmx->loaded_vmcs->vmcs)
9155 loaded_vmcs_init(vmx->loaded_vmcs);
9158 vmx_vcpu_load(&vmx->vcpu, cpu);
9159 vmx->vcpu.cpu = cpu;
9160 err = vmx_vcpu_setup(vmx);
9161 vmx_vcpu_put(&vmx->vcpu);
9165 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9166 err = alloc_apic_access_page(kvm);
9172 if (!kvm->arch.ept_identity_map_addr)
9173 kvm->arch.ept_identity_map_addr =
9174 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9175 err = init_rmode_identity_map(kvm);
9181 nested_vmx_setup_ctls_msrs(vmx);
9182 vmx->nested.vpid02 = allocate_vpid();
9185 vmx->nested.posted_intr_nv = -1;
9186 vmx->nested.current_vmptr = -1ull;
9187 vmx->nested.current_vmcs12 = NULL;
9189 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9194 free_vpid(vmx->nested.vpid02);
9195 free_loaded_vmcs(vmx->loaded_vmcs);
9197 kfree(vmx->guest_msrs);
9199 vmx_destroy_pml_buffer(vmx);
9201 kvm_vcpu_uninit(&vmx->vcpu);
9203 free_vpid(vmx->vpid);
9204 kmem_cache_free(kvm_vcpu_cache, vmx);
9205 return ERR_PTR(err);
9208 static void __init vmx_check_processor_compat(void *rtn)
9210 struct vmcs_config vmcs_conf;
9213 if (setup_vmcs_config(&vmcs_conf) < 0)
9215 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9216 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9217 smp_processor_id());
9222 static int get_ept_level(void)
9224 return VMX_EPT_DEFAULT_GAW + 1;
9227 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9232 /* For VT-d and EPT combination
9233 * 1. MMIO: always map as UC
9235 * a. VT-d without snooping control feature: can't guarantee the
9236 * result, try to trust guest.
9237 * b. VT-d with snooping control feature: snooping control feature of
9238 * VT-d engine can guarantee the cache correctness. Just set it
9239 * to WB to keep consistent with host. So the same as item 3.
9240 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9241 * consistent with host MTRR
9244 cache = MTRR_TYPE_UNCACHABLE;
9248 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9249 ipat = VMX_EPT_IPAT_BIT;
9250 cache = MTRR_TYPE_WRBACK;
9254 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9255 ipat = VMX_EPT_IPAT_BIT;
9256 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9257 cache = MTRR_TYPE_WRBACK;
9259 cache = MTRR_TYPE_UNCACHABLE;
9263 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9266 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9269 static int vmx_get_lpage_level(void)
9271 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9272 return PT_DIRECTORY_LEVEL;
9274 /* For shadow and EPT supported 1GB page */
9275 return PT_PDPE_LEVEL;
9278 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9281 * These bits in the secondary execution controls field
9282 * are dynamic, the others are mostly based on the hypervisor
9283 * architecture and the guest's CPUID. Do not touch the
9287 SECONDARY_EXEC_SHADOW_VMCS |
9288 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9289 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9291 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9293 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9294 (new_ctl & ~mask) | (cur_ctl & mask));
9298 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9299 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9301 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9303 struct vcpu_vmx *vmx = to_vmx(vcpu);
9304 struct kvm_cpuid_entry2 *entry;
9306 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9307 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9309 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9310 if (entry && (entry->_reg & (_cpuid_mask))) \
9311 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9314 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9315 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9316 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9317 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9318 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9319 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9320 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9321 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9322 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9323 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9324 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9325 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9326 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9327 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9328 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9330 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9331 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9332 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9333 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9334 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9335 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9336 cr4_fixed1_update(bit(11), ecx, bit(2));
9338 #undef cr4_fixed1_update
9341 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9343 struct kvm_cpuid_entry2 *best;
9344 struct vcpu_vmx *vmx = to_vmx(vcpu);
9345 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9347 if (vmx_rdtscp_supported()) {
9348 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9349 if (!rdtscp_enabled)
9350 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9354 vmx->nested.nested_vmx_secondary_ctls_high |=
9355 SECONDARY_EXEC_RDTSCP;
9357 vmx->nested.nested_vmx_secondary_ctls_high &=
9358 ~SECONDARY_EXEC_RDTSCP;
9362 /* Exposing INVPCID only when PCID is exposed */
9363 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9364 if (vmx_invpcid_supported() &&
9365 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9366 !guest_cpuid_has_pcid(vcpu))) {
9367 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9370 best->ebx &= ~bit(X86_FEATURE_INVPCID);
9373 if (cpu_has_secondary_exec_ctrls())
9374 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9376 if (nested_vmx_allowed(vcpu))
9377 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9378 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9380 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9381 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9383 if (nested_vmx_allowed(vcpu))
9384 nested_vmx_cr_fixed1_bits_update(vcpu);
9387 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9389 if (func == 1 && nested)
9390 entry->ecx |= bit(X86_FEATURE_VMX);
9393 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9394 struct x86_exception *fault)
9396 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9399 if (fault->error_code & PFERR_RSVD_MASK)
9400 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9402 exit_reason = EXIT_REASON_EPT_VIOLATION;
9403 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9404 vmcs12->guest_physical_address = fault->address;
9407 /* Callbacks for nested_ept_init_mmu_context: */
9409 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9411 /* return the page table to be shadowed - in our case, EPT12 */
9412 return get_vmcs12(vcpu)->ept_pointer;
9415 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9419 WARN_ON(mmu_is_nested(vcpu));
9420 eptp = nested_ept_get_cr3(vcpu);
9421 if ((eptp & VMX_EPT_AD_ENABLE_BIT) && !enable_ept_ad_bits)
9424 kvm_mmu_unload(vcpu);
9425 kvm_init_shadow_ept_mmu(vcpu,
9426 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9427 VMX_EPT_EXECUTE_ONLY_BIT,
9428 eptp & VMX_EPT_AD_ENABLE_BIT);
9429 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9430 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9431 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9433 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
9437 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9439 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9442 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9445 bool inequality, bit;
9447 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9449 (error_code & vmcs12->page_fault_error_code_mask) !=
9450 vmcs12->page_fault_error_code_match;
9451 return inequality ^ bit;
9454 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9455 struct x86_exception *fault)
9457 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9459 WARN_ON(!is_guest_mode(vcpu));
9461 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9462 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9463 vmcs_read32(VM_EXIT_INTR_INFO),
9464 vmcs_readl(EXIT_QUALIFICATION));
9466 kvm_inject_page_fault(vcpu, fault);
9469 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9470 struct vmcs12 *vmcs12);
9472 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9473 struct vmcs12 *vmcs12)
9475 struct vcpu_vmx *vmx = to_vmx(vcpu);
9478 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9480 * Translate L1 physical address to host physical
9481 * address for vmcs02. Keep the page pinned, so this
9482 * physical address remains valid. We keep a reference
9483 * to it so we can release it later.
9485 if (vmx->nested.apic_access_page) /* shouldn't happen */
9486 nested_release_page(vmx->nested.apic_access_page);
9487 vmx->nested.apic_access_page =
9488 nested_get_page(vcpu, vmcs12->apic_access_addr);
9490 * If translation failed, no matter: This feature asks
9491 * to exit when accessing the given address, and if it
9492 * can never be accessed, this feature won't do
9495 if (vmx->nested.apic_access_page) {
9496 hpa = page_to_phys(vmx->nested.apic_access_page);
9497 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9499 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9500 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9502 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9503 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9504 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9505 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9506 kvm_vcpu_reload_apic_access_page(vcpu);
9509 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9510 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9511 nested_release_page(vmx->nested.virtual_apic_page);
9512 vmx->nested.virtual_apic_page =
9513 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9516 * If translation failed, VM entry will fail because
9517 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9518 * Failing the vm entry is _not_ what the processor
9519 * does but it's basically the only possibility we
9520 * have. We could still enter the guest if CR8 load
9521 * exits are enabled, CR8 store exits are enabled, and
9522 * virtualize APIC access is disabled; in this case
9523 * the processor would never use the TPR shadow and we
9524 * could simply clear the bit from the execution
9525 * control. But such a configuration is useless, so
9526 * let's keep the code simple.
9528 if (vmx->nested.virtual_apic_page) {
9529 hpa = page_to_phys(vmx->nested.virtual_apic_page);
9530 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9534 if (nested_cpu_has_posted_intr(vmcs12)) {
9535 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9536 kunmap(vmx->nested.pi_desc_page);
9537 nested_release_page(vmx->nested.pi_desc_page);
9539 vmx->nested.pi_desc_page =
9540 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9541 vmx->nested.pi_desc =
9542 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9543 if (!vmx->nested.pi_desc) {
9544 nested_release_page_clean(vmx->nested.pi_desc_page);
9547 vmx->nested.pi_desc =
9548 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9549 (unsigned long)(vmcs12->posted_intr_desc_addr &
9551 vmcs_write64(POSTED_INTR_DESC_ADDR,
9552 page_to_phys(vmx->nested.pi_desc_page) +
9553 (unsigned long)(vmcs12->posted_intr_desc_addr &
9556 if (cpu_has_vmx_msr_bitmap() &&
9557 nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9558 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9561 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9562 CPU_BASED_USE_MSR_BITMAPS);
9565 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9567 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9568 struct vcpu_vmx *vmx = to_vmx(vcpu);
9570 if (vcpu->arch.virtual_tsc_khz == 0)
9573 /* Make sure short timeouts reliably trigger an immediate vmexit.
9574 * hrtimer_start does not guarantee this. */
9575 if (preemption_timeout <= 1) {
9576 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9580 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9581 preemption_timeout *= 1000000;
9582 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9583 hrtimer_start(&vmx->nested.preemption_timer,
9584 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9587 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9588 struct vmcs12 *vmcs12)
9593 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9596 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9600 maxphyaddr = cpuid_maxphyaddr(vcpu);
9602 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9603 ((addr + PAGE_SIZE) >> maxphyaddr))
9610 * Merge L0's and L1's MSR bitmap, return false to indicate that
9611 * we do not use the hardware.
9613 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9614 struct vmcs12 *vmcs12)
9618 unsigned long *msr_bitmap_l1;
9619 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9621 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9622 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9625 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9628 msr_bitmap_l1 = (unsigned long *)kmap(page);
9630 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9632 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9633 if (nested_cpu_has_apic_reg_virt(vmcs12))
9634 for (msr = 0x800; msr <= 0x8ff; msr++)
9635 nested_vmx_disable_intercept_for_msr(
9636 msr_bitmap_l1, msr_bitmap_l0,
9639 nested_vmx_disable_intercept_for_msr(
9640 msr_bitmap_l1, msr_bitmap_l0,
9641 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9642 MSR_TYPE_R | MSR_TYPE_W);
9644 if (nested_cpu_has_vid(vmcs12)) {
9645 nested_vmx_disable_intercept_for_msr(
9646 msr_bitmap_l1, msr_bitmap_l0,
9647 APIC_BASE_MSR + (APIC_EOI >> 4),
9649 nested_vmx_disable_intercept_for_msr(
9650 msr_bitmap_l1, msr_bitmap_l0,
9651 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9656 nested_release_page_clean(page);
9661 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9662 struct vmcs12 *vmcs12)
9664 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9665 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9666 !nested_cpu_has_vid(vmcs12) &&
9667 !nested_cpu_has_posted_intr(vmcs12))
9671 * If virtualize x2apic mode is enabled,
9672 * virtualize apic access must be disabled.
9674 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9675 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9679 * If virtual interrupt delivery is enabled,
9680 * we must exit on external interrupts.
9682 if (nested_cpu_has_vid(vmcs12) &&
9683 !nested_exit_on_intr(vcpu))
9687 * bits 15:8 should be zero in posted_intr_nv,
9688 * the descriptor address has been already checked
9689 * in nested_get_vmcs12_pages.
9691 if (nested_cpu_has_posted_intr(vmcs12) &&
9692 (!nested_cpu_has_vid(vmcs12) ||
9693 !nested_exit_intr_ack_set(vcpu) ||
9694 vmcs12->posted_intr_nv & 0xff00))
9697 /* tpr shadow is needed by all apicv features. */
9698 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9704 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9705 unsigned long count_field,
9706 unsigned long addr_field)
9711 if (vmcs12_read_any(vcpu, count_field, &count) ||
9712 vmcs12_read_any(vcpu, addr_field, &addr)) {
9718 maxphyaddr = cpuid_maxphyaddr(vcpu);
9719 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9720 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9721 pr_debug_ratelimited(
9722 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9723 addr_field, maxphyaddr, count, addr);
9729 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9730 struct vmcs12 *vmcs12)
9732 if (vmcs12->vm_exit_msr_load_count == 0 &&
9733 vmcs12->vm_exit_msr_store_count == 0 &&
9734 vmcs12->vm_entry_msr_load_count == 0)
9735 return 0; /* Fast path */
9736 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9737 VM_EXIT_MSR_LOAD_ADDR) ||
9738 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9739 VM_EXIT_MSR_STORE_ADDR) ||
9740 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9741 VM_ENTRY_MSR_LOAD_ADDR))
9746 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9747 struct vmx_msr_entry *e)
9749 /* x2APIC MSR accesses are not allowed */
9750 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9752 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9753 e->index == MSR_IA32_UCODE_REV)
9755 if (e->reserved != 0)
9760 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9761 struct vmx_msr_entry *e)
9763 if (e->index == MSR_FS_BASE ||
9764 e->index == MSR_GS_BASE ||
9765 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9766 nested_vmx_msr_check_common(vcpu, e))
9771 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9772 struct vmx_msr_entry *e)
9774 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9775 nested_vmx_msr_check_common(vcpu, e))
9781 * Load guest's/host's msr at nested entry/exit.
9782 * return 0 for success, entry index for failure.
9784 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9787 struct vmx_msr_entry e;
9788 struct msr_data msr;
9790 msr.host_initiated = false;
9791 for (i = 0; i < count; i++) {
9792 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9794 pr_debug_ratelimited(
9795 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9796 __func__, i, gpa + i * sizeof(e));
9799 if (nested_vmx_load_msr_check(vcpu, &e)) {
9800 pr_debug_ratelimited(
9801 "%s check failed (%u, 0x%x, 0x%x)\n",
9802 __func__, i, e.index, e.reserved);
9805 msr.index = e.index;
9807 if (kvm_set_msr(vcpu, &msr)) {
9808 pr_debug_ratelimited(
9809 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9810 __func__, i, e.index, e.value);
9819 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9822 struct vmx_msr_entry e;
9824 for (i = 0; i < count; i++) {
9825 struct msr_data msr_info;
9826 if (kvm_vcpu_read_guest(vcpu,
9827 gpa + i * sizeof(e),
9828 &e, 2 * sizeof(u32))) {
9829 pr_debug_ratelimited(
9830 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9831 __func__, i, gpa + i * sizeof(e));
9834 if (nested_vmx_store_msr_check(vcpu, &e)) {
9835 pr_debug_ratelimited(
9836 "%s check failed (%u, 0x%x, 0x%x)\n",
9837 __func__, i, e.index, e.reserved);
9840 msr_info.host_initiated = false;
9841 msr_info.index = e.index;
9842 if (kvm_get_msr(vcpu, &msr_info)) {
9843 pr_debug_ratelimited(
9844 "%s cannot read MSR (%u, 0x%x)\n",
9845 __func__, i, e.index);
9848 if (kvm_vcpu_write_guest(vcpu,
9849 gpa + i * sizeof(e) +
9850 offsetof(struct vmx_msr_entry, value),
9851 &msr_info.data, sizeof(msr_info.data))) {
9852 pr_debug_ratelimited(
9853 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9854 __func__, i, e.index, msr_info.data);
9861 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9863 unsigned long invalid_mask;
9865 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9866 return (val & invalid_mask) == 0;
9870 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9871 * emulating VM entry into a guest with EPT enabled.
9872 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9873 * is assigned to entry_failure_code on failure.
9875 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9876 u32 *entry_failure_code)
9878 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9879 if (!nested_cr3_valid(vcpu, cr3)) {
9880 *entry_failure_code = ENTRY_FAIL_DEFAULT;
9885 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9886 * must not be dereferenced.
9888 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9890 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9891 *entry_failure_code = ENTRY_FAIL_PDPTE;
9896 vcpu->arch.cr3 = cr3;
9897 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9900 kvm_mmu_reset_context(vcpu);
9905 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9906 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9907 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9908 * guest in a way that will both be appropriate to L1's requests, and our
9909 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9910 * function also has additional necessary side-effects, like setting various
9911 * vcpu->arch fields.
9912 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9913 * is assigned to entry_failure_code on failure.
9915 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9916 bool from_vmentry, u32 *entry_failure_code)
9918 struct vcpu_vmx *vmx = to_vmx(vcpu);
9921 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9922 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9923 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9924 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9925 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9926 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9927 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9928 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9929 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9930 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9931 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9932 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9933 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9934 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9935 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9936 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9937 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9938 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9939 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9940 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9941 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9942 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9943 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9944 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9945 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9946 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9947 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9948 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9949 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9950 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9951 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9952 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9953 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9954 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9955 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9956 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9959 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
9960 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9961 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9963 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9964 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9967 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9968 vmcs12->vm_entry_intr_info_field);
9969 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9970 vmcs12->vm_entry_exception_error_code);
9971 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9972 vmcs12->vm_entry_instruction_len);
9973 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9974 vmcs12->guest_interruptibility_info);
9976 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9978 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9979 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9980 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9981 vmcs12->guest_pending_dbg_exceptions);
9982 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9983 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9985 if (nested_cpu_has_xsaves(vmcs12))
9986 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9987 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9989 exec_control = vmcs12->pin_based_vm_exec_control;
9991 /* Preemption timer setting is only taken from vmcs01. */
9992 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9993 exec_control |= vmcs_config.pin_based_exec_ctrl;
9994 if (vmx->hv_deadline_tsc == -1)
9995 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9997 /* Posted interrupts setting is only taken from vmcs12. */
9998 if (nested_cpu_has_posted_intr(vmcs12)) {
10000 * Note that we use L0's vector here and in
10001 * vmx_deliver_nested_posted_interrupt.
10003 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10004 vmx->nested.pi_pending = false;
10005 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10007 exec_control &= ~PIN_BASED_POSTED_INTR;
10010 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10012 vmx->nested.preemption_timer_expired = false;
10013 if (nested_cpu_has_preemption_timer(vmcs12))
10014 vmx_start_preemption_timer(vcpu);
10017 * Whether page-faults are trapped is determined by a combination of
10018 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10019 * If enable_ept, L0 doesn't care about page faults and we should
10020 * set all of these to L1's desires. However, if !enable_ept, L0 does
10021 * care about (at least some) page faults, and because it is not easy
10022 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10023 * to exit on each and every L2 page fault. This is done by setting
10024 * MASK=MATCH=0 and (see below) EB.PF=1.
10025 * Note that below we don't need special code to set EB.PF beyond the
10026 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10027 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10028 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10030 * A problem with this approach (when !enable_ept) is that L1 may be
10031 * injected with more page faults than it asked for. This could have
10032 * caused problems, but in practice existing hypervisors don't care.
10033 * To fix this, we will need to emulate the PFEC checking (on the L1
10034 * page tables), using walk_addr(), when injecting PFs to L1.
10036 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10037 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10038 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10039 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10041 if (cpu_has_secondary_exec_ctrls()) {
10042 exec_control = vmx_secondary_exec_control(vmx);
10044 /* Take the following fields only from vmcs12 */
10045 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10046 SECONDARY_EXEC_RDTSCP |
10047 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10048 SECONDARY_EXEC_APIC_REGISTER_VIRT);
10049 if (nested_cpu_has(vmcs12,
10050 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10051 exec_control |= vmcs12->secondary_vm_exec_control;
10053 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10054 vmcs_write64(EOI_EXIT_BITMAP0,
10055 vmcs12->eoi_exit_bitmap0);
10056 vmcs_write64(EOI_EXIT_BITMAP1,
10057 vmcs12->eoi_exit_bitmap1);
10058 vmcs_write64(EOI_EXIT_BITMAP2,
10059 vmcs12->eoi_exit_bitmap2);
10060 vmcs_write64(EOI_EXIT_BITMAP3,
10061 vmcs12->eoi_exit_bitmap3);
10062 vmcs_write16(GUEST_INTR_STATUS,
10063 vmcs12->guest_intr_status);
10067 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10068 * nested_get_vmcs12_pages will either fix it up or
10069 * remove the VM execution control.
10071 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10072 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10074 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10079 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10080 * Some constant fields are set here by vmx_set_constant_host_state().
10081 * Other fields are different per CPU, and will be set later when
10082 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10084 vmx_set_constant_host_state(vmx);
10087 * Set the MSR load/store lists to match L0's settings.
10089 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10090 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10091 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10092 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10093 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10096 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10097 * entry, but only if the current (host) sp changed from the value
10098 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10099 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10100 * here we just force the write to happen on entry.
10104 exec_control = vmx_exec_control(vmx); /* L0's desires */
10105 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10106 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10107 exec_control &= ~CPU_BASED_TPR_SHADOW;
10108 exec_control |= vmcs12->cpu_based_vm_exec_control;
10111 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10112 * nested_get_vmcs12_pages can't fix it up, the illegal value
10113 * will result in a VM entry failure.
10115 if (exec_control & CPU_BASED_TPR_SHADOW) {
10116 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10117 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10121 * Merging of IO bitmap not currently supported.
10122 * Rather, exit every time.
10124 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10125 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10127 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10129 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10130 * bitwise-or of what L1 wants to trap for L2, and what we want to
10131 * trap. Note that CR0.TS also needs updating - we do this later.
10133 update_exception_bitmap(vcpu);
10134 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10135 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10137 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10138 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10139 * bits are further modified by vmx_set_efer() below.
10141 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10143 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10144 * emulated by vmx_set_efer(), below.
10146 vm_entry_controls_init(vmx,
10147 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10148 ~VM_ENTRY_IA32E_MODE) |
10149 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10151 if (from_vmentry &&
10152 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10153 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10154 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10155 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10156 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10159 set_cr4_guest_host_mask(vmx);
10161 if (from_vmentry &&
10162 vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10163 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10165 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10166 vmcs_write64(TSC_OFFSET,
10167 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10169 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10170 if (kvm_has_tsc_control)
10171 decache_tsc_multiplier(vmx);
10175 * There is no direct mapping between vpid02 and vpid12, the
10176 * vpid02 is per-vCPU for L0 and reused while the value of
10177 * vpid12 is changed w/ one invvpid during nested vmentry.
10178 * The vpid12 is allocated by L1 for L2, so it will not
10179 * influence global bitmap(for vpid01 and vpid02 allocation)
10180 * even if spawn a lot of nested vCPUs.
10182 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10183 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10184 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10185 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10186 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10189 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10190 vmx_flush_tlb(vcpu);
10195 if (nested_cpu_has_ept(vmcs12)) {
10196 if (nested_ept_init_mmu_context(vcpu)) {
10197 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10200 } else if (nested_cpu_has2(vmcs12,
10201 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10202 vmx_flush_tlb_ept_only(vcpu);
10206 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10207 * bits which we consider mandatory enabled.
10208 * The CR0_READ_SHADOW is what L2 should have expected to read given
10209 * the specifications by L1; It's not enough to take
10210 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10211 * have more bits than L1 expected.
10213 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10214 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10216 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10217 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10219 if (from_vmentry &&
10220 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10221 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10222 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10223 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10225 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10226 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10227 vmx_set_efer(vcpu, vcpu->arch.efer);
10229 /* Shadow page tables on either EPT or shadow page tables. */
10230 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10231 entry_failure_code))
10235 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10238 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10241 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10242 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10243 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10244 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10247 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10248 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10252 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10254 struct vcpu_vmx *vmx = to_vmx(vcpu);
10256 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10257 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10258 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10260 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10261 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10263 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10264 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10266 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10267 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10269 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10270 vmx->nested.nested_vmx_procbased_ctls_low,
10271 vmx->nested.nested_vmx_procbased_ctls_high) ||
10272 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10273 vmx->nested.nested_vmx_secondary_ctls_low,
10274 vmx->nested.nested_vmx_secondary_ctls_high) ||
10275 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10276 vmx->nested.nested_vmx_pinbased_ctls_low,
10277 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10278 !vmx_control_verify(vmcs12->vm_exit_controls,
10279 vmx->nested.nested_vmx_exit_ctls_low,
10280 vmx->nested.nested_vmx_exit_ctls_high) ||
10281 !vmx_control_verify(vmcs12->vm_entry_controls,
10282 vmx->nested.nested_vmx_entry_ctls_low,
10283 vmx->nested.nested_vmx_entry_ctls_high))
10284 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10286 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10287 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10288 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10289 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10294 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10299 *exit_qual = ENTRY_FAIL_DEFAULT;
10301 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10302 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10305 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10306 vmcs12->vmcs_link_pointer != -1ull) {
10307 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10312 * If the load IA32_EFER VM-entry control is 1, the following checks
10313 * are performed on the field for the IA32_EFER MSR:
10314 * - Bits reserved in the IA32_EFER MSR must be 0.
10315 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10316 * the IA-32e mode guest VM-exit control. It must also be identical
10317 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10320 if (to_vmx(vcpu)->nested.nested_run_pending &&
10321 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10322 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10323 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10324 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10325 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10326 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10331 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10332 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10333 * the values of the LMA and LME bits in the field must each be that of
10334 * the host address-space size VM-exit control.
10336 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10337 ia32e = (vmcs12->vm_exit_controls &
10338 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10339 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10340 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10341 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10348 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10350 struct vcpu_vmx *vmx = to_vmx(vcpu);
10351 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10352 struct loaded_vmcs *vmcs02;
10356 vmcs02 = nested_get_current_vmcs02(vmx);
10360 enter_guest_mode(vcpu);
10362 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10363 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10365 vmx_switch_vmcs(vcpu, vmcs02);
10366 vmx_segment_cache_clear(vmx);
10368 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10369 leave_guest_mode(vcpu);
10370 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10371 nested_vmx_entry_failure(vcpu, vmcs12,
10372 EXIT_REASON_INVALID_STATE, exit_qual);
10376 nested_get_vmcs12_pages(vcpu, vmcs12);
10378 msr_entry_idx = nested_vmx_load_msr(vcpu,
10379 vmcs12->vm_entry_msr_load_addr,
10380 vmcs12->vm_entry_msr_load_count);
10381 if (msr_entry_idx) {
10382 leave_guest_mode(vcpu);
10383 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10384 nested_vmx_entry_failure(vcpu, vmcs12,
10385 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10389 vmcs12->launch_state = 1;
10392 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10393 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10394 * returned as far as L1 is concerned. It will only return (and set
10395 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10401 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10402 * for running an L2 nested guest.
10404 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10406 struct vmcs12 *vmcs12;
10407 struct vcpu_vmx *vmx = to_vmx(vcpu);
10411 if (!nested_vmx_check_permission(vcpu))
10414 if (!nested_vmx_check_vmcs12(vcpu))
10417 vmcs12 = get_vmcs12(vcpu);
10419 if (enable_shadow_vmcs)
10420 copy_shadow_to_vmcs12(vmx);
10423 * The nested entry process starts with enforcing various prerequisites
10424 * on vmcs12 as required by the Intel SDM, and act appropriately when
10425 * they fail: As the SDM explains, some conditions should cause the
10426 * instruction to fail, while others will cause the instruction to seem
10427 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10428 * To speed up the normal (success) code path, we should avoid checking
10429 * for misconfigurations which will anyway be caught by the processor
10430 * when using the merged vmcs02.
10432 if (vmcs12->launch_state == launch) {
10433 nested_vmx_failValid(vcpu,
10434 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10435 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10439 ret = check_vmentry_prereqs(vcpu, vmcs12);
10441 nested_vmx_failValid(vcpu, ret);
10446 * After this point, the trap flag no longer triggers a singlestep trap
10447 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10448 * This is not 100% correct; for performance reasons, we delegate most
10449 * of the checks on host state to the processor. If those fail,
10450 * the singlestep trap is missed.
10452 skip_emulated_instruction(vcpu);
10454 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10456 nested_vmx_entry_failure(vcpu, vmcs12,
10457 EXIT_REASON_INVALID_STATE, exit_qual);
10462 * We're finally done with prerequisite checking, and can start with
10463 * the nested entry.
10466 ret = enter_vmx_non_root_mode(vcpu, true);
10470 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10471 return kvm_vcpu_halt(vcpu);
10473 vmx->nested.nested_run_pending = 1;
10478 return kvm_skip_emulated_instruction(vcpu);
10482 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10483 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10484 * This function returns the new value we should put in vmcs12.guest_cr0.
10485 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10486 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10487 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10488 * didn't trap the bit, because if L1 did, so would L0).
10489 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10490 * been modified by L2, and L1 knows it. So just leave the old value of
10491 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10492 * isn't relevant, because if L0 traps this bit it can set it to anything.
10493 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10494 * changed these bits, and therefore they need to be updated, but L0
10495 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10496 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10498 static inline unsigned long
10499 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10502 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10503 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10504 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10505 vcpu->arch.cr0_guest_owned_bits));
10508 static inline unsigned long
10509 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10512 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10513 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10514 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10515 vcpu->arch.cr4_guest_owned_bits));
10518 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10519 struct vmcs12 *vmcs12)
10524 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10525 nr = vcpu->arch.exception.nr;
10526 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10528 if (kvm_exception_is_soft(nr)) {
10529 vmcs12->vm_exit_instruction_len =
10530 vcpu->arch.event_exit_inst_len;
10531 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10533 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10535 if (vcpu->arch.exception.has_error_code) {
10536 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10537 vmcs12->idt_vectoring_error_code =
10538 vcpu->arch.exception.error_code;
10541 vmcs12->idt_vectoring_info_field = idt_vectoring;
10542 } else if (vcpu->arch.nmi_injected) {
10543 vmcs12->idt_vectoring_info_field =
10544 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10545 } else if (vcpu->arch.interrupt.pending) {
10546 nr = vcpu->arch.interrupt.nr;
10547 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10549 if (vcpu->arch.interrupt.soft) {
10550 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10551 vmcs12->vm_entry_instruction_len =
10552 vcpu->arch.event_exit_inst_len;
10554 idt_vectoring |= INTR_TYPE_EXT_INTR;
10556 vmcs12->idt_vectoring_info_field = idt_vectoring;
10560 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10562 struct vcpu_vmx *vmx = to_vmx(vcpu);
10564 if (vcpu->arch.exception.pending ||
10565 vcpu->arch.nmi_injected ||
10566 vcpu->arch.interrupt.pending)
10569 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10570 vmx->nested.preemption_timer_expired) {
10571 if (vmx->nested.nested_run_pending)
10573 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10577 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10578 if (vmx->nested.nested_run_pending)
10580 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10581 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10582 INTR_INFO_VALID_MASK, 0);
10584 * The NMI-triggered VM exit counts as injection:
10585 * clear this one and block further NMIs.
10587 vcpu->arch.nmi_pending = 0;
10588 vmx_set_nmi_mask(vcpu, true);
10592 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10593 nested_exit_on_intr(vcpu)) {
10594 if (vmx->nested.nested_run_pending)
10596 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10600 vmx_complete_nested_posted_interrupt(vcpu);
10604 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10606 ktime_t remaining =
10607 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10610 if (ktime_to_ns(remaining) <= 0)
10613 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10614 do_div(value, 1000000);
10615 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10619 * Update the guest state fields of vmcs12 to reflect changes that
10620 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10621 * VM-entry controls is also updated, since this is really a guest
10624 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10626 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10627 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10629 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10630 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10631 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10633 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10634 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10635 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10636 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10637 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10638 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10639 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10640 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10641 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10642 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10643 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10644 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10645 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10646 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10647 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10648 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10649 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10650 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10651 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10652 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10653 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10654 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10655 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10656 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10657 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10658 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10659 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10660 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10661 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10662 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10663 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10664 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10665 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10666 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10667 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10668 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10670 vmcs12->guest_interruptibility_info =
10671 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10672 vmcs12->guest_pending_dbg_exceptions =
10673 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10674 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10675 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10677 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10679 if (nested_cpu_has_preemption_timer(vmcs12)) {
10680 if (vmcs12->vm_exit_controls &
10681 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10682 vmcs12->vmx_preemption_timer_value =
10683 vmx_get_preemption_timer_value(vcpu);
10684 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10688 * In some cases (usually, nested EPT), L2 is allowed to change its
10689 * own CR3 without exiting. If it has changed it, we must keep it.
10690 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10691 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10693 * Additionally, restore L2's PDPTR to vmcs12.
10696 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10697 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10698 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10699 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10700 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10703 if (nested_cpu_has_ept(vmcs12))
10704 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10706 if (nested_cpu_has_vid(vmcs12))
10707 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10709 vmcs12->vm_entry_controls =
10710 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10711 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10713 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10714 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10715 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10718 /* TODO: These cannot have changed unless we have MSR bitmaps and
10719 * the relevant bit asks not to trap the change */
10720 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10721 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10722 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10723 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10724 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10725 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10726 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10727 if (kvm_mpx_supported())
10728 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10729 if (nested_cpu_has_xsaves(vmcs12))
10730 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10734 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10735 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10736 * and this function updates it to reflect the changes to the guest state while
10737 * L2 was running (and perhaps made some exits which were handled directly by L0
10738 * without going back to L1), and to reflect the exit reason.
10739 * Note that we do not have to copy here all VMCS fields, just those that
10740 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10741 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10742 * which already writes to vmcs12 directly.
10744 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10745 u32 exit_reason, u32 exit_intr_info,
10746 unsigned long exit_qualification)
10748 /* update guest state fields: */
10749 sync_vmcs12(vcpu, vmcs12);
10751 /* update exit information fields: */
10753 vmcs12->vm_exit_reason = exit_reason;
10754 vmcs12->exit_qualification = exit_qualification;
10756 vmcs12->vm_exit_intr_info = exit_intr_info;
10757 if ((vmcs12->vm_exit_intr_info &
10758 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10759 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10760 vmcs12->vm_exit_intr_error_code =
10761 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10762 vmcs12->idt_vectoring_info_field = 0;
10763 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10764 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10766 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10767 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10768 * instead of reading the real value. */
10769 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10772 * Transfer the event that L0 or L1 may wanted to inject into
10773 * L2 to IDT_VECTORING_INFO_FIELD.
10775 vmcs12_save_pending_event(vcpu, vmcs12);
10779 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10780 * preserved above and would only end up incorrectly in L1.
10782 vcpu->arch.nmi_injected = false;
10783 kvm_clear_exception_queue(vcpu);
10784 kvm_clear_interrupt_queue(vcpu);
10788 * A part of what we need to when the nested L2 guest exits and we want to
10789 * run its L1 parent, is to reset L1's guest state to the host state specified
10791 * This function is to be called not only on normal nested exit, but also on
10792 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10793 * Failures During or After Loading Guest State").
10794 * This function should be called when the active VMCS is L1's (vmcs01).
10796 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10797 struct vmcs12 *vmcs12)
10799 struct kvm_segment seg;
10800 u32 entry_failure_code;
10802 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10803 vcpu->arch.efer = vmcs12->host_ia32_efer;
10804 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10805 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10807 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10808 vmx_set_efer(vcpu, vcpu->arch.efer);
10810 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10811 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10812 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10814 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10815 * actually changed, because vmx_set_cr0 refers to efer set above.
10817 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10818 * (KVM doesn't change it);
10820 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10821 vmx_set_cr0(vcpu, vmcs12->host_cr0);
10823 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
10824 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10825 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10827 nested_ept_uninit_mmu_context(vcpu);
10830 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10831 * couldn't have changed.
10833 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10834 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10837 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10841 * Trivially support vpid by letting L2s share their parent
10842 * L1's vpid. TODO: move to a more elaborate solution, giving
10843 * each L2 its own vpid and exposing the vpid feature to L1.
10845 vmx_flush_tlb(vcpu);
10849 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10850 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10851 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10852 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10853 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10855 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10856 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10857 vmcs_write64(GUEST_BNDCFGS, 0);
10859 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10860 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10861 vcpu->arch.pat = vmcs12->host_ia32_pat;
10863 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10864 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10865 vmcs12->host_ia32_perf_global_ctrl);
10867 /* Set L1 segment info according to Intel SDM
10868 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10869 seg = (struct kvm_segment) {
10871 .limit = 0xFFFFFFFF,
10872 .selector = vmcs12->host_cs_selector,
10878 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10882 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10883 seg = (struct kvm_segment) {
10885 .limit = 0xFFFFFFFF,
10892 seg.selector = vmcs12->host_ds_selector;
10893 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10894 seg.selector = vmcs12->host_es_selector;
10895 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10896 seg.selector = vmcs12->host_ss_selector;
10897 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10898 seg.selector = vmcs12->host_fs_selector;
10899 seg.base = vmcs12->host_fs_base;
10900 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10901 seg.selector = vmcs12->host_gs_selector;
10902 seg.base = vmcs12->host_gs_base;
10903 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10904 seg = (struct kvm_segment) {
10905 .base = vmcs12->host_tr_base,
10907 .selector = vmcs12->host_tr_selector,
10911 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10913 kvm_set_dr(vcpu, 7, 0x400);
10914 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10916 if (cpu_has_vmx_msr_bitmap())
10917 vmx_set_msr_bitmap(vcpu);
10919 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10920 vmcs12->vm_exit_msr_load_count))
10921 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10925 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10926 * and modify vmcs12 to make it see what it would expect to see there if
10927 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10929 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10930 u32 exit_intr_info,
10931 unsigned long exit_qualification)
10933 struct vcpu_vmx *vmx = to_vmx(vcpu);
10934 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10935 u32 vm_inst_error = 0;
10937 /* trying to cancel vmlaunch/vmresume is a bug */
10938 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10940 leave_guest_mode(vcpu);
10941 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10942 exit_qualification);
10944 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10945 vmcs12->vm_exit_msr_store_count))
10946 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10948 if (unlikely(vmx->fail))
10949 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
10951 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10953 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10954 && nested_exit_intr_ack_set(vcpu)) {
10955 int irq = kvm_cpu_get_interrupt(vcpu);
10957 vmcs12->vm_exit_intr_info = irq |
10958 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10961 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10962 vmcs12->exit_qualification,
10963 vmcs12->idt_vectoring_info_field,
10964 vmcs12->vm_exit_intr_info,
10965 vmcs12->vm_exit_intr_error_code,
10968 vm_entry_controls_reset_shadow(vmx);
10969 vm_exit_controls_reset_shadow(vmx);
10970 vmx_segment_cache_clear(vmx);
10972 /* if no vmcs02 cache requested, remove the one we used */
10973 if (VMCS02_POOL_SIZE == 0)
10974 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10976 load_vmcs12_host_state(vcpu, vmcs12);
10978 /* Update any VMCS fields that might have changed while L2 ran */
10979 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10980 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10981 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10982 if (vmx->hv_deadline_tsc == -1)
10983 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10984 PIN_BASED_VMX_PREEMPTION_TIMER);
10986 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10987 PIN_BASED_VMX_PREEMPTION_TIMER);
10988 if (kvm_has_tsc_control)
10989 decache_tsc_multiplier(vmx);
10991 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
10992 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
10993 vmx_set_virtual_x2apic_mode(vcpu,
10994 vcpu->arch.apic_base & X2APIC_ENABLE);
10995 } else if (!nested_cpu_has_ept(vmcs12) &&
10996 nested_cpu_has2(vmcs12,
10997 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10998 vmx_flush_tlb_ept_only(vcpu);
11001 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11004 /* Unpin physical memory we referred to in vmcs02 */
11005 if (vmx->nested.apic_access_page) {
11006 nested_release_page(vmx->nested.apic_access_page);
11007 vmx->nested.apic_access_page = NULL;
11009 if (vmx->nested.virtual_apic_page) {
11010 nested_release_page(vmx->nested.virtual_apic_page);
11011 vmx->nested.virtual_apic_page = NULL;
11013 if (vmx->nested.pi_desc_page) {
11014 kunmap(vmx->nested.pi_desc_page);
11015 nested_release_page(vmx->nested.pi_desc_page);
11016 vmx->nested.pi_desc_page = NULL;
11017 vmx->nested.pi_desc = NULL;
11021 * We are now running in L2, mmu_notifier will force to reload the
11022 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11024 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11027 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11028 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11029 * success or failure flag accordingly.
11031 if (unlikely(vmx->fail)) {
11033 nested_vmx_failValid(vcpu, vm_inst_error);
11035 nested_vmx_succeed(vcpu);
11036 if (enable_shadow_vmcs)
11037 vmx->nested.sync_shadow_vmcs = true;
11039 /* in case we halted in L2 */
11040 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11044 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11046 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11048 if (is_guest_mode(vcpu)) {
11049 to_vmx(vcpu)->nested.nested_run_pending = 0;
11050 nested_vmx_vmexit(vcpu, -1, 0, 0);
11052 free_nested(to_vmx(vcpu));
11056 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11057 * 23.7 "VM-entry failures during or after loading guest state" (this also
11058 * lists the acceptable exit-reason and exit-qualification parameters).
11059 * It should only be called before L2 actually succeeded to run, and when
11060 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11062 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11063 struct vmcs12 *vmcs12,
11064 u32 reason, unsigned long qualification)
11066 load_vmcs12_host_state(vcpu, vmcs12);
11067 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11068 vmcs12->exit_qualification = qualification;
11069 nested_vmx_succeed(vcpu);
11070 if (enable_shadow_vmcs)
11071 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11074 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11075 struct x86_instruction_info *info,
11076 enum x86_intercept_stage stage)
11078 return X86EMUL_CONTINUE;
11081 #ifdef CONFIG_X86_64
11082 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11083 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11084 u64 divisor, u64 *result)
11086 u64 low = a << shift, high = a >> (64 - shift);
11088 /* To avoid the overflow on divq */
11089 if (high >= divisor)
11092 /* Low hold the result, high hold rem which is discarded */
11093 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11094 "rm" (divisor), "0" (low), "1" (high));
11100 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11102 struct vcpu_vmx *vmx = to_vmx(vcpu);
11103 u64 tscl = rdtsc();
11104 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11105 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11107 /* Convert to host delta tsc if tsc scaling is enabled */
11108 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11109 u64_shl_div_u64(delta_tsc,
11110 kvm_tsc_scaling_ratio_frac_bits,
11111 vcpu->arch.tsc_scaling_ratio,
11116 * If the delta tsc can't fit in the 32 bit after the multi shift,
11117 * we can't use the preemption timer.
11118 * It's possible that it fits on later vmentries, but checking
11119 * on every vmentry is costly so we just use an hrtimer.
11121 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11124 vmx->hv_deadline_tsc = tscl + delta_tsc;
11125 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11126 PIN_BASED_VMX_PREEMPTION_TIMER);
11130 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11132 struct vcpu_vmx *vmx = to_vmx(vcpu);
11133 vmx->hv_deadline_tsc = -1;
11134 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11135 PIN_BASED_VMX_PREEMPTION_TIMER);
11139 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11142 shrink_ple_window(vcpu);
11145 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11146 struct kvm_memory_slot *slot)
11148 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11149 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11152 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11153 struct kvm_memory_slot *slot)
11155 kvm_mmu_slot_set_dirty(kvm, slot);
11158 static void vmx_flush_log_dirty(struct kvm *kvm)
11160 kvm_flush_pml_buffers(kvm);
11163 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11164 struct kvm_memory_slot *memslot,
11165 gfn_t offset, unsigned long mask)
11167 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11171 * This routine does the following things for vCPU which is going
11172 * to be blocked if VT-d PI is enabled.
11173 * - Store the vCPU to the wakeup list, so when interrupts happen
11174 * we can find the right vCPU to wake up.
11175 * - Change the Posted-interrupt descriptor as below:
11176 * 'NDST' <-- vcpu->pre_pcpu
11177 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11178 * - If 'ON' is set during this process, which means at least one
11179 * interrupt is posted for this vCPU, we cannot block it, in
11180 * this case, return 1, otherwise, return 0.
11183 static int pi_pre_block(struct kvm_vcpu *vcpu)
11185 unsigned long flags;
11187 struct pi_desc old, new;
11188 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11190 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11191 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11192 !kvm_vcpu_apicv_active(vcpu))
11195 vcpu->pre_pcpu = vcpu->cpu;
11196 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11197 vcpu->pre_pcpu), flags);
11198 list_add_tail(&vcpu->blocked_vcpu_list,
11199 &per_cpu(blocked_vcpu_on_cpu,
11201 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11202 vcpu->pre_pcpu), flags);
11205 old.control = new.control = pi_desc->control;
11208 * We should not block the vCPU if
11209 * an interrupt is posted for it.
11211 if (pi_test_on(pi_desc) == 1) {
11212 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11213 vcpu->pre_pcpu), flags);
11214 list_del(&vcpu->blocked_vcpu_list);
11215 spin_unlock_irqrestore(
11216 &per_cpu(blocked_vcpu_on_cpu_lock,
11217 vcpu->pre_pcpu), flags);
11218 vcpu->pre_pcpu = -1;
11223 WARN((pi_desc->sn == 1),
11224 "Warning: SN field of posted-interrupts "
11225 "is set before blocking\n");
11228 * Since vCPU can be preempted during this process,
11229 * vcpu->cpu could be different with pre_pcpu, we
11230 * need to set pre_pcpu as the destination of wakeup
11231 * notification event, then we can find the right vCPU
11232 * to wakeup in wakeup handler if interrupts happen
11233 * when the vCPU is in blocked state.
11235 dest = cpu_physical_id(vcpu->pre_pcpu);
11237 if (x2apic_enabled())
11240 new.ndst = (dest << 8) & 0xFF00;
11242 /* set 'NV' to 'wakeup vector' */
11243 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11244 } while (cmpxchg(&pi_desc->control, old.control,
11245 new.control) != old.control);
11250 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11252 if (pi_pre_block(vcpu))
11255 if (kvm_lapic_hv_timer_in_use(vcpu))
11256 kvm_lapic_switch_to_sw_timer(vcpu);
11261 static void pi_post_block(struct kvm_vcpu *vcpu)
11263 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11264 struct pi_desc old, new;
11266 unsigned long flags;
11268 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11269 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11270 !kvm_vcpu_apicv_active(vcpu))
11274 old.control = new.control = pi_desc->control;
11276 dest = cpu_physical_id(vcpu->cpu);
11278 if (x2apic_enabled())
11281 new.ndst = (dest << 8) & 0xFF00;
11283 /* Allow posting non-urgent interrupts */
11286 /* set 'NV' to 'notification vector' */
11287 new.nv = POSTED_INTR_VECTOR;
11288 } while (cmpxchg(&pi_desc->control, old.control,
11289 new.control) != old.control);
11291 if(vcpu->pre_pcpu != -1) {
11293 &per_cpu(blocked_vcpu_on_cpu_lock,
11294 vcpu->pre_pcpu), flags);
11295 list_del(&vcpu->blocked_vcpu_list);
11296 spin_unlock_irqrestore(
11297 &per_cpu(blocked_vcpu_on_cpu_lock,
11298 vcpu->pre_pcpu), flags);
11299 vcpu->pre_pcpu = -1;
11303 static void vmx_post_block(struct kvm_vcpu *vcpu)
11305 if (kvm_x86_ops->set_hv_timer)
11306 kvm_lapic_switch_to_hv_timer(vcpu);
11308 pi_post_block(vcpu);
11312 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11315 * @host_irq: host irq of the interrupt
11316 * @guest_irq: gsi of the interrupt
11317 * @set: set or unset PI
11318 * returns 0 on success, < 0 on failure
11320 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11321 uint32_t guest_irq, bool set)
11323 struct kvm_kernel_irq_routing_entry *e;
11324 struct kvm_irq_routing_table *irq_rt;
11325 struct kvm_lapic_irq irq;
11326 struct kvm_vcpu *vcpu;
11327 struct vcpu_data vcpu_info;
11328 int idx, ret = -EINVAL;
11330 if (!kvm_arch_has_assigned_device(kvm) ||
11331 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11332 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11335 idx = srcu_read_lock(&kvm->irq_srcu);
11336 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11337 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11339 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11340 if (e->type != KVM_IRQ_ROUTING_MSI)
11343 * VT-d PI cannot support posting multicast/broadcast
11344 * interrupts to a vCPU, we still use interrupt remapping
11345 * for these kind of interrupts.
11347 * For lowest-priority interrupts, we only support
11348 * those with single CPU as the destination, e.g. user
11349 * configures the interrupts via /proc/irq or uses
11350 * irqbalance to make the interrupts single-CPU.
11352 * We will support full lowest-priority interrupt later.
11355 kvm_set_msi_irq(kvm, e, &irq);
11356 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11358 * Make sure the IRTE is in remapped mode if
11359 * we don't handle it in posted mode.
11361 ret = irq_set_vcpu_affinity(host_irq, NULL);
11364 "failed to back to remapped mode, irq: %u\n",
11372 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11373 vcpu_info.vector = irq.vector;
11375 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11376 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11379 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11381 /* suppress notification event before unposting */
11382 pi_set_sn(vcpu_to_pi_desc(vcpu));
11383 ret = irq_set_vcpu_affinity(host_irq, NULL);
11384 pi_clear_sn(vcpu_to_pi_desc(vcpu));
11388 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11396 srcu_read_unlock(&kvm->irq_srcu, idx);
11400 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11402 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11403 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11404 FEATURE_CONTROL_LMCE;
11406 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11407 ~FEATURE_CONTROL_LMCE;
11410 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11411 .cpu_has_kvm_support = cpu_has_kvm_support,
11412 .disabled_by_bios = vmx_disabled_by_bios,
11413 .hardware_setup = hardware_setup,
11414 .hardware_unsetup = hardware_unsetup,
11415 .check_processor_compatibility = vmx_check_processor_compat,
11416 .hardware_enable = hardware_enable,
11417 .hardware_disable = hardware_disable,
11418 .cpu_has_accelerated_tpr = report_flexpriority,
11419 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11421 .vcpu_create = vmx_create_vcpu,
11422 .vcpu_free = vmx_free_vcpu,
11423 .vcpu_reset = vmx_vcpu_reset,
11425 .prepare_guest_switch = vmx_save_host_state,
11426 .vcpu_load = vmx_vcpu_load,
11427 .vcpu_put = vmx_vcpu_put,
11429 .update_bp_intercept = update_exception_bitmap,
11430 .get_msr = vmx_get_msr,
11431 .set_msr = vmx_set_msr,
11432 .get_segment_base = vmx_get_segment_base,
11433 .get_segment = vmx_get_segment,
11434 .set_segment = vmx_set_segment,
11435 .get_cpl = vmx_get_cpl,
11436 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11437 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11438 .decache_cr3 = vmx_decache_cr3,
11439 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11440 .set_cr0 = vmx_set_cr0,
11441 .set_cr3 = vmx_set_cr3,
11442 .set_cr4 = vmx_set_cr4,
11443 .set_efer = vmx_set_efer,
11444 .get_idt = vmx_get_idt,
11445 .set_idt = vmx_set_idt,
11446 .get_gdt = vmx_get_gdt,
11447 .set_gdt = vmx_set_gdt,
11448 .get_dr6 = vmx_get_dr6,
11449 .set_dr6 = vmx_set_dr6,
11450 .set_dr7 = vmx_set_dr7,
11451 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11452 .cache_reg = vmx_cache_reg,
11453 .get_rflags = vmx_get_rflags,
11454 .set_rflags = vmx_set_rflags,
11456 .get_pkru = vmx_get_pkru,
11458 .tlb_flush = vmx_flush_tlb,
11460 .run = vmx_vcpu_run,
11461 .handle_exit = vmx_handle_exit,
11462 .skip_emulated_instruction = skip_emulated_instruction,
11463 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11464 .get_interrupt_shadow = vmx_get_interrupt_shadow,
11465 .patch_hypercall = vmx_patch_hypercall,
11466 .set_irq = vmx_inject_irq,
11467 .set_nmi = vmx_inject_nmi,
11468 .queue_exception = vmx_queue_exception,
11469 .cancel_injection = vmx_cancel_injection,
11470 .interrupt_allowed = vmx_interrupt_allowed,
11471 .nmi_allowed = vmx_nmi_allowed,
11472 .get_nmi_mask = vmx_get_nmi_mask,
11473 .set_nmi_mask = vmx_set_nmi_mask,
11474 .enable_nmi_window = enable_nmi_window,
11475 .enable_irq_window = enable_irq_window,
11476 .update_cr8_intercept = update_cr8_intercept,
11477 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11478 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11479 .get_enable_apicv = vmx_get_enable_apicv,
11480 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11481 .load_eoi_exitmap = vmx_load_eoi_exitmap,
11482 .apicv_post_state_restore = vmx_apicv_post_state_restore,
11483 .hwapic_irr_update = vmx_hwapic_irr_update,
11484 .hwapic_isr_update = vmx_hwapic_isr_update,
11485 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11486 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11488 .set_tss_addr = vmx_set_tss_addr,
11489 .get_tdp_level = get_ept_level,
11490 .get_mt_mask = vmx_get_mt_mask,
11492 .get_exit_info = vmx_get_exit_info,
11494 .get_lpage_level = vmx_get_lpage_level,
11496 .cpuid_update = vmx_cpuid_update,
11498 .rdtscp_supported = vmx_rdtscp_supported,
11499 .invpcid_supported = vmx_invpcid_supported,
11501 .set_supported_cpuid = vmx_set_supported_cpuid,
11503 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11505 .write_tsc_offset = vmx_write_tsc_offset,
11507 .set_tdp_cr3 = vmx_set_cr3,
11509 .check_intercept = vmx_check_intercept,
11510 .handle_external_intr = vmx_handle_external_intr,
11511 .mpx_supported = vmx_mpx_supported,
11512 .xsaves_supported = vmx_xsaves_supported,
11514 .check_nested_events = vmx_check_nested_events,
11516 .sched_in = vmx_sched_in,
11518 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11519 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11520 .flush_log_dirty = vmx_flush_log_dirty,
11521 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11523 .pre_block = vmx_pre_block,
11524 .post_block = vmx_post_block,
11526 .pmu_ops = &intel_pmu_ops,
11528 .update_pi_irte = vmx_update_pi_irte,
11530 #ifdef CONFIG_X86_64
11531 .set_hv_timer = vmx_set_hv_timer,
11532 .cancel_hv_timer = vmx_cancel_hv_timer,
11535 .setup_mce = vmx_setup_mce,
11538 static int __init vmx_init(void)
11540 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11541 __alignof__(struct vcpu_vmx), THIS_MODULE);
11545 #ifdef CONFIG_KEXEC_CORE
11546 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11547 crash_vmclear_local_loaded_vmcss);
11553 static void __exit vmx_exit(void)
11555 #ifdef CONFIG_KEXEC_CORE
11556 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11563 module_init(vmx_init)
11564 module_exit(vmx_exit)