arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45 #include <asm/kexec.h>
  46
  47 #include "trace.h"
  48
  49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  50 #define __ex_clear(x, reg) \
  51         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  52
  53 MODULE_AUTHOR("Qumranet");
  54 MODULE_LICENSE("GPL");
  55
  56 static const struct x86_cpu_id vmx_cpu_id[] = {
  57         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  58         {}
  59 };
  60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  61
  62 static bool __read_mostly enable_vpid = 1;
  63 module_param_named(vpid, enable_vpid, bool, 0444);
  64
  65 static bool __read_mostly flexpriority_enabled = 1;
  66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  67
  68 static bool __read_mostly enable_ept = 1;
  69 module_param_named(ept, enable_ept, bool, S_IRUGO);
  70
  71 static bool __read_mostly enable_unrestricted_guest = 1;
  72 module_param_named(unrestricted_guest,
  73                         enable_unrestricted_guest, bool, S_IRUGO);
  74
  75 static bool __read_mostly enable_ept_ad_bits = 1;
  76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  77
  78 static bool __read_mostly emulate_invalid_guest_state = true;
  79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  80
  81 static bool __read_mostly vmm_exclusive = 1;
  82 module_param(vmm_exclusive, bool, S_IRUGO);
  83
  84 static bool __read_mostly fasteoi = 1;
  85 module_param(fasteoi, bool, S_IRUGO);
  86
  87 static bool __read_mostly enable_apicv = 1;
  88 module_param(enable_apicv, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_shadow_vmcs = 1;
  91 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  92 /*
  93  * If nested=1, nested virtualization is supported, i.e., guests may use
  94  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  95  * use VMX instructions.
  96  */
  97 static bool __read_mostly nested = 0;
  98 module_param(nested, bool, S_IRUGO);
  99
 100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 102 #define KVM_VM_CR0_ALWAYS_ON                                            \
 103         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 104 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 105         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 106          | X86_CR4_OSXMMEXCPT)
 107
 108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 110
 111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 112
 113 /*
 114  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 115  * ple_gap:    upper bound on the amount of time between two successive
 116  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 117  *             According to test, this time is usually smaller than 128 cycles.
 118  * ple_window: upper bound on the amount of time a guest is allowed to execute
 119  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 120  *             less than 2^12 cycles
 121  * Time is measured based on a counter that runs at the same rate as the TSC,
 122  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 123  */
 124 #define KVM_VMX_DEFAULT_PLE_GAP    128
 125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 126 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 127 module_param(ple_gap, int, S_IRUGO);
 128
 129 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 130 module_param(ple_window, int, S_IRUGO);
 131
 132 extern const ulong vmx_return;
 133
 134 #define NR_AUTOLOAD_MSRS 8
 135 #define VMCS02_POOL_SIZE 1
 136
 137 struct vmcs {
 138         u32 revision_id;
 139         u32 abort;
 140         char data[0];
 141 };
 142
 143 /*
 144  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 145  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 146  * loaded on this CPU (so we can clear them if the CPU goes down).
 147  */
 148 struct loaded_vmcs {
 149         struct vmcs *vmcs;
 150         int cpu;
 151         int launched;
 152         struct list_head loaded_vmcss_on_cpu_link;
 153 };
 154
 155 struct shared_msr_entry {
 156         unsigned index;
 157         u64 data;
 158         u64 mask;
 159 };
 160
 161 /*
 162  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 163  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 164  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 165  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 166  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 167  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 168  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 169  * underlying hardware which will be used to run L2.
 170  * This structure is packed to ensure that its layout is identical across
 171  * machines (necessary for live migration).
 172  * If there are changes in this struct, VMCS12_REVISION must be changed.
 173  */
 174 typedef u64 natural_width;
 175 struct __packed vmcs12 {
 176         /* According to the Intel spec, a VMCS region must start with the
 177          * following two fields. Then follow implementation-specific data.
 178          */
 179         u32 revision_id;
 180         u32 abort;
 181
 182         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 183         u32 padding[7]; /* room for future expansion */
 184
 185         u64 io_bitmap_a;
 186         u64 io_bitmap_b;
 187         u64 msr_bitmap;
 188         u64 vm_exit_msr_store_addr;
 189         u64 vm_exit_msr_load_addr;
 190         u64 vm_entry_msr_load_addr;
 191         u64 tsc_offset;
 192         u64 virtual_apic_page_addr;
 193         u64 apic_access_addr;
 194         u64 ept_pointer;
 195         u64 guest_physical_address;
 196         u64 vmcs_link_pointer;
 197         u64 guest_ia32_debugctl;
 198         u64 guest_ia32_pat;
 199         u64 guest_ia32_efer;
 200         u64 guest_ia32_perf_global_ctrl;
 201         u64 guest_pdptr0;
 202         u64 guest_pdptr1;
 203         u64 guest_pdptr2;
 204         u64 guest_pdptr3;
 205         u64 host_ia32_pat;
 206         u64 host_ia32_efer;
 207         u64 host_ia32_perf_global_ctrl;
 208         u64 padding64[8]; /* room for future expansion */
 209         /*
 210          * To allow migration of L1 (complete with its L2 guests) between
 211          * machines of different natural widths (32 or 64 bit), we cannot have
 212          * unsigned long fields with no explict size. We use u64 (aliased
 213          * natural_width) instead. Luckily, x86 is little-endian.
 214          */
 215         natural_width cr0_guest_host_mask;
 216         natural_width cr4_guest_host_mask;
 217         natural_width cr0_read_shadow;
 218         natural_width cr4_read_shadow;
 219         natural_width cr3_target_value0;
 220         natural_width cr3_target_value1;
 221         natural_width cr3_target_value2;
 222         natural_width cr3_target_value3;
 223         natural_width exit_qualification;
 224         natural_width guest_linear_address;
 225         natural_width guest_cr0;
 226         natural_width guest_cr3;
 227         natural_width guest_cr4;
 228         natural_width guest_es_base;
 229         natural_width guest_cs_base;
 230         natural_width guest_ss_base;
 231         natural_width guest_ds_base;
 232         natural_width guest_fs_base;
 233         natural_width guest_gs_base;
 234         natural_width guest_ldtr_base;
 235         natural_width guest_tr_base;
 236         natural_width guest_gdtr_base;
 237         natural_width guest_idtr_base;
 238         natural_width guest_dr7;
 239         natural_width guest_rsp;
 240         natural_width guest_rip;
 241         natural_width guest_rflags;
 242         natural_width guest_pending_dbg_exceptions;
 243         natural_width guest_sysenter_esp;
 244         natural_width guest_sysenter_eip;
 245         natural_width host_cr0;
 246         natural_width host_cr3;
 247         natural_width host_cr4;
 248         natural_width host_fs_base;
 249         natural_width host_gs_base;
 250         natural_width host_tr_base;
 251         natural_width host_gdtr_base;
 252         natural_width host_idtr_base;
 253         natural_width host_ia32_sysenter_esp;
 254         natural_width host_ia32_sysenter_eip;
 255         natural_width host_rsp;
 256         natural_width host_rip;
 257         natural_width paddingl[8]; /* room for future expansion */
 258         u32 pin_based_vm_exec_control;
 259         u32 cpu_based_vm_exec_control;
 260         u32 exception_bitmap;
 261         u32 page_fault_error_code_mask;
 262         u32 page_fault_error_code_match;
 263         u32 cr3_target_count;
 264         u32 vm_exit_controls;
 265         u32 vm_exit_msr_store_count;
 266         u32 vm_exit_msr_load_count;
 267         u32 vm_entry_controls;
 268         u32 vm_entry_msr_load_count;
 269         u32 vm_entry_intr_info_field;
 270         u32 vm_entry_exception_error_code;
 271         u32 vm_entry_instruction_len;
 272         u32 tpr_threshold;
 273         u32 secondary_vm_exec_control;
 274         u32 vm_instruction_error;
 275         u32 vm_exit_reason;
 276         u32 vm_exit_intr_info;
 277         u32 vm_exit_intr_error_code;
 278         u32 idt_vectoring_info_field;
 279         u32 idt_vectoring_error_code;
 280         u32 vm_exit_instruction_len;
 281         u32 vmx_instruction_info;
 282         u32 guest_es_limit;
 283         u32 guest_cs_limit;
 284         u32 guest_ss_limit;
 285         u32 guest_ds_limit;
 286         u32 guest_fs_limit;
 287         u32 guest_gs_limit;
 288         u32 guest_ldtr_limit;
 289         u32 guest_tr_limit;
 290         u32 guest_gdtr_limit;
 291         u32 guest_idtr_limit;
 292         u32 guest_es_ar_bytes;
 293         u32 guest_cs_ar_bytes;
 294         u32 guest_ss_ar_bytes;
 295         u32 guest_ds_ar_bytes;
 296         u32 guest_fs_ar_bytes;
 297         u32 guest_gs_ar_bytes;
 298         u32 guest_ldtr_ar_bytes;
 299         u32 guest_tr_ar_bytes;
 300         u32 guest_interruptibility_info;
 301         u32 guest_activity_state;
 302         u32 guest_sysenter_cs;
 303         u32 host_ia32_sysenter_cs;
 304         u32 vmx_preemption_timer_value;
 305         u32 padding32[7]; /* room for future expansion */
 306         u16 virtual_processor_id;
 307         u16 guest_es_selector;
 308         u16 guest_cs_selector;
 309         u16 guest_ss_selector;
 310         u16 guest_ds_selector;
 311         u16 guest_fs_selector;
 312         u16 guest_gs_selector;
 313         u16 guest_ldtr_selector;
 314         u16 guest_tr_selector;
 315         u16 host_es_selector;
 316         u16 host_cs_selector;
 317         u16 host_ss_selector;
 318         u16 host_ds_selector;
 319         u16 host_fs_selector;
 320         u16 host_gs_selector;
 321         u16 host_tr_selector;
 322 };
 323
 324 /*
 325  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 326  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 327  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 328  */
 329 #define VMCS12_REVISION 0x11e57ed0
 330
 331 /*
 332  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 333  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 334  * current implementation, 4K are reserved to avoid future complications.
 335  */
 336 #define VMCS12_SIZE 0x1000
 337
 338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 339 struct vmcs02_list {
 340         struct list_head list;
 341         gpa_t vmptr;
 342         struct loaded_vmcs vmcs02;
 343 };
 344
 345 /*
 346  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 347  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 348  */
 349 struct nested_vmx {
 350         /* Has the level1 guest done vmxon? */
 351         bool vmxon;
 352
 353         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 354         gpa_t current_vmptr;
 355         /* The host-usable pointer to the above */
 356         struct page *current_vmcs12_page;
 357         struct vmcs12 *current_vmcs12;
 358         struct vmcs *current_shadow_vmcs;
 359         /*
 360          * Indicates if the shadow vmcs must be updated with the
 361          * data hold by vmcs12
 362          */
 363         bool sync_shadow_vmcs;
 364
 365         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 366         struct list_head vmcs02_pool;
 367         int vmcs02_num;
 368         u64 vmcs01_tsc_offset;
 369         /* L2 must run next, and mustn't decide to exit to L1. */
 370         bool nested_run_pending;
 371         /*
 372          * Guest pages referred to in vmcs02 with host-physical pointers, so
 373          * we must keep them pinned while L2 runs.
 374          */
 375         struct page *apic_access_page;
 376         u64 msr_ia32_feature_control;
 377 };
 378
 379 #define POSTED_INTR_ON  0
 380 /* Posted-Interrupt Descriptor */
 381 struct pi_desc {
 382         u32 pir[8];     /* Posted interrupt requested */
 383         u32 control;    /* bit 0 of control is outstanding notification bit */
 384         u32 rsvd[7];
 385 } __aligned(64);
 386
 387 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 388 {
 389         return test_and_set_bit(POSTED_INTR_ON,
 390                         (unsigned long *)&pi_desc->control);
 391 }
 392
 393 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 394 {
 395         return test_and_clear_bit(POSTED_INTR_ON,
 396                         (unsigned long *)&pi_desc->control);
 397 }
 398
 399 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 400 {
 401         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 402 }
 403
 404 struct vcpu_vmx {
 405         struct kvm_vcpu       vcpu;
 406         unsigned long         host_rsp;
 407         u8                    fail;
 408         u8                    cpl;
 409         bool                  nmi_known_unmasked;
 410         u32                   exit_intr_info;
 411         u32                   idt_vectoring_info;
 412         ulong                 rflags;
 413         struct shared_msr_entry *guest_msrs;
 414         int                   nmsrs;
 415         int                   save_nmsrs;
 416         unsigned long         host_idt_base;
 417 #ifdef CONFIG_X86_64
 418         u64                   msr_host_kernel_gs_base;
 419         u64                   msr_guest_kernel_gs_base;
 420 #endif
 421         u32 vm_entry_controls_shadow;
 422         u32 vm_exit_controls_shadow;
 423         /*
 424          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 425          * non-nested (L1) guest, it always points to vmcs01. For a nested
 426          * guest (L2), it points to a different VMCS.
 427          */
 428         struct loaded_vmcs    vmcs01;
 429         struct loaded_vmcs   *loaded_vmcs;
 430         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 431         struct msr_autoload {
 432                 unsigned nr;
 433                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 434                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 435         } msr_autoload;
 436         struct {
 437                 int           loaded;
 438                 u16           fs_sel, gs_sel, ldt_sel;
 439 #ifdef CONFIG_X86_64
 440                 u16           ds_sel, es_sel;
 441 #endif
 442                 int           gs_ldt_reload_needed;
 443                 int           fs_reload_needed;
 444         } host_state;
 445         struct {
 446                 int vm86_active;
 447                 ulong save_rflags;
 448                 struct kvm_segment segs[8];
 449         } rmode;
 450         struct {
 451                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 452                 struct kvm_save_segment {
 453                         u16 selector;
 454                         unsigned long base;
 455                         u32 limit;
 456                         u32 ar;
 457                 } seg[8];
 458         } segment_cache;
 459         int vpid;
 460         bool emulation_required;
 461
 462         /* Support for vnmi-less CPUs */
 463         int soft_vnmi_blocked;
 464         ktime_t entry_time;
 465         s64 vnmi_blocked_time;
 466         u32 exit_reason;
 467
 468         bool rdtscp_enabled;
 469
 470         /* Posted interrupt descriptor */
 471         struct pi_desc pi_desc;
 472
 473         /* Support for a guest hypervisor (nested VMX) */
 474         struct nested_vmx nested;
 475 };
 476
 477 enum segment_cache_field {
 478         SEG_FIELD_SEL = 0,
 479         SEG_FIELD_BASE = 1,
 480         SEG_FIELD_LIMIT = 2,
 481         SEG_FIELD_AR = 3,
 482
 483         SEG_FIELD_NR = 4
 484 };
 485
 486 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 487 {
 488         return container_of(vcpu, struct vcpu_vmx, vcpu);
 489 }
 490
 491 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 492 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 493 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 494                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 495
 496
 497 static const unsigned long shadow_read_only_fields[] = {
 498         /*
 499          * We do NOT shadow fields that are modified when L0
 500          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 501          * VMXON...) executed by L1.
 502          * For example, VM_INSTRUCTION_ERROR is read
 503          * by L1 if a vmx instruction fails (part of the error path).
 504          * Note the code assumes this logic. If for some reason
 505          * we start shadowing these fields then we need to
 506          * force a shadow sync when L0 emulates vmx instructions
 507          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 508          * by nested_vmx_failValid)
 509          */
 510         VM_EXIT_REASON,
 511         VM_EXIT_INTR_INFO,
 512         VM_EXIT_INSTRUCTION_LEN,
 513         IDT_VECTORING_INFO_FIELD,
 514         IDT_VECTORING_ERROR_CODE,
 515         VM_EXIT_INTR_ERROR_CODE,
 516         EXIT_QUALIFICATION,
 517         GUEST_LINEAR_ADDRESS,
 518         GUEST_PHYSICAL_ADDRESS
 519 };
 520 static const int max_shadow_read_only_fields =
 521         ARRAY_SIZE(shadow_read_only_fields);
 522
 523 static const unsigned long shadow_read_write_fields[] = {
 524         GUEST_RIP,
 525         GUEST_RSP,
 526         GUEST_CR0,
 527         GUEST_CR3,
 528         GUEST_CR4,
 529         GUEST_INTERRUPTIBILITY_INFO,
 530         GUEST_RFLAGS,
 531         GUEST_CS_SELECTOR,
 532         GUEST_CS_AR_BYTES,
 533         GUEST_CS_LIMIT,
 534         GUEST_CS_BASE,
 535         GUEST_ES_BASE,
 536         CR0_GUEST_HOST_MASK,
 537         CR0_READ_SHADOW,
 538         CR4_READ_SHADOW,
 539         TSC_OFFSET,
 540         EXCEPTION_BITMAP,
 541         CPU_BASED_VM_EXEC_CONTROL,
 542         VM_ENTRY_EXCEPTION_ERROR_CODE,
 543         VM_ENTRY_INTR_INFO_FIELD,
 544         VM_ENTRY_INSTRUCTION_LEN,
 545         VM_ENTRY_EXCEPTION_ERROR_CODE,
 546         HOST_FS_BASE,
 547         HOST_GS_BASE,
 548         HOST_FS_SELECTOR,
 549         HOST_GS_SELECTOR
 550 };
 551 static const int max_shadow_read_write_fields =
 552         ARRAY_SIZE(shadow_read_write_fields);
 553
 554 static const unsigned short vmcs_field_to_offset_table[] = {
 555         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 556         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 557         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 558         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 559         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 560         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 561         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 562         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 563         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 564         FIELD(HOST_ES_SELECTOR, host_es_selector),
 565         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 566         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 567         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 568         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 569         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 570         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 571         FIELD64(IO_BITMAP_A, io_bitmap_a),
 572         FIELD64(IO_BITMAP_B, io_bitmap_b),
 573         FIELD64(MSR_BITMAP, msr_bitmap),
 574         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 575         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 576         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 577         FIELD64(TSC_OFFSET, tsc_offset),
 578         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 579         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 580         FIELD64(EPT_POINTER, ept_pointer),
 581         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 582         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 583         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 584         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 585         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 586         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 587         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 588         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 589         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 590         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 591         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 592         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 593         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 594         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 595         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 596         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 597         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 598         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 599         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 600         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 601         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 602         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 603         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 604         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 605         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 606         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 607         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 608         FIELD(TPR_THRESHOLD, tpr_threshold),
 609         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 610         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 611         FIELD(VM_EXIT_REASON, vm_exit_reason),
 612         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 613         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 614         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 615         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 616         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 617         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 618         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 619         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 620         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 621         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 622         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 623         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 624         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 625         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 626         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 627         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 628         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 629         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 630         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 631         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 632         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 633         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 634         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 635         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 636         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 637         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 638         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 639         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 640         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 641         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 642         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 643         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 644         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 645         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 646         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 647         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 648         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 649         FIELD(EXIT_QUALIFICATION, exit_qualification),
 650         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 651         FIELD(GUEST_CR0, guest_cr0),
 652         FIELD(GUEST_CR3, guest_cr3),
 653         FIELD(GUEST_CR4, guest_cr4),
 654         FIELD(GUEST_ES_BASE, guest_es_base),
 655         FIELD(GUEST_CS_BASE, guest_cs_base),
 656         FIELD(GUEST_SS_BASE, guest_ss_base),
 657         FIELD(GUEST_DS_BASE, guest_ds_base),
 658         FIELD(GUEST_FS_BASE, guest_fs_base),
 659         FIELD(GUEST_GS_BASE, guest_gs_base),
 660         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 661         FIELD(GUEST_TR_BASE, guest_tr_base),
 662         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 663         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 664         FIELD(GUEST_DR7, guest_dr7),
 665         FIELD(GUEST_RSP, guest_rsp),
 666         FIELD(GUEST_RIP, guest_rip),
 667         FIELD(GUEST_RFLAGS, guest_rflags),
 668         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 669         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 670         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 671         FIELD(HOST_CR0, host_cr0),
 672         FIELD(HOST_CR3, host_cr3),
 673         FIELD(HOST_CR4, host_cr4),
 674         FIELD(HOST_FS_BASE, host_fs_base),
 675         FIELD(HOST_GS_BASE, host_gs_base),
 676         FIELD(HOST_TR_BASE, host_tr_base),
 677         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 678         FIELD(HOST_IDTR_BASE, host_idtr_base),
 679         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 680         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 681         FIELD(HOST_RSP, host_rsp),
 682         FIELD(HOST_RIP, host_rip),
 683 };
 684 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 685
 686 static inline short vmcs_field_to_offset(unsigned long field)
 687 {
 688         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 689                 return -1;
 690         return vmcs_field_to_offset_table[field];
 691 }
 692
 693 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 694 {
 695         return to_vmx(vcpu)->nested.current_vmcs12;
 696 }
 697
 698 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 699 {
 700         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 701         if (is_error_page(page))
 702                 return NULL;
 703
 704         return page;
 705 }
 706
 707 static void nested_release_page(struct page *page)
 708 {
 709         kvm_release_page_dirty(page);
 710 }
 711
 712 static void nested_release_page_clean(struct page *page)
 713 {
 714         kvm_release_page_clean(page);
 715 }
 716
 717 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 718 static u64 construct_eptp(unsigned long root_hpa);
 719 static void kvm_cpu_vmxon(u64 addr);
 720 static void kvm_cpu_vmxoff(void);
 721 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 722 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 723                             struct kvm_segment *var, int seg);
 724 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 725                             struct kvm_segment *var, int seg);
 726 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 727 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 728 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 729 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 730 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 731
 732 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 733 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 734 /*
 735  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 736  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 737  */
 738 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 739 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 740
 741 static unsigned long *vmx_io_bitmap_a;
 742 static unsigned long *vmx_io_bitmap_b;
 743 static unsigned long *vmx_msr_bitmap_legacy;
 744 static unsigned long *vmx_msr_bitmap_longmode;
 745 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 746 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 747 static unsigned long *vmx_vmread_bitmap;
 748 static unsigned long *vmx_vmwrite_bitmap;
 749
 750 static bool cpu_has_load_ia32_efer;
 751 static bool cpu_has_load_perf_global_ctrl;
 752
 753 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 754 static DEFINE_SPINLOCK(vmx_vpid_lock);
 755
 756 static struct vmcs_config {
 757         int size;
 758         int order;
 759         u32 revision_id;
 760         u32 pin_based_exec_ctrl;
 761         u32 cpu_based_exec_ctrl;
 762         u32 cpu_based_2nd_exec_ctrl;
 763         u32 vmexit_ctrl;
 764         u32 vmentry_ctrl;
 765 } vmcs_config;
 766
 767 static struct vmx_capability {
 768         u32 ept;
 769         u32 vpid;
 770 } vmx_capability;
 771
 772 #define VMX_SEGMENT_FIELD(seg)                                  \
 773         [VCPU_SREG_##seg] = {                                   \
 774                 .selector = GUEST_##seg##_SELECTOR,             \
 775                 .base = GUEST_##seg##_BASE,                     \
 776                 .limit = GUEST_##seg##_LIMIT,                   \
 777                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 778         }
 779
 780 static const struct kvm_vmx_segment_field {
 781         unsigned selector;
 782         unsigned base;
 783         unsigned limit;
 784         unsigned ar_bytes;
 785 } kvm_vmx_segment_fields[] = {
 786         VMX_SEGMENT_FIELD(CS),
 787         VMX_SEGMENT_FIELD(DS),
 788         VMX_SEGMENT_FIELD(ES),
 789         VMX_SEGMENT_FIELD(FS),
 790         VMX_SEGMENT_FIELD(GS),
 791         VMX_SEGMENT_FIELD(SS),
 792         VMX_SEGMENT_FIELD(TR),
 793         VMX_SEGMENT_FIELD(LDTR),
 794 };
 795
 796 static u64 host_efer;
 797
 798 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 799
 800 /*
 801  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 802  * away by decrementing the array size.
 803  */
 804 static const u32 vmx_msr_index[] = {
 805 #ifdef CONFIG_X86_64
 806         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 807 #endif
 808         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 809 };
 810 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 811
 812 static inline bool is_page_fault(u32 intr_info)
 813 {
 814         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 815                              INTR_INFO_VALID_MASK)) ==
 816                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 817 }
 818
 819 static inline bool is_no_device(u32 intr_info)
 820 {
 821         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 822                              INTR_INFO_VALID_MASK)) ==
 823                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 824 }
 825
 826 static inline bool is_invalid_opcode(u32 intr_info)
 827 {
 828         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 829                              INTR_INFO_VALID_MASK)) ==
 830                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 831 }
 832
 833 static inline bool is_external_interrupt(u32 intr_info)
 834 {
 835         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 836                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 837 }
 838
 839 static inline bool is_machine_check(u32 intr_info)
 840 {
 841         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 842                              INTR_INFO_VALID_MASK)) ==
 843                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 844 }
 845
 846 static inline bool cpu_has_vmx_msr_bitmap(void)
 847 {
 848         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 849 }
 850
 851 static inline bool cpu_has_vmx_tpr_shadow(void)
 852 {
 853         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 854 }
 855
 856 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 857 {
 858         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 859 }
 860
 861 static inline bool cpu_has_secondary_exec_ctrls(void)
 862 {
 863         return vmcs_config.cpu_based_exec_ctrl &
 864                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 865 }
 866
 867 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 868 {
 869         return vmcs_config.cpu_based_2nd_exec_ctrl &
 870                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 871 }
 872
 873 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 874 {
 875         return vmcs_config.cpu_based_2nd_exec_ctrl &
 876                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 877 }
 878
 879 static inline bool cpu_has_vmx_apic_register_virt(void)
 880 {
 881         return vmcs_config.cpu_based_2nd_exec_ctrl &
 882                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 883 }
 884
 885 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 886 {
 887         return vmcs_config.cpu_based_2nd_exec_ctrl &
 888                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 889 }
 890
 891 static inline bool cpu_has_vmx_posted_intr(void)
 892 {
 893         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 894 }
 895
 896 static inline bool cpu_has_vmx_apicv(void)
 897 {
 898         return cpu_has_vmx_apic_register_virt() &&
 899                 cpu_has_vmx_virtual_intr_delivery() &&
 900                 cpu_has_vmx_posted_intr();
 901 }
 902
 903 static inline bool cpu_has_vmx_flexpriority(void)
 904 {
 905         return cpu_has_vmx_tpr_shadow() &&
 906                 cpu_has_vmx_virtualize_apic_accesses();
 907 }
 908
 909 static inline bool cpu_has_vmx_ept_execute_only(void)
 910 {
 911         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 912 }
 913
 914 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 915 {
 916         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 917 }
 918
 919 static inline bool cpu_has_vmx_eptp_writeback(void)
 920 {
 921         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 922 }
 923
 924 static inline bool cpu_has_vmx_ept_2m_page(void)
 925 {
 926         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 927 }
 928
 929 static inline bool cpu_has_vmx_ept_1g_page(void)
 930 {
 931         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 932 }
 933
 934 static inline bool cpu_has_vmx_ept_4levels(void)
 935 {
 936         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 937 }
 938
 939 static inline bool cpu_has_vmx_ept_ad_bits(void)
 940 {
 941         return vmx_capability.ept & VMX_EPT_AD_BIT;
 942 }
 943
 944 static inline bool cpu_has_vmx_invept_context(void)
 945 {
 946         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 947 }
 948
 949 static inline bool cpu_has_vmx_invept_global(void)
 950 {
 951         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 952 }
 953
 954 static inline bool cpu_has_vmx_invvpid_single(void)
 955 {
 956         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 957 }
 958
 959 static inline bool cpu_has_vmx_invvpid_global(void)
 960 {
 961         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 962 }
 963
 964 static inline bool cpu_has_vmx_ept(void)
 965 {
 966         return vmcs_config.cpu_based_2nd_exec_ctrl &
 967                 SECONDARY_EXEC_ENABLE_EPT;
 968 }
 969
 970 static inline bool cpu_has_vmx_unrestricted_guest(void)
 971 {
 972         return vmcs_config.cpu_based_2nd_exec_ctrl &
 973                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 974 }
 975
 976 static inline bool cpu_has_vmx_ple(void)
 977 {
 978         return vmcs_config.cpu_based_2nd_exec_ctrl &
 979                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 980 }
 981
 982 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 983 {
 984         return flexpriority_enabled && irqchip_in_kernel(kvm);
 985 }
 986
 987 static inline bool cpu_has_vmx_vpid(void)
 988 {
 989         return vmcs_config.cpu_based_2nd_exec_ctrl &
 990                 SECONDARY_EXEC_ENABLE_VPID;
 991 }
 992
 993 static inline bool cpu_has_vmx_rdtscp(void)
 994 {
 995         return vmcs_config.cpu_based_2nd_exec_ctrl &
 996                 SECONDARY_EXEC_RDTSCP;
 997 }
 998
 999 static inline bool cpu_has_vmx_invpcid(void)
1000 {
1001         return vmcs_config.cpu_based_2nd_exec_ctrl &
1002                 SECONDARY_EXEC_ENABLE_INVPCID;
1003 }
1004
1005 static inline bool cpu_has_virtual_nmis(void)
1006 {
1007         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1008 }
1009
1010 static inline bool cpu_has_vmx_wbinvd_exit(void)
1011 {
1012         return vmcs_config.cpu_based_2nd_exec_ctrl &
1013                 SECONDARY_EXEC_WBINVD_EXITING;
1014 }
1015
1016 static inline bool cpu_has_vmx_shadow_vmcs(void)
1017 {
1018         u64 vmx_msr;
1019         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1020         /* check if the cpu supports writing r/o exit information fields */
1021         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1022                 return false;
1023
1024         return vmcs_config.cpu_based_2nd_exec_ctrl &
1025                 SECONDARY_EXEC_SHADOW_VMCS;
1026 }
1027
1028 static inline bool report_flexpriority(void)
1029 {
1030         return flexpriority_enabled;
1031 }
1032
1033 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1034 {
1035         return vmcs12->cpu_based_vm_exec_control & bit;
1036 }
1037
1038 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1039 {
1040         return (vmcs12->cpu_based_vm_exec_control &
1041                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1042                 (vmcs12->secondary_vm_exec_control & bit);
1043 }
1044
1045 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1046 {
1047         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1048 }
1049
1050 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1051 {
1052         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1053 }
1054
1055 static inline bool is_exception(u32 intr_info)
1056 {
1057         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1058                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1059 }
1060
1061 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1062                               u32 exit_intr_info,
1063                               unsigned long exit_qualification);
1064 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1065                         struct vmcs12 *vmcs12,
1066                         u32 reason, unsigned long qualification);
1067
1068 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1069 {
1070         int i;
1071
1072         for (i = 0; i < vmx->nmsrs; ++i)
1073                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1074                         return i;
1075         return -1;
1076 }
1077
1078 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1079 {
1080     struct {
1081         u64 vpid : 16;
1082         u64 rsvd : 48;
1083         u64 gva;
1084     } operand = { vpid, 0, gva };
1085
1086     asm volatile (__ex(ASM_VMX_INVVPID)
1087                   /* CF==1 or ZF==1 --> rc = -1 */
1088                   "; ja 1f ; ud2 ; 1:"
1089                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1090 }
1091
1092 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1093 {
1094         struct {
1095                 u64 eptp, gpa;
1096         } operand = {eptp, gpa};
1097
1098         asm volatile (__ex(ASM_VMX_INVEPT)
1099                         /* CF==1 or ZF==1 --> rc = -1 */
1100                         "; ja 1f ; ud2 ; 1:\n"
1101                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1102 }
1103
1104 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1105 {
1106         int i;
1107
1108         i = __find_msr_index(vmx, msr);
1109         if (i >= 0)
1110                 return &vmx->guest_msrs[i];
1111         return NULL;
1112 }
1113
1114 static void vmcs_clear(struct vmcs *vmcs)
1115 {
1116         u64 phys_addr = __pa(vmcs);
1117         u8 error;
1118
1119         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1120                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1121                       : "cc", "memory");
1122         if (error)
1123                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1124                        vmcs, phys_addr);
1125 }
1126
1127 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1128 {
1129         vmcs_clear(loaded_vmcs->vmcs);
1130         loaded_vmcs->cpu = -1;
1131         loaded_vmcs->launched = 0;
1132 }
1133
1134 static void vmcs_load(struct vmcs *vmcs)
1135 {
1136         u64 phys_addr = __pa(vmcs);
1137         u8 error;
1138
1139         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1140                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1141                         : "cc", "memory");
1142         if (error)
1143                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1144                        vmcs, phys_addr);
1145 }
1146
1147 #ifdef CONFIG_KEXEC
1148 /*
1149  * This bitmap is used to indicate whether the vmclear
1150  * operation is enabled on all cpus. All disabled by
1151  * default.
1152  */
1153 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1154
1155 static inline void crash_enable_local_vmclear(int cpu)
1156 {
1157         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1158 }
1159
1160 static inline void crash_disable_local_vmclear(int cpu)
1161 {
1162         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1163 }
1164
1165 static inline int crash_local_vmclear_enabled(int cpu)
1166 {
1167         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1168 }
1169
1170 static void crash_vmclear_local_loaded_vmcss(void)
1171 {
1172         int cpu = raw_smp_processor_id();
1173         struct loaded_vmcs *v;
1174
1175         if (!crash_local_vmclear_enabled(cpu))
1176                 return;
1177
1178         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1179                             loaded_vmcss_on_cpu_link)
1180                 vmcs_clear(v->vmcs);
1181 }
1182 #else
1183 static inline void crash_enable_local_vmclear(int cpu) { }
1184 static inline void crash_disable_local_vmclear(int cpu) { }
1185 #endif /* CONFIG_KEXEC */
1186
1187 static void __loaded_vmcs_clear(void *arg)
1188 {
1189         struct loaded_vmcs *loaded_vmcs = arg;
1190         int cpu = raw_smp_processor_id();
1191
1192         if (loaded_vmcs->cpu != cpu)
1193                 return; /* vcpu migration can race with cpu offline */
1194         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1195                 per_cpu(current_vmcs, cpu) = NULL;
1196         crash_disable_local_vmclear(cpu);
1197         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1198
1199         /*
1200          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1201          * is before setting loaded_vmcs->vcpu to -1 which is done in
1202          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1203          * then adds the vmcs into percpu list before it is deleted.
1204          */
1205         smp_wmb();
1206
1207         loaded_vmcs_init(loaded_vmcs);
1208         crash_enable_local_vmclear(cpu);
1209 }
1210
1211 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1212 {
1213         int cpu = loaded_vmcs->cpu;
1214
1215         if (cpu != -1)
1216                 smp_call_function_single(cpu,
1217                          __loaded_vmcs_clear, loaded_vmcs, 1);
1218 }
1219
1220 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1221 {
1222         if (vmx->vpid == 0)
1223                 return;
1224
1225         if (cpu_has_vmx_invvpid_single())
1226                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1227 }
1228
1229 static inline void vpid_sync_vcpu_global(void)
1230 {
1231         if (cpu_has_vmx_invvpid_global())
1232                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1233 }
1234
1235 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1236 {
1237         if (cpu_has_vmx_invvpid_single())
1238                 vpid_sync_vcpu_single(vmx);
1239         else
1240                 vpid_sync_vcpu_global();
1241 }
1242
1243 static inline void ept_sync_global(void)
1244 {
1245         if (cpu_has_vmx_invept_global())
1246                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1247 }
1248
1249 static inline void ept_sync_context(u64 eptp)
1250 {
1251         if (enable_ept) {
1252                 if (cpu_has_vmx_invept_context())
1253                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1254                 else
1255                         ept_sync_global();
1256         }
1257 }
1258
1259 static __always_inline unsigned long vmcs_readl(unsigned long field)
1260 {
1261         unsigned long value;
1262
1263         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1264                       : "=a"(value) : "d"(field) : "cc");
1265         return value;
1266 }
1267
1268 static __always_inline u16 vmcs_read16(unsigned long field)
1269 {
1270         return vmcs_readl(field);
1271 }
1272
1273 static __always_inline u32 vmcs_read32(unsigned long field)
1274 {
1275         return vmcs_readl(field);
1276 }
1277
1278 static __always_inline u64 vmcs_read64(unsigned long field)
1279 {
1280 #ifdef CONFIG_X86_64
1281         return vmcs_readl(field);
1282 #else
1283         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1284 #endif
1285 }
1286
1287 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1288 {
1289         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1290                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1291         dump_stack();
1292 }
1293
1294 static void vmcs_writel(unsigned long field, unsigned long value)
1295 {
1296         u8 error;
1297
1298         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1299                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1300         if (unlikely(error))
1301                 vmwrite_error(field, value);
1302 }
1303
1304 static void vmcs_write16(unsigned long field, u16 value)
1305 {
1306         vmcs_writel(field, value);
1307 }
1308
1309 static void vmcs_write32(unsigned long field, u32 value)
1310 {
1311         vmcs_writel(field, value);
1312 }
1313
1314 static void vmcs_write64(unsigned long field, u64 value)
1315 {
1316         vmcs_writel(field, value);
1317 #ifndef CONFIG_X86_64
1318         asm volatile ("");
1319         vmcs_writel(field+1, value >> 32);
1320 #endif
1321 }
1322
1323 static void vmcs_clear_bits(unsigned long field, u32 mask)
1324 {
1325         vmcs_writel(field, vmcs_readl(field) & ~mask);
1326 }
1327
1328 static void vmcs_set_bits(unsigned long field, u32 mask)
1329 {
1330         vmcs_writel(field, vmcs_readl(field) | mask);
1331 }
1332
1333 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1334 {
1335         vmcs_write32(VM_ENTRY_CONTROLS, val);
1336         vmx->vm_entry_controls_shadow = val;
1337 }
1338
1339 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1340 {
1341         if (vmx->vm_entry_controls_shadow != val)
1342                 vm_entry_controls_init(vmx, val);
1343 }
1344
1345 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1346 {
1347         return vmx->vm_entry_controls_shadow;
1348 }
1349
1350
1351 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1352 {
1353         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1354 }
1355
1356 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1357 {
1358         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1359 }
1360
1361 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1362 {
1363         vmcs_write32(VM_EXIT_CONTROLS, val);
1364         vmx->vm_exit_controls_shadow = val;
1365 }
1366
1367 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1368 {
1369         if (vmx->vm_exit_controls_shadow != val)
1370                 vm_exit_controls_init(vmx, val);
1371 }
1372
1373 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1374 {
1375         return vmx->vm_exit_controls_shadow;
1376 }
1377
1378
1379 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1380 {
1381         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1382 }
1383
1384 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1385 {
1386         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1387 }
1388
1389 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1390 {
1391         vmx->segment_cache.bitmask = 0;
1392 }
1393
1394 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1395                                        unsigned field)
1396 {
1397         bool ret;
1398         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1399
1400         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1401                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1402                 vmx->segment_cache.bitmask = 0;
1403         }
1404         ret = vmx->segment_cache.bitmask & mask;
1405         vmx->segment_cache.bitmask |= mask;
1406         return ret;
1407 }
1408
1409 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1410 {
1411         u16 *p = &vmx->segment_cache.seg[seg].selector;
1412
1413         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1414                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1415         return *p;
1416 }
1417
1418 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1419 {
1420         ulong *p = &vmx->segment_cache.seg[seg].base;
1421
1422         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1423                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1424         return *p;
1425 }
1426
1427 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1428 {
1429         u32 *p = &vmx->segment_cache.seg[seg].limit;
1430
1431         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1432                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1433         return *p;
1434 }
1435
1436 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1437 {
1438         u32 *p = &vmx->segment_cache.seg[seg].ar;
1439
1440         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1441                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1442         return *p;
1443 }
1444
1445 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1446 {
1447         u32 eb;
1448
1449         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1450              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1451         if ((vcpu->guest_debug &
1452              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1453             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1454                 eb |= 1u << BP_VECTOR;
1455         if (to_vmx(vcpu)->rmode.vm86_active)
1456                 eb = ~0;
1457         if (enable_ept)
1458                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1459         if (vcpu->fpu_active)
1460                 eb &= ~(1u << NM_VECTOR);
1461
1462         /* When we are running a nested L2 guest and L1 specified for it a
1463          * certain exception bitmap, we must trap the same exceptions and pass
1464          * them to L1. When running L2, we will only handle the exceptions
1465          * specified above if L1 did not want them.
1466          */
1467         if (is_guest_mode(vcpu))
1468                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1469
1470         vmcs_write32(EXCEPTION_BITMAP, eb);
1471 }
1472
1473 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1474                 unsigned long entry, unsigned long exit)
1475 {
1476         vm_entry_controls_clearbit(vmx, entry);
1477         vm_exit_controls_clearbit(vmx, exit);
1478 }
1479
1480 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1481 {
1482         unsigned i;
1483         struct msr_autoload *m = &vmx->msr_autoload;
1484
1485         switch (msr) {
1486         case MSR_EFER:
1487                 if (cpu_has_load_ia32_efer) {
1488                         clear_atomic_switch_msr_special(vmx,
1489                                         VM_ENTRY_LOAD_IA32_EFER,
1490                                         VM_EXIT_LOAD_IA32_EFER);
1491                         return;
1492                 }
1493                 break;
1494         case MSR_CORE_PERF_GLOBAL_CTRL:
1495                 if (cpu_has_load_perf_global_ctrl) {
1496                         clear_atomic_switch_msr_special(vmx,
1497                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1498                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1499                         return;
1500                 }
1501                 break;
1502         }
1503
1504         for (i = 0; i < m->nr; ++i)
1505                 if (m->guest[i].index == msr)
1506                         break;
1507
1508         if (i == m->nr)
1509                 return;
1510         --m->nr;
1511         m->guest[i] = m->guest[m->nr];
1512         m->host[i] = m->host[m->nr];
1513         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1514         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1515 }
1516
1517 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1518                 unsigned long entry, unsigned long exit,
1519                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1520                 u64 guest_val, u64 host_val)
1521 {
1522         vmcs_write64(guest_val_vmcs, guest_val);
1523         vmcs_write64(host_val_vmcs, host_val);
1524         vm_entry_controls_setbit(vmx, entry);
1525         vm_exit_controls_setbit(vmx, exit);
1526 }
1527
1528 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1529                                   u64 guest_val, u64 host_val)
1530 {
1531         unsigned i;
1532         struct msr_autoload *m = &vmx->msr_autoload;
1533
1534         switch (msr) {
1535         case MSR_EFER:
1536                 if (cpu_has_load_ia32_efer) {
1537                         add_atomic_switch_msr_special(vmx,
1538                                         VM_ENTRY_LOAD_IA32_EFER,
1539                                         VM_EXIT_LOAD_IA32_EFER,
1540                                         GUEST_IA32_EFER,
1541                                         HOST_IA32_EFER,
1542                                         guest_val, host_val);
1543                         return;
1544                 }
1545                 break;
1546         case MSR_CORE_PERF_GLOBAL_CTRL:
1547                 if (cpu_has_load_perf_global_ctrl) {
1548                         add_atomic_switch_msr_special(vmx,
1549                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1550                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1551                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1552                                         HOST_IA32_PERF_GLOBAL_CTRL,
1553                                         guest_val, host_val);
1554                         return;
1555                 }
1556                 break;
1557         }
1558
1559         for (i = 0; i < m->nr; ++i)
1560                 if (m->guest[i].index == msr)
1561                         break;
1562
1563         if (i == NR_AUTOLOAD_MSRS) {
1564                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1565                                 "Can't add msr %x\n", msr);
1566                 return;
1567         } else if (i == m->nr) {
1568                 ++m->nr;
1569                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1570                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1571         }
1572
1573         m->guest[i].index = msr;
1574         m->guest[i].value = guest_val;
1575         m->host[i].index = msr;
1576         m->host[i].value = host_val;
1577 }
1578
1579 static void reload_tss(void)
1580 {
1581         /*
1582          * VT restores TR but not its size.  Useless.
1583          */
1584         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1585         struct desc_struct *descs;
1586
1587         descs = (void *)gdt->address;
1588         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1589         load_TR_desc();
1590 }
1591
1592 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1593 {
1594         u64 guest_efer;
1595         u64 ignore_bits;
1596
1597         guest_efer = vmx->vcpu.arch.efer;
1598
1599         /*
1600          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1601          * outside long mode
1602          */
1603         ignore_bits = EFER_NX | EFER_SCE;
1604 #ifdef CONFIG_X86_64
1605         ignore_bits |= EFER_LMA | EFER_LME;
1606         /* SCE is meaningful only in long mode on Intel */
1607         if (guest_efer & EFER_LMA)
1608                 ignore_bits &= ~(u64)EFER_SCE;
1609 #endif
1610         guest_efer &= ~ignore_bits;
1611         guest_efer |= host_efer & ignore_bits;
1612         vmx->guest_msrs[efer_offset].data = guest_efer;
1613         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1614
1615         clear_atomic_switch_msr(vmx, MSR_EFER);
1616         /* On ept, can't emulate nx, and must switch nx atomically */
1617         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1618                 guest_efer = vmx->vcpu.arch.efer;
1619                 if (!(guest_efer & EFER_LMA))
1620                         guest_efer &= ~EFER_LME;
1621                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1622                 return false;
1623         }
1624
1625         return true;
1626 }
1627
1628 static unsigned long segment_base(u16 selector)
1629 {
1630         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1631         struct desc_struct *d;
1632         unsigned long table_base;
1633         unsigned long v;
1634
1635         if (!(selector & ~3))
1636                 return 0;
1637
1638         table_base = gdt->address;
1639
1640         if (selector & 4) {           /* from ldt */
1641                 u16 ldt_selector = kvm_read_ldt();
1642
1643                 if (!(ldt_selector & ~3))
1644                         return 0;
1645
1646                 table_base = segment_base(ldt_selector);
1647         }
1648         d = (struct desc_struct *)(table_base + (selector & ~7));
1649         v = get_desc_base(d);
1650 #ifdef CONFIG_X86_64
1651        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1652                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1653 #endif
1654         return v;
1655 }
1656
1657 static inline unsigned long kvm_read_tr_base(void)
1658 {
1659         u16 tr;
1660         asm("str %0" : "=g"(tr));
1661         return segment_base(tr);
1662 }
1663
1664 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1665 {
1666         struct vcpu_vmx *vmx = to_vmx(vcpu);
1667         int i;
1668
1669         if (vmx->host_state.loaded)
1670                 return;
1671
1672         vmx->host_state.loaded = 1;
1673         /*
1674          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1675          * allow segment selectors with cpl > 0 or ti == 1.
1676          */
1677         vmx->host_state.ldt_sel = kvm_read_ldt();
1678         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1679         savesegment(fs, vmx->host_state.fs_sel);
1680         if (!(vmx->host_state.fs_sel & 7)) {
1681                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1682                 vmx->host_state.fs_reload_needed = 0;
1683         } else {
1684                 vmcs_write16(HOST_FS_SELECTOR, 0);
1685                 vmx->host_state.fs_reload_needed = 1;
1686         }
1687         savesegment(gs, vmx->host_state.gs_sel);
1688         if (!(vmx->host_state.gs_sel & 7))
1689                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1690         else {
1691                 vmcs_write16(HOST_GS_SELECTOR, 0);
1692                 vmx->host_state.gs_ldt_reload_needed = 1;
1693         }
1694
1695 #ifdef CONFIG_X86_64
1696         savesegment(ds, vmx->host_state.ds_sel);
1697         savesegment(es, vmx->host_state.es_sel);
1698 #endif
1699
1700 #ifdef CONFIG_X86_64
1701         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1702         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1703 #else
1704         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1705         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1706 #endif
1707
1708 #ifdef CONFIG_X86_64
1709         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1710         if (is_long_mode(&vmx->vcpu))
1711                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1712 #endif
1713         for (i = 0; i < vmx->save_nmsrs; ++i)
1714                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1715                                    vmx->guest_msrs[i].data,
1716                                    vmx->guest_msrs[i].mask);
1717 }
1718
1719 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1720 {
1721         if (!vmx->host_state.loaded)
1722                 return;
1723
1724         ++vmx->vcpu.stat.host_state_reload;
1725         vmx->host_state.loaded = 0;
1726 #ifdef CONFIG_X86_64
1727         if (is_long_mode(&vmx->vcpu))
1728                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1729 #endif
1730         if (vmx->host_state.gs_ldt_reload_needed) {
1731                 kvm_load_ldt(vmx->host_state.ldt_sel);
1732 #ifdef CONFIG_X86_64
1733                 load_gs_index(vmx->host_state.gs_sel);
1734 #else
1735                 loadsegment(gs, vmx->host_state.gs_sel);
1736 #endif
1737         }
1738         if (vmx->host_state.fs_reload_needed)
1739                 loadsegment(fs, vmx->host_state.fs_sel);
1740 #ifdef CONFIG_X86_64
1741         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1742                 loadsegment(ds, vmx->host_state.ds_sel);
1743                 loadsegment(es, vmx->host_state.es_sel);
1744         }
1745 #endif
1746         reload_tss();
1747 #ifdef CONFIG_X86_64
1748         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1749 #endif
1750         /*
1751          * If the FPU is not active (through the host task or
1752          * the guest vcpu), then restore the cr0.TS bit.
1753          */
1754         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1755                 stts();
1756         load_gdt(&__get_cpu_var(host_gdt));
1757 }
1758
1759 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1760 {
1761         preempt_disable();
1762         __vmx_load_host_state(vmx);
1763         preempt_enable();
1764 }
1765
1766 /*
1767  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1768  * vcpu mutex is already taken.
1769  */
1770 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1771 {
1772         struct vcpu_vmx *vmx = to_vmx(vcpu);
1773         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1774
1775         if (!vmm_exclusive)
1776                 kvm_cpu_vmxon(phys_addr);
1777         else if (vmx->loaded_vmcs->cpu != cpu)
1778                 loaded_vmcs_clear(vmx->loaded_vmcs);
1779
1780         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1781                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1782                 vmcs_load(vmx->loaded_vmcs->vmcs);
1783         }
1784
1785         if (vmx->loaded_vmcs->cpu != cpu) {
1786                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1787                 unsigned long sysenter_esp;
1788
1789                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1790                 local_irq_disable();
1791                 crash_disable_local_vmclear(cpu);
1792
1793                 /*
1794                  * Read loaded_vmcs->cpu should be before fetching
1795                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1796                  * See the comments in __loaded_vmcs_clear().
1797                  */
1798                 smp_rmb();
1799
1800                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1801                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1802                 crash_enable_local_vmclear(cpu);
1803                 local_irq_enable();
1804
1805                 /*
1806                  * Linux uses per-cpu TSS and GDT, so set these when switching
1807                  * processors.
1808                  */
1809                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1810                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1811
1812                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1813                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1814                 vmx->loaded_vmcs->cpu = cpu;
1815         }
1816 }
1817
1818 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1819 {
1820         __vmx_load_host_state(to_vmx(vcpu));
1821         if (!vmm_exclusive) {
1822                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1823                 vcpu->cpu = -1;
1824                 kvm_cpu_vmxoff();
1825         }
1826 }
1827
1828 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1829 {
1830         ulong cr0;
1831
1832         if (vcpu->fpu_active)
1833                 return;
1834         vcpu->fpu_active = 1;
1835         cr0 = vmcs_readl(GUEST_CR0);
1836         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1837         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1838         vmcs_writel(GUEST_CR0, cr0);
1839         update_exception_bitmap(vcpu);
1840         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1841         if (is_guest_mode(vcpu))
1842                 vcpu->arch.cr0_guest_owned_bits &=
1843                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1844         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1845 }
1846
1847 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1848
1849 /*
1850  * Return the cr0 value that a nested guest would read. This is a combination
1851  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1852  * its hypervisor (cr0_read_shadow).
1853  */
1854 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1855 {
1856         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1857                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1858 }
1859 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1860 {
1861         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1862                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1863 }
1864
1865 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1866 {
1867         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1868          * set this *before* calling this function.
1869          */
1870         vmx_decache_cr0_guest_bits(vcpu);
1871         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1872         update_exception_bitmap(vcpu);
1873         vcpu->arch.cr0_guest_owned_bits = 0;
1874         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1875         if (is_guest_mode(vcpu)) {
1876                 /*
1877                  * L1's specified read shadow might not contain the TS bit,
1878                  * so now that we turned on shadowing of this bit, we need to
1879                  * set this bit of the shadow. Like in nested_vmx_run we need
1880                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1881                  * up-to-date here because we just decached cr0.TS (and we'll
1882                  * only update vmcs12->guest_cr0 on nested exit).
1883                  */
1884                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1885                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1886                         (vcpu->arch.cr0 & X86_CR0_TS);
1887                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1888         } else
1889                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1890 }
1891
1892 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1893 {
1894         unsigned long rflags, save_rflags;
1895
1896         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1897                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1898                 rflags = vmcs_readl(GUEST_RFLAGS);
1899                 if (to_vmx(vcpu)->rmode.vm86_active) {
1900                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1901                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1902                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1903                 }
1904                 to_vmx(vcpu)->rflags = rflags;
1905         }
1906         return to_vmx(vcpu)->rflags;
1907 }
1908
1909 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1910 {
1911         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1912         to_vmx(vcpu)->rflags = rflags;
1913         if (to_vmx(vcpu)->rmode.vm86_active) {
1914                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1915                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1916         }
1917         vmcs_writel(GUEST_RFLAGS, rflags);
1918 }
1919
1920 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1921 {
1922         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1923         int ret = 0;
1924
1925         if (interruptibility & GUEST_INTR_STATE_STI)
1926                 ret |= KVM_X86_SHADOW_INT_STI;
1927         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1928                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1929
1930         return ret & mask;
1931 }
1932
1933 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1934 {
1935         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1936         u32 interruptibility = interruptibility_old;
1937
1938         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1939
1940         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1941                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1942         else if (mask & KVM_X86_SHADOW_INT_STI)
1943                 interruptibility |= GUEST_INTR_STATE_STI;
1944
1945         if ((interruptibility != interruptibility_old))
1946                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1947 }
1948
1949 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1950 {
1951         unsigned long rip;
1952
1953         rip = kvm_rip_read(vcpu);
1954         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1955         kvm_rip_write(vcpu, rip);
1956
1957         /* skipping an emulated instruction also counts */
1958         vmx_set_interrupt_shadow(vcpu, 0);
1959 }
1960
1961 /*
1962  * KVM wants to inject page-faults which it got to the guest. This function
1963  * checks whether in a nested guest, we need to inject them to L1 or L2.
1964  */
1965 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
1966 {
1967         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1968
1969         if (!(vmcs12->exception_bitmap & (1u << nr)))
1970                 return 0;
1971
1972         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1973                           vmcs_read32(VM_EXIT_INTR_INFO),
1974                           vmcs_readl(EXIT_QUALIFICATION));
1975         return 1;
1976 }
1977
1978 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1979                                 bool has_error_code, u32 error_code,
1980                                 bool reinject)
1981 {
1982         struct vcpu_vmx *vmx = to_vmx(vcpu);
1983         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1984
1985         if (!reinject && is_guest_mode(vcpu) &&
1986             nested_vmx_check_exception(vcpu, nr))
1987                 return;
1988
1989         if (has_error_code) {
1990                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1991                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1992         }
1993
1994         if (vmx->rmode.vm86_active) {
1995                 int inc_eip = 0;
1996                 if (kvm_exception_is_soft(nr))
1997                         inc_eip = vcpu->arch.event_exit_inst_len;
1998                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1999                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2000                 return;
2001         }
2002
2003         if (kvm_exception_is_soft(nr)) {
2004                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2005                              vmx->vcpu.arch.event_exit_inst_len);
2006                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2007         } else
2008                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2009
2010         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2011 }
2012
2013 static bool vmx_rdtscp_supported(void)
2014 {
2015         return cpu_has_vmx_rdtscp();
2016 }
2017
2018 static bool vmx_invpcid_supported(void)
2019 {
2020         return cpu_has_vmx_invpcid() && enable_ept;
2021 }
2022
2023 /*
2024  * Swap MSR entry in host/guest MSR entry array.
2025  */
2026 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2027 {
2028         struct shared_msr_entry tmp;
2029
2030         tmp = vmx->guest_msrs[to];
2031         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2032         vmx->guest_msrs[from] = tmp;
2033 }
2034
2035 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2036 {
2037         unsigned long *msr_bitmap;
2038
2039         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2040                 if (is_long_mode(vcpu))
2041                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2042                 else
2043                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2044         } else {
2045                 if (is_long_mode(vcpu))
2046                         msr_bitmap = vmx_msr_bitmap_longmode;
2047                 else
2048                         msr_bitmap = vmx_msr_bitmap_legacy;
2049         }
2050
2051         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2052 }
2053
2054 /*
2055  * Set up the vmcs to automatically save and restore system
2056  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2057  * mode, as fiddling with msrs is very expensive.
2058  */
2059 static void setup_msrs(struct vcpu_vmx *vmx)
2060 {
2061         int save_nmsrs, index;
2062
2063         save_nmsrs = 0;
2064 #ifdef CONFIG_X86_64
2065         if (is_long_mode(&vmx->vcpu)) {
2066                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2067                 if (index >= 0)
2068                         move_msr_up(vmx, index, save_nmsrs++);
2069                 index = __find_msr_index(vmx, MSR_LSTAR);
2070                 if (index >= 0)
2071                         move_msr_up(vmx, index, save_nmsrs++);
2072                 index = __find_msr_index(vmx, MSR_CSTAR);
2073                 if (index >= 0)
2074                         move_msr_up(vmx, index, save_nmsrs++);
2075                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2076                 if (index >= 0 && vmx->rdtscp_enabled)
2077                         move_msr_up(vmx, index, save_nmsrs++);
2078                 /*
2079                  * MSR_STAR is only needed on long mode guests, and only
2080                  * if efer.sce is enabled.
2081                  */
2082                 index = __find_msr_index(vmx, MSR_STAR);
2083                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2084                         move_msr_up(vmx, index, save_nmsrs++);
2085         }
2086 #endif
2087         index = __find_msr_index(vmx, MSR_EFER);
2088         if (index >= 0 && update_transition_efer(vmx, index))
2089                 move_msr_up(vmx, index, save_nmsrs++);
2090
2091         vmx->save_nmsrs = save_nmsrs;
2092
2093         if (cpu_has_vmx_msr_bitmap())
2094                 vmx_set_msr_bitmap(&vmx->vcpu);
2095 }
2096
2097 /*
2098  * reads and returns guest's timestamp counter "register"
2099  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2100  */
2101 static u64 guest_read_tsc(void)
2102 {
2103         u64 host_tsc, tsc_offset;
2104
2105         rdtscll(host_tsc);
2106         tsc_offset = vmcs_read64(TSC_OFFSET);
2107         return host_tsc + tsc_offset;
2108 }
2109
2110 /*
2111  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2112  * counter, even if a nested guest (L2) is currently running.
2113  */
2114 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2115 {
2116         u64 tsc_offset;
2117
2118         tsc_offset = is_guest_mode(vcpu) ?
2119                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2120                 vmcs_read64(TSC_OFFSET);
2121         return host_tsc + tsc_offset;
2122 }
2123
2124 /*
2125  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2126  * software catchup for faster rates on slower CPUs.
2127  */
2128 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2129 {
2130         if (!scale)
2131                 return;
2132
2133         if (user_tsc_khz > tsc_khz) {
2134                 vcpu->arch.tsc_catchup = 1;
2135                 vcpu->arch.tsc_always_catchup = 1;
2136         } else
2137                 WARN(1, "user requested TSC rate below hardware speed\n");
2138 }
2139
2140 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2141 {
2142         return vmcs_read64(TSC_OFFSET);
2143 }
2144
2145 /*
2146  * writes 'offset' into guest's timestamp counter offset register
2147  */
2148 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2149 {
2150         if (is_guest_mode(vcpu)) {
2151                 /*
2152                  * We're here if L1 chose not to trap WRMSR to TSC. According
2153                  * to the spec, this should set L1's TSC; The offset that L1
2154                  * set for L2 remains unchanged, and still needs to be added
2155                  * to the newly set TSC to get L2's TSC.
2156                  */
2157                 struct vmcs12 *vmcs12;
2158                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2159                 /* recalculate vmcs02.TSC_OFFSET: */
2160                 vmcs12 = get_vmcs12(vcpu);
2161                 vmcs_write64(TSC_OFFSET, offset +
2162                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2163                          vmcs12->tsc_offset : 0));
2164         } else {
2165                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2166                                            vmcs_read64(TSC_OFFSET), offset);
2167                 vmcs_write64(TSC_OFFSET, offset);
2168         }
2169 }
2170
2171 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2172 {
2173         u64 offset = vmcs_read64(TSC_OFFSET);
2174
2175         vmcs_write64(TSC_OFFSET, offset + adjustment);
2176         if (is_guest_mode(vcpu)) {
2177                 /* Even when running L2, the adjustment needs to apply to L1 */
2178                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2179         } else
2180                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2181                                            offset + adjustment);
2182 }
2183
2184 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2185 {
2186         return target_tsc - native_read_tsc();
2187 }
2188
2189 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2190 {
2191         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2192         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2193 }
2194
2195 /*
2196  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2197  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2198  * all guests if the "nested" module option is off, and can also be disabled
2199  * for a single guest by disabling its VMX cpuid bit.
2200  */
2201 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2202 {
2203         return nested && guest_cpuid_has_vmx(vcpu);
2204 }
2205
2206 /*
2207  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2208  * returned for the various VMX controls MSRs when nested VMX is enabled.
2209  * The same values should also be used to verify that vmcs12 control fields are
2210  * valid during nested entry from L1 to L2.
2211  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2212  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2213  * bit in the high half is on if the corresponding bit in the control field
2214  * may be on. See also vmx_control_verify().
2215  * TODO: allow these variables to be modified (downgraded) by module options
2216  * or other means.
2217  */
2218 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2219 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2220 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2221 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2222 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2223 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2224 static u32 nested_vmx_ept_caps;
2225 static __init void nested_vmx_setup_ctls_msrs(void)
2226 {
2227         /*
2228          * Note that as a general rule, the high half of the MSRs (bits in
2229          * the control fields which may be 1) should be initialized by the
2230          * intersection of the underlying hardware's MSR (i.e., features which
2231          * can be supported) and the list of features we want to expose -
2232          * because they are known to be properly supported in our code.
2233          * Also, usually, the low half of the MSRs (bits which must be 1) can
2234          * be set to 0, meaning that L1 may turn off any of these bits. The
2235          * reason is that if one of these bits is necessary, it will appear
2236          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2237          * fields of vmcs01 and vmcs02, will turn these bits off - and
2238          * nested_vmx_exit_handled() will not pass related exits to L1.
2239          * These rules have exceptions below.
2240          */
2241
2242         /* pin-based controls */
2243         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2244               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2245         /*
2246          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2247          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2248          */
2249         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2250         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2251                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2252                 PIN_BASED_VMX_PREEMPTION_TIMER;
2253         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2254
2255         /*
2256          * Exit controls
2257          * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2258          * 17 must be 1.
2259          */
2260         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2261                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2262         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2263         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2264         nested_vmx_exit_ctls_high &=
2265 #ifdef CONFIG_X86_64
2266                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2267 #endif
2268                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
2269                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2270         if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
2271             !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
2272                 nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2273                 nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2274         }
2275         nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2276                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
2277
2278         /* entry controls */
2279         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2280                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2281         /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2282         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2283         nested_vmx_entry_ctls_high &=
2284 #ifdef CONFIG_X86_64
2285                 VM_ENTRY_IA32E_MODE |
2286 #endif
2287                 VM_ENTRY_LOAD_IA32_PAT;
2288         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2289                                        VM_ENTRY_LOAD_IA32_EFER);
2290
2291         /* cpu-based controls */
2292         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2293                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2294         nested_vmx_procbased_ctls_low = 0;
2295         nested_vmx_procbased_ctls_high &=
2296                 CPU_BASED_VIRTUAL_INTR_PENDING |
2297                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2298                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2299                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2300                 CPU_BASED_CR3_STORE_EXITING |
2301 #ifdef CONFIG_X86_64
2302                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2303 #endif
2304                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2305                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2306                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2307                 CPU_BASED_PAUSE_EXITING |
2308                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2309         /*
2310          * We can allow some features even when not supported by the
2311          * hardware. For example, L1 can specify an MSR bitmap - and we
2312          * can use it to avoid exits to L1 - even when L0 runs L2
2313          * without MSR bitmaps.
2314          */
2315         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2316
2317         /* secondary cpu-based controls */
2318         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2319                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2320         nested_vmx_secondary_ctls_low = 0;
2321         nested_vmx_secondary_ctls_high &=
2322                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2323                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2324                 SECONDARY_EXEC_WBINVD_EXITING;
2325
2326         if (enable_ept) {
2327                 /* nested EPT: emulate EPT also to L1 */
2328                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2329                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2330                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2331                          VMX_EPT_INVEPT_BIT;
2332                 nested_vmx_ept_caps &= vmx_capability.ept;
2333                 /*
2334                  * Since invept is completely emulated we support both global
2335                  * and context invalidation independent of what host cpu
2336                  * supports
2337                  */
2338                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2339                         VMX_EPT_EXTENT_CONTEXT_BIT;
2340         } else
2341                 nested_vmx_ept_caps = 0;
2342
2343         /* miscellaneous data */
2344         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2345         nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2346                 VMX_MISC_SAVE_EFER_LMA;
2347         nested_vmx_misc_low |= VMX_MISC_ACTIVITY_HLT;
2348         nested_vmx_misc_high = 0;
2349 }
2350
2351 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2352 {
2353         /*
2354          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2355          */
2356         return ((control & high) | low) == control;
2357 }
2358
2359 static inline u64 vmx_control_msr(u32 low, u32 high)
2360 {
2361         return low | ((u64)high << 32);
2362 }
2363
2364 /* Returns 0 on success, non-0 otherwise. */
2365 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2366 {
2367         switch (msr_index) {
2368         case MSR_IA32_VMX_BASIC:
2369                 /*
2370                  * This MSR reports some information about VMX support. We
2371                  * should return information about the VMX we emulate for the
2372                  * guest, and the VMCS structure we give it - not about the
2373                  * VMX support of the underlying hardware.
2374                  */
2375                 *pdata = VMCS12_REVISION |
2376                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2377                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2378                 break;
2379         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2380         case MSR_IA32_VMX_PINBASED_CTLS:
2381                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2382                                         nested_vmx_pinbased_ctls_high);
2383                 break;
2384         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2385         case MSR_IA32_VMX_PROCBASED_CTLS:
2386                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2387                                         nested_vmx_procbased_ctls_high);
2388                 break;
2389         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2390         case MSR_IA32_VMX_EXIT_CTLS:
2391                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2392                                         nested_vmx_exit_ctls_high);
2393                 break;
2394         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2395         case MSR_IA32_VMX_ENTRY_CTLS:
2396                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2397                                         nested_vmx_entry_ctls_high);
2398                 break;
2399         case MSR_IA32_VMX_MISC:
2400                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2401                                          nested_vmx_misc_high);
2402                 break;
2403         /*
2404          * These MSRs specify bits which the guest must keep fixed (on or off)
2405          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2406          * We picked the standard core2 setting.
2407          */
2408 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2409 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2410         case MSR_IA32_VMX_CR0_FIXED0:
2411                 *pdata = VMXON_CR0_ALWAYSON;
2412                 break;
2413         case MSR_IA32_VMX_CR0_FIXED1:
2414                 *pdata = -1ULL;
2415                 break;
2416         case MSR_IA32_VMX_CR4_FIXED0:
2417                 *pdata = VMXON_CR4_ALWAYSON;
2418                 break;
2419         case MSR_IA32_VMX_CR4_FIXED1:
2420                 *pdata = -1ULL;
2421                 break;
2422         case MSR_IA32_VMX_VMCS_ENUM:
2423                 *pdata = 0x1f;
2424                 break;
2425         case MSR_IA32_VMX_PROCBASED_CTLS2:
2426                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2427                                         nested_vmx_secondary_ctls_high);
2428                 break;
2429         case MSR_IA32_VMX_EPT_VPID_CAP:
2430                 /* Currently, no nested vpid support */
2431                 *pdata = nested_vmx_ept_caps;
2432                 break;
2433         default:
2434                 return 1;
2435         }
2436
2437         return 0;
2438 }
2439
2440 /*
2441  * Reads an msr value (of 'msr_index') into 'pdata'.
2442  * Returns 0 on success, non-0 otherwise.
2443  * Assumes vcpu_load() was already called.
2444  */
2445 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2446 {
2447         u64 data;
2448         struct shared_msr_entry *msr;
2449
2450         if (!pdata) {
2451                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2452                 return -EINVAL;
2453         }
2454
2455         switch (msr_index) {
2456 #ifdef CONFIG_X86_64
2457         case MSR_FS_BASE:
2458                 data = vmcs_readl(GUEST_FS_BASE);
2459                 break;
2460         case MSR_GS_BASE:
2461                 data = vmcs_readl(GUEST_GS_BASE);
2462                 break;
2463         case MSR_KERNEL_GS_BASE:
2464                 vmx_load_host_state(to_vmx(vcpu));
2465                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2466                 break;
2467 #endif
2468         case MSR_EFER:
2469                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2470         case MSR_IA32_TSC:
2471                 data = guest_read_tsc();
2472                 break;
2473         case MSR_IA32_SYSENTER_CS:
2474                 data = vmcs_read32(GUEST_SYSENTER_CS);
2475                 break;
2476         case MSR_IA32_SYSENTER_EIP:
2477                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2478                 break;
2479         case MSR_IA32_SYSENTER_ESP:
2480                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2481                 break;
2482         case MSR_IA32_FEATURE_CONTROL:
2483                 if (!nested_vmx_allowed(vcpu))
2484                         return 1;
2485                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2486                 break;
2487         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2488                 if (!nested_vmx_allowed(vcpu))
2489                         return 1;
2490                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2491         case MSR_TSC_AUX:
2492                 if (!to_vmx(vcpu)->rdtscp_enabled)
2493                         return 1;
2494                 /* Otherwise falls through */
2495         default:
2496                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2497                 if (msr) {
2498                         data = msr->data;
2499                         break;
2500                 }
2501                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2502         }
2503
2504         *pdata = data;
2505         return 0;
2506 }
2507
2508 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2509
2510 /*
2511  * Writes msr value into into the appropriate "register".
2512  * Returns 0 on success, non-0 otherwise.
2513  * Assumes vcpu_load() was already called.
2514  */
2515 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2516 {
2517         struct vcpu_vmx *vmx = to_vmx(vcpu);
2518         struct shared_msr_entry *msr;
2519         int ret = 0;
2520         u32 msr_index = msr_info->index;
2521         u64 data = msr_info->data;
2522
2523         switch (msr_index) {
2524         case MSR_EFER:
2525                 ret = kvm_set_msr_common(vcpu, msr_info);
2526                 break;
2527 #ifdef CONFIG_X86_64
2528         case MSR_FS_BASE:
2529                 vmx_segment_cache_clear(vmx);
2530                 vmcs_writel(GUEST_FS_BASE, data);
2531                 break;
2532         case MSR_GS_BASE:
2533                 vmx_segment_cache_clear(vmx);
2534                 vmcs_writel(GUEST_GS_BASE, data);
2535                 break;
2536         case MSR_KERNEL_GS_BASE:
2537                 vmx_load_host_state(vmx);
2538                 vmx->msr_guest_kernel_gs_base = data;
2539                 break;
2540 #endif
2541         case MSR_IA32_SYSENTER_CS:
2542                 vmcs_write32(GUEST_SYSENTER_CS, data);
2543                 break;
2544         case MSR_IA32_SYSENTER_EIP:
2545                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2546                 break;
2547         case MSR_IA32_SYSENTER_ESP:
2548                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2549                 break;
2550         case MSR_IA32_TSC:
2551                 kvm_write_tsc(vcpu, msr_info);
2552                 break;
2553         case MSR_IA32_CR_PAT:
2554                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2555                         vmcs_write64(GUEST_IA32_PAT, data);
2556                         vcpu->arch.pat = data;
2557                         break;
2558                 }
2559                 ret = kvm_set_msr_common(vcpu, msr_info);
2560                 break;
2561         case MSR_IA32_TSC_ADJUST:
2562                 ret = kvm_set_msr_common(vcpu, msr_info);
2563                 break;
2564         case MSR_IA32_FEATURE_CONTROL:
2565                 if (!nested_vmx_allowed(vcpu) ||
2566                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2567                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2568                         return 1;
2569                 vmx->nested.msr_ia32_feature_control = data;
2570                 if (msr_info->host_initiated && data == 0)
2571                         vmx_leave_nested(vcpu);
2572                 break;
2573         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2574                 return 1; /* they are read-only */
2575         case MSR_TSC_AUX:
2576                 if (!vmx->rdtscp_enabled)
2577                         return 1;
2578                 /* Check reserved bit, higher 32 bits should be zero */
2579                 if ((data >> 32) != 0)
2580                         return 1;
2581                 /* Otherwise falls through */
2582         default:
2583                 msr = find_msr_entry(vmx, msr_index);
2584                 if (msr) {
2585                         u64 old_msr_data = msr->data;
2586                         msr->data = data;
2587                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2588                                 preempt_disable();
2589                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2590                                                          msr->mask);
2591                                 preempt_enable();
2592                                 if (ret)
2593                                         msr->data = old_msr_data;
2594                         }
2595                         break;
2596                 }
2597                 ret = kvm_set_msr_common(vcpu, msr_info);
2598         }
2599
2600         return ret;
2601 }
2602
2603 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2604 {
2605         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2606         switch (reg) {
2607         case VCPU_REGS_RSP:
2608                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2609                 break;
2610         case VCPU_REGS_RIP:
2611                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2612                 break;
2613         case VCPU_EXREG_PDPTR:
2614                 if (enable_ept)
2615                         ept_save_pdptrs(vcpu);
2616                 break;
2617         default:
2618                 break;
2619         }
2620 }
2621
2622 static __init int cpu_has_kvm_support(void)
2623 {
2624         return cpu_has_vmx();
2625 }
2626
2627 static __init int vmx_disabled_by_bios(void)
2628 {
2629         u64 msr;
2630
2631         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2632         if (msr & FEATURE_CONTROL_LOCKED) {
2633                 /* launched w/ TXT and VMX disabled */
2634                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2635                         && tboot_enabled())
2636                         return 1;
2637                 /* launched w/o TXT and VMX only enabled w/ TXT */
2638                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2639                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2640                         && !tboot_enabled()) {
2641                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2642                                 "activate TXT before enabling KVM\n");
2643                         return 1;
2644                 }
2645                 /* launched w/o TXT and VMX disabled */
2646                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2647                         && !tboot_enabled())
2648                         return 1;
2649         }
2650
2651         return 0;
2652 }
2653
2654 static void kvm_cpu_vmxon(u64 addr)
2655 {
2656         asm volatile (ASM_VMX_VMXON_RAX
2657                         : : "a"(&addr), "m"(addr)
2658                         : "memory", "cc");
2659 }
2660
2661 static int hardware_enable(void *garbage)
2662 {
2663         int cpu = raw_smp_processor_id();
2664         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2665         u64 old, test_bits;
2666
2667         if (read_cr4() & X86_CR4_VMXE)
2668                 return -EBUSY;
2669
2670         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2671
2672         /*
2673          * Now we can enable the vmclear operation in kdump
2674          * since the loaded_vmcss_on_cpu list on this cpu
2675          * has been initialized.
2676          *
2677          * Though the cpu is not in VMX operation now, there
2678          * is no problem to enable the vmclear operation
2679          * for the loaded_vmcss_on_cpu list is empty!
2680          */
2681         crash_enable_local_vmclear(cpu);
2682
2683         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2684
2685         test_bits = FEATURE_CONTROL_LOCKED;
2686         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2687         if (tboot_enabled())
2688                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2689
2690         if ((old & test_bits) != test_bits) {
2691                 /* enable and lock */
2692                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2693         }
2694         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2695
2696         if (vmm_exclusive) {
2697                 kvm_cpu_vmxon(phys_addr);
2698                 ept_sync_global();
2699         }
2700
2701         native_store_gdt(&__get_cpu_var(host_gdt));
2702
2703         return 0;
2704 }
2705
2706 static void vmclear_local_loaded_vmcss(void)
2707 {
2708         int cpu = raw_smp_processor_id();
2709         struct loaded_vmcs *v, *n;
2710
2711         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2712                                  loaded_vmcss_on_cpu_link)
2713                 __loaded_vmcs_clear(v);
2714 }
2715
2716
2717 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2718  * tricks.
2719  */
2720 static void kvm_cpu_vmxoff(void)
2721 {
2722         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2723 }
2724
2725 static void hardware_disable(void *garbage)
2726 {
2727         if (vmm_exclusive) {
2728                 vmclear_local_loaded_vmcss();
2729                 kvm_cpu_vmxoff();
2730         }
2731         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2732 }
2733
2734 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2735                                       u32 msr, u32 *result)
2736 {
2737         u32 vmx_msr_low, vmx_msr_high;
2738         u32 ctl = ctl_min | ctl_opt;
2739
2740         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2741
2742         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2743         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2744
2745         /* Ensure minimum (required) set of control bits are supported. */
2746         if (ctl_min & ~ctl)
2747                 return -EIO;
2748
2749         *result = ctl;
2750         return 0;
2751 }
2752
2753 static __init bool allow_1_setting(u32 msr, u32 ctl)
2754 {
2755         u32 vmx_msr_low, vmx_msr_high;
2756
2757         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2758         return vmx_msr_high & ctl;
2759 }
2760
2761 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2762 {
2763         u32 vmx_msr_low, vmx_msr_high;
2764         u32 min, opt, min2, opt2;
2765         u32 _pin_based_exec_control = 0;
2766         u32 _cpu_based_exec_control = 0;
2767         u32 _cpu_based_2nd_exec_control = 0;
2768         u32 _vmexit_control = 0;
2769         u32 _vmentry_control = 0;
2770
2771         min = CPU_BASED_HLT_EXITING |
2772 #ifdef CONFIG_X86_64
2773               CPU_BASED_CR8_LOAD_EXITING |
2774               CPU_BASED_CR8_STORE_EXITING |
2775 #endif
2776               CPU_BASED_CR3_LOAD_EXITING |
2777               CPU_BASED_CR3_STORE_EXITING |
2778               CPU_BASED_USE_IO_BITMAPS |
2779               CPU_BASED_MOV_DR_EXITING |
2780               CPU_BASED_USE_TSC_OFFSETING |
2781               CPU_BASED_MWAIT_EXITING |
2782               CPU_BASED_MONITOR_EXITING |
2783               CPU_BASED_INVLPG_EXITING |
2784               CPU_BASED_RDPMC_EXITING;
2785
2786         opt = CPU_BASED_TPR_SHADOW |
2787               CPU_BASED_USE_MSR_BITMAPS |
2788               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2789         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2790                                 &_cpu_based_exec_control) < 0)
2791                 return -EIO;
2792 #ifdef CONFIG_X86_64
2793         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2794                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2795                                            ~CPU_BASED_CR8_STORE_EXITING;
2796 #endif
2797         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2798                 min2 = 0;
2799                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2800                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2801                         SECONDARY_EXEC_WBINVD_EXITING |
2802                         SECONDARY_EXEC_ENABLE_VPID |
2803                         SECONDARY_EXEC_ENABLE_EPT |
2804                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2805                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2806                         SECONDARY_EXEC_RDTSCP |
2807                         SECONDARY_EXEC_ENABLE_INVPCID |
2808                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2809                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2810                         SECONDARY_EXEC_SHADOW_VMCS;
2811                 if (adjust_vmx_controls(min2, opt2,
2812                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2813                                         &_cpu_based_2nd_exec_control) < 0)
2814                         return -EIO;
2815         }
2816 #ifndef CONFIG_X86_64
2817         if (!(_cpu_based_2nd_exec_control &
2818                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2819                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2820 #endif
2821
2822         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2823                 _cpu_based_2nd_exec_control &= ~(
2824                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2825                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2826                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2827
2828         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2829                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2830                    enabled */
2831                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2832                                              CPU_BASED_CR3_STORE_EXITING |
2833                                              CPU_BASED_INVLPG_EXITING);
2834                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2835                       vmx_capability.ept, vmx_capability.vpid);
2836         }
2837
2838         min = 0;
2839 #ifdef CONFIG_X86_64
2840         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2841 #endif
2842         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2843                 VM_EXIT_ACK_INTR_ON_EXIT;
2844         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2845                                 &_vmexit_control) < 0)
2846                 return -EIO;
2847
2848         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2849         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2850         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2851                                 &_pin_based_exec_control) < 0)
2852                 return -EIO;
2853
2854         if (!(_cpu_based_2nd_exec_control &
2855                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2856                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2857                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2858
2859         min = 0;
2860         opt = VM_ENTRY_LOAD_IA32_PAT;
2861         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2862                                 &_vmentry_control) < 0)
2863                 return -EIO;
2864
2865         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2866
2867         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2868         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2869                 return -EIO;
2870
2871 #ifdef CONFIG_X86_64
2872         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2873         if (vmx_msr_high & (1u<<16))
2874                 return -EIO;
2875 #endif
2876
2877         /* Require Write-Back (WB) memory type for VMCS accesses. */
2878         if (((vmx_msr_high >> 18) & 15) != 6)
2879                 return -EIO;
2880
2881         vmcs_conf->size = vmx_msr_high & 0x1fff;
2882         vmcs_conf->order = get_order(vmcs_config.size);
2883         vmcs_conf->revision_id = vmx_msr_low;
2884
2885         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2886         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2887         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2888         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2889         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2890
2891         cpu_has_load_ia32_efer =
2892                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2893                                 VM_ENTRY_LOAD_IA32_EFER)
2894                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2895                                    VM_EXIT_LOAD_IA32_EFER);
2896
2897         cpu_has_load_perf_global_ctrl =
2898                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2899                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2900                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2901                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2902
2903         /*
2904          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2905          * but due to arrata below it can't be used. Workaround is to use
2906          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2907          *
2908          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2909          *
2910          * AAK155             (model 26)
2911          * AAP115             (model 30)
2912          * AAT100             (model 37)
2913          * BC86,AAY89,BD102   (model 44)
2914          * BA97               (model 46)
2915          *
2916          */
2917         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2918                 switch (boot_cpu_data.x86_model) {
2919                 case 26:
2920                 case 30:
2921                 case 37:
2922                 case 44:
2923                 case 46:
2924                         cpu_has_load_perf_global_ctrl = false;
2925                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2926                                         "does not work properly. Using workaround\n");
2927                         break;
2928                 default:
2929                         break;
2930                 }
2931         }
2932
2933         return 0;
2934 }
2935
2936 static struct vmcs *alloc_vmcs_cpu(int cpu)
2937 {
2938         int node = cpu_to_node(cpu);
2939         struct page *pages;
2940         struct vmcs *vmcs;
2941
2942         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2943         if (!pages)
2944                 return NULL;
2945         vmcs = page_address(pages);
2946         memset(vmcs, 0, vmcs_config.size);
2947         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2948         return vmcs;
2949 }
2950
2951 static struct vmcs *alloc_vmcs(void)
2952 {
2953         return alloc_vmcs_cpu(raw_smp_processor_id());
2954 }
2955
2956 static void free_vmcs(struct vmcs *vmcs)
2957 {
2958         free_pages((unsigned long)vmcs, vmcs_config.order);
2959 }
2960
2961 /*
2962  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2963  */
2964 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2965 {
2966         if (!loaded_vmcs->vmcs)
2967                 return;
2968         loaded_vmcs_clear(loaded_vmcs);
2969         free_vmcs(loaded_vmcs->vmcs);
2970         loaded_vmcs->vmcs = NULL;
2971 }
2972
2973 static void free_kvm_area(void)
2974 {
2975         int cpu;
2976
2977         for_each_possible_cpu(cpu) {
2978                 free_vmcs(per_cpu(vmxarea, cpu));
2979                 per_cpu(vmxarea, cpu) = NULL;
2980         }
2981 }
2982
2983 static __init int alloc_kvm_area(void)
2984 {
2985         int cpu;
2986
2987         for_each_possible_cpu(cpu) {
2988                 struct vmcs *vmcs;
2989
2990                 vmcs = alloc_vmcs_cpu(cpu);
2991                 if (!vmcs) {
2992                         free_kvm_area();
2993                         return -ENOMEM;
2994                 }
2995
2996                 per_cpu(vmxarea, cpu) = vmcs;
2997         }
2998         return 0;
2999 }
3000
3001 static __init int hardware_setup(void)
3002 {
3003         if (setup_vmcs_config(&vmcs_config) < 0)
3004                 return -EIO;
3005
3006         if (boot_cpu_has(X86_FEATURE_NX))
3007                 kvm_enable_efer_bits(EFER_NX);
3008
3009         if (!cpu_has_vmx_vpid())
3010                 enable_vpid = 0;
3011         if (!cpu_has_vmx_shadow_vmcs())
3012                 enable_shadow_vmcs = 0;
3013
3014         if (!cpu_has_vmx_ept() ||
3015             !cpu_has_vmx_ept_4levels()) {
3016                 enable_ept = 0;
3017                 enable_unrestricted_guest = 0;
3018                 enable_ept_ad_bits = 0;
3019         }
3020
3021         if (!cpu_has_vmx_ept_ad_bits())
3022                 enable_ept_ad_bits = 0;
3023
3024         if (!cpu_has_vmx_unrestricted_guest())
3025                 enable_unrestricted_guest = 0;
3026
3027         if (!cpu_has_vmx_flexpriority())
3028                 flexpriority_enabled = 0;
3029
3030         if (!cpu_has_vmx_tpr_shadow())
3031                 kvm_x86_ops->update_cr8_intercept = NULL;
3032
3033         if (enable_ept && !cpu_has_vmx_ept_2m_page())
3034                 kvm_disable_largepages();
3035
3036         if (!cpu_has_vmx_ple())
3037                 ple_gap = 0;
3038
3039         if (!cpu_has_vmx_apicv())
3040                 enable_apicv = 0;
3041
3042         if (enable_apicv)
3043                 kvm_x86_ops->update_cr8_intercept = NULL;
3044         else {
3045                 kvm_x86_ops->hwapic_irr_update = NULL;
3046                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3047                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3048         }
3049
3050         if (nested)
3051                 nested_vmx_setup_ctls_msrs();
3052
3053         return alloc_kvm_area();
3054 }
3055
3056 static __exit void hardware_unsetup(void)
3057 {
3058         free_kvm_area();
3059 }
3060
3061 static bool emulation_required(struct kvm_vcpu *vcpu)
3062 {
3063         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3064 }
3065
3066 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3067                 struct kvm_segment *save)
3068 {
3069         if (!emulate_invalid_guest_state) {
3070                 /*
3071                  * CS and SS RPL should be equal during guest entry according
3072                  * to VMX spec, but in reality it is not always so. Since vcpu
3073                  * is in the middle of the transition from real mode to
3074                  * protected mode it is safe to assume that RPL 0 is a good
3075                  * default value.
3076                  */
3077                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3078                         save->selector &= ~SELECTOR_RPL_MASK;
3079                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3080                 save->s = 1;
3081         }
3082         vmx_set_segment(vcpu, save, seg);
3083 }
3084
3085 static void enter_pmode(struct kvm_vcpu *vcpu)
3086 {
3087         unsigned long flags;
3088         struct vcpu_vmx *vmx = to_vmx(vcpu);
3089
3090         /*
3091          * Update real mode segment cache. It may be not up-to-date if sement
3092          * register was written while vcpu was in a guest mode.
3093          */
3094         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3095         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3096         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3097         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3098         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3099         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3100
3101         vmx->rmode.vm86_active = 0;
3102
3103         vmx_segment_cache_clear(vmx);
3104
3105         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3106
3107         flags = vmcs_readl(GUEST_RFLAGS);
3108         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3109         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3110         vmcs_writel(GUEST_RFLAGS, flags);
3111
3112         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3113                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3114
3115         update_exception_bitmap(vcpu);
3116
3117         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3118         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3119         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3120         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3121         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3122         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3123
3124         /* CPL is always 0 when CPU enters protected mode */
3125         __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3126         vmx->cpl = 0;
3127 }
3128
3129 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3130 {
3131         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3132         struct kvm_segment var = *save;
3133
3134         var.dpl = 0x3;
3135         if (seg == VCPU_SREG_CS)
3136                 var.type = 0x3;
3137
3138         if (!emulate_invalid_guest_state) {
3139                 var.selector = var.base >> 4;
3140                 var.base = var.base & 0xffff0;
3141                 var.limit = 0xffff;
3142                 var.g = 0;
3143                 var.db = 0;
3144                 var.present = 1;
3145                 var.s = 1;
3146                 var.l = 0;
3147                 var.unusable = 0;
3148                 var.type = 0x3;
3149                 var.avl = 0;
3150                 if (save->base & 0xf)
3151                         printk_once(KERN_WARNING "kvm: segment base is not "
3152                                         "paragraph aligned when entering "
3153                                         "protected mode (seg=%d)", seg);
3154         }
3155
3156         vmcs_write16(sf->selector, var.selector);
3157         vmcs_write32(sf->base, var.base);
3158         vmcs_write32(sf->limit, var.limit);
3159         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3160 }
3161
3162 static void enter_rmode(struct kvm_vcpu *vcpu)
3163 {
3164         unsigned long flags;
3165         struct vcpu_vmx *vmx = to_vmx(vcpu);
3166
3167         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3168         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3169         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3170         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3171         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3172         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3173         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3174
3175         vmx->rmode.vm86_active = 1;
3176
3177         /*
3178          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3179          * vcpu. Warn the user that an update is overdue.
3180          */
3181         if (!vcpu->kvm->arch.tss_addr)
3182                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3183                              "called before entering vcpu\n");
3184
3185         vmx_segment_cache_clear(vmx);
3186
3187         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3188         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3189         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3190
3191         flags = vmcs_readl(GUEST_RFLAGS);
3192         vmx->rmode.save_rflags = flags;
3193
3194         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3195
3196         vmcs_writel(GUEST_RFLAGS, flags);
3197         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3198         update_exception_bitmap(vcpu);
3199
3200         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3201         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3202         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3203         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3204         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3205         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3206
3207         kvm_mmu_reset_context(vcpu);
3208 }
3209
3210 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3211 {
3212         struct vcpu_vmx *vmx = to_vmx(vcpu);
3213         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3214
3215         if (!msr)
3216                 return;
3217
3218         /*
3219          * Force kernel_gs_base reloading before EFER changes, as control
3220          * of this msr depends on is_long_mode().
3221          */
3222         vmx_load_host_state(to_vmx(vcpu));
3223         vcpu->arch.efer = efer;
3224         if (efer & EFER_LMA) {
3225                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3226                 msr->data = efer;
3227         } else {
3228                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3229
3230                 msr->data = efer & ~EFER_LME;
3231         }
3232         setup_msrs(vmx);
3233 }
3234
3235 #ifdef CONFIG_X86_64
3236
3237 static void enter_lmode(struct kvm_vcpu *vcpu)
3238 {
3239         u32 guest_tr_ar;
3240
3241         vmx_segment_cache_clear(to_vmx(vcpu));
3242
3243         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3244         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3245                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3246                                      __func__);
3247                 vmcs_write32(GUEST_TR_AR_BYTES,
3248                              (guest_tr_ar & ~AR_TYPE_MASK)
3249                              | AR_TYPE_BUSY_64_TSS);
3250         }
3251         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3252 }
3253
3254 static void exit_lmode(struct kvm_vcpu *vcpu)
3255 {
3256         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3257         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3258 }
3259
3260 #endif
3261
3262 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3263 {
3264         vpid_sync_context(to_vmx(vcpu));
3265         if (enable_ept) {
3266                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3267                         return;
3268                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3269         }
3270 }
3271
3272 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3273 {
3274         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3275
3276         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3277         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3278 }
3279
3280 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3281 {
3282         if (enable_ept && is_paging(vcpu))
3283                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3284         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3285 }
3286
3287 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3288 {
3289         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3290
3291         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3292         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3293 }
3294
3295 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3296 {
3297         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3298
3299         if (!test_bit(VCPU_EXREG_PDPTR,
3300                       (unsigned long *)&vcpu->arch.regs_dirty))
3301                 return;
3302
3303         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3304                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3305                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3306                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3307                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3308         }
3309 }
3310
3311 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3312 {
3313         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3314
3315         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3316                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3317                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3318                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3319                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3320         }
3321
3322         __set_bit(VCPU_EXREG_PDPTR,
3323                   (unsigned long *)&vcpu->arch.regs_avail);
3324         __set_bit(VCPU_EXREG_PDPTR,
3325                   (unsigned long *)&vcpu->arch.regs_dirty);
3326 }
3327
3328 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3329
3330 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3331                                         unsigned long cr0,
3332                                         struct kvm_vcpu *vcpu)
3333 {
3334         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3335                 vmx_decache_cr3(vcpu);
3336         if (!(cr0 & X86_CR0_PG)) {
3337                 /* From paging/starting to nonpaging */
3338                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3339                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3340                              (CPU_BASED_CR3_LOAD_EXITING |
3341                               CPU_BASED_CR3_STORE_EXITING));
3342                 vcpu->arch.cr0 = cr0;
3343                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3344         } else if (!is_paging(vcpu)) {
3345                 /* From nonpaging to paging */
3346                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3347                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3348                              ~(CPU_BASED_CR3_LOAD_EXITING |
3349                                CPU_BASED_CR3_STORE_EXITING));
3350                 vcpu->arch.cr0 = cr0;
3351                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3352         }
3353
3354         if (!(cr0 & X86_CR0_WP))
3355                 *hw_cr0 &= ~X86_CR0_WP;
3356 }
3357
3358 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3359 {
3360         struct vcpu_vmx *vmx = to_vmx(vcpu);
3361         unsigned long hw_cr0;
3362
3363         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3364         if (enable_unrestricted_guest)
3365                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3366         else {
3367                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3368
3369                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3370                         enter_pmode(vcpu);
3371
3372                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3373                         enter_rmode(vcpu);
3374         }
3375
3376 #ifdef CONFIG_X86_64
3377         if (vcpu->arch.efer & EFER_LME) {
3378                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3379                         enter_lmode(vcpu);
3380                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3381                         exit_lmode(vcpu);
3382         }
3383 #endif
3384
3385         if (enable_ept)
3386                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3387
3388         if (!vcpu->fpu_active)
3389                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3390
3391         vmcs_writel(CR0_READ_SHADOW, cr0);
3392         vmcs_writel(GUEST_CR0, hw_cr0);
3393         vcpu->arch.cr0 = cr0;
3394
3395         /* depends on vcpu->arch.cr0 to be set to a new value */
3396         vmx->emulation_required = emulation_required(vcpu);
3397 }
3398
3399 static u64 construct_eptp(unsigned long root_hpa)
3400 {
3401         u64 eptp;
3402
3403         /* TODO write the value reading from MSR */
3404         eptp = VMX_EPT_DEFAULT_MT |
3405                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3406         if (enable_ept_ad_bits)
3407                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3408         eptp |= (root_hpa & PAGE_MASK);
3409
3410         return eptp;
3411 }
3412
3413 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3414 {
3415         unsigned long guest_cr3;
3416         u64 eptp;
3417
3418         guest_cr3 = cr3;
3419         if (enable_ept) {
3420                 eptp = construct_eptp(cr3);
3421                 vmcs_write64(EPT_POINTER, eptp);
3422                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3423                         guest_cr3 = kvm_read_cr3(vcpu);
3424                 else
3425                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3426                 ept_load_pdptrs(vcpu);
3427         }
3428
3429         vmx_flush_tlb(vcpu);
3430         vmcs_writel(GUEST_CR3, guest_cr3);
3431 }
3432
3433 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3434 {
3435         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3436                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3437
3438         if (cr4 & X86_CR4_VMXE) {
3439                 /*
3440                  * To use VMXON (and later other VMX instructions), a guest
3441                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3442                  * So basically the check on whether to allow nested VMX
3443                  * is here.
3444                  */
3445                 if (!nested_vmx_allowed(vcpu))
3446                         return 1;
3447         }
3448         if (to_vmx(vcpu)->nested.vmxon &&
3449             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3450                 return 1;
3451
3452         vcpu->arch.cr4 = cr4;
3453         if (enable_ept) {
3454                 if (!is_paging(vcpu)) {
3455                         hw_cr4 &= ~X86_CR4_PAE;
3456                         hw_cr4 |= X86_CR4_PSE;
3457                         /*
3458                          * SMEP is disabled if CPU is in non-paging mode in
3459                          * hardware. However KVM always uses paging mode to
3460                          * emulate guest non-paging mode with TDP.
3461                          * To emulate this behavior, SMEP needs to be manually
3462                          * disabled when guest switches to non-paging mode.
3463                          */
3464                         hw_cr4 &= ~X86_CR4_SMEP;
3465                 } else if (!(cr4 & X86_CR4_PAE)) {
3466                         hw_cr4 &= ~X86_CR4_PAE;
3467                 }
3468         }
3469
3470         vmcs_writel(CR4_READ_SHADOW, cr4);
3471         vmcs_writel(GUEST_CR4, hw_cr4);
3472         return 0;
3473 }
3474
3475 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3476                             struct kvm_segment *var, int seg)
3477 {
3478         struct vcpu_vmx *vmx = to_vmx(vcpu);
3479         u32 ar;
3480
3481         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3482                 *var = vmx->rmode.segs[seg];
3483                 if (seg == VCPU_SREG_TR
3484                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3485                         return;
3486                 var->base = vmx_read_guest_seg_base(vmx, seg);
3487                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3488                 return;
3489         }
3490         var->base = vmx_read_guest_seg_base(vmx, seg);
3491         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3492         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3493         ar = vmx_read_guest_seg_ar(vmx, seg);
3494         var->unusable = (ar >> 16) & 1;
3495         var->type = ar & 15;
3496         var->s = (ar >> 4) & 1;
3497         var->dpl = (ar >> 5) & 3;
3498         /*
3499          * Some userspaces do not preserve unusable property. Since usable
3500          * segment has to be present according to VMX spec we can use present
3501          * property to amend userspace bug by making unusable segment always
3502          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3503          * segment as unusable.
3504          */
3505         var->present = !var->unusable;
3506         var->avl = (ar >> 12) & 1;
3507         var->l = (ar >> 13) & 1;
3508         var->db = (ar >> 14) & 1;
3509         var->g = (ar >> 15) & 1;
3510 }
3511
3512 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3513 {
3514         struct kvm_segment s;
3515
3516         if (to_vmx(vcpu)->rmode.vm86_active) {
3517                 vmx_get_segment(vcpu, &s, seg);
3518                 return s.base;
3519         }
3520         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3521 }
3522
3523 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3524 {
3525         struct vcpu_vmx *vmx = to_vmx(vcpu);
3526
3527         if (!is_protmode(vcpu))
3528                 return 0;
3529
3530         if (!is_long_mode(vcpu)
3531             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3532                 return 3;
3533
3534         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3535                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3536                 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
3537         }
3538
3539         return vmx->cpl;
3540 }
3541
3542
3543 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3544 {
3545         u32 ar;
3546
3547         if (var->unusable || !var->present)
3548                 ar = 1 << 16;
3549         else {
3550                 ar = var->type & 15;
3551                 ar |= (var->s & 1) << 4;
3552                 ar |= (var->dpl & 3) << 5;
3553                 ar |= (var->present & 1) << 7;
3554                 ar |= (var->avl & 1) << 12;
3555                 ar |= (var->l & 1) << 13;
3556                 ar |= (var->db & 1) << 14;
3557                 ar |= (var->g & 1) << 15;
3558         }
3559
3560         return ar;
3561 }
3562
3563 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3564                             struct kvm_segment *var, int seg)
3565 {
3566         struct vcpu_vmx *vmx = to_vmx(vcpu);
3567         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3568
3569         vmx_segment_cache_clear(vmx);
3570         if (seg == VCPU_SREG_CS)
3571                 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3572
3573         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3574                 vmx->rmode.segs[seg] = *var;
3575                 if (seg == VCPU_SREG_TR)
3576                         vmcs_write16(sf->selector, var->selector);
3577                 else if (var->s)
3578                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3579                 goto out;
3580         }
3581
3582         vmcs_writel(sf->base, var->base);
3583         vmcs_write32(sf->limit, var->limit);
3584         vmcs_write16(sf->selector, var->selector);
3585
3586         /*
3587          *   Fix the "Accessed" bit in AR field of segment registers for older
3588          * qemu binaries.
3589          *   IA32 arch specifies that at the time of processor reset the
3590          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3591          * is setting it to 0 in the userland code. This causes invalid guest
3592          * state vmexit when "unrestricted guest" mode is turned on.
3593          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3594          * tree. Newer qemu binaries with that qemu fix would not need this
3595          * kvm hack.
3596          */
3597         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3598                 var->type |= 0x1; /* Accessed */
3599
3600         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3601
3602 out:
3603         vmx->emulation_required |= emulation_required(vcpu);
3604 }
3605
3606 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3607 {
3608         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3609
3610         *db = (ar >> 14) & 1;
3611         *l = (ar >> 13) & 1;
3612 }
3613
3614 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3615 {
3616         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3617         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3618 }
3619
3620 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3621 {
3622         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3623         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3624 }
3625
3626 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3627 {
3628         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3629         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3630 }
3631
3632 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3633 {
3634         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3635         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3636 }
3637
3638 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3639 {
3640         struct kvm_segment var;
3641         u32 ar;
3642
3643         vmx_get_segment(vcpu, &var, seg);
3644         var.dpl = 0x3;
3645         if (seg == VCPU_SREG_CS)
3646                 var.type = 0x3;
3647         ar = vmx_segment_access_rights(&var);
3648
3649         if (var.base != (var.selector << 4))
3650                 return false;
3651         if (var.limit != 0xffff)
3652                 return false;
3653         if (ar != 0xf3)
3654                 return false;
3655
3656         return true;
3657 }
3658
3659 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3660 {
3661         struct kvm_segment cs;
3662         unsigned int cs_rpl;
3663
3664         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3665         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3666
3667         if (cs.unusable)
3668                 return false;
3669         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3670                 return false;
3671         if (!cs.s)
3672                 return false;
3673         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3674                 if (cs.dpl > cs_rpl)
3675                         return false;
3676         } else {
3677                 if (cs.dpl != cs_rpl)
3678                         return false;
3679         }
3680         if (!cs.present)
3681                 return false;
3682
3683         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3684         return true;
3685 }
3686
3687 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3688 {
3689         struct kvm_segment ss;
3690         unsigned int ss_rpl;
3691
3692         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3693         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3694
3695         if (ss.unusable)
3696                 return true;
3697         if (ss.type != 3 && ss.type != 7)
3698                 return false;
3699         if (!ss.s)
3700                 return false;
3701         if (ss.dpl != ss_rpl) /* DPL != RPL */
3702                 return false;
3703         if (!ss.present)
3704                 return false;
3705
3706         return true;
3707 }
3708
3709 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3710 {
3711         struct kvm_segment var;
3712         unsigned int rpl;
3713
3714         vmx_get_segment(vcpu, &var, seg);
3715         rpl = var.selector & SELECTOR_RPL_MASK;
3716
3717         if (var.unusable)
3718                 return true;
3719         if (!var.s)
3720                 return false;
3721         if (!var.present)
3722                 return false;
3723         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3724                 if (var.dpl < rpl) /* DPL < RPL */
3725                         return false;
3726         }
3727
3728         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3729          * rights flags
3730          */
3731         return true;
3732 }
3733
3734 static bool tr_valid(struct kvm_vcpu *vcpu)
3735 {
3736         struct kvm_segment tr;
3737
3738         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3739
3740         if (tr.unusable)
3741                 return false;
3742         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3743                 return false;
3744         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3745                 return false;
3746         if (!tr.present)
3747                 return false;
3748
3749         return true;
3750 }
3751
3752 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3753 {
3754         struct kvm_segment ldtr;
3755
3756         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3757
3758         if (ldtr.unusable)
3759                 return true;
3760         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3761                 return false;
3762         if (ldtr.type != 2)
3763                 return false;
3764         if (!ldtr.present)
3765                 return false;
3766
3767         return true;
3768 }
3769
3770 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3771 {
3772         struct kvm_segment cs, ss;
3773
3774         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3775         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3776
3777         return ((cs.selector & SELECTOR_RPL_MASK) ==
3778                  (ss.selector & SELECTOR_RPL_MASK));
3779 }
3780
3781 /*
3782  * Check if guest state is valid. Returns true if valid, false if
3783  * not.
3784  * We assume that registers are always usable
3785  */
3786 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3787 {
3788         if (enable_unrestricted_guest)
3789                 return true;
3790
3791         /* real mode guest state checks */
3792         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3793                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3794                         return false;
3795                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3796                         return false;
3797                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3798                         return false;
3799                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3800                         return false;
3801                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3802                         return false;
3803                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3804                         return false;
3805         } else {
3806         /* protected mode guest state checks */
3807                 if (!cs_ss_rpl_check(vcpu))
3808                         return false;
3809                 if (!code_segment_valid(vcpu))
3810                         return false;
3811                 if (!stack_segment_valid(vcpu))
3812                         return false;
3813                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3814                         return false;
3815                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3816                         return false;
3817                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3818                         return false;
3819                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3820                         return false;
3821                 if (!tr_valid(vcpu))
3822                         return false;
3823                 if (!ldtr_valid(vcpu))
3824                         return false;
3825         }
3826         /* TODO:
3827          * - Add checks on RIP
3828          * - Add checks on RFLAGS
3829          */
3830
3831         return true;
3832 }
3833
3834 static int init_rmode_tss(struct kvm *kvm)
3835 {
3836         gfn_t fn;
3837         u16 data = 0;
3838         int r, idx, ret = 0;
3839
3840         idx = srcu_read_lock(&kvm->srcu);
3841         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3842         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3843         if (r < 0)
3844                 goto out;
3845         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3846         r = kvm_write_guest_page(kvm, fn++, &data,
3847                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3848         if (r < 0)
3849                 goto out;
3850         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3851         if (r < 0)
3852                 goto out;
3853         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3854         if (r < 0)
3855                 goto out;
3856         data = ~0;
3857         r = kvm_write_guest_page(kvm, fn, &data,
3858                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3859                                  sizeof(u8));
3860         if (r < 0)
3861                 goto out;
3862
3863         ret = 1;
3864 out:
3865         srcu_read_unlock(&kvm->srcu, idx);
3866         return ret;
3867 }
3868
3869 static int init_rmode_identity_map(struct kvm *kvm)
3870 {
3871         int i, idx, r, ret;
3872         pfn_t identity_map_pfn;
3873         u32 tmp;
3874
3875         if (!enable_ept)
3876                 return 1;
3877         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3878                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3879                         "haven't been allocated!\n");
3880                 return 0;
3881         }
3882         if (likely(kvm->arch.ept_identity_pagetable_done))
3883                 return 1;
3884         ret = 0;
3885         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3886         idx = srcu_read_lock(&kvm->srcu);
3887         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3888         if (r < 0)
3889                 goto out;
3890         /* Set up identity-mapping pagetable for EPT in real mode */
3891         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3892                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3893                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3894                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3895                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3896                 if (r < 0)
3897                         goto out;
3898         }
3899         kvm->arch.ept_identity_pagetable_done = true;
3900         ret = 1;
3901 out:
3902         srcu_read_unlock(&kvm->srcu, idx);
3903         return ret;
3904 }
3905
3906 static void seg_setup(int seg)
3907 {
3908         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3909         unsigned int ar;
3910
3911         vmcs_write16(sf->selector, 0);
3912         vmcs_writel(sf->base, 0);
3913         vmcs_write32(sf->limit, 0xffff);
3914         ar = 0x93;
3915         if (seg == VCPU_SREG_CS)
3916                 ar |= 0x08; /* code segment */
3917
3918         vmcs_write32(sf->ar_bytes, ar);
3919 }
3920
3921 static int alloc_apic_access_page(struct kvm *kvm)
3922 {
3923         struct page *page;
3924         struct kvm_userspace_memory_region kvm_userspace_mem;
3925         int r = 0;
3926
3927         mutex_lock(&kvm->slots_lock);
3928         if (kvm->arch.apic_access_page)
3929                 goto out;
3930         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3931         kvm_userspace_mem.flags = 0;
3932         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3933         kvm_userspace_mem.memory_size = PAGE_SIZE;
3934         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3935         if (r)
3936                 goto out;
3937
3938         page = gfn_to_page(kvm, 0xfee00);
3939         if (is_error_page(page)) {
3940                 r = -EFAULT;
3941                 goto out;
3942         }
3943
3944         kvm->arch.apic_access_page = page;
3945 out:
3946         mutex_unlock(&kvm->slots_lock);
3947         return r;
3948 }
3949
3950 static int alloc_identity_pagetable(struct kvm *kvm)
3951 {
3952         struct page *page;
3953         struct kvm_userspace_memory_region kvm_userspace_mem;
3954         int r = 0;
3955
3956         mutex_lock(&kvm->slots_lock);
3957         if (kvm->arch.ept_identity_pagetable)
3958                 goto out;
3959         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3960         kvm_userspace_mem.flags = 0;
3961         kvm_userspace_mem.guest_phys_addr =
3962                 kvm->arch.ept_identity_map_addr;
3963         kvm_userspace_mem.memory_size = PAGE_SIZE;
3964         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3965         if (r)
3966                 goto out;
3967
3968         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3969         if (is_error_page(page)) {
3970                 r = -EFAULT;
3971                 goto out;
3972         }
3973
3974         kvm->arch.ept_identity_pagetable = page;
3975 out:
3976         mutex_unlock(&kvm->slots_lock);
3977         return r;
3978 }
3979
3980 static void allocate_vpid(struct vcpu_vmx *vmx)
3981 {
3982         int vpid;
3983
3984         vmx->vpid = 0;
3985         if (!enable_vpid)
3986                 return;
3987         spin_lock(&vmx_vpid_lock);
3988         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3989         if (vpid < VMX_NR_VPIDS) {
3990                 vmx->vpid = vpid;
3991                 __set_bit(vpid, vmx_vpid_bitmap);
3992         }
3993         spin_unlock(&vmx_vpid_lock);
3994 }
3995
3996 static void free_vpid(struct vcpu_vmx *vmx)
3997 {
3998         if (!enable_vpid)
3999                 return;
4000         spin_lock(&vmx_vpid_lock);
4001         if (vmx->vpid != 0)
4002                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4003         spin_unlock(&vmx_vpid_lock);
4004 }
4005
4006 #define MSR_TYPE_R      1
4007 #define MSR_TYPE_W      2
4008 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4009                                                 u32 msr, int type)
4010 {
4011         int f = sizeof(unsigned long);
4012
4013         if (!cpu_has_vmx_msr_bitmap())
4014                 return;
4015
4016         /*
4017          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4018          * have the write-low and read-high bitmap offsets the wrong way round.
4019          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4020          */
4021         if (msr <= 0x1fff) {
4022                 if (type & MSR_TYPE_R)
4023                         /* read-low */
4024                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4025
4026                 if (type & MSR_TYPE_W)
4027                         /* write-low */
4028                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4029
4030         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4031                 msr &= 0x1fff;
4032                 if (type & MSR_TYPE_R)
4033                         /* read-high */
4034                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4035
4036                 if (type & MSR_TYPE_W)
4037                         /* write-high */
4038                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4039
4040         }
4041 }
4042
4043 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4044                                                 u32 msr, int type)
4045 {
4046         int f = sizeof(unsigned long);
4047
4048         if (!cpu_has_vmx_msr_bitmap())
4049                 return;
4050
4051         /*
4052          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4053          * have the write-low and read-high bitmap offsets the wrong way round.
4054          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4055          */
4056         if (msr <= 0x1fff) {
4057                 if (type & MSR_TYPE_R)
4058                         /* read-low */
4059                         __set_bit(msr, msr_bitmap + 0x000 / f);
4060
4061                 if (type & MSR_TYPE_W)
4062                         /* write-low */
4063                         __set_bit(msr, msr_bitmap + 0x800 / f);
4064
4065         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4066                 msr &= 0x1fff;
4067                 if (type & MSR_TYPE_R)
4068                         /* read-high */
4069                         __set_bit(msr, msr_bitmap + 0x400 / f);
4070
4071                 if (type & MSR_TYPE_W)
4072                         /* write-high */
4073                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4074
4075         }
4076 }
4077
4078 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4079 {
4080         if (!longmode_only)
4081                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4082                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4083         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4084                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4085 }
4086
4087 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4088 {
4089         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4090                         msr, MSR_TYPE_R);
4091         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4092                         msr, MSR_TYPE_R);
4093 }
4094
4095 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4096 {
4097         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4098                         msr, MSR_TYPE_R);
4099         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4100                         msr, MSR_TYPE_R);
4101 }
4102
4103 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4104 {
4105         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4106                         msr, MSR_TYPE_W);
4107         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4108                         msr, MSR_TYPE_W);
4109 }
4110
4111 static int vmx_vm_has_apicv(struct kvm *kvm)
4112 {
4113         return enable_apicv && irqchip_in_kernel(kvm);
4114 }
4115
4116 /*
4117  * Send interrupt to vcpu via posted interrupt way.
4118  * 1. If target vcpu is running(non-root mode), send posted interrupt
4119  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4120  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4121  * interrupt from PIR in next vmentry.
4122  */
4123 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4124 {
4125         struct vcpu_vmx *vmx = to_vmx(vcpu);
4126         int r;
4127
4128         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4129                 return;
4130
4131         r = pi_test_and_set_on(&vmx->pi_desc);
4132         kvm_make_request(KVM_REQ_EVENT, vcpu);
4133 #ifdef CONFIG_SMP
4134         if (!r && (vcpu->mode == IN_GUEST_MODE))
4135                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4136                                 POSTED_INTR_VECTOR);
4137         else
4138 #endif
4139                 kvm_vcpu_kick(vcpu);
4140 }
4141
4142 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4143 {
4144         struct vcpu_vmx *vmx = to_vmx(vcpu);
4145
4146         if (!pi_test_and_clear_on(&vmx->pi_desc))
4147                 return;
4148
4149         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4150 }
4151
4152 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4153 {
4154         return;
4155 }
4156
4157 /*
4158  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4159  * will not change in the lifetime of the guest.
4160  * Note that host-state that does change is set elsewhere. E.g., host-state
4161  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4162  */
4163 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4164 {
4165         u32 low32, high32;
4166         unsigned long tmpl;
4167         struct desc_ptr dt;
4168
4169         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4170         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4171         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4172
4173         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4174 #ifdef CONFIG_X86_64
4175         /*
4176          * Load null selectors, so we can avoid reloading them in
4177          * __vmx_load_host_state(), in case userspace uses the null selectors
4178          * too (the expected case).
4179          */
4180         vmcs_write16(HOST_DS_SELECTOR, 0);
4181         vmcs_write16(HOST_ES_SELECTOR, 0);
4182 #else
4183         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4184         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4185 #endif
4186         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4187         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4188
4189         native_store_idt(&dt);
4190         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4191         vmx->host_idt_base = dt.address;
4192
4193         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4194
4195         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4196         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4197         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4198         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4199
4200         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4201                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4202                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4203         }
4204 }
4205
4206 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4207 {
4208         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4209         if (enable_ept)
4210                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4211         if (is_guest_mode(&vmx->vcpu))
4212                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4213                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4214         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4215 }
4216
4217 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4218 {
4219         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4220
4221         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4222                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4223         return pin_based_exec_ctrl;
4224 }
4225
4226 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4227 {
4228         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4229         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4230                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4231 #ifdef CONFIG_X86_64
4232                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4233                                 CPU_BASED_CR8_LOAD_EXITING;
4234 #endif
4235         }
4236         if (!enable_ept)
4237                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4238                                 CPU_BASED_CR3_LOAD_EXITING  |
4239                                 CPU_BASED_INVLPG_EXITING;
4240         return exec_control;
4241 }
4242
4243 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4244 {
4245         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4246         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4247                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4248         if (vmx->vpid == 0)
4249                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4250         if (!enable_ept) {
4251                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4252                 enable_unrestricted_guest = 0;
4253                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4254                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4255         }
4256         if (!enable_unrestricted_guest)
4257                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4258         if (!ple_gap)
4259                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4260         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4261                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4262                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4263         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4264         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4265            (handle_vmptrld).
4266            We can NOT enable shadow_vmcs here because we don't have yet
4267            a current VMCS12
4268         */
4269         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4270         return exec_control;
4271 }
4272
4273 static void ept_set_mmio_spte_mask(void)
4274 {
4275         /*
4276          * EPT Misconfigurations can be generated if the value of bits 2:0
4277          * of an EPT paging-structure entry is 110b (write/execute).
4278          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4279          * spte.
4280          */
4281         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4282 }
4283
4284 /*
4285  * Sets up the vmcs for emulated real mode.
4286  */
4287 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4288 {
4289 #ifdef CONFIG_X86_64
4290         unsigned long a;
4291 #endif
4292         int i;
4293
4294         /* I/O */
4295         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4296         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4297
4298         if (enable_shadow_vmcs) {
4299                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4300                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4301         }
4302         if (cpu_has_vmx_msr_bitmap())
4303                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4304
4305         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4306
4307         /* Control */
4308         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4309
4310         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4311
4312         if (cpu_has_secondary_exec_ctrls()) {
4313                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4314                                 vmx_secondary_exec_control(vmx));
4315         }
4316
4317         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4318                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4319                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4320                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4321                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4322
4323                 vmcs_write16(GUEST_INTR_STATUS, 0);
4324
4325                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4326                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4327         }
4328
4329         if (ple_gap) {
4330                 vmcs_write32(PLE_GAP, ple_gap);
4331                 vmcs_write32(PLE_WINDOW, ple_window);
4332         }
4333
4334         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4335         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4336         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4337
4338         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4339         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4340         vmx_set_constant_host_state(vmx);
4341 #ifdef CONFIG_X86_64
4342         rdmsrl(MSR_FS_BASE, a);
4343         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4344         rdmsrl(MSR_GS_BASE, a);
4345         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4346 #else
4347         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4348         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4349 #endif
4350
4351         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4352         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4353         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4354         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4355         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4356
4357         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4358                 u32 msr_low, msr_high;
4359                 u64 host_pat;
4360                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4361                 host_pat = msr_low | ((u64) msr_high << 32);
4362                 /* Write the default value follow host pat */
4363                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4364                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4365                 vmx->vcpu.arch.pat = host_pat;
4366         }
4367
4368         for (i = 0; i < NR_VMX_MSR; ++i) {
4369                 u32 index = vmx_msr_index[i];
4370                 u32 data_low, data_high;
4371                 int j = vmx->nmsrs;
4372
4373                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4374                         continue;
4375                 if (wrmsr_safe(index, data_low, data_high) < 0)
4376                         continue;
4377                 vmx->guest_msrs[j].index = i;
4378                 vmx->guest_msrs[j].data = 0;
4379                 vmx->guest_msrs[j].mask = -1ull;
4380                 ++vmx->nmsrs;
4381         }
4382
4383
4384         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4385
4386         /* 22.2.1, 20.8.1 */
4387         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4388
4389         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4390         set_cr4_guest_host_mask(vmx);
4391
4392         return 0;
4393 }
4394
4395 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4396 {
4397         struct vcpu_vmx *vmx = to_vmx(vcpu);
4398         struct msr_data apic_base_msr;
4399
4400         vmx->rmode.vm86_active = 0;
4401
4402         vmx->soft_vnmi_blocked = 0;
4403
4404         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4405         kvm_set_cr8(&vmx->vcpu, 0);
4406         apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4407         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4408                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4409         apic_base_msr.host_initiated = true;
4410         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4411
4412         vmx_segment_cache_clear(vmx);
4413
4414         seg_setup(VCPU_SREG_CS);
4415         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4416         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4417
4418         seg_setup(VCPU_SREG_DS);
4419         seg_setup(VCPU_SREG_ES);
4420         seg_setup(VCPU_SREG_FS);
4421         seg_setup(VCPU_SREG_GS);
4422         seg_setup(VCPU_SREG_SS);
4423
4424         vmcs_write16(GUEST_TR_SELECTOR, 0);
4425         vmcs_writel(GUEST_TR_BASE, 0);
4426         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4427         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4428
4429         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4430         vmcs_writel(GUEST_LDTR_BASE, 0);
4431         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4432         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4433
4434         vmcs_write32(GUEST_SYSENTER_CS, 0);
4435         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4436         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4437
4438         vmcs_writel(GUEST_RFLAGS, 0x02);
4439         kvm_rip_write(vcpu, 0xfff0);
4440
4441         vmcs_writel(GUEST_GDTR_BASE, 0);
4442         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4443
4444         vmcs_writel(GUEST_IDTR_BASE, 0);
4445         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4446
4447         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4448         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4449         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4450
4451         /* Special registers */
4452         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4453
4454         setup_msrs(vmx);
4455
4456         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4457
4458         if (cpu_has_vmx_tpr_shadow()) {
4459                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4460                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4461                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4462                                      __pa(vmx->vcpu.arch.apic->regs));
4463                 vmcs_write32(TPR_THRESHOLD, 0);
4464         }
4465
4466         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4467                 vmcs_write64(APIC_ACCESS_ADDR,
4468                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4469
4470         if (vmx_vm_has_apicv(vcpu->kvm))
4471                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4472
4473         if (vmx->vpid != 0)
4474                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4475
4476         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4477         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4478         vmx_set_cr4(&vmx->vcpu, 0);
4479         vmx_set_efer(&vmx->vcpu, 0);
4480         vmx_fpu_activate(&vmx->vcpu);
4481         update_exception_bitmap(&vmx->vcpu);
4482
4483         vpid_sync_context(vmx);
4484 }
4485
4486 /*
4487  * In nested virtualization, check if L1 asked to exit on external interrupts.
4488  * For most existing hypervisors, this will always return true.
4489  */
4490 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4491 {
4492         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4493                 PIN_BASED_EXT_INTR_MASK;
4494 }
4495
4496 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4497 {
4498         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4499                 PIN_BASED_NMI_EXITING;
4500 }
4501
4502 static int enable_irq_window(struct kvm_vcpu *vcpu)
4503 {
4504         u32 cpu_based_vm_exec_control;
4505
4506         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
4507                 /*
4508                  * We get here if vmx_interrupt_allowed() said we can't
4509                  * inject to L1 now because L2 must run. The caller will have
4510                  * to make L2 exit right after entry, so we can inject to L1
4511                  * more promptly.
4512                  */
4513                 return -EBUSY;
4514
4515         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4516         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4517         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4518         return 0;
4519 }
4520
4521 static int enable_nmi_window(struct kvm_vcpu *vcpu)
4522 {
4523         u32 cpu_based_vm_exec_control;
4524
4525         if (!cpu_has_virtual_nmis())
4526                 return enable_irq_window(vcpu);
4527
4528         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4529                 return enable_irq_window(vcpu);
4530
4531         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4532         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4533         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4534         return 0;
4535 }
4536
4537 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4538 {
4539         struct vcpu_vmx *vmx = to_vmx(vcpu);
4540         uint32_t intr;
4541         int irq = vcpu->arch.interrupt.nr;
4542
4543         trace_kvm_inj_virq(irq);
4544
4545         ++vcpu->stat.irq_injections;
4546         if (vmx->rmode.vm86_active) {
4547                 int inc_eip = 0;
4548                 if (vcpu->arch.interrupt.soft)
4549                         inc_eip = vcpu->arch.event_exit_inst_len;
4550                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4551                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4552                 return;
4553         }
4554         intr = irq | INTR_INFO_VALID_MASK;
4555         if (vcpu->arch.interrupt.soft) {
4556                 intr |= INTR_TYPE_SOFT_INTR;
4557                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4558                              vmx->vcpu.arch.event_exit_inst_len);
4559         } else
4560                 intr |= INTR_TYPE_EXT_INTR;
4561         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4562 }
4563
4564 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4565 {
4566         struct vcpu_vmx *vmx = to_vmx(vcpu);
4567
4568         if (is_guest_mode(vcpu))
4569                 return;
4570
4571         if (!cpu_has_virtual_nmis()) {
4572                 /*
4573                  * Tracking the NMI-blocked state in software is built upon
4574                  * finding the next open IRQ window. This, in turn, depends on
4575                  * well-behaving guests: They have to keep IRQs disabled at
4576                  * least as long as the NMI handler runs. Otherwise we may
4577                  * cause NMI nesting, maybe breaking the guest. But as this is
4578                  * highly unlikely, we can live with the residual risk.
4579                  */
4580                 vmx->soft_vnmi_blocked = 1;
4581                 vmx->vnmi_blocked_time = 0;
4582         }
4583
4584         ++vcpu->stat.nmi_injections;
4585         vmx->nmi_known_unmasked = false;
4586         if (vmx->rmode.vm86_active) {
4587                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4588                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4589                 return;
4590         }
4591         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4592                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4593 }
4594
4595 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4596 {
4597         if (!cpu_has_virtual_nmis())
4598                 return to_vmx(vcpu)->soft_vnmi_blocked;
4599         if (to_vmx(vcpu)->nmi_known_unmasked)
4600                 return false;
4601         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4602 }
4603
4604 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4605 {
4606         struct vcpu_vmx *vmx = to_vmx(vcpu);
4607
4608         if (!cpu_has_virtual_nmis()) {
4609                 if (vmx->soft_vnmi_blocked != masked) {
4610                         vmx->soft_vnmi_blocked = masked;
4611                         vmx->vnmi_blocked_time = 0;
4612                 }
4613         } else {
4614                 vmx->nmi_known_unmasked = !masked;
4615                 if (masked)
4616                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4617                                       GUEST_INTR_STATE_NMI);
4618                 else
4619                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4620                                         GUEST_INTR_STATE_NMI);
4621         }
4622 }
4623
4624 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4625 {
4626         if (is_guest_mode(vcpu)) {
4627                 if (to_vmx(vcpu)->nested.nested_run_pending)
4628                         return 0;
4629                 if (nested_exit_on_nmi(vcpu)) {
4630                         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
4631                                           NMI_VECTOR | INTR_TYPE_NMI_INTR |
4632                                           INTR_INFO_VALID_MASK, 0);
4633                         /*
4634                          * The NMI-triggered VM exit counts as injection:
4635                          * clear this one and block further NMIs.
4636                          */
4637                         vcpu->arch.nmi_pending = 0;
4638                         vmx_set_nmi_mask(vcpu, true);
4639                         return 0;
4640                 }
4641         }
4642
4643         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4644                 return 0;
4645
4646         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4647                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4648                    | GUEST_INTR_STATE_NMI));
4649 }
4650
4651 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4652 {
4653         if (is_guest_mode(vcpu)) {
4654                 if (to_vmx(vcpu)->nested.nested_run_pending)
4655                         return 0;
4656                 if (nested_exit_on_intr(vcpu)) {
4657                         nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT,
4658                                           0, 0);
4659                         /*
4660                          * fall through to normal code, but now in L1, not L2
4661                          */
4662                 }
4663         }
4664
4665         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4666                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4667                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4668 }
4669
4670 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4671 {
4672         int ret;
4673         struct kvm_userspace_memory_region tss_mem = {
4674                 .slot = TSS_PRIVATE_MEMSLOT,
4675                 .guest_phys_addr = addr,
4676                 .memory_size = PAGE_SIZE * 3,
4677                 .flags = 0,
4678         };
4679
4680         ret = kvm_set_memory_region(kvm, &tss_mem);
4681         if (ret)
4682                 return ret;
4683         kvm->arch.tss_addr = addr;
4684         if (!init_rmode_tss(kvm))
4685                 return  -ENOMEM;
4686
4687         return 0;
4688 }
4689
4690 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4691 {
4692         switch (vec) {
4693         case BP_VECTOR:
4694                 /*
4695                  * Update instruction length as we may reinject the exception
4696                  * from user space while in guest debugging mode.
4697                  */
4698                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4699                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4700                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4701                         return false;
4702                 /* fall through */
4703         case DB_VECTOR:
4704                 if (vcpu->guest_debug &
4705                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4706                         return false;
4707                 /* fall through */
4708         case DE_VECTOR:
4709         case OF_VECTOR:
4710         case BR_VECTOR:
4711         case UD_VECTOR:
4712         case DF_VECTOR:
4713         case SS_VECTOR:
4714         case GP_VECTOR:
4715         case MF_VECTOR:
4716                 return true;
4717         break;
4718         }
4719         return false;
4720 }
4721
4722 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4723                                   int vec, u32 err_code)
4724 {
4725         /*
4726          * Instruction with address size override prefix opcode 0x67
4727          * Cause the #SS fault with 0 error code in VM86 mode.
4728          */
4729         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4730                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4731                         if (vcpu->arch.halt_request) {
4732                                 vcpu->arch.halt_request = 0;
4733                                 return kvm_emulate_halt(vcpu);
4734                         }
4735                         return 1;
4736                 }
4737                 return 0;
4738         }
4739
4740         /*
4741          * Forward all other exceptions that are valid in real mode.
4742          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4743          *        the required debugging infrastructure rework.
4744          */
4745         kvm_queue_exception(vcpu, vec);
4746         return 1;
4747 }
4748
4749 /*
4750  * Trigger machine check on the host. We assume all the MSRs are already set up
4751  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4752  * We pass a fake environment to the machine check handler because we want
4753  * the guest to be always treated like user space, no matter what context
4754  * it used internally.
4755  */
4756 static void kvm_machine_check(void)
4757 {
4758 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4759         struct pt_regs regs = {
4760                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4761                 .flags = X86_EFLAGS_IF,
4762         };
4763
4764         do_machine_check(&regs, 0);
4765 #endif
4766 }
4767
4768 static int handle_machine_check(struct kvm_vcpu *vcpu)
4769 {
4770         /* already handled by vcpu_run */
4771         return 1;
4772 }
4773
4774 static int handle_exception(struct kvm_vcpu *vcpu)
4775 {
4776         struct vcpu_vmx *vmx = to_vmx(vcpu);
4777         struct kvm_run *kvm_run = vcpu->run;
4778         u32 intr_info, ex_no, error_code;
4779         unsigned long cr2, rip, dr6;
4780         u32 vect_info;
4781         enum emulation_result er;
4782
4783         vect_info = vmx->idt_vectoring_info;
4784         intr_info = vmx->exit_intr_info;
4785
4786         if (is_machine_check(intr_info))
4787                 return handle_machine_check(vcpu);
4788
4789         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4790                 return 1;  /* already handled by vmx_vcpu_run() */
4791
4792         if (is_no_device(intr_info)) {
4793                 vmx_fpu_activate(vcpu);
4794                 return 1;
4795         }
4796
4797         if (is_invalid_opcode(intr_info)) {
4798                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4799                 if (er != EMULATE_DONE)
4800                         kvm_queue_exception(vcpu, UD_VECTOR);
4801                 return 1;
4802         }
4803
4804         error_code = 0;
4805         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4806                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4807
4808         /*
4809          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4810          * MMIO, it is better to report an internal error.
4811          * See the comments in vmx_handle_exit.
4812          */
4813         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4814             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4815                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4816                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4817                 vcpu->run->internal.ndata = 2;
4818                 vcpu->run->internal.data[0] = vect_info;
4819                 vcpu->run->internal.data[1] = intr_info;
4820                 return 0;
4821         }
4822
4823         if (is_page_fault(intr_info)) {
4824                 /* EPT won't cause page fault directly */
4825                 BUG_ON(enable_ept);
4826                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4827                 trace_kvm_page_fault(cr2, error_code);
4828
4829                 if (kvm_event_needs_reinjection(vcpu))
4830                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4831                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4832         }
4833
4834         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4835
4836         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4837                 return handle_rmode_exception(vcpu, ex_no, error_code);
4838
4839         switch (ex_no) {
4840         case DB_VECTOR:
4841                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4842                 if (!(vcpu->guest_debug &
4843                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4844                         vcpu->arch.dr6 &= ~15;
4845                         vcpu->arch.dr6 |= dr6;
4846                         kvm_queue_exception(vcpu, DB_VECTOR);
4847                         return 1;
4848                 }
4849                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4850                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4851                 /* fall through */
4852         case BP_VECTOR:
4853                 /*
4854                  * Update instruction length as we may reinject #BP from
4855                  * user space while in guest debugging mode. Reading it for
4856                  * #DB as well causes no harm, it is not used in that case.
4857                  */
4858                 vmx->vcpu.arch.event_exit_inst_len =
4859                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4860                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4861                 rip = kvm_rip_read(vcpu);
4862                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4863                 kvm_run->debug.arch.exception = ex_no;
4864                 break;
4865         default:
4866                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4867                 kvm_run->ex.exception = ex_no;
4868                 kvm_run->ex.error_code = error_code;
4869                 break;
4870         }
4871         return 0;
4872 }
4873
4874 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4875 {
4876         ++vcpu->stat.irq_exits;
4877         return 1;
4878 }
4879
4880 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4881 {
4882         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4883         return 0;
4884 }
4885
4886 static int handle_io(struct kvm_vcpu *vcpu)
4887 {
4888         unsigned long exit_qualification;
4889         int size, in, string;
4890         unsigned port;
4891
4892         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4893         string = (exit_qualification & 16) != 0;
4894         in = (exit_qualification & 8) != 0;
4895
4896         ++vcpu->stat.io_exits;
4897
4898         if (string || in)
4899                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4900
4901         port = exit_qualification >> 16;
4902         size = (exit_qualification & 7) + 1;
4903         skip_emulated_instruction(vcpu);
4904
4905         return kvm_fast_pio_out(vcpu, size, port);
4906 }
4907
4908 static void
4909 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4910 {
4911         /*
4912          * Patch in the VMCALL instruction:
4913          */
4914         hypercall[0] = 0x0f;
4915         hypercall[1] = 0x01;
4916         hypercall[2] = 0xc1;
4917 }
4918
4919 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4920 {
4921         unsigned long always_on = VMXON_CR0_ALWAYSON;
4922
4923         if (nested_vmx_secondary_ctls_high &
4924                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4925             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4926                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4927         return (val & always_on) == always_on;
4928 }
4929
4930 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4931 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4932 {
4933         if (is_guest_mode(vcpu)) {
4934                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4935                 unsigned long orig_val = val;
4936
4937                 /*
4938                  * We get here when L2 changed cr0 in a way that did not change
4939                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4940                  * but did change L0 shadowed bits. So we first calculate the
4941                  * effective cr0 value that L1 would like to write into the
4942                  * hardware. It consists of the L2-owned bits from the new
4943                  * value combined with the L1-owned bits from L1's guest_cr0.
4944                  */
4945                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4946                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4947
4948                 if (!nested_cr0_valid(vmcs12, val))
4949                         return 1;
4950
4951                 if (kvm_set_cr0(vcpu, val))
4952                         return 1;
4953                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4954                 return 0;
4955         } else {
4956                 if (to_vmx(vcpu)->nested.vmxon &&
4957                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4958                         return 1;
4959                 return kvm_set_cr0(vcpu, val);
4960         }
4961 }
4962
4963 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4964 {
4965         if (is_guest_mode(vcpu)) {
4966                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4967                 unsigned long orig_val = val;
4968
4969                 /* analogously to handle_set_cr0 */
4970                 val = (val & ~vmcs12->cr4_guest_host_mask) |
4971                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4972                 if (kvm_set_cr4(vcpu, val))
4973                         return 1;
4974                 vmcs_writel(CR4_READ_SHADOW, orig_val);
4975                 return 0;
4976         } else
4977                 return kvm_set_cr4(vcpu, val);
4978 }
4979
4980 /* called to set cr0 as approriate for clts instruction exit. */
4981 static void handle_clts(struct kvm_vcpu *vcpu)
4982 {
4983         if (is_guest_mode(vcpu)) {
4984                 /*
4985                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4986                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4987                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4988                  */
4989                 vmcs_writel(CR0_READ_SHADOW,
4990                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4991                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4992         } else
4993                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4994 }
4995
4996 static int handle_cr(struct kvm_vcpu *vcpu)
4997 {
4998         unsigned long exit_qualification, val;
4999         int cr;
5000         int reg;
5001         int err;
5002
5003         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5004         cr = exit_qualification & 15;
5005         reg = (exit_qualification >> 8) & 15;
5006         switch ((exit_qualification >> 4) & 3) {
5007         case 0: /* mov to cr */
5008                 val = kvm_register_read(vcpu, reg);
5009                 trace_kvm_cr_write(cr, val);
5010                 switch (cr) {
5011                 case 0:
5012                         err = handle_set_cr0(vcpu, val);
5013                         kvm_complete_insn_gp(vcpu, err);
5014                         return 1;
5015                 case 3:
5016                         err = kvm_set_cr3(vcpu, val);
5017                         kvm_complete_insn_gp(vcpu, err);
5018                         return 1;
5019                 case 4:
5020                         err = handle_set_cr4(vcpu, val);
5021                         kvm_complete_insn_gp(vcpu, err);
5022                         return 1;
5023                 case 8: {
5024                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5025                                 u8 cr8 = kvm_register_read(vcpu, reg);
5026                                 err = kvm_set_cr8(vcpu, cr8);
5027                                 kvm_complete_insn_gp(vcpu, err);
5028                                 if (irqchip_in_kernel(vcpu->kvm))
5029                                         return 1;
5030                                 if (cr8_prev <= cr8)
5031                                         return 1;
5032                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5033                                 return 0;
5034                         }
5035                 }
5036                 break;
5037         case 2: /* clts */
5038                 handle_clts(vcpu);
5039                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5040                 skip_emulated_instruction(vcpu);
5041                 vmx_fpu_activate(vcpu);
5042                 return 1;
5043         case 1: /*mov from cr*/
5044                 switch (cr) {
5045                 case 3:
5046                         val = kvm_read_cr3(vcpu);
5047                         kvm_register_write(vcpu, reg, val);
5048                         trace_kvm_cr_read(cr, val);
5049                         skip_emulated_instruction(vcpu);
5050                         return 1;
5051                 case 8:
5052                         val = kvm_get_cr8(vcpu);
5053                         kvm_register_write(vcpu, reg, val);
5054                         trace_kvm_cr_read(cr, val);
5055                         skip_emulated_instruction(vcpu);
5056                         return 1;
5057                 }
5058                 break;
5059         case 3: /* lmsw */
5060                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5061                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5062                 kvm_lmsw(vcpu, val);
5063
5064                 skip_emulated_instruction(vcpu);
5065                 return 1;
5066         default:
5067                 break;
5068         }
5069         vcpu->run->exit_reason = 0;
5070         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5071                (int)(exit_qualification >> 4) & 3, cr);
5072         return 0;
5073 }
5074
5075 static int handle_dr(struct kvm_vcpu *vcpu)
5076 {
5077         unsigned long exit_qualification;
5078         int dr, reg;
5079
5080         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5081         if (!kvm_require_cpl(vcpu, 0))
5082                 return 1;
5083         dr = vmcs_readl(GUEST_DR7);
5084         if (dr & DR7_GD) {
5085                 /*
5086                  * As the vm-exit takes precedence over the debug trap, we
5087                  * need to emulate the latter, either for the host or the
5088                  * guest debugging itself.
5089                  */
5090                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5091                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5092                         vcpu->run->debug.arch.dr7 = dr;
5093                         vcpu->run->debug.arch.pc =
5094                                 vmcs_readl(GUEST_CS_BASE) +
5095                                 vmcs_readl(GUEST_RIP);
5096                         vcpu->run->debug.arch.exception = DB_VECTOR;
5097                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5098                         return 0;
5099                 } else {
5100                         vcpu->arch.dr7 &= ~DR7_GD;
5101                         vcpu->arch.dr6 |= DR6_BD;
5102                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5103                         kvm_queue_exception(vcpu, DB_VECTOR);
5104                         return 1;
5105                 }
5106         }
5107
5108         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5109         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5110         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5111         if (exit_qualification & TYPE_MOV_FROM_DR) {
5112                 unsigned long val;
5113
5114                 if (kvm_get_dr(vcpu, dr, &val))
5115                         return 1;
5116                 kvm_register_write(vcpu, reg, val);
5117         } else
5118                 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5119                         return 1;
5120
5121         skip_emulated_instruction(vcpu);
5122         return 1;
5123 }
5124
5125 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5126 {
5127         return vcpu->arch.dr6;
5128 }
5129
5130 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5131 {
5132 }
5133
5134 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5135 {
5136         vmcs_writel(GUEST_DR7, val);
5137 }
5138
5139 static int handle_cpuid(struct kvm_vcpu *vcpu)
5140 {
5141         kvm_emulate_cpuid(vcpu);
5142         return 1;
5143 }
5144
5145 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5146 {
5147         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5148         u64 data;
5149
5150         if (vmx_get_msr(vcpu, ecx, &data)) {
5151                 trace_kvm_msr_read_ex(ecx);
5152                 kvm_inject_gp(vcpu, 0);
5153                 return 1;
5154         }
5155
5156         trace_kvm_msr_read(ecx, data);
5157
5158         /* FIXME: handling of bits 32:63 of rax, rdx */
5159         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5160         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5161         skip_emulated_instruction(vcpu);
5162         return 1;
5163 }
5164
5165 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5166 {
5167         struct msr_data msr;
5168         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5169         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5170                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5171
5172         msr.data = data;
5173         msr.index = ecx;
5174         msr.host_initiated = false;
5175         if (kvm_set_msr(vcpu, &msr) != 0) {
5176                 trace_kvm_msr_write_ex(ecx, data);
5177                 kvm_inject_gp(vcpu, 0);
5178                 return 1;
5179         }
5180
5181         trace_kvm_msr_write(ecx, data);
5182         skip_emulated_instruction(vcpu);
5183         return 1;
5184 }
5185
5186 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5187 {
5188         kvm_make_request(KVM_REQ_EVENT, vcpu);
5189         return 1;
5190 }
5191
5192 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5193 {
5194         u32 cpu_based_vm_exec_control;
5195
5196         /* clear pending irq */
5197         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5198         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5199         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5200
5201         kvm_make_request(KVM_REQ_EVENT, vcpu);
5202
5203         ++vcpu->stat.irq_window_exits;
5204
5205         /*
5206          * If the user space waits to inject interrupts, exit as soon as
5207          * possible
5208          */
5209         if (!irqchip_in_kernel(vcpu->kvm) &&
5210             vcpu->run->request_interrupt_window &&
5211             !kvm_cpu_has_interrupt(vcpu)) {
5212                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5213                 return 0;
5214         }
5215         return 1;
5216 }
5217
5218 static int handle_halt(struct kvm_vcpu *vcpu)
5219 {
5220         skip_emulated_instruction(vcpu);
5221         return kvm_emulate_halt(vcpu);
5222 }
5223
5224 static int handle_vmcall(struct kvm_vcpu *vcpu)
5225 {
5226         skip_emulated_instruction(vcpu);
5227         kvm_emulate_hypercall(vcpu);
5228         return 1;
5229 }
5230
5231 static int handle_invd(struct kvm_vcpu *vcpu)
5232 {
5233         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5234 }
5235
5236 static int handle_invlpg(struct kvm_vcpu *vcpu)
5237 {
5238         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5239
5240         kvm_mmu_invlpg(vcpu, exit_qualification);
5241         skip_emulated_instruction(vcpu);
5242         return 1;
5243 }
5244
5245 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5246 {
5247         int err;
5248
5249         err = kvm_rdpmc(vcpu);
5250         kvm_complete_insn_gp(vcpu, err);
5251
5252         return 1;
5253 }
5254
5255 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5256 {
5257         skip_emulated_instruction(vcpu);
5258         kvm_emulate_wbinvd(vcpu);
5259         return 1;
5260 }
5261
5262 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5263 {
5264         u64 new_bv = kvm_read_edx_eax(vcpu);
5265         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5266
5267         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5268                 skip_emulated_instruction(vcpu);
5269         return 1;
5270 }
5271
5272 static int handle_apic_access(struct kvm_vcpu *vcpu)
5273 {
5274         if (likely(fasteoi)) {
5275                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5276                 int access_type, offset;
5277
5278                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5279                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5280                 /*
5281                  * Sane guest uses MOV to write EOI, with written value
5282                  * not cared. So make a short-circuit here by avoiding
5283                  * heavy instruction emulation.
5284                  */
5285                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5286                     (offset == APIC_EOI)) {
5287                         kvm_lapic_set_eoi(vcpu);
5288                         skip_emulated_instruction(vcpu);
5289                         return 1;
5290                 }
5291         }
5292         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5293 }
5294
5295 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5296 {
5297         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5298         int vector = exit_qualification & 0xff;
5299
5300         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5301         kvm_apic_set_eoi_accelerated(vcpu, vector);
5302         return 1;
5303 }
5304
5305 static int handle_apic_write(struct kvm_vcpu *vcpu)
5306 {
5307         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5308         u32 offset = exit_qualification & 0xfff;
5309
5310         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5311         kvm_apic_write_nodecode(vcpu, offset);
5312         return 1;
5313 }
5314
5315 static int handle_task_switch(struct kvm_vcpu *vcpu)
5316 {
5317         struct vcpu_vmx *vmx = to_vmx(vcpu);
5318         unsigned long exit_qualification;
5319         bool has_error_code = false;
5320         u32 error_code = 0;
5321         u16 tss_selector;
5322         int reason, type, idt_v, idt_index;
5323
5324         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5325         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5326         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5327
5328         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5329
5330         reason = (u32)exit_qualification >> 30;
5331         if (reason == TASK_SWITCH_GATE && idt_v) {
5332                 switch (type) {
5333                 case INTR_TYPE_NMI_INTR:
5334                         vcpu->arch.nmi_injected = false;
5335                         vmx_set_nmi_mask(vcpu, true);
5336                         break;
5337                 case INTR_TYPE_EXT_INTR:
5338                 case INTR_TYPE_SOFT_INTR:
5339                         kvm_clear_interrupt_queue(vcpu);
5340                         break;
5341                 case INTR_TYPE_HARD_EXCEPTION:
5342                         if (vmx->idt_vectoring_info &
5343                             VECTORING_INFO_DELIVER_CODE_MASK) {
5344                                 has_error_code = true;
5345                                 error_code =
5346                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5347                         }
5348                         /* fall through */
5349                 case INTR_TYPE_SOFT_EXCEPTION:
5350                         kvm_clear_exception_queue(vcpu);
5351                         break;
5352                 default:
5353                         break;
5354                 }
5355         }
5356         tss_selector = exit_qualification;
5357
5358         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5359                        type != INTR_TYPE_EXT_INTR &&
5360                        type != INTR_TYPE_NMI_INTR))
5361                 skip_emulated_instruction(vcpu);
5362
5363         if (kvm_task_switch(vcpu, tss_selector,
5364                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5365                             has_error_code, error_code) == EMULATE_FAIL) {
5366                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5367                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5368                 vcpu->run->internal.ndata = 0;
5369                 return 0;
5370         }
5371
5372         /* clear all local breakpoint enable flags */
5373         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5374
5375         /*
5376          * TODO: What about debug traps on tss switch?
5377          *       Are we supposed to inject them and update dr6?
5378          */
5379
5380         return 1;
5381 }
5382
5383 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5384 {
5385         unsigned long exit_qualification;
5386         gpa_t gpa;
5387         u32 error_code;
5388         int gla_validity;
5389
5390         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5391
5392         gla_validity = (exit_qualification >> 7) & 0x3;
5393         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5394                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5395                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5396                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5397                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5398                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5399                         (long unsigned int)exit_qualification);
5400                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5401                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5402                 return 0;
5403         }
5404
5405         /*
5406          * EPT violation happened while executing iret from NMI,
5407          * "blocked by NMI" bit has to be set before next VM entry.
5408          * There are errata that may cause this bit to not be set:
5409          * AAK134, BY25.
5410          */
5411         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5412                         cpu_has_virtual_nmis() &&
5413                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5414                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5415
5416         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5417         trace_kvm_page_fault(gpa, exit_qualification);
5418
5419         /* It is a write fault? */
5420         error_code = exit_qualification & (1U << 1);
5421         /* It is a fetch fault? */
5422         error_code |= (exit_qualification & (1U << 2)) << 2;
5423         /* ept page table is present? */
5424         error_code |= (exit_qualification >> 3) & 0x1;
5425
5426         vcpu->arch.exit_qualification = exit_qualification;
5427
5428         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5429 }
5430
5431 static u64 ept_rsvd_mask(u64 spte, int level)
5432 {
5433         int i;
5434         u64 mask = 0;
5435
5436         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5437                 mask |= (1ULL << i);
5438
5439         if (level > 2)
5440                 /* bits 7:3 reserved */
5441                 mask |= 0xf8;
5442         else if (level == 2) {
5443                 if (spte & (1ULL << 7))
5444                         /* 2MB ref, bits 20:12 reserved */
5445                         mask |= 0x1ff000;
5446                 else
5447                         /* bits 6:3 reserved */
5448                         mask |= 0x78;
5449         }
5450
5451         return mask;
5452 }
5453
5454 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5455                                        int level)
5456 {
5457         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5458
5459         /* 010b (write-only) */
5460         WARN_ON((spte & 0x7) == 0x2);
5461
5462         /* 110b (write/execute) */
5463         WARN_ON((spte & 0x7) == 0x6);
5464
5465         /* 100b (execute-only) and value not supported by logical processor */
5466         if (!cpu_has_vmx_ept_execute_only())
5467                 WARN_ON((spte & 0x7) == 0x4);
5468
5469         /* not 000b */
5470         if ((spte & 0x7)) {
5471                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5472
5473                 if (rsvd_bits != 0) {
5474                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5475                                          __func__, rsvd_bits);
5476                         WARN_ON(1);
5477                 }
5478
5479                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5480                         u64 ept_mem_type = (spte & 0x38) >> 3;
5481
5482                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5483                             ept_mem_type == 7) {
5484                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5485                                                 __func__, ept_mem_type);
5486                                 WARN_ON(1);
5487                         }
5488                 }
5489         }
5490 }
5491
5492 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5493 {
5494         u64 sptes[4];
5495         int nr_sptes, i, ret;
5496         gpa_t gpa;
5497
5498         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5499
5500         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5501         if (likely(ret == RET_MMIO_PF_EMULATE))
5502                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5503                                               EMULATE_DONE;
5504
5505         if (unlikely(ret == RET_MMIO_PF_INVALID))
5506                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5507
5508         if (unlikely(ret == RET_MMIO_PF_RETRY))
5509                 return 1;
5510
5511         /* It is the real ept misconfig */
5512         printk(KERN_ERR "EPT: Misconfiguration.\n");
5513         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5514
5515         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5516
5517         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5518                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5519
5520         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5521         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5522
5523         return 0;
5524 }
5525
5526 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5527 {
5528         u32 cpu_based_vm_exec_control;
5529
5530         /* clear pending NMI */
5531         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5532         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5533         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5534         ++vcpu->stat.nmi_window_exits;
5535         kvm_make_request(KVM_REQ_EVENT, vcpu);
5536
5537         return 1;
5538 }
5539
5540 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5541 {
5542         struct vcpu_vmx *vmx = to_vmx(vcpu);
5543         enum emulation_result err = EMULATE_DONE;
5544         int ret = 1;
5545         u32 cpu_exec_ctrl;
5546         bool intr_window_requested;
5547         unsigned count = 130;
5548
5549         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5550         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5551
5552         while (!guest_state_valid(vcpu) && count-- != 0) {
5553                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5554                         return handle_interrupt_window(&vmx->vcpu);
5555
5556                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5557                         return 1;
5558
5559                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5560
5561                 if (err == EMULATE_USER_EXIT) {
5562                         ++vcpu->stat.mmio_exits;
5563                         ret = 0;
5564                         goto out;
5565                 }
5566
5567                 if (err != EMULATE_DONE) {
5568                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5569                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5570                         vcpu->run->internal.ndata = 0;
5571                         return 0;
5572                 }
5573
5574                 if (vcpu->arch.halt_request) {
5575                         vcpu->arch.halt_request = 0;
5576                         ret = kvm_emulate_halt(vcpu);
5577                         goto out;
5578                 }
5579
5580                 if (signal_pending(current))
5581                         goto out;
5582                 if (need_resched())
5583                         schedule();
5584         }
5585
5586         vmx->emulation_required = emulation_required(vcpu);
5587 out:
5588         return ret;
5589 }
5590
5591 /*
5592  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5593  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5594  */
5595 static int handle_pause(struct kvm_vcpu *vcpu)
5596 {
5597         skip_emulated_instruction(vcpu);
5598         kvm_vcpu_on_spin(vcpu);
5599
5600         return 1;
5601 }
5602
5603 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5604 {
5605         kvm_queue_exception(vcpu, UD_VECTOR);
5606         return 1;
5607 }
5608
5609 /*
5610  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5611  * We could reuse a single VMCS for all the L2 guests, but we also want the
5612  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5613  * allows keeping them loaded on the processor, and in the future will allow
5614  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5615  * every entry if they never change.
5616  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5617  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5618  *
5619  * The following functions allocate and free a vmcs02 in this pool.
5620  */
5621
5622 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5623 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5624 {
5625         struct vmcs02_list *item;
5626         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5627                 if (item->vmptr == vmx->nested.current_vmptr) {
5628                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5629                         return &item->vmcs02;
5630                 }
5631
5632         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5633                 /* Recycle the least recently used VMCS. */
5634                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5635                         struct vmcs02_list, list);
5636                 item->vmptr = vmx->nested.current_vmptr;
5637                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5638                 return &item->vmcs02;
5639         }
5640
5641         /* Create a new VMCS */
5642         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5643         if (!item)
5644                 return NULL;
5645         item->vmcs02.vmcs = alloc_vmcs();
5646         if (!item->vmcs02.vmcs) {
5647                 kfree(item);
5648                 return NULL;
5649         }
5650         loaded_vmcs_init(&item->vmcs02);
5651         item->vmptr = vmx->nested.current_vmptr;
5652         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5653         vmx->nested.vmcs02_num++;
5654         return &item->vmcs02;
5655 }
5656
5657 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5658 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5659 {
5660         struct vmcs02_list *item;
5661         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5662                 if (item->vmptr == vmptr) {
5663                         free_loaded_vmcs(&item->vmcs02);
5664                         list_del(&item->list);
5665                         kfree(item);
5666                         vmx->nested.vmcs02_num--;
5667                         return;
5668                 }
5669 }
5670
5671 /*
5672  * Free all VMCSs saved for this vcpu, except the one pointed by
5673  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5674  * currently used, if running L2), and vmcs01 when running L2.
5675  */
5676 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5677 {
5678         struct vmcs02_list *item, *n;
5679         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5680                 if (vmx->loaded_vmcs != &item->vmcs02)
5681                         free_loaded_vmcs(&item->vmcs02);
5682                 list_del(&item->list);
5683                 kfree(item);
5684         }
5685         vmx->nested.vmcs02_num = 0;
5686
5687         if (vmx->loaded_vmcs != &vmx->vmcs01)
5688                 free_loaded_vmcs(&vmx->vmcs01);
5689 }
5690
5691 /*
5692  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5693  * set the success or error code of an emulated VMX instruction, as specified
5694  * by Vol 2B, VMX Instruction Reference, "Conventions".
5695  */
5696 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5697 {
5698         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5699                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5700                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5701 }
5702
5703 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5704 {
5705         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5706                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5707                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5708                         | X86_EFLAGS_CF);
5709 }
5710
5711 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5712                                         u32 vm_instruction_error)
5713 {
5714         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5715                 /*
5716                  * failValid writes the error number to the current VMCS, which
5717                  * can't be done there isn't a current VMCS.
5718                  */
5719                 nested_vmx_failInvalid(vcpu);
5720                 return;
5721         }
5722         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5723                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5724                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5725                         | X86_EFLAGS_ZF);
5726         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5727         /*
5728          * We don't need to force a shadow sync because
5729          * VM_INSTRUCTION_ERROR is not shadowed
5730          */
5731 }
5732
5733 /*
5734  * Emulate the VMXON instruction.
5735  * Currently, we just remember that VMX is active, and do not save or even
5736  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5737  * do not currently need to store anything in that guest-allocated memory
5738  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5739  * argument is different from the VMXON pointer (which the spec says they do).
5740  */
5741 static int handle_vmon(struct kvm_vcpu *vcpu)
5742 {
5743         struct kvm_segment cs;
5744         struct vcpu_vmx *vmx = to_vmx(vcpu);
5745         struct vmcs *shadow_vmcs;
5746         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5747                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
5748
5749         /* The Intel VMX Instruction Reference lists a bunch of bits that
5750          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5751          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5752          * Otherwise, we should fail with #UD. We test these now:
5753          */
5754         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5755             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5756             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5757                 kvm_queue_exception(vcpu, UD_VECTOR);
5758                 return 1;
5759         }
5760
5761         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5762         if (is_long_mode(vcpu) && !cs.l) {
5763                 kvm_queue_exception(vcpu, UD_VECTOR);
5764                 return 1;
5765         }
5766
5767         if (vmx_get_cpl(vcpu)) {
5768                 kvm_inject_gp(vcpu, 0);
5769                 return 1;
5770         }
5771         if (vmx->nested.vmxon) {
5772                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5773                 skip_emulated_instruction(vcpu);
5774                 return 1;
5775         }
5776
5777         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5778                         != VMXON_NEEDED_FEATURES) {
5779                 kvm_inject_gp(vcpu, 0);
5780                 return 1;
5781         }
5782
5783         if (enable_shadow_vmcs) {
5784                 shadow_vmcs = alloc_vmcs();
5785                 if (!shadow_vmcs)
5786                         return -ENOMEM;
5787                 /* mark vmcs as shadow */
5788                 shadow_vmcs->revision_id |= (1u << 31);
5789                 /* init shadow vmcs */
5790                 vmcs_clear(shadow_vmcs);
5791                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5792         }
5793
5794         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5795         vmx->nested.vmcs02_num = 0;
5796
5797         vmx->nested.vmxon = true;
5798
5799         skip_emulated_instruction(vcpu);
5800         nested_vmx_succeed(vcpu);
5801         return 1;
5802 }
5803
5804 /*
5805  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5806  * for running VMX instructions (except VMXON, whose prerequisites are
5807  * slightly different). It also specifies what exception to inject otherwise.
5808  */
5809 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5810 {
5811         struct kvm_segment cs;
5812         struct vcpu_vmx *vmx = to_vmx(vcpu);
5813
5814         if (!vmx->nested.vmxon) {
5815                 kvm_queue_exception(vcpu, UD_VECTOR);
5816                 return 0;
5817         }
5818
5819         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5820         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5821             (is_long_mode(vcpu) && !cs.l)) {
5822                 kvm_queue_exception(vcpu, UD_VECTOR);
5823                 return 0;
5824         }
5825
5826         if (vmx_get_cpl(vcpu)) {
5827                 kvm_inject_gp(vcpu, 0);
5828                 return 0;
5829         }
5830
5831         return 1;
5832 }
5833
5834 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5835 {
5836         u32 exec_control;
5837         if (enable_shadow_vmcs) {
5838                 if (vmx->nested.current_vmcs12 != NULL) {
5839                         /* copy to memory all shadowed fields in case
5840                            they were modified */
5841                         copy_shadow_to_vmcs12(vmx);
5842                         vmx->nested.sync_shadow_vmcs = false;
5843                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5844                         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5845                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5846                         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5847                 }
5848         }
5849         kunmap(vmx->nested.current_vmcs12_page);
5850         nested_release_page(vmx->nested.current_vmcs12_page);
5851 }
5852
5853 /*
5854  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5855  * just stops using VMX.
5856  */
5857 static void free_nested(struct vcpu_vmx *vmx)
5858 {
5859         if (!vmx->nested.vmxon)
5860                 return;
5861         vmx->nested.vmxon = false;
5862         if (vmx->nested.current_vmptr != -1ull) {
5863                 nested_release_vmcs12(vmx);
5864                 vmx->nested.current_vmptr = -1ull;
5865                 vmx->nested.current_vmcs12 = NULL;
5866         }
5867         if (enable_shadow_vmcs)
5868                 free_vmcs(vmx->nested.current_shadow_vmcs);
5869         /* Unpin physical memory we referred to in current vmcs02 */
5870         if (vmx->nested.apic_access_page) {
5871                 nested_release_page(vmx->nested.apic_access_page);
5872                 vmx->nested.apic_access_page = 0;
5873         }
5874
5875         nested_free_all_saved_vmcss(vmx);
5876 }
5877
5878 /* Emulate the VMXOFF instruction */
5879 static int handle_vmoff(struct kvm_vcpu *vcpu)
5880 {
5881         if (!nested_vmx_check_permission(vcpu))
5882                 return 1;
5883         free_nested(to_vmx(vcpu));
5884         skip_emulated_instruction(vcpu);
5885         nested_vmx_succeed(vcpu);
5886         return 1;
5887 }
5888
5889 /*
5890  * Decode the memory-address operand of a vmx instruction, as recorded on an
5891  * exit caused by such an instruction (run by a guest hypervisor).
5892  * On success, returns 0. When the operand is invalid, returns 1 and throws
5893  * #UD or #GP.
5894  */
5895 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5896                                  unsigned long exit_qualification,
5897                                  u32 vmx_instruction_info, gva_t *ret)
5898 {
5899         /*
5900          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5901          * Execution", on an exit, vmx_instruction_info holds most of the
5902          * addressing components of the operand. Only the displacement part
5903          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5904          * For how an actual address is calculated from all these components,
5905          * refer to Vol. 1, "Operand Addressing".
5906          */
5907         int  scaling = vmx_instruction_info & 3;
5908         int  addr_size = (vmx_instruction_info >> 7) & 7;
5909         bool is_reg = vmx_instruction_info & (1u << 10);
5910         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5911         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5912         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5913         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5914         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5915
5916         if (is_reg) {
5917                 kvm_queue_exception(vcpu, UD_VECTOR);
5918                 return 1;
5919         }
5920
5921         /* Addr = segment_base + offset */
5922         /* offset = base + [index * scale] + displacement */
5923         *ret = vmx_get_segment_base(vcpu, seg_reg);
5924         if (base_is_valid)
5925                 *ret += kvm_register_read(vcpu, base_reg);
5926         if (index_is_valid)
5927                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5928         *ret += exit_qualification; /* holds the displacement */
5929
5930         if (addr_size == 1) /* 32 bit */
5931                 *ret &= 0xffffffff;
5932
5933         /*
5934          * TODO: throw #GP (and return 1) in various cases that the VM*
5935          * instructions require it - e.g., offset beyond segment limit,
5936          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5937          * address, and so on. Currently these are not checked.
5938          */
5939         return 0;
5940 }
5941
5942 /* Emulate the VMCLEAR instruction */
5943 static int handle_vmclear(struct kvm_vcpu *vcpu)
5944 {
5945         struct vcpu_vmx *vmx = to_vmx(vcpu);
5946         gva_t gva;
5947         gpa_t vmptr;
5948         struct vmcs12 *vmcs12;
5949         struct page *page;
5950         struct x86_exception e;
5951
5952         if (!nested_vmx_check_permission(vcpu))
5953                 return 1;
5954
5955         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5956                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5957                 return 1;
5958
5959         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5960                                 sizeof(vmptr), &e)) {
5961                 kvm_inject_page_fault(vcpu, &e);
5962                 return 1;
5963         }
5964
5965         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5966                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5967                 skip_emulated_instruction(vcpu);
5968                 return 1;
5969         }
5970
5971         if (vmptr == vmx->nested.current_vmptr) {
5972                 nested_release_vmcs12(vmx);
5973                 vmx->nested.current_vmptr = -1ull;
5974                 vmx->nested.current_vmcs12 = NULL;
5975         }
5976
5977         page = nested_get_page(vcpu, vmptr);
5978         if (page == NULL) {
5979                 /*
5980                  * For accurate processor emulation, VMCLEAR beyond available
5981                  * physical memory should do nothing at all. However, it is
5982                  * possible that a nested vmx bug, not a guest hypervisor bug,
5983                  * resulted in this case, so let's shut down before doing any
5984                  * more damage:
5985                  */
5986                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5987                 return 1;
5988         }
5989         vmcs12 = kmap(page);
5990         vmcs12->launch_state = 0;
5991         kunmap(page);
5992         nested_release_page(page);
5993
5994         nested_free_vmcs02(vmx, vmptr);
5995
5996         skip_emulated_instruction(vcpu);
5997         nested_vmx_succeed(vcpu);
5998         return 1;
5999 }
6000
6001 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6002
6003 /* Emulate the VMLAUNCH instruction */
6004 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6005 {
6006         return nested_vmx_run(vcpu, true);
6007 }
6008
6009 /* Emulate the VMRESUME instruction */
6010 static int handle_vmresume(struct kvm_vcpu *vcpu)
6011 {
6012
6013         return nested_vmx_run(vcpu, false);
6014 }
6015
6016 enum vmcs_field_type {
6017         VMCS_FIELD_TYPE_U16 = 0,
6018         VMCS_FIELD_TYPE_U64 = 1,
6019         VMCS_FIELD_TYPE_U32 = 2,
6020         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6021 };
6022
6023 static inline int vmcs_field_type(unsigned long field)
6024 {
6025         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6026                 return VMCS_FIELD_TYPE_U32;
6027         return (field >> 13) & 0x3 ;
6028 }
6029
6030 static inline int vmcs_field_readonly(unsigned long field)
6031 {
6032         return (((field >> 10) & 0x3) == 1);
6033 }
6034
6035 /*
6036  * Read a vmcs12 field. Since these can have varying lengths and we return
6037  * one type, we chose the biggest type (u64) and zero-extend the return value
6038  * to that size. Note that the caller, handle_vmread, might need to use only
6039  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6040  * 64-bit fields are to be returned).
6041  */
6042 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6043                                         unsigned long field, u64 *ret)
6044 {
6045         short offset = vmcs_field_to_offset(field);
6046         char *p;
6047
6048         if (offset < 0)
6049                 return 0;
6050
6051         p = ((char *)(get_vmcs12(vcpu))) + offset;
6052
6053         switch (vmcs_field_type(field)) {
6054         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6055                 *ret = *((natural_width *)p);
6056                 return 1;
6057         case VMCS_FIELD_TYPE_U16:
6058                 *ret = *((u16 *)p);
6059                 return 1;
6060         case VMCS_FIELD_TYPE_U32:
6061                 *ret = *((u32 *)p);
6062                 return 1;
6063         case VMCS_FIELD_TYPE_U64:
6064                 *ret = *((u64 *)p);
6065                 return 1;
6066         default:
6067                 return 0; /* can never happen. */
6068         }
6069 }
6070
6071
6072 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6073                                     unsigned long field, u64 field_value){
6074         short offset = vmcs_field_to_offset(field);
6075         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6076         if (offset < 0)
6077                 return false;
6078
6079         switch (vmcs_field_type(field)) {
6080         case VMCS_FIELD_TYPE_U16:
6081                 *(u16 *)p = field_value;
6082                 return true;
6083         case VMCS_FIELD_TYPE_U32:
6084                 *(u32 *)p = field_value;
6085                 return true;
6086         case VMCS_FIELD_TYPE_U64:
6087                 *(u64 *)p = field_value;
6088                 return true;
6089         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6090                 *(natural_width *)p = field_value;
6091                 return true;
6092         default:
6093                 return false; /* can never happen. */
6094         }
6095
6096 }
6097
6098 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6099 {
6100         int i;
6101         unsigned long field;
6102         u64 field_value;
6103         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6104         const unsigned long *fields = shadow_read_write_fields;
6105         const int num_fields = max_shadow_read_write_fields;
6106
6107         vmcs_load(shadow_vmcs);
6108
6109         for (i = 0; i < num_fields; i++) {
6110                 field = fields[i];
6111                 switch (vmcs_field_type(field)) {
6112                 case VMCS_FIELD_TYPE_U16:
6113                         field_value = vmcs_read16(field);
6114                         break;
6115                 case VMCS_FIELD_TYPE_U32:
6116                         field_value = vmcs_read32(field);
6117                         break;
6118                 case VMCS_FIELD_TYPE_U64:
6119                         field_value = vmcs_read64(field);
6120                         break;
6121                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6122                         field_value = vmcs_readl(field);
6123                         break;
6124                 }
6125                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6126         }
6127
6128         vmcs_clear(shadow_vmcs);
6129         vmcs_load(vmx->loaded_vmcs->vmcs);
6130 }
6131
6132 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6133 {
6134         const unsigned long *fields[] = {
6135                 shadow_read_write_fields,
6136                 shadow_read_only_fields
6137         };
6138         const int max_fields[] = {
6139                 max_shadow_read_write_fields,
6140                 max_shadow_read_only_fields
6141         };
6142         int i, q;
6143         unsigned long field;
6144         u64 field_value = 0;
6145         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6146
6147         vmcs_load(shadow_vmcs);
6148
6149         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6150                 for (i = 0; i < max_fields[q]; i++) {
6151                         field = fields[q][i];
6152                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6153
6154                         switch (vmcs_field_type(field)) {
6155                         case VMCS_FIELD_TYPE_U16:
6156                                 vmcs_write16(field, (u16)field_value);
6157                                 break;
6158                         case VMCS_FIELD_TYPE_U32:
6159                                 vmcs_write32(field, (u32)field_value);
6160                                 break;
6161                         case VMCS_FIELD_TYPE_U64:
6162                                 vmcs_write64(field, (u64)field_value);
6163                                 break;
6164                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6165                                 vmcs_writel(field, (long)field_value);
6166                                 break;
6167                         }
6168                 }
6169         }
6170
6171         vmcs_clear(shadow_vmcs);
6172         vmcs_load(vmx->loaded_vmcs->vmcs);
6173 }
6174
6175 /*
6176  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6177  * used before) all generate the same failure when it is missing.
6178  */
6179 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6180 {
6181         struct vcpu_vmx *vmx = to_vmx(vcpu);
6182         if (vmx->nested.current_vmptr == -1ull) {
6183                 nested_vmx_failInvalid(vcpu);
6184                 skip_emulated_instruction(vcpu);
6185                 return 0;
6186         }
6187         return 1;
6188 }
6189
6190 static int handle_vmread(struct kvm_vcpu *vcpu)
6191 {
6192         unsigned long field;
6193         u64 field_value;
6194         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6195         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6196         gva_t gva = 0;
6197
6198         if (!nested_vmx_check_permission(vcpu) ||
6199             !nested_vmx_check_vmcs12(vcpu))
6200                 return 1;
6201
6202         /* Decode instruction info and find the field to read */
6203         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6204         /* Read the field, zero-extended to a u64 field_value */
6205         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6206                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6207                 skip_emulated_instruction(vcpu);
6208                 return 1;
6209         }
6210         /*
6211          * Now copy part of this value to register or memory, as requested.
6212          * Note that the number of bits actually copied is 32 or 64 depending
6213          * on the guest's mode (32 or 64 bit), not on the given field's length.
6214          */
6215         if (vmx_instruction_info & (1u << 10)) {
6216                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6217                         field_value);
6218         } else {
6219                 if (get_vmx_mem_address(vcpu, exit_qualification,
6220                                 vmx_instruction_info, &gva))
6221                         return 1;
6222                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6223                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6224                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6225         }
6226
6227         nested_vmx_succeed(vcpu);
6228         skip_emulated_instruction(vcpu);
6229         return 1;
6230 }
6231
6232
6233 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6234 {
6235         unsigned long field;
6236         gva_t gva;
6237         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6238         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6239         /* The value to write might be 32 or 64 bits, depending on L1's long
6240          * mode, and eventually we need to write that into a field of several
6241          * possible lengths. The code below first zero-extends the value to 64
6242          * bit (field_value), and then copies only the approriate number of
6243          * bits into the vmcs12 field.
6244          */
6245         u64 field_value = 0;
6246         struct x86_exception e;
6247
6248         if (!nested_vmx_check_permission(vcpu) ||
6249             !nested_vmx_check_vmcs12(vcpu))
6250                 return 1;
6251
6252         if (vmx_instruction_info & (1u << 10))
6253                 field_value = kvm_register_read(vcpu,
6254                         (((vmx_instruction_info) >> 3) & 0xf));
6255         else {
6256                 if (get_vmx_mem_address(vcpu, exit_qualification,
6257                                 vmx_instruction_info, &gva))
6258                         return 1;
6259                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6260                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6261                         kvm_inject_page_fault(vcpu, &e);
6262                         return 1;
6263                 }
6264         }
6265
6266
6267         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6268         if (vmcs_field_readonly(field)) {
6269                 nested_vmx_failValid(vcpu,
6270                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6271                 skip_emulated_instruction(vcpu);
6272                 return 1;
6273         }
6274
6275         if (!vmcs12_write_any(vcpu, field, field_value)) {
6276                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6277                 skip_emulated_instruction(vcpu);
6278                 return 1;
6279         }
6280
6281         nested_vmx_succeed(vcpu);
6282         skip_emulated_instruction(vcpu);
6283         return 1;
6284 }
6285
6286 /* Emulate the VMPTRLD instruction */
6287 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6288 {
6289         struct vcpu_vmx *vmx = to_vmx(vcpu);
6290         gva_t gva;
6291         gpa_t vmptr;
6292         struct x86_exception e;
6293         u32 exec_control;
6294
6295         if (!nested_vmx_check_permission(vcpu))
6296                 return 1;
6297
6298         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6299                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6300                 return 1;
6301
6302         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6303                                 sizeof(vmptr), &e)) {
6304                 kvm_inject_page_fault(vcpu, &e);
6305                 return 1;
6306         }
6307
6308         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6309                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6310                 skip_emulated_instruction(vcpu);
6311                 return 1;
6312         }
6313
6314         if (vmx->nested.current_vmptr != vmptr) {
6315                 struct vmcs12 *new_vmcs12;
6316                 struct page *page;
6317                 page = nested_get_page(vcpu, vmptr);
6318                 if (page == NULL) {
6319                         nested_vmx_failInvalid(vcpu);
6320                         skip_emulated_instruction(vcpu);
6321                         return 1;
6322                 }
6323                 new_vmcs12 = kmap(page);
6324                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6325                         kunmap(page);
6326                         nested_release_page_clean(page);
6327                         nested_vmx_failValid(vcpu,
6328                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6329                         skip_emulated_instruction(vcpu);
6330                         return 1;
6331                 }
6332                 if (vmx->nested.current_vmptr != -1ull)
6333                         nested_release_vmcs12(vmx);
6334
6335                 vmx->nested.current_vmptr = vmptr;
6336                 vmx->nested.current_vmcs12 = new_vmcs12;
6337                 vmx->nested.current_vmcs12_page = page;
6338                 if (enable_shadow_vmcs) {
6339                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6340                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6341                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6342                         vmcs_write64(VMCS_LINK_POINTER,
6343                                      __pa(vmx->nested.current_shadow_vmcs));
6344                         vmx->nested.sync_shadow_vmcs = true;
6345                 }
6346         }
6347
6348         nested_vmx_succeed(vcpu);
6349         skip_emulated_instruction(vcpu);
6350         return 1;
6351 }
6352
6353 /* Emulate the VMPTRST instruction */
6354 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6355 {
6356         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6357         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6358         gva_t vmcs_gva;
6359         struct x86_exception e;
6360
6361         if (!nested_vmx_check_permission(vcpu))
6362                 return 1;
6363
6364         if (get_vmx_mem_address(vcpu, exit_qualification,
6365                         vmx_instruction_info, &vmcs_gva))
6366                 return 1;
6367         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6368         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6369                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6370                                  sizeof(u64), &e)) {
6371                 kvm_inject_page_fault(vcpu, &e);
6372                 return 1;
6373         }
6374         nested_vmx_succeed(vcpu);
6375         skip_emulated_instruction(vcpu);
6376         return 1;
6377 }
6378
6379 /* Emulate the INVEPT instruction */
6380 static int handle_invept(struct kvm_vcpu *vcpu)
6381 {
6382         u32 vmx_instruction_info, types;
6383         unsigned long type;
6384         gva_t gva;
6385         struct x86_exception e;
6386         struct {
6387                 u64 eptp, gpa;
6388         } operand;
6389         u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6390
6391         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6392             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6393                 kvm_queue_exception(vcpu, UD_VECTOR);
6394                 return 1;
6395         }
6396
6397         if (!nested_vmx_check_permission(vcpu))
6398                 return 1;
6399
6400         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6401                 kvm_queue_exception(vcpu, UD_VECTOR);
6402                 return 1;
6403         }
6404
6405         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6406         type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6407
6408         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6409
6410         if (!(types & (1UL << type))) {
6411                 nested_vmx_failValid(vcpu,
6412                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6413                 return 1;
6414         }
6415
6416         /* According to the Intel VMX instruction reference, the memory
6417          * operand is read even if it isn't needed (e.g., for type==global)
6418          */
6419         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6420                         vmx_instruction_info, &gva))
6421                 return 1;
6422         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6423                                 sizeof(operand), &e)) {
6424                 kvm_inject_page_fault(vcpu, &e);
6425                 return 1;
6426         }
6427
6428         switch (type) {
6429         case VMX_EPT_EXTENT_CONTEXT:
6430                 if ((operand.eptp & eptp_mask) !=
6431                                 (nested_ept_get_cr3(vcpu) & eptp_mask))
6432                         break;
6433         case VMX_EPT_EXTENT_GLOBAL:
6434                 kvm_mmu_sync_roots(vcpu);
6435                 kvm_mmu_flush_tlb(vcpu);
6436                 nested_vmx_succeed(vcpu);
6437                 break;
6438         default:
6439                 BUG_ON(1);
6440                 break;
6441         }
6442
6443         skip_emulated_instruction(vcpu);
6444         return 1;
6445 }
6446
6447 static int handle_invvpid(struct kvm_vcpu *vcpu)
6448 {
6449         kvm_queue_exception(vcpu, UD_VECTOR);
6450         return 1;
6451 }
6452
6453 /*
6454  * The exit handlers return 1 if the exit was handled fully and guest execution
6455  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6456  * to be done to userspace and return 0.
6457  */
6458 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6459         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6460         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6461         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6462         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6463         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6464         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6465         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6466         [EXIT_REASON_CPUID]                   = handle_cpuid,
6467         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6468         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6469         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6470         [EXIT_REASON_HLT]                     = handle_halt,
6471         [EXIT_REASON_INVD]                    = handle_invd,
6472         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6473         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6474         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6475         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6476         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6477         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6478         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6479         [EXIT_REASON_VMREAD]                  = handle_vmread,
6480         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6481         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6482         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6483         [EXIT_REASON_VMON]                    = handle_vmon,
6484         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6485         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6486         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6487         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6488         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6489         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6490         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6491         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6492         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6493         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6494         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6495         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
6496         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
6497         [EXIT_REASON_INVEPT]                  = handle_invept,
6498         [EXIT_REASON_INVVPID]                 = handle_invvpid,
6499 };
6500
6501 static const int kvm_vmx_max_exit_handlers =
6502         ARRAY_SIZE(kvm_vmx_exit_handlers);
6503
6504 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6505                                        struct vmcs12 *vmcs12)
6506 {
6507         unsigned long exit_qualification;
6508         gpa_t bitmap, last_bitmap;
6509         unsigned int port;
6510         int size;
6511         u8 b;
6512
6513         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6514                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
6515
6516         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6517
6518         port = exit_qualification >> 16;
6519         size = (exit_qualification & 7) + 1;
6520
6521         last_bitmap = (gpa_t)-1;
6522         b = -1;
6523
6524         while (size > 0) {
6525                 if (port < 0x8000)
6526                         bitmap = vmcs12->io_bitmap_a;
6527                 else if (port < 0x10000)
6528                         bitmap = vmcs12->io_bitmap_b;
6529                 else
6530                         return 1;
6531                 bitmap += (port & 0x7fff) / 8;
6532
6533                 if (last_bitmap != bitmap)
6534                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6535                                 return 1;
6536                 if (b & (1 << (port & 7)))
6537                         return 1;
6538
6539                 port++;
6540                 size--;
6541                 last_bitmap = bitmap;
6542         }
6543
6544         return 0;
6545 }
6546
6547 /*
6548  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6549  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6550  * disinterest in the current event (read or write a specific MSR) by using an
6551  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6552  */
6553 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6554         struct vmcs12 *vmcs12, u32 exit_reason)
6555 {
6556         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6557         gpa_t bitmap;
6558
6559         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6560                 return 1;
6561
6562         /*
6563          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6564          * for the four combinations of read/write and low/high MSR numbers.
6565          * First we need to figure out which of the four to use:
6566          */
6567         bitmap = vmcs12->msr_bitmap;
6568         if (exit_reason == EXIT_REASON_MSR_WRITE)
6569                 bitmap += 2048;
6570         if (msr_index >= 0xc0000000) {
6571                 msr_index -= 0xc0000000;
6572                 bitmap += 1024;
6573         }
6574
6575         /* Then read the msr_index'th bit from this bitmap: */
6576         if (msr_index < 1024*8) {
6577                 unsigned char b;
6578                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6579                         return 1;
6580                 return 1 & (b >> (msr_index & 7));
6581         } else
6582                 return 1; /* let L1 handle the wrong parameter */
6583 }
6584
6585 /*
6586  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6587  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6588  * intercept (via guest_host_mask etc.) the current event.
6589  */
6590 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6591         struct vmcs12 *vmcs12)
6592 {
6593         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6594         int cr = exit_qualification & 15;
6595         int reg = (exit_qualification >> 8) & 15;
6596         unsigned long val = kvm_register_read(vcpu, reg);
6597
6598         switch ((exit_qualification >> 4) & 3) {
6599         case 0: /* mov to cr */
6600                 switch (cr) {
6601                 case 0:
6602                         if (vmcs12->cr0_guest_host_mask &
6603                             (val ^ vmcs12->cr0_read_shadow))
6604                                 return 1;
6605                         break;
6606                 case 3:
6607                         if ((vmcs12->cr3_target_count >= 1 &&
6608                                         vmcs12->cr3_target_value0 == val) ||
6609                                 (vmcs12->cr3_target_count >= 2 &&
6610                                         vmcs12->cr3_target_value1 == val) ||
6611                                 (vmcs12->cr3_target_count >= 3 &&
6612                                         vmcs12->cr3_target_value2 == val) ||
6613                                 (vmcs12->cr3_target_count >= 4 &&
6614                                         vmcs12->cr3_target_value3 == val))
6615                                 return 0;
6616                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6617                                 return 1;
6618                         break;
6619                 case 4:
6620                         if (vmcs12->cr4_guest_host_mask &
6621                             (vmcs12->cr4_read_shadow ^ val))
6622                                 return 1;
6623                         break;
6624                 case 8:
6625                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6626                                 return 1;
6627                         break;
6628                 }
6629                 break;
6630         case 2: /* clts */
6631                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6632                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6633                         return 1;
6634                 break;
6635         case 1: /* mov from cr */
6636                 switch (cr) {
6637                 case 3:
6638                         if (vmcs12->cpu_based_vm_exec_control &
6639                             CPU_BASED_CR3_STORE_EXITING)
6640                                 return 1;
6641                         break;
6642                 case 8:
6643                         if (vmcs12->cpu_based_vm_exec_control &
6644                             CPU_BASED_CR8_STORE_EXITING)
6645                                 return 1;
6646                         break;
6647                 }
6648                 break;
6649         case 3: /* lmsw */
6650                 /*
6651                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6652                  * cr0. Other attempted changes are ignored, with no exit.
6653                  */
6654                 if (vmcs12->cr0_guest_host_mask & 0xe &
6655                     (val ^ vmcs12->cr0_read_shadow))
6656                         return 1;
6657                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6658                     !(vmcs12->cr0_read_shadow & 0x1) &&
6659                     (val & 0x1))
6660                         return 1;
6661                 break;
6662         }
6663         return 0;
6664 }
6665
6666 /*
6667  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6668  * should handle it ourselves in L0 (and then continue L2). Only call this
6669  * when in is_guest_mode (L2).
6670  */
6671 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6672 {
6673         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6674         struct vcpu_vmx *vmx = to_vmx(vcpu);
6675         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6676         u32 exit_reason = vmx->exit_reason;
6677
6678         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6679                                 vmcs_readl(EXIT_QUALIFICATION),
6680                                 vmx->idt_vectoring_info,
6681                                 intr_info,
6682                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6683                                 KVM_ISA_VMX);
6684
6685         if (vmx->nested.nested_run_pending)
6686                 return 0;
6687
6688         if (unlikely(vmx->fail)) {
6689                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6690                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6691                 return 1;
6692         }
6693
6694         switch (exit_reason) {
6695         case EXIT_REASON_EXCEPTION_NMI:
6696                 if (!is_exception(intr_info))
6697                         return 0;
6698                 else if (is_page_fault(intr_info))
6699                         return enable_ept;
6700                 else if (is_no_device(intr_info) &&
6701                          !(vmcs12->guest_cr0 & X86_CR0_TS))
6702                         return 0;
6703                 return vmcs12->exception_bitmap &
6704                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6705         case EXIT_REASON_EXTERNAL_INTERRUPT:
6706                 return 0;
6707         case EXIT_REASON_TRIPLE_FAULT:
6708                 return 1;
6709         case EXIT_REASON_PENDING_INTERRUPT:
6710                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6711         case EXIT_REASON_NMI_WINDOW:
6712                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6713         case EXIT_REASON_TASK_SWITCH:
6714                 return 1;
6715         case EXIT_REASON_CPUID:
6716                 return 1;
6717         case EXIT_REASON_HLT:
6718                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6719         case EXIT_REASON_INVD:
6720                 return 1;
6721         case EXIT_REASON_INVLPG:
6722                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6723         case EXIT_REASON_RDPMC:
6724                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6725         case EXIT_REASON_RDTSC:
6726                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6727         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6728         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6729         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6730         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6731         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6732         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
6733                 /*
6734                  * VMX instructions trap unconditionally. This allows L1 to
6735                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
6736                  */
6737                 return 1;
6738         case EXIT_REASON_CR_ACCESS:
6739                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6740         case EXIT_REASON_DR_ACCESS:
6741                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6742         case EXIT_REASON_IO_INSTRUCTION:
6743                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
6744         case EXIT_REASON_MSR_READ:
6745         case EXIT_REASON_MSR_WRITE:
6746                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6747         case EXIT_REASON_INVALID_STATE:
6748                 return 1;
6749         case EXIT_REASON_MWAIT_INSTRUCTION:
6750                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6751         case EXIT_REASON_MONITOR_INSTRUCTION:
6752                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6753         case EXIT_REASON_PAUSE_INSTRUCTION:
6754                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6755                         nested_cpu_has2(vmcs12,
6756                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6757         case EXIT_REASON_MCE_DURING_VMENTRY:
6758                 return 0;
6759         case EXIT_REASON_TPR_BELOW_THRESHOLD:
6760                 return 1;
6761         case EXIT_REASON_APIC_ACCESS:
6762                 return nested_cpu_has2(vmcs12,
6763                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6764         case EXIT_REASON_EPT_VIOLATION:
6765                 /*
6766                  * L0 always deals with the EPT violation. If nested EPT is
6767                  * used, and the nested mmu code discovers that the address is
6768                  * missing in the guest EPT table (EPT12), the EPT violation
6769                  * will be injected with nested_ept_inject_page_fault()
6770                  */
6771                 return 0;
6772         case EXIT_REASON_EPT_MISCONFIG:
6773                 /*
6774                  * L2 never uses directly L1's EPT, but rather L0's own EPT
6775                  * table (shadow on EPT) or a merged EPT table that L0 built
6776                  * (EPT on EPT). So any problems with the structure of the
6777                  * table is L0's fault.
6778                  */
6779                 return 0;
6780         case EXIT_REASON_PREEMPTION_TIMER:
6781                 return vmcs12->pin_based_vm_exec_control &
6782                         PIN_BASED_VMX_PREEMPTION_TIMER;
6783         case EXIT_REASON_WBINVD:
6784                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6785         case EXIT_REASON_XSETBV:
6786                 return 1;
6787         default:
6788                 return 1;
6789         }
6790 }
6791
6792 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6793 {
6794         *info1 = vmcs_readl(EXIT_QUALIFICATION);
6795         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6796 }
6797
6798 static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
6799 {
6800         u64 delta_tsc_l1;
6801         u32 preempt_val_l1, preempt_val_l2, preempt_scale;
6802
6803         if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
6804                         PIN_BASED_VMX_PREEMPTION_TIMER))
6805                 return;
6806         preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
6807                         MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
6808         preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
6809         delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
6810                 - vcpu->arch.last_guest_tsc;
6811         preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
6812         if (preempt_val_l2 <= preempt_val_l1)
6813                 preempt_val_l2 = 0;
6814         else
6815                 preempt_val_l2 -= preempt_val_l1;
6816         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
6817 }
6818
6819 /*
6820  * The guest has exited.  See if we can fix it or if we need userspace
6821  * assistance.
6822  */
6823 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6824 {
6825         struct vcpu_vmx *vmx = to_vmx(vcpu);
6826         u32 exit_reason = vmx->exit_reason;
6827         u32 vectoring_info = vmx->idt_vectoring_info;
6828
6829         /* If guest state is invalid, start emulating */
6830         if (vmx->emulation_required)
6831                 return handle_invalid_guest_state(vcpu);
6832
6833         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6834                 nested_vmx_vmexit(vcpu, exit_reason,
6835                                   vmcs_read32(VM_EXIT_INTR_INFO),
6836                                   vmcs_readl(EXIT_QUALIFICATION));
6837                 return 1;
6838         }
6839
6840         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6841                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6842                 vcpu->run->fail_entry.hardware_entry_failure_reason
6843                         = exit_reason;
6844                 return 0;
6845         }
6846
6847         if (unlikely(vmx->fail)) {
6848                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6849                 vcpu->run->fail_entry.hardware_entry_failure_reason
6850                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6851                 return 0;
6852         }
6853
6854         /*
6855          * Note:
6856          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6857          * delivery event since it indicates guest is accessing MMIO.
6858          * The vm-exit can be triggered again after return to guest that
6859          * will cause infinite loop.
6860          */
6861         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6862                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6863                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6864                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
6865                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6866                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6867                 vcpu->run->internal.ndata = 2;
6868                 vcpu->run->internal.data[0] = vectoring_info;
6869                 vcpu->run->internal.data[1] = exit_reason;
6870                 return 0;
6871         }
6872
6873         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6874             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6875                                         get_vmcs12(vcpu))))) {
6876                 if (vmx_interrupt_allowed(vcpu)) {
6877                         vmx->soft_vnmi_blocked = 0;
6878                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6879                            vcpu->arch.nmi_pending) {
6880                         /*
6881                          * This CPU don't support us in finding the end of an
6882                          * NMI-blocked window if the guest runs with IRQs
6883                          * disabled. So we pull the trigger after 1 s of
6884                          * futile waiting, but inform the user about this.
6885                          */
6886                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6887                                "state on VCPU %d after 1 s timeout\n",
6888                                __func__, vcpu->vcpu_id);
6889                         vmx->soft_vnmi_blocked = 0;
6890                 }
6891         }
6892
6893         if (exit_reason < kvm_vmx_max_exit_handlers
6894             && kvm_vmx_exit_handlers[exit_reason])
6895                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6896         else {
6897                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
6898                 kvm_queue_exception(vcpu, UD_VECTOR);
6899                 return 1;
6900         }
6901 }
6902
6903 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6904 {
6905         if (irr == -1 || tpr < irr) {
6906                 vmcs_write32(TPR_THRESHOLD, 0);
6907                 return;
6908         }
6909
6910         vmcs_write32(TPR_THRESHOLD, irr);
6911 }
6912
6913 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6914 {
6915         u32 sec_exec_control;
6916
6917         /*
6918          * There is not point to enable virtualize x2apic without enable
6919          * apicv
6920          */
6921         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6922                                 !vmx_vm_has_apicv(vcpu->kvm))
6923                 return;
6924
6925         if (!vm_need_tpr_shadow(vcpu->kvm))
6926                 return;
6927
6928         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6929
6930         if (set) {
6931                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6932                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6933         } else {
6934                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6935                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6936         }
6937         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6938
6939         vmx_set_msr_bitmap(vcpu);
6940 }
6941
6942 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6943 {
6944         u16 status;
6945         u8 old;
6946
6947         if (!vmx_vm_has_apicv(kvm))
6948                 return;
6949
6950         if (isr == -1)
6951                 isr = 0;
6952
6953         status = vmcs_read16(GUEST_INTR_STATUS);
6954         old = status >> 8;
6955         if (isr != old) {
6956                 status &= 0xff;
6957                 status |= isr << 8;
6958                 vmcs_write16(GUEST_INTR_STATUS, status);
6959         }
6960 }
6961
6962 static void vmx_set_rvi(int vector)
6963 {
6964         u16 status;
6965         u8 old;
6966
6967         status = vmcs_read16(GUEST_INTR_STATUS);
6968         old = (u8)status & 0xff;
6969         if ((u8)vector != old) {
6970                 status &= ~0xff;
6971                 status |= (u8)vector;
6972                 vmcs_write16(GUEST_INTR_STATUS, status);
6973         }
6974 }
6975
6976 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6977 {
6978         if (max_irr == -1)
6979                 return;
6980
6981         vmx_set_rvi(max_irr);
6982 }
6983
6984 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6985 {
6986         if (!vmx_vm_has_apicv(vcpu->kvm))
6987                 return;
6988
6989         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6990         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6991         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6992         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6993 }
6994
6995 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6996 {
6997         u32 exit_intr_info;
6998
6999         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7000               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7001                 return;
7002
7003         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7004         exit_intr_info = vmx->exit_intr_info;
7005
7006         /* Handle machine checks before interrupts are enabled */
7007         if (is_machine_check(exit_intr_info))
7008                 kvm_machine_check();
7009
7010         /* We need to handle NMIs before interrupts are enabled */
7011         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7012             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7013                 kvm_before_handle_nmi(&vmx->vcpu);
7014                 asm("int $2");
7015                 kvm_after_handle_nmi(&vmx->vcpu);
7016         }
7017 }
7018
7019 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7020 {
7021         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7022
7023         /*
7024          * If external interrupt exists, IF bit is set in rflags/eflags on the
7025          * interrupt stack frame, and interrupt will be enabled on a return
7026          * from interrupt handler.
7027          */
7028         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7029                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7030                 unsigned int vector;
7031                 unsigned long entry;
7032                 gate_desc *desc;
7033                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7034 #ifdef CONFIG_X86_64
7035                 unsigned long tmp;
7036 #endif
7037
7038                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7039                 desc = (gate_desc *)vmx->host_idt_base + vector;
7040                 entry = gate_offset(*desc);
7041                 asm volatile(
7042 #ifdef CONFIG_X86_64
7043                         "mov %%" _ASM_SP ", %[sp]\n\t"
7044                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7045                         "push $%c[ss]\n\t"
7046                         "push %[sp]\n\t"
7047 #endif
7048                         "pushf\n\t"
7049                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7050                         __ASM_SIZE(push) " $%c[cs]\n\t"
7051                         "call *%[entry]\n\t"
7052                         :
7053 #ifdef CONFIG_X86_64
7054                         [sp]"=&r"(tmp)
7055 #endif
7056                         :
7057                         [entry]"r"(entry),
7058                         [ss]"i"(__KERNEL_DS),
7059                         [cs]"i"(__KERNEL_CS)
7060                         );
7061         } else
7062                 local_irq_enable();
7063 }
7064
7065 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7066 {
7067         u32 exit_intr_info;
7068         bool unblock_nmi;
7069         u8 vector;
7070         bool idtv_info_valid;
7071
7072         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7073
7074         if (cpu_has_virtual_nmis()) {
7075                 if (vmx->nmi_known_unmasked)
7076                         return;
7077                 /*
7078                  * Can't use vmx->exit_intr_info since we're not sure what
7079                  * the exit reason is.
7080                  */
7081                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7082                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7083                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7084                 /*
7085                  * SDM 3: 27.7.1.2 (September 2008)
7086                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7087                  * a guest IRET fault.
7088                  * SDM 3: 23.2.2 (September 2008)
7089                  * Bit 12 is undefined in any of the following cases:
7090                  *  If the VM exit sets the valid bit in the IDT-vectoring
7091                  *   information field.
7092                  *  If the VM exit is due to a double fault.
7093                  */
7094                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7095                     vector != DF_VECTOR && !idtv_info_valid)
7096                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7097                                       GUEST_INTR_STATE_NMI);
7098                 else
7099                         vmx->nmi_known_unmasked =
7100                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7101                                   & GUEST_INTR_STATE_NMI);
7102         } else if (unlikely(vmx->soft_vnmi_blocked))
7103                 vmx->vnmi_blocked_time +=
7104                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7105 }
7106
7107 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7108                                       u32 idt_vectoring_info,
7109                                       int instr_len_field,
7110                                       int error_code_field)
7111 {
7112         u8 vector;
7113         int type;
7114         bool idtv_info_valid;
7115
7116         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7117
7118         vcpu->arch.nmi_injected = false;
7119         kvm_clear_exception_queue(vcpu);
7120         kvm_clear_interrupt_queue(vcpu);
7121
7122         if (!idtv_info_valid)
7123                 return;
7124
7125         kvm_make_request(KVM_REQ_EVENT, vcpu);
7126
7127         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7128         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7129
7130         switch (type) {
7131         case INTR_TYPE_NMI_INTR:
7132                 vcpu->arch.nmi_injected = true;
7133                 /*
7134                  * SDM 3: 27.7.1.2 (September 2008)
7135                  * Clear bit "block by NMI" before VM entry if a NMI
7136                  * delivery faulted.
7137                  */
7138                 vmx_set_nmi_mask(vcpu, false);
7139                 break;
7140         case INTR_TYPE_SOFT_EXCEPTION:
7141                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7142                 /* fall through */
7143         case INTR_TYPE_HARD_EXCEPTION:
7144                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7145                         u32 err = vmcs_read32(error_code_field);
7146                         kvm_requeue_exception_e(vcpu, vector, err);
7147                 } else
7148                         kvm_requeue_exception(vcpu, vector);
7149                 break;
7150         case INTR_TYPE_SOFT_INTR:
7151                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7152                 /* fall through */
7153         case INTR_TYPE_EXT_INTR:
7154                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7155                 break;
7156         default:
7157                 break;
7158         }
7159 }
7160
7161 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7162 {
7163         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7164                                   VM_EXIT_INSTRUCTION_LEN,
7165                                   IDT_VECTORING_ERROR_CODE);
7166 }
7167
7168 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7169 {
7170         __vmx_complete_interrupts(vcpu,
7171                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7172                                   VM_ENTRY_INSTRUCTION_LEN,
7173                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7174
7175         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7176 }
7177
7178 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7179 {
7180         int i, nr_msrs;
7181         struct perf_guest_switch_msr *msrs;
7182
7183         msrs = perf_guest_get_msrs(&nr_msrs);
7184
7185         if (!msrs)
7186                 return;
7187
7188         for (i = 0; i < nr_msrs; i++)
7189                 if (msrs[i].host == msrs[i].guest)
7190                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7191                 else
7192                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7193                                         msrs[i].host);
7194 }
7195
7196 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7197 {
7198         struct vcpu_vmx *vmx = to_vmx(vcpu);
7199         unsigned long debugctlmsr;
7200
7201         /* Record the guest's net vcpu time for enforced NMI injections. */
7202         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7203                 vmx->entry_time = ktime_get();
7204
7205         /* Don't enter VMX if guest state is invalid, let the exit handler
7206            start emulation until we arrive back to a valid state */
7207         if (vmx->emulation_required)
7208                 return;
7209
7210         if (vmx->nested.sync_shadow_vmcs) {
7211                 copy_vmcs12_to_shadow(vmx);
7212                 vmx->nested.sync_shadow_vmcs = false;
7213         }
7214
7215         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7216                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7217         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7218                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7219
7220         /* When single-stepping over STI and MOV SS, we must clear the
7221          * corresponding interruptibility bits in the guest state. Otherwise
7222          * vmentry fails as it then expects bit 14 (BS) in pending debug
7223          * exceptions being set, but that's not correct for the guest debugging
7224          * case. */
7225         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7226                 vmx_set_interrupt_shadow(vcpu, 0);
7227
7228         atomic_switch_perf_msrs(vmx);
7229         debugctlmsr = get_debugctlmsr();
7230
7231         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
7232                 nested_adjust_preemption_timer(vcpu);
7233         vmx->__launched = vmx->loaded_vmcs->launched;
7234         asm(
7235                 /* Store host registers */
7236                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7237                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7238                 "push %%" _ASM_CX " \n\t"
7239                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7240                 "je 1f \n\t"
7241                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7242                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7243                 "1: \n\t"
7244                 /* Reload cr2 if changed */
7245                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7246                 "mov %%cr2, %%" _ASM_DX " \n\t"
7247                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7248                 "je 2f \n\t"
7249                 "mov %%" _ASM_AX", %%cr2 \n\t"
7250                 "2: \n\t"
7251                 /* Check if vmlaunch of vmresume is needed */
7252                 "cmpl $0, %c[launched](%0) \n\t"
7253                 /* Load guest registers.  Don't clobber flags. */
7254                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7255                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7256                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7257                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7258                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7259                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7260 #ifdef CONFIG_X86_64
7261                 "mov %c[r8](%0),  %%r8  \n\t"
7262                 "mov %c[r9](%0),  %%r9  \n\t"
7263                 "mov %c[r10](%0), %%r10 \n\t"
7264                 "mov %c[r11](%0), %%r11 \n\t"
7265                 "mov %c[r12](%0), %%r12 \n\t"
7266                 "mov %c[r13](%0), %%r13 \n\t"
7267                 "mov %c[r14](%0), %%r14 \n\t"
7268                 "mov %c[r15](%0), %%r15 \n\t"
7269 #endif
7270                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7271
7272                 /* Enter guest mode */
7273                 "jne 1f \n\t"
7274                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7275                 "jmp 2f \n\t"
7276                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7277                 "2: "
7278                 /* Save guest registers, load host registers, keep flags */
7279                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7280                 "pop %0 \n\t"
7281                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7282                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7283                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7284                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7285                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7286                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7287                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7288 #ifdef CONFIG_X86_64
7289                 "mov %%r8,  %c[r8](%0) \n\t"
7290                 "mov %%r9,  %c[r9](%0) \n\t"
7291                 "mov %%r10, %c[r10](%0) \n\t"
7292                 "mov %%r11, %c[r11](%0) \n\t"
7293                 "mov %%r12, %c[r12](%0) \n\t"
7294                 "mov %%r13, %c[r13](%0) \n\t"
7295                 "mov %%r14, %c[r14](%0) \n\t"
7296                 "mov %%r15, %c[r15](%0) \n\t"
7297 #endif
7298                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7299                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7300
7301                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7302                 "setbe %c[fail](%0) \n\t"
7303                 ".pushsection .rodata \n\t"
7304                 ".global vmx_return \n\t"
7305                 "vmx_return: " _ASM_PTR " 2b \n\t"
7306                 ".popsection"
7307               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7308                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7309                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7310                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7311                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7312                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7313                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7314                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7315                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7316                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7317                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7318 #ifdef CONFIG_X86_64
7319                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7320                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7321                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7322                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7323                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7324                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7325                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7326                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7327 #endif
7328                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7329                 [wordsize]"i"(sizeof(ulong))
7330               : "cc", "memory"
7331 #ifdef CONFIG_X86_64
7332                 , "rax", "rbx", "rdi", "rsi"
7333                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7334 #else
7335                 , "eax", "ebx", "edi", "esi"
7336 #endif
7337               );
7338
7339         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7340         if (debugctlmsr)
7341                 update_debugctlmsr(debugctlmsr);
7342
7343 #ifndef CONFIG_X86_64
7344         /*
7345          * The sysexit path does not restore ds/es, so we must set them to
7346          * a reasonable value ourselves.
7347          *
7348          * We can't defer this to vmx_load_host_state() since that function
7349          * may be executed in interrupt context, which saves and restore segments
7350          * around it, nullifying its effect.
7351          */
7352         loadsegment(ds, __USER_DS);
7353         loadsegment(es, __USER_DS);
7354 #endif
7355
7356         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7357                                   | (1 << VCPU_EXREG_RFLAGS)
7358                                   | (1 << VCPU_EXREG_CPL)
7359                                   | (1 << VCPU_EXREG_PDPTR)
7360                                   | (1 << VCPU_EXREG_SEGMENTS)
7361                                   | (1 << VCPU_EXREG_CR3));
7362         vcpu->arch.regs_dirty = 0;
7363
7364         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7365
7366         vmx->loaded_vmcs->launched = 1;
7367
7368         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7369         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7370
7371         /*
7372          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7373          * we did not inject a still-pending event to L1 now because of
7374          * nested_run_pending, we need to re-enable this bit.
7375          */
7376         if (vmx->nested.nested_run_pending)
7377                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7378
7379         vmx->nested.nested_run_pending = 0;
7380
7381         vmx_complete_atomic_exit(vmx);
7382         vmx_recover_nmi_blocking(vmx);
7383         vmx_complete_interrupts(vmx);
7384 }
7385
7386 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7387 {
7388         struct vcpu_vmx *vmx = to_vmx(vcpu);
7389
7390         free_vpid(vmx);
7391         free_loaded_vmcs(vmx->loaded_vmcs);
7392         free_nested(vmx);
7393         kfree(vmx->guest_msrs);
7394         kvm_vcpu_uninit(vcpu);
7395         kmem_cache_free(kvm_vcpu_cache, vmx);
7396 }
7397
7398 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7399 {
7400         int err;
7401         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7402         int cpu;
7403
7404         if (!vmx)
7405                 return ERR_PTR(-ENOMEM);
7406
7407         allocate_vpid(vmx);
7408
7409         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7410         if (err)
7411                 goto free_vcpu;
7412
7413         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7414         err = -ENOMEM;
7415         if (!vmx->guest_msrs) {
7416                 goto uninit_vcpu;
7417         }
7418
7419         vmx->loaded_vmcs = &vmx->vmcs01;
7420         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7421         if (!vmx->loaded_vmcs->vmcs)
7422                 goto free_msrs;
7423         if (!vmm_exclusive)
7424                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7425         loaded_vmcs_init(vmx->loaded_vmcs);
7426         if (!vmm_exclusive)
7427                 kvm_cpu_vmxoff();
7428
7429         cpu = get_cpu();
7430         vmx_vcpu_load(&vmx->vcpu, cpu);
7431         vmx->vcpu.cpu = cpu;
7432         err = vmx_vcpu_setup(vmx);
7433         vmx_vcpu_put(&vmx->vcpu);
7434         put_cpu();
7435         if (err)
7436                 goto free_vmcs;
7437         if (vm_need_virtualize_apic_accesses(kvm)) {
7438                 err = alloc_apic_access_page(kvm);
7439                 if (err)
7440                         goto free_vmcs;
7441         }
7442
7443         if (enable_ept) {
7444                 if (!kvm->arch.ept_identity_map_addr)
7445                         kvm->arch.ept_identity_map_addr =
7446                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7447                 err = -ENOMEM;
7448                 if (alloc_identity_pagetable(kvm) != 0)
7449                         goto free_vmcs;
7450                 if (!init_rmode_identity_map(kvm))
7451                         goto free_vmcs;
7452         }
7453
7454         vmx->nested.current_vmptr = -1ull;
7455         vmx->nested.current_vmcs12 = NULL;
7456
7457         return &vmx->vcpu;
7458
7459 free_vmcs:
7460         free_loaded_vmcs(vmx->loaded_vmcs);
7461 free_msrs:
7462         kfree(vmx->guest_msrs);
7463 uninit_vcpu:
7464         kvm_vcpu_uninit(&vmx->vcpu);
7465 free_vcpu:
7466         free_vpid(vmx);
7467         kmem_cache_free(kvm_vcpu_cache, vmx);
7468         return ERR_PTR(err);
7469 }
7470
7471 static void __init vmx_check_processor_compat(void *rtn)
7472 {
7473         struct vmcs_config vmcs_conf;
7474
7475         *(int *)rtn = 0;
7476         if (setup_vmcs_config(&vmcs_conf) < 0)
7477                 *(int *)rtn = -EIO;
7478         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7479                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7480                                 smp_processor_id());
7481                 *(int *)rtn = -EIO;
7482         }
7483 }
7484
7485 static int get_ept_level(void)
7486 {
7487         return VMX_EPT_DEFAULT_GAW + 1;
7488 }
7489
7490 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7491 {
7492         u64 ret;
7493
7494         /* For VT-d and EPT combination
7495          * 1. MMIO: always map as UC
7496          * 2. EPT with VT-d:
7497          *   a. VT-d without snooping control feature: can't guarantee the
7498          *      result, try to trust guest.
7499          *   b. VT-d with snooping control feature: snooping control feature of
7500          *      VT-d engine can guarantee the cache correctness. Just set it
7501          *      to WB to keep consistent with host. So the same as item 3.
7502          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7503          *    consistent with host MTRR
7504          */
7505         if (is_mmio)
7506                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7507         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
7508                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7509                       VMX_EPT_MT_EPTE_SHIFT;
7510         else
7511                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7512                         | VMX_EPT_IPAT_BIT;
7513
7514         return ret;
7515 }
7516
7517 static int vmx_get_lpage_level(void)
7518 {
7519         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7520                 return PT_DIRECTORY_LEVEL;
7521         else
7522                 /* For shadow and EPT supported 1GB page */
7523                 return PT_PDPE_LEVEL;
7524 }
7525
7526 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7527 {
7528         struct kvm_cpuid_entry2 *best;
7529         struct vcpu_vmx *vmx = to_vmx(vcpu);
7530         u32 exec_control;
7531
7532         vmx->rdtscp_enabled = false;
7533         if (vmx_rdtscp_supported()) {
7534                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7535                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7536                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7537                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7538                                 vmx->rdtscp_enabled = true;
7539                         else {
7540                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7541                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7542                                                 exec_control);
7543                         }
7544                 }
7545         }
7546
7547         /* Exposing INVPCID only when PCID is exposed */
7548         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7549         if (vmx_invpcid_supported() &&
7550             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7551             guest_cpuid_has_pcid(vcpu)) {
7552                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7553                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7554                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7555                              exec_control);
7556         } else {
7557                 if (cpu_has_secondary_exec_ctrls()) {
7558                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7559                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7560                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7561                                      exec_control);
7562                 }
7563                 if (best)
7564                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7565         }
7566 }
7567
7568 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7569 {
7570         if (func == 1 && nested)
7571                 entry->ecx |= bit(X86_FEATURE_VMX);
7572 }
7573
7574 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7575                 struct x86_exception *fault)
7576 {
7577         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7578         u32 exit_reason;
7579
7580         if (fault->error_code & PFERR_RSVD_MASK)
7581                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
7582         else
7583                 exit_reason = EXIT_REASON_EPT_VIOLATION;
7584         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
7585         vmcs12->guest_physical_address = fault->address;
7586 }
7587
7588 /* Callbacks for nested_ept_init_mmu_context: */
7589
7590 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7591 {
7592         /* return the page table to be shadowed - in our case, EPT12 */
7593         return get_vmcs12(vcpu)->ept_pointer;
7594 }
7595
7596 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7597 {
7598         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7599                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7600
7601         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7602         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7603         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7604
7605         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7606 }
7607
7608 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7609 {
7610         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7611 }
7612
7613 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7614                 struct x86_exception *fault)
7615 {
7616         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7617
7618         WARN_ON(!is_guest_mode(vcpu));
7619
7620         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7621         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7622                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7623                                   vmcs_read32(VM_EXIT_INTR_INFO),
7624                                   vmcs_readl(EXIT_QUALIFICATION));
7625         else
7626                 kvm_inject_page_fault(vcpu, fault);
7627 }
7628
7629 /*
7630  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7631  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7632  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7633  * guest in a way that will both be appropriate to L1's requests, and our
7634  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7635  * function also has additional necessary side-effects, like setting various
7636  * vcpu->arch fields.
7637  */
7638 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7639 {
7640         struct vcpu_vmx *vmx = to_vmx(vcpu);
7641         u32 exec_control;
7642         u32 exit_control;
7643
7644         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7645         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7646         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7647         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7648         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7649         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7650         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7651         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7652         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7653         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7654         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7655         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7656         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7657         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7658         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7659         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7660         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7661         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7662         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7663         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7664         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7665         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7666         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7667         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7668         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7669         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7670         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7671         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7672         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7673         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7674         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7675         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7676         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7677         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7678         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7679         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7680
7681         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7682         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7683                 vmcs12->vm_entry_intr_info_field);
7684         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7685                 vmcs12->vm_entry_exception_error_code);
7686         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7687                 vmcs12->vm_entry_instruction_len);
7688         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7689                 vmcs12->guest_interruptibility_info);
7690         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
7691         kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7692         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
7693         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7694                 vmcs12->guest_pending_dbg_exceptions);
7695         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7696         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7697
7698         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7699
7700         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7701                 (vmcs_config.pin_based_exec_ctrl |
7702                  vmcs12->pin_based_vm_exec_control));
7703
7704         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7705                 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7706                              vmcs12->vmx_preemption_timer_value);
7707
7708         /*
7709          * Whether page-faults are trapped is determined by a combination of
7710          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7711          * If enable_ept, L0 doesn't care about page faults and we should
7712          * set all of these to L1's desires. However, if !enable_ept, L0 does
7713          * care about (at least some) page faults, and because it is not easy
7714          * (if at all possible?) to merge L0 and L1's desires, we simply ask
7715          * to exit on each and every L2 page fault. This is done by setting
7716          * MASK=MATCH=0 and (see below) EB.PF=1.
7717          * Note that below we don't need special code to set EB.PF beyond the
7718          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7719          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7720          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7721          *
7722          * A problem with this approach (when !enable_ept) is that L1 may be
7723          * injected with more page faults than it asked for. This could have
7724          * caused problems, but in practice existing hypervisors don't care.
7725          * To fix this, we will need to emulate the PFEC checking (on the L1
7726          * page tables), using walk_addr(), when injecting PFs to L1.
7727          */
7728         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7729                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7730         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7731                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7732
7733         if (cpu_has_secondary_exec_ctrls()) {
7734                 u32 exec_control = vmx_secondary_exec_control(vmx);
7735                 if (!vmx->rdtscp_enabled)
7736                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
7737                 /* Take the following fields only from vmcs12 */
7738                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7739                 if (nested_cpu_has(vmcs12,
7740                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7741                         exec_control |= vmcs12->secondary_vm_exec_control;
7742
7743                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7744                         /*
7745                          * Translate L1 physical address to host physical
7746                          * address for vmcs02. Keep the page pinned, so this
7747                          * physical address remains valid. We keep a reference
7748                          * to it so we can release it later.
7749                          */
7750                         if (vmx->nested.apic_access_page) /* shouldn't happen */
7751                                 nested_release_page(vmx->nested.apic_access_page);
7752                         vmx->nested.apic_access_page =
7753                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
7754                         /*
7755                          * If translation failed, no matter: This feature asks
7756                          * to exit when accessing the given address, and if it
7757                          * can never be accessed, this feature won't do
7758                          * anything anyway.
7759                          */
7760                         if (!vmx->nested.apic_access_page)
7761                                 exec_control &=
7762                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7763                         else
7764                                 vmcs_write64(APIC_ACCESS_ADDR,
7765                                   page_to_phys(vmx->nested.apic_access_page));
7766                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7767                         exec_control |=
7768                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7769                         vmcs_write64(APIC_ACCESS_ADDR,
7770                                 page_to_phys(vcpu->kvm->arch.apic_access_page));
7771                 }
7772
7773                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7774         }
7775
7776
7777         /*
7778          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7779          * Some constant fields are set here by vmx_set_constant_host_state().
7780          * Other fields are different per CPU, and will be set later when
7781          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7782          */
7783         vmx_set_constant_host_state(vmx);
7784
7785         /*
7786          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7787          * entry, but only if the current (host) sp changed from the value
7788          * we wrote last (vmx->host_rsp). This cache is no longer relevant
7789          * if we switch vmcs, and rather than hold a separate cache per vmcs,
7790          * here we just force the write to happen on entry.
7791          */
7792         vmx->host_rsp = 0;
7793
7794         exec_control = vmx_exec_control(vmx); /* L0's desires */
7795         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7796         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7797         exec_control &= ~CPU_BASED_TPR_SHADOW;
7798         exec_control |= vmcs12->cpu_based_vm_exec_control;
7799         /*
7800          * Merging of IO and MSR bitmaps not currently supported.
7801          * Rather, exit every time.
7802          */
7803         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7804         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7805         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7806
7807         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7808
7809         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7810          * bitwise-or of what L1 wants to trap for L2, and what we want to
7811          * trap. Note that CR0.TS also needs updating - we do this later.
7812          */
7813         update_exception_bitmap(vcpu);
7814         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7815         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7816
7817         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7818          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7819          * bits are further modified by vmx_set_efer() below.
7820          */
7821         exit_control = vmcs_config.vmexit_ctrl;
7822         if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7823                 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
7824         vm_exit_controls_init(vmx, exit_control);
7825
7826         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7827          * emulated by vmx_set_efer(), below.
7828          */
7829         vm_entry_controls_init(vmx,
7830                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7831                         ~VM_ENTRY_IA32E_MODE) |
7832                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7833
7834         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
7835                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7836                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7837         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7838                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7839
7840
7841         set_cr4_guest_host_mask(vmx);
7842
7843         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7844                 vmcs_write64(TSC_OFFSET,
7845                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7846         else
7847                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7848
7849         if (enable_vpid) {
7850                 /*
7851                  * Trivially support vpid by letting L2s share their parent
7852                  * L1's vpid. TODO: move to a more elaborate solution, giving
7853                  * each L2 its own vpid and exposing the vpid feature to L1.
7854                  */
7855                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7856                 vmx_flush_tlb(vcpu);
7857         }
7858
7859         if (nested_cpu_has_ept(vmcs12)) {
7860                 kvm_mmu_unload(vcpu);
7861                 nested_ept_init_mmu_context(vcpu);
7862         }
7863
7864         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7865                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7866         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7867                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7868         else
7869                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7870         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7871         vmx_set_efer(vcpu, vcpu->arch.efer);
7872
7873         /*
7874          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7875          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7876          * The CR0_READ_SHADOW is what L2 should have expected to read given
7877          * the specifications by L1; It's not enough to take
7878          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7879          * have more bits than L1 expected.
7880          */
7881         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7882         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7883
7884         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7885         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7886
7887         /* shadow page tables on either EPT or shadow page tables */
7888         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7889         kvm_mmu_reset_context(vcpu);
7890
7891         if (!enable_ept)
7892                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7893
7894         /*
7895          * L1 may access the L2's PDPTR, so save them to construct vmcs12
7896          */
7897         if (enable_ept) {
7898                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7899                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7900                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7901                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7902         }
7903
7904         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7905         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7906 }
7907
7908 /*
7909  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7910  * for running an L2 nested guest.
7911  */
7912 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7913 {
7914         struct vmcs12 *vmcs12;
7915         struct vcpu_vmx *vmx = to_vmx(vcpu);
7916         int cpu;
7917         struct loaded_vmcs *vmcs02;
7918         bool ia32e;
7919
7920         if (!nested_vmx_check_permission(vcpu) ||
7921             !nested_vmx_check_vmcs12(vcpu))
7922                 return 1;
7923
7924         skip_emulated_instruction(vcpu);
7925         vmcs12 = get_vmcs12(vcpu);
7926
7927         if (enable_shadow_vmcs)
7928                 copy_shadow_to_vmcs12(vmx);
7929
7930         /*
7931          * The nested entry process starts with enforcing various prerequisites
7932          * on vmcs12 as required by the Intel SDM, and act appropriately when
7933          * they fail: As the SDM explains, some conditions should cause the
7934          * instruction to fail, while others will cause the instruction to seem
7935          * to succeed, but return an EXIT_REASON_INVALID_STATE.
7936          * To speed up the normal (success) code path, we should avoid checking
7937          * for misconfigurations which will anyway be caught by the processor
7938          * when using the merged vmcs02.
7939          */
7940         if (vmcs12->launch_state == launch) {
7941                 nested_vmx_failValid(vcpu,
7942                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7943                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7944                 return 1;
7945         }
7946
7947         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
7948             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
7949                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7950                 return 1;
7951         }
7952
7953         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7954                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7955                 /*TODO: Also verify bits beyond physical address width are 0*/
7956                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7957                 return 1;
7958         }
7959
7960         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7961                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7962                 /*TODO: Also verify bits beyond physical address width are 0*/
7963                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7964                 return 1;
7965         }
7966
7967         if (vmcs12->vm_entry_msr_load_count > 0 ||
7968             vmcs12->vm_exit_msr_load_count > 0 ||
7969             vmcs12->vm_exit_msr_store_count > 0) {
7970                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7971                                     __func__);
7972                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7973                 return 1;
7974         }
7975
7976         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7977               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7978             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7979               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7980             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7981               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7982             !vmx_control_verify(vmcs12->vm_exit_controls,
7983               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7984             !vmx_control_verify(vmcs12->vm_entry_controls,
7985               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7986         {
7987                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7988                 return 1;
7989         }
7990
7991         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7992             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7993                 nested_vmx_failValid(vcpu,
7994                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7995                 return 1;
7996         }
7997
7998         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7999             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8000                 nested_vmx_entry_failure(vcpu, vmcs12,
8001                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8002                 return 1;
8003         }
8004         if (vmcs12->vmcs_link_pointer != -1ull) {
8005                 nested_vmx_entry_failure(vcpu, vmcs12,
8006                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8007                 return 1;
8008         }
8009
8010         /*
8011          * If the load IA32_EFER VM-entry control is 1, the following checks
8012          * are performed on the field for the IA32_EFER MSR:
8013          * - Bits reserved in the IA32_EFER MSR must be 0.
8014          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8015          *   the IA-32e mode guest VM-exit control. It must also be identical
8016          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8017          *   CR0.PG) is 1.
8018          */
8019         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8020                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8021                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8022                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8023                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8024                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8025                         nested_vmx_entry_failure(vcpu, vmcs12,
8026                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8027                         return 1;
8028                 }
8029         }
8030
8031         /*
8032          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8033          * IA32_EFER MSR must be 0 in the field for that register. In addition,
8034          * the values of the LMA and LME bits in the field must each be that of
8035          * the host address-space size VM-exit control.
8036          */
8037         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8038                 ia32e = (vmcs12->vm_exit_controls &
8039                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8040                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8041                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8042                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8043                         nested_vmx_entry_failure(vcpu, vmcs12,
8044                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8045                         return 1;
8046                 }
8047         }
8048
8049         /*
8050          * We're finally done with prerequisite checking, and can start with
8051          * the nested entry.
8052          */
8053
8054         vmcs02 = nested_get_current_vmcs02(vmx);
8055         if (!vmcs02)
8056                 return -ENOMEM;
8057
8058         enter_guest_mode(vcpu);
8059
8060         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8061
8062         cpu = get_cpu();
8063         vmx->loaded_vmcs = vmcs02;
8064         vmx_vcpu_put(vcpu);
8065         vmx_vcpu_load(vcpu, cpu);
8066         vcpu->cpu = cpu;
8067         put_cpu();
8068
8069         vmx_segment_cache_clear(vmx);
8070
8071         vmcs12->launch_state = 1;
8072
8073         prepare_vmcs02(vcpu, vmcs12);
8074
8075         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8076                 return kvm_emulate_halt(vcpu);
8077
8078         vmx->nested.nested_run_pending = 1;
8079
8080         /*
8081          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8082          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8083          * returned as far as L1 is concerned. It will only return (and set
8084          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8085          */
8086         return 1;
8087 }
8088
8089 /*
8090  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8091  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8092  * This function returns the new value we should put in vmcs12.guest_cr0.
8093  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8094  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8095  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8096  *     didn't trap the bit, because if L1 did, so would L0).
8097  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8098  *     been modified by L2, and L1 knows it. So just leave the old value of
8099  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8100  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8101  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8102  *     changed these bits, and therefore they need to be updated, but L0
8103  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8104  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8105  */
8106 static inline unsigned long
8107 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8108 {
8109         return
8110         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8111         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8112         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8113                         vcpu->arch.cr0_guest_owned_bits));
8114 }
8115
8116 static inline unsigned long
8117 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8118 {
8119         return
8120         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8121         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8122         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8123                         vcpu->arch.cr4_guest_owned_bits));
8124 }
8125
8126 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8127                                        struct vmcs12 *vmcs12)
8128 {
8129         u32 idt_vectoring;
8130         unsigned int nr;
8131
8132         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8133                 nr = vcpu->arch.exception.nr;
8134                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8135
8136                 if (kvm_exception_is_soft(nr)) {
8137                         vmcs12->vm_exit_instruction_len =
8138                                 vcpu->arch.event_exit_inst_len;
8139                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8140                 } else
8141                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8142
8143                 if (vcpu->arch.exception.has_error_code) {
8144                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8145                         vmcs12->idt_vectoring_error_code =
8146                                 vcpu->arch.exception.error_code;
8147                 }
8148
8149                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8150         } else if (vcpu->arch.nmi_injected) {
8151                 vmcs12->idt_vectoring_info_field =
8152                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8153         } else if (vcpu->arch.interrupt.pending) {
8154                 nr = vcpu->arch.interrupt.nr;
8155                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8156
8157                 if (vcpu->arch.interrupt.soft) {
8158                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8159                         vmcs12->vm_entry_instruction_len =
8160                                 vcpu->arch.event_exit_inst_len;
8161                 } else
8162                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8163
8164                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8165         }
8166 }
8167
8168 /*
8169  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8170  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8171  * and this function updates it to reflect the changes to the guest state while
8172  * L2 was running (and perhaps made some exits which were handled directly by L0
8173  * without going back to L1), and to reflect the exit reason.
8174  * Note that we do not have to copy here all VMCS fields, just those that
8175  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8176  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8177  * which already writes to vmcs12 directly.
8178  */
8179 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8180                            u32 exit_reason, u32 exit_intr_info,
8181                            unsigned long exit_qualification)
8182 {
8183         /* update guest state fields: */
8184         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8185         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8186
8187         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8188         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8189         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8190         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8191
8192         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8193         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8194         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8195         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8196         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8197         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8198         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8199         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8200         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8201         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8202         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8203         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8204         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8205         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8206         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8207         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8208         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8209         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8210         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8211         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8212         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8213         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8214         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8215         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8216         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8217         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8218         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8219         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8220         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8221         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8222         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8223         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8224         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8225         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8226         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8227         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8228
8229         vmcs12->guest_interruptibility_info =
8230                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8231         vmcs12->guest_pending_dbg_exceptions =
8232                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8233         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8234                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8235         else
8236                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8237
8238         if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
8239             (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
8240                 vmcs12->vmx_preemption_timer_value =
8241                         vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
8242
8243         /*
8244          * In some cases (usually, nested EPT), L2 is allowed to change its
8245          * own CR3 without exiting. If it has changed it, we must keep it.
8246          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8247          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8248          *
8249          * Additionally, restore L2's PDPTR to vmcs12.
8250          */
8251         if (enable_ept) {
8252                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8253                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8254                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8255                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8256                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8257         }
8258
8259         vmcs12->vm_entry_controls =
8260                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8261                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8262
8263         /* TODO: These cannot have changed unless we have MSR bitmaps and
8264          * the relevant bit asks not to trap the change */
8265         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8266         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8267                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8268         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8269                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8270         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8271         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8272         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8273
8274         /* update exit information fields: */
8275
8276         vmcs12->vm_exit_reason = exit_reason;
8277         vmcs12->exit_qualification = exit_qualification;
8278
8279         vmcs12->vm_exit_intr_info = exit_intr_info;
8280         if ((vmcs12->vm_exit_intr_info &
8281              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8282             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8283                 vmcs12->vm_exit_intr_error_code =
8284                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8285         vmcs12->idt_vectoring_info_field = 0;
8286         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8287         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8288
8289         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8290                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8291                  * instead of reading the real value. */
8292                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8293
8294                 /*
8295                  * Transfer the event that L0 or L1 may wanted to inject into
8296                  * L2 to IDT_VECTORING_INFO_FIELD.
8297                  */
8298                 vmcs12_save_pending_event(vcpu, vmcs12);
8299         }
8300
8301         /*
8302          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8303          * preserved above and would only end up incorrectly in L1.
8304          */
8305         vcpu->arch.nmi_injected = false;
8306         kvm_clear_exception_queue(vcpu);
8307         kvm_clear_interrupt_queue(vcpu);
8308 }
8309
8310 /*
8311  * A part of what we need to when the nested L2 guest exits and we want to
8312  * run its L1 parent, is to reset L1's guest state to the host state specified
8313  * in vmcs12.
8314  * This function is to be called not only on normal nested exit, but also on
8315  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8316  * Failures During or After Loading Guest State").
8317  * This function should be called when the active VMCS is L1's (vmcs01).
8318  */
8319 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8320                                    struct vmcs12 *vmcs12)
8321 {
8322         struct kvm_segment seg;
8323
8324         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8325                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8326         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8327                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8328         else
8329                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8330         vmx_set_efer(vcpu, vcpu->arch.efer);
8331
8332         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8333         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8334         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8335         /*
8336          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8337          * actually changed, because it depends on the current state of
8338          * fpu_active (which may have changed).
8339          * Note that vmx_set_cr0 refers to efer set above.
8340          */
8341         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8342         /*
8343          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8344          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8345          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8346          */
8347         update_exception_bitmap(vcpu);
8348         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8349         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8350
8351         /*
8352          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8353          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8354          */
8355         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8356         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8357
8358         nested_ept_uninit_mmu_context(vcpu);
8359
8360         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8361         kvm_mmu_reset_context(vcpu);
8362
8363         if (!enable_ept)
8364                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8365
8366         if (enable_vpid) {
8367                 /*
8368                  * Trivially support vpid by letting L2s share their parent
8369                  * L1's vpid. TODO: move to a more elaborate solution, giving
8370                  * each L2 its own vpid and exposing the vpid feature to L1.
8371                  */
8372                 vmx_flush_tlb(vcpu);
8373         }
8374
8375
8376         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8377         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8378         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8379         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8380         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8381
8382         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8383                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8384                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8385         }
8386         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8387                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8388                         vmcs12->host_ia32_perf_global_ctrl);
8389
8390         /* Set L1 segment info according to Intel SDM
8391             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8392         seg = (struct kvm_segment) {
8393                 .base = 0,
8394                 .limit = 0xFFFFFFFF,
8395                 .selector = vmcs12->host_cs_selector,
8396                 .type = 11,
8397                 .present = 1,
8398                 .s = 1,
8399                 .g = 1
8400         };
8401         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8402                 seg.l = 1;
8403         else
8404                 seg.db = 1;
8405         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8406         seg = (struct kvm_segment) {
8407                 .base = 0,
8408                 .limit = 0xFFFFFFFF,
8409                 .type = 3,
8410                 .present = 1,
8411                 .s = 1,
8412                 .db = 1,
8413                 .g = 1
8414         };
8415         seg.selector = vmcs12->host_ds_selector;
8416         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8417         seg.selector = vmcs12->host_es_selector;
8418         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8419         seg.selector = vmcs12->host_ss_selector;
8420         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8421         seg.selector = vmcs12->host_fs_selector;
8422         seg.base = vmcs12->host_fs_base;
8423         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8424         seg.selector = vmcs12->host_gs_selector;
8425         seg.base = vmcs12->host_gs_base;
8426         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8427         seg = (struct kvm_segment) {
8428                 .base = vmcs12->host_tr_base,
8429                 .limit = 0x67,
8430                 .selector = vmcs12->host_tr_selector,
8431                 .type = 11,
8432                 .present = 1
8433         };
8434         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8435
8436         kvm_set_dr(vcpu, 7, 0x400);
8437         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8438 }
8439
8440 /*
8441  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8442  * and modify vmcs12 to make it see what it would expect to see there if
8443  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8444  */
8445 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8446                               u32 exit_intr_info,
8447                               unsigned long exit_qualification)
8448 {
8449         struct vcpu_vmx *vmx = to_vmx(vcpu);
8450         int cpu;
8451         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8452
8453         /* trying to cancel vmlaunch/vmresume is a bug */
8454         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8455
8456         leave_guest_mode(vcpu);
8457         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8458                        exit_qualification);
8459
8460         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8461                                        vmcs12->exit_qualification,
8462                                        vmcs12->idt_vectoring_info_field,
8463                                        vmcs12->vm_exit_intr_info,
8464                                        vmcs12->vm_exit_intr_error_code,
8465                                        KVM_ISA_VMX);
8466
8467         cpu = get_cpu();
8468         vmx->loaded_vmcs = &vmx->vmcs01;
8469         vmx_vcpu_put(vcpu);
8470         vmx_vcpu_load(vcpu, cpu);
8471         vcpu->cpu = cpu;
8472         put_cpu();
8473
8474         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8475         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
8476         vmx_segment_cache_clear(vmx);
8477
8478         /* if no vmcs02 cache requested, remove the one we used */
8479         if (VMCS02_POOL_SIZE == 0)
8480                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8481
8482         load_vmcs12_host_state(vcpu, vmcs12);
8483
8484         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8485         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8486
8487         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8488         vmx->host_rsp = 0;
8489
8490         /* Unpin physical memory we referred to in vmcs02 */
8491         if (vmx->nested.apic_access_page) {
8492                 nested_release_page(vmx->nested.apic_access_page);
8493                 vmx->nested.apic_access_page = 0;
8494         }
8495
8496         /*
8497          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8498          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8499          * success or failure flag accordingly.
8500          */
8501         if (unlikely(vmx->fail)) {
8502                 vmx->fail = 0;
8503                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8504         } else
8505                 nested_vmx_succeed(vcpu);
8506         if (enable_shadow_vmcs)
8507                 vmx->nested.sync_shadow_vmcs = true;
8508 }
8509
8510 /*
8511  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8512  */
8513 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8514 {
8515         if (is_guest_mode(vcpu))
8516                 nested_vmx_vmexit(vcpu, -1, 0, 0);
8517         free_nested(to_vmx(vcpu));
8518 }
8519
8520 /*
8521  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8522  * 23.7 "VM-entry failures during or after loading guest state" (this also
8523  * lists the acceptable exit-reason and exit-qualification parameters).
8524  * It should only be called before L2 actually succeeded to run, and when
8525  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8526  */
8527 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8528                         struct vmcs12 *vmcs12,
8529                         u32 reason, unsigned long qualification)
8530 {
8531         load_vmcs12_host_state(vcpu, vmcs12);
8532         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8533         vmcs12->exit_qualification = qualification;
8534         nested_vmx_succeed(vcpu);
8535         if (enable_shadow_vmcs)
8536                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8537 }
8538
8539 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8540                                struct x86_instruction_info *info,
8541                                enum x86_intercept_stage stage)
8542 {
8543         return X86EMUL_CONTINUE;
8544 }
8545
8546 static struct kvm_x86_ops vmx_x86_ops = {
8547         .cpu_has_kvm_support = cpu_has_kvm_support,
8548         .disabled_by_bios = vmx_disabled_by_bios,
8549         .hardware_setup = hardware_setup,
8550         .hardware_unsetup = hardware_unsetup,
8551         .check_processor_compatibility = vmx_check_processor_compat,
8552         .hardware_enable = hardware_enable,
8553         .hardware_disable = hardware_disable,
8554         .cpu_has_accelerated_tpr = report_flexpriority,
8555
8556         .vcpu_create = vmx_create_vcpu,
8557         .vcpu_free = vmx_free_vcpu,
8558         .vcpu_reset = vmx_vcpu_reset,
8559
8560         .prepare_guest_switch = vmx_save_host_state,
8561         .vcpu_load = vmx_vcpu_load,
8562         .vcpu_put = vmx_vcpu_put,
8563
8564         .update_db_bp_intercept = update_exception_bitmap,
8565         .get_msr = vmx_get_msr,
8566         .set_msr = vmx_set_msr,
8567         .get_segment_base = vmx_get_segment_base,
8568         .get_segment = vmx_get_segment,
8569         .set_segment = vmx_set_segment,
8570         .get_cpl = vmx_get_cpl,
8571         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8572         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8573         .decache_cr3 = vmx_decache_cr3,
8574         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8575         .set_cr0 = vmx_set_cr0,
8576         .set_cr3 = vmx_set_cr3,
8577         .set_cr4 = vmx_set_cr4,
8578         .set_efer = vmx_set_efer,
8579         .get_idt = vmx_get_idt,
8580         .set_idt = vmx_set_idt,
8581         .get_gdt = vmx_get_gdt,
8582         .set_gdt = vmx_set_gdt,
8583         .get_dr6 = vmx_get_dr6,
8584         .set_dr6 = vmx_set_dr6,
8585         .set_dr7 = vmx_set_dr7,
8586         .cache_reg = vmx_cache_reg,
8587         .get_rflags = vmx_get_rflags,
8588         .set_rflags = vmx_set_rflags,
8589         .fpu_activate = vmx_fpu_activate,
8590         .fpu_deactivate = vmx_fpu_deactivate,
8591
8592         .tlb_flush = vmx_flush_tlb,
8593
8594         .run = vmx_vcpu_run,
8595         .handle_exit = vmx_handle_exit,
8596         .skip_emulated_instruction = skip_emulated_instruction,
8597         .set_interrupt_shadow = vmx_set_interrupt_shadow,
8598         .get_interrupt_shadow = vmx_get_interrupt_shadow,
8599         .patch_hypercall = vmx_patch_hypercall,
8600         .set_irq = vmx_inject_irq,
8601         .set_nmi = vmx_inject_nmi,
8602         .queue_exception = vmx_queue_exception,
8603         .cancel_injection = vmx_cancel_injection,
8604         .interrupt_allowed = vmx_interrupt_allowed,
8605         .nmi_allowed = vmx_nmi_allowed,
8606         .get_nmi_mask = vmx_get_nmi_mask,
8607         .set_nmi_mask = vmx_set_nmi_mask,
8608         .enable_nmi_window = enable_nmi_window,
8609         .enable_irq_window = enable_irq_window,
8610         .update_cr8_intercept = update_cr8_intercept,
8611         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
8612         .vm_has_apicv = vmx_vm_has_apicv,
8613         .load_eoi_exitmap = vmx_load_eoi_exitmap,
8614         .hwapic_irr_update = vmx_hwapic_irr_update,
8615         .hwapic_isr_update = vmx_hwapic_isr_update,
8616         .sync_pir_to_irr = vmx_sync_pir_to_irr,
8617         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
8618
8619         .set_tss_addr = vmx_set_tss_addr,
8620         .get_tdp_level = get_ept_level,
8621         .get_mt_mask = vmx_get_mt_mask,
8622
8623         .get_exit_info = vmx_get_exit_info,
8624
8625         .get_lpage_level = vmx_get_lpage_level,
8626
8627         .cpuid_update = vmx_cpuid_update,
8628
8629         .rdtscp_supported = vmx_rdtscp_supported,
8630         .invpcid_supported = vmx_invpcid_supported,
8631
8632         .set_supported_cpuid = vmx_set_supported_cpuid,
8633
8634         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
8635
8636         .set_tsc_khz = vmx_set_tsc_khz,
8637         .read_tsc_offset = vmx_read_tsc_offset,
8638         .write_tsc_offset = vmx_write_tsc_offset,
8639         .adjust_tsc_offset = vmx_adjust_tsc_offset,
8640         .compute_tsc_offset = vmx_compute_tsc_offset,
8641         .read_l1_tsc = vmx_read_l1_tsc,
8642
8643         .set_tdp_cr3 = vmx_set_cr3,
8644
8645         .check_intercept = vmx_check_intercept,
8646         .handle_external_intr = vmx_handle_external_intr,
8647 };
8648
8649 static int __init vmx_init(void)
8650 {
8651         int r, i, msr;
8652
8653         rdmsrl_safe(MSR_EFER, &host_efer);
8654
8655         for (i = 0; i < NR_VMX_MSR; ++i)
8656                 kvm_define_shared_msr(i, vmx_msr_index[i]);
8657
8658         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
8659         if (!vmx_io_bitmap_a)
8660                 return -ENOMEM;
8661
8662         r = -ENOMEM;
8663
8664         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
8665         if (!vmx_io_bitmap_b)
8666                 goto out;
8667
8668         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
8669         if (!vmx_msr_bitmap_legacy)
8670                 goto out1;
8671
8672         vmx_msr_bitmap_legacy_x2apic =
8673                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8674         if (!vmx_msr_bitmap_legacy_x2apic)
8675                 goto out2;
8676
8677         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
8678         if (!vmx_msr_bitmap_longmode)
8679                 goto out3;
8680
8681         vmx_msr_bitmap_longmode_x2apic =
8682                                 (unsigned long *)__get_free_page(GFP_KERNEL);
8683         if (!vmx_msr_bitmap_longmode_x2apic)
8684                 goto out4;
8685         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8686         if (!vmx_vmread_bitmap)
8687                 goto out5;
8688
8689         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8690         if (!vmx_vmwrite_bitmap)
8691                 goto out6;
8692
8693         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8694         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8695         /* shadowed read/write fields */
8696         for (i = 0; i < max_shadow_read_write_fields; i++) {
8697                 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8698                 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8699         }
8700         /* shadowed read only fields */
8701         for (i = 0; i < max_shadow_read_only_fields; i++)
8702                 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
8703
8704         /*
8705          * Allow direct access to the PC debug port (it is often used for I/O
8706          * delays, but the vmexits simply slow things down).
8707          */
8708         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8709         clear_bit(0x80, vmx_io_bitmap_a);
8710
8711         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
8712
8713         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8714         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
8715
8716         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8717
8718         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8719                      __alignof__(struct vcpu_vmx), THIS_MODULE);
8720         if (r)
8721                 goto out7;
8722
8723 #ifdef CONFIG_KEXEC
8724         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8725                            crash_vmclear_local_loaded_vmcss);
8726 #endif
8727
8728         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8729         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8730         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8731         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8732         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8733         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8734         memcpy(vmx_msr_bitmap_legacy_x2apic,
8735                         vmx_msr_bitmap_legacy, PAGE_SIZE);
8736         memcpy(vmx_msr_bitmap_longmode_x2apic,
8737                         vmx_msr_bitmap_longmode, PAGE_SIZE);
8738
8739         if (enable_apicv) {
8740                 for (msr = 0x800; msr <= 0x8ff; msr++)
8741                         vmx_disable_intercept_msr_read_x2apic(msr);
8742
8743                 /* According SDM, in x2apic mode, the whole id reg is used.
8744                  * But in KVM, it only use the highest eight bits. Need to
8745                  * intercept it */
8746                 vmx_enable_intercept_msr_read_x2apic(0x802);
8747                 /* TMCCT */
8748                 vmx_enable_intercept_msr_read_x2apic(0x839);
8749                 /* TPR */
8750                 vmx_disable_intercept_msr_write_x2apic(0x808);
8751                 /* EOI */
8752                 vmx_disable_intercept_msr_write_x2apic(0x80b);
8753                 /* SELF-IPI */
8754                 vmx_disable_intercept_msr_write_x2apic(0x83f);
8755         }
8756
8757         if (enable_ept) {
8758                 kvm_mmu_set_mask_ptes(0ull,
8759                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8760                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8761                         0ull, VMX_EPT_EXECUTABLE_MASK);
8762                 ept_set_mmio_spte_mask();
8763                 kvm_enable_tdp();
8764         } else
8765                 kvm_disable_tdp();
8766
8767         return 0;
8768
8769 out7:
8770         free_page((unsigned long)vmx_vmwrite_bitmap);
8771 out6:
8772         free_page((unsigned long)vmx_vmread_bitmap);
8773 out5:
8774         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8775 out4:
8776         free_page((unsigned long)vmx_msr_bitmap_longmode);
8777 out3:
8778         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8779 out2:
8780         free_page((unsigned long)vmx_msr_bitmap_legacy);
8781 out1:
8782         free_page((unsigned long)vmx_io_bitmap_b);
8783 out:
8784         free_page((unsigned long)vmx_io_bitmap_a);
8785         return r;
8786 }
8787
8788 static void __exit vmx_exit(void)
8789 {
8790         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8791         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8792         free_page((unsigned long)vmx_msr_bitmap_legacy);
8793         free_page((unsigned long)vmx_msr_bitmap_longmode);
8794         free_page((unsigned long)vmx_io_bitmap_b);
8795         free_page((unsigned long)vmx_io_bitmap_a);
8796         free_page((unsigned long)vmx_vmwrite_bitmap);
8797         free_page((unsigned long)vmx_vmread_bitmap);
8798
8799 #ifdef CONFIG_KEXEC
8800         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8801         synchronize_rcu();
8802 #endif
8803
8804         kvm_exit();
8805 }
8806
8807 module_init(vmx_init)
8808 module_exit(vmx_exit)