arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include "kvm_cache_regs.h"
  38 #include "x86.h"
  39
  40 #include <asm/cpu.h>
  41 #include <asm/io.h>
  42 #include <asm/desc.h>
  43 #include <asm/vmx.h>
  44 #include <asm/virtext.h>
  45 #include <asm/mce.h>
  46 #include <asm/fpu/internal.h>
  47 #include <asm/perf_event.h>
  48 #include <asm/debugreg.h>
  49 #include <asm/kexec.h>
  50 #include <asm/apic.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/mmu_context.h>
  53
  54 #include "trace.h"
  55 #include "pmu.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58 #define __ex_clear(x, reg) \
  59         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  60
  61 MODULE_AUTHOR("Qumranet");
  62 MODULE_LICENSE("GPL");
  63
  64 static const struct x86_cpu_id vmx_cpu_id[] = {
  65         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  66         {}
  67 };
  68 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  69
  70 static bool __read_mostly enable_vpid = 1;
  71 module_param_named(vpid, enable_vpid, bool, 0444);
  72
  73 static bool __read_mostly flexpriority_enabled = 1;
  74 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_ept = 1;
  77 module_param_named(ept, enable_ept, bool, S_IRUGO);
  78
  79 static bool __read_mostly enable_unrestricted_guest = 1;
  80 module_param_named(unrestricted_guest,
  81                         enable_unrestricted_guest, bool, S_IRUGO);
  82
  83 static bool __read_mostly enable_ept_ad_bits = 1;
  84 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  85
  86 static bool __read_mostly emulate_invalid_guest_state = true;
  87 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 113 static int __read_mostly cpu_preemption_timer_multi;
 114 static bool __read_mostly enable_preemption_timer = 1;
 115 #ifdef CONFIG_X86_64
 116 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 117 #endif
 118
 119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 121 #define KVM_VM_CR0_ALWAYS_ON                                            \
 122         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 123 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 124         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 125          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
 126
 127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 129
 130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 131
 132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 133
 134 /*
 135  * Hyper-V requires all of these, so mark them as supported even though
 136  * they are just treated the same as all-context.
 137  */
 138 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 139         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 140         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 141         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 143
 144 /*
 145  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 146  * ple_gap:    upper bound on the amount of time between two successive
 147  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 148  *             According to test, this time is usually smaller than 128 cycles.
 149  * ple_window: upper bound on the amount of time a guest is allowed to execute
 150  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 151  *             less than 2^12 cycles
 152  * Time is measured based on a counter that runs at the same rate as the TSC,
 153  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 154  */
 155 #define KVM_VMX_DEFAULT_PLE_GAP           128
 156 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 160                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 161
 162 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 163 module_param(ple_gap, int, S_IRUGO);
 164
 165 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 166 module_param(ple_window, int, S_IRUGO);
 167
 168 /* Default doubles per-vcpu window every exit. */
 169 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 170 module_param(ple_window_grow, int, S_IRUGO);
 171
 172 /* Default resets per-vcpu window every exit to ple_window. */
 173 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 174 module_param(ple_window_shrink, int, S_IRUGO);
 175
 176 /* Default is to compute the maximum so we can never overflow. */
 177 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 178 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, int, S_IRUGO);
 180
 181 extern const ulong vmx_return;
 182
 183 #define NR_AUTOLOAD_MSRS 8
 184 #define VMCS02_POOL_SIZE 1
 185
 186 struct vmcs {
 187         u32 revision_id;
 188         u32 abort;
 189         char data[0];
 190 };
 191
 192 /*
 193  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 194  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 195  * loaded on this CPU (so we can clear them if the CPU goes down).
 196  */
 197 struct loaded_vmcs {
 198         struct vmcs *vmcs;
 199         struct vmcs *shadow_vmcs;
 200         int cpu;
 201         bool launched;
 202         bool nmi_known_unmasked;
 203         unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 204         unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 205         struct list_head loaded_vmcss_on_cpu_link;
 206 };
 207
 208 struct shared_msr_entry {
 209         unsigned index;
 210         u64 data;
 211         u64 mask;
 212 };
 213
 214 /*
 215  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 216  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 217  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 218  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 219  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 220  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 221  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 222  * underlying hardware which will be used to run L2.
 223  * This structure is packed to ensure that its layout is identical across
 224  * machines (necessary for live migration).
 225  * If there are changes in this struct, VMCS12_REVISION must be changed.
 226  */
 227 typedef u64 natural_width;
 228 struct __packed vmcs12 {
 229         /* According to the Intel spec, a VMCS region must start with the
 230          * following two fields. Then follow implementation-specific data.
 231          */
 232         u32 revision_id;
 233         u32 abort;
 234
 235         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 236         u32 padding[7]; /* room for future expansion */
 237
 238         u64 io_bitmap_a;
 239         u64 io_bitmap_b;
 240         u64 msr_bitmap;
 241         u64 vm_exit_msr_store_addr;
 242         u64 vm_exit_msr_load_addr;
 243         u64 vm_entry_msr_load_addr;
 244         u64 tsc_offset;
 245         u64 virtual_apic_page_addr;
 246         u64 apic_access_addr;
 247         u64 posted_intr_desc_addr;
 248         u64 vm_function_control;
 249         u64 ept_pointer;
 250         u64 eoi_exit_bitmap0;
 251         u64 eoi_exit_bitmap1;
 252         u64 eoi_exit_bitmap2;
 253         u64 eoi_exit_bitmap3;
 254         u64 eptp_list_address;
 255         u64 xss_exit_bitmap;
 256         u64 guest_physical_address;
 257         u64 vmcs_link_pointer;
 258         u64 pml_address;
 259         u64 guest_ia32_debugctl;
 260         u64 guest_ia32_pat;
 261         u64 guest_ia32_efer;
 262         u64 guest_ia32_perf_global_ctrl;
 263         u64 guest_pdptr0;
 264         u64 guest_pdptr1;
 265         u64 guest_pdptr2;
 266         u64 guest_pdptr3;
 267         u64 guest_bndcfgs;
 268         u64 host_ia32_pat;
 269         u64 host_ia32_efer;
 270         u64 host_ia32_perf_global_ctrl;
 271         u64 padding64[8]; /* room for future expansion */
 272         /*
 273          * To allow migration of L1 (complete with its L2 guests) between
 274          * machines of different natural widths (32 or 64 bit), we cannot have
 275          * unsigned long fields with no explict size. We use u64 (aliased
 276          * natural_width) instead. Luckily, x86 is little-endian.
 277          */
 278         natural_width cr0_guest_host_mask;
 279         natural_width cr4_guest_host_mask;
 280         natural_width cr0_read_shadow;
 281         natural_width cr4_read_shadow;
 282         natural_width cr3_target_value0;
 283         natural_width cr3_target_value1;
 284         natural_width cr3_target_value2;
 285         natural_width cr3_target_value3;
 286         natural_width exit_qualification;
 287         natural_width guest_linear_address;
 288         natural_width guest_cr0;
 289         natural_width guest_cr3;
 290         natural_width guest_cr4;
 291         natural_width guest_es_base;
 292         natural_width guest_cs_base;
 293         natural_width guest_ss_base;
 294         natural_width guest_ds_base;
 295         natural_width guest_fs_base;
 296         natural_width guest_gs_base;
 297         natural_width guest_ldtr_base;
 298         natural_width guest_tr_base;
 299         natural_width guest_gdtr_base;
 300         natural_width guest_idtr_base;
 301         natural_width guest_dr7;
 302         natural_width guest_rsp;
 303         natural_width guest_rip;
 304         natural_width guest_rflags;
 305         natural_width guest_pending_dbg_exceptions;
 306         natural_width guest_sysenter_esp;
 307         natural_width guest_sysenter_eip;
 308         natural_width host_cr0;
 309         natural_width host_cr3;
 310         natural_width host_cr4;
 311         natural_width host_fs_base;
 312         natural_width host_gs_base;
 313         natural_width host_tr_base;
 314         natural_width host_gdtr_base;
 315         natural_width host_idtr_base;
 316         natural_width host_ia32_sysenter_esp;
 317         natural_width host_ia32_sysenter_eip;
 318         natural_width host_rsp;
 319         natural_width host_rip;
 320         natural_width paddingl[8]; /* room for future expansion */
 321         u32 pin_based_vm_exec_control;
 322         u32 cpu_based_vm_exec_control;
 323         u32 exception_bitmap;
 324         u32 page_fault_error_code_mask;
 325         u32 page_fault_error_code_match;
 326         u32 cr3_target_count;
 327         u32 vm_exit_controls;
 328         u32 vm_exit_msr_store_count;
 329         u32 vm_exit_msr_load_count;
 330         u32 vm_entry_controls;
 331         u32 vm_entry_msr_load_count;
 332         u32 vm_entry_intr_info_field;
 333         u32 vm_entry_exception_error_code;
 334         u32 vm_entry_instruction_len;
 335         u32 tpr_threshold;
 336         u32 secondary_vm_exec_control;
 337         u32 vm_instruction_error;
 338         u32 vm_exit_reason;
 339         u32 vm_exit_intr_info;
 340         u32 vm_exit_intr_error_code;
 341         u32 idt_vectoring_info_field;
 342         u32 idt_vectoring_error_code;
 343         u32 vm_exit_instruction_len;
 344         u32 vmx_instruction_info;
 345         u32 guest_es_limit;
 346         u32 guest_cs_limit;
 347         u32 guest_ss_limit;
 348         u32 guest_ds_limit;
 349         u32 guest_fs_limit;
 350         u32 guest_gs_limit;
 351         u32 guest_ldtr_limit;
 352         u32 guest_tr_limit;
 353         u32 guest_gdtr_limit;
 354         u32 guest_idtr_limit;
 355         u32 guest_es_ar_bytes;
 356         u32 guest_cs_ar_bytes;
 357         u32 guest_ss_ar_bytes;
 358         u32 guest_ds_ar_bytes;
 359         u32 guest_fs_ar_bytes;
 360         u32 guest_gs_ar_bytes;
 361         u32 guest_ldtr_ar_bytes;
 362         u32 guest_tr_ar_bytes;
 363         u32 guest_interruptibility_info;
 364         u32 guest_activity_state;
 365         u32 guest_sysenter_cs;
 366         u32 host_ia32_sysenter_cs;
 367         u32 vmx_preemption_timer_value;
 368         u32 padding32[7]; /* room for future expansion */
 369         u16 virtual_processor_id;
 370         u16 posted_intr_nv;
 371         u16 guest_es_selector;
 372         u16 guest_cs_selector;
 373         u16 guest_ss_selector;
 374         u16 guest_ds_selector;
 375         u16 guest_fs_selector;
 376         u16 guest_gs_selector;
 377         u16 guest_ldtr_selector;
 378         u16 guest_tr_selector;
 379         u16 guest_intr_status;
 380         u16 guest_pml_index;
 381         u16 host_es_selector;
 382         u16 host_cs_selector;
 383         u16 host_ss_selector;
 384         u16 host_ds_selector;
 385         u16 host_fs_selector;
 386         u16 host_gs_selector;
 387         u16 host_tr_selector;
 388 };
 389
 390 /*
 391  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 392  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 393  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 394  */
 395 #define VMCS12_REVISION 0x11e57ed0
 396
 397 /*
 398  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 399  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 400  * current implementation, 4K are reserved to avoid future complications.
 401  */
 402 #define VMCS12_SIZE 0x1000
 403
 404 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 405 struct vmcs02_list {
 406         struct list_head list;
 407         gpa_t vmptr;
 408         struct loaded_vmcs vmcs02;
 409 };
 410
 411 /*
 412  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 413  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 414  */
 415 struct nested_vmx {
 416         /* Has the level1 guest done vmxon? */
 417         bool vmxon;
 418         gpa_t vmxon_ptr;
 419         bool pml_full;
 420
 421         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 422         gpa_t current_vmptr;
 423         /*
 424          * Cache of the guest's VMCS, existing outside of guest memory.
 425          * Loaded from guest memory during VMPTRLD. Flushed to guest
 426          * memory during VMCLEAR and VMPTRLD.
 427          */
 428         struct vmcs12 *cached_vmcs12;
 429         /*
 430          * Indicates if the shadow vmcs must be updated with the
 431          * data hold by vmcs12
 432          */
 433         bool sync_shadow_vmcs;
 434
 435         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 436         struct list_head vmcs02_pool;
 437         int vmcs02_num;
 438         bool change_vmcs01_virtual_x2apic_mode;
 439         /* L2 must run next, and mustn't decide to exit to L1. */
 440         bool nested_run_pending;
 441         /*
 442          * Guest pages referred to in vmcs02 with host-physical pointers, so
 443          * we must keep them pinned while L2 runs.
 444          */
 445         struct page *apic_access_page;
 446         struct page *virtual_apic_page;
 447         struct page *pi_desc_page;
 448         struct pi_desc *pi_desc;
 449         bool pi_pending;
 450         u16 posted_intr_nv;
 451
 452         unsigned long *msr_bitmap;
 453
 454         struct hrtimer preemption_timer;
 455         bool preemption_timer_expired;
 456
 457         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 458         u64 vmcs01_debugctl;
 459
 460         u16 vpid02;
 461         u16 last_vpid;
 462
 463         /*
 464          * We only store the "true" versions of the VMX capability MSRs. We
 465          * generate the "non-true" versions by setting the must-be-1 bits
 466          * according to the SDM.
 467          */
 468         u32 nested_vmx_procbased_ctls_low;
 469         u32 nested_vmx_procbased_ctls_high;
 470         u32 nested_vmx_secondary_ctls_low;
 471         u32 nested_vmx_secondary_ctls_high;
 472         u32 nested_vmx_pinbased_ctls_low;
 473         u32 nested_vmx_pinbased_ctls_high;
 474         u32 nested_vmx_exit_ctls_low;
 475         u32 nested_vmx_exit_ctls_high;
 476         u32 nested_vmx_entry_ctls_low;
 477         u32 nested_vmx_entry_ctls_high;
 478         u32 nested_vmx_misc_low;
 479         u32 nested_vmx_misc_high;
 480         u32 nested_vmx_ept_caps;
 481         u32 nested_vmx_vpid_caps;
 482         u64 nested_vmx_basic;
 483         u64 nested_vmx_cr0_fixed0;
 484         u64 nested_vmx_cr0_fixed1;
 485         u64 nested_vmx_cr4_fixed0;
 486         u64 nested_vmx_cr4_fixed1;
 487         u64 nested_vmx_vmcs_enum;
 488         u64 nested_vmx_vmfunc_controls;
 489 };
 490
 491 #define POSTED_INTR_ON  0
 492 #define POSTED_INTR_SN  1
 493
 494 /* Posted-Interrupt Descriptor */
 495 struct pi_desc {
 496         u32 pir[8];     /* Posted interrupt requested */
 497         union {
 498                 struct {
 499                                 /* bit 256 - Outstanding Notification */
 500                         u16     on      : 1,
 501                                 /* bit 257 - Suppress Notification */
 502                                 sn      : 1,
 503                                 /* bit 271:258 - Reserved */
 504                                 rsvd_1  : 14;
 505                                 /* bit 279:272 - Notification Vector */
 506                         u8      nv;
 507                                 /* bit 287:280 - Reserved */
 508                         u8      rsvd_2;
 509                                 /* bit 319:288 - Notification Destination */
 510                         u32     ndst;
 511                 };
 512                 u64 control;
 513         };
 514         u32 rsvd[6];
 515 } __aligned(64);
 516
 517 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 518 {
 519         return test_and_set_bit(POSTED_INTR_ON,
 520                         (unsigned long *)&pi_desc->control);
 521 }
 522
 523 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 524 {
 525         return test_and_clear_bit(POSTED_INTR_ON,
 526                         (unsigned long *)&pi_desc->control);
 527 }
 528
 529 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 530 {
 531         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 532 }
 533
 534 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 535 {
 536         return clear_bit(POSTED_INTR_SN,
 537                         (unsigned long *)&pi_desc->control);
 538 }
 539
 540 static inline void pi_set_sn(struct pi_desc *pi_desc)
 541 {
 542         return set_bit(POSTED_INTR_SN,
 543                         (unsigned long *)&pi_desc->control);
 544 }
 545
 546 static inline void pi_clear_on(struct pi_desc *pi_desc)
 547 {
 548         clear_bit(POSTED_INTR_ON,
 549                   (unsigned long *)&pi_desc->control);
 550 }
 551
 552 static inline int pi_test_on(struct pi_desc *pi_desc)
 553 {
 554         return test_bit(POSTED_INTR_ON,
 555                         (unsigned long *)&pi_desc->control);
 556 }
 557
 558 static inline int pi_test_sn(struct pi_desc *pi_desc)
 559 {
 560         return test_bit(POSTED_INTR_SN,
 561                         (unsigned long *)&pi_desc->control);
 562 }
 563
 564 struct vcpu_vmx {
 565         struct kvm_vcpu       vcpu;
 566         unsigned long         host_rsp;
 567         u8                    fail;
 568         u32                   exit_intr_info;
 569         u32                   idt_vectoring_info;
 570         ulong                 rflags;
 571         struct shared_msr_entry *guest_msrs;
 572         int                   nmsrs;
 573         int                   save_nmsrs;
 574         unsigned long         host_idt_base;
 575 #ifdef CONFIG_X86_64
 576         u64                   msr_host_kernel_gs_base;
 577         u64                   msr_guest_kernel_gs_base;
 578 #endif
 579         u32 vm_entry_controls_shadow;
 580         u32 vm_exit_controls_shadow;
 581         u32 secondary_exec_control;
 582
 583         /*
 584          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 585          * non-nested (L1) guest, it always points to vmcs01. For a nested
 586          * guest (L2), it points to a different VMCS.
 587          */
 588         struct loaded_vmcs    vmcs01;
 589         struct loaded_vmcs   *loaded_vmcs;
 590         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 591         struct msr_autoload {
 592                 unsigned nr;
 593                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 594                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 595         } msr_autoload;
 596         struct {
 597                 int           loaded;
 598                 u16           fs_sel, gs_sel, ldt_sel;
 599 #ifdef CONFIG_X86_64
 600                 u16           ds_sel, es_sel;
 601 #endif
 602                 int           gs_ldt_reload_needed;
 603                 int           fs_reload_needed;
 604                 u64           msr_host_bndcfgs;
 605         } host_state;
 606         struct {
 607                 int vm86_active;
 608                 ulong save_rflags;
 609                 struct kvm_segment segs[8];
 610         } rmode;
 611         struct {
 612                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 613                 struct kvm_save_segment {
 614                         u16 selector;
 615                         unsigned long base;
 616                         u32 limit;
 617                         u32 ar;
 618                 } seg[8];
 619         } segment_cache;
 620         int vpid;
 621         bool emulation_required;
 622
 623         u32 exit_reason;
 624
 625         /* Posted interrupt descriptor */
 626         struct pi_desc pi_desc;
 627
 628         /* Support for a guest hypervisor (nested VMX) */
 629         struct nested_vmx nested;
 630
 631         /* Dynamic PLE window. */
 632         int ple_window;
 633         bool ple_window_dirty;
 634
 635         /* Support for PML */
 636 #define PML_ENTITY_NUM          512
 637         struct page *pml_pg;
 638
 639         /* apic deadline value in host tsc */
 640         u64 hv_deadline_tsc;
 641
 642         u64 current_tsc_ratio;
 643
 644         u32 host_pkru;
 645
 646         /*
 647          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 648          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 649          * in msr_ia32_feature_control_valid_bits.
 650          */
 651         u64 msr_ia32_feature_control;
 652         u64 msr_ia32_feature_control_valid_bits;
 653 };
 654
 655 enum segment_cache_field {
 656         SEG_FIELD_SEL = 0,
 657         SEG_FIELD_BASE = 1,
 658         SEG_FIELD_LIMIT = 2,
 659         SEG_FIELD_AR = 3,
 660
 661         SEG_FIELD_NR = 4
 662 };
 663
 664 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 665 {
 666         return container_of(vcpu, struct vcpu_vmx, vcpu);
 667 }
 668
 669 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 670 {
 671         return &(to_vmx(vcpu)->pi_desc);
 672 }
 673
 674 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 675 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 676 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 677                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 678
 679
 680 static unsigned long shadow_read_only_fields[] = {
 681         /*
 682          * We do NOT shadow fields that are modified when L0
 683          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 684          * VMXON...) executed by L1.
 685          * For example, VM_INSTRUCTION_ERROR is read
 686          * by L1 if a vmx instruction fails (part of the error path).
 687          * Note the code assumes this logic. If for some reason
 688          * we start shadowing these fields then we need to
 689          * force a shadow sync when L0 emulates vmx instructions
 690          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 691          * by nested_vmx_failValid)
 692          */
 693         VM_EXIT_REASON,
 694         VM_EXIT_INTR_INFO,
 695         VM_EXIT_INSTRUCTION_LEN,
 696         IDT_VECTORING_INFO_FIELD,
 697         IDT_VECTORING_ERROR_CODE,
 698         VM_EXIT_INTR_ERROR_CODE,
 699         EXIT_QUALIFICATION,
 700         GUEST_LINEAR_ADDRESS,
 701         GUEST_PHYSICAL_ADDRESS
 702 };
 703 static int max_shadow_read_only_fields =
 704         ARRAY_SIZE(shadow_read_only_fields);
 705
 706 static unsigned long shadow_read_write_fields[] = {
 707         TPR_THRESHOLD,
 708         GUEST_RIP,
 709         GUEST_RSP,
 710         GUEST_CR0,
 711         GUEST_CR3,
 712         GUEST_CR4,
 713         GUEST_INTERRUPTIBILITY_INFO,
 714         GUEST_RFLAGS,
 715         GUEST_CS_SELECTOR,
 716         GUEST_CS_AR_BYTES,
 717         GUEST_CS_LIMIT,
 718         GUEST_CS_BASE,
 719         GUEST_ES_BASE,
 720         GUEST_BNDCFGS,
 721         CR0_GUEST_HOST_MASK,
 722         CR0_READ_SHADOW,
 723         CR4_READ_SHADOW,
 724         TSC_OFFSET,
 725         EXCEPTION_BITMAP,
 726         CPU_BASED_VM_EXEC_CONTROL,
 727         VM_ENTRY_EXCEPTION_ERROR_CODE,
 728         VM_ENTRY_INTR_INFO_FIELD,
 729         VM_ENTRY_INSTRUCTION_LEN,
 730         VM_ENTRY_EXCEPTION_ERROR_CODE,
 731         HOST_FS_BASE,
 732         HOST_GS_BASE,
 733         HOST_FS_SELECTOR,
 734         HOST_GS_SELECTOR
 735 };
 736 static int max_shadow_read_write_fields =
 737         ARRAY_SIZE(shadow_read_write_fields);
 738
 739 static const unsigned short vmcs_field_to_offset_table[] = {
 740         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 741         FIELD(POSTED_INTR_NV, posted_intr_nv),
 742         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 743         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 744         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 745         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 746         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 747         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 748         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 749         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 750         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 751         FIELD(GUEST_PML_INDEX, guest_pml_index),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
 770         FIELD64(EPT_POINTER, ept_pointer),
 771         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 772         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 773         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 774         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 775         FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
 776         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 777         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 778         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 779         FIELD64(PML_ADDRESS, pml_address),
 780         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 781         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 782         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 783         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 784         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 785         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 786         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 787         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 788         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 789         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 790         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 791         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 792         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 793         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 794         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 795         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 796         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 797         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 798         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 799         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 800         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 801         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 802         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 803         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 804         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 805         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 806         FIELD(TPR_THRESHOLD, tpr_threshold),
 807         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 808         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 809         FIELD(VM_EXIT_REASON, vm_exit_reason),
 810         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 811         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 812         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 813         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 814         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 815         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 816         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 817         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 818         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 819         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 820         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 821         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 822         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 823         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 824         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 825         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 826         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 827         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 828         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 829         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 830         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 831         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 832         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 833         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 834         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 835         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 836         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 837         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 838         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 839         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 840         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 841         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 842         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 843         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 844         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 845         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 846         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 847         FIELD(EXIT_QUALIFICATION, exit_qualification),
 848         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 849         FIELD(GUEST_CR0, guest_cr0),
 850         FIELD(GUEST_CR3, guest_cr3),
 851         FIELD(GUEST_CR4, guest_cr4),
 852         FIELD(GUEST_ES_BASE, guest_es_base),
 853         FIELD(GUEST_CS_BASE, guest_cs_base),
 854         FIELD(GUEST_SS_BASE, guest_ss_base),
 855         FIELD(GUEST_DS_BASE, guest_ds_base),
 856         FIELD(GUEST_FS_BASE, guest_fs_base),
 857         FIELD(GUEST_GS_BASE, guest_gs_base),
 858         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 859         FIELD(GUEST_TR_BASE, guest_tr_base),
 860         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 861         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 862         FIELD(GUEST_DR7, guest_dr7),
 863         FIELD(GUEST_RSP, guest_rsp),
 864         FIELD(GUEST_RIP, guest_rip),
 865         FIELD(GUEST_RFLAGS, guest_rflags),
 866         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 867         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 868         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 869         FIELD(HOST_CR0, host_cr0),
 870         FIELD(HOST_CR3, host_cr3),
 871         FIELD(HOST_CR4, host_cr4),
 872         FIELD(HOST_FS_BASE, host_fs_base),
 873         FIELD(HOST_GS_BASE, host_gs_base),
 874         FIELD(HOST_TR_BASE, host_tr_base),
 875         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 876         FIELD(HOST_IDTR_BASE, host_idtr_base),
 877         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 878         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 879         FIELD(HOST_RSP, host_rsp),
 880         FIELD(HOST_RIP, host_rip),
 881 };
 882
 883 static inline short vmcs_field_to_offset(unsigned long field)
 884 {
 885         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 886
 887         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 888             vmcs_field_to_offset_table[field] == 0)
 889                 return -ENOENT;
 890
 891         return vmcs_field_to_offset_table[field];
 892 }
 893
 894 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 895 {
 896         return to_vmx(vcpu)->nested.cached_vmcs12;
 897 }
 898
 899 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 900 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 901 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 902 static bool vmx_xsaves_supported(void);
 903 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 904 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 905                             struct kvm_segment *var, int seg);
 906 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 907                             struct kvm_segment *var, int seg);
 908 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 909 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 910 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 911 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 912 static int alloc_identity_pagetable(struct kvm *kvm);
 913 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 914 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 915 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
 916                                             u16 error_code);
 917
 918 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 919 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 920 /*
 921  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 922  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 923  */
 924 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 925
 926 /*
 927  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 928  * can find which vCPU should be waken up.
 929  */
 930 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 931 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 932
 933 enum {
 934         VMX_IO_BITMAP_A,
 935         VMX_IO_BITMAP_B,
 936         VMX_MSR_BITMAP_LEGACY,
 937         VMX_MSR_BITMAP_LONGMODE,
 938         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 939         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 940         VMX_MSR_BITMAP_LEGACY_X2APIC,
 941         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 942         VMX_VMREAD_BITMAP,
 943         VMX_VMWRITE_BITMAP,
 944         VMX_BITMAP_NR
 945 };
 946
 947 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 948
 949 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 950 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 951 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 952 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 953 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 954 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 955 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 956 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 957 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 958 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 959
 960 static bool cpu_has_load_ia32_efer;
 961 static bool cpu_has_load_perf_global_ctrl;
 962
 963 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 964 static DEFINE_SPINLOCK(vmx_vpid_lock);
 965
 966 static struct vmcs_config {
 967         int size;
 968         int order;
 969         u32 basic_cap;
 970         u32 revision_id;
 971         u32 pin_based_exec_ctrl;
 972         u32 cpu_based_exec_ctrl;
 973         u32 cpu_based_2nd_exec_ctrl;
 974         u32 vmexit_ctrl;
 975         u32 vmentry_ctrl;
 976 } vmcs_config;
 977
 978 static struct vmx_capability {
 979         u32 ept;
 980         u32 vpid;
 981 } vmx_capability;
 982
 983 #define VMX_SEGMENT_FIELD(seg)                                  \
 984         [VCPU_SREG_##seg] = {                                   \
 985                 .selector = GUEST_##seg##_SELECTOR,             \
 986                 .base = GUEST_##seg##_BASE,                     \
 987                 .limit = GUEST_##seg##_LIMIT,                   \
 988                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 989         }
 990
 991 static const struct kvm_vmx_segment_field {
 992         unsigned selector;
 993         unsigned base;
 994         unsigned limit;
 995         unsigned ar_bytes;
 996 } kvm_vmx_segment_fields[] = {
 997         VMX_SEGMENT_FIELD(CS),
 998         VMX_SEGMENT_FIELD(DS),
 999         VMX_SEGMENT_FIELD(ES),
1000         VMX_SEGMENT_FIELD(FS),
1001         VMX_SEGMENT_FIELD(GS),
1002         VMX_SEGMENT_FIELD(SS),
1003         VMX_SEGMENT_FIELD(TR),
1004         VMX_SEGMENT_FIELD(LDTR),
1005 };
1006
1007 static u64 host_efer;
1008
1009 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1010
1011 /*
1012  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1013  * away by decrementing the array size.
1014  */
1015 static const u32 vmx_msr_index[] = {
1016 #ifdef CONFIG_X86_64
1017         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1018 #endif
1019         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1020 };
1021
1022 static inline bool is_exception_n(u32 intr_info, u8 vector)
1023 {
1024         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1025                              INTR_INFO_VALID_MASK)) ==
1026                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1027 }
1028
1029 static inline bool is_debug(u32 intr_info)
1030 {
1031         return is_exception_n(intr_info, DB_VECTOR);
1032 }
1033
1034 static inline bool is_breakpoint(u32 intr_info)
1035 {
1036         return is_exception_n(intr_info, BP_VECTOR);
1037 }
1038
1039 static inline bool is_page_fault(u32 intr_info)
1040 {
1041         return is_exception_n(intr_info, PF_VECTOR);
1042 }
1043
1044 static inline bool is_no_device(u32 intr_info)
1045 {
1046         return is_exception_n(intr_info, NM_VECTOR);
1047 }
1048
1049 static inline bool is_invalid_opcode(u32 intr_info)
1050 {
1051         return is_exception_n(intr_info, UD_VECTOR);
1052 }
1053
1054 static inline bool is_external_interrupt(u32 intr_info)
1055 {
1056         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1057                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1058 }
1059
1060 static inline bool is_machine_check(u32 intr_info)
1061 {
1062         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1063                              INTR_INFO_VALID_MASK)) ==
1064                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1065 }
1066
1067 static inline bool cpu_has_vmx_msr_bitmap(void)
1068 {
1069         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1070 }
1071
1072 static inline bool cpu_has_vmx_tpr_shadow(void)
1073 {
1074         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1075 }
1076
1077 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1078 {
1079         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1080 }
1081
1082 static inline bool cpu_has_secondary_exec_ctrls(void)
1083 {
1084         return vmcs_config.cpu_based_exec_ctrl &
1085                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1086 }
1087
1088 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1089 {
1090         return vmcs_config.cpu_based_2nd_exec_ctrl &
1091                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1092 }
1093
1094 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1095 {
1096         return vmcs_config.cpu_based_2nd_exec_ctrl &
1097                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1098 }
1099
1100 static inline bool cpu_has_vmx_apic_register_virt(void)
1101 {
1102         return vmcs_config.cpu_based_2nd_exec_ctrl &
1103                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1104 }
1105
1106 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1107 {
1108         return vmcs_config.cpu_based_2nd_exec_ctrl &
1109                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1110 }
1111
1112 /*
1113  * Comment's format: document - errata name - stepping - processor name.
1114  * Refer from
1115  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1116  */
1117 static u32 vmx_preemption_cpu_tfms[] = {
1118 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1119 0x000206E6,
1120 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1121 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1122 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1123 0x00020652,
1124 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1125 0x00020655,
1126 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1127 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1128 /*
1129  * 320767.pdf - AAP86  - B1 -
1130  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1131  */
1132 0x000106E5,
1133 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1134 0x000106A0,
1135 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1136 0x000106A1,
1137 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1138 0x000106A4,
1139  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1140  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1141  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1142 0x000106A5,
1143 };
1144
1145 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1146 {
1147         u32 eax = cpuid_eax(0x00000001), i;
1148
1149         /* Clear the reserved bits */
1150         eax &= ~(0x3U << 14 | 0xfU << 28);
1151         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1152                 if (eax == vmx_preemption_cpu_tfms[i])
1153                         return true;
1154
1155         return false;
1156 }
1157
1158 static inline bool cpu_has_vmx_preemption_timer(void)
1159 {
1160         return vmcs_config.pin_based_exec_ctrl &
1161                 PIN_BASED_VMX_PREEMPTION_TIMER;
1162 }
1163
1164 static inline bool cpu_has_vmx_posted_intr(void)
1165 {
1166         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1167                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1168 }
1169
1170 static inline bool cpu_has_vmx_apicv(void)
1171 {
1172         return cpu_has_vmx_apic_register_virt() &&
1173                 cpu_has_vmx_virtual_intr_delivery() &&
1174                 cpu_has_vmx_posted_intr();
1175 }
1176
1177 static inline bool cpu_has_vmx_flexpriority(void)
1178 {
1179         return cpu_has_vmx_tpr_shadow() &&
1180                 cpu_has_vmx_virtualize_apic_accesses();
1181 }
1182
1183 static inline bool cpu_has_vmx_ept_execute_only(void)
1184 {
1185         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1186 }
1187
1188 static inline bool cpu_has_vmx_ept_2m_page(void)
1189 {
1190         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1191 }
1192
1193 static inline bool cpu_has_vmx_ept_1g_page(void)
1194 {
1195         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1196 }
1197
1198 static inline bool cpu_has_vmx_ept_4levels(void)
1199 {
1200         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1201 }
1202
1203 static inline bool cpu_has_vmx_ept_mt_wb(void)
1204 {
1205         return vmx_capability.ept & VMX_EPTP_WB_BIT;
1206 }
1207
1208 static inline bool cpu_has_vmx_ept_5levels(void)
1209 {
1210         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1211 }
1212
1213 static inline bool cpu_has_vmx_ept_ad_bits(void)
1214 {
1215         return vmx_capability.ept & VMX_EPT_AD_BIT;
1216 }
1217
1218 static inline bool cpu_has_vmx_invept_context(void)
1219 {
1220         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1221 }
1222
1223 static inline bool cpu_has_vmx_invept_global(void)
1224 {
1225         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1226 }
1227
1228 static inline bool cpu_has_vmx_invvpid_single(void)
1229 {
1230         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1231 }
1232
1233 static inline bool cpu_has_vmx_invvpid_global(void)
1234 {
1235         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1236 }
1237
1238 static inline bool cpu_has_vmx_invvpid(void)
1239 {
1240         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1241 }
1242
1243 static inline bool cpu_has_vmx_ept(void)
1244 {
1245         return vmcs_config.cpu_based_2nd_exec_ctrl &
1246                 SECONDARY_EXEC_ENABLE_EPT;
1247 }
1248
1249 static inline bool cpu_has_vmx_unrestricted_guest(void)
1250 {
1251         return vmcs_config.cpu_based_2nd_exec_ctrl &
1252                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1253 }
1254
1255 static inline bool cpu_has_vmx_ple(void)
1256 {
1257         return vmcs_config.cpu_based_2nd_exec_ctrl &
1258                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1259 }
1260
1261 static inline bool cpu_has_vmx_basic_inout(void)
1262 {
1263         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1264 }
1265
1266 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1267 {
1268         return flexpriority_enabled && lapic_in_kernel(vcpu);
1269 }
1270
1271 static inline bool cpu_has_vmx_vpid(void)
1272 {
1273         return vmcs_config.cpu_based_2nd_exec_ctrl &
1274                 SECONDARY_EXEC_ENABLE_VPID;
1275 }
1276
1277 static inline bool cpu_has_vmx_rdtscp(void)
1278 {
1279         return vmcs_config.cpu_based_2nd_exec_ctrl &
1280                 SECONDARY_EXEC_RDTSCP;
1281 }
1282
1283 static inline bool cpu_has_vmx_invpcid(void)
1284 {
1285         return vmcs_config.cpu_based_2nd_exec_ctrl &
1286                 SECONDARY_EXEC_ENABLE_INVPCID;
1287 }
1288
1289 static inline bool cpu_has_vmx_wbinvd_exit(void)
1290 {
1291         return vmcs_config.cpu_based_2nd_exec_ctrl &
1292                 SECONDARY_EXEC_WBINVD_EXITING;
1293 }
1294
1295 static inline bool cpu_has_vmx_shadow_vmcs(void)
1296 {
1297         u64 vmx_msr;
1298         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1299         /* check if the cpu supports writing r/o exit information fields */
1300         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1301                 return false;
1302
1303         return vmcs_config.cpu_based_2nd_exec_ctrl &
1304                 SECONDARY_EXEC_SHADOW_VMCS;
1305 }
1306
1307 static inline bool cpu_has_vmx_pml(void)
1308 {
1309         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1310 }
1311
1312 static inline bool cpu_has_vmx_tsc_scaling(void)
1313 {
1314         return vmcs_config.cpu_based_2nd_exec_ctrl &
1315                 SECONDARY_EXEC_TSC_SCALING;
1316 }
1317
1318 static inline bool cpu_has_vmx_vmfunc(void)
1319 {
1320         return vmcs_config.cpu_based_2nd_exec_ctrl &
1321                 SECONDARY_EXEC_ENABLE_VMFUNC;
1322 }
1323
1324 static inline bool report_flexpriority(void)
1325 {
1326         return flexpriority_enabled;
1327 }
1328
1329 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1330 {
1331         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1332 }
1333
1334 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1335 {
1336         return vmcs12->cpu_based_vm_exec_control & bit;
1337 }
1338
1339 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1340 {
1341         return (vmcs12->cpu_based_vm_exec_control &
1342                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1343                 (vmcs12->secondary_vm_exec_control & bit);
1344 }
1345
1346 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1347 {
1348         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1349 }
1350
1351 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1352 {
1353         return vmcs12->pin_based_vm_exec_control &
1354                 PIN_BASED_VMX_PREEMPTION_TIMER;
1355 }
1356
1357 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1358 {
1359         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1360 }
1361
1362 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1363 {
1364         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1365 }
1366
1367 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1368 {
1369         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1370 }
1371
1372 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1373 {
1374         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1375 }
1376
1377 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1378 {
1379         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1380 }
1381
1382 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1383 {
1384         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1385 }
1386
1387 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1388 {
1389         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1390 }
1391
1392 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1393 {
1394         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1395 }
1396
1397 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1398 {
1399         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1400 }
1401
1402 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1403 {
1404         return nested_cpu_has_vmfunc(vmcs12) &&
1405                 (vmcs12->vm_function_control &
1406                  VMX_VMFUNC_EPTP_SWITCHING);
1407 }
1408
1409 static inline bool is_nmi(u32 intr_info)
1410 {
1411         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1412                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1413 }
1414
1415 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1416                               u32 exit_intr_info,
1417                               unsigned long exit_qualification);
1418 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1419                         struct vmcs12 *vmcs12,
1420                         u32 reason, unsigned long qualification);
1421
1422 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1423 {
1424         int i;
1425
1426         for (i = 0; i < vmx->nmsrs; ++i)
1427                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1428                         return i;
1429         return -1;
1430 }
1431
1432 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1433 {
1434     struct {
1435         u64 vpid : 16;
1436         u64 rsvd : 48;
1437         u64 gva;
1438     } operand = { vpid, 0, gva };
1439
1440     asm volatile (__ex(ASM_VMX_INVVPID)
1441                   /* CF==1 or ZF==1 --> rc = -1 */
1442                   "; ja 1f ; ud2 ; 1:"
1443                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1444 }
1445
1446 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1447 {
1448         struct {
1449                 u64 eptp, gpa;
1450         } operand = {eptp, gpa};
1451
1452         asm volatile (__ex(ASM_VMX_INVEPT)
1453                         /* CF==1 or ZF==1 --> rc = -1 */
1454                         "; ja 1f ; ud2 ; 1:\n"
1455                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1456 }
1457
1458 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1459 {
1460         int i;
1461
1462         i = __find_msr_index(vmx, msr);
1463         if (i >= 0)
1464                 return &vmx->guest_msrs[i];
1465         return NULL;
1466 }
1467
1468 static void vmcs_clear(struct vmcs *vmcs)
1469 {
1470         u64 phys_addr = __pa(vmcs);
1471         u8 error;
1472
1473         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1474                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1475                       : "cc", "memory");
1476         if (error)
1477                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1478                        vmcs, phys_addr);
1479 }
1480
1481 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1482 {
1483         vmcs_clear(loaded_vmcs->vmcs);
1484         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1485                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1486         loaded_vmcs->cpu = -1;
1487         loaded_vmcs->launched = 0;
1488 }
1489
1490 static void vmcs_load(struct vmcs *vmcs)
1491 {
1492         u64 phys_addr = __pa(vmcs);
1493         u8 error;
1494
1495         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1496                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1497                         : "cc", "memory");
1498         if (error)
1499                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1500                        vmcs, phys_addr);
1501 }
1502
1503 #ifdef CONFIG_KEXEC_CORE
1504 /*
1505  * This bitmap is used to indicate whether the vmclear
1506  * operation is enabled on all cpus. All disabled by
1507  * default.
1508  */
1509 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1510
1511 static inline void crash_enable_local_vmclear(int cpu)
1512 {
1513         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1514 }
1515
1516 static inline void crash_disable_local_vmclear(int cpu)
1517 {
1518         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1519 }
1520
1521 static inline int crash_local_vmclear_enabled(int cpu)
1522 {
1523         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1524 }
1525
1526 static void crash_vmclear_local_loaded_vmcss(void)
1527 {
1528         int cpu = raw_smp_processor_id();
1529         struct loaded_vmcs *v;
1530
1531         if (!crash_local_vmclear_enabled(cpu))
1532                 return;
1533
1534         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1535                             loaded_vmcss_on_cpu_link)
1536                 vmcs_clear(v->vmcs);
1537 }
1538 #else
1539 static inline void crash_enable_local_vmclear(int cpu) { }
1540 static inline void crash_disable_local_vmclear(int cpu) { }
1541 #endif /* CONFIG_KEXEC_CORE */
1542
1543 static void __loaded_vmcs_clear(void *arg)
1544 {
1545         struct loaded_vmcs *loaded_vmcs = arg;
1546         int cpu = raw_smp_processor_id();
1547
1548         if (loaded_vmcs->cpu != cpu)
1549                 return; /* vcpu migration can race with cpu offline */
1550         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1551                 per_cpu(current_vmcs, cpu) = NULL;
1552         crash_disable_local_vmclear(cpu);
1553         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1554
1555         /*
1556          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1557          * is before setting loaded_vmcs->vcpu to -1 which is done in
1558          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1559          * then adds the vmcs into percpu list before it is deleted.
1560          */
1561         smp_wmb();
1562
1563         loaded_vmcs_init(loaded_vmcs);
1564         crash_enable_local_vmclear(cpu);
1565 }
1566
1567 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1568 {
1569         int cpu = loaded_vmcs->cpu;
1570
1571         if (cpu != -1)
1572                 smp_call_function_single(cpu,
1573                          __loaded_vmcs_clear, loaded_vmcs, 1);
1574 }
1575
1576 static inline void vpid_sync_vcpu_single(int vpid)
1577 {
1578         if (vpid == 0)
1579                 return;
1580
1581         if (cpu_has_vmx_invvpid_single())
1582                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1583 }
1584
1585 static inline void vpid_sync_vcpu_global(void)
1586 {
1587         if (cpu_has_vmx_invvpid_global())
1588                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1589 }
1590
1591 static inline void vpid_sync_context(int vpid)
1592 {
1593         if (cpu_has_vmx_invvpid_single())
1594                 vpid_sync_vcpu_single(vpid);
1595         else
1596                 vpid_sync_vcpu_global();
1597 }
1598
1599 static inline void ept_sync_global(void)
1600 {
1601         if (cpu_has_vmx_invept_global())
1602                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1603 }
1604
1605 static inline void ept_sync_context(u64 eptp)
1606 {
1607         if (enable_ept) {
1608                 if (cpu_has_vmx_invept_context())
1609                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1610                 else
1611                         ept_sync_global();
1612         }
1613 }
1614
1615 static __always_inline void vmcs_check16(unsigned long field)
1616 {
1617         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1618                          "16-bit accessor invalid for 64-bit field");
1619         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1620                          "16-bit accessor invalid for 64-bit high field");
1621         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1622                          "16-bit accessor invalid for 32-bit high field");
1623         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1624                          "16-bit accessor invalid for natural width field");
1625 }
1626
1627 static __always_inline void vmcs_check32(unsigned long field)
1628 {
1629         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1630                          "32-bit accessor invalid for 16-bit field");
1631         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1632                          "32-bit accessor invalid for natural width field");
1633 }
1634
1635 static __always_inline void vmcs_check64(unsigned long field)
1636 {
1637         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1638                          "64-bit accessor invalid for 16-bit field");
1639         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1640                          "64-bit accessor invalid for 64-bit high field");
1641         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1642                          "64-bit accessor invalid for 32-bit field");
1643         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1644                          "64-bit accessor invalid for natural width field");
1645 }
1646
1647 static __always_inline void vmcs_checkl(unsigned long field)
1648 {
1649         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1650                          "Natural width accessor invalid for 16-bit field");
1651         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1652                          "Natural width accessor invalid for 64-bit field");
1653         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1654                          "Natural width accessor invalid for 64-bit high field");
1655         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1656                          "Natural width accessor invalid for 32-bit field");
1657 }
1658
1659 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1660 {
1661         unsigned long value;
1662
1663         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1664                       : "=a"(value) : "d"(field) : "cc");
1665         return value;
1666 }
1667
1668 static __always_inline u16 vmcs_read16(unsigned long field)
1669 {
1670         vmcs_check16(field);
1671         return __vmcs_readl(field);
1672 }
1673
1674 static __always_inline u32 vmcs_read32(unsigned long field)
1675 {
1676         vmcs_check32(field);
1677         return __vmcs_readl(field);
1678 }
1679
1680 static __always_inline u64 vmcs_read64(unsigned long field)
1681 {
1682         vmcs_check64(field);
1683 #ifdef CONFIG_X86_64
1684         return __vmcs_readl(field);
1685 #else
1686         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1687 #endif
1688 }
1689
1690 static __always_inline unsigned long vmcs_readl(unsigned long field)
1691 {
1692         vmcs_checkl(field);
1693         return __vmcs_readl(field);
1694 }
1695
1696 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1697 {
1698         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1699                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1700         dump_stack();
1701 }
1702
1703 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1704 {
1705         u8 error;
1706
1707         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1708                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1709         if (unlikely(error))
1710                 vmwrite_error(field, value);
1711 }
1712
1713 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1714 {
1715         vmcs_check16(field);
1716         __vmcs_writel(field, value);
1717 }
1718
1719 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1720 {
1721         vmcs_check32(field);
1722         __vmcs_writel(field, value);
1723 }
1724
1725 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1726 {
1727         vmcs_check64(field);
1728         __vmcs_writel(field, value);
1729 #ifndef CONFIG_X86_64
1730         asm volatile ("");
1731         __vmcs_writel(field+1, value >> 32);
1732 #endif
1733 }
1734
1735 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1736 {
1737         vmcs_checkl(field);
1738         __vmcs_writel(field, value);
1739 }
1740
1741 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1742 {
1743         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1744                          "vmcs_clear_bits does not support 64-bit fields");
1745         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1746 }
1747
1748 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1749 {
1750         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1751                          "vmcs_set_bits does not support 64-bit fields");
1752         __vmcs_writel(field, __vmcs_readl(field) | mask);
1753 }
1754
1755 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1756 {
1757         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1758 }
1759
1760 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1761 {
1762         vmcs_write32(VM_ENTRY_CONTROLS, val);
1763         vmx->vm_entry_controls_shadow = val;
1764 }
1765
1766 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1767 {
1768         if (vmx->vm_entry_controls_shadow != val)
1769                 vm_entry_controls_init(vmx, val);
1770 }
1771
1772 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1773 {
1774         return vmx->vm_entry_controls_shadow;
1775 }
1776
1777
1778 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1779 {
1780         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1781 }
1782
1783 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1784 {
1785         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1786 }
1787
1788 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1789 {
1790         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1791 }
1792
1793 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1794 {
1795         vmcs_write32(VM_EXIT_CONTROLS, val);
1796         vmx->vm_exit_controls_shadow = val;
1797 }
1798
1799 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1800 {
1801         if (vmx->vm_exit_controls_shadow != val)
1802                 vm_exit_controls_init(vmx, val);
1803 }
1804
1805 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1806 {
1807         return vmx->vm_exit_controls_shadow;
1808 }
1809
1810
1811 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1812 {
1813         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1814 }
1815
1816 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1817 {
1818         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1819 }
1820
1821 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1822 {
1823         vmx->segment_cache.bitmask = 0;
1824 }
1825
1826 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1827                                        unsigned field)
1828 {
1829         bool ret;
1830         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1831
1832         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1833                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1834                 vmx->segment_cache.bitmask = 0;
1835         }
1836         ret = vmx->segment_cache.bitmask & mask;
1837         vmx->segment_cache.bitmask |= mask;
1838         return ret;
1839 }
1840
1841 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1842 {
1843         u16 *p = &vmx->segment_cache.seg[seg].selector;
1844
1845         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1846                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1847         return *p;
1848 }
1849
1850 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1851 {
1852         ulong *p = &vmx->segment_cache.seg[seg].base;
1853
1854         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1855                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1856         return *p;
1857 }
1858
1859 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1860 {
1861         u32 *p = &vmx->segment_cache.seg[seg].limit;
1862
1863         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1864                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1865         return *p;
1866 }
1867
1868 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1869 {
1870         u32 *p = &vmx->segment_cache.seg[seg].ar;
1871
1872         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1873                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1874         return *p;
1875 }
1876
1877 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1878 {
1879         u32 eb;
1880
1881         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1882              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1883         if ((vcpu->guest_debug &
1884              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1885             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1886                 eb |= 1u << BP_VECTOR;
1887         if (to_vmx(vcpu)->rmode.vm86_active)
1888                 eb = ~0;
1889         if (enable_ept)
1890                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1891
1892         /* When we are running a nested L2 guest and L1 specified for it a
1893          * certain exception bitmap, we must trap the same exceptions and pass
1894          * them to L1. When running L2, we will only handle the exceptions
1895          * specified above if L1 did not want them.
1896          */
1897         if (is_guest_mode(vcpu))
1898                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1899
1900         vmcs_write32(EXCEPTION_BITMAP, eb);
1901 }
1902
1903 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1904                 unsigned long entry, unsigned long exit)
1905 {
1906         vm_entry_controls_clearbit(vmx, entry);
1907         vm_exit_controls_clearbit(vmx, exit);
1908 }
1909
1910 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1911 {
1912         unsigned i;
1913         struct msr_autoload *m = &vmx->msr_autoload;
1914
1915         switch (msr) {
1916         case MSR_EFER:
1917                 if (cpu_has_load_ia32_efer) {
1918                         clear_atomic_switch_msr_special(vmx,
1919                                         VM_ENTRY_LOAD_IA32_EFER,
1920                                         VM_EXIT_LOAD_IA32_EFER);
1921                         return;
1922                 }
1923                 break;
1924         case MSR_CORE_PERF_GLOBAL_CTRL:
1925                 if (cpu_has_load_perf_global_ctrl) {
1926                         clear_atomic_switch_msr_special(vmx,
1927                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1928                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1929                         return;
1930                 }
1931                 break;
1932         }
1933
1934         for (i = 0; i < m->nr; ++i)
1935                 if (m->guest[i].index == msr)
1936                         break;
1937
1938         if (i == m->nr)
1939                 return;
1940         --m->nr;
1941         m->guest[i] = m->guest[m->nr];
1942         m->host[i] = m->host[m->nr];
1943         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1944         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1945 }
1946
1947 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1948                 unsigned long entry, unsigned long exit,
1949                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1950                 u64 guest_val, u64 host_val)
1951 {
1952         vmcs_write64(guest_val_vmcs, guest_val);
1953         vmcs_write64(host_val_vmcs, host_val);
1954         vm_entry_controls_setbit(vmx, entry);
1955         vm_exit_controls_setbit(vmx, exit);
1956 }
1957
1958 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1959                                   u64 guest_val, u64 host_val)
1960 {
1961         unsigned i;
1962         struct msr_autoload *m = &vmx->msr_autoload;
1963
1964         switch (msr) {
1965         case MSR_EFER:
1966                 if (cpu_has_load_ia32_efer) {
1967                         add_atomic_switch_msr_special(vmx,
1968                                         VM_ENTRY_LOAD_IA32_EFER,
1969                                         VM_EXIT_LOAD_IA32_EFER,
1970                                         GUEST_IA32_EFER,
1971                                         HOST_IA32_EFER,
1972                                         guest_val, host_val);
1973                         return;
1974                 }
1975                 break;
1976         case MSR_CORE_PERF_GLOBAL_CTRL:
1977                 if (cpu_has_load_perf_global_ctrl) {
1978                         add_atomic_switch_msr_special(vmx,
1979                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1980                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1981                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1982                                         HOST_IA32_PERF_GLOBAL_CTRL,
1983                                         guest_val, host_val);
1984                         return;
1985                 }
1986                 break;
1987         case MSR_IA32_PEBS_ENABLE:
1988                 /* PEBS needs a quiescent period after being disabled (to write
1989                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1990                  * provide that period, so a CPU could write host's record into
1991                  * guest's memory.
1992                  */
1993                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1994         }
1995
1996         for (i = 0; i < m->nr; ++i)
1997                 if (m->guest[i].index == msr)
1998                         break;
1999
2000         if (i == NR_AUTOLOAD_MSRS) {
2001                 printk_once(KERN_WARNING "Not enough msr switch entries. "
2002                                 "Can't add msr %x\n", msr);
2003                 return;
2004         } else if (i == m->nr) {
2005                 ++m->nr;
2006                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2007                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2008         }
2009
2010         m->guest[i].index = msr;
2011         m->guest[i].value = guest_val;
2012         m->host[i].index = msr;
2013         m->host[i].value = host_val;
2014 }
2015
2016 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2017 {
2018         u64 guest_efer = vmx->vcpu.arch.efer;
2019         u64 ignore_bits = 0;
2020
2021         if (!enable_ept) {
2022                 /*
2023                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2024                  * host CPUID is more efficient than testing guest CPUID
2025                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2026                  */
2027                 if (boot_cpu_has(X86_FEATURE_SMEP))
2028                         guest_efer |= EFER_NX;
2029                 else if (!(guest_efer & EFER_NX))
2030                         ignore_bits |= EFER_NX;
2031         }
2032
2033         /*
2034          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2035          */
2036         ignore_bits |= EFER_SCE;
2037 #ifdef CONFIG_X86_64
2038         ignore_bits |= EFER_LMA | EFER_LME;
2039         /* SCE is meaningful only in long mode on Intel */
2040         if (guest_efer & EFER_LMA)
2041                 ignore_bits &= ~(u64)EFER_SCE;
2042 #endif
2043
2044         clear_atomic_switch_msr(vmx, MSR_EFER);
2045
2046         /*
2047          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2048          * On CPUs that support "load IA32_EFER", always switch EFER
2049          * atomically, since it's faster than switching it manually.
2050          */
2051         if (cpu_has_load_ia32_efer ||
2052             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2053                 if (!(guest_efer & EFER_LMA))
2054                         guest_efer &= ~EFER_LME;
2055                 if (guest_efer != host_efer)
2056                         add_atomic_switch_msr(vmx, MSR_EFER,
2057                                               guest_efer, host_efer);
2058                 return false;
2059         } else {
2060                 guest_efer &= ~ignore_bits;
2061                 guest_efer |= host_efer & ignore_bits;
2062
2063                 vmx->guest_msrs[efer_offset].data = guest_efer;
2064                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2065
2066                 return true;
2067         }
2068 }
2069
2070 #ifdef CONFIG_X86_32
2071 /*
2072  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2073  * VMCS rather than the segment table.  KVM uses this helper to figure
2074  * out the current bases to poke them into the VMCS before entry.
2075  */
2076 static unsigned long segment_base(u16 selector)
2077 {
2078         struct desc_struct *table;
2079         unsigned long v;
2080
2081         if (!(selector & ~SEGMENT_RPL_MASK))
2082                 return 0;
2083
2084         table = get_current_gdt_ro();
2085
2086         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2087                 u16 ldt_selector = kvm_read_ldt();
2088
2089                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2090                         return 0;
2091
2092                 table = (struct desc_struct *)segment_base(ldt_selector);
2093         }
2094         v = get_desc_base(&table[selector >> 3]);
2095         return v;
2096 }
2097 #endif
2098
2099 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2100 {
2101         struct vcpu_vmx *vmx = to_vmx(vcpu);
2102         int i;
2103
2104         if (vmx->host_state.loaded)
2105                 return;
2106
2107         vmx->host_state.loaded = 1;
2108         /*
2109          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2110          * allow segment selectors with cpl > 0 or ti == 1.
2111          */
2112         vmx->host_state.ldt_sel = kvm_read_ldt();
2113         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2114         savesegment(fs, vmx->host_state.fs_sel);
2115         if (!(vmx->host_state.fs_sel & 7)) {
2116                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2117                 vmx->host_state.fs_reload_needed = 0;
2118         } else {
2119                 vmcs_write16(HOST_FS_SELECTOR, 0);
2120                 vmx->host_state.fs_reload_needed = 1;
2121         }
2122         savesegment(gs, vmx->host_state.gs_sel);
2123         if (!(vmx->host_state.gs_sel & 7))
2124                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2125         else {
2126                 vmcs_write16(HOST_GS_SELECTOR, 0);
2127                 vmx->host_state.gs_ldt_reload_needed = 1;
2128         }
2129
2130 #ifdef CONFIG_X86_64
2131         savesegment(ds, vmx->host_state.ds_sel);
2132         savesegment(es, vmx->host_state.es_sel);
2133 #endif
2134
2135 #ifdef CONFIG_X86_64
2136         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2137         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2138 #else
2139         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2140         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2141 #endif
2142
2143 #ifdef CONFIG_X86_64
2144         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2145         if (is_long_mode(&vmx->vcpu))
2146                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2147 #endif
2148         if (boot_cpu_has(X86_FEATURE_MPX))
2149                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2150         for (i = 0; i < vmx->save_nmsrs; ++i)
2151                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2152                                    vmx->guest_msrs[i].data,
2153                                    vmx->guest_msrs[i].mask);
2154 }
2155
2156 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2157 {
2158         if (!vmx->host_state.loaded)
2159                 return;
2160
2161         ++vmx->vcpu.stat.host_state_reload;
2162         vmx->host_state.loaded = 0;
2163 #ifdef CONFIG_X86_64
2164         if (is_long_mode(&vmx->vcpu))
2165                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2166 #endif
2167         if (vmx->host_state.gs_ldt_reload_needed) {
2168                 kvm_load_ldt(vmx->host_state.ldt_sel);
2169 #ifdef CONFIG_X86_64
2170                 load_gs_index(vmx->host_state.gs_sel);
2171 #else
2172                 loadsegment(gs, vmx->host_state.gs_sel);
2173 #endif
2174         }
2175         if (vmx->host_state.fs_reload_needed)
2176                 loadsegment(fs, vmx->host_state.fs_sel);
2177 #ifdef CONFIG_X86_64
2178         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2179                 loadsegment(ds, vmx->host_state.ds_sel);
2180                 loadsegment(es, vmx->host_state.es_sel);
2181         }
2182 #endif
2183         invalidate_tss_limit();
2184 #ifdef CONFIG_X86_64
2185         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2186 #endif
2187         if (vmx->host_state.msr_host_bndcfgs)
2188                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2189         load_fixmap_gdt(raw_smp_processor_id());
2190 }
2191
2192 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2193 {
2194         preempt_disable();
2195         __vmx_load_host_state(vmx);
2196         preempt_enable();
2197 }
2198
2199 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2200 {
2201         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2202         struct pi_desc old, new;
2203         unsigned int dest;
2204
2205         /*
2206          * In case of hot-plug or hot-unplug, we may have to undo
2207          * vmx_vcpu_pi_put even if there is no assigned device.  And we
2208          * always keep PI.NDST up to date for simplicity: it makes the
2209          * code easier, and CPU migration is not a fast path.
2210          */
2211         if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2212                 return;
2213
2214         /*
2215          * First handle the simple case where no cmpxchg is necessary; just
2216          * allow posting non-urgent interrupts.
2217          *
2218          * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2219          * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2220          * expects the VCPU to be on the blocked_vcpu_list that matches
2221          * PI.NDST.
2222          */
2223         if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2224             vcpu->cpu == cpu) {
2225                 pi_clear_sn(pi_desc);
2226                 return;
2227         }
2228
2229         /* The full case.  */
2230         do {
2231                 old.control = new.control = pi_desc->control;
2232
2233                 dest = cpu_physical_id(cpu);
2234
2235                 if (x2apic_enabled())
2236                         new.ndst = dest;
2237                 else
2238                         new.ndst = (dest << 8) & 0xFF00;
2239
2240                 new.sn = 0;
2241         } while (cmpxchg64(&pi_desc->control, old.control,
2242                            new.control) != old.control);
2243 }
2244
2245 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2246 {
2247         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2248         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2249 }
2250
2251 /*
2252  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2253  * vcpu mutex is already taken.
2254  */
2255 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2256 {
2257         struct vcpu_vmx *vmx = to_vmx(vcpu);
2258         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2259
2260         if (!already_loaded) {
2261                 loaded_vmcs_clear(vmx->loaded_vmcs);
2262                 local_irq_disable();
2263                 crash_disable_local_vmclear(cpu);
2264
2265                 /*
2266                  * Read loaded_vmcs->cpu should be before fetching
2267                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2268                  * See the comments in __loaded_vmcs_clear().
2269                  */
2270                 smp_rmb();
2271
2272                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2273                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2274                 crash_enable_local_vmclear(cpu);
2275                 local_irq_enable();
2276         }
2277
2278         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2279                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2280                 vmcs_load(vmx->loaded_vmcs->vmcs);
2281         }
2282
2283         if (!already_loaded) {
2284                 void *gdt = get_current_gdt_ro();
2285                 unsigned long sysenter_esp;
2286
2287                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2288
2289                 /*
2290                  * Linux uses per-cpu TSS and GDT, so set these when switching
2291                  * processors.  See 22.2.4.
2292                  */
2293                 vmcs_writel(HOST_TR_BASE,
2294                             (unsigned long)this_cpu_ptr(&cpu_tss));
2295                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2296
2297                 /*
2298                  * VM exits change the host TR limit to 0x67 after a VM
2299                  * exit.  This is okay, since 0x67 covers everything except
2300                  * the IO bitmap and have have code to handle the IO bitmap
2301                  * being lost after a VM exit.
2302                  */
2303                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2304
2305                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2306                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2307
2308                 vmx->loaded_vmcs->cpu = cpu;
2309         }
2310
2311         /* Setup TSC multiplier */
2312         if (kvm_has_tsc_control &&
2313             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2314                 decache_tsc_multiplier(vmx);
2315
2316         vmx_vcpu_pi_load(vcpu, cpu);
2317         vmx->host_pkru = read_pkru();
2318 }
2319
2320 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2321 {
2322         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2323
2324         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2325                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2326                 !kvm_vcpu_apicv_active(vcpu))
2327                 return;
2328
2329         /* Set SN when the vCPU is preempted */
2330         if (vcpu->preempted)
2331                 pi_set_sn(pi_desc);
2332 }
2333
2334 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2335 {
2336         vmx_vcpu_pi_put(vcpu);
2337
2338         __vmx_load_host_state(to_vmx(vcpu));
2339 }
2340
2341 static bool emulation_required(struct kvm_vcpu *vcpu)
2342 {
2343         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2344 }
2345
2346 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2347
2348 /*
2349  * Return the cr0 value that a nested guest would read. This is a combination
2350  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2351  * its hypervisor (cr0_read_shadow).
2352  */
2353 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2354 {
2355         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2356                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2357 }
2358 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2359 {
2360         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2361                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2362 }
2363
2364 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2365 {
2366         unsigned long rflags, save_rflags;
2367
2368         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2369                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2370                 rflags = vmcs_readl(GUEST_RFLAGS);
2371                 if (to_vmx(vcpu)->rmode.vm86_active) {
2372                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2373                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2374                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2375                 }
2376                 to_vmx(vcpu)->rflags = rflags;
2377         }
2378         return to_vmx(vcpu)->rflags;
2379 }
2380
2381 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2382 {
2383         unsigned long old_rflags = vmx_get_rflags(vcpu);
2384
2385         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2386         to_vmx(vcpu)->rflags = rflags;
2387         if (to_vmx(vcpu)->rmode.vm86_active) {
2388                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2389                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2390         }
2391         vmcs_writel(GUEST_RFLAGS, rflags);
2392
2393         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2394                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2395 }
2396
2397 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2398 {
2399         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2400         int ret = 0;
2401
2402         if (interruptibility & GUEST_INTR_STATE_STI)
2403                 ret |= KVM_X86_SHADOW_INT_STI;
2404         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2405                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2406
2407         return ret;
2408 }
2409
2410 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2411 {
2412         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2413         u32 interruptibility = interruptibility_old;
2414
2415         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2416
2417         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2418                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2419         else if (mask & KVM_X86_SHADOW_INT_STI)
2420                 interruptibility |= GUEST_INTR_STATE_STI;
2421
2422         if ((interruptibility != interruptibility_old))
2423                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2424 }
2425
2426 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2427 {
2428         unsigned long rip;
2429
2430         rip = kvm_rip_read(vcpu);
2431         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2432         kvm_rip_write(vcpu, rip);
2433
2434         /* skipping an emulated instruction also counts */
2435         vmx_set_interrupt_shadow(vcpu, 0);
2436 }
2437
2438 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2439                                                unsigned long exit_qual)
2440 {
2441         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2442         unsigned int nr = vcpu->arch.exception.nr;
2443         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2444
2445         if (vcpu->arch.exception.has_error_code) {
2446                 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2447                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2448         }
2449
2450         if (kvm_exception_is_soft(nr))
2451                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2452         else
2453                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2454
2455         if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2456             vmx_get_nmi_mask(vcpu))
2457                 intr_info |= INTR_INFO_UNBLOCK_NMI;
2458
2459         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2460 }
2461
2462 /*
2463  * KVM wants to inject page-faults which it got to the guest. This function
2464  * checks whether in a nested guest, we need to inject them to L1 or L2.
2465  */
2466 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2467 {
2468         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2469         unsigned int nr = vcpu->arch.exception.nr;
2470
2471         if (nr == PF_VECTOR) {
2472                 if (vcpu->arch.exception.nested_apf) {
2473                         *exit_qual = vcpu->arch.apf.nested_apf_token;
2474                         return 1;
2475                 }
2476                 /*
2477                  * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2478                  * The fix is to add the ancillary datum (CR2 or DR6) to structs
2479                  * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2480                  * can be written only when inject_pending_event runs.  This should be
2481                  * conditional on a new capability---if the capability is disabled,
2482                  * kvm_multiple_exception would write the ancillary information to
2483                  * CR2 or DR6, for backwards ABI-compatibility.
2484                  */
2485                 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2486                                                     vcpu->arch.exception.error_code)) {
2487                         *exit_qual = vcpu->arch.cr2;
2488                         return 1;
2489                 }
2490         } else {
2491                 if (vmcs12->exception_bitmap & (1u << nr)) {
2492                         if (nr == DB_VECTOR)
2493                                 *exit_qual = vcpu->arch.dr6;
2494                         else
2495                                 *exit_qual = 0;
2496                         return 1;
2497                 }
2498         }
2499
2500         return 0;
2501 }
2502
2503 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2504 {
2505         struct vcpu_vmx *vmx = to_vmx(vcpu);
2506         unsigned nr = vcpu->arch.exception.nr;
2507         bool has_error_code = vcpu->arch.exception.has_error_code;
2508         u32 error_code = vcpu->arch.exception.error_code;
2509         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2510
2511         if (has_error_code) {
2512                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2513                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2514         }
2515
2516         if (vmx->rmode.vm86_active) {
2517                 int inc_eip = 0;
2518                 if (kvm_exception_is_soft(nr))
2519                         inc_eip = vcpu->arch.event_exit_inst_len;
2520                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2521                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2522                 return;
2523         }
2524
2525         if (kvm_exception_is_soft(nr)) {
2526                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2527                              vmx->vcpu.arch.event_exit_inst_len);
2528                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2529         } else
2530                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2531
2532         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2533 }
2534
2535 static bool vmx_rdtscp_supported(void)
2536 {
2537         return cpu_has_vmx_rdtscp();
2538 }
2539
2540 static bool vmx_invpcid_supported(void)
2541 {
2542         return cpu_has_vmx_invpcid() && enable_ept;
2543 }
2544
2545 /*
2546  * Swap MSR entry in host/guest MSR entry array.
2547  */
2548 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2549 {
2550         struct shared_msr_entry tmp;
2551
2552         tmp = vmx->guest_msrs[to];
2553         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2554         vmx->guest_msrs[from] = tmp;
2555 }
2556
2557 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2558 {
2559         unsigned long *msr_bitmap;
2560
2561         if (is_guest_mode(vcpu))
2562                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2563         else if (cpu_has_secondary_exec_ctrls() &&
2564                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2565                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2566                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2567                         if (is_long_mode(vcpu))
2568                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2569                         else
2570                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2571                 } else {
2572                         if (is_long_mode(vcpu))
2573                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2574                         else
2575                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2576                 }
2577         } else {
2578                 if (is_long_mode(vcpu))
2579                         msr_bitmap = vmx_msr_bitmap_longmode;
2580                 else
2581                         msr_bitmap = vmx_msr_bitmap_legacy;
2582         }
2583
2584         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2585 }
2586
2587 /*
2588  * Set up the vmcs to automatically save and restore system
2589  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2590  * mode, as fiddling with msrs is very expensive.
2591  */
2592 static void setup_msrs(struct vcpu_vmx *vmx)
2593 {
2594         int save_nmsrs, index;
2595
2596         save_nmsrs = 0;
2597 #ifdef CONFIG_X86_64
2598         if (is_long_mode(&vmx->vcpu)) {
2599                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2600                 if (index >= 0)
2601                         move_msr_up(vmx, index, save_nmsrs++);
2602                 index = __find_msr_index(vmx, MSR_LSTAR);
2603                 if (index >= 0)
2604                         move_msr_up(vmx, index, save_nmsrs++);
2605                 index = __find_msr_index(vmx, MSR_CSTAR);
2606                 if (index >= 0)
2607                         move_msr_up(vmx, index, save_nmsrs++);
2608                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2609                 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2610                         move_msr_up(vmx, index, save_nmsrs++);
2611                 /*
2612                  * MSR_STAR is only needed on long mode guests, and only
2613                  * if efer.sce is enabled.
2614                  */
2615                 index = __find_msr_index(vmx, MSR_STAR);
2616                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2617                         move_msr_up(vmx, index, save_nmsrs++);
2618         }
2619 #endif
2620         index = __find_msr_index(vmx, MSR_EFER);
2621         if (index >= 0 && update_transition_efer(vmx, index))
2622                 move_msr_up(vmx, index, save_nmsrs++);
2623
2624         vmx->save_nmsrs = save_nmsrs;
2625
2626         if (cpu_has_vmx_msr_bitmap())
2627                 vmx_set_msr_bitmap(&vmx->vcpu);
2628 }
2629
2630 /*
2631  * reads and returns guest's timestamp counter "register"
2632  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2633  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2634  */
2635 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2636 {
2637         u64 host_tsc, tsc_offset;
2638
2639         host_tsc = rdtsc();
2640         tsc_offset = vmcs_read64(TSC_OFFSET);
2641         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2642 }
2643
2644 /*
2645  * writes 'offset' into guest's timestamp counter offset register
2646  */
2647 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2648 {
2649         if (is_guest_mode(vcpu)) {
2650                 /*
2651                  * We're here if L1 chose not to trap WRMSR to TSC. According
2652                  * to the spec, this should set L1's TSC; The offset that L1
2653                  * set for L2 remains unchanged, and still needs to be added
2654                  * to the newly set TSC to get L2's TSC.
2655                  */
2656                 struct vmcs12 *vmcs12;
2657                 /* recalculate vmcs02.TSC_OFFSET: */
2658                 vmcs12 = get_vmcs12(vcpu);
2659                 vmcs_write64(TSC_OFFSET, offset +
2660                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2661                          vmcs12->tsc_offset : 0));
2662         } else {
2663                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2664                                            vmcs_read64(TSC_OFFSET), offset);
2665                 vmcs_write64(TSC_OFFSET, offset);
2666         }
2667 }
2668
2669 /*
2670  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2671  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2672  * all guests if the "nested" module option is off, and can also be disabled
2673  * for a single guest by disabling its VMX cpuid bit.
2674  */
2675 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2676 {
2677         return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2678 }
2679
2680 /*
2681  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2682  * returned for the various VMX controls MSRs when nested VMX is enabled.
2683  * The same values should also be used to verify that vmcs12 control fields are
2684  * valid during nested entry from L1 to L2.
2685  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2686  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2687  * bit in the high half is on if the corresponding bit in the control field
2688  * may be on. See also vmx_control_verify().
2689  */
2690 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2691 {
2692         /*
2693          * Note that as a general rule, the high half of the MSRs (bits in
2694          * the control fields which may be 1) should be initialized by the
2695          * intersection of the underlying hardware's MSR (i.e., features which
2696          * can be supported) and the list of features we want to expose -
2697          * because they are known to be properly supported in our code.
2698          * Also, usually, the low half of the MSRs (bits which must be 1) can
2699          * be set to 0, meaning that L1 may turn off any of these bits. The
2700          * reason is that if one of these bits is necessary, it will appear
2701          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2702          * fields of vmcs01 and vmcs02, will turn these bits off - and
2703          * nested_vmx_exit_reflected() will not pass related exits to L1.
2704          * These rules have exceptions below.
2705          */
2706
2707         /* pin-based controls */
2708         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2709                 vmx->nested.nested_vmx_pinbased_ctls_low,
2710                 vmx->nested.nested_vmx_pinbased_ctls_high);
2711         vmx->nested.nested_vmx_pinbased_ctls_low |=
2712                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2713         vmx->nested.nested_vmx_pinbased_ctls_high &=
2714                 PIN_BASED_EXT_INTR_MASK |
2715                 PIN_BASED_NMI_EXITING |
2716                 PIN_BASED_VIRTUAL_NMIS;
2717         vmx->nested.nested_vmx_pinbased_ctls_high |=
2718                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2719                 PIN_BASED_VMX_PREEMPTION_TIMER;
2720         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2721                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2722                         PIN_BASED_POSTED_INTR;
2723
2724         /* exit controls */
2725         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2726                 vmx->nested.nested_vmx_exit_ctls_low,
2727                 vmx->nested.nested_vmx_exit_ctls_high);
2728         vmx->nested.nested_vmx_exit_ctls_low =
2729                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2730
2731         vmx->nested.nested_vmx_exit_ctls_high &=
2732 #ifdef CONFIG_X86_64
2733                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2734 #endif
2735                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2736         vmx->nested.nested_vmx_exit_ctls_high |=
2737                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2738                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2739                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2740
2741         if (kvm_mpx_supported())
2742                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2743
2744         /* We support free control of debug control saving. */
2745         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2746
2747         /* entry controls */
2748         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2749                 vmx->nested.nested_vmx_entry_ctls_low,
2750                 vmx->nested.nested_vmx_entry_ctls_high);
2751         vmx->nested.nested_vmx_entry_ctls_low =
2752                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2753         vmx->nested.nested_vmx_entry_ctls_high &=
2754 #ifdef CONFIG_X86_64
2755                 VM_ENTRY_IA32E_MODE |
2756 #endif
2757                 VM_ENTRY_LOAD_IA32_PAT;
2758         vmx->nested.nested_vmx_entry_ctls_high |=
2759                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2760         if (kvm_mpx_supported())
2761                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2762
2763         /* We support free control of debug control loading. */
2764         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2765
2766         /* cpu-based controls */
2767         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2768                 vmx->nested.nested_vmx_procbased_ctls_low,
2769                 vmx->nested.nested_vmx_procbased_ctls_high);
2770         vmx->nested.nested_vmx_procbased_ctls_low =
2771                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2772         vmx->nested.nested_vmx_procbased_ctls_high &=
2773                 CPU_BASED_VIRTUAL_INTR_PENDING |
2774                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2775                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2776                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2777                 CPU_BASED_CR3_STORE_EXITING |
2778 #ifdef CONFIG_X86_64
2779                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2780 #endif
2781                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2782                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2783                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2784                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2785                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2786         /*
2787          * We can allow some features even when not supported by the
2788          * hardware. For example, L1 can specify an MSR bitmap - and we
2789          * can use it to avoid exits to L1 - even when L0 runs L2
2790          * without MSR bitmaps.
2791          */
2792         vmx->nested.nested_vmx_procbased_ctls_high |=
2793                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2794                 CPU_BASED_USE_MSR_BITMAPS;
2795
2796         /* We support free control of CR3 access interception. */
2797         vmx->nested.nested_vmx_procbased_ctls_low &=
2798                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2799
2800         /*
2801          * secondary cpu-based controls.  Do not include those that
2802          * depend on CPUID bits, they are added later by vmx_cpuid_update.
2803          */
2804         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2805                 vmx->nested.nested_vmx_secondary_ctls_low,
2806                 vmx->nested.nested_vmx_secondary_ctls_high);
2807         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2808         vmx->nested.nested_vmx_secondary_ctls_high &=
2809                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2810                 SECONDARY_EXEC_DESC |
2811                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2812                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2813                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2814                 SECONDARY_EXEC_WBINVD_EXITING;
2815
2816         if (enable_ept) {
2817                 /* nested EPT: emulate EPT also to L1 */
2818                 vmx->nested.nested_vmx_secondary_ctls_high |=
2819                         SECONDARY_EXEC_ENABLE_EPT;
2820                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2821                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2822                 if (cpu_has_vmx_ept_execute_only())
2823                         vmx->nested.nested_vmx_ept_caps |=
2824                                 VMX_EPT_EXECUTE_ONLY_BIT;
2825                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2826                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2827                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2828                         VMX_EPT_1GB_PAGE_BIT;
2829                 if (enable_ept_ad_bits) {
2830                         vmx->nested.nested_vmx_secondary_ctls_high |=
2831                                 SECONDARY_EXEC_ENABLE_PML;
2832                         vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2833                 }
2834         } else
2835                 vmx->nested.nested_vmx_ept_caps = 0;
2836
2837         if (cpu_has_vmx_vmfunc()) {
2838                 vmx->nested.nested_vmx_secondary_ctls_high |=
2839                         SECONDARY_EXEC_ENABLE_VMFUNC;
2840                 /*
2841                  * Advertise EPTP switching unconditionally
2842                  * since we emulate it
2843                  */
2844                 vmx->nested.nested_vmx_vmfunc_controls =
2845                         VMX_VMFUNC_EPTP_SWITCHING;
2846         }
2847
2848         /*
2849          * Old versions of KVM use the single-context version without
2850          * checking for support, so declare that it is supported even
2851          * though it is treated as global context.  The alternative is
2852          * not failing the single-context invvpid, and it is worse.
2853          */
2854         if (enable_vpid) {
2855                 vmx->nested.nested_vmx_secondary_ctls_high |=
2856                         SECONDARY_EXEC_ENABLE_VPID;
2857                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2858                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2859         } else
2860                 vmx->nested.nested_vmx_vpid_caps = 0;
2861
2862         if (enable_unrestricted_guest)
2863                 vmx->nested.nested_vmx_secondary_ctls_high |=
2864                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2865
2866         /* miscellaneous data */
2867         rdmsr(MSR_IA32_VMX_MISC,
2868                 vmx->nested.nested_vmx_misc_low,
2869                 vmx->nested.nested_vmx_misc_high);
2870         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2871         vmx->nested.nested_vmx_misc_low |=
2872                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2873                 VMX_MISC_ACTIVITY_HLT;
2874         vmx->nested.nested_vmx_misc_high = 0;
2875
2876         /*
2877          * This MSR reports some information about VMX support. We
2878          * should return information about the VMX we emulate for the
2879          * guest, and the VMCS structure we give it - not about the
2880          * VMX support of the underlying hardware.
2881          */
2882         vmx->nested.nested_vmx_basic =
2883                 VMCS12_REVISION |
2884                 VMX_BASIC_TRUE_CTLS |
2885                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2886                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2887
2888         if (cpu_has_vmx_basic_inout())
2889                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2890
2891         /*
2892          * These MSRs specify bits which the guest must keep fixed on
2893          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2894          * We picked the standard core2 setting.
2895          */
2896 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2897 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2898         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2899         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2900
2901         /* These MSRs specify bits which the guest must keep fixed off. */
2902         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2903         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2904
2905         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2906         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2907 }
2908
2909 /*
2910  * if fixed0[i] == 1: val[i] must be 1
2911  * if fixed1[i] == 0: val[i] must be 0
2912  */
2913 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2914 {
2915         return ((val & fixed1) | fixed0) == val;
2916 }
2917
2918 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2919 {
2920         return fixed_bits_valid(control, low, high);
2921 }
2922
2923 static inline u64 vmx_control_msr(u32 low, u32 high)
2924 {
2925         return low | ((u64)high << 32);
2926 }
2927
2928 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2929 {
2930         superset &= mask;
2931         subset &= mask;
2932
2933         return (superset | subset) == superset;
2934 }
2935
2936 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2937 {
2938         const u64 feature_and_reserved =
2939                 /* feature (except bit 48; see below) */
2940                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2941                 /* reserved */
2942                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2943         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2944
2945         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2946                 return -EINVAL;
2947
2948         /*
2949          * KVM does not emulate a version of VMX that constrains physical
2950          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2951          */
2952         if (data & BIT_ULL(48))
2953                 return -EINVAL;
2954
2955         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2956             vmx_basic_vmcs_revision_id(data))
2957                 return -EINVAL;
2958
2959         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2960                 return -EINVAL;
2961
2962         vmx->nested.nested_vmx_basic = data;
2963         return 0;
2964 }
2965
2966 static int
2967 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2968 {
2969         u64 supported;
2970         u32 *lowp, *highp;
2971
2972         switch (msr_index) {
2973         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2974                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2975                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2976                 break;
2977         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2978                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2979                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2980                 break;
2981         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2982                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2983                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2984                 break;
2985         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2986                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2987                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2988                 break;
2989         case MSR_IA32_VMX_PROCBASED_CTLS2:
2990                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2991                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2992                 break;
2993         default:
2994                 BUG();
2995         }
2996
2997         supported = vmx_control_msr(*lowp, *highp);
2998
2999         /* Check must-be-1 bits are still 1. */
3000         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3001                 return -EINVAL;
3002
3003         /* Check must-be-0 bits are still 0. */
3004         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3005                 return -EINVAL;
3006
3007         *lowp = data;
3008         *highp = data >> 32;
3009         return 0;
3010 }
3011
3012 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3013 {
3014         const u64 feature_and_reserved_bits =
3015                 /* feature */
3016                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3017                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3018                 /* reserved */
3019                 GENMASK_ULL(13, 9) | BIT_ULL(31);
3020         u64 vmx_misc;
3021
3022         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3023                                    vmx->nested.nested_vmx_misc_high);
3024
3025         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3026                 return -EINVAL;
3027
3028         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3029              PIN_BASED_VMX_PREEMPTION_TIMER) &&
3030             vmx_misc_preemption_timer_rate(data) !=
3031             vmx_misc_preemption_timer_rate(vmx_misc))
3032                 return -EINVAL;
3033
3034         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3035                 return -EINVAL;
3036
3037         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3038                 return -EINVAL;
3039
3040         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3041                 return -EINVAL;
3042
3043         vmx->nested.nested_vmx_misc_low = data;
3044         vmx->nested.nested_vmx_misc_high = data >> 32;
3045         return 0;
3046 }
3047
3048 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3049 {
3050         u64 vmx_ept_vpid_cap;
3051
3052         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3053                                            vmx->nested.nested_vmx_vpid_caps);
3054
3055         /* Every bit is either reserved or a feature bit. */
3056         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3057                 return -EINVAL;
3058
3059         vmx->nested.nested_vmx_ept_caps = data;
3060         vmx->nested.nested_vmx_vpid_caps = data >> 32;
3061         return 0;
3062 }
3063
3064 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3065 {
3066         u64 *msr;
3067
3068         switch (msr_index) {
3069         case MSR_IA32_VMX_CR0_FIXED0:
3070                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3071                 break;
3072         case MSR_IA32_VMX_CR4_FIXED0:
3073                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3074                 break;
3075         default:
3076                 BUG();
3077         }
3078
3079         /*
3080          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3081          * must be 1 in the restored value.
3082          */
3083         if (!is_bitwise_subset(data, *msr, -1ULL))
3084                 return -EINVAL;
3085
3086         *msr = data;
3087         return 0;
3088 }
3089
3090 /*
3091  * Called when userspace is restoring VMX MSRs.
3092  *
3093  * Returns 0 on success, non-0 otherwise.
3094  */
3095 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3096 {
3097         struct vcpu_vmx *vmx = to_vmx(vcpu);
3098
3099         switch (msr_index) {
3100         case MSR_IA32_VMX_BASIC:
3101                 return vmx_restore_vmx_basic(vmx, data);
3102         case MSR_IA32_VMX_PINBASED_CTLS:
3103         case MSR_IA32_VMX_PROCBASED_CTLS:
3104         case MSR_IA32_VMX_EXIT_CTLS:
3105         case MSR_IA32_VMX_ENTRY_CTLS:
3106                 /*
3107                  * The "non-true" VMX capability MSRs are generated from the
3108                  * "true" MSRs, so we do not support restoring them directly.
3109                  *
3110                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3111                  * should restore the "true" MSRs with the must-be-1 bits
3112                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3113                  * DEFAULT SETTINGS".
3114                  */
3115                 return -EINVAL;
3116         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3117         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3118         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3119         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3120         case MSR_IA32_VMX_PROCBASED_CTLS2:
3121                 return vmx_restore_control_msr(vmx, msr_index, data);
3122         case MSR_IA32_VMX_MISC:
3123                 return vmx_restore_vmx_misc(vmx, data);
3124         case MSR_IA32_VMX_CR0_FIXED0:
3125         case MSR_IA32_VMX_CR4_FIXED0:
3126                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3127         case MSR_IA32_VMX_CR0_FIXED1:
3128         case MSR_IA32_VMX_CR4_FIXED1:
3129                 /*
3130                  * These MSRs are generated based on the vCPU's CPUID, so we
3131                  * do not support restoring them directly.
3132                  */
3133                 return -EINVAL;
3134         case MSR_IA32_VMX_EPT_VPID_CAP:
3135                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3136         case MSR_IA32_VMX_VMCS_ENUM:
3137                 vmx->nested.nested_vmx_vmcs_enum = data;
3138                 return 0;
3139         default:
3140                 /*
3141                  * The rest of the VMX capability MSRs do not support restore.
3142                  */
3143                 return -EINVAL;
3144         }
3145 }
3146
3147 /* Returns 0 on success, non-0 otherwise. */
3148 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3149 {
3150         struct vcpu_vmx *vmx = to_vmx(vcpu);
3151
3152         switch (msr_index) {
3153         case MSR_IA32_VMX_BASIC:
3154                 *pdata = vmx->nested.nested_vmx_basic;
3155                 break;
3156         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3157         case MSR_IA32_VMX_PINBASED_CTLS:
3158                 *pdata = vmx_control_msr(
3159                         vmx->nested.nested_vmx_pinbased_ctls_low,
3160                         vmx->nested.nested_vmx_pinbased_ctls_high);
3161                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3162                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3163                 break;
3164         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3165         case MSR_IA32_VMX_PROCBASED_CTLS:
3166                 *pdata = vmx_control_msr(
3167                         vmx->nested.nested_vmx_procbased_ctls_low,
3168                         vmx->nested.nested_vmx_procbased_ctls_high);
3169                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3170                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3171                 break;
3172         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3173         case MSR_IA32_VMX_EXIT_CTLS:
3174                 *pdata = vmx_control_msr(
3175                         vmx->nested.nested_vmx_exit_ctls_low,
3176                         vmx->nested.nested_vmx_exit_ctls_high);
3177                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3178                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3179                 break;
3180         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3181         case MSR_IA32_VMX_ENTRY_CTLS:
3182                 *pdata = vmx_control_msr(
3183                         vmx->nested.nested_vmx_entry_ctls_low,
3184                         vmx->nested.nested_vmx_entry_ctls_high);
3185                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3186                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3187                 break;
3188         case MSR_IA32_VMX_MISC:
3189                 *pdata = vmx_control_msr(
3190                         vmx->nested.nested_vmx_misc_low,
3191                         vmx->nested.nested_vmx_misc_high);
3192                 break;
3193         case MSR_IA32_VMX_CR0_FIXED0:
3194                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3195                 break;
3196         case MSR_IA32_VMX_CR0_FIXED1:
3197                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3198                 break;
3199         case MSR_IA32_VMX_CR4_FIXED0:
3200                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3201                 break;
3202         case MSR_IA32_VMX_CR4_FIXED1:
3203                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3204                 break;
3205         case MSR_IA32_VMX_VMCS_ENUM:
3206                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3207                 break;
3208         case MSR_IA32_VMX_PROCBASED_CTLS2:
3209                 *pdata = vmx_control_msr(
3210                         vmx->nested.nested_vmx_secondary_ctls_low,
3211                         vmx->nested.nested_vmx_secondary_ctls_high);
3212                 break;
3213         case MSR_IA32_VMX_EPT_VPID_CAP:
3214                 *pdata = vmx->nested.nested_vmx_ept_caps |
3215                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3216                 break;
3217         case MSR_IA32_VMX_VMFUNC:
3218                 *pdata = vmx->nested.nested_vmx_vmfunc_controls;
3219                 break;
3220         default:
3221                 return 1;
3222         }
3223
3224         return 0;
3225 }
3226
3227 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3228                                                  uint64_t val)
3229 {
3230         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3231
3232         return !(val & ~valid_bits);
3233 }
3234
3235 /*
3236  * Reads an msr value (of 'msr_index') into 'pdata'.
3237  * Returns 0 on success, non-0 otherwise.
3238  * Assumes vcpu_load() was already called.
3239  */
3240 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3241 {
3242         struct shared_msr_entry *msr;
3243
3244         switch (msr_info->index) {
3245 #ifdef CONFIG_X86_64
3246         case MSR_FS_BASE:
3247                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3248                 break;
3249         case MSR_GS_BASE:
3250                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3251                 break;
3252         case MSR_KERNEL_GS_BASE:
3253                 vmx_load_host_state(to_vmx(vcpu));
3254                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3255                 break;
3256 #endif
3257         case MSR_EFER:
3258                 return kvm_get_msr_common(vcpu, msr_info);
3259         case MSR_IA32_TSC:
3260                 msr_info->data = guest_read_tsc(vcpu);
3261                 break;
3262         case MSR_IA32_SYSENTER_CS:
3263                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3264                 break;
3265         case MSR_IA32_SYSENTER_EIP:
3266                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3267                 break;
3268         case MSR_IA32_SYSENTER_ESP:
3269                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3270                 break;
3271         case MSR_IA32_BNDCFGS:
3272                 if (!kvm_mpx_supported() ||
3273                     (!msr_info->host_initiated &&
3274                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3275                         return 1;
3276                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3277                 break;
3278         case MSR_IA32_MCG_EXT_CTL:
3279                 if (!msr_info->host_initiated &&
3280                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3281                       FEATURE_CONTROL_LMCE))
3282                         return 1;
3283                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3284                 break;
3285         case MSR_IA32_FEATURE_CONTROL:
3286                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3287                 break;
3288         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3289                 if (!nested_vmx_allowed(vcpu))
3290                         return 1;
3291                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3292         case MSR_IA32_XSS:
3293                 if (!vmx_xsaves_supported())
3294                         return 1;
3295                 msr_info->data = vcpu->arch.ia32_xss;
3296                 break;
3297         case MSR_TSC_AUX:
3298                 if (!msr_info->host_initiated &&
3299                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3300                         return 1;
3301                 /* Otherwise falls through */
3302         default:
3303                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3304                 if (msr) {
3305                         msr_info->data = msr->data;
3306                         break;
3307                 }
3308                 return kvm_get_msr_common(vcpu, msr_info);
3309         }
3310
3311         return 0;
3312 }
3313
3314 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3315
3316 /*
3317  * Writes msr value into into the appropriate "register".
3318  * Returns 0 on success, non-0 otherwise.
3319  * Assumes vcpu_load() was already called.
3320  */
3321 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3322 {
3323         struct vcpu_vmx *vmx = to_vmx(vcpu);
3324         struct shared_msr_entry *msr;
3325         int ret = 0;
3326         u32 msr_index = msr_info->index;
3327         u64 data = msr_info->data;
3328
3329         switch (msr_index) {
3330         case MSR_EFER:
3331                 ret = kvm_set_msr_common(vcpu, msr_info);
3332                 break;
3333 #ifdef CONFIG_X86_64
3334         case MSR_FS_BASE:
3335                 vmx_segment_cache_clear(vmx);
3336                 vmcs_writel(GUEST_FS_BASE, data);
3337                 break;
3338         case MSR_GS_BASE:
3339                 vmx_segment_cache_clear(vmx);
3340                 vmcs_writel(GUEST_GS_BASE, data);
3341                 break;
3342         case MSR_KERNEL_GS_BASE:
3343                 vmx_load_host_state(vmx);
3344                 vmx->msr_guest_kernel_gs_base = data;
3345                 break;
3346 #endif
3347         case MSR_IA32_SYSENTER_CS:
3348                 vmcs_write32(GUEST_SYSENTER_CS, data);
3349                 break;
3350         case MSR_IA32_SYSENTER_EIP:
3351                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3352                 break;
3353         case MSR_IA32_SYSENTER_ESP:
3354                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3355                 break;
3356         case MSR_IA32_BNDCFGS:
3357                 if (!kvm_mpx_supported() ||
3358                     (!msr_info->host_initiated &&
3359                      !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3360                         return 1;
3361                 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3362                     (data & MSR_IA32_BNDCFGS_RSVD))
3363                         return 1;
3364                 vmcs_write64(GUEST_BNDCFGS, data);
3365                 break;
3366         case MSR_IA32_TSC:
3367                 kvm_write_tsc(vcpu, msr_info);
3368                 break;
3369         case MSR_IA32_CR_PAT:
3370                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3371                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3372                                 return 1;
3373                         vmcs_write64(GUEST_IA32_PAT, data);
3374                         vcpu->arch.pat = data;
3375                         break;
3376                 }
3377                 ret = kvm_set_msr_common(vcpu, msr_info);
3378                 break;
3379         case MSR_IA32_TSC_ADJUST:
3380                 ret = kvm_set_msr_common(vcpu, msr_info);
3381                 break;
3382         case MSR_IA32_MCG_EXT_CTL:
3383                 if ((!msr_info->host_initiated &&
3384                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3385                        FEATURE_CONTROL_LMCE)) ||
3386                     (data & ~MCG_EXT_CTL_LMCE_EN))
3387                         return 1;
3388                 vcpu->arch.mcg_ext_ctl = data;
3389                 break;
3390         case MSR_IA32_FEATURE_CONTROL:
3391                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3392                     (to_vmx(vcpu)->msr_ia32_feature_control &
3393                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3394                         return 1;
3395                 vmx->msr_ia32_feature_control = data;
3396                 if (msr_info->host_initiated && data == 0)
3397                         vmx_leave_nested(vcpu);
3398                 break;
3399         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3400                 if (!msr_info->host_initiated)
3401                         return 1; /* they are read-only */
3402                 if (!nested_vmx_allowed(vcpu))
3403                         return 1;
3404                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3405         case MSR_IA32_XSS:
3406                 if (!vmx_xsaves_supported())
3407                         return 1;
3408                 /*
3409                  * The only supported bit as of Skylake is bit 8, but
3410                  * it is not supported on KVM.
3411                  */
3412                 if (data != 0)
3413                         return 1;
3414                 vcpu->arch.ia32_xss = data;
3415                 if (vcpu->arch.ia32_xss != host_xss)
3416                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3417                                 vcpu->arch.ia32_xss, host_xss);
3418                 else
3419                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3420                 break;
3421         case MSR_TSC_AUX:
3422                 if (!msr_info->host_initiated &&
3423                     !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3424                         return 1;
3425                 /* Check reserved bit, higher 32 bits should be zero */
3426                 if ((data >> 32) != 0)
3427                         return 1;
3428                 /* Otherwise falls through */
3429         default:
3430                 msr = find_msr_entry(vmx, msr_index);
3431                 if (msr) {
3432                         u64 old_msr_data = msr->data;
3433                         msr->data = data;
3434                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3435                                 preempt_disable();
3436                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3437                                                          msr->mask);
3438                                 preempt_enable();
3439                                 if (ret)
3440                                         msr->data = old_msr_data;
3441                         }
3442                         break;
3443                 }
3444                 ret = kvm_set_msr_common(vcpu, msr_info);
3445         }
3446
3447         return ret;
3448 }
3449
3450 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3451 {
3452         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3453         switch (reg) {
3454         case VCPU_REGS_RSP:
3455                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3456                 break;
3457         case VCPU_REGS_RIP:
3458                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3459                 break;
3460         case VCPU_EXREG_PDPTR:
3461                 if (enable_ept)
3462                         ept_save_pdptrs(vcpu);
3463                 break;
3464         default:
3465                 break;
3466         }
3467 }
3468
3469 static __init int cpu_has_kvm_support(void)
3470 {
3471         return cpu_has_vmx();
3472 }
3473
3474 static __init int vmx_disabled_by_bios(void)
3475 {
3476         u64 msr;
3477
3478         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3479         if (msr & FEATURE_CONTROL_LOCKED) {
3480                 /* launched w/ TXT and VMX disabled */
3481                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3482                         && tboot_enabled())
3483                         return 1;
3484                 /* launched w/o TXT and VMX only enabled w/ TXT */
3485                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3486                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3487                         && !tboot_enabled()) {
3488                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3489                                 "activate TXT before enabling KVM\n");
3490                         return 1;
3491                 }
3492                 /* launched w/o TXT and VMX disabled */
3493                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3494                         && !tboot_enabled())
3495                         return 1;
3496         }
3497
3498         return 0;
3499 }
3500
3501 static void kvm_cpu_vmxon(u64 addr)
3502 {
3503         cr4_set_bits(X86_CR4_VMXE);
3504         intel_pt_handle_vmx(1);
3505
3506         asm volatile (ASM_VMX_VMXON_RAX
3507                         : : "a"(&addr), "m"(addr)
3508                         : "memory", "cc");
3509 }
3510
3511 static int hardware_enable(void)
3512 {
3513         int cpu = raw_smp_processor_id();
3514         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3515         u64 old, test_bits;
3516
3517         if (cr4_read_shadow() & X86_CR4_VMXE)
3518                 return -EBUSY;
3519
3520         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3521         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3522         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3523
3524         /*
3525          * Now we can enable the vmclear operation in kdump
3526          * since the loaded_vmcss_on_cpu list on this cpu
3527          * has been initialized.
3528          *
3529          * Though the cpu is not in VMX operation now, there
3530          * is no problem to enable the vmclear operation
3531          * for the loaded_vmcss_on_cpu list is empty!
3532          */
3533         crash_enable_local_vmclear(cpu);
3534
3535         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3536
3537         test_bits = FEATURE_CONTROL_LOCKED;
3538         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3539         if (tboot_enabled())
3540                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3541
3542         if ((old & test_bits) != test_bits) {
3543                 /* enable and lock */
3544                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3545         }
3546         kvm_cpu_vmxon(phys_addr);
3547         ept_sync_global();
3548
3549         return 0;
3550 }
3551
3552 static void vmclear_local_loaded_vmcss(void)
3553 {
3554         int cpu = raw_smp_processor_id();
3555         struct loaded_vmcs *v, *n;
3556
3557         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3558                                  loaded_vmcss_on_cpu_link)
3559                 __loaded_vmcs_clear(v);
3560 }
3561
3562
3563 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3564  * tricks.
3565  */
3566 static void kvm_cpu_vmxoff(void)
3567 {
3568         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3569
3570         intel_pt_handle_vmx(0);
3571         cr4_clear_bits(X86_CR4_VMXE);
3572 }
3573
3574 static void hardware_disable(void)
3575 {
3576         vmclear_local_loaded_vmcss();
3577         kvm_cpu_vmxoff();
3578 }
3579
3580 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3581                                       u32 msr, u32 *result)
3582 {
3583         u32 vmx_msr_low, vmx_msr_high;
3584         u32 ctl = ctl_min | ctl_opt;
3585
3586         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3587
3588         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3589         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3590
3591         /* Ensure minimum (required) set of control bits are supported. */
3592         if (ctl_min & ~ctl)
3593                 return -EIO;
3594
3595         *result = ctl;
3596         return 0;
3597 }
3598
3599 static __init bool allow_1_setting(u32 msr, u32 ctl)
3600 {
3601         u32 vmx_msr_low, vmx_msr_high;
3602
3603         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3604         return vmx_msr_high & ctl;
3605 }
3606
3607 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3608 {
3609         u32 vmx_msr_low, vmx_msr_high;
3610         u32 min, opt, min2, opt2;
3611         u32 _pin_based_exec_control = 0;
3612         u32 _cpu_based_exec_control = 0;
3613         u32 _cpu_based_2nd_exec_control = 0;
3614         u32 _vmexit_control = 0;
3615         u32 _vmentry_control = 0;
3616
3617         min = CPU_BASED_HLT_EXITING |
3618 #ifdef CONFIG_X86_64
3619               CPU_BASED_CR8_LOAD_EXITING |
3620               CPU_BASED_CR8_STORE_EXITING |
3621 #endif
3622               CPU_BASED_CR3_LOAD_EXITING |
3623               CPU_BASED_CR3_STORE_EXITING |
3624               CPU_BASED_USE_IO_BITMAPS |
3625               CPU_BASED_MOV_DR_EXITING |
3626               CPU_BASED_USE_TSC_OFFSETING |
3627               CPU_BASED_INVLPG_EXITING |
3628               CPU_BASED_RDPMC_EXITING;
3629
3630         if (!kvm_mwait_in_guest())
3631                 min |= CPU_BASED_MWAIT_EXITING |
3632                         CPU_BASED_MONITOR_EXITING;
3633
3634         opt = CPU_BASED_TPR_SHADOW |
3635               CPU_BASED_USE_MSR_BITMAPS |
3636               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3637         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3638                                 &_cpu_based_exec_control) < 0)
3639                 return -EIO;
3640 #ifdef CONFIG_X86_64
3641         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3642                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3643                                            ~CPU_BASED_CR8_STORE_EXITING;
3644 #endif
3645         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3646                 min2 = 0;
3647                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3648                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3649                         SECONDARY_EXEC_WBINVD_EXITING |
3650                         SECONDARY_EXEC_ENABLE_VPID |
3651                         SECONDARY_EXEC_ENABLE_EPT |
3652                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3653                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3654                         SECONDARY_EXEC_RDTSCP |
3655                         SECONDARY_EXEC_ENABLE_INVPCID |
3656                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3657                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3658                         SECONDARY_EXEC_SHADOW_VMCS |
3659                         SECONDARY_EXEC_XSAVES |
3660                         SECONDARY_EXEC_RDSEED |
3661                         SECONDARY_EXEC_RDRAND |
3662                         SECONDARY_EXEC_ENABLE_PML |
3663                         SECONDARY_EXEC_TSC_SCALING |
3664                         SECONDARY_EXEC_ENABLE_VMFUNC;
3665                 if (adjust_vmx_controls(min2, opt2,
3666                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3667                                         &_cpu_based_2nd_exec_control) < 0)
3668                         return -EIO;
3669         }
3670 #ifndef CONFIG_X86_64
3671         if (!(_cpu_based_2nd_exec_control &
3672                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3673                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3674 #endif
3675
3676         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3677                 _cpu_based_2nd_exec_control &= ~(
3678                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3679                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3680                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3681
3682         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3683                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3684                    enabled */
3685                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3686                                              CPU_BASED_CR3_STORE_EXITING |
3687                                              CPU_BASED_INVLPG_EXITING);
3688                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3689                       vmx_capability.ept, vmx_capability.vpid);
3690         }
3691
3692         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3693 #ifdef CONFIG_X86_64
3694         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3695 #endif
3696         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3697                 VM_EXIT_CLEAR_BNDCFGS;
3698         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3699                                 &_vmexit_control) < 0)
3700                 return -EIO;
3701
3702         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3703                 PIN_BASED_VIRTUAL_NMIS;
3704         opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3705         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3706                                 &_pin_based_exec_control) < 0)
3707                 return -EIO;
3708
3709         if (cpu_has_broken_vmx_preemption_timer())
3710                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3711         if (!(_cpu_based_2nd_exec_control &
3712                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3713                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3714
3715         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3716         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3717         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3718                                 &_vmentry_control) < 0)
3719                 return -EIO;
3720
3721         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3722
3723         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3724         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3725                 return -EIO;
3726
3727 #ifdef CONFIG_X86_64
3728         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3729         if (vmx_msr_high & (1u<<16))
3730                 return -EIO;
3731 #endif
3732
3733         /* Require Write-Back (WB) memory type for VMCS accesses. */
3734         if (((vmx_msr_high >> 18) & 15) != 6)
3735                 return -EIO;
3736
3737         vmcs_conf->size = vmx_msr_high & 0x1fff;
3738         vmcs_conf->order = get_order(vmcs_conf->size);
3739         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3740         vmcs_conf->revision_id = vmx_msr_low;
3741
3742         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3743         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3744         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3745         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3746         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3747
3748         cpu_has_load_ia32_efer =
3749                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3750                                 VM_ENTRY_LOAD_IA32_EFER)
3751                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3752                                    VM_EXIT_LOAD_IA32_EFER);
3753
3754         cpu_has_load_perf_global_ctrl =
3755                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3756                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3757                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3758                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3759
3760         /*
3761          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3762          * but due to errata below it can't be used. Workaround is to use
3763          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3764          *
3765          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3766          *
3767          * AAK155             (model 26)
3768          * AAP115             (model 30)
3769          * AAT100             (model 37)
3770          * BC86,AAY89,BD102   (model 44)
3771          * BA97               (model 46)
3772          *
3773          */
3774         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3775                 switch (boot_cpu_data.x86_model) {
3776                 case 26:
3777                 case 30:
3778                 case 37:
3779                 case 44:
3780                 case 46:
3781                         cpu_has_load_perf_global_ctrl = false;
3782                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3783                                         "does not work properly. Using workaround\n");
3784                         break;
3785                 default:
3786                         break;
3787                 }
3788         }
3789
3790         if (boot_cpu_has(X86_FEATURE_XSAVES))
3791                 rdmsrl(MSR_IA32_XSS, host_xss);
3792
3793         return 0;
3794 }
3795
3796 static struct vmcs *alloc_vmcs_cpu(int cpu)
3797 {
3798         int node = cpu_to_node(cpu);
3799         struct page *pages;
3800         struct vmcs *vmcs;
3801
3802         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3803         if (!pages)
3804                 return NULL;
3805         vmcs = page_address(pages);
3806         memset(vmcs, 0, vmcs_config.size);
3807         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3808         return vmcs;
3809 }
3810
3811 static struct vmcs *alloc_vmcs(void)
3812 {
3813         return alloc_vmcs_cpu(raw_smp_processor_id());
3814 }
3815
3816 static void free_vmcs(struct vmcs *vmcs)
3817 {
3818         free_pages((unsigned long)vmcs, vmcs_config.order);
3819 }
3820
3821 /*
3822  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3823  */
3824 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3825 {
3826         if (!loaded_vmcs->vmcs)
3827                 return;
3828         loaded_vmcs_clear(loaded_vmcs);
3829         free_vmcs(loaded_vmcs->vmcs);
3830         loaded_vmcs->vmcs = NULL;
3831         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3832 }
3833
3834 static void free_kvm_area(void)
3835 {
3836         int cpu;
3837
3838         for_each_possible_cpu(cpu) {
3839                 free_vmcs(per_cpu(vmxarea, cpu));
3840                 per_cpu(vmxarea, cpu) = NULL;
3841         }
3842 }
3843
3844 enum vmcs_field_type {
3845         VMCS_FIELD_TYPE_U16 = 0,
3846         VMCS_FIELD_TYPE_U64 = 1,
3847         VMCS_FIELD_TYPE_U32 = 2,
3848         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3849 };
3850
3851 static inline int vmcs_field_type(unsigned long field)
3852 {
3853         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
3854                 return VMCS_FIELD_TYPE_U32;
3855         return (field >> 13) & 0x3 ;
3856 }
3857
3858 static inline int vmcs_field_readonly(unsigned long field)
3859 {
3860         return (((field >> 10) & 0x3) == 1);
3861 }
3862
3863 static void init_vmcs_shadow_fields(void)
3864 {
3865         int i, j;
3866
3867         /* No checks for read only fields yet */
3868
3869         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3870                 switch (shadow_read_write_fields[i]) {
3871                 case GUEST_BNDCFGS:
3872                         if (!kvm_mpx_supported())
3873                                 continue;
3874                         break;
3875                 default:
3876                         break;
3877                 }
3878
3879                 if (j < i)
3880                         shadow_read_write_fields[j] =
3881                                 shadow_read_write_fields[i];
3882                 j++;
3883         }
3884         max_shadow_read_write_fields = j;
3885
3886         /* shadowed fields guest access without vmexit */
3887         for (i = 0; i < max_shadow_read_write_fields; i++) {
3888                 unsigned long field = shadow_read_write_fields[i];
3889
3890                 clear_bit(field, vmx_vmwrite_bitmap);
3891                 clear_bit(field, vmx_vmread_bitmap);
3892                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3893                         clear_bit(field + 1, vmx_vmwrite_bitmap);
3894                         clear_bit(field + 1, vmx_vmread_bitmap);
3895                 }
3896         }
3897         for (i = 0; i < max_shadow_read_only_fields; i++) {
3898                 unsigned long field = shadow_read_only_fields[i];
3899
3900                 clear_bit(field, vmx_vmread_bitmap);
3901                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3902                         clear_bit(field + 1, vmx_vmread_bitmap);
3903         }
3904 }
3905
3906 static __init int alloc_kvm_area(void)
3907 {
3908         int cpu;
3909
3910         for_each_possible_cpu(cpu) {
3911                 struct vmcs *vmcs;
3912
3913                 vmcs = alloc_vmcs_cpu(cpu);
3914                 if (!vmcs) {
3915                         free_kvm_area();
3916                         return -ENOMEM;
3917                 }
3918
3919                 per_cpu(vmxarea, cpu) = vmcs;
3920         }
3921         return 0;
3922 }
3923
3924 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3925                 struct kvm_segment *save)
3926 {
3927         if (!emulate_invalid_guest_state) {
3928                 /*
3929                  * CS and SS RPL should be equal during guest entry according
3930                  * to VMX spec, but in reality it is not always so. Since vcpu
3931                  * is in the middle of the transition from real mode to
3932                  * protected mode it is safe to assume that RPL 0 is a good
3933                  * default value.
3934                  */
3935                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3936                         save->selector &= ~SEGMENT_RPL_MASK;
3937                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3938                 save->s = 1;
3939         }
3940         vmx_set_segment(vcpu, save, seg);
3941 }
3942
3943 static void enter_pmode(struct kvm_vcpu *vcpu)
3944 {
3945         unsigned long flags;
3946         struct vcpu_vmx *vmx = to_vmx(vcpu);
3947
3948         /*
3949          * Update real mode segment cache. It may be not up-to-date if sement
3950          * register was written while vcpu was in a guest mode.
3951          */
3952         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3953         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3954         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3955         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3956         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3957         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3958
3959         vmx->rmode.vm86_active = 0;
3960
3961         vmx_segment_cache_clear(vmx);
3962
3963         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3964
3965         flags = vmcs_readl(GUEST_RFLAGS);
3966         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3967         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3968         vmcs_writel(GUEST_RFLAGS, flags);
3969
3970         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3971                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3972
3973         update_exception_bitmap(vcpu);
3974
3975         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3976         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3977         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3978         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3979         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3980         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3981 }
3982
3983 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3984 {
3985         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3986         struct kvm_segment var = *save;
3987
3988         var.dpl = 0x3;
3989         if (seg == VCPU_SREG_CS)
3990                 var.type = 0x3;
3991
3992         if (!emulate_invalid_guest_state) {
3993                 var.selector = var.base >> 4;
3994                 var.base = var.base & 0xffff0;
3995                 var.limit = 0xffff;
3996                 var.g = 0;
3997                 var.db = 0;
3998                 var.present = 1;
3999                 var.s = 1;
4000                 var.l = 0;
4001                 var.unusable = 0;
4002                 var.type = 0x3;
4003                 var.avl = 0;
4004                 if (save->base & 0xf)
4005                         printk_once(KERN_WARNING "kvm: segment base is not "
4006                                         "paragraph aligned when entering "
4007                                         "protected mode (seg=%d)", seg);
4008         }
4009
4010         vmcs_write16(sf->selector, var.selector);
4011         vmcs_writel(sf->base, var.base);
4012         vmcs_write32(sf->limit, var.limit);
4013         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4014 }
4015
4016 static void enter_rmode(struct kvm_vcpu *vcpu)
4017 {
4018         unsigned long flags;
4019         struct vcpu_vmx *vmx = to_vmx(vcpu);
4020
4021         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4022         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4023         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4024         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4025         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4026         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4027         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4028
4029         vmx->rmode.vm86_active = 1;
4030
4031         /*
4032          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4033          * vcpu. Warn the user that an update is overdue.
4034          */
4035         if (!vcpu->kvm->arch.tss_addr)
4036                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4037                              "called before entering vcpu\n");
4038
4039         vmx_segment_cache_clear(vmx);
4040
4041         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
4042         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4043         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4044
4045         flags = vmcs_readl(GUEST_RFLAGS);
4046         vmx->rmode.save_rflags = flags;
4047
4048         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4049
4050         vmcs_writel(GUEST_RFLAGS, flags);
4051         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4052         update_exception_bitmap(vcpu);
4053
4054         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4055         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4056         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4057         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4058         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4059         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4060
4061         kvm_mmu_reset_context(vcpu);
4062 }
4063
4064 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4065 {
4066         struct vcpu_vmx *vmx = to_vmx(vcpu);
4067         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4068
4069         if (!msr)
4070                 return;
4071
4072         /*
4073          * Force kernel_gs_base reloading before EFER changes, as control
4074          * of this msr depends on is_long_mode().
4075          */
4076         vmx_load_host_state(to_vmx(vcpu));
4077         vcpu->arch.efer = efer;
4078         if (efer & EFER_LMA) {
4079                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4080                 msr->data = efer;
4081         } else {
4082                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4083
4084                 msr->data = efer & ~EFER_LME;
4085         }
4086         setup_msrs(vmx);
4087 }
4088
4089 #ifdef CONFIG_X86_64
4090
4091 static void enter_lmode(struct kvm_vcpu *vcpu)
4092 {
4093         u32 guest_tr_ar;
4094
4095         vmx_segment_cache_clear(to_vmx(vcpu));
4096
4097         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4098         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4099                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4100                                      __func__);
4101                 vmcs_write32(GUEST_TR_AR_BYTES,
4102                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4103                              | VMX_AR_TYPE_BUSY_64_TSS);
4104         }
4105         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4106 }
4107
4108 static void exit_lmode(struct kvm_vcpu *vcpu)
4109 {
4110         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4111         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4112 }
4113
4114 #endif
4115
4116 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4117 {
4118         if (enable_ept) {
4119                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4120                         return;
4121                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4122         } else {
4123                 vpid_sync_context(vpid);
4124         }
4125 }
4126
4127 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4128 {
4129         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4130 }
4131
4132 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4133 {
4134         if (enable_ept)
4135                 vmx_flush_tlb(vcpu);
4136 }
4137
4138 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4139 {
4140         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4141
4142         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4143         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4144 }
4145
4146 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4147 {
4148         if (enable_ept && is_paging(vcpu))
4149                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4150         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4151 }
4152
4153 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4154 {
4155         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4156
4157         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4158         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4159 }
4160
4161 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4162 {
4163         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4164
4165         if (!test_bit(VCPU_EXREG_PDPTR,
4166                       (unsigned long *)&vcpu->arch.regs_dirty))
4167                 return;
4168
4169         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4170                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4171                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4172                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4173                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4174         }
4175 }
4176
4177 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4178 {
4179         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4180
4181         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4182                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4183                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4184                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4185                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4186         }
4187
4188         __set_bit(VCPU_EXREG_PDPTR,
4189                   (unsigned long *)&vcpu->arch.regs_avail);
4190         __set_bit(VCPU_EXREG_PDPTR,
4191                   (unsigned long *)&vcpu->arch.regs_dirty);
4192 }
4193
4194 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4195 {
4196         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4197         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4198         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4199
4200         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4201                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4202             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4203                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4204
4205         return fixed_bits_valid(val, fixed0, fixed1);
4206 }
4207
4208 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4209 {
4210         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4211         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4212
4213         return fixed_bits_valid(val, fixed0, fixed1);
4214 }
4215
4216 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4217 {
4218         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4219         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4220
4221         return fixed_bits_valid(val, fixed0, fixed1);
4222 }
4223
4224 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4225 #define nested_guest_cr4_valid  nested_cr4_valid
4226 #define nested_host_cr4_valid   nested_cr4_valid
4227
4228 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4229
4230 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4231                                         unsigned long cr0,
4232                                         struct kvm_vcpu *vcpu)
4233 {
4234         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4235                 vmx_decache_cr3(vcpu);
4236         if (!(cr0 & X86_CR0_PG)) {
4237                 /* From paging/starting to nonpaging */
4238                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4239                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4240                              (CPU_BASED_CR3_LOAD_EXITING |
4241                               CPU_BASED_CR3_STORE_EXITING));
4242                 vcpu->arch.cr0 = cr0;
4243                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4244         } else if (!is_paging(vcpu)) {
4245                 /* From nonpaging to paging */
4246                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4247                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4248                              ~(CPU_BASED_CR3_LOAD_EXITING |
4249                                CPU_BASED_CR3_STORE_EXITING));
4250                 vcpu->arch.cr0 = cr0;
4251                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4252         }
4253
4254         if (!(cr0 & X86_CR0_WP))
4255                 *hw_cr0 &= ~X86_CR0_WP;
4256 }
4257
4258 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4259 {
4260         struct vcpu_vmx *vmx = to_vmx(vcpu);
4261         unsigned long hw_cr0;
4262
4263         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4264         if (enable_unrestricted_guest)
4265                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4266         else {
4267                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4268
4269                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4270                         enter_pmode(vcpu);
4271
4272                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4273                         enter_rmode(vcpu);
4274         }
4275
4276 #ifdef CONFIG_X86_64
4277         if (vcpu->arch.efer & EFER_LME) {
4278                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4279                         enter_lmode(vcpu);
4280                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4281                         exit_lmode(vcpu);
4282         }
4283 #endif
4284
4285         if (enable_ept)
4286                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4287
4288         vmcs_writel(CR0_READ_SHADOW, cr0);
4289         vmcs_writel(GUEST_CR0, hw_cr0);
4290         vcpu->arch.cr0 = cr0;
4291
4292         /* depends on vcpu->arch.cr0 to be set to a new value */
4293         vmx->emulation_required = emulation_required(vcpu);
4294 }
4295
4296 static int get_ept_level(struct kvm_vcpu *vcpu)
4297 {
4298         if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4299                 return 5;
4300         return 4;
4301 }
4302
4303 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4304 {
4305         u64 eptp = VMX_EPTP_MT_WB;
4306
4307         eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4308
4309         if (enable_ept_ad_bits &&
4310             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4311                 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4312         eptp |= (root_hpa & PAGE_MASK);
4313
4314         return eptp;
4315 }
4316
4317 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4318 {
4319         unsigned long guest_cr3;
4320         u64 eptp;
4321
4322         guest_cr3 = cr3;
4323         if (enable_ept) {
4324                 eptp = construct_eptp(vcpu, cr3);
4325                 vmcs_write64(EPT_POINTER, eptp);
4326                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4327                         guest_cr3 = kvm_read_cr3(vcpu);
4328                 else
4329                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4330                 ept_load_pdptrs(vcpu);
4331         }
4332
4333         vmx_flush_tlb(vcpu);
4334         vmcs_writel(GUEST_CR3, guest_cr3);
4335 }
4336
4337 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4338 {
4339         /*
4340          * Pass through host's Machine Check Enable value to hw_cr4, which
4341          * is in force while we are in guest mode.  Do not let guests control
4342          * this bit, even if host CR4.MCE == 0.
4343          */
4344         unsigned long hw_cr4 =
4345                 (cr4_read_shadow() & X86_CR4_MCE) |
4346                 (cr4 & ~X86_CR4_MCE) |
4347                 (to_vmx(vcpu)->rmode.vm86_active ?
4348                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4349
4350         if (cr4 & X86_CR4_VMXE) {
4351                 /*
4352                  * To use VMXON (and later other VMX instructions), a guest
4353                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4354                  * So basically the check on whether to allow nested VMX
4355                  * is here.
4356                  */
4357                 if (!nested_vmx_allowed(vcpu))
4358                         return 1;
4359         }
4360
4361         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4362                 return 1;
4363
4364         vcpu->arch.cr4 = cr4;
4365         if (enable_ept) {
4366                 if (!is_paging(vcpu)) {
4367                         hw_cr4 &= ~X86_CR4_PAE;
4368                         hw_cr4 |= X86_CR4_PSE;
4369                 } else if (!(cr4 & X86_CR4_PAE)) {
4370                         hw_cr4 &= ~X86_CR4_PAE;
4371                 }
4372         }
4373
4374         if (!enable_unrestricted_guest && !is_paging(vcpu))
4375                 /*
4376                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4377                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4378                  * to be manually disabled when guest switches to non-paging
4379                  * mode.
4380                  *
4381                  * If !enable_unrestricted_guest, the CPU is always running
4382                  * with CR0.PG=1 and CR4 needs to be modified.
4383                  * If enable_unrestricted_guest, the CPU automatically
4384                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4385                  */
4386                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4387
4388         vmcs_writel(CR4_READ_SHADOW, cr4);
4389         vmcs_writel(GUEST_CR4, hw_cr4);
4390         return 0;
4391 }
4392
4393 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4394                             struct kvm_segment *var, int seg)
4395 {
4396         struct vcpu_vmx *vmx = to_vmx(vcpu);
4397         u32 ar;
4398
4399         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4400                 *var = vmx->rmode.segs[seg];
4401                 if (seg == VCPU_SREG_TR
4402                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4403                         return;
4404                 var->base = vmx_read_guest_seg_base(vmx, seg);
4405                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4406                 return;
4407         }
4408         var->base = vmx_read_guest_seg_base(vmx, seg);
4409         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4410         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4411         ar = vmx_read_guest_seg_ar(vmx, seg);
4412         var->unusable = (ar >> 16) & 1;
4413         var->type = ar & 15;
4414         var->s = (ar >> 4) & 1;
4415         var->dpl = (ar >> 5) & 3;
4416         /*
4417          * Some userspaces do not preserve unusable property. Since usable
4418          * segment has to be present according to VMX spec we can use present
4419          * property to amend userspace bug by making unusable segment always
4420          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4421          * segment as unusable.
4422          */
4423         var->present = !var->unusable;
4424         var->avl = (ar >> 12) & 1;
4425         var->l = (ar >> 13) & 1;
4426         var->db = (ar >> 14) & 1;
4427         var->g = (ar >> 15) & 1;
4428 }
4429
4430 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4431 {
4432         struct kvm_segment s;
4433
4434         if (to_vmx(vcpu)->rmode.vm86_active) {
4435                 vmx_get_segment(vcpu, &s, seg);
4436                 return s.base;
4437         }
4438         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4439 }
4440
4441 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4442 {
4443         struct vcpu_vmx *vmx = to_vmx(vcpu);
4444
4445         if (unlikely(vmx->rmode.vm86_active))
4446                 return 0;
4447         else {
4448                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4449                 return VMX_AR_DPL(ar);
4450         }
4451 }
4452
4453 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4454 {
4455         u32 ar;
4456
4457         if (var->unusable || !var->present)
4458                 ar = 1 << 16;
4459         else {
4460                 ar = var->type & 15;
4461                 ar |= (var->s & 1) << 4;
4462                 ar |= (var->dpl & 3) << 5;
4463                 ar |= (var->present & 1) << 7;
4464                 ar |= (var->avl & 1) << 12;
4465                 ar |= (var->l & 1) << 13;
4466                 ar |= (var->db & 1) << 14;
4467                 ar |= (var->g & 1) << 15;
4468         }
4469
4470         return ar;
4471 }
4472
4473 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4474                             struct kvm_segment *var, int seg)
4475 {
4476         struct vcpu_vmx *vmx = to_vmx(vcpu);
4477         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4478
4479         vmx_segment_cache_clear(vmx);
4480
4481         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4482                 vmx->rmode.segs[seg] = *var;
4483                 if (seg == VCPU_SREG_TR)
4484                         vmcs_write16(sf->selector, var->selector);
4485                 else if (var->s)
4486                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4487                 goto out;
4488         }
4489
4490         vmcs_writel(sf->base, var->base);
4491         vmcs_write32(sf->limit, var->limit);
4492         vmcs_write16(sf->selector, var->selector);
4493
4494         /*
4495          *   Fix the "Accessed" bit in AR field of segment registers for older
4496          * qemu binaries.
4497          *   IA32 arch specifies that at the time of processor reset the
4498          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4499          * is setting it to 0 in the userland code. This causes invalid guest
4500          * state vmexit when "unrestricted guest" mode is turned on.
4501          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4502          * tree. Newer qemu binaries with that qemu fix would not need this
4503          * kvm hack.
4504          */
4505         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4506                 var->type |= 0x1; /* Accessed */
4507
4508         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4509
4510 out:
4511         vmx->emulation_required = emulation_required(vcpu);
4512 }
4513
4514 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4515 {
4516         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4517
4518         *db = (ar >> 14) & 1;
4519         *l = (ar >> 13) & 1;
4520 }
4521
4522 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4523 {
4524         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4525         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4526 }
4527
4528 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4529 {
4530         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4531         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4532 }
4533
4534 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4535 {
4536         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4537         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4538 }
4539
4540 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4541 {
4542         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4543         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4544 }
4545
4546 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4547 {
4548         struct kvm_segment var;
4549         u32 ar;
4550
4551         vmx_get_segment(vcpu, &var, seg);
4552         var.dpl = 0x3;
4553         if (seg == VCPU_SREG_CS)
4554                 var.type = 0x3;
4555         ar = vmx_segment_access_rights(&var);
4556
4557         if (var.base != (var.selector << 4))
4558                 return false;
4559         if (var.limit != 0xffff)
4560                 return false;
4561         if (ar != 0xf3)
4562                 return false;
4563
4564         return true;
4565 }
4566
4567 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4568 {
4569         struct kvm_segment cs;
4570         unsigned int cs_rpl;
4571
4572         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4573         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4574
4575         if (cs.unusable)
4576                 return false;
4577         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4578                 return false;
4579         if (!cs.s)
4580                 return false;
4581         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4582                 if (cs.dpl > cs_rpl)
4583                         return false;
4584         } else {
4585                 if (cs.dpl != cs_rpl)
4586                         return false;
4587         }
4588         if (!cs.present)
4589                 return false;
4590
4591         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4592         return true;
4593 }
4594
4595 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4596 {
4597         struct kvm_segment ss;
4598         unsigned int ss_rpl;
4599
4600         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4601         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4602
4603         if (ss.unusable)
4604                 return true;
4605         if (ss.type != 3 && ss.type != 7)
4606                 return false;
4607         if (!ss.s)
4608                 return false;
4609         if (ss.dpl != ss_rpl) /* DPL != RPL */
4610                 return false;
4611         if (!ss.present)
4612                 return false;
4613
4614         return true;
4615 }
4616
4617 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4618 {
4619         struct kvm_segment var;
4620         unsigned int rpl;
4621
4622         vmx_get_segment(vcpu, &var, seg);
4623         rpl = var.selector & SEGMENT_RPL_MASK;
4624
4625         if (var.unusable)
4626                 return true;
4627         if (!var.s)
4628                 return false;
4629         if (!var.present)
4630                 return false;
4631         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4632                 if (var.dpl < rpl) /* DPL < RPL */
4633                         return false;
4634         }
4635
4636         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4637          * rights flags
4638          */
4639         return true;
4640 }
4641
4642 static bool tr_valid(struct kvm_vcpu *vcpu)
4643 {
4644         struct kvm_segment tr;
4645
4646         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4647
4648         if (tr.unusable)
4649                 return false;
4650         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4651                 return false;
4652         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4653                 return false;
4654         if (!tr.present)
4655                 return false;
4656
4657         return true;
4658 }
4659
4660 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4661 {
4662         struct kvm_segment ldtr;
4663
4664         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4665
4666         if (ldtr.unusable)
4667                 return true;
4668         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4669                 return false;
4670         if (ldtr.type != 2)
4671                 return false;
4672         if (!ldtr.present)
4673                 return false;
4674
4675         return true;
4676 }
4677
4678 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4679 {
4680         struct kvm_segment cs, ss;
4681
4682         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4683         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4684
4685         return ((cs.selector & SEGMENT_RPL_MASK) ==
4686                  (ss.selector & SEGMENT_RPL_MASK));
4687 }
4688
4689 /*
4690  * Check if guest state is valid. Returns true if valid, false if
4691  * not.
4692  * We assume that registers are always usable
4693  */
4694 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4695 {
4696         if (enable_unrestricted_guest)
4697                 return true;
4698
4699         /* real mode guest state checks */
4700         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4701                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4702                         return false;
4703                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4704                         return false;
4705                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4706                         return false;
4707                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4708                         return false;
4709                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4710                         return false;
4711                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4712                         return false;
4713         } else {
4714         /* protected mode guest state checks */
4715                 if (!cs_ss_rpl_check(vcpu))
4716                         return false;
4717                 if (!code_segment_valid(vcpu))
4718                         return false;
4719                 if (!stack_segment_valid(vcpu))
4720                         return false;
4721                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4722                         return false;
4723                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4724                         return false;
4725                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4726                         return false;
4727                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4728                         return false;
4729                 if (!tr_valid(vcpu))
4730                         return false;
4731                 if (!ldtr_valid(vcpu))
4732                         return false;
4733         }
4734         /* TODO:
4735          * - Add checks on RIP
4736          * - Add checks on RFLAGS
4737          */
4738
4739         return true;
4740 }
4741
4742 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4743 {
4744         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4745 }
4746
4747 static int init_rmode_tss(struct kvm *kvm)
4748 {
4749         gfn_t fn;
4750         u16 data = 0;
4751         int idx, r;
4752
4753         idx = srcu_read_lock(&kvm->srcu);
4754         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4755         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4756         if (r < 0)
4757                 goto out;
4758         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4759         r = kvm_write_guest_page(kvm, fn++, &data,
4760                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4761         if (r < 0)
4762                 goto out;
4763         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4764         if (r < 0)
4765                 goto out;
4766         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4767         if (r < 0)
4768                 goto out;
4769         data = ~0;
4770         r = kvm_write_guest_page(kvm, fn, &data,
4771                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4772                                  sizeof(u8));
4773 out:
4774         srcu_read_unlock(&kvm->srcu, idx);
4775         return r;
4776 }
4777
4778 static int init_rmode_identity_map(struct kvm *kvm)
4779 {
4780         int i, idx, r = 0;
4781         kvm_pfn_t identity_map_pfn;
4782         u32 tmp;
4783
4784         if (!enable_ept)
4785                 return 0;
4786
4787         /* Protect kvm->arch.ept_identity_pagetable_done. */
4788         mutex_lock(&kvm->slots_lock);
4789
4790         if (likely(kvm->arch.ept_identity_pagetable_done))
4791                 goto out2;
4792
4793         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4794
4795         r = alloc_identity_pagetable(kvm);
4796         if (r < 0)
4797                 goto out2;
4798
4799         idx = srcu_read_lock(&kvm->srcu);
4800         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4801         if (r < 0)
4802                 goto out;
4803         /* Set up identity-mapping pagetable for EPT in real mode */
4804         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4805                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4806                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4807                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4808                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4809                 if (r < 0)
4810                         goto out;
4811         }
4812         kvm->arch.ept_identity_pagetable_done = true;
4813
4814 out:
4815         srcu_read_unlock(&kvm->srcu, idx);
4816
4817 out2:
4818         mutex_unlock(&kvm->slots_lock);
4819         return r;
4820 }
4821
4822 static void seg_setup(int seg)
4823 {
4824         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4825         unsigned int ar;
4826
4827         vmcs_write16(sf->selector, 0);
4828         vmcs_writel(sf->base, 0);
4829         vmcs_write32(sf->limit, 0xffff);
4830         ar = 0x93;
4831         if (seg == VCPU_SREG_CS)
4832                 ar |= 0x08; /* code segment */
4833
4834         vmcs_write32(sf->ar_bytes, ar);
4835 }
4836
4837 static int alloc_apic_access_page(struct kvm *kvm)
4838 {
4839         struct page *page;
4840         int r = 0;
4841
4842         mutex_lock(&kvm->slots_lock);
4843         if (kvm->arch.apic_access_page_done)
4844                 goto out;
4845         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4846                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4847         if (r)
4848                 goto out;
4849
4850         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4851         if (is_error_page(page)) {
4852                 r = -EFAULT;
4853                 goto out;
4854         }
4855
4856         /*
4857          * Do not pin the page in memory, so that memory hot-unplug
4858          * is able to migrate it.
4859          */
4860         put_page(page);
4861         kvm->arch.apic_access_page_done = true;
4862 out:
4863         mutex_unlock(&kvm->slots_lock);
4864         return r;
4865 }
4866
4867 static int alloc_identity_pagetable(struct kvm *kvm)
4868 {
4869         /* Called with kvm->slots_lock held. */
4870
4871         int r = 0;
4872
4873         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4874
4875         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4876                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4877
4878         return r;
4879 }
4880
4881 static int allocate_vpid(void)
4882 {
4883         int vpid;
4884
4885         if (!enable_vpid)
4886                 return 0;
4887         spin_lock(&vmx_vpid_lock);
4888         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4889         if (vpid < VMX_NR_VPIDS)
4890                 __set_bit(vpid, vmx_vpid_bitmap);
4891         else
4892                 vpid = 0;
4893         spin_unlock(&vmx_vpid_lock);
4894         return vpid;
4895 }
4896
4897 static void free_vpid(int vpid)
4898 {
4899         if (!enable_vpid || vpid == 0)
4900                 return;
4901         spin_lock(&vmx_vpid_lock);
4902         __clear_bit(vpid, vmx_vpid_bitmap);
4903         spin_unlock(&vmx_vpid_lock);
4904 }
4905
4906 #define MSR_TYPE_R      1
4907 #define MSR_TYPE_W      2
4908 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4909                                                 u32 msr, int type)
4910 {
4911         int f = sizeof(unsigned long);
4912
4913         if (!cpu_has_vmx_msr_bitmap())
4914                 return;
4915
4916         /*
4917          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4918          * have the write-low and read-high bitmap offsets the wrong way round.
4919          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4920          */
4921         if (msr <= 0x1fff) {
4922                 if (type & MSR_TYPE_R)
4923                         /* read-low */
4924                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4925
4926                 if (type & MSR_TYPE_W)
4927                         /* write-low */
4928                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4929
4930         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4931                 msr &= 0x1fff;
4932                 if (type & MSR_TYPE_R)
4933                         /* read-high */
4934                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4935
4936                 if (type & MSR_TYPE_W)
4937                         /* write-high */
4938                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4939
4940         }
4941 }
4942
4943 /*
4944  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4945  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4946  */
4947 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4948                                                unsigned long *msr_bitmap_nested,
4949                                                u32 msr, int type)
4950 {
4951         int f = sizeof(unsigned long);
4952
4953         if (!cpu_has_vmx_msr_bitmap()) {
4954                 WARN_ON(1);
4955                 return;
4956         }
4957
4958         /*
4959          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4960          * have the write-low and read-high bitmap offsets the wrong way round.
4961          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4962          */
4963         if (msr <= 0x1fff) {
4964                 if (type & MSR_TYPE_R &&
4965                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4966                         /* read-low */
4967                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4968
4969                 if (type & MSR_TYPE_W &&
4970                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4971                         /* write-low */
4972                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4973
4974         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4975                 msr &= 0x1fff;
4976                 if (type & MSR_TYPE_R &&
4977                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4978                         /* read-high */
4979                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4980
4981                 if (type & MSR_TYPE_W &&
4982                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4983                         /* write-high */
4984                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4985
4986         }
4987 }
4988
4989 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4990 {
4991         if (!longmode_only)
4992                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4993                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4994         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4995                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4996 }
4997
4998 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4999 {
5000         if (apicv_active) {
5001                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
5002                                 msr, type);
5003                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
5004                                 msr, type);
5005         } else {
5006                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
5007                                 msr, type);
5008                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
5009                                 msr, type);
5010         }
5011 }
5012
5013 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5014 {
5015         return enable_apicv;
5016 }
5017
5018 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5019 {
5020         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5021         gfn_t gfn;
5022
5023         /*
5024          * Don't need to mark the APIC access page dirty; it is never
5025          * written to by the CPU during APIC virtualization.
5026          */
5027
5028         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5029                 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5030                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5031         }
5032
5033         if (nested_cpu_has_posted_intr(vmcs12)) {
5034                 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5035                 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5036         }
5037 }
5038
5039
5040 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5041 {
5042         struct vcpu_vmx *vmx = to_vmx(vcpu);
5043         int max_irr;
5044         void *vapic_page;
5045         u16 status;
5046
5047         if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5048                 return;
5049
5050         vmx->nested.pi_pending = false;
5051         if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5052                 return;
5053
5054         max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5055         if (max_irr != 256) {
5056                 vapic_page = kmap(vmx->nested.virtual_apic_page);
5057                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
5058                 kunmap(vmx->nested.virtual_apic_page);
5059
5060                 status = vmcs_read16(GUEST_INTR_STATUS);
5061                 if ((u8)max_irr > ((u8)status & 0xff)) {
5062                         status &= ~0xff;
5063                         status |= (u8)max_irr;
5064                         vmcs_write16(GUEST_INTR_STATUS, status);
5065                 }
5066         }
5067
5068         nested_mark_vmcs12_pages_dirty(vcpu);
5069 }
5070
5071 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5072                                                      bool nested)
5073 {
5074 #ifdef CONFIG_SMP
5075         int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5076
5077         if (vcpu->mode == IN_GUEST_MODE) {
5078                 /*
5079                  * The vector of interrupt to be delivered to vcpu had
5080                  * been set in PIR before this function.
5081                  *
5082                  * Following cases will be reached in this block, and
5083                  * we always send a notification event in all cases as
5084                  * explained below.
5085                  *
5086                  * Case 1: vcpu keeps in non-root mode. Sending a
5087                  * notification event posts the interrupt to vcpu.
5088                  *
5089                  * Case 2: vcpu exits to root mode and is still
5090                  * runnable. PIR will be synced to vIRR before the
5091                  * next vcpu entry. Sending a notification event in
5092                  * this case has no effect, as vcpu is not in root
5093                  * mode.
5094                  *
5095                  * Case 3: vcpu exits to root mode and is blocked.
5096                  * vcpu_block() has already synced PIR to vIRR and
5097                  * never blocks vcpu if vIRR is not cleared. Therefore,
5098                  * a blocked vcpu here does not wait for any requested
5099                  * interrupts in PIR, and sending a notification event
5100                  * which has no effect is safe here.
5101                  */
5102
5103                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5104                 return true;
5105         }
5106 #endif
5107         return false;
5108 }
5109
5110 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5111                                                 int vector)
5112 {
5113         struct vcpu_vmx *vmx = to_vmx(vcpu);
5114
5115         if (is_guest_mode(vcpu) &&
5116             vector == vmx->nested.posted_intr_nv) {
5117                 /* the PIR and ON have been set by L1. */
5118                 kvm_vcpu_trigger_posted_interrupt(vcpu, true);
5119                 /*
5120                  * If a posted intr is not recognized by hardware,
5121                  * we will accomplish it in the next vmentry.
5122                  */
5123                 vmx->nested.pi_pending = true;
5124                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5125                 return 0;
5126         }
5127         return -1;
5128 }
5129 /*
5130  * Send interrupt to vcpu via posted interrupt way.
5131  * 1. If target vcpu is running(non-root mode), send posted interrupt
5132  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5133  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5134  * interrupt from PIR in next vmentry.
5135  */
5136 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5137 {
5138         struct vcpu_vmx *vmx = to_vmx(vcpu);
5139         int r;
5140
5141         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5142         if (!r)
5143                 return;
5144
5145         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5146                 return;
5147
5148         /* If a previous notification has sent the IPI, nothing to do.  */
5149         if (pi_test_and_set_on(&vmx->pi_desc))
5150                 return;
5151
5152         if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5153                 kvm_vcpu_kick(vcpu);
5154 }
5155
5156 /*
5157  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5158  * will not change in the lifetime of the guest.
5159  * Note that host-state that does change is set elsewhere. E.g., host-state
5160  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5161  */
5162 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5163 {
5164         u32 low32, high32;
5165         unsigned long tmpl;
5166         struct desc_ptr dt;
5167         unsigned long cr0, cr3, cr4;
5168
5169         cr0 = read_cr0();
5170         WARN_ON(cr0 & X86_CR0_TS);
5171         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5172
5173         /*
5174          * Save the most likely value for this task's CR3 in the VMCS.
5175          * We can't use __get_current_cr3_fast() because we're not atomic.
5176          */
5177         cr3 = __read_cr3();
5178         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5179         vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5180
5181         /* Save the most likely value for this task's CR4 in the VMCS. */
5182         cr4 = cr4_read_shadow();
5183         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5184         vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5185
5186         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5187 #ifdef CONFIG_X86_64
5188         /*
5189          * Load null selectors, so we can avoid reloading them in
5190          * __vmx_load_host_state(), in case userspace uses the null selectors
5191          * too (the expected case).
5192          */
5193         vmcs_write16(HOST_DS_SELECTOR, 0);
5194         vmcs_write16(HOST_ES_SELECTOR, 0);
5195 #else
5196         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5197         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5198 #endif
5199         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5200         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5201
5202         store_idt(&dt);
5203         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5204         vmx->host_idt_base = dt.address;
5205
5206         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5207
5208         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5209         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5210         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5211         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5212
5213         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5214                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5215                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5216         }
5217 }
5218
5219 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5220 {
5221         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5222         if (enable_ept)
5223                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5224         if (is_guest_mode(&vmx->vcpu))
5225                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5226                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5227         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5228 }
5229
5230 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5231 {
5232         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5233
5234         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5235                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5236         /* Enable the preemption timer dynamically */
5237         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5238         return pin_based_exec_ctrl;
5239 }
5240
5241 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5242 {
5243         struct vcpu_vmx *vmx = to_vmx(vcpu);
5244
5245         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5246         if (cpu_has_secondary_exec_ctrls()) {
5247                 if (kvm_vcpu_apicv_active(vcpu))
5248                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5249                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5250                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5251                 else
5252                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5253                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5254                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5255         }
5256
5257         if (cpu_has_vmx_msr_bitmap())
5258                 vmx_set_msr_bitmap(vcpu);
5259 }
5260
5261 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5262 {
5263         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5264
5265         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5266                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5267
5268         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5269                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5270 #ifdef CONFIG_X86_64
5271                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5272                                 CPU_BASED_CR8_LOAD_EXITING;
5273 #endif
5274         }
5275         if (!enable_ept)
5276                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5277                                 CPU_BASED_CR3_LOAD_EXITING  |
5278                                 CPU_BASED_INVLPG_EXITING;
5279         return exec_control;
5280 }
5281
5282 static bool vmx_rdrand_supported(void)
5283 {
5284         return vmcs_config.cpu_based_2nd_exec_ctrl &
5285                 SECONDARY_EXEC_RDRAND;
5286 }
5287
5288 static bool vmx_rdseed_supported(void)
5289 {
5290         return vmcs_config.cpu_based_2nd_exec_ctrl &
5291                 SECONDARY_EXEC_RDSEED;
5292 }
5293
5294 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
5295 {
5296         struct kvm_vcpu *vcpu = &vmx->vcpu;
5297
5298         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5299         if (!cpu_need_virtualize_apic_accesses(vcpu))
5300                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5301         if (vmx->vpid == 0)
5302                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5303         if (!enable_ept) {
5304                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5305                 enable_unrestricted_guest = 0;
5306                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5307                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5308         }
5309         if (!enable_unrestricted_guest)
5310                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5311         if (!ple_gap)
5312                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5313         if (!kvm_vcpu_apicv_active(vcpu))
5314                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5315                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5316         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5317         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5318            (handle_vmptrld).
5319            We can NOT enable shadow_vmcs here because we don't have yet
5320            a current VMCS12
5321         */
5322         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5323
5324         if (!enable_pml)
5325                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5326
5327         if (vmx_xsaves_supported()) {
5328                 /* Exposing XSAVES only when XSAVE is exposed */
5329                 bool xsaves_enabled =
5330                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
5331                         guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
5332
5333                 if (!xsaves_enabled)
5334                         exec_control &= ~SECONDARY_EXEC_XSAVES;
5335
5336                 if (nested) {
5337                         if (xsaves_enabled)
5338                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5339                                         SECONDARY_EXEC_XSAVES;
5340                         else
5341                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5342                                         ~SECONDARY_EXEC_XSAVES;
5343                 }
5344         }
5345
5346         if (vmx_rdtscp_supported()) {
5347                 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
5348                 if (!rdtscp_enabled)
5349                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
5350
5351                 if (nested) {
5352                         if (rdtscp_enabled)
5353                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5354                                         SECONDARY_EXEC_RDTSCP;
5355                         else
5356                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5357                                         ~SECONDARY_EXEC_RDTSCP;
5358                 }
5359         }
5360
5361         if (vmx_invpcid_supported()) {
5362                 /* Exposing INVPCID only when PCID is exposed */
5363                 bool invpcid_enabled =
5364                         guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
5365                         guest_cpuid_has(vcpu, X86_FEATURE_PCID);
5366
5367                 if (!invpcid_enabled) {
5368                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5369                         guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
5370                 }
5371
5372                 if (nested) {
5373                         if (invpcid_enabled)
5374                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5375                                         SECONDARY_EXEC_ENABLE_INVPCID;
5376                         else
5377                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5378                                         ~SECONDARY_EXEC_ENABLE_INVPCID;
5379                 }
5380         }
5381
5382         if (vmx_rdrand_supported()) {
5383                 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
5384                 if (rdrand_enabled)
5385                         exec_control &= ~SECONDARY_EXEC_RDRAND;
5386
5387                 if (nested) {
5388                         if (rdrand_enabled)
5389                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5390                                         SECONDARY_EXEC_RDRAND;
5391                         else
5392                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5393                                         ~SECONDARY_EXEC_RDRAND;
5394                 }
5395         }
5396
5397         if (vmx_rdseed_supported()) {
5398                 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
5399                 if (rdseed_enabled)
5400                         exec_control &= ~SECONDARY_EXEC_RDSEED;
5401
5402                 if (nested) {
5403                         if (rdseed_enabled)
5404                                 vmx->nested.nested_vmx_secondary_ctls_high |=
5405                                         SECONDARY_EXEC_RDSEED;
5406                         else
5407                                 vmx->nested.nested_vmx_secondary_ctls_high &=
5408                                         ~SECONDARY_EXEC_RDSEED;
5409                 }
5410         }
5411
5412         vmx->secondary_exec_control = exec_control;
5413 }
5414
5415 static void ept_set_mmio_spte_mask(void)
5416 {
5417         /*
5418          * EPT Misconfigurations can be generated if the value of bits 2:0
5419          * of an EPT paging-structure entry is 110b (write/execute).
5420          */
5421         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5422                                    VMX_EPT_MISCONFIG_WX_VALUE);
5423 }
5424
5425 #define VMX_XSS_EXIT_BITMAP 0
5426 /*
5427  * Sets up the vmcs for emulated real mode.
5428  */
5429 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5430 {
5431 #ifdef CONFIG_X86_64
5432         unsigned long a;
5433 #endif
5434         int i;
5435
5436         /* I/O */
5437         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5438         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5439
5440         if (enable_shadow_vmcs) {
5441                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5442                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5443         }
5444         if (cpu_has_vmx_msr_bitmap())
5445                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5446
5447         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5448
5449         /* Control */
5450         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5451         vmx->hv_deadline_tsc = -1;
5452
5453         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5454
5455         if (cpu_has_secondary_exec_ctrls()) {
5456                 vmx_compute_secondary_exec_control(vmx);
5457                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5458                              vmx->secondary_exec_control);
5459         }
5460
5461         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5462                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5463                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5464                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5465                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5466
5467                 vmcs_write16(GUEST_INTR_STATUS, 0);
5468
5469                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5470                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5471         }
5472
5473         if (ple_gap) {
5474                 vmcs_write32(PLE_GAP, ple_gap);
5475                 vmx->ple_window = ple_window;
5476                 vmx->ple_window_dirty = true;
5477         }
5478
5479         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5480         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5481         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5482
5483         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5484         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5485         vmx_set_constant_host_state(vmx);
5486 #ifdef CONFIG_X86_64
5487         rdmsrl(MSR_FS_BASE, a);
5488         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5489         rdmsrl(MSR_GS_BASE, a);
5490         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5491 #else
5492         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5493         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5494 #endif
5495
5496         if (cpu_has_vmx_vmfunc())
5497                 vmcs_write64(VM_FUNCTION_CONTROL, 0);
5498
5499         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5500         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5501         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5502         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5503         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5504
5505         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5506                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5507
5508         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5509                 u32 index = vmx_msr_index[i];
5510                 u32 data_low, data_high;
5511                 int j = vmx->nmsrs;
5512
5513                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5514                         continue;
5515                 if (wrmsr_safe(index, data_low, data_high) < 0)
5516                         continue;
5517                 vmx->guest_msrs[j].index = i;
5518                 vmx->guest_msrs[j].data = 0;
5519                 vmx->guest_msrs[j].mask = -1ull;
5520                 ++vmx->nmsrs;
5521         }
5522
5523
5524         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5525
5526         /* 22.2.1, 20.8.1 */
5527         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5528
5529         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5530         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5531
5532         set_cr4_guest_host_mask(vmx);
5533
5534         if (vmx_xsaves_supported())
5535                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5536
5537         if (enable_pml) {
5538                 ASSERT(vmx->pml_pg);
5539                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5540                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5541         }
5542
5543         return 0;
5544 }
5545
5546 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5547 {
5548         struct vcpu_vmx *vmx = to_vmx(vcpu);
5549         struct msr_data apic_base_msr;
5550         u64 cr0;
5551
5552         vmx->rmode.vm86_active = 0;
5553
5554         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5555         kvm_set_cr8(vcpu, 0);
5556
5557         if (!init_event) {
5558                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5559                                      MSR_IA32_APICBASE_ENABLE;
5560                 if (kvm_vcpu_is_reset_bsp(vcpu))
5561                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5562                 apic_base_msr.host_initiated = true;
5563                 kvm_set_apic_base(vcpu, &apic_base_msr);
5564         }
5565
5566         vmx_segment_cache_clear(vmx);
5567
5568         seg_setup(VCPU_SREG_CS);
5569         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5570         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5571
5572         seg_setup(VCPU_SREG_DS);
5573         seg_setup(VCPU_SREG_ES);
5574         seg_setup(VCPU_SREG_FS);
5575         seg_setup(VCPU_SREG_GS);
5576         seg_setup(VCPU_SREG_SS);
5577
5578         vmcs_write16(GUEST_TR_SELECTOR, 0);
5579         vmcs_writel(GUEST_TR_BASE, 0);
5580         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5581         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5582
5583         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5584         vmcs_writel(GUEST_LDTR_BASE, 0);
5585         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5586         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5587
5588         if (!init_event) {
5589                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5590                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5591                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5592                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5593         }
5594
5595         vmcs_writel(GUEST_RFLAGS, 0x02);
5596         kvm_rip_write(vcpu, 0xfff0);
5597
5598         vmcs_writel(GUEST_GDTR_BASE, 0);
5599         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5600
5601         vmcs_writel(GUEST_IDTR_BASE, 0);
5602         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5603
5604         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5605         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5606         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5607
5608         setup_msrs(vmx);
5609
5610         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5611
5612         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5613                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5614                 if (cpu_need_tpr_shadow(vcpu))
5615                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5616                                      __pa(vcpu->arch.apic->regs));
5617                 vmcs_write32(TPR_THRESHOLD, 0);
5618         }
5619
5620         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5621
5622         if (kvm_vcpu_apicv_active(vcpu))
5623                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5624
5625         if (vmx->vpid != 0)
5626                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5627
5628         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5629         vmx->vcpu.arch.cr0 = cr0;
5630         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5631         vmx_set_cr4(vcpu, 0);
5632         vmx_set_efer(vcpu, 0);
5633
5634         update_exception_bitmap(vcpu);
5635
5636         vpid_sync_context(vmx->vpid);
5637 }
5638
5639 /*
5640  * In nested virtualization, check if L1 asked to exit on external interrupts.
5641  * For most existing hypervisors, this will always return true.
5642  */
5643 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5644 {
5645         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5646                 PIN_BASED_EXT_INTR_MASK;
5647 }
5648
5649 /*
5650  * In nested virtualization, check if L1 has set
5651  * VM_EXIT_ACK_INTR_ON_EXIT
5652  */
5653 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5654 {
5655         return get_vmcs12(vcpu)->vm_exit_controls &
5656                 VM_EXIT_ACK_INTR_ON_EXIT;
5657 }
5658
5659 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5660 {
5661         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5662                 PIN_BASED_NMI_EXITING;
5663 }
5664
5665 static void enable_irq_window(struct kvm_vcpu *vcpu)
5666 {
5667         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5668                       CPU_BASED_VIRTUAL_INTR_PENDING);
5669 }
5670
5671 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5672 {
5673         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5674                 enable_irq_window(vcpu);
5675                 return;
5676         }
5677
5678         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5679                       CPU_BASED_VIRTUAL_NMI_PENDING);
5680 }
5681
5682 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5683 {
5684         struct vcpu_vmx *vmx = to_vmx(vcpu);
5685         uint32_t intr;
5686         int irq = vcpu->arch.interrupt.nr;
5687
5688         trace_kvm_inj_virq(irq);
5689
5690         ++vcpu->stat.irq_injections;
5691         if (vmx->rmode.vm86_active) {
5692                 int inc_eip = 0;
5693                 if (vcpu->arch.interrupt.soft)
5694                         inc_eip = vcpu->arch.event_exit_inst_len;
5695                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5696                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5697                 return;
5698         }
5699         intr = irq | INTR_INFO_VALID_MASK;
5700         if (vcpu->arch.interrupt.soft) {
5701                 intr |= INTR_TYPE_SOFT_INTR;
5702                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5703                              vmx->vcpu.arch.event_exit_inst_len);
5704         } else
5705                 intr |= INTR_TYPE_EXT_INTR;
5706         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5707 }
5708
5709 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5710 {
5711         struct vcpu_vmx *vmx = to_vmx(vcpu);
5712
5713         ++vcpu->stat.nmi_injections;
5714         vmx->loaded_vmcs->nmi_known_unmasked = false;
5715
5716         if (vmx->rmode.vm86_active) {
5717                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5718                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5719                 return;
5720         }
5721
5722         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5723                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5724 }
5725
5726 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5727 {
5728         struct vcpu_vmx *vmx = to_vmx(vcpu);
5729         bool masked;
5730
5731         if (vmx->loaded_vmcs->nmi_known_unmasked)
5732                 return false;
5733         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5734         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5735         return masked;
5736 }
5737
5738 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5739 {
5740         struct vcpu_vmx *vmx = to_vmx(vcpu);
5741
5742         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5743         if (masked)
5744                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5745                               GUEST_INTR_STATE_NMI);
5746         else
5747                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5748                                 GUEST_INTR_STATE_NMI);
5749 }
5750
5751 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5752 {
5753         if (to_vmx(vcpu)->nested.nested_run_pending)
5754                 return 0;
5755
5756         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5757                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5758                    | GUEST_INTR_STATE_NMI));
5759 }
5760
5761 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5762 {
5763         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5764                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5765                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5766                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5767 }
5768
5769 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5770 {
5771         int ret;
5772
5773         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5774                                     PAGE_SIZE * 3);
5775         if (ret)
5776                 return ret;
5777         kvm->arch.tss_addr = addr;
5778         return init_rmode_tss(kvm);
5779 }
5780
5781 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5782 {
5783         switch (vec) {
5784         case BP_VECTOR:
5785                 /*
5786                  * Update instruction length as we may reinject the exception
5787                  * from user space while in guest debugging mode.
5788                  */
5789                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5790                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5791                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5792                         return false;
5793                 /* fall through */
5794         case DB_VECTOR:
5795                 if (vcpu->guest_debug &
5796                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5797                         return false;
5798                 /* fall through */
5799         case DE_VECTOR:
5800         case OF_VECTOR:
5801         case BR_VECTOR:
5802         case UD_VECTOR:
5803         case DF_VECTOR:
5804         case SS_VECTOR:
5805         case GP_VECTOR:
5806         case MF_VECTOR:
5807                 return true;
5808         break;
5809         }
5810         return false;
5811 }
5812
5813 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5814                                   int vec, u32 err_code)
5815 {
5816         /*
5817          * Instruction with address size override prefix opcode 0x67
5818          * Cause the #SS fault with 0 error code in VM86 mode.
5819          */
5820         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5821                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5822                         if (vcpu->arch.halt_request) {
5823                                 vcpu->arch.halt_request = 0;
5824                                 return kvm_vcpu_halt(vcpu);
5825                         }
5826                         return 1;
5827                 }
5828                 return 0;
5829         }
5830
5831         /*
5832          * Forward all other exceptions that are valid in real mode.
5833          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5834          *        the required debugging infrastructure rework.
5835          */
5836         kvm_queue_exception(vcpu, vec);
5837         return 1;
5838 }
5839
5840 /*
5841  * Trigger machine check on the host. We assume all the MSRs are already set up
5842  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5843  * We pass a fake environment to the machine check handler because we want
5844  * the guest to be always treated like user space, no matter what context
5845  * it used internally.
5846  */
5847 static void kvm_machine_check(void)
5848 {
5849 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5850         struct pt_regs regs = {
5851                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5852                 .flags = X86_EFLAGS_IF,
5853         };
5854
5855         do_machine_check(&regs, 0);
5856 #endif
5857 }
5858
5859 static int handle_machine_check(struct kvm_vcpu *vcpu)
5860 {
5861         /* already handled by vcpu_run */
5862         return 1;
5863 }
5864
5865 static int handle_exception(struct kvm_vcpu *vcpu)
5866 {
5867         struct vcpu_vmx *vmx = to_vmx(vcpu);
5868         struct kvm_run *kvm_run = vcpu->run;
5869         u32 intr_info, ex_no, error_code;
5870         unsigned long cr2, rip, dr6;
5871         u32 vect_info;
5872         enum emulation_result er;
5873
5874         vect_info = vmx->idt_vectoring_info;
5875         intr_info = vmx->exit_intr_info;
5876
5877         if (is_machine_check(intr_info))
5878                 return handle_machine_check(vcpu);
5879
5880         if (is_nmi(intr_info))
5881                 return 1;  /* already handled by vmx_vcpu_run() */
5882
5883         if (is_invalid_opcode(intr_info)) {
5884                 if (is_guest_mode(vcpu)) {
5885                         kvm_queue_exception(vcpu, UD_VECTOR);
5886                         return 1;
5887                 }
5888                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5889                 if (er != EMULATE_DONE)
5890                         kvm_queue_exception(vcpu, UD_VECTOR);
5891                 return 1;
5892         }
5893
5894         error_code = 0;
5895         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5896                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5897
5898         /*
5899          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5900          * MMIO, it is better to report an internal error.
5901          * See the comments in vmx_handle_exit.
5902          */
5903         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5904             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5905                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5906                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5907                 vcpu->run->internal.ndata = 3;
5908                 vcpu->run->internal.data[0] = vect_info;
5909                 vcpu->run->internal.data[1] = intr_info;
5910                 vcpu->run->internal.data[2] = error_code;
5911                 return 0;
5912         }
5913
5914         if (is_page_fault(intr_info)) {
5915                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5916                 /* EPT won't cause page fault directly */
5917                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5918                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
5919                                 true);
5920         }
5921
5922         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5923
5924         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5925                 return handle_rmode_exception(vcpu, ex_no, error_code);
5926
5927         switch (ex_no) {
5928         case AC_VECTOR:
5929                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5930                 return 1;
5931         case DB_VECTOR:
5932                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5933                 if (!(vcpu->guest_debug &
5934                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5935                         vcpu->arch.dr6 &= ~15;
5936                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5937                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5938                                 skip_emulated_instruction(vcpu);
5939
5940                         kvm_queue_exception(vcpu, DB_VECTOR);
5941                         return 1;
5942                 }
5943                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5944                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5945                 /* fall through */
5946         case BP_VECTOR:
5947                 /*
5948                  * Update instruction length as we may reinject #BP from
5949                  * user space while in guest debugging mode. Reading it for
5950                  * #DB as well causes no harm, it is not used in that case.
5951                  */
5952                 vmx->vcpu.arch.event_exit_inst_len =
5953                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5954                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5955                 rip = kvm_rip_read(vcpu);
5956                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5957                 kvm_run->debug.arch.exception = ex_no;
5958                 break;
5959         default:
5960                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5961                 kvm_run->ex.exception = ex_no;
5962                 kvm_run->ex.error_code = error_code;
5963                 break;
5964         }
5965         return 0;
5966 }
5967
5968 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5969 {
5970         ++vcpu->stat.irq_exits;
5971         return 1;
5972 }
5973
5974 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5975 {
5976         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5977         vcpu->mmio_needed = 0;
5978         return 0;
5979 }
5980
5981 static int handle_io(struct kvm_vcpu *vcpu)
5982 {
5983         unsigned long exit_qualification;
5984         int size, in, string, ret;
5985         unsigned port;
5986
5987         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5988         string = (exit_qualification & 16) != 0;
5989         in = (exit_qualification & 8) != 0;
5990
5991         ++vcpu->stat.io_exits;
5992
5993         if (string || in)
5994                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5995
5996         port = exit_qualification >> 16;
5997         size = (exit_qualification & 7) + 1;
5998
5999         ret = kvm_skip_emulated_instruction(vcpu);
6000
6001         /*
6002          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6003          * KVM_EXIT_DEBUG here.
6004          */
6005         return kvm_fast_pio_out(vcpu, size, port) && ret;
6006 }
6007
6008 static void
6009 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6010 {
6011         /*
6012          * Patch in the VMCALL instruction:
6013          */
6014         hypercall[0] = 0x0f;
6015         hypercall[1] = 0x01;
6016         hypercall[2] = 0xc1;
6017 }
6018
6019 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6020 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6021 {
6022         if (is_guest_mode(vcpu)) {
6023                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6024                 unsigned long orig_val = val;
6025
6026                 /*
6027                  * We get here when L2 changed cr0 in a way that did not change
6028                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6029                  * but did change L0 shadowed bits. So we first calculate the
6030                  * effective cr0 value that L1 would like to write into the
6031                  * hardware. It consists of the L2-owned bits from the new
6032                  * value combined with the L1-owned bits from L1's guest_cr0.
6033                  */
6034                 val = (val & ~vmcs12->cr0_guest_host_mask) |
6035                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6036
6037                 if (!nested_guest_cr0_valid(vcpu, val))
6038                         return 1;
6039
6040                 if (kvm_set_cr0(vcpu, val))
6041                         return 1;
6042                 vmcs_writel(CR0_READ_SHADOW, orig_val);
6043                 return 0;
6044         } else {
6045                 if (to_vmx(vcpu)->nested.vmxon &&
6046                     !nested_host_cr0_valid(vcpu, val))
6047                         return 1;
6048
6049                 return kvm_set_cr0(vcpu, val);
6050         }
6051 }
6052
6053 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6054 {
6055         if (is_guest_mode(vcpu)) {
6056                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6057                 unsigned long orig_val = val;
6058
6059                 /* analogously to handle_set_cr0 */
6060                 val = (val & ~vmcs12->cr4_guest_host_mask) |
6061                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6062                 if (kvm_set_cr4(vcpu, val))
6063                         return 1;
6064                 vmcs_writel(CR4_READ_SHADOW, orig_val);
6065                 return 0;
6066         } else
6067                 return kvm_set_cr4(vcpu, val);
6068 }
6069
6070 static int handle_cr(struct kvm_vcpu *vcpu)
6071 {
6072         unsigned long exit_qualification, val;
6073         int cr;
6074         int reg;
6075         int err;
6076         int ret;
6077
6078         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6079         cr = exit_qualification & 15;
6080         reg = (exit_qualification >> 8) & 15;
6081         switch ((exit_qualification >> 4) & 3) {
6082         case 0: /* mov to cr */
6083                 val = kvm_register_readl(vcpu, reg);
6084                 trace_kvm_cr_write(cr, val);
6085                 switch (cr) {
6086                 case 0:
6087                         err = handle_set_cr0(vcpu, val);
6088                         return kvm_complete_insn_gp(vcpu, err);
6089                 case 3:
6090                         err = kvm_set_cr3(vcpu, val);
6091                         return kvm_complete_insn_gp(vcpu, err);
6092                 case 4:
6093                         err = handle_set_cr4(vcpu, val);
6094                         return kvm_complete_insn_gp(vcpu, err);
6095                 case 8: {
6096                                 u8 cr8_prev = kvm_get_cr8(vcpu);
6097                                 u8 cr8 = (u8)val;
6098                                 err = kvm_set_cr8(vcpu, cr8);
6099                                 ret = kvm_complete_insn_gp(vcpu, err);
6100                                 if (lapic_in_kernel(vcpu))
6101                                         return ret;
6102                                 if (cr8_prev <= cr8)
6103                                         return ret;
6104                                 /*
6105                                  * TODO: we might be squashing a
6106                                  * KVM_GUESTDBG_SINGLESTEP-triggered
6107                                  * KVM_EXIT_DEBUG here.
6108                                  */
6109                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6110                                 return 0;
6111                         }
6112                 }
6113                 break;
6114         case 2: /* clts */
6115                 WARN_ONCE(1, "Guest should always own CR0.TS");
6116                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6117                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6118                 return kvm_skip_emulated_instruction(vcpu);
6119         case 1: /*mov from cr*/
6120                 switch (cr) {
6121                 case 3:
6122                         val = kvm_read_cr3(vcpu);
6123                         kvm_register_write(vcpu, reg, val);
6124                         trace_kvm_cr_read(cr, val);
6125                         return kvm_skip_emulated_instruction(vcpu);
6126                 case 8:
6127                         val = kvm_get_cr8(vcpu);
6128                         kvm_register_write(vcpu, reg, val);
6129                         trace_kvm_cr_read(cr, val);
6130                         return kvm_skip_emulated_instruction(vcpu);
6131                 }
6132                 break;
6133         case 3: /* lmsw */
6134                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6135                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6136                 kvm_lmsw(vcpu, val);
6137
6138                 return kvm_skip_emulated_instruction(vcpu);
6139         default:
6140                 break;
6141         }
6142         vcpu->run->exit_reason = 0;
6143         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6144                (int)(exit_qualification >> 4) & 3, cr);
6145         return 0;
6146 }
6147
6148 static int handle_dr(struct kvm_vcpu *vcpu)
6149 {
6150         unsigned long exit_qualification;
6151         int dr, dr7, reg;
6152
6153         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6154         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6155
6156         /* First, if DR does not exist, trigger UD */
6157         if (!kvm_require_dr(vcpu, dr))
6158                 return 1;
6159
6160         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6161         if (!kvm_require_cpl(vcpu, 0))
6162                 return 1;
6163         dr7 = vmcs_readl(GUEST_DR7);
6164         if (dr7 & DR7_GD) {
6165                 /*
6166                  * As the vm-exit takes precedence over the debug trap, we
6167                  * need to emulate the latter, either for the host or the
6168                  * guest debugging itself.
6169                  */
6170                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6171                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6172                         vcpu->run->debug.arch.dr7 = dr7;
6173                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6174                         vcpu->run->debug.arch.exception = DB_VECTOR;
6175                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6176                         return 0;
6177                 } else {
6178                         vcpu->arch.dr6 &= ~15;
6179                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6180                         kvm_queue_exception(vcpu, DB_VECTOR);
6181                         return 1;
6182                 }
6183         }
6184
6185         if (vcpu->guest_debug == 0) {
6186                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6187                                 CPU_BASED_MOV_DR_EXITING);
6188
6189                 /*
6190                  * No more DR vmexits; force a reload of the debug registers
6191                  * and reenter on this instruction.  The next vmexit will
6192                  * retrieve the full state of the debug registers.
6193                  */
6194                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6195                 return 1;
6196         }
6197
6198         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6199         if (exit_qualification & TYPE_MOV_FROM_DR) {
6200                 unsigned long val;
6201
6202                 if (kvm_get_dr(vcpu, dr, &val))
6203                         return 1;
6204                 kvm_register_write(vcpu, reg, val);
6205         } else
6206                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6207                         return 1;
6208
6209         return kvm_skip_emulated_instruction(vcpu);
6210 }
6211
6212 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6213 {
6214         return vcpu->arch.dr6;
6215 }
6216
6217 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6218 {
6219 }
6220
6221 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6222 {
6223         get_debugreg(vcpu->arch.db[0], 0);
6224         get_debugreg(vcpu->arch.db[1], 1);
6225         get_debugreg(vcpu->arch.db[2], 2);
6226         get_debugreg(vcpu->arch.db[3], 3);
6227         get_debugreg(vcpu->arch.dr6, 6);
6228         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6229
6230         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6231         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6232 }
6233
6234 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6235 {
6236         vmcs_writel(GUEST_DR7, val);
6237 }
6238
6239 static int handle_cpuid(struct kvm_vcpu *vcpu)
6240 {
6241         return kvm_emulate_cpuid(vcpu);
6242 }
6243
6244 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6245 {
6246         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6247         struct msr_data msr_info;
6248
6249         msr_info.index = ecx;
6250         msr_info.host_initiated = false;
6251         if (vmx_get_msr(vcpu, &msr_info)) {
6252                 trace_kvm_msr_read_ex(ecx);
6253                 kvm_inject_gp(vcpu, 0);
6254                 return 1;
6255         }
6256
6257         trace_kvm_msr_read(ecx, msr_info.data);
6258
6259         /* FIXME: handling of bits 32:63 of rax, rdx */
6260         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6261         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6262         return kvm_skip_emulated_instruction(vcpu);
6263 }
6264
6265 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6266 {
6267         struct msr_data msr;
6268         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6269         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6270                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6271
6272         msr.data = data;
6273         msr.index = ecx;
6274         msr.host_initiated = false;
6275         if (kvm_set_msr(vcpu, &msr) != 0) {
6276                 trace_kvm_msr_write_ex(ecx, data);
6277                 kvm_inject_gp(vcpu, 0);
6278                 return 1;
6279         }
6280
6281         trace_kvm_msr_write(ecx, data);
6282         return kvm_skip_emulated_instruction(vcpu);
6283 }
6284
6285 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6286 {
6287         kvm_apic_update_ppr(vcpu);
6288         return 1;
6289 }
6290
6291 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6292 {
6293         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6294                         CPU_BASED_VIRTUAL_INTR_PENDING);
6295
6296         kvm_make_request(KVM_REQ_EVENT, vcpu);
6297
6298         ++vcpu->stat.irq_window_exits;
6299         return 1;
6300 }
6301
6302 static int handle_halt(struct kvm_vcpu *vcpu)
6303 {
6304         return kvm_emulate_halt(vcpu);
6305 }
6306
6307 static int handle_vmcall(struct kvm_vcpu *vcpu)
6308 {
6309         return kvm_emulate_hypercall(vcpu);
6310 }
6311
6312 static int handle_invd(struct kvm_vcpu *vcpu)
6313 {
6314         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6315 }
6316
6317 static int handle_invlpg(struct kvm_vcpu *vcpu)
6318 {
6319         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6320
6321         kvm_mmu_invlpg(vcpu, exit_qualification);
6322         return kvm_skip_emulated_instruction(vcpu);
6323 }
6324
6325 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6326 {
6327         int err;
6328
6329         err = kvm_rdpmc(vcpu);
6330         return kvm_complete_insn_gp(vcpu, err);
6331 }
6332
6333 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6334 {
6335         return kvm_emulate_wbinvd(vcpu);
6336 }
6337
6338 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6339 {
6340         u64 new_bv = kvm_read_edx_eax(vcpu);
6341         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6342
6343         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6344                 return kvm_skip_emulated_instruction(vcpu);
6345         return 1;
6346 }
6347
6348 static int handle_xsaves(struct kvm_vcpu *vcpu)
6349 {
6350         kvm_skip_emulated_instruction(vcpu);
6351         WARN(1, "this should never happen\n");
6352         return 1;
6353 }
6354
6355 static int handle_xrstors(struct kvm_vcpu *vcpu)
6356 {
6357         kvm_skip_emulated_instruction(vcpu);
6358         WARN(1, "this should never happen\n");
6359         return 1;
6360 }
6361
6362 static int handle_apic_access(struct kvm_vcpu *vcpu)
6363 {
6364         if (likely(fasteoi)) {
6365                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6366                 int access_type, offset;
6367
6368                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6369                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6370                 /*
6371                  * Sane guest uses MOV to write EOI, with written value
6372                  * not cared. So make a short-circuit here by avoiding
6373                  * heavy instruction emulation.
6374                  */
6375                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6376                     (offset == APIC_EOI)) {
6377                         kvm_lapic_set_eoi(vcpu);
6378                         return kvm_skip_emulated_instruction(vcpu);
6379                 }
6380         }
6381         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6382 }
6383
6384 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6385 {
6386         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6387         int vector = exit_qualification & 0xff;
6388
6389         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6390         kvm_apic_set_eoi_accelerated(vcpu, vector);
6391         return 1;
6392 }
6393
6394 static int handle_apic_write(struct kvm_vcpu *vcpu)
6395 {
6396         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6397         u32 offset = exit_qualification & 0xfff;
6398
6399         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6400         kvm_apic_write_nodecode(vcpu, offset);
6401         return 1;
6402 }
6403
6404 static int handle_task_switch(struct kvm_vcpu *vcpu)
6405 {
6406         struct vcpu_vmx *vmx = to_vmx(vcpu);
6407         unsigned long exit_qualification;
6408         bool has_error_code = false;
6409         u32 error_code = 0;
6410         u16 tss_selector;
6411         int reason, type, idt_v, idt_index;
6412
6413         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6414         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6415         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6416
6417         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6418
6419         reason = (u32)exit_qualification >> 30;
6420         if (reason == TASK_SWITCH_GATE && idt_v) {
6421                 switch (type) {
6422                 case INTR_TYPE_NMI_INTR:
6423                         vcpu->arch.nmi_injected = false;
6424                         vmx_set_nmi_mask(vcpu, true);
6425                         break;
6426                 case INTR_TYPE_EXT_INTR:
6427                 case INTR_TYPE_SOFT_INTR:
6428                         kvm_clear_interrupt_queue(vcpu);
6429                         break;
6430                 case INTR_TYPE_HARD_EXCEPTION:
6431                         if (vmx->idt_vectoring_info &
6432                             VECTORING_INFO_DELIVER_CODE_MASK) {
6433                                 has_error_code = true;
6434                                 error_code =
6435                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6436                         }
6437                         /* fall through */
6438                 case INTR_TYPE_SOFT_EXCEPTION:
6439                         kvm_clear_exception_queue(vcpu);
6440                         break;
6441                 default:
6442                         break;
6443                 }
6444         }
6445         tss_selector = exit_qualification;
6446
6447         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6448                        type != INTR_TYPE_EXT_INTR &&
6449                        type != INTR_TYPE_NMI_INTR))
6450                 skip_emulated_instruction(vcpu);
6451
6452         if (kvm_task_switch(vcpu, tss_selector,
6453                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6454                             has_error_code, error_code) == EMULATE_FAIL) {
6455                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6456                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6457                 vcpu->run->internal.ndata = 0;
6458                 return 0;
6459         }
6460
6461         /*
6462          * TODO: What about debug traps on tss switch?
6463          *       Are we supposed to inject them and update dr6?
6464          */
6465
6466         return 1;
6467 }
6468
6469 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6470 {
6471         unsigned long exit_qualification;
6472         gpa_t gpa;
6473         u64 error_code;
6474
6475         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6476
6477         /*
6478          * EPT violation happened while executing iret from NMI,
6479          * "blocked by NMI" bit has to be set before next VM entry.
6480          * There are errata that may cause this bit to not be set:
6481          * AAK134, BY25.
6482          */
6483         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6484                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6485                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6486
6487         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6488         trace_kvm_page_fault(gpa, exit_qualification);
6489
6490         /* Is it a read fault? */
6491         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6492                      ? PFERR_USER_MASK : 0;
6493         /* Is it a write fault? */
6494         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6495                       ? PFERR_WRITE_MASK : 0;
6496         /* Is it a fetch fault? */
6497         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6498                       ? PFERR_FETCH_MASK : 0;
6499         /* ept page table entry is present? */
6500         error_code |= (exit_qualification &
6501                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6502                         EPT_VIOLATION_EXECUTABLE))
6503                       ? PFERR_PRESENT_MASK : 0;
6504
6505         error_code |= (exit_qualification & 0x100) != 0 ?
6506                PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
6507
6508         vcpu->arch.exit_qualification = exit_qualification;
6509         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6510 }
6511
6512 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6513 {
6514         int ret;
6515         gpa_t gpa;
6516
6517         /*
6518          * A nested guest cannot optimize MMIO vmexits, because we have an
6519          * nGPA here instead of the required GPA.
6520          */
6521         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6522         if (!is_guest_mode(vcpu) &&
6523             !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6524                 trace_kvm_fast_mmio(gpa);
6525                 return kvm_skip_emulated_instruction(vcpu);
6526         }
6527
6528         ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
6529         if (ret >= 0)
6530                 return ret;
6531
6532         /* It is the real ept misconfig */
6533         WARN_ON(1);
6534
6535         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6536         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6537
6538         return 0;
6539 }
6540
6541 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6542 {
6543         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6544                         CPU_BASED_VIRTUAL_NMI_PENDING);
6545         ++vcpu->stat.nmi_window_exits;
6546         kvm_make_request(KVM_REQ_EVENT, vcpu);
6547
6548         return 1;
6549 }
6550
6551 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6552 {
6553         struct vcpu_vmx *vmx = to_vmx(vcpu);
6554         enum emulation_result err = EMULATE_DONE;
6555         int ret = 1;
6556         u32 cpu_exec_ctrl;
6557         bool intr_window_requested;
6558         unsigned count = 130;
6559
6560         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6561         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6562
6563         while (vmx->emulation_required && count-- != 0) {
6564                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6565                         return handle_interrupt_window(&vmx->vcpu);
6566
6567                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6568                         return 1;
6569
6570                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6571
6572                 if (err == EMULATE_USER_EXIT) {
6573                         ++vcpu->stat.mmio_exits;
6574                         ret = 0;
6575                         goto out;
6576                 }
6577
6578                 if (err != EMULATE_DONE) {
6579                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6580                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6581                         vcpu->run->internal.ndata = 0;
6582                         return 0;
6583                 }
6584
6585                 if (vcpu->arch.halt_request) {
6586                         vcpu->arch.halt_request = 0;
6587                         ret = kvm_vcpu_halt(vcpu);
6588                         goto out;
6589                 }
6590
6591                 if (signal_pending(current))
6592                         goto out;
6593                 if (need_resched())
6594                         schedule();
6595         }
6596
6597 out:
6598         return ret;
6599 }
6600
6601 static int __grow_ple_window(int val)
6602 {
6603         if (ple_window_grow < 1)
6604                 return ple_window;
6605
6606         val = min(val, ple_window_actual_max);
6607
6608         if (ple_window_grow < ple_window)
6609                 val *= ple_window_grow;
6610         else
6611                 val += ple_window_grow;
6612
6613         return val;
6614 }
6615
6616 static int __shrink_ple_window(int val, int modifier, int minimum)
6617 {
6618         if (modifier < 1)
6619                 return ple_window;
6620
6621         if (modifier < ple_window)
6622                 val /= modifier;
6623         else
6624                 val -= modifier;
6625
6626         return max(val, minimum);
6627 }
6628
6629 static void grow_ple_window(struct kvm_vcpu *vcpu)
6630 {
6631         struct vcpu_vmx *vmx = to_vmx(vcpu);
6632         int old = vmx->ple_window;
6633
6634         vmx->ple_window = __grow_ple_window(old);
6635
6636         if (vmx->ple_window != old)
6637                 vmx->ple_window_dirty = true;
6638
6639         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6640 }
6641
6642 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6643 {
6644         struct vcpu_vmx *vmx = to_vmx(vcpu);
6645         int old = vmx->ple_window;
6646
6647         vmx->ple_window = __shrink_ple_window(old,
6648                                               ple_window_shrink, ple_window);
6649
6650         if (vmx->ple_window != old)
6651                 vmx->ple_window_dirty = true;
6652
6653         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6654 }
6655
6656 /*
6657  * ple_window_actual_max is computed to be one grow_ple_window() below
6658  * ple_window_max. (See __grow_ple_window for the reason.)
6659  * This prevents overflows, because ple_window_max is int.
6660  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6661  * this process.
6662  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6663  */
6664 static void update_ple_window_actual_max(void)
6665 {
6666         ple_window_actual_max =
6667                         __shrink_ple_window(max(ple_window_max, ple_window),
6668                                             ple_window_grow, INT_MIN);
6669 }
6670
6671 /*
6672  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6673  */
6674 static void wakeup_handler(void)
6675 {
6676         struct kvm_vcpu *vcpu;
6677         int cpu = smp_processor_id();
6678
6679         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6680         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6681                         blocked_vcpu_list) {
6682                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6683
6684                 if (pi_test_on(pi_desc) == 1)
6685                         kvm_vcpu_kick(vcpu);
6686         }
6687         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6688 }
6689
6690 void vmx_enable_tdp(void)
6691 {
6692         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6693                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6694                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6695                 0ull, VMX_EPT_EXECUTABLE_MASK,
6696                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6697                 VMX_EPT_RWX_MASK, 0ull);
6698
6699         ept_set_mmio_spte_mask();
6700         kvm_enable_tdp();
6701 }
6702
6703 static __init int hardware_setup(void)
6704 {
6705         int r = -ENOMEM, i, msr;
6706
6707         rdmsrl_safe(MSR_EFER, &host_efer);
6708
6709         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6710                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6711
6712         for (i = 0; i < VMX_BITMAP_NR; i++) {
6713                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6714                 if (!vmx_bitmap[i])
6715                         goto out;
6716         }
6717
6718         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6719         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6720         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6721
6722         /*
6723          * Allow direct access to the PC debug port (it is often used for I/O
6724          * delays, but the vmexits simply slow things down).
6725          */
6726         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6727         clear_bit(0x80, vmx_io_bitmap_a);
6728
6729         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6730
6731         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6732         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6733
6734         if (setup_vmcs_config(&vmcs_config) < 0) {
6735                 r = -EIO;
6736                 goto out;
6737         }
6738
6739         if (boot_cpu_has(X86_FEATURE_NX))
6740                 kvm_enable_efer_bits(EFER_NX);
6741
6742         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6743                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6744                 enable_vpid = 0;
6745
6746         if (!cpu_has_vmx_shadow_vmcs())
6747                 enable_shadow_vmcs = 0;
6748         if (enable_shadow_vmcs)
6749                 init_vmcs_shadow_fields();
6750
6751         if (!cpu_has_vmx_ept() ||
6752             !cpu_has_vmx_ept_4levels() ||
6753             !cpu_has_vmx_ept_mt_wb()) {
6754                 enable_ept = 0;
6755                 enable_unrestricted_guest = 0;
6756                 enable_ept_ad_bits = 0;
6757         }
6758
6759         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6760                 enable_ept_ad_bits = 0;
6761
6762         if (!cpu_has_vmx_unrestricted_guest())
6763                 enable_unrestricted_guest = 0;
6764
6765         if (!cpu_has_vmx_flexpriority())
6766                 flexpriority_enabled = 0;
6767
6768         /*
6769          * set_apic_access_page_addr() is used to reload apic access
6770          * page upon invalidation.  No need to do anything if not
6771          * using the APIC_ACCESS_ADDR VMCS field.
6772          */
6773         if (!flexpriority_enabled)
6774                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6775
6776         if (!cpu_has_vmx_tpr_shadow())
6777                 kvm_x86_ops->update_cr8_intercept = NULL;
6778
6779         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6780                 kvm_disable_largepages();
6781
6782         if (!cpu_has_vmx_ple())
6783                 ple_gap = 0;
6784
6785         if (!cpu_has_vmx_apicv()) {
6786                 enable_apicv = 0;
6787                 kvm_x86_ops->sync_pir_to_irr = NULL;
6788         }
6789
6790         if (cpu_has_vmx_tsc_scaling()) {
6791                 kvm_has_tsc_control = true;
6792                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6793                 kvm_tsc_scaling_ratio_frac_bits = 48;
6794         }
6795
6796         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6797         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6798         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6799         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6800         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6801         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6802
6803         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6804                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6805         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6806                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6807         memcpy(vmx_msr_bitmap_legacy_x2apic,
6808                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6809         memcpy(vmx_msr_bitmap_longmode_x2apic,
6810                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6811
6812         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6813
6814         for (msr = 0x800; msr <= 0x8ff; msr++) {
6815                 if (msr == 0x839 /* TMCCT */)
6816                         continue;
6817                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6818         }
6819
6820         /*
6821          * TPR reads and writes can be virtualized even if virtual interrupt
6822          * delivery is not in use.
6823          */
6824         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6825         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6826
6827         /* EOI */
6828         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6829         /* SELF-IPI */
6830         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6831
6832         if (enable_ept)
6833                 vmx_enable_tdp();
6834         else
6835                 kvm_disable_tdp();
6836
6837         update_ple_window_actual_max();
6838
6839         /*
6840          * Only enable PML when hardware supports PML feature, and both EPT
6841          * and EPT A/D bit features are enabled -- PML depends on them to work.
6842          */
6843         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6844                 enable_pml = 0;
6845
6846         if (!enable_pml) {
6847                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6848                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6849                 kvm_x86_ops->flush_log_dirty = NULL;
6850                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6851         }
6852
6853         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6854                 u64 vmx_msr;
6855
6856                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6857                 cpu_preemption_timer_multi =
6858                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6859         } else {
6860                 kvm_x86_ops->set_hv_timer = NULL;
6861                 kvm_x86_ops->cancel_hv_timer = NULL;
6862         }
6863
6864         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6865
6866         kvm_mce_cap_supported |= MCG_LMCE_P;
6867
6868         return alloc_kvm_area();
6869
6870 out:
6871         for (i = 0; i < VMX_BITMAP_NR; i++)
6872                 free_page((unsigned long)vmx_bitmap[i]);
6873
6874     return r;
6875 }
6876
6877 static __exit void hardware_unsetup(void)
6878 {
6879         int i;
6880
6881         for (i = 0; i < VMX_BITMAP_NR; i++)
6882                 free_page((unsigned long)vmx_bitmap[i]);
6883
6884         free_kvm_area();
6885 }
6886
6887 /*
6888  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6889  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6890  */
6891 static int handle_pause(struct kvm_vcpu *vcpu)
6892 {
6893         if (ple_gap)
6894                 grow_ple_window(vcpu);
6895
6896         /*
6897          * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6898          * VM-execution control is ignored if CPL > 0. OTOH, KVM
6899          * never set PAUSE_EXITING and just set PLE if supported,
6900          * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6901          */
6902         kvm_vcpu_on_spin(vcpu, true);
6903         return kvm_skip_emulated_instruction(vcpu);
6904 }
6905
6906 static int handle_nop(struct kvm_vcpu *vcpu)
6907 {
6908         return kvm_skip_emulated_instruction(vcpu);
6909 }
6910
6911 static int handle_mwait(struct kvm_vcpu *vcpu)
6912 {
6913         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6914         return handle_nop(vcpu);
6915 }
6916
6917 static int handle_invalid_op(struct kvm_vcpu *vcpu)
6918 {
6919         kvm_queue_exception(vcpu, UD_VECTOR);
6920         return 1;
6921 }
6922
6923 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6924 {
6925         return 1;
6926 }
6927
6928 static int handle_monitor(struct kvm_vcpu *vcpu)
6929 {
6930         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6931         return handle_nop(vcpu);
6932 }
6933
6934 /*
6935  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6936  * We could reuse a single VMCS for all the L2 guests, but we also want the
6937  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6938  * allows keeping them loaded on the processor, and in the future will allow
6939  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6940  * every entry if they never change.
6941  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6942  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6943  *
6944  * The following functions allocate and free a vmcs02 in this pool.
6945  */
6946
6947 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6948 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6949 {
6950         struct vmcs02_list *item;
6951         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6952                 if (item->vmptr == vmx->nested.current_vmptr) {
6953                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6954                         return &item->vmcs02;
6955                 }
6956
6957         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6958                 /* Recycle the least recently used VMCS. */
6959                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6960                                        struct vmcs02_list, list);
6961                 item->vmptr = vmx->nested.current_vmptr;
6962                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6963                 return &item->vmcs02;
6964         }
6965
6966         /* Create a new VMCS */
6967         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6968         if (!item)
6969                 return NULL;
6970         item->vmcs02.vmcs = alloc_vmcs();
6971         item->vmcs02.shadow_vmcs = NULL;
6972         if (!item->vmcs02.vmcs) {
6973                 kfree(item);
6974                 return NULL;
6975         }
6976         loaded_vmcs_init(&item->vmcs02);
6977         item->vmptr = vmx->nested.current_vmptr;
6978         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6979         vmx->nested.vmcs02_num++;
6980         return &item->vmcs02;
6981 }
6982
6983 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6984 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6985 {
6986         struct vmcs02_list *item;
6987         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6988                 if (item->vmptr == vmptr) {
6989                         free_loaded_vmcs(&item->vmcs02);
6990                         list_del(&item->list);
6991                         kfree(item);
6992                         vmx->nested.vmcs02_num--;
6993                         return;
6994                 }
6995 }
6996
6997 /*
6998  * Free all VMCSs saved for this vcpu, except the one pointed by
6999  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
7000  * must be &vmx->vmcs01.
7001  */
7002 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
7003 {
7004         struct vmcs02_list *item, *n;
7005
7006         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
7007         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
7008                 /*
7009                  * Something will leak if the above WARN triggers.  Better than
7010                  * a use-after-free.
7011                  */
7012                 if (vmx->loaded_vmcs == &item->vmcs02)
7013                         continue;
7014
7015                 free_loaded_vmcs(&item->vmcs02);
7016                 list_del(&item->list);
7017                 kfree(item);
7018                 vmx->nested.vmcs02_num--;
7019         }
7020 }
7021
7022 /*
7023  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7024  * set the success or error code of an emulated VMX instruction, as specified
7025  * by Vol 2B, VMX Instruction Reference, "Conventions".
7026  */
7027 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7028 {
7029         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7030                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7031                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7032 }
7033
7034 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7035 {
7036         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7037                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7038                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7039                         | X86_EFLAGS_CF);
7040 }
7041
7042 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7043                                         u32 vm_instruction_error)
7044 {
7045         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7046                 /*
7047                  * failValid writes the error number to the current VMCS, which
7048                  * can't be done there isn't a current VMCS.
7049                  */
7050                 nested_vmx_failInvalid(vcpu);
7051                 return;
7052         }
7053         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7054                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7055                             X86_EFLAGS_SF | X86_EFLAGS_OF))
7056                         | X86_EFLAGS_ZF);
7057         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7058         /*
7059          * We don't need to force a shadow sync because
7060          * VM_INSTRUCTION_ERROR is not shadowed
7061          */
7062 }
7063
7064 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7065 {
7066         /* TODO: not to reset guest simply here. */
7067         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7068         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7069 }
7070
7071 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7072 {
7073         struct vcpu_vmx *vmx =
7074                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7075
7076         vmx->nested.preemption_timer_expired = true;
7077         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7078         kvm_vcpu_kick(&vmx->vcpu);
7079
7080         return HRTIMER_NORESTART;
7081 }
7082
7083 /*
7084  * Decode the memory-address operand of a vmx instruction, as recorded on an
7085  * exit caused by such an instruction (run by a guest hypervisor).
7086  * On success, returns 0. When the operand is invalid, returns 1 and throws
7087  * #UD or #GP.
7088  */
7089 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7090                                  unsigned long exit_qualification,
7091                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
7092 {
7093         gva_t off;
7094         bool exn;
7095         struct kvm_segment s;
7096
7097         /*
7098          * According to Vol. 3B, "Information for VM Exits Due to Instruction
7099          * Execution", on an exit, vmx_instruction_info holds most of the
7100          * addressing components of the operand. Only the displacement part
7101          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7102          * For how an actual address is calculated from all these components,
7103          * refer to Vol. 1, "Operand Addressing".
7104          */
7105         int  scaling = vmx_instruction_info & 3;
7106         int  addr_size = (vmx_instruction_info >> 7) & 7;
7107         bool is_reg = vmx_instruction_info & (1u << 10);
7108         int  seg_reg = (vmx_instruction_info >> 15) & 7;
7109         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
7110         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7111         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
7112         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
7113
7114         if (is_reg) {
7115                 kvm_queue_exception(vcpu, UD_VECTOR);
7116                 return 1;
7117         }
7118
7119         /* Addr = segment_base + offset */
7120         /* offset = base + [index * scale] + displacement */
7121         off = exit_qualification; /* holds the displacement */
7122         if (base_is_valid)
7123                 off += kvm_register_read(vcpu, base_reg);
7124         if (index_is_valid)
7125                 off += kvm_register_read(vcpu, index_reg)<<scaling;
7126         vmx_get_segment(vcpu, &s, seg_reg);
7127         *ret = s.base + off;
7128
7129         if (addr_size == 1) /* 32 bit */
7130                 *ret &= 0xffffffff;
7131
7132         /* Checks for #GP/#SS exceptions. */
7133         exn = false;
7134         if (is_long_mode(vcpu)) {
7135                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7136                  * non-canonical form. This is the only check on the memory
7137                  * destination for long mode!
7138                  */
7139                 exn = is_noncanonical_address(*ret, vcpu);
7140         } else if (is_protmode(vcpu)) {
7141                 /* Protected mode: apply checks for segment validity in the
7142                  * following order:
7143                  * - segment type check (#GP(0) may be thrown)
7144                  * - usability check (#GP(0)/#SS(0))
7145                  * - limit check (#GP(0)/#SS(0))
7146                  */
7147                 if (wr)
7148                         /* #GP(0) if the destination operand is located in a
7149                          * read-only data segment or any code segment.
7150                          */
7151                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
7152                 else
7153                         /* #GP(0) if the source operand is located in an
7154                          * execute-only code segment
7155                          */
7156                         exn = ((s.type & 0xa) == 8);
7157                 if (exn) {
7158                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7159                         return 1;
7160                 }
7161                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7162                  */
7163                 exn = (s.unusable != 0);
7164                 /* Protected mode: #GP(0)/#SS(0) if the memory
7165                  * operand is outside the segment limit.
7166                  */
7167                 exn = exn || (off + sizeof(u64) > s.limit);
7168         }
7169         if (exn) {
7170                 kvm_queue_exception_e(vcpu,
7171                                       seg_reg == VCPU_SREG_SS ?
7172                                                 SS_VECTOR : GP_VECTOR,
7173                                       0);
7174                 return 1;
7175         }
7176
7177         return 0;
7178 }
7179
7180 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7181 {
7182         gva_t gva;
7183         struct x86_exception e;
7184
7185         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7186                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7187                 return 1;
7188
7189         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7190                                 sizeof(*vmpointer), &e)) {
7191                 kvm_inject_page_fault(vcpu, &e);
7192                 return 1;
7193         }
7194
7195         return 0;
7196 }
7197
7198 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7199 {
7200         struct vcpu_vmx *vmx = to_vmx(vcpu);
7201         struct vmcs *shadow_vmcs;
7202
7203         if (cpu_has_vmx_msr_bitmap()) {
7204                 vmx->nested.msr_bitmap =
7205                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7206                 if (!vmx->nested.msr_bitmap)
7207                         goto out_msr_bitmap;
7208         }
7209
7210         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7211         if (!vmx->nested.cached_vmcs12)
7212                 goto out_cached_vmcs12;
7213
7214         if (enable_shadow_vmcs) {
7215                 shadow_vmcs = alloc_vmcs();
7216                 if (!shadow_vmcs)
7217                         goto out_shadow_vmcs;
7218                 /* mark vmcs as shadow */
7219                 shadow_vmcs->revision_id |= (1u << 31);
7220                 /* init shadow vmcs */
7221                 vmcs_clear(shadow_vmcs);
7222                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7223         }
7224
7225         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7226         vmx->nested.vmcs02_num = 0;
7227
7228         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7229                      HRTIMER_MODE_REL_PINNED);
7230         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7231
7232         vmx->nested.vmxon = true;
7233         return 0;
7234
7235 out_shadow_vmcs:
7236         kfree(vmx->nested.cached_vmcs12);
7237
7238 out_cached_vmcs12:
7239         free_page((unsigned long)vmx->nested.msr_bitmap);
7240
7241 out_msr_bitmap:
7242         return -ENOMEM;
7243 }
7244
7245 /*
7246  * Emulate the VMXON instruction.
7247  * Currently, we just remember that VMX is active, and do not save or even
7248  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7249  * do not currently need to store anything in that guest-allocated memory
7250  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7251  * argument is different from the VMXON pointer (which the spec says they do).
7252  */
7253 static int handle_vmon(struct kvm_vcpu *vcpu)
7254 {
7255         int ret;
7256         gpa_t vmptr;
7257         struct page *page;
7258         struct vcpu_vmx *vmx = to_vmx(vcpu);
7259         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7260                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7261
7262         /*
7263          * The Intel VMX Instruction Reference lists a bunch of bits that are
7264          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7265          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7266          * Otherwise, we should fail with #UD.  But most faulting conditions
7267          * have already been checked by hardware, prior to the VM-exit for
7268          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7269          * that bit set to 1 in non-root mode.
7270          */
7271         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7272                 kvm_queue_exception(vcpu, UD_VECTOR);
7273                 return 1;
7274         }
7275
7276         if (vmx->nested.vmxon) {
7277                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7278                 return kvm_skip_emulated_instruction(vcpu);
7279         }
7280
7281         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7282                         != VMXON_NEEDED_FEATURES) {
7283                 kvm_inject_gp(vcpu, 0);
7284                 return 1;
7285         }
7286
7287         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7288                 return 1;
7289
7290         /*
7291          * SDM 3: 24.11.5
7292          * The first 4 bytes of VMXON region contain the supported
7293          * VMCS revision identifier
7294          *
7295          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7296          * which replaces physical address width with 32
7297          */
7298         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7299                 nested_vmx_failInvalid(vcpu);
7300                 return kvm_skip_emulated_instruction(vcpu);
7301         }
7302
7303         page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7304         if (is_error_page(page)) {
7305                 nested_vmx_failInvalid(vcpu);
7306                 return kvm_skip_emulated_instruction(vcpu);
7307         }
7308         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7309                 kunmap(page);
7310                 kvm_release_page_clean(page);
7311                 nested_vmx_failInvalid(vcpu);
7312                 return kvm_skip_emulated_instruction(vcpu);
7313         }
7314         kunmap(page);
7315         kvm_release_page_clean(page);
7316
7317         vmx->nested.vmxon_ptr = vmptr;
7318         ret = enter_vmx_operation(vcpu);
7319         if (ret)
7320                 return ret;
7321
7322         nested_vmx_succeed(vcpu);
7323         return kvm_skip_emulated_instruction(vcpu);
7324 }
7325
7326 /*
7327  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7328  * for running VMX instructions (except VMXON, whose prerequisites are
7329  * slightly different). It also specifies what exception to inject otherwise.
7330  * Note that many of these exceptions have priority over VM exits, so they
7331  * don't have to be checked again here.
7332  */
7333 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7334 {
7335         if (!to_vmx(vcpu)->nested.vmxon) {
7336                 kvm_queue_exception(vcpu, UD_VECTOR);
7337                 return 0;
7338         }
7339         return 1;
7340 }
7341
7342 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7343 {
7344         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7345         vmcs_write64(VMCS_LINK_POINTER, -1ull);
7346 }
7347
7348 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7349 {
7350         if (vmx->nested.current_vmptr == -1ull)
7351                 return;
7352
7353         if (enable_shadow_vmcs) {
7354                 /* copy to memory all shadowed fields in case
7355                    they were modified */
7356                 copy_shadow_to_vmcs12(vmx);
7357                 vmx->nested.sync_shadow_vmcs = false;
7358                 vmx_disable_shadow_vmcs(vmx);
7359         }
7360         vmx->nested.posted_intr_nv = -1;
7361
7362         /* Flush VMCS12 to guest memory */
7363         kvm_vcpu_write_guest_page(&vmx->vcpu,
7364                                   vmx->nested.current_vmptr >> PAGE_SHIFT,
7365                                   vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7366
7367         vmx->nested.current_vmptr = -1ull;
7368 }
7369
7370 /*
7371  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7372  * just stops using VMX.
7373  */
7374 static void free_nested(struct vcpu_vmx *vmx)
7375 {
7376         if (!vmx->nested.vmxon)
7377                 return;
7378
7379         vmx->nested.vmxon = false;
7380         free_vpid(vmx->nested.vpid02);
7381         vmx->nested.posted_intr_nv = -1;
7382         vmx->nested.current_vmptr = -1ull;
7383         if (vmx->nested.msr_bitmap) {
7384                 free_page((unsigned long)vmx->nested.msr_bitmap);
7385                 vmx->nested.msr_bitmap = NULL;
7386         }
7387         if (enable_shadow_vmcs) {
7388                 vmx_disable_shadow_vmcs(vmx);
7389                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7390                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7391                 vmx->vmcs01.shadow_vmcs = NULL;
7392         }
7393         kfree(vmx->nested.cached_vmcs12);
7394         /* Unpin physical memory we referred to in current vmcs02 */
7395         if (vmx->nested.apic_access_page) {
7396                 kvm_release_page_dirty(vmx->nested.apic_access_page);
7397                 vmx->nested.apic_access_page = NULL;
7398         }
7399         if (vmx->nested.virtual_apic_page) {
7400                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
7401                 vmx->nested.virtual_apic_page = NULL;
7402         }
7403         if (vmx->nested.pi_desc_page) {
7404                 kunmap(vmx->nested.pi_desc_page);
7405                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
7406                 vmx->nested.pi_desc_page = NULL;
7407                 vmx->nested.pi_desc = NULL;
7408         }
7409
7410         nested_free_all_saved_vmcss(vmx);
7411 }
7412
7413 /* Emulate the VMXOFF instruction */
7414 static int handle_vmoff(struct kvm_vcpu *vcpu)
7415 {
7416         if (!nested_vmx_check_permission(vcpu))
7417                 return 1;
7418         free_nested(to_vmx(vcpu));
7419         nested_vmx_succeed(vcpu);
7420         return kvm_skip_emulated_instruction(vcpu);
7421 }
7422
7423 /* Emulate the VMCLEAR instruction */
7424 static int handle_vmclear(struct kvm_vcpu *vcpu)
7425 {
7426         struct vcpu_vmx *vmx = to_vmx(vcpu);
7427         u32 zero = 0;
7428         gpa_t vmptr;
7429
7430         if (!nested_vmx_check_permission(vcpu))
7431                 return 1;
7432
7433         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7434                 return 1;
7435
7436         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7437                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7438                 return kvm_skip_emulated_instruction(vcpu);
7439         }
7440
7441         if (vmptr == vmx->nested.vmxon_ptr) {
7442                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7443                 return kvm_skip_emulated_instruction(vcpu);
7444         }
7445
7446         if (vmptr == vmx->nested.current_vmptr)
7447                 nested_release_vmcs12(vmx);
7448
7449         kvm_vcpu_write_guest(vcpu,
7450                         vmptr + offsetof(struct vmcs12, launch_state),
7451                         &zero, sizeof(zero));
7452
7453         nested_free_vmcs02(vmx, vmptr);
7454
7455         nested_vmx_succeed(vcpu);
7456         return kvm_skip_emulated_instruction(vcpu);
7457 }
7458
7459 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7460
7461 /* Emulate the VMLAUNCH instruction */
7462 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7463 {
7464         return nested_vmx_run(vcpu, true);
7465 }
7466
7467 /* Emulate the VMRESUME instruction */
7468 static int handle_vmresume(struct kvm_vcpu *vcpu)
7469 {
7470
7471         return nested_vmx_run(vcpu, false);
7472 }
7473
7474 /*
7475  * Read a vmcs12 field. Since these can have varying lengths and we return
7476  * one type, we chose the biggest type (u64) and zero-extend the return value
7477  * to that size. Note that the caller, handle_vmread, might need to use only
7478  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7479  * 64-bit fields are to be returned).
7480  */
7481 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7482                                   unsigned long field, u64 *ret)
7483 {
7484         short offset = vmcs_field_to_offset(field);
7485         char *p;
7486
7487         if (offset < 0)
7488                 return offset;
7489
7490         p = ((char *)(get_vmcs12(vcpu))) + offset;
7491
7492         switch (vmcs_field_type(field)) {
7493         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7494                 *ret = *((natural_width *)p);
7495                 return 0;
7496         case VMCS_FIELD_TYPE_U16:
7497                 *ret = *((u16 *)p);
7498                 return 0;
7499         case VMCS_FIELD_TYPE_U32:
7500                 *ret = *((u32 *)p);
7501                 return 0;
7502         case VMCS_FIELD_TYPE_U64:
7503                 *ret = *((u64 *)p);
7504                 return 0;
7505         default:
7506                 WARN_ON(1);
7507                 return -ENOENT;
7508         }
7509 }
7510
7511
7512 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7513                                    unsigned long field, u64 field_value){
7514         short offset = vmcs_field_to_offset(field);
7515         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7516         if (offset < 0)
7517                 return offset;
7518
7519         switch (vmcs_field_type(field)) {
7520         case VMCS_FIELD_TYPE_U16:
7521                 *(u16 *)p = field_value;
7522                 return 0;
7523         case VMCS_FIELD_TYPE_U32:
7524                 *(u32 *)p = field_value;
7525                 return 0;
7526         case VMCS_FIELD_TYPE_U64:
7527                 *(u64 *)p = field_value;
7528                 return 0;
7529         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7530                 *(natural_width *)p = field_value;
7531                 return 0;
7532         default:
7533                 WARN_ON(1);
7534                 return -ENOENT;
7535         }
7536
7537 }
7538
7539 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7540 {
7541         int i;
7542         unsigned long field;
7543         u64 field_value;
7544         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7545         const unsigned long *fields = shadow_read_write_fields;
7546         const int num_fields = max_shadow_read_write_fields;
7547
7548         preempt_disable();
7549
7550         vmcs_load(shadow_vmcs);
7551
7552         for (i = 0; i < num_fields; i++) {
7553                 field = fields[i];
7554                 switch (vmcs_field_type(field)) {
7555                 case VMCS_FIELD_TYPE_U16:
7556                         field_value = vmcs_read16(field);
7557                         break;
7558                 case VMCS_FIELD_TYPE_U32:
7559                         field_value = vmcs_read32(field);
7560                         break;
7561                 case VMCS_FIELD_TYPE_U64:
7562                         field_value = vmcs_read64(field);
7563                         break;
7564                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7565                         field_value = vmcs_readl(field);
7566                         break;
7567                 default:
7568                         WARN_ON(1);
7569                         continue;
7570                 }
7571                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7572         }
7573
7574         vmcs_clear(shadow_vmcs);
7575         vmcs_load(vmx->loaded_vmcs->vmcs);
7576
7577         preempt_enable();
7578 }
7579
7580 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7581 {
7582         const unsigned long *fields[] = {
7583                 shadow_read_write_fields,
7584                 shadow_read_only_fields
7585         };
7586         const int max_fields[] = {
7587                 max_shadow_read_write_fields,
7588                 max_shadow_read_only_fields
7589         };
7590         int i, q;
7591         unsigned long field;
7592         u64 field_value = 0;
7593         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7594
7595         vmcs_load(shadow_vmcs);
7596
7597         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7598                 for (i = 0; i < max_fields[q]; i++) {
7599                         field = fields[q][i];
7600                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7601
7602                         switch (vmcs_field_type(field)) {
7603                         case VMCS_FIELD_TYPE_U16:
7604                                 vmcs_write16(field, (u16)field_value);
7605                                 break;
7606                         case VMCS_FIELD_TYPE_U32:
7607                                 vmcs_write32(field, (u32)field_value);
7608                                 break;
7609                         case VMCS_FIELD_TYPE_U64:
7610                                 vmcs_write64(field, (u64)field_value);
7611                                 break;
7612                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7613                                 vmcs_writel(field, (long)field_value);
7614                                 break;
7615                         default:
7616                                 WARN_ON(1);
7617                                 break;
7618                         }
7619                 }
7620         }
7621
7622         vmcs_clear(shadow_vmcs);
7623         vmcs_load(vmx->loaded_vmcs->vmcs);
7624 }
7625
7626 /*
7627  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7628  * used before) all generate the same failure when it is missing.
7629  */
7630 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7631 {
7632         struct vcpu_vmx *vmx = to_vmx(vcpu);
7633         if (vmx->nested.current_vmptr == -1ull) {
7634                 nested_vmx_failInvalid(vcpu);
7635                 return 0;
7636         }
7637         return 1;
7638 }
7639
7640 static int handle_vmread(struct kvm_vcpu *vcpu)
7641 {
7642         unsigned long field;
7643         u64 field_value;
7644         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7645         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7646         gva_t gva = 0;
7647
7648         if (!nested_vmx_check_permission(vcpu))
7649                 return 1;
7650
7651         if (!nested_vmx_check_vmcs12(vcpu))
7652                 return kvm_skip_emulated_instruction(vcpu);
7653
7654         /* Decode instruction info and find the field to read */
7655         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7656         /* Read the field, zero-extended to a u64 field_value */
7657         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7658                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7659                 return kvm_skip_emulated_instruction(vcpu);
7660         }
7661         /*
7662          * Now copy part of this value to register or memory, as requested.
7663          * Note that the number of bits actually copied is 32 or 64 depending
7664          * on the guest's mode (32 or 64 bit), not on the given field's length.
7665          */
7666         if (vmx_instruction_info & (1u << 10)) {
7667                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7668                         field_value);
7669         } else {
7670                 if (get_vmx_mem_address(vcpu, exit_qualification,
7671                                 vmx_instruction_info, true, &gva))
7672                         return 1;
7673                 /* _system ok, as hardware has verified cpl=0 */
7674                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7675                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7676         }
7677
7678         nested_vmx_succeed(vcpu);
7679         return kvm_skip_emulated_instruction(vcpu);
7680 }
7681
7682
7683 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7684 {
7685         unsigned long field;
7686         gva_t gva;
7687         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7688         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7689         /* The value to write might be 32 or 64 bits, depending on L1's long
7690          * mode, and eventually we need to write that into a field of several
7691          * possible lengths. The code below first zero-extends the value to 64
7692          * bit (field_value), and then copies only the appropriate number of
7693          * bits into the vmcs12 field.
7694          */
7695         u64 field_value = 0;
7696         struct x86_exception e;
7697
7698         if (!nested_vmx_check_permission(vcpu))
7699                 return 1;
7700
7701         if (!nested_vmx_check_vmcs12(vcpu))
7702                 return kvm_skip_emulated_instruction(vcpu);
7703
7704         if (vmx_instruction_info & (1u << 10))
7705                 field_value = kvm_register_readl(vcpu,
7706                         (((vmx_instruction_info) >> 3) & 0xf));
7707         else {
7708                 if (get_vmx_mem_address(vcpu, exit_qualification,
7709                                 vmx_instruction_info, false, &gva))
7710                         return 1;
7711                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7712                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7713                         kvm_inject_page_fault(vcpu, &e);
7714                         return 1;
7715                 }
7716         }
7717
7718
7719         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7720         if (vmcs_field_readonly(field)) {
7721                 nested_vmx_failValid(vcpu,
7722                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7723                 return kvm_skip_emulated_instruction(vcpu);
7724         }
7725
7726         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7727                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7728                 return kvm_skip_emulated_instruction(vcpu);
7729         }
7730
7731         nested_vmx_succeed(vcpu);
7732         return kvm_skip_emulated_instruction(vcpu);
7733 }
7734
7735 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7736 {
7737         vmx->nested.current_vmptr = vmptr;
7738         if (enable_shadow_vmcs) {
7739                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7740                               SECONDARY_EXEC_SHADOW_VMCS);
7741                 vmcs_write64(VMCS_LINK_POINTER,
7742                              __pa(vmx->vmcs01.shadow_vmcs));
7743                 vmx->nested.sync_shadow_vmcs = true;
7744         }
7745 }
7746
7747 /* Emulate the VMPTRLD instruction */
7748 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7749 {
7750         struct vcpu_vmx *vmx = to_vmx(vcpu);
7751         gpa_t vmptr;
7752
7753         if (!nested_vmx_check_permission(vcpu))
7754                 return 1;
7755
7756         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7757                 return 1;
7758
7759         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7760                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7761                 return kvm_skip_emulated_instruction(vcpu);
7762         }
7763
7764         if (vmptr == vmx->nested.vmxon_ptr) {
7765                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7766                 return kvm_skip_emulated_instruction(vcpu);
7767         }
7768
7769         if (vmx->nested.current_vmptr != vmptr) {
7770                 struct vmcs12 *new_vmcs12;
7771                 struct page *page;
7772                 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7773                 if (is_error_page(page)) {
7774                         nested_vmx_failInvalid(vcpu);
7775                         return kvm_skip_emulated_instruction(vcpu);
7776                 }
7777                 new_vmcs12 = kmap(page);
7778                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7779                         kunmap(page);
7780                         kvm_release_page_clean(page);
7781                         nested_vmx_failValid(vcpu,
7782                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7783                         return kvm_skip_emulated_instruction(vcpu);
7784                 }
7785
7786                 nested_release_vmcs12(vmx);
7787                 /*
7788                  * Load VMCS12 from guest memory since it is not already
7789                  * cached.
7790                  */
7791                 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
7792                 kunmap(page);
7793                 kvm_release_page_clean(page);
7794
7795                 set_current_vmptr(vmx, vmptr);
7796         }
7797
7798         nested_vmx_succeed(vcpu);
7799         return kvm_skip_emulated_instruction(vcpu);
7800 }
7801
7802 /* Emulate the VMPTRST instruction */
7803 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7804 {
7805         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7806         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7807         gva_t vmcs_gva;
7808         struct x86_exception e;
7809
7810         if (!nested_vmx_check_permission(vcpu))
7811                 return 1;
7812
7813         if (get_vmx_mem_address(vcpu, exit_qualification,
7814                         vmx_instruction_info, true, &vmcs_gva))
7815                 return 1;
7816         /* ok to use *_system, as hardware has verified cpl=0 */
7817         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7818                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7819                                  sizeof(u64), &e)) {
7820                 kvm_inject_page_fault(vcpu, &e);
7821                 return 1;
7822         }
7823         nested_vmx_succeed(vcpu);
7824         return kvm_skip_emulated_instruction(vcpu);
7825 }
7826
7827 /* Emulate the INVEPT instruction */
7828 static int handle_invept(struct kvm_vcpu *vcpu)
7829 {
7830         struct vcpu_vmx *vmx = to_vmx(vcpu);
7831         u32 vmx_instruction_info, types;
7832         unsigned long type;
7833         gva_t gva;
7834         struct x86_exception e;
7835         struct {
7836                 u64 eptp, gpa;
7837         } operand;
7838
7839         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7840               SECONDARY_EXEC_ENABLE_EPT) ||
7841             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7842                 kvm_queue_exception(vcpu, UD_VECTOR);
7843                 return 1;
7844         }
7845
7846         if (!nested_vmx_check_permission(vcpu))
7847                 return 1;
7848
7849         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7850         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7851
7852         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7853
7854         if (type >= 32 || !(types & (1 << type))) {
7855                 nested_vmx_failValid(vcpu,
7856                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7857                 return kvm_skip_emulated_instruction(vcpu);
7858         }
7859
7860         /* According to the Intel VMX instruction reference, the memory
7861          * operand is read even if it isn't needed (e.g., for type==global)
7862          */
7863         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7864                         vmx_instruction_info, false, &gva))
7865                 return 1;
7866         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7867                                 sizeof(operand), &e)) {
7868                 kvm_inject_page_fault(vcpu, &e);
7869                 return 1;
7870         }
7871
7872         switch (type) {
7873         case VMX_EPT_EXTENT_GLOBAL:
7874         /*
7875          * TODO: track mappings and invalidate
7876          * single context requests appropriately
7877          */
7878         case VMX_EPT_EXTENT_CONTEXT:
7879                 kvm_mmu_sync_roots(vcpu);
7880                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7881                 nested_vmx_succeed(vcpu);
7882                 break;
7883         default:
7884                 BUG_ON(1);
7885                 break;
7886         }
7887
7888         return kvm_skip_emulated_instruction(vcpu);
7889 }
7890
7891 static int handle_invvpid(struct kvm_vcpu *vcpu)
7892 {
7893         struct vcpu_vmx *vmx = to_vmx(vcpu);
7894         u32 vmx_instruction_info;
7895         unsigned long type, types;
7896         gva_t gva;
7897         struct x86_exception e;
7898         struct {
7899                 u64 vpid;
7900                 u64 gla;
7901         } operand;
7902
7903         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7904               SECONDARY_EXEC_ENABLE_VPID) ||
7905                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7906                 kvm_queue_exception(vcpu, UD_VECTOR);
7907                 return 1;
7908         }
7909
7910         if (!nested_vmx_check_permission(vcpu))
7911                 return 1;
7912
7913         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7914         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7915
7916         types = (vmx->nested.nested_vmx_vpid_caps &
7917                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7918
7919         if (type >= 32 || !(types & (1 << type))) {
7920                 nested_vmx_failValid(vcpu,
7921                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7922                 return kvm_skip_emulated_instruction(vcpu);
7923         }
7924
7925         /* according to the intel vmx instruction reference, the memory
7926          * operand is read even if it isn't needed (e.g., for type==global)
7927          */
7928         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7929                         vmx_instruction_info, false, &gva))
7930                 return 1;
7931         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7932                                 sizeof(operand), &e)) {
7933                 kvm_inject_page_fault(vcpu, &e);
7934                 return 1;
7935         }
7936         if (operand.vpid >> 16) {
7937                 nested_vmx_failValid(vcpu,
7938                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7939                 return kvm_skip_emulated_instruction(vcpu);
7940         }
7941
7942         switch (type) {
7943         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7944                 if (is_noncanonical_address(operand.gla, vcpu)) {
7945                         nested_vmx_failValid(vcpu,
7946                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7947                         return kvm_skip_emulated_instruction(vcpu);
7948                 }
7949                 /* fall through */
7950         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7951         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7952                 if (!operand.vpid) {
7953                         nested_vmx_failValid(vcpu,
7954                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7955                         return kvm_skip_emulated_instruction(vcpu);
7956                 }
7957                 break;
7958         case VMX_VPID_EXTENT_ALL_CONTEXT:
7959                 break;
7960         default:
7961                 WARN_ON_ONCE(1);
7962                 return kvm_skip_emulated_instruction(vcpu);
7963         }
7964
7965         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7966         nested_vmx_succeed(vcpu);
7967
7968         return kvm_skip_emulated_instruction(vcpu);
7969 }
7970
7971 static int handle_pml_full(struct kvm_vcpu *vcpu)
7972 {
7973         unsigned long exit_qualification;
7974
7975         trace_kvm_pml_full(vcpu->vcpu_id);
7976
7977         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7978
7979         /*
7980          * PML buffer FULL happened while executing iret from NMI,
7981          * "blocked by NMI" bit has to be set before next VM entry.
7982          */
7983         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7984                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7985                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7986                                 GUEST_INTR_STATE_NMI);
7987
7988         /*
7989          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7990          * here.., and there's no userspace involvement needed for PML.
7991          */
7992         return 1;
7993 }
7994
7995 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7996 {
7997         kvm_lapic_expired_hv_timer(vcpu);
7998         return 1;
7999 }
8000
8001 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8002 {
8003         struct vcpu_vmx *vmx = to_vmx(vcpu);
8004         int maxphyaddr = cpuid_maxphyaddr(vcpu);
8005
8006         /* Check for memory type validity */
8007         switch (address & VMX_EPTP_MT_MASK) {
8008         case VMX_EPTP_MT_UC:
8009                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT))
8010                         return false;
8011                 break;
8012         case VMX_EPTP_MT_WB:
8013                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT))
8014                         return false;
8015                 break;
8016         default:
8017                 return false;
8018         }
8019
8020         /* only 4 levels page-walk length are valid */
8021         if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8022                 return false;
8023
8024         /* Reserved bits should not be set */
8025         if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8026                 return false;
8027
8028         /* AD, if set, should be supported */
8029         if (address & VMX_EPTP_AD_ENABLE_BIT) {
8030                 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT))
8031                         return false;
8032         }
8033
8034         return true;
8035 }
8036
8037 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8038                                      struct vmcs12 *vmcs12)
8039 {
8040         u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8041         u64 address;
8042         bool accessed_dirty;
8043         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8044
8045         if (!nested_cpu_has_eptp_switching(vmcs12) ||
8046             !nested_cpu_has_ept(vmcs12))
8047                 return 1;
8048
8049         if (index >= VMFUNC_EPTP_ENTRIES)
8050                 return 1;
8051
8052
8053         if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8054                                      &address, index * 8, 8))
8055                 return 1;
8056
8057         accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8058
8059         /*
8060          * If the (L2) guest does a vmfunc to the currently
8061          * active ept pointer, we don't have to do anything else
8062          */
8063         if (vmcs12->ept_pointer != address) {
8064                 if (!valid_ept_address(vcpu, address))
8065                         return 1;
8066
8067                 kvm_mmu_unload(vcpu);
8068                 mmu->ept_ad = accessed_dirty;
8069                 mmu->base_role.ad_disabled = !accessed_dirty;
8070                 vmcs12->ept_pointer = address;
8071                 /*
8072                  * TODO: Check what's the correct approach in case
8073                  * mmu reload fails. Currently, we just let the next
8074                  * reload potentially fail
8075                  */
8076                 kvm_mmu_reload(vcpu);
8077         }
8078
8079         return 0;
8080 }
8081
8082 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8083 {
8084         struct vcpu_vmx *vmx = to_vmx(vcpu);
8085         struct vmcs12 *vmcs12;
8086         u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8087
8088         /*
8089          * VMFUNC is only supported for nested guests, but we always enable the
8090          * secondary control for simplicity; for non-nested mode, fake that we
8091          * didn't by injecting #UD.
8092          */
8093         if (!is_guest_mode(vcpu)) {
8094                 kvm_queue_exception(vcpu, UD_VECTOR);
8095                 return 1;
8096         }
8097
8098         vmcs12 = get_vmcs12(vcpu);
8099         if ((vmcs12->vm_function_control & (1 << function)) == 0)
8100                 goto fail;
8101
8102         switch (function) {
8103         case 0:
8104                 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8105                         goto fail;
8106                 break;
8107         default:
8108                 goto fail;
8109         }
8110         return kvm_skip_emulated_instruction(vcpu);
8111
8112 fail:
8113         nested_vmx_vmexit(vcpu, vmx->exit_reason,
8114                           vmcs_read32(VM_EXIT_INTR_INFO),
8115                           vmcs_readl(EXIT_QUALIFICATION));
8116         return 1;
8117 }
8118
8119 /*
8120  * The exit handlers return 1 if the exit was handled fully and guest execution
8121  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
8122  * to be done to userspace and return 0.
8123  */
8124 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8125         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
8126         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
8127         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
8128         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
8129         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
8130         [EXIT_REASON_CR_ACCESS]               = handle_cr,
8131         [EXIT_REASON_DR_ACCESS]               = handle_dr,
8132         [EXIT_REASON_CPUID]                   = handle_cpuid,
8133         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
8134         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
8135         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
8136         [EXIT_REASON_HLT]                     = handle_halt,
8137         [EXIT_REASON_INVD]                    = handle_invd,
8138         [EXIT_REASON_INVLPG]                  = handle_invlpg,
8139         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
8140         [EXIT_REASON_VMCALL]                  = handle_vmcall,
8141         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
8142         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
8143         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
8144         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
8145         [EXIT_REASON_VMREAD]                  = handle_vmread,
8146         [EXIT_REASON_VMRESUME]                = handle_vmresume,
8147         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
8148         [EXIT_REASON_VMOFF]                   = handle_vmoff,
8149         [EXIT_REASON_VMON]                    = handle_vmon,
8150         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
8151         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
8152         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
8153         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
8154         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
8155         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
8156         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
8157         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
8158         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
8159         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
8160         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
8161         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
8162         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
8163         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
8164         [EXIT_REASON_INVEPT]                  = handle_invept,
8165         [EXIT_REASON_INVVPID]                 = handle_invvpid,
8166         [EXIT_REASON_RDRAND]                  = handle_invalid_op,
8167         [EXIT_REASON_RDSEED]                  = handle_invalid_op,
8168         [EXIT_REASON_XSAVES]                  = handle_xsaves,
8169         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
8170         [EXIT_REASON_PML_FULL]                = handle_pml_full,
8171         [EXIT_REASON_VMFUNC]                  = handle_vmfunc,
8172         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
8173 };
8174
8175 static const int kvm_vmx_max_exit_handlers =
8176         ARRAY_SIZE(kvm_vmx_exit_handlers);
8177
8178 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8179                                        struct vmcs12 *vmcs12)
8180 {
8181         unsigned long exit_qualification;
8182         gpa_t bitmap, last_bitmap;
8183         unsigned int port;
8184         int size;
8185         u8 b;
8186
8187         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8188                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8189
8190         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8191
8192         port = exit_qualification >> 16;
8193         size = (exit_qualification & 7) + 1;
8194
8195         last_bitmap = (gpa_t)-1;
8196         b = -1;
8197
8198         while (size > 0) {
8199                 if (port < 0x8000)
8200                         bitmap = vmcs12->io_bitmap_a;
8201                 else if (port < 0x10000)
8202                         bitmap = vmcs12->io_bitmap_b;
8203                 else
8204                         return true;
8205                 bitmap += (port & 0x7fff) / 8;
8206
8207                 if (last_bitmap != bitmap)
8208                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8209                                 return true;
8210                 if (b & (1 << (port & 7)))
8211                         return true;
8212
8213                 port++;
8214                 size--;
8215                 last_bitmap = bitmap;
8216         }
8217
8218         return false;
8219 }
8220
8221 /*
8222  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8223  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8224  * disinterest in the current event (read or write a specific MSR) by using an
8225  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8226  */
8227 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8228         struct vmcs12 *vmcs12, u32 exit_reason)
8229 {
8230         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8231         gpa_t bitmap;
8232
8233         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8234                 return true;
8235
8236         /*
8237          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8238          * for the four combinations of read/write and low/high MSR numbers.
8239          * First we need to figure out which of the four to use:
8240          */
8241         bitmap = vmcs12->msr_bitmap;
8242         if (exit_reason == EXIT_REASON_MSR_WRITE)
8243                 bitmap += 2048;
8244         if (msr_index >= 0xc0000000) {
8245                 msr_index -= 0xc0000000;
8246                 bitmap += 1024;
8247         }
8248
8249         /* Then read the msr_index'th bit from this bitmap: */
8250         if (msr_index < 1024*8) {
8251                 unsigned char b;
8252                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8253                         return true;
8254                 return 1 & (b >> (msr_index & 7));
8255         } else
8256                 return true; /* let L1 handle the wrong parameter */
8257 }
8258
8259 /*
8260  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8261  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8262  * intercept (via guest_host_mask etc.) the current event.
8263  */
8264 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8265         struct vmcs12 *vmcs12)
8266 {
8267         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8268         int cr = exit_qualification & 15;
8269         int reg;
8270         unsigned long val;
8271
8272         switch ((exit_qualification >> 4) & 3) {
8273         case 0: /* mov to cr */
8274                 reg = (exit_qualification >> 8) & 15;
8275                 val = kvm_register_readl(vcpu, reg);
8276                 switch (cr) {
8277                 case 0:
8278                         if (vmcs12->cr0_guest_host_mask &
8279                             (val ^ vmcs12->cr0_read_shadow))
8280                                 return true;
8281                         break;
8282                 case 3:
8283                         if ((vmcs12->cr3_target_count >= 1 &&
8284                                         vmcs12->cr3_target_value0 == val) ||
8285                                 (vmcs12->cr3_target_count >= 2 &&
8286                                         vmcs12->cr3_target_value1 == val) ||
8287                                 (vmcs12->cr3_target_count >= 3 &&
8288                                         vmcs12->cr3_target_value2 == val) ||
8289                                 (vmcs12->cr3_target_count >= 4 &&
8290                                         vmcs12->cr3_target_value3 == val))
8291                                 return false;
8292                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8293                                 return true;
8294                         break;
8295                 case 4:
8296                         if (vmcs12->cr4_guest_host_mask &
8297                             (vmcs12->cr4_read_shadow ^ val))
8298                                 return true;
8299                         break;
8300                 case 8:
8301                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8302                                 return true;
8303                         break;
8304                 }
8305                 break;
8306         case 2: /* clts */
8307                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8308                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8309                         return true;
8310                 break;
8311         case 1: /* mov from cr */
8312                 switch (cr) {
8313                 case 3:
8314                         if (vmcs12->cpu_based_vm_exec_control &
8315                             CPU_BASED_CR3_STORE_EXITING)
8316                                 return true;
8317                         break;
8318                 case 8:
8319                         if (vmcs12->cpu_based_vm_exec_control &
8320                             CPU_BASED_CR8_STORE_EXITING)
8321                                 return true;
8322                         break;
8323                 }
8324                 break;
8325         case 3: /* lmsw */
8326                 /*
8327                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8328                  * cr0. Other attempted changes are ignored, with no exit.
8329                  */
8330                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8331                 if (vmcs12->cr0_guest_host_mask & 0xe &
8332                     (val ^ vmcs12->cr0_read_shadow))
8333                         return true;
8334                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8335                     !(vmcs12->cr0_read_shadow & 0x1) &&
8336                     (val & 0x1))
8337                         return true;
8338                 break;
8339         }
8340         return false;
8341 }
8342
8343 /*
8344  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8345  * should handle it ourselves in L0 (and then continue L2). Only call this
8346  * when in is_guest_mode (L2).
8347  */
8348 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8349 {
8350         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8351         struct vcpu_vmx *vmx = to_vmx(vcpu);
8352         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8353
8354         if (vmx->nested.nested_run_pending)
8355                 return false;
8356
8357         if (unlikely(vmx->fail)) {
8358                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8359                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8360                 return true;
8361         }
8362
8363         /*
8364          * The host physical addresses of some pages of guest memory
8365          * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8366          * may write to these pages via their host physical address while
8367          * L2 is running, bypassing any address-translation-based dirty
8368          * tracking (e.g. EPT write protection).
8369          *
8370          * Mark them dirty on every exit from L2 to prevent them from
8371          * getting out of sync with dirty tracking.
8372          */
8373         nested_mark_vmcs12_pages_dirty(vcpu);
8374
8375         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8376                                 vmcs_readl(EXIT_QUALIFICATION),
8377                                 vmx->idt_vectoring_info,
8378                                 intr_info,
8379                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8380                                 KVM_ISA_VMX);
8381
8382         switch (exit_reason) {
8383         case EXIT_REASON_EXCEPTION_NMI:
8384                 if (is_nmi(intr_info))
8385                         return false;
8386                 else if (is_page_fault(intr_info))
8387                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8388                 else if (is_no_device(intr_info) &&
8389                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8390                         return false;
8391                 else if (is_debug(intr_info) &&
8392                          vcpu->guest_debug &
8393                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8394                         return false;
8395                 else if (is_breakpoint(intr_info) &&
8396                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8397                         return false;
8398                 return vmcs12->exception_bitmap &
8399                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8400         case EXIT_REASON_EXTERNAL_INTERRUPT:
8401                 return false;
8402         case EXIT_REASON_TRIPLE_FAULT:
8403                 return true;
8404         case EXIT_REASON_PENDING_INTERRUPT:
8405                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8406         case EXIT_REASON_NMI_WINDOW:
8407                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8408         case EXIT_REASON_TASK_SWITCH:
8409                 return true;
8410         case EXIT_REASON_CPUID:
8411                 return true;
8412         case EXIT_REASON_HLT:
8413                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8414         case EXIT_REASON_INVD:
8415                 return true;
8416         case EXIT_REASON_INVLPG:
8417                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8418         case EXIT_REASON_RDPMC:
8419                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8420         case EXIT_REASON_RDRAND:
8421                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8422         case EXIT_REASON_RDSEED:
8423                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8424         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8425                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8426         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8427         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8428         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8429         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8430         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8431         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8432                 /*
8433                  * VMX instructions trap unconditionally. This allows L1 to
8434                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8435                  */
8436                 return true;
8437         case EXIT_REASON_CR_ACCESS:
8438                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8439         case EXIT_REASON_DR_ACCESS:
8440                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8441         case EXIT_REASON_IO_INSTRUCTION:
8442                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8443         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8444                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8445         case EXIT_REASON_MSR_READ:
8446         case EXIT_REASON_MSR_WRITE:
8447                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8448         case EXIT_REASON_INVALID_STATE:
8449                 return true;
8450         case EXIT_REASON_MWAIT_INSTRUCTION:
8451                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8452         case EXIT_REASON_MONITOR_TRAP_FLAG:
8453                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8454         case EXIT_REASON_MONITOR_INSTRUCTION:
8455                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8456         case EXIT_REASON_PAUSE_INSTRUCTION:
8457                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8458                         nested_cpu_has2(vmcs12,
8459                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8460         case EXIT_REASON_MCE_DURING_VMENTRY:
8461                 return false;
8462         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8463                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8464         case EXIT_REASON_APIC_ACCESS:
8465                 return nested_cpu_has2(vmcs12,
8466                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8467         case EXIT_REASON_APIC_WRITE:
8468         case EXIT_REASON_EOI_INDUCED:
8469                 /* apic_write and eoi_induced should exit unconditionally. */
8470                 return true;
8471         case EXIT_REASON_EPT_VIOLATION:
8472                 /*
8473                  * L0 always deals with the EPT violation. If nested EPT is
8474                  * used, and the nested mmu code discovers that the address is
8475                  * missing in the guest EPT table (EPT12), the EPT violation
8476                  * will be injected with nested_ept_inject_page_fault()
8477                  */
8478                 return false;
8479         case EXIT_REASON_EPT_MISCONFIG:
8480                 /*
8481                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8482                  * table (shadow on EPT) or a merged EPT table that L0 built
8483                  * (EPT on EPT). So any problems with the structure of the
8484                  * table is L0's fault.
8485                  */
8486                 return false;
8487         case EXIT_REASON_INVPCID:
8488                 return
8489                         nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
8490                         nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8491         case EXIT_REASON_WBINVD:
8492                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8493         case EXIT_REASON_XSETBV:
8494                 return true;
8495         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8496                 /*
8497                  * This should never happen, since it is not possible to
8498                  * set XSS to a non-zero value---neither in L1 nor in L2.
8499                  * If if it were, XSS would have to be checked against
8500                  * the XSS exit bitmap in vmcs12.
8501                  */
8502                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8503         case EXIT_REASON_PREEMPTION_TIMER:
8504                 return false;
8505         case EXIT_REASON_PML_FULL:
8506                 /* We emulate PML support to L1. */
8507                 return false;
8508         case EXIT_REASON_VMFUNC:
8509                 /* VM functions are emulated through L2->L0 vmexits. */
8510                 return false;
8511         default:
8512                 return true;
8513         }
8514 }
8515
8516 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8517 {
8518         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8519
8520         /*
8521          * At this point, the exit interruption info in exit_intr_info
8522          * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
8523          * we need to query the in-kernel LAPIC.
8524          */
8525         WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8526         if ((exit_intr_info &
8527              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8528             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8529                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8530                 vmcs12->vm_exit_intr_error_code =
8531                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8532         }
8533
8534         nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8535                           vmcs_readl(EXIT_QUALIFICATION));
8536         return 1;
8537 }
8538
8539 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8540 {
8541         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8542         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8543 }
8544
8545 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8546 {
8547         if (vmx->pml_pg) {
8548                 __free_page(vmx->pml_pg);
8549                 vmx->pml_pg = NULL;
8550         }
8551 }
8552
8553 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8554 {
8555         struct vcpu_vmx *vmx = to_vmx(vcpu);
8556         u64 *pml_buf;
8557         u16 pml_idx;
8558
8559         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8560
8561         /* Do nothing if PML buffer is empty */
8562         if (pml_idx == (PML_ENTITY_NUM - 1))
8563                 return;
8564
8565         /* PML index always points to next available PML buffer entity */
8566         if (pml_idx >= PML_ENTITY_NUM)
8567                 pml_idx = 0;
8568         else
8569                 pml_idx++;
8570
8571         pml_buf = page_address(vmx->pml_pg);
8572         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8573                 u64 gpa;
8574
8575                 gpa = pml_buf[pml_idx];
8576                 WARN_ON(gpa & (PAGE_SIZE - 1));
8577                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8578         }
8579
8580         /* reset PML index */
8581         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8582 }
8583
8584 /*
8585  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8586  * Called before reporting dirty_bitmap to userspace.
8587  */
8588 static void kvm_flush_pml_buffers(struct kvm *kvm)
8589 {
8590         int i;
8591         struct kvm_vcpu *vcpu;
8592         /*
8593          * We only need to kick vcpu out of guest mode here, as PML buffer
8594          * is flushed at beginning of all VMEXITs, and it's obvious that only
8595          * vcpus running in guest are possible to have unflushed GPAs in PML
8596          * buffer.
8597          */
8598         kvm_for_each_vcpu(i, vcpu, kvm)
8599                 kvm_vcpu_kick(vcpu);
8600 }
8601
8602 static void vmx_dump_sel(char *name, uint32_t sel)
8603 {
8604         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8605                name, vmcs_read16(sel),
8606                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8607                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8608                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8609 }
8610
8611 static void vmx_dump_dtsel(char *name, uint32_t limit)
8612 {
8613         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8614                name, vmcs_read32(limit),
8615                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8616 }
8617
8618 static void dump_vmcs(void)
8619 {
8620         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8621         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8622         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8623         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8624         u32 secondary_exec_control = 0;
8625         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8626         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8627         int i, n;
8628
8629         if (cpu_has_secondary_exec_ctrls())
8630                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8631
8632         pr_err("*** Guest State ***\n");
8633         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8634                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8635                vmcs_readl(CR0_GUEST_HOST_MASK));
8636         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8637                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8638         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8639         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8640             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8641         {
8642                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8643                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8644                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8645                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8646         }
8647         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8648                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8649         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8650                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8651         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8652                vmcs_readl(GUEST_SYSENTER_ESP),
8653                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8654         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8655         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8656         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8657         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8658         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8659         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8660         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8661         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8662         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8663         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8664         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8665             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8666                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8667                        efer, vmcs_read64(GUEST_IA32_PAT));
8668         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8669                vmcs_read64(GUEST_IA32_DEBUGCTL),
8670                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8671         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8672                 pr_err("PerfGlobCtl = 0x%016llx\n",
8673                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8674         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8675                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8676         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8677                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8678                vmcs_read32(GUEST_ACTIVITY_STATE));
8679         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8680                 pr_err("InterruptStatus = %04x\n",
8681                        vmcs_read16(GUEST_INTR_STATUS));
8682
8683         pr_err("*** Host State ***\n");
8684         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8685                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8686         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8687                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8688                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8689                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8690                vmcs_read16(HOST_TR_SELECTOR));
8691         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8692                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8693                vmcs_readl(HOST_TR_BASE));
8694         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8695                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8696         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8697                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8698                vmcs_readl(HOST_CR4));
8699         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8700                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8701                vmcs_read32(HOST_IA32_SYSENTER_CS),
8702                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8703         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8704                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8705                        vmcs_read64(HOST_IA32_EFER),
8706                        vmcs_read64(HOST_IA32_PAT));
8707         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8708                 pr_err("PerfGlobCtl = 0x%016llx\n",
8709                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8710
8711         pr_err("*** Control State ***\n");
8712         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8713                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8714         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8715         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8716                vmcs_read32(EXCEPTION_BITMAP),
8717                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8718                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8719         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8720                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8721                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8722                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8723         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8724                vmcs_read32(VM_EXIT_INTR_INFO),
8725                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8726                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8727         pr_err("        reason=%08x qualification=%016lx\n",
8728                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8729         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8730                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8731                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8732         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8733         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8734                 pr_err("TSC Multiplier = 0x%016llx\n",
8735                        vmcs_read64(TSC_MULTIPLIER));
8736         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8737                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8738         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8739                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8740         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8741                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8742         n = vmcs_read32(CR3_TARGET_COUNT);
8743         for (i = 0; i + 1 < n; i += 4)
8744                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8745                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8746                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8747         if (i < n)
8748                 pr_err("CR3 target%u=%016lx\n",
8749                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8750         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8751                 pr_err("PLE Gap=%08x Window=%08x\n",
8752                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8753         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8754                 pr_err("Virtual processor ID = 0x%04x\n",
8755                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8756 }
8757
8758 /*
8759  * The guest has exited.  See if we can fix it or if we need userspace
8760  * assistance.
8761  */
8762 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8763 {
8764         struct vcpu_vmx *vmx = to_vmx(vcpu);
8765         u32 exit_reason = vmx->exit_reason;
8766         u32 vectoring_info = vmx->idt_vectoring_info;
8767
8768         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8769
8770         /*
8771          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8772          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8773          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8774          * mode as if vcpus is in root mode, the PML buffer must has been
8775          * flushed already.
8776          */
8777         if (enable_pml)
8778                 vmx_flush_pml_buffer(vcpu);
8779
8780         /* If guest state is invalid, start emulating */
8781         if (vmx->emulation_required)
8782                 return handle_invalid_guest_state(vcpu);
8783
8784         if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8785                 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
8786
8787         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8788                 dump_vmcs();
8789                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8790                 vcpu->run->fail_entry.hardware_entry_failure_reason
8791                         = exit_reason;
8792                 return 0;
8793         }
8794
8795         if (unlikely(vmx->fail)) {
8796                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8797                 vcpu->run->fail_entry.hardware_entry_failure_reason
8798                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8799                 return 0;
8800         }
8801
8802         /*
8803          * Note:
8804          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8805          * delivery event since it indicates guest is accessing MMIO.
8806          * The vm-exit can be triggered again after return to guest that
8807          * will cause infinite loop.
8808          */
8809         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8810                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8811                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8812                         exit_reason != EXIT_REASON_PML_FULL &&
8813                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8814                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8815                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8816                 vcpu->run->internal.ndata = 3;
8817                 vcpu->run->internal.data[0] = vectoring_info;
8818                 vcpu->run->internal.data[1] = exit_reason;
8819                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8820                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8821                         vcpu->run->internal.ndata++;
8822                         vcpu->run->internal.data[3] =
8823                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8824                 }
8825                 return 0;
8826         }
8827
8828         if (exit_reason < kvm_vmx_max_exit_handlers
8829             && kvm_vmx_exit_handlers[exit_reason])
8830                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8831         else {
8832                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8833                                 exit_reason);
8834                 kvm_queue_exception(vcpu, UD_VECTOR);
8835                 return 1;
8836         }
8837 }
8838
8839 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8840 {
8841         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8842
8843         if (is_guest_mode(vcpu) &&
8844                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8845                 return;
8846
8847         if (irr == -1 || tpr < irr) {
8848                 vmcs_write32(TPR_THRESHOLD, 0);
8849                 return;
8850         }
8851
8852         vmcs_write32(TPR_THRESHOLD, irr);
8853 }
8854
8855 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8856 {
8857         u32 sec_exec_control;
8858
8859         /* Postpone execution until vmcs01 is the current VMCS. */
8860         if (is_guest_mode(vcpu)) {
8861                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8862                 return;
8863         }
8864
8865         if (!cpu_has_vmx_virtualize_x2apic_mode())
8866                 return;
8867
8868         if (!cpu_need_tpr_shadow(vcpu))
8869                 return;
8870
8871         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8872
8873         if (set) {
8874                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8875                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8876         } else {
8877                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8878                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8879                 vmx_flush_tlb_ept_only(vcpu);
8880         }
8881         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8882
8883         vmx_set_msr_bitmap(vcpu);
8884 }
8885
8886 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8887 {
8888         struct vcpu_vmx *vmx = to_vmx(vcpu);
8889
8890         /*
8891          * Currently we do not handle the nested case where L2 has an
8892          * APIC access page of its own; that page is still pinned.
8893          * Hence, we skip the case where the VCPU is in guest mode _and_
8894          * L1 prepared an APIC access page for L2.
8895          *
8896          * For the case where L1 and L2 share the same APIC access page
8897          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8898          * in the vmcs12), this function will only update either the vmcs01
8899          * or the vmcs02.  If the former, the vmcs02 will be updated by
8900          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8901          * the next L2->L1 exit.
8902          */
8903         if (!is_guest_mode(vcpu) ||
8904             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8905                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8906                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8907                 vmx_flush_tlb_ept_only(vcpu);
8908         }
8909 }
8910
8911 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8912 {
8913         u16 status;
8914         u8 old;
8915
8916         if (max_isr == -1)
8917                 max_isr = 0;
8918
8919         status = vmcs_read16(GUEST_INTR_STATUS);
8920         old = status >> 8;
8921         if (max_isr != old) {
8922                 status &= 0xff;
8923                 status |= max_isr << 8;
8924                 vmcs_write16(GUEST_INTR_STATUS, status);
8925         }
8926 }
8927
8928 static void vmx_set_rvi(int vector)
8929 {
8930         u16 status;
8931         u8 old;
8932
8933         if (vector == -1)
8934                 vector = 0;
8935
8936         status = vmcs_read16(GUEST_INTR_STATUS);
8937         old = (u8)status & 0xff;
8938         if ((u8)vector != old) {
8939                 status &= ~0xff;
8940                 status |= (u8)vector;
8941                 vmcs_write16(GUEST_INTR_STATUS, status);
8942         }
8943 }
8944
8945 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8946 {
8947         if (!is_guest_mode(vcpu)) {
8948                 vmx_set_rvi(max_irr);
8949                 return;
8950         }
8951
8952         if (max_irr == -1)
8953                 return;
8954
8955         /*
8956          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8957          * handles it.
8958          */
8959         if (nested_exit_on_intr(vcpu))
8960                 return;
8961
8962         /*
8963          * Else, fall back to pre-APICv interrupt injection since L2
8964          * is run without virtual interrupt delivery.
8965          */
8966         if (!kvm_event_needs_reinjection(vcpu) &&
8967             vmx_interrupt_allowed(vcpu)) {
8968                 kvm_queue_interrupt(vcpu, max_irr, false);
8969                 vmx_inject_irq(vcpu);
8970         }
8971 }
8972
8973 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8974 {
8975         struct vcpu_vmx *vmx = to_vmx(vcpu);
8976         int max_irr;
8977
8978         WARN_ON(!vcpu->arch.apicv_active);
8979         if (pi_test_on(&vmx->pi_desc)) {
8980                 pi_clear_on(&vmx->pi_desc);
8981                 /*
8982                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8983                  * But on x86 this is just a compiler barrier anyway.
8984                  */
8985                 smp_mb__after_atomic();
8986                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8987         } else {
8988                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8989         }
8990         vmx_hwapic_irr_update(vcpu, max_irr);
8991         return max_irr;
8992 }
8993
8994 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8995 {
8996         if (!kvm_vcpu_apicv_active(vcpu))
8997                 return;
8998
8999         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9000         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9001         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9002         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9003 }
9004
9005 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9006 {
9007         struct vcpu_vmx *vmx = to_vmx(vcpu);
9008
9009         pi_clear_on(&vmx->pi_desc);
9010         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9011 }
9012
9013 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9014 {
9015         u32 exit_intr_info = 0;
9016         u16 basic_exit_reason = (u16)vmx->exit_reason;
9017
9018         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9019               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9020                 return;
9021
9022         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9023                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9024         vmx->exit_intr_info = exit_intr_info;
9025
9026         /* if exit due to PF check for async PF */
9027         if (is_page_fault(exit_intr_info))
9028                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9029
9030         /* Handle machine checks before interrupts are enabled */
9031         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9032             is_machine_check(exit_intr_info))
9033                 kvm_machine_check();
9034
9035         /* We need to handle NMIs before interrupts are enabled */
9036         if (is_nmi(exit_intr_info)) {
9037                 kvm_before_handle_nmi(&vmx->vcpu);
9038                 asm("int $2");
9039                 kvm_after_handle_nmi(&vmx->vcpu);
9040         }
9041 }
9042
9043 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9044 {
9045         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9046
9047         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9048                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9049                 unsigned int vector;
9050                 unsigned long entry;
9051                 gate_desc *desc;
9052                 struct vcpu_vmx *vmx = to_vmx(vcpu);
9053 #ifdef CONFIG_X86_64
9054                 unsigned long tmp;
9055 #endif
9056
9057                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
9058                 desc = (gate_desc *)vmx->host_idt_base + vector;
9059                 entry = gate_offset(desc);
9060                 asm volatile(
9061 #ifdef CONFIG_X86_64
9062                         "mov %%" _ASM_SP ", %[sp]\n\t"
9063                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9064                         "push $%c[ss]\n\t"
9065                         "push %[sp]\n\t"
9066 #endif
9067                         "pushf\n\t"
9068                         __ASM_SIZE(push) " $%c[cs]\n\t"
9069                         "call *%[entry]\n\t"
9070                         :
9071 #ifdef CONFIG_X86_64
9072                         [sp]"=&r"(tmp),
9073 #endif
9074                         ASM_CALL_CONSTRAINT
9075                         :
9076                         [entry]"r"(entry),
9077                         [ss]"i"(__KERNEL_DS),
9078                         [cs]"i"(__KERNEL_CS)
9079                         );
9080         }
9081 }
9082 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9083
9084 static bool vmx_has_high_real_mode_segbase(void)
9085 {
9086         return enable_unrestricted_guest || emulate_invalid_guest_state;
9087 }
9088
9089 static bool vmx_mpx_supported(void)
9090 {
9091         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9092                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9093 }
9094
9095 static bool vmx_xsaves_supported(void)
9096 {
9097         return vmcs_config.cpu_based_2nd_exec_ctrl &
9098                 SECONDARY_EXEC_XSAVES;
9099 }
9100
9101 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9102 {
9103         u32 exit_intr_info;
9104         bool unblock_nmi;
9105         u8 vector;
9106         bool idtv_info_valid;
9107
9108         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9109
9110         if (vmx->loaded_vmcs->nmi_known_unmasked)
9111                 return;
9112         /*
9113          * Can't use vmx->exit_intr_info since we're not sure what
9114          * the exit reason is.
9115          */
9116         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9117         unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9118         vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9119         /*
9120          * SDM 3: 27.7.1.2 (September 2008)
9121          * Re-set bit "block by NMI" before VM entry if vmexit caused by
9122          * a guest IRET fault.
9123          * SDM 3: 23.2.2 (September 2008)
9124          * Bit 12 is undefined in any of the following cases:
9125          *  If the VM exit sets the valid bit in the IDT-vectoring
9126          *   information field.
9127          *  If the VM exit is due to a double fault.
9128          */
9129         if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9130             vector != DF_VECTOR && !idtv_info_valid)
9131                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9132                               GUEST_INTR_STATE_NMI);
9133         else
9134                 vmx->loaded_vmcs->nmi_known_unmasked =
9135                         !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9136                           & GUEST_INTR_STATE_NMI);
9137 }
9138
9139 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9140                                       u32 idt_vectoring_info,
9141                                       int instr_len_field,
9142                                       int error_code_field)
9143 {
9144         u8 vector;
9145         int type;
9146         bool idtv_info_valid;
9147
9148         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9149
9150         vcpu->arch.nmi_injected = false;
9151         kvm_clear_exception_queue(vcpu);
9152         kvm_clear_interrupt_queue(vcpu);
9153
9154         if (!idtv_info_valid)
9155                 return;
9156
9157         kvm_make_request(KVM_REQ_EVENT, vcpu);
9158
9159         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9160         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9161
9162         switch (type) {
9163         case INTR_TYPE_NMI_INTR:
9164                 vcpu->arch.nmi_injected = true;
9165                 /*
9166                  * SDM 3: 27.7.1.2 (September 2008)
9167                  * Clear bit "block by NMI" before VM entry if a NMI
9168                  * delivery faulted.
9169                  */
9170                 vmx_set_nmi_mask(vcpu, false);
9171                 break;
9172         case INTR_TYPE_SOFT_EXCEPTION:
9173                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9174                 /* fall through */
9175         case INTR_TYPE_HARD_EXCEPTION:
9176                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9177                         u32 err = vmcs_read32(error_code_field);
9178                         kvm_requeue_exception_e(vcpu, vector, err);
9179                 } else
9180                         kvm_requeue_exception(vcpu, vector);
9181                 break;
9182         case INTR_TYPE_SOFT_INTR:
9183                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9184                 /* fall through */
9185         case INTR_TYPE_EXT_INTR:
9186                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9187                 break;
9188         default:
9189                 break;
9190         }
9191 }
9192
9193 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9194 {
9195         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9196                                   VM_EXIT_INSTRUCTION_LEN,
9197                                   IDT_VECTORING_ERROR_CODE);
9198 }
9199
9200 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9201 {
9202         __vmx_complete_interrupts(vcpu,
9203                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9204                                   VM_ENTRY_INSTRUCTION_LEN,
9205                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
9206
9207         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9208 }
9209
9210 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9211 {
9212         int i, nr_msrs;
9213         struct perf_guest_switch_msr *msrs;
9214
9215         msrs = perf_guest_get_msrs(&nr_msrs);
9216
9217         if (!msrs)
9218                 return;
9219
9220         for (i = 0; i < nr_msrs; i++)
9221                 if (msrs[i].host == msrs[i].guest)
9222                         clear_atomic_switch_msr(vmx, msrs[i].msr);
9223                 else
9224                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9225                                         msrs[i].host);
9226 }
9227
9228 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9229 {
9230         struct vcpu_vmx *vmx = to_vmx(vcpu);
9231         u64 tscl;
9232         u32 delta_tsc;
9233
9234         if (vmx->hv_deadline_tsc == -1)
9235                 return;
9236
9237         tscl = rdtsc();
9238         if (vmx->hv_deadline_tsc > tscl)
9239                 /* sure to be 32 bit only because checked on set_hv_timer */
9240                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9241                         cpu_preemption_timer_multi);
9242         else
9243                 delta_tsc = 0;
9244
9245         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9246 }
9247
9248 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9249 {
9250         struct vcpu_vmx *vmx = to_vmx(vcpu);
9251         unsigned long debugctlmsr, cr3, cr4;
9252
9253         /* Don't enter VMX if guest state is invalid, let the exit handler
9254            start emulation until we arrive back to a valid state */
9255         if (vmx->emulation_required)
9256                 return;
9257
9258         if (vmx->ple_window_dirty) {
9259                 vmx->ple_window_dirty = false;
9260                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9261         }
9262
9263         if (vmx->nested.sync_shadow_vmcs) {
9264                 copy_vmcs12_to_shadow(vmx);
9265                 vmx->nested.sync_shadow_vmcs = false;
9266         }
9267
9268         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9269                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9270         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9271                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9272
9273         cr3 = __get_current_cr3_fast();
9274         if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9275                 vmcs_writel(HOST_CR3, cr3);
9276                 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9277         }
9278
9279         cr4 = cr4_read_shadow();
9280         if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9281                 vmcs_writel(HOST_CR4, cr4);
9282                 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9283         }
9284
9285         /* When single-stepping over STI and MOV SS, we must clear the
9286          * corresponding interruptibility bits in the guest state. Otherwise
9287          * vmentry fails as it then expects bit 14 (BS) in pending debug
9288          * exceptions being set, but that's not correct for the guest debugging
9289          * case. */
9290         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9291                 vmx_set_interrupt_shadow(vcpu, 0);
9292
9293         if (static_cpu_has(X86_FEATURE_PKU) &&
9294             kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9295             vcpu->arch.pkru != vmx->host_pkru)
9296                 __write_pkru(vcpu->arch.pkru);
9297
9298         atomic_switch_perf_msrs(vmx);
9299         debugctlmsr = get_debugctlmsr();
9300
9301         vmx_arm_hv_timer(vcpu);
9302
9303         vmx->__launched = vmx->loaded_vmcs->launched;
9304         asm(
9305                 /* Store host registers */
9306                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9307                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9308                 "push %%" _ASM_CX " \n\t"
9309                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9310                 "je 1f \n\t"
9311                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9312                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9313                 "1: \n\t"
9314                 /* Reload cr2 if changed */
9315                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9316                 "mov %%cr2, %%" _ASM_DX " \n\t"
9317                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9318                 "je 2f \n\t"
9319                 "mov %%" _ASM_AX", %%cr2 \n\t"
9320                 "2: \n\t"
9321                 /* Check if vmlaunch of vmresume is needed */
9322                 "cmpl $0, %c[launched](%0) \n\t"
9323                 /* Load guest registers.  Don't clobber flags. */
9324                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9325                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9326                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9327                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9328                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9329                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9330 #ifdef CONFIG_X86_64
9331                 "mov %c[r8](%0),  %%r8  \n\t"
9332                 "mov %c[r9](%0),  %%r9  \n\t"
9333                 "mov %c[r10](%0), %%r10 \n\t"
9334                 "mov %c[r11](%0), %%r11 \n\t"
9335                 "mov %c[r12](%0), %%r12 \n\t"
9336                 "mov %c[r13](%0), %%r13 \n\t"
9337                 "mov %c[r14](%0), %%r14 \n\t"
9338                 "mov %c[r15](%0), %%r15 \n\t"
9339 #endif
9340                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9341
9342                 /* Enter guest mode */
9343                 "jne 1f \n\t"
9344                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9345                 "jmp 2f \n\t"
9346                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9347                 "2: "
9348                 /* Save guest registers, load host registers, keep flags */
9349                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9350                 "pop %0 \n\t"
9351                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9352                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9353                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9354                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9355                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9356                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9357                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9358 #ifdef CONFIG_X86_64
9359                 "mov %%r8,  %c[r8](%0) \n\t"
9360                 "mov %%r9,  %c[r9](%0) \n\t"
9361                 "mov %%r10, %c[r10](%0) \n\t"
9362                 "mov %%r11, %c[r11](%0) \n\t"
9363                 "mov %%r12, %c[r12](%0) \n\t"
9364                 "mov %%r13, %c[r13](%0) \n\t"
9365                 "mov %%r14, %c[r14](%0) \n\t"
9366                 "mov %%r15, %c[r15](%0) \n\t"
9367 #endif
9368                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9369                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9370
9371                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9372                 "setbe %c[fail](%0) \n\t"
9373                 ".pushsection .rodata \n\t"
9374                 ".global vmx_return \n\t"
9375                 "vmx_return: " _ASM_PTR " 2b \n\t"
9376                 ".popsection"
9377               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9378                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9379                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9380                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9381                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9382                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9383                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9384                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9385                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9386                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9387                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9388 #ifdef CONFIG_X86_64
9389                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9390                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9391                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9392                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9393                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9394                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9395                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9396                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9397 #endif
9398                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9399                 [wordsize]"i"(sizeof(ulong))
9400               : "cc", "memory"
9401 #ifdef CONFIG_X86_64
9402                 , "rax", "rbx", "rdi", "rsi"
9403                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9404 #else
9405                 , "eax", "ebx", "edi", "esi"
9406 #endif
9407               );
9408
9409         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9410         if (debugctlmsr)
9411                 update_debugctlmsr(debugctlmsr);
9412
9413 #ifndef CONFIG_X86_64
9414         /*
9415          * The sysexit path does not restore ds/es, so we must set them to
9416          * a reasonable value ourselves.
9417          *
9418          * We can't defer this to vmx_load_host_state() since that function
9419          * may be executed in interrupt context, which saves and restore segments
9420          * around it, nullifying its effect.
9421          */
9422         loadsegment(ds, __USER_DS);
9423         loadsegment(es, __USER_DS);
9424 #endif
9425
9426         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9427                                   | (1 << VCPU_EXREG_RFLAGS)
9428                                   | (1 << VCPU_EXREG_PDPTR)
9429                                   | (1 << VCPU_EXREG_SEGMENTS)
9430                                   | (1 << VCPU_EXREG_CR3));
9431         vcpu->arch.regs_dirty = 0;
9432
9433         /*
9434          * eager fpu is enabled if PKEY is supported and CR4 is switched
9435          * back on host, so it is safe to read guest PKRU from current
9436          * XSAVE.
9437          */
9438         if (static_cpu_has(X86_FEATURE_PKU) &&
9439             kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
9440                 vcpu->arch.pkru = __read_pkru();
9441                 if (vcpu->arch.pkru != vmx->host_pkru)
9442                         __write_pkru(vmx->host_pkru);
9443         }
9444
9445         /*
9446          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9447          * we did not inject a still-pending event to L1 now because of
9448          * nested_run_pending, we need to re-enable this bit.
9449          */
9450         if (vmx->nested.nested_run_pending)
9451                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9452
9453         vmx->nested.nested_run_pending = 0;
9454         vmx->idt_vectoring_info = 0;
9455
9456         vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
9457         if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9458                 return;
9459
9460         vmx->loaded_vmcs->launched = 1;
9461         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9462
9463         vmx_complete_atomic_exit(vmx);
9464         vmx_recover_nmi_blocking(vmx);
9465         vmx_complete_interrupts(vmx);
9466 }
9467 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9468
9469 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9470 {
9471         struct vcpu_vmx *vmx = to_vmx(vcpu);
9472         int cpu;
9473
9474         if (vmx->loaded_vmcs == vmcs)
9475                 return;
9476
9477         cpu = get_cpu();
9478         vmx->loaded_vmcs = vmcs;
9479         vmx_vcpu_put(vcpu);
9480         vmx_vcpu_load(vcpu, cpu);
9481         vcpu->cpu = cpu;
9482         put_cpu();
9483 }
9484
9485 /*
9486  * Ensure that the current vmcs of the logical processor is the
9487  * vmcs01 of the vcpu before calling free_nested().
9488  */
9489 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9490 {
9491        struct vcpu_vmx *vmx = to_vmx(vcpu);
9492        int r;
9493
9494        r = vcpu_load(vcpu);
9495        BUG_ON(r);
9496        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9497        free_nested(vmx);
9498        vcpu_put(vcpu);
9499 }
9500
9501 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9502 {
9503         struct vcpu_vmx *vmx = to_vmx(vcpu);
9504
9505         if (enable_pml)
9506                 vmx_destroy_pml_buffer(vmx);
9507         free_vpid(vmx->vpid);
9508         leave_guest_mode(vcpu);
9509         vmx_free_vcpu_nested(vcpu);
9510         free_loaded_vmcs(vmx->loaded_vmcs);
9511         kfree(vmx->guest_msrs);
9512         kvm_vcpu_uninit(vcpu);
9513         kmem_cache_free(kvm_vcpu_cache, vmx);
9514 }
9515
9516 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9517 {
9518         int err;
9519         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9520         int cpu;
9521
9522         if (!vmx)
9523                 return ERR_PTR(-ENOMEM);
9524
9525         vmx->vpid = allocate_vpid();
9526
9527         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9528         if (err)
9529                 goto free_vcpu;
9530
9531         err = -ENOMEM;
9532
9533         /*
9534          * If PML is turned on, failure on enabling PML just results in failure
9535          * of creating the vcpu, therefore we can simplify PML logic (by
9536          * avoiding dealing with cases, such as enabling PML partially on vcpus
9537          * for the guest, etc.
9538          */
9539         if (enable_pml) {
9540                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9541                 if (!vmx->pml_pg)
9542                         goto uninit_vcpu;
9543         }
9544
9545         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9546         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9547                      > PAGE_SIZE);
9548
9549         if (!vmx->guest_msrs)
9550                 goto free_pml;
9551
9552         vmx->loaded_vmcs = &vmx->vmcs01;
9553         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9554         vmx->loaded_vmcs->shadow_vmcs = NULL;
9555         if (!vmx->loaded_vmcs->vmcs)
9556                 goto free_msrs;
9557         loaded_vmcs_init(vmx->loaded_vmcs);
9558
9559         cpu = get_cpu();
9560         vmx_vcpu_load(&vmx->vcpu, cpu);
9561         vmx->vcpu.cpu = cpu;
9562         err = vmx_vcpu_setup(vmx);
9563         vmx_vcpu_put(&vmx->vcpu);
9564         put_cpu();
9565         if (err)
9566                 goto free_vmcs;
9567         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9568                 err = alloc_apic_access_page(kvm);
9569                 if (err)
9570                         goto free_vmcs;
9571         }
9572
9573         if (enable_ept) {
9574                 if (!kvm->arch.ept_identity_map_addr)
9575                         kvm->arch.ept_identity_map_addr =
9576                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9577                 err = init_rmode_identity_map(kvm);
9578                 if (err)
9579                         goto free_vmcs;
9580         }
9581
9582         if (nested) {
9583                 nested_vmx_setup_ctls_msrs(vmx);
9584                 vmx->nested.vpid02 = allocate_vpid();
9585         }
9586
9587         vmx->nested.posted_intr_nv = -1;
9588         vmx->nested.current_vmptr = -1ull;
9589
9590         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9591
9592         /*
9593          * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9594          * or POSTED_INTR_WAKEUP_VECTOR.
9595          */
9596         vmx->pi_desc.nv = POSTED_INTR_VECTOR;
9597         vmx->pi_desc.sn = 1;
9598
9599         return &vmx->vcpu;
9600
9601 free_vmcs:
9602         free_vpid(vmx->nested.vpid02);
9603         free_loaded_vmcs(vmx->loaded_vmcs);
9604 free_msrs:
9605         kfree(vmx->guest_msrs);
9606 free_pml:
9607         vmx_destroy_pml_buffer(vmx);
9608 uninit_vcpu:
9609         kvm_vcpu_uninit(&vmx->vcpu);
9610 free_vcpu:
9611         free_vpid(vmx->vpid);
9612         kmem_cache_free(kvm_vcpu_cache, vmx);
9613         return ERR_PTR(err);
9614 }
9615
9616 static void __init vmx_check_processor_compat(void *rtn)
9617 {
9618         struct vmcs_config vmcs_conf;
9619
9620         *(int *)rtn = 0;
9621         if (setup_vmcs_config(&vmcs_conf) < 0)
9622                 *(int *)rtn = -EIO;
9623         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9624                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9625                                 smp_processor_id());
9626                 *(int *)rtn = -EIO;
9627         }
9628 }
9629
9630 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9631 {
9632         u8 cache;
9633         u64 ipat = 0;
9634
9635         /* For VT-d and EPT combination
9636          * 1. MMIO: always map as UC
9637          * 2. EPT with VT-d:
9638          *   a. VT-d without snooping control feature: can't guarantee the
9639          *      result, try to trust guest.
9640          *   b. VT-d with snooping control feature: snooping control feature of
9641          *      VT-d engine can guarantee the cache correctness. Just set it
9642          *      to WB to keep consistent with host. So the same as item 3.
9643          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9644          *    consistent with host MTRR
9645          */
9646         if (is_mmio) {
9647                 cache = MTRR_TYPE_UNCACHABLE;
9648                 goto exit;
9649         }
9650
9651         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9652                 ipat = VMX_EPT_IPAT_BIT;
9653                 cache = MTRR_TYPE_WRBACK;
9654                 goto exit;
9655         }
9656
9657         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9658                 ipat = VMX_EPT_IPAT_BIT;
9659                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9660                         cache = MTRR_TYPE_WRBACK;
9661                 else
9662                         cache = MTRR_TYPE_UNCACHABLE;
9663                 goto exit;
9664         }
9665
9666         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9667
9668 exit:
9669         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9670 }
9671
9672 static int vmx_get_lpage_level(void)
9673 {
9674         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9675                 return PT_DIRECTORY_LEVEL;
9676         else
9677                 /* For shadow and EPT supported 1GB page */
9678                 return PT_PDPE_LEVEL;
9679 }
9680
9681 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9682 {
9683         /*
9684          * These bits in the secondary execution controls field
9685          * are dynamic, the others are mostly based on the hypervisor
9686          * architecture and the guest's CPUID.  Do not touch the
9687          * dynamic bits.
9688          */
9689         u32 mask =
9690                 SECONDARY_EXEC_SHADOW_VMCS |
9691                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9692                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9693
9694         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9695
9696         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9697                      (new_ctl & ~mask) | (cur_ctl & mask));
9698 }
9699
9700 /*
9701  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9702  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9703  */
9704 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9705 {
9706         struct vcpu_vmx *vmx = to_vmx(vcpu);
9707         struct kvm_cpuid_entry2 *entry;
9708
9709         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9710         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9711
9712 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9713         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9714                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9715 } while (0)
9716
9717         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9718         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9719         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9720         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9721         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9722         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9723         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9724         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9725         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9726         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9727         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9728         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9729         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9730         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9731         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9732
9733         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9734         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9735         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9736         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9737         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9738         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9739         cr4_fixed1_update(bit(11),            ecx, bit(2));
9740
9741 #undef cr4_fixed1_update
9742 }
9743
9744 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9745 {
9746         struct vcpu_vmx *vmx = to_vmx(vcpu);
9747
9748         if (cpu_has_secondary_exec_ctrls()) {
9749                 vmx_compute_secondary_exec_control(vmx);
9750                 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
9751         }
9752
9753         if (nested_vmx_allowed(vcpu))
9754                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9755                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9756         else
9757                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9758                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9759
9760         if (nested_vmx_allowed(vcpu))
9761                 nested_vmx_cr_fixed1_bits_update(vcpu);
9762 }
9763
9764 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9765 {
9766         if (func == 1 && nested)
9767                 entry->ecx |= bit(X86_FEATURE_VMX);
9768 }
9769
9770 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9771                 struct x86_exception *fault)
9772 {
9773         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9774         struct vcpu_vmx *vmx = to_vmx(vcpu);
9775         u32 exit_reason;
9776         unsigned long exit_qualification = vcpu->arch.exit_qualification;
9777
9778         if (vmx->nested.pml_full) {
9779                 exit_reason = EXIT_REASON_PML_FULL;
9780                 vmx->nested.pml_full = false;
9781                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9782         } else if (fault->error_code & PFERR_RSVD_MASK)
9783                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9784         else
9785                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9786
9787         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9788         vmcs12->guest_physical_address = fault->address;
9789 }
9790
9791 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9792 {
9793         return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
9794 }
9795
9796 /* Callbacks for nested_ept_init_mmu_context: */
9797
9798 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9799 {
9800         /* return the page table to be shadowed - in our case, EPT12 */
9801         return get_vmcs12(vcpu)->ept_pointer;
9802 }
9803
9804 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9805 {
9806         WARN_ON(mmu_is_nested(vcpu));
9807         if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
9808                 return 1;
9809
9810         kvm_mmu_unload(vcpu);
9811         kvm_init_shadow_ept_mmu(vcpu,
9812                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9813                         VMX_EPT_EXECUTE_ONLY_BIT,
9814                         nested_ept_ad_enabled(vcpu));
9815         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9816         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9817         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9818
9819         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9820         return 0;
9821 }
9822
9823 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9824 {
9825         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9826 }
9827
9828 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9829                                             u16 error_code)
9830 {
9831         bool inequality, bit;
9832
9833         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9834         inequality =
9835                 (error_code & vmcs12->page_fault_error_code_mask) !=
9836                  vmcs12->page_fault_error_code_match;
9837         return inequality ^ bit;
9838 }
9839
9840 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9841                 struct x86_exception *fault)
9842 {
9843         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9844
9845         WARN_ON(!is_guest_mode(vcpu));
9846
9847         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
9848                 !to_vmx(vcpu)->nested.nested_run_pending) {
9849                 vmcs12->vm_exit_intr_error_code = fault->error_code;
9850                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9851                                   PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
9852                                   INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
9853                                   fault->address);
9854         } else {
9855                 kvm_inject_page_fault(vcpu, fault);
9856         }
9857 }
9858
9859 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9860                                                struct vmcs12 *vmcs12);
9861
9862 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9863                                         struct vmcs12 *vmcs12)
9864 {
9865         struct vcpu_vmx *vmx = to_vmx(vcpu);
9866         struct page *page;
9867         u64 hpa;
9868
9869         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9870                 /*
9871                  * Translate L1 physical address to host physical
9872                  * address for vmcs02. Keep the page pinned, so this
9873                  * physical address remains valid. We keep a reference
9874                  * to it so we can release it later.
9875                  */
9876                 if (vmx->nested.apic_access_page) { /* shouldn't happen */
9877                         kvm_release_page_dirty(vmx->nested.apic_access_page);
9878                         vmx->nested.apic_access_page = NULL;
9879                 }
9880                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
9881                 /*
9882                  * If translation failed, no matter: This feature asks
9883                  * to exit when accessing the given address, and if it
9884                  * can never be accessed, this feature won't do
9885                  * anything anyway.
9886                  */
9887                 if (!is_error_page(page)) {
9888                         vmx->nested.apic_access_page = page;
9889                         hpa = page_to_phys(vmx->nested.apic_access_page);
9890                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9891                 } else {
9892                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9893                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9894                 }
9895         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9896                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9897                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9898                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9899                 kvm_vcpu_reload_apic_access_page(vcpu);
9900         }
9901
9902         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9903                 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
9904                         kvm_release_page_dirty(vmx->nested.virtual_apic_page);
9905                         vmx->nested.virtual_apic_page = NULL;
9906                 }
9907                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
9908
9909                 /*
9910                  * If translation failed, VM entry will fail because
9911                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9912                  * Failing the vm entry is _not_ what the processor
9913                  * does but it's basically the only possibility we
9914                  * have.  We could still enter the guest if CR8 load
9915                  * exits are enabled, CR8 store exits are enabled, and
9916                  * virtualize APIC access is disabled; in this case
9917                  * the processor would never use the TPR shadow and we
9918                  * could simply clear the bit from the execution
9919                  * control.  But such a configuration is useless, so
9920                  * let's keep the code simple.
9921                  */
9922                 if (!is_error_page(page)) {
9923                         vmx->nested.virtual_apic_page = page;
9924                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9925                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9926                 }
9927         }
9928
9929         if (nested_cpu_has_posted_intr(vmcs12)) {
9930                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9931                         kunmap(vmx->nested.pi_desc_page);
9932                         kvm_release_page_dirty(vmx->nested.pi_desc_page);
9933                         vmx->nested.pi_desc_page = NULL;
9934                 }
9935                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
9936                 if (is_error_page(page))
9937                         return;
9938                 vmx->nested.pi_desc_page = page;
9939                 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
9940                 vmx->nested.pi_desc =
9941                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9942                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9943                         (PAGE_SIZE - 1)));
9944                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9945                         page_to_phys(vmx->nested.pi_desc_page) +
9946                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9947                         (PAGE_SIZE - 1)));
9948         }
9949         if (cpu_has_vmx_msr_bitmap() &&
9950             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9951             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9952                 ;
9953         else
9954                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9955                                 CPU_BASED_USE_MSR_BITMAPS);
9956 }
9957
9958 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9959 {
9960         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9961         struct vcpu_vmx *vmx = to_vmx(vcpu);
9962
9963         if (vcpu->arch.virtual_tsc_khz == 0)
9964                 return;
9965
9966         /* Make sure short timeouts reliably trigger an immediate vmexit.
9967          * hrtimer_start does not guarantee this. */
9968         if (preemption_timeout <= 1) {
9969                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9970                 return;
9971         }
9972
9973         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9974         preemption_timeout *= 1000000;
9975         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9976         hrtimer_start(&vmx->nested.preemption_timer,
9977                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9978 }
9979
9980 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9981                                                struct vmcs12 *vmcs12)
9982 {
9983         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9984                 return 0;
9985
9986         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9987             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9988                 return -EINVAL;
9989
9990         return 0;
9991 }
9992
9993 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9994                                                 struct vmcs12 *vmcs12)
9995 {
9996         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9997                 return 0;
9998
9999         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10000                 return -EINVAL;
10001
10002         return 0;
10003 }
10004
10005 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10006                                                 struct vmcs12 *vmcs12)
10007 {
10008         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10009                 return 0;
10010
10011         if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10012                 return -EINVAL;
10013
10014         return 0;
10015 }
10016
10017 /*
10018  * Merge L0's and L1's MSR bitmap, return false to indicate that
10019  * we do not use the hardware.
10020  */
10021 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
10022                                                struct vmcs12 *vmcs12)
10023 {
10024         int msr;
10025         struct page *page;
10026         unsigned long *msr_bitmap_l1;
10027         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
10028
10029         /* This shortcut is ok because we support only x2APIC MSRs so far. */
10030         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
10031                 return false;
10032
10033         page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10034         if (is_error_page(page))
10035                 return false;
10036         msr_bitmap_l1 = (unsigned long *)kmap(page);
10037
10038         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
10039
10040         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
10041                 if (nested_cpu_has_apic_reg_virt(vmcs12))
10042                         for (msr = 0x800; msr <= 0x8ff; msr++)
10043                                 nested_vmx_disable_intercept_for_msr(
10044                                         msr_bitmap_l1, msr_bitmap_l0,
10045                                         msr, MSR_TYPE_R);
10046
10047                 nested_vmx_disable_intercept_for_msr(
10048                                 msr_bitmap_l1, msr_bitmap_l0,
10049                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
10050                                 MSR_TYPE_R | MSR_TYPE_W);
10051
10052                 if (nested_cpu_has_vid(vmcs12)) {
10053                         nested_vmx_disable_intercept_for_msr(
10054                                 msr_bitmap_l1, msr_bitmap_l0,
10055                                 APIC_BASE_MSR + (APIC_EOI >> 4),
10056                                 MSR_TYPE_W);
10057                         nested_vmx_disable_intercept_for_msr(
10058                                 msr_bitmap_l1, msr_bitmap_l0,
10059                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
10060                                 MSR_TYPE_W);
10061                 }
10062         }
10063         kunmap(page);
10064         kvm_release_page_clean(page);
10065
10066         return true;
10067 }
10068
10069 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10070                                            struct vmcs12 *vmcs12)
10071 {
10072         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10073             !nested_cpu_has_apic_reg_virt(vmcs12) &&
10074             !nested_cpu_has_vid(vmcs12) &&
10075             !nested_cpu_has_posted_intr(vmcs12))
10076                 return 0;
10077
10078         /*
10079          * If virtualize x2apic mode is enabled,
10080          * virtualize apic access must be disabled.
10081          */
10082         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10083             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10084                 return -EINVAL;
10085
10086         /*
10087          * If virtual interrupt delivery is enabled,
10088          * we must exit on external interrupts.
10089          */
10090         if (nested_cpu_has_vid(vmcs12) &&
10091            !nested_exit_on_intr(vcpu))
10092                 return -EINVAL;
10093
10094         /*
10095          * bits 15:8 should be zero in posted_intr_nv,
10096          * the descriptor address has been already checked
10097          * in nested_get_vmcs12_pages.
10098          */
10099         if (nested_cpu_has_posted_intr(vmcs12) &&
10100            (!nested_cpu_has_vid(vmcs12) ||
10101             !nested_exit_intr_ack_set(vcpu) ||
10102             vmcs12->posted_intr_nv & 0xff00))
10103                 return -EINVAL;
10104
10105         /* tpr shadow is needed by all apicv features. */
10106         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10107                 return -EINVAL;
10108
10109         return 0;
10110 }
10111
10112 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10113                                        unsigned long count_field,
10114                                        unsigned long addr_field)
10115 {
10116         int maxphyaddr;
10117         u64 count, addr;
10118
10119         if (vmcs12_read_any(vcpu, count_field, &count) ||
10120             vmcs12_read_any(vcpu, addr_field, &addr)) {
10121                 WARN_ON(1);
10122                 return -EINVAL;
10123         }
10124         if (count == 0)
10125                 return 0;
10126         maxphyaddr = cpuid_maxphyaddr(vcpu);
10127         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10128             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10129                 pr_debug_ratelimited(
10130                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10131                         addr_field, maxphyaddr, count, addr);
10132                 return -EINVAL;
10133         }
10134         return 0;
10135 }
10136
10137 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10138                                                 struct vmcs12 *vmcs12)
10139 {
10140         if (vmcs12->vm_exit_msr_load_count == 0 &&
10141             vmcs12->vm_exit_msr_store_count == 0 &&
10142             vmcs12->vm_entry_msr_load_count == 0)
10143                 return 0; /* Fast path */
10144         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10145                                         VM_EXIT_MSR_LOAD_ADDR) ||
10146             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10147                                         VM_EXIT_MSR_STORE_ADDR) ||
10148             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10149                                         VM_ENTRY_MSR_LOAD_ADDR))
10150                 return -EINVAL;
10151         return 0;
10152 }
10153
10154 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10155                                          struct vmcs12 *vmcs12)
10156 {
10157         u64 address = vmcs12->pml_address;
10158         int maxphyaddr = cpuid_maxphyaddr(vcpu);
10159
10160         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10161                 if (!nested_cpu_has_ept(vmcs12) ||
10162                     !IS_ALIGNED(address, 4096)  ||
10163                     address >> maxphyaddr)
10164                         return -EINVAL;
10165         }
10166
10167         return 0;
10168 }
10169
10170 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10171                                        struct vmx_msr_entry *e)
10172 {
10173         /* x2APIC MSR accesses are not allowed */
10174         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10175                 return -EINVAL;
10176         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10177             e->index == MSR_IA32_UCODE_REV)
10178                 return -EINVAL;
10179         if (e->reserved != 0)
10180                 return -EINVAL;
10181         return 0;
10182 }
10183
10184 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10185                                      struct vmx_msr_entry *e)
10186 {
10187         if (e->index == MSR_FS_BASE ||
10188             e->index == MSR_GS_BASE ||
10189             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10190             nested_vmx_msr_check_common(vcpu, e))
10191                 return -EINVAL;
10192         return 0;
10193 }
10194
10195 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10196                                       struct vmx_msr_entry *e)
10197 {
10198         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10199             nested_vmx_msr_check_common(vcpu, e))
10200                 return -EINVAL;
10201         return 0;
10202 }
10203
10204 /*
10205  * Load guest's/host's msr at nested entry/exit.
10206  * return 0 for success, entry index for failure.
10207  */
10208 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10209 {
10210         u32 i;
10211         struct vmx_msr_entry e;
10212         struct msr_data msr;
10213
10214         msr.host_initiated = false;
10215         for (i = 0; i < count; i++) {
10216                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10217                                         &e, sizeof(e))) {
10218                         pr_debug_ratelimited(
10219                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10220                                 __func__, i, gpa + i * sizeof(e));
10221                         goto fail;
10222                 }
10223                 if (nested_vmx_load_msr_check(vcpu, &e)) {
10224                         pr_debug_ratelimited(
10225                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10226                                 __func__, i, e.index, e.reserved);
10227                         goto fail;
10228                 }
10229                 msr.index = e.index;
10230                 msr.data = e.value;
10231                 if (kvm_set_msr(vcpu, &msr)) {
10232                         pr_debug_ratelimited(
10233                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10234                                 __func__, i, e.index, e.value);
10235                         goto fail;
10236                 }
10237         }
10238         return 0;
10239 fail:
10240         return i + 1;
10241 }
10242
10243 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10244 {
10245         u32 i;
10246         struct vmx_msr_entry e;
10247
10248         for (i = 0; i < count; i++) {
10249                 struct msr_data msr_info;
10250                 if (kvm_vcpu_read_guest(vcpu,
10251                                         gpa + i * sizeof(e),
10252                                         &e, 2 * sizeof(u32))) {
10253                         pr_debug_ratelimited(
10254                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10255                                 __func__, i, gpa + i * sizeof(e));
10256                         return -EINVAL;
10257                 }
10258                 if (nested_vmx_store_msr_check(vcpu, &e)) {
10259                         pr_debug_ratelimited(
10260                                 "%s check failed (%u, 0x%x, 0x%x)\n",
10261                                 __func__, i, e.index, e.reserved);
10262                         return -EINVAL;
10263                 }
10264                 msr_info.host_initiated = false;
10265                 msr_info.index = e.index;
10266                 if (kvm_get_msr(vcpu, &msr_info)) {
10267                         pr_debug_ratelimited(
10268                                 "%s cannot read MSR (%u, 0x%x)\n",
10269                                 __func__, i, e.index);
10270                         return -EINVAL;
10271                 }
10272                 if (kvm_vcpu_write_guest(vcpu,
10273                                          gpa + i * sizeof(e) +
10274                                              offsetof(struct vmx_msr_entry, value),
10275                                          &msr_info.data, sizeof(msr_info.data))) {
10276                         pr_debug_ratelimited(
10277                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10278                                 __func__, i, e.index, msr_info.data);
10279                         return -EINVAL;
10280                 }
10281         }
10282         return 0;
10283 }
10284
10285 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10286 {
10287         unsigned long invalid_mask;
10288
10289         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10290         return (val & invalid_mask) == 0;
10291 }
10292
10293 /*
10294  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10295  * emulating VM entry into a guest with EPT enabled.
10296  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10297  * is assigned to entry_failure_code on failure.
10298  */
10299 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10300                                u32 *entry_failure_code)
10301 {
10302         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10303                 if (!nested_cr3_valid(vcpu, cr3)) {
10304                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10305                         return 1;
10306                 }
10307
10308                 /*
10309                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10310                  * must not be dereferenced.
10311                  */
10312                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10313                     !nested_ept) {
10314                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10315                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
10316                                 return 1;
10317                         }
10318                 }
10319
10320                 vcpu->arch.cr3 = cr3;
10321                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10322         }
10323
10324         kvm_mmu_reset_context(vcpu);
10325         return 0;
10326 }
10327
10328 /*
10329  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10330  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10331  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10332  * guest in a way that will both be appropriate to L1's requests, and our
10333  * needs. In addition to modifying the active vmcs (which is vmcs02), this
10334  * function also has additional necessary side-effects, like setting various
10335  * vcpu->arch fields.
10336  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10337  * is assigned to entry_failure_code on failure.
10338  */
10339 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10340                           bool from_vmentry, u32 *entry_failure_code)
10341 {
10342         struct vcpu_vmx *vmx = to_vmx(vcpu);
10343         u32 exec_control, vmcs12_exec_ctrl;
10344
10345         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10346         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10347         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10348         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10349         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10350         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10351         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10352         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10353         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10354         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10355         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10356         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10357         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10358         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10359         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10360         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10361         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10362         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10363         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10364         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10365         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10366         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10367         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10368         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10369         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10370         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10371         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10372         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10373         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10374         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10375         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10376         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10377         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10378         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10379         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10380         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10381
10382         if (from_vmentry &&
10383             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10384                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10385                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10386         } else {
10387                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10388                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10389         }
10390         if (from_vmentry) {
10391                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10392                              vmcs12->vm_entry_intr_info_field);
10393                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10394                              vmcs12->vm_entry_exception_error_code);
10395                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10396                              vmcs12->vm_entry_instruction_len);
10397                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10398                              vmcs12->guest_interruptibility_info);
10399                 vmx->loaded_vmcs->nmi_known_unmasked =
10400                         !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
10401         } else {
10402                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10403         }
10404         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10405         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10406         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10407                 vmcs12->guest_pending_dbg_exceptions);
10408         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10409         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10410
10411         if (nested_cpu_has_xsaves(vmcs12))
10412                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10413         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10414
10415         exec_control = vmcs12->pin_based_vm_exec_control;
10416
10417         /* Preemption timer setting is only taken from vmcs01.  */
10418         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10419         exec_control |= vmcs_config.pin_based_exec_ctrl;
10420         if (vmx->hv_deadline_tsc == -1)
10421                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10422
10423         /* Posted interrupts setting is only taken from vmcs12.  */
10424         if (nested_cpu_has_posted_intr(vmcs12)) {
10425                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10426                 vmx->nested.pi_pending = false;
10427                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10428         } else {
10429                 exec_control &= ~PIN_BASED_POSTED_INTR;
10430         }
10431
10432         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10433
10434         vmx->nested.preemption_timer_expired = false;
10435         if (nested_cpu_has_preemption_timer(vmcs12))
10436                 vmx_start_preemption_timer(vcpu);
10437
10438         /*
10439          * Whether page-faults are trapped is determined by a combination of
10440          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10441          * If enable_ept, L0 doesn't care about page faults and we should
10442          * set all of these to L1's desires. However, if !enable_ept, L0 does
10443          * care about (at least some) page faults, and because it is not easy
10444          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10445          * to exit on each and every L2 page fault. This is done by setting
10446          * MASK=MATCH=0 and (see below) EB.PF=1.
10447          * Note that below we don't need special code to set EB.PF beyond the
10448          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10449          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10450          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10451          */
10452         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10453                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10454         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10455                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10456
10457         if (cpu_has_secondary_exec_ctrls()) {
10458                 exec_control = vmx->secondary_exec_control;
10459
10460                 /* Take the following fields only from vmcs12 */
10461                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10462                                   SECONDARY_EXEC_ENABLE_INVPCID |
10463                                   SECONDARY_EXEC_RDTSCP |
10464                                   SECONDARY_EXEC_XSAVES |
10465                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10466                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
10467                                   SECONDARY_EXEC_ENABLE_VMFUNC);
10468                 if (nested_cpu_has(vmcs12,
10469                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10470                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10471                                 ~SECONDARY_EXEC_ENABLE_PML;
10472                         exec_control |= vmcs12_exec_ctrl;
10473                 }
10474
10475                 /* All VMFUNCs are currently emulated through L0 vmexits.  */
10476                 if (exec_control & SECONDARY_EXEC_ENABLE_VMFUNC)
10477                         vmcs_write64(VM_FUNCTION_CONTROL, 0);
10478
10479                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10480                         vmcs_write64(EOI_EXIT_BITMAP0,
10481                                 vmcs12->eoi_exit_bitmap0);
10482                         vmcs_write64(EOI_EXIT_BITMAP1,
10483                                 vmcs12->eoi_exit_bitmap1);
10484                         vmcs_write64(EOI_EXIT_BITMAP2,
10485                                 vmcs12->eoi_exit_bitmap2);
10486                         vmcs_write64(EOI_EXIT_BITMAP3,
10487                                 vmcs12->eoi_exit_bitmap3);
10488                         vmcs_write16(GUEST_INTR_STATUS,
10489                                 vmcs12->guest_intr_status);
10490                 }
10491
10492                 /*
10493                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10494                  * nested_get_vmcs12_pages will either fix it up or
10495                  * remove the VM execution control.
10496                  */
10497                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10498                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10499
10500                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10501         }
10502
10503
10504         /*
10505          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10506          * Some constant fields are set here by vmx_set_constant_host_state().
10507          * Other fields are different per CPU, and will be set later when
10508          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10509          */
10510         vmx_set_constant_host_state(vmx);
10511
10512         /*
10513          * Set the MSR load/store lists to match L0's settings.
10514          */
10515         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10516         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10517         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10518         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10519         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10520
10521         /*
10522          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10523          * entry, but only if the current (host) sp changed from the value
10524          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10525          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10526          * here we just force the write to happen on entry.
10527          */
10528         vmx->host_rsp = 0;
10529
10530         exec_control = vmx_exec_control(vmx); /* L0's desires */
10531         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10532         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10533         exec_control &= ~CPU_BASED_TPR_SHADOW;
10534         exec_control |= vmcs12->cpu_based_vm_exec_control;
10535
10536         /*
10537          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10538          * nested_get_vmcs12_pages can't fix it up, the illegal value
10539          * will result in a VM entry failure.
10540          */
10541         if (exec_control & CPU_BASED_TPR_SHADOW) {
10542                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10543                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10544         } else {
10545 #ifdef CONFIG_X86_64
10546                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
10547                                 CPU_BASED_CR8_STORE_EXITING;
10548 #endif
10549         }
10550
10551         /*
10552          * Merging of IO bitmap not currently supported.
10553          * Rather, exit every time.
10554          */
10555         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10556         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10557
10558         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10559
10560         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10561          * bitwise-or of what L1 wants to trap for L2, and what we want to
10562          * trap. Note that CR0.TS also needs updating - we do this later.
10563          */
10564         update_exception_bitmap(vcpu);
10565         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10566         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10567
10568         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10569          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10570          * bits are further modified by vmx_set_efer() below.
10571          */
10572         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10573
10574         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10575          * emulated by vmx_set_efer(), below.
10576          */
10577         vm_entry_controls_init(vmx,
10578                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10579                         ~VM_ENTRY_IA32E_MODE) |
10580                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10581
10582         if (from_vmentry &&
10583             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10584                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10585                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10586         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10587                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10588         }
10589
10590         set_cr4_guest_host_mask(vmx);
10591
10592         if (from_vmentry &&
10593             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10594                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10595
10596         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10597                 vmcs_write64(TSC_OFFSET,
10598                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10599         else
10600                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10601         if (kvm_has_tsc_control)
10602                 decache_tsc_multiplier(vmx);
10603
10604         if (enable_vpid) {
10605                 /*
10606                  * There is no direct mapping between vpid02 and vpid12, the
10607                  * vpid02 is per-vCPU for L0 and reused while the value of
10608                  * vpid12 is changed w/ one invvpid during nested vmentry.
10609                  * The vpid12 is allocated by L1 for L2, so it will not
10610                  * influence global bitmap(for vpid01 and vpid02 allocation)
10611                  * even if spawn a lot of nested vCPUs.
10612                  */
10613                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10614                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10615                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10616                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10617                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10618                         }
10619                 } else {
10620                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10621                         vmx_flush_tlb(vcpu);
10622                 }
10623
10624         }
10625
10626         if (enable_pml) {
10627                 /*
10628                  * Conceptually we want to copy the PML address and index from
10629                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10630                  * since we always flush the log on each vmexit, this happens
10631                  * to be equivalent to simply resetting the fields in vmcs02.
10632                  */
10633                 ASSERT(vmx->pml_pg);
10634                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10635                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10636         }
10637
10638         if (nested_cpu_has_ept(vmcs12)) {
10639                 if (nested_ept_init_mmu_context(vcpu)) {
10640                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10641                         return 1;
10642                 }
10643         } else if (nested_cpu_has2(vmcs12,
10644                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10645                 vmx_flush_tlb_ept_only(vcpu);
10646         }
10647
10648         /*
10649          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10650          * bits which we consider mandatory enabled.
10651          * The CR0_READ_SHADOW is what L2 should have expected to read given
10652          * the specifications by L1; It's not enough to take
10653          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10654          * have more bits than L1 expected.
10655          */
10656         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10657         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10658
10659         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10660         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10661
10662         if (from_vmentry &&
10663             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10664                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10665         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10666                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10667         else
10668                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10669         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10670         vmx_set_efer(vcpu, vcpu->arch.efer);
10671
10672         /* Shadow page tables on either EPT or shadow page tables. */
10673         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10674                                 entry_failure_code))
10675                 return 1;
10676
10677         if (!enable_ept)
10678                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10679
10680         /*
10681          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10682          */
10683         if (enable_ept) {
10684                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10685                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10686                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10687                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10688         }
10689
10690         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10691         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10692         return 0;
10693 }
10694
10695 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10696 {
10697         struct vcpu_vmx *vmx = to_vmx(vcpu);
10698
10699         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10700             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10701                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10702
10703         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10704                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10705
10706         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10707                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10708
10709         if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
10710                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10711
10712         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10713                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10714
10715         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10716                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10717
10718         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10719                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10720
10721         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10722                                 vmx->nested.nested_vmx_procbased_ctls_low,
10723                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10724             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10725              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10726                                  vmx->nested.nested_vmx_secondary_ctls_low,
10727                                  vmx->nested.nested_vmx_secondary_ctls_high)) ||
10728             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10729                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10730                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10731             !vmx_control_verify(vmcs12->vm_exit_controls,
10732                                 vmx->nested.nested_vmx_exit_ctls_low,
10733                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10734             !vmx_control_verify(vmcs12->vm_entry_controls,
10735                                 vmx->nested.nested_vmx_entry_ctls_low,
10736                                 vmx->nested.nested_vmx_entry_ctls_high))
10737                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10738
10739         if (nested_cpu_has_vmfunc(vmcs12)) {
10740                 if (vmcs12->vm_function_control &
10741                     ~vmx->nested.nested_vmx_vmfunc_controls)
10742                         return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10743
10744                 if (nested_cpu_has_eptp_switching(vmcs12)) {
10745                         if (!nested_cpu_has_ept(vmcs12) ||
10746                             !page_address_valid(vcpu, vmcs12->eptp_list_address))
10747                                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10748                 }
10749         }
10750
10751         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10752                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10753
10754         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10755             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10756             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10757                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10758
10759         return 0;
10760 }
10761
10762 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10763                                   u32 *exit_qual)
10764 {
10765         bool ia32e;
10766
10767         *exit_qual = ENTRY_FAIL_DEFAULT;
10768
10769         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10770             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10771                 return 1;
10772
10773         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10774             vmcs12->vmcs_link_pointer != -1ull) {
10775                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10776                 return 1;
10777         }
10778
10779         /*
10780          * If the load IA32_EFER VM-entry control is 1, the following checks
10781          * are performed on the field for the IA32_EFER MSR:
10782          * - Bits reserved in the IA32_EFER MSR must be 0.
10783          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10784          *   the IA-32e mode guest VM-exit control. It must also be identical
10785          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10786          *   CR0.PG) is 1.
10787          */
10788         if (to_vmx(vcpu)->nested.nested_run_pending &&
10789             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10790                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10791                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10792                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10793                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10794                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10795                         return 1;
10796         }
10797
10798         /*
10799          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10800          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10801          * the values of the LMA and LME bits in the field must each be that of
10802          * the host address-space size VM-exit control.
10803          */
10804         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10805                 ia32e = (vmcs12->vm_exit_controls &
10806                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10807                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10808                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10809                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10810                         return 1;
10811         }
10812
10813         return 0;
10814 }
10815
10816 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10817 {
10818         struct vcpu_vmx *vmx = to_vmx(vcpu);
10819         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10820         struct loaded_vmcs *vmcs02;
10821         u32 msr_entry_idx;
10822         u32 exit_qual;
10823
10824         vmcs02 = nested_get_current_vmcs02(vmx);
10825         if (!vmcs02)
10826                 return -ENOMEM;
10827
10828         enter_guest_mode(vcpu);
10829
10830         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10831                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10832
10833         vmx_switch_vmcs(vcpu, vmcs02);
10834         vmx_segment_cache_clear(vmx);
10835
10836         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10837                 leave_guest_mode(vcpu);
10838                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10839                 nested_vmx_entry_failure(vcpu, vmcs12,
10840                                          EXIT_REASON_INVALID_STATE, exit_qual);
10841                 return 1;
10842         }
10843
10844         nested_get_vmcs12_pages(vcpu, vmcs12);
10845
10846         msr_entry_idx = nested_vmx_load_msr(vcpu,
10847                                             vmcs12->vm_entry_msr_load_addr,
10848                                             vmcs12->vm_entry_msr_load_count);
10849         if (msr_entry_idx) {
10850                 leave_guest_mode(vcpu);
10851                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10852                 nested_vmx_entry_failure(vcpu, vmcs12,
10853                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10854                 return 1;
10855         }
10856
10857         /*
10858          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10859          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10860          * returned as far as L1 is concerned. It will only return (and set
10861          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10862          */
10863         return 0;
10864 }
10865
10866 /*
10867  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10868  * for running an L2 nested guest.
10869  */
10870 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10871 {
10872         struct vmcs12 *vmcs12;
10873         struct vcpu_vmx *vmx = to_vmx(vcpu);
10874         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
10875         u32 exit_qual;
10876         int ret;
10877
10878         if (!nested_vmx_check_permission(vcpu))
10879                 return 1;
10880
10881         if (!nested_vmx_check_vmcs12(vcpu))
10882                 goto out;
10883
10884         vmcs12 = get_vmcs12(vcpu);
10885
10886         if (enable_shadow_vmcs)
10887                 copy_shadow_to_vmcs12(vmx);
10888
10889         /*
10890          * The nested entry process starts with enforcing various prerequisites
10891          * on vmcs12 as required by the Intel SDM, and act appropriately when
10892          * they fail: As the SDM explains, some conditions should cause the
10893          * instruction to fail, while others will cause the instruction to seem
10894          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10895          * To speed up the normal (success) code path, we should avoid checking
10896          * for misconfigurations which will anyway be caught by the processor
10897          * when using the merged vmcs02.
10898          */
10899         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
10900                 nested_vmx_failValid(vcpu,
10901                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
10902                 goto out;
10903         }
10904
10905         if (vmcs12->launch_state == launch) {
10906                 nested_vmx_failValid(vcpu,
10907                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10908                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10909                 goto out;
10910         }
10911
10912         ret = check_vmentry_prereqs(vcpu, vmcs12);
10913         if (ret) {
10914                 nested_vmx_failValid(vcpu, ret);
10915                 goto out;
10916         }
10917
10918         /*
10919          * After this point, the trap flag no longer triggers a singlestep trap
10920          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10921          * This is not 100% correct; for performance reasons, we delegate most
10922          * of the checks on host state to the processor.  If those fail,
10923          * the singlestep trap is missed.
10924          */
10925         skip_emulated_instruction(vcpu);
10926
10927         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10928         if (ret) {
10929                 nested_vmx_entry_failure(vcpu, vmcs12,
10930                                          EXIT_REASON_INVALID_STATE, exit_qual);
10931                 return 1;
10932         }
10933
10934         /*
10935          * We're finally done with prerequisite checking, and can start with
10936          * the nested entry.
10937          */
10938
10939         ret = enter_vmx_non_root_mode(vcpu, true);
10940         if (ret)
10941                 return ret;
10942
10943         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10944                 return kvm_vcpu_halt(vcpu);
10945
10946         vmx->nested.nested_run_pending = 1;
10947
10948         return 1;
10949
10950 out:
10951         return kvm_skip_emulated_instruction(vcpu);
10952 }
10953
10954 /*
10955  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10956  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10957  * This function returns the new value we should put in vmcs12.guest_cr0.
10958  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10959  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10960  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10961  *     didn't trap the bit, because if L1 did, so would L0).
10962  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10963  *     been modified by L2, and L1 knows it. So just leave the old value of
10964  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10965  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10966  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10967  *     changed these bits, and therefore they need to be updated, but L0
10968  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10969  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10970  */
10971 static inline unsigned long
10972 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10973 {
10974         return
10975         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10976         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10977         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10978                         vcpu->arch.cr0_guest_owned_bits));
10979 }
10980
10981 static inline unsigned long
10982 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10983 {
10984         return
10985         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10986         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10987         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10988                         vcpu->arch.cr4_guest_owned_bits));
10989 }
10990
10991 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10992                                        struct vmcs12 *vmcs12)
10993 {
10994         u32 idt_vectoring;
10995         unsigned int nr;
10996
10997         if (vcpu->arch.exception.injected) {
10998                 nr = vcpu->arch.exception.nr;
10999                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11000
11001                 if (kvm_exception_is_soft(nr)) {
11002                         vmcs12->vm_exit_instruction_len =
11003                                 vcpu->arch.event_exit_inst_len;
11004                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11005                 } else
11006                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11007
11008                 if (vcpu->arch.exception.has_error_code) {
11009                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11010                         vmcs12->idt_vectoring_error_code =
11011                                 vcpu->arch.exception.error_code;
11012                 }
11013
11014                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11015         } else if (vcpu->arch.nmi_injected) {
11016                 vmcs12->idt_vectoring_info_field =
11017                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11018         } else if (vcpu->arch.interrupt.pending) {
11019                 nr = vcpu->arch.interrupt.nr;
11020                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11021
11022                 if (vcpu->arch.interrupt.soft) {
11023                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
11024                         vmcs12->vm_entry_instruction_len =
11025                                 vcpu->arch.event_exit_inst_len;
11026                 } else
11027                         idt_vectoring |= INTR_TYPE_EXT_INTR;
11028
11029                 vmcs12->idt_vectoring_info_field = idt_vectoring;
11030         }
11031 }
11032
11033 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11034 {
11035         struct vcpu_vmx *vmx = to_vmx(vcpu);
11036         unsigned long exit_qual;
11037
11038         if (kvm_event_needs_reinjection(vcpu))
11039                 return -EBUSY;
11040
11041         if (vcpu->arch.exception.pending &&
11042                 nested_vmx_check_exception(vcpu, &exit_qual)) {
11043                 if (vmx->nested.nested_run_pending)
11044                         return -EBUSY;
11045                 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11046                 vcpu->arch.exception.pending = false;
11047                 return 0;
11048         }
11049
11050         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11051             vmx->nested.preemption_timer_expired) {
11052                 if (vmx->nested.nested_run_pending)
11053                         return -EBUSY;
11054                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11055                 return 0;
11056         }
11057
11058         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11059                 if (vmx->nested.nested_run_pending)
11060                         return -EBUSY;
11061                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11062                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
11063                                   INTR_INFO_VALID_MASK, 0);
11064                 /*
11065                  * The NMI-triggered VM exit counts as injection:
11066                  * clear this one and block further NMIs.
11067                  */
11068                 vcpu->arch.nmi_pending = 0;
11069                 vmx_set_nmi_mask(vcpu, true);
11070                 return 0;
11071         }
11072
11073         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
11074             nested_exit_on_intr(vcpu)) {
11075                 if (vmx->nested.nested_run_pending)
11076                         return -EBUSY;
11077                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11078                 return 0;
11079         }
11080
11081         vmx_complete_nested_posted_interrupt(vcpu);
11082         return 0;
11083 }
11084
11085 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11086 {
11087         ktime_t remaining =
11088                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11089         u64 value;
11090
11091         if (ktime_to_ns(remaining) <= 0)
11092                 return 0;
11093
11094         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11095         do_div(value, 1000000);
11096         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11097 }
11098
11099 /*
11100  * Update the guest state fields of vmcs12 to reflect changes that
11101  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11102  * VM-entry controls is also updated, since this is really a guest
11103  * state bit.)
11104  */
11105 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11106 {
11107         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11108         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11109
11110         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11111         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11112         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11113
11114         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11115         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11116         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11117         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11118         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11119         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11120         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11121         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11122         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11123         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11124         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11125         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11126         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11127         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11128         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11129         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11130         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11131         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11132         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11133         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11134         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
11135         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
11136         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
11137         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
11138         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
11139         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
11140         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
11141         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
11142         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
11143         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
11144         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
11145         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
11146         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
11147         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
11148         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
11149         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
11150
11151         vmcs12->guest_interruptibility_info =
11152                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
11153         vmcs12->guest_pending_dbg_exceptions =
11154                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
11155         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11156                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
11157         else
11158                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
11159
11160         if (nested_cpu_has_preemption_timer(vmcs12)) {
11161                 if (vmcs12->vm_exit_controls &
11162                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
11163                         vmcs12->vmx_preemption_timer_value =
11164                                 vmx_get_preemption_timer_value(vcpu);
11165                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
11166         }
11167
11168         /*
11169          * In some cases (usually, nested EPT), L2 is allowed to change its
11170          * own CR3 without exiting. If it has changed it, we must keep it.
11171          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11172          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11173          *
11174          * Additionally, restore L2's PDPTR to vmcs12.
11175          */
11176         if (enable_ept) {
11177                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
11178                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
11179                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
11180                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
11181                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
11182         }
11183
11184         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
11185
11186         if (nested_cpu_has_vid(vmcs12))
11187                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
11188
11189         vmcs12->vm_entry_controls =
11190                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
11191                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
11192
11193         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
11194                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
11195                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11196         }
11197
11198         /* TODO: These cannot have changed unless we have MSR bitmaps and
11199          * the relevant bit asks not to trap the change */
11200         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
11201                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
11202         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11203                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
11204         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11205         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11206         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
11207         if (kvm_mpx_supported())
11208                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
11209 }
11210
11211 /*
11212  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11213  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11214  * and this function updates it to reflect the changes to the guest state while
11215  * L2 was running (and perhaps made some exits which were handled directly by L0
11216  * without going back to L1), and to reflect the exit reason.
11217  * Note that we do not have to copy here all VMCS fields, just those that
11218  * could have changed by the L2 guest or the exit - i.e., the guest-state and
11219  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11220  * which already writes to vmcs12 directly.
11221  */
11222 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11223                            u32 exit_reason, u32 exit_intr_info,
11224                            unsigned long exit_qualification)
11225 {
11226         /* update guest state fields: */
11227         sync_vmcs12(vcpu, vmcs12);
11228
11229         /* update exit information fields: */
11230
11231         vmcs12->vm_exit_reason = exit_reason;
11232         vmcs12->exit_qualification = exit_qualification;
11233         vmcs12->vm_exit_intr_info = exit_intr_info;
11234
11235         vmcs12->idt_vectoring_info_field = 0;
11236         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11237         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11238
11239         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11240                 vmcs12->launch_state = 1;
11241
11242                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11243                  * instead of reading the real value. */
11244                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
11245
11246                 /*
11247                  * Transfer the event that L0 or L1 may wanted to inject into
11248                  * L2 to IDT_VECTORING_INFO_FIELD.
11249                  */
11250                 vmcs12_save_pending_event(vcpu, vmcs12);
11251         }
11252
11253         /*
11254          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11255          * preserved above and would only end up incorrectly in L1.
11256          */
11257         vcpu->arch.nmi_injected = false;
11258         kvm_clear_exception_queue(vcpu);
11259         kvm_clear_interrupt_queue(vcpu);
11260 }
11261
11262 /*
11263  * A part of what we need to when the nested L2 guest exits and we want to
11264  * run its L1 parent, is to reset L1's guest state to the host state specified
11265  * in vmcs12.
11266  * This function is to be called not only on normal nested exit, but also on
11267  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11268  * Failures During or After Loading Guest State").
11269  * This function should be called when the active VMCS is L1's (vmcs01).
11270  */
11271 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11272                                    struct vmcs12 *vmcs12)
11273 {
11274         struct kvm_segment seg;
11275         u32 entry_failure_code;
11276
11277         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11278                 vcpu->arch.efer = vmcs12->host_ia32_efer;
11279         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11280                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11281         else
11282                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11283         vmx_set_efer(vcpu, vcpu->arch.efer);
11284
11285         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11286         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11287         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11288         /*
11289          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11290          * actually changed, because vmx_set_cr0 refers to efer set above.
11291          *
11292          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11293          * (KVM doesn't change it);
11294          */
11295         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11296         vmx_set_cr0(vcpu, vmcs12->host_cr0);
11297
11298         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
11299         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11300         vmx_set_cr4(vcpu, vmcs12->host_cr4);
11301
11302         nested_ept_uninit_mmu_context(vcpu);
11303
11304         /*
11305          * Only PDPTE load can fail as the value of cr3 was checked on entry and
11306          * couldn't have changed.
11307          */
11308         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11309                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11310
11311         if (!enable_ept)
11312                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11313
11314         if (enable_vpid) {
11315                 /*
11316                  * Trivially support vpid by letting L2s share their parent
11317                  * L1's vpid. TODO: move to a more elaborate solution, giving
11318                  * each L2 its own vpid and exposing the vpid feature to L1.
11319                  */
11320                 vmx_flush_tlb(vcpu);
11321         }
11322         /* Restore posted intr vector. */
11323         if (nested_cpu_has_posted_intr(vmcs12))
11324                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
11325
11326         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11327         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11328         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11329         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11330         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11331
11332         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
11333         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11334                 vmcs_write64(GUEST_BNDCFGS, 0);
11335
11336         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11337                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11338                 vcpu->arch.pat = vmcs12->host_ia32_pat;
11339         }
11340         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11341                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11342                         vmcs12->host_ia32_perf_global_ctrl);
11343
11344         /* Set L1 segment info according to Intel SDM
11345             27.5.2 Loading Host Segment and Descriptor-Table Registers */
11346         seg = (struct kvm_segment) {
11347                 .base = 0,
11348                 .limit = 0xFFFFFFFF,
11349                 .selector = vmcs12->host_cs_selector,
11350                 .type = 11,
11351                 .present = 1,
11352                 .s = 1,
11353                 .g = 1
11354         };
11355         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11356                 seg.l = 1;
11357         else
11358                 seg.db = 1;
11359         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11360         seg = (struct kvm_segment) {
11361                 .base = 0,
11362                 .limit = 0xFFFFFFFF,
11363                 .type = 3,
11364                 .present = 1,
11365                 .s = 1,
11366                 .db = 1,
11367                 .g = 1
11368         };
11369         seg.selector = vmcs12->host_ds_selector;
11370         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11371         seg.selector = vmcs12->host_es_selector;
11372         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11373         seg.selector = vmcs12->host_ss_selector;
11374         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11375         seg.selector = vmcs12->host_fs_selector;
11376         seg.base = vmcs12->host_fs_base;
11377         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11378         seg.selector = vmcs12->host_gs_selector;
11379         seg.base = vmcs12->host_gs_base;
11380         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11381         seg = (struct kvm_segment) {
11382                 .base = vmcs12->host_tr_base,
11383                 .limit = 0x67,
11384                 .selector = vmcs12->host_tr_selector,
11385                 .type = 11,
11386                 .present = 1
11387         };
11388         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11389
11390         kvm_set_dr(vcpu, 7, 0x400);
11391         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11392
11393         if (cpu_has_vmx_msr_bitmap())
11394                 vmx_set_msr_bitmap(vcpu);
11395
11396         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11397                                 vmcs12->vm_exit_msr_load_count))
11398                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11399 }
11400
11401 /*
11402  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11403  * and modify vmcs12 to make it see what it would expect to see there if
11404  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11405  */
11406 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11407                               u32 exit_intr_info,
11408                               unsigned long exit_qualification)
11409 {
11410         struct vcpu_vmx *vmx = to_vmx(vcpu);
11411         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11412
11413         /* trying to cancel vmlaunch/vmresume is a bug */
11414         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11415
11416         /*
11417          * The only expected VM-instruction error is "VM entry with
11418          * invalid control field(s)." Anything else indicates a
11419          * problem with L0.
11420          */
11421         WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
11422                                    VMXERR_ENTRY_INVALID_CONTROL_FIELD));
11423
11424         leave_guest_mode(vcpu);
11425
11426         if (likely(!vmx->fail)) {
11427                 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11428                                exit_qualification);
11429
11430                 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11431                                          vmcs12->vm_exit_msr_store_count))
11432                         nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11433         }
11434
11435         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11436         vm_entry_controls_reset_shadow(vmx);
11437         vm_exit_controls_reset_shadow(vmx);
11438         vmx_segment_cache_clear(vmx);
11439
11440         /* if no vmcs02 cache requested, remove the one we used */
11441         if (VMCS02_POOL_SIZE == 0)
11442                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11443
11444         /* Update any VMCS fields that might have changed while L2 ran */
11445         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11446         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11447         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11448         if (vmx->hv_deadline_tsc == -1)
11449                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11450                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11451         else
11452                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11453                               PIN_BASED_VMX_PREEMPTION_TIMER);
11454         if (kvm_has_tsc_control)
11455                 decache_tsc_multiplier(vmx);
11456
11457         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11458                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11459                 vmx_set_virtual_x2apic_mode(vcpu,
11460                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11461         } else if (!nested_cpu_has_ept(vmcs12) &&
11462                    nested_cpu_has2(vmcs12,
11463                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11464                 vmx_flush_tlb_ept_only(vcpu);
11465         }
11466
11467         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11468         vmx->host_rsp = 0;
11469
11470         /* Unpin physical memory we referred to in vmcs02 */
11471         if (vmx->nested.apic_access_page) {
11472                 kvm_release_page_dirty(vmx->nested.apic_access_page);
11473                 vmx->nested.apic_access_page = NULL;
11474         }
11475         if (vmx->nested.virtual_apic_page) {
11476                 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11477                 vmx->nested.virtual_apic_page = NULL;
11478         }
11479         if (vmx->nested.pi_desc_page) {
11480                 kunmap(vmx->nested.pi_desc_page);
11481                 kvm_release_page_dirty(vmx->nested.pi_desc_page);
11482                 vmx->nested.pi_desc_page = NULL;
11483                 vmx->nested.pi_desc = NULL;
11484         }
11485
11486         /*
11487          * We are now running in L2, mmu_notifier will force to reload the
11488          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11489          */
11490         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11491
11492         if (enable_shadow_vmcs)
11493                 vmx->nested.sync_shadow_vmcs = true;
11494
11495         /* in case we halted in L2 */
11496         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11497
11498         if (likely(!vmx->fail)) {
11499                 /*
11500                  * TODO: SDM says that with acknowledge interrupt on
11501                  * exit, bit 31 of the VM-exit interrupt information
11502                  * (valid interrupt) is always set to 1 on
11503                  * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11504                  * need kvm_cpu_has_interrupt().  See the commit
11505                  * message for details.
11506                  */
11507                 if (nested_exit_intr_ack_set(vcpu) &&
11508                     exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
11509                     kvm_cpu_has_interrupt(vcpu)) {
11510                         int irq = kvm_cpu_get_interrupt(vcpu);
11511                         WARN_ON(irq < 0);
11512                         vmcs12->vm_exit_intr_info = irq |
11513                                 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11514                 }
11515
11516                 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11517                                                vmcs12->exit_qualification,
11518                                                vmcs12->idt_vectoring_info_field,
11519                                                vmcs12->vm_exit_intr_info,
11520                                                vmcs12->vm_exit_intr_error_code,
11521                                                KVM_ISA_VMX);
11522
11523                 load_vmcs12_host_state(vcpu, vmcs12);
11524
11525                 return;
11526         }
11527
11528         /*
11529          * After an early L2 VM-entry failure, we're now back
11530          * in L1 which thinks it just finished a VMLAUNCH or
11531          * VMRESUME instruction, so we need to set the failure
11532          * flag and the VM-instruction error field of the VMCS
11533          * accordingly.
11534          */
11535         nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
11536         /*
11537          * The emulated instruction was already skipped in
11538          * nested_vmx_run, but the updated RIP was never
11539          * written back to the vmcs01.
11540          */
11541         skip_emulated_instruction(vcpu);
11542         vmx->fail = 0;
11543 }
11544
11545 /*
11546  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11547  */
11548 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11549 {
11550         if (is_guest_mode(vcpu)) {
11551                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11552                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11553         }
11554         free_nested(to_vmx(vcpu));
11555 }
11556
11557 /*
11558  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11559  * 23.7 "VM-entry failures during or after loading guest state" (this also
11560  * lists the acceptable exit-reason and exit-qualification parameters).
11561  * It should only be called before L2 actually succeeded to run, and when
11562  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11563  */
11564 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11565                         struct vmcs12 *vmcs12,
11566                         u32 reason, unsigned long qualification)
11567 {
11568         load_vmcs12_host_state(vcpu, vmcs12);
11569         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11570         vmcs12->exit_qualification = qualification;
11571         nested_vmx_succeed(vcpu);
11572         if (enable_shadow_vmcs)
11573                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11574 }
11575
11576 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11577                                struct x86_instruction_info *info,
11578                                enum x86_intercept_stage stage)
11579 {
11580         return X86EMUL_CONTINUE;
11581 }
11582
11583 #ifdef CONFIG_X86_64
11584 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11585 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11586                                   u64 divisor, u64 *result)
11587 {
11588         u64 low = a << shift, high = a >> (64 - shift);
11589
11590         /* To avoid the overflow on divq */
11591         if (high >= divisor)
11592                 return 1;
11593
11594         /* Low hold the result, high hold rem which is discarded */
11595         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11596             "rm" (divisor), "0" (low), "1" (high));
11597         *result = low;
11598
11599         return 0;
11600 }
11601
11602 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11603 {
11604         struct vcpu_vmx *vmx = to_vmx(vcpu);
11605         u64 tscl = rdtsc();
11606         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11607         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11608
11609         /* Convert to host delta tsc if tsc scaling is enabled */
11610         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11611                         u64_shl_div_u64(delta_tsc,
11612                                 kvm_tsc_scaling_ratio_frac_bits,
11613                                 vcpu->arch.tsc_scaling_ratio,
11614                                 &delta_tsc))
11615                 return -ERANGE;
11616
11617         /*
11618          * If the delta tsc can't fit in the 32 bit after the multi shift,
11619          * we can't use the preemption timer.
11620          * It's possible that it fits on later vmentries, but checking
11621          * on every vmentry is costly so we just use an hrtimer.
11622          */
11623         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11624                 return -ERANGE;
11625
11626         vmx->hv_deadline_tsc = tscl + delta_tsc;
11627         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11628                         PIN_BASED_VMX_PREEMPTION_TIMER);
11629
11630         return delta_tsc == 0;
11631 }
11632
11633 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11634 {
11635         struct vcpu_vmx *vmx = to_vmx(vcpu);
11636         vmx->hv_deadline_tsc = -1;
11637         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11638                         PIN_BASED_VMX_PREEMPTION_TIMER);
11639 }
11640 #endif
11641
11642 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11643 {
11644         if (ple_gap)
11645                 shrink_ple_window(vcpu);
11646 }
11647
11648 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11649                                      struct kvm_memory_slot *slot)
11650 {
11651         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11652         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11653 }
11654
11655 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11656                                        struct kvm_memory_slot *slot)
11657 {
11658         kvm_mmu_slot_set_dirty(kvm, slot);
11659 }
11660
11661 static void vmx_flush_log_dirty(struct kvm *kvm)
11662 {
11663         kvm_flush_pml_buffers(kvm);
11664 }
11665
11666 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11667 {
11668         struct vmcs12 *vmcs12;
11669         struct vcpu_vmx *vmx = to_vmx(vcpu);
11670         gpa_t gpa;
11671         struct page *page = NULL;
11672         u64 *pml_address;
11673
11674         if (is_guest_mode(vcpu)) {
11675                 WARN_ON_ONCE(vmx->nested.pml_full);
11676
11677                 /*
11678                  * Check if PML is enabled for the nested guest.
11679                  * Whether eptp bit 6 is set is already checked
11680                  * as part of A/D emulation.
11681                  */
11682                 vmcs12 = get_vmcs12(vcpu);
11683                 if (!nested_cpu_has_pml(vmcs12))
11684                         return 0;
11685
11686                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11687                         vmx->nested.pml_full = true;
11688                         return 1;
11689                 }
11690
11691                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11692
11693                 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
11694                 if (is_error_page(page))
11695                         return 0;
11696
11697                 pml_address = kmap(page);
11698                 pml_address[vmcs12->guest_pml_index--] = gpa;
11699                 kunmap(page);
11700                 kvm_release_page_clean(page);
11701         }
11702
11703         return 0;
11704 }
11705
11706 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11707                                            struct kvm_memory_slot *memslot,
11708                                            gfn_t offset, unsigned long mask)
11709 {
11710         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11711 }
11712
11713 static void __pi_post_block(struct kvm_vcpu *vcpu)
11714 {
11715         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11716         struct pi_desc old, new;
11717         unsigned int dest;
11718
11719         do {
11720                 old.control = new.control = pi_desc->control;
11721                 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
11722                      "Wakeup handler not enabled while the VCPU is blocked\n");
11723
11724                 dest = cpu_physical_id(vcpu->cpu);
11725
11726                 if (x2apic_enabled())
11727                         new.ndst = dest;
11728                 else
11729                         new.ndst = (dest << 8) & 0xFF00;
11730
11731                 /* set 'NV' to 'notification vector' */
11732                 new.nv = POSTED_INTR_VECTOR;
11733         } while (cmpxchg64(&pi_desc->control, old.control,
11734                            new.control) != old.control);
11735
11736         if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
11737                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11738                 list_del(&vcpu->blocked_vcpu_list);
11739                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11740                 vcpu->pre_pcpu = -1;
11741         }
11742 }
11743
11744 /*
11745  * This routine does the following things for vCPU which is going
11746  * to be blocked if VT-d PI is enabled.
11747  * - Store the vCPU to the wakeup list, so when interrupts happen
11748  *   we can find the right vCPU to wake up.
11749  * - Change the Posted-interrupt descriptor as below:
11750  *      'NDST' <-- vcpu->pre_pcpu
11751  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11752  * - If 'ON' is set during this process, which means at least one
11753  *   interrupt is posted for this vCPU, we cannot block it, in
11754  *   this case, return 1, otherwise, return 0.
11755  *
11756  */
11757 static int pi_pre_block(struct kvm_vcpu *vcpu)
11758 {
11759         unsigned int dest;
11760         struct pi_desc old, new;
11761         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11762
11763         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11764                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11765                 !kvm_vcpu_apicv_active(vcpu))
11766                 return 0;
11767
11768         WARN_ON(irqs_disabled());
11769         local_irq_disable();
11770         if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
11771                 vcpu->pre_pcpu = vcpu->cpu;
11772                 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11773                 list_add_tail(&vcpu->blocked_vcpu_list,
11774                               &per_cpu(blocked_vcpu_on_cpu,
11775                                        vcpu->pre_pcpu));
11776                 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11777         }
11778
11779         do {
11780                 old.control = new.control = pi_desc->control;
11781
11782                 WARN((pi_desc->sn == 1),
11783                      "Warning: SN field of posted-interrupts "
11784                      "is set before blocking\n");
11785
11786                 /*
11787                  * Since vCPU can be preempted during this process,
11788                  * vcpu->cpu could be different with pre_pcpu, we
11789                  * need to set pre_pcpu as the destination of wakeup
11790                  * notification event, then we can find the right vCPU
11791                  * to wakeup in wakeup handler if interrupts happen
11792                  * when the vCPU is in blocked state.
11793                  */
11794                 dest = cpu_physical_id(vcpu->pre_pcpu);
11795
11796                 if (x2apic_enabled())
11797                         new.ndst = dest;
11798                 else
11799                         new.ndst = (dest << 8) & 0xFF00;
11800
11801                 /* set 'NV' to 'wakeup vector' */
11802                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11803         } while (cmpxchg64(&pi_desc->control, old.control,
11804                            new.control) != old.control);
11805
11806         /* We should not block the vCPU if an interrupt is posted for it.  */
11807         if (pi_test_on(pi_desc) == 1)
11808                 __pi_post_block(vcpu);
11809
11810         local_irq_enable();
11811         return (vcpu->pre_pcpu == -1);
11812 }
11813
11814 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11815 {
11816         if (pi_pre_block(vcpu))
11817                 return 1;
11818
11819         if (kvm_lapic_hv_timer_in_use(vcpu))
11820                 kvm_lapic_switch_to_sw_timer(vcpu);
11821
11822         return 0;
11823 }
11824
11825 static void pi_post_block(struct kvm_vcpu *vcpu)
11826 {
11827         if (vcpu->pre_pcpu == -1)
11828                 return;
11829
11830         WARN_ON(irqs_disabled());
11831         local_irq_disable();
11832         __pi_post_block(vcpu);
11833         local_irq_enable();
11834 }
11835
11836 static void vmx_post_block(struct kvm_vcpu *vcpu)
11837 {
11838         if (kvm_x86_ops->set_hv_timer)
11839                 kvm_lapic_switch_to_hv_timer(vcpu);
11840
11841         pi_post_block(vcpu);
11842 }
11843
11844 /*
11845  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11846  *
11847  * @kvm: kvm
11848  * @host_irq: host irq of the interrupt
11849  * @guest_irq: gsi of the interrupt
11850  * @set: set or unset PI
11851  * returns 0 on success, < 0 on failure
11852  */
11853 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11854                               uint32_t guest_irq, bool set)
11855 {
11856         struct kvm_kernel_irq_routing_entry *e;
11857         struct kvm_irq_routing_table *irq_rt;
11858         struct kvm_lapic_irq irq;
11859         struct kvm_vcpu *vcpu;
11860         struct vcpu_data vcpu_info;
11861         int idx, ret = 0;
11862
11863         if (!kvm_arch_has_assigned_device(kvm) ||
11864                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11865                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11866                 return 0;
11867
11868         idx = srcu_read_lock(&kvm->irq_srcu);
11869         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11870         if (guest_irq >= irq_rt->nr_rt_entries ||
11871             hlist_empty(&irq_rt->map[guest_irq])) {
11872                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11873                              guest_irq, irq_rt->nr_rt_entries);
11874                 goto out;
11875         }
11876
11877         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11878                 if (e->type != KVM_IRQ_ROUTING_MSI)
11879                         continue;
11880                 /*
11881                  * VT-d PI cannot support posting multicast/broadcast
11882                  * interrupts to a vCPU, we still use interrupt remapping
11883                  * for these kind of interrupts.
11884                  *
11885                  * For lowest-priority interrupts, we only support
11886                  * those with single CPU as the destination, e.g. user
11887                  * configures the interrupts via /proc/irq or uses
11888                  * irqbalance to make the interrupts single-CPU.
11889                  *
11890                  * We will support full lowest-priority interrupt later.
11891                  */
11892
11893                 kvm_set_msi_irq(kvm, e, &irq);
11894                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11895                         /*
11896                          * Make sure the IRTE is in remapped mode if
11897                          * we don't handle it in posted mode.
11898                          */
11899                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11900                         if (ret < 0) {
11901                                 printk(KERN_INFO
11902                                    "failed to back to remapped mode, irq: %u\n",
11903                                    host_irq);
11904                                 goto out;
11905                         }
11906
11907                         continue;
11908                 }
11909
11910                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11911                 vcpu_info.vector = irq.vector;
11912
11913                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11914                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11915
11916                 if (set)
11917                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11918                 else
11919                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11920
11921                 if (ret < 0) {
11922                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11923                                         __func__);
11924                         goto out;
11925                 }
11926         }
11927
11928         ret = 0;
11929 out:
11930         srcu_read_unlock(&kvm->irq_srcu, idx);
11931         return ret;
11932 }
11933
11934 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11935 {
11936         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11937                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11938                         FEATURE_CONTROL_LMCE;
11939         else
11940                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11941                         ~FEATURE_CONTROL_LMCE;
11942 }
11943
11944 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11945         .cpu_has_kvm_support = cpu_has_kvm_support,
11946         .disabled_by_bios = vmx_disabled_by_bios,
11947         .hardware_setup = hardware_setup,
11948         .hardware_unsetup = hardware_unsetup,
11949         .check_processor_compatibility = vmx_check_processor_compat,
11950         .hardware_enable = hardware_enable,
11951         .hardware_disable = hardware_disable,
11952         .cpu_has_accelerated_tpr = report_flexpriority,
11953         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11954
11955         .vcpu_create = vmx_create_vcpu,
11956         .vcpu_free = vmx_free_vcpu,
11957         .vcpu_reset = vmx_vcpu_reset,
11958
11959         .prepare_guest_switch = vmx_save_host_state,
11960         .vcpu_load = vmx_vcpu_load,
11961         .vcpu_put = vmx_vcpu_put,
11962
11963         .update_bp_intercept = update_exception_bitmap,
11964         .get_msr = vmx_get_msr,
11965         .set_msr = vmx_set_msr,
11966         .get_segment_base = vmx_get_segment_base,
11967         .get_segment = vmx_get_segment,
11968         .set_segment = vmx_set_segment,
11969         .get_cpl = vmx_get_cpl,
11970         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11971         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11972         .decache_cr3 = vmx_decache_cr3,
11973         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11974         .set_cr0 = vmx_set_cr0,
11975         .set_cr3 = vmx_set_cr3,
11976         .set_cr4 = vmx_set_cr4,
11977         .set_efer = vmx_set_efer,
11978         .get_idt = vmx_get_idt,
11979         .set_idt = vmx_set_idt,
11980         .get_gdt = vmx_get_gdt,
11981         .set_gdt = vmx_set_gdt,
11982         .get_dr6 = vmx_get_dr6,
11983         .set_dr6 = vmx_set_dr6,
11984         .set_dr7 = vmx_set_dr7,
11985         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11986         .cache_reg = vmx_cache_reg,
11987         .get_rflags = vmx_get_rflags,
11988         .set_rflags = vmx_set_rflags,
11989
11990         .tlb_flush = vmx_flush_tlb,
11991
11992         .run = vmx_vcpu_run,
11993         .handle_exit = vmx_handle_exit,
11994         .skip_emulated_instruction = skip_emulated_instruction,
11995         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11996         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11997         .patch_hypercall = vmx_patch_hypercall,
11998         .set_irq = vmx_inject_irq,
11999         .set_nmi = vmx_inject_nmi,
12000         .queue_exception = vmx_queue_exception,
12001         .cancel_injection = vmx_cancel_injection,
12002         .interrupt_allowed = vmx_interrupt_allowed,
12003         .nmi_allowed = vmx_nmi_allowed,
12004         .get_nmi_mask = vmx_get_nmi_mask,
12005         .set_nmi_mask = vmx_set_nmi_mask,
12006         .enable_nmi_window = enable_nmi_window,
12007         .enable_irq_window = enable_irq_window,
12008         .update_cr8_intercept = update_cr8_intercept,
12009         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
12010         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12011         .get_enable_apicv = vmx_get_enable_apicv,
12012         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12013         .load_eoi_exitmap = vmx_load_eoi_exitmap,
12014         .apicv_post_state_restore = vmx_apicv_post_state_restore,
12015         .hwapic_irr_update = vmx_hwapic_irr_update,
12016         .hwapic_isr_update = vmx_hwapic_isr_update,
12017         .sync_pir_to_irr = vmx_sync_pir_to_irr,
12018         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12019
12020         .set_tss_addr = vmx_set_tss_addr,
12021         .get_tdp_level = get_ept_level,
12022         .get_mt_mask = vmx_get_mt_mask,
12023
12024         .get_exit_info = vmx_get_exit_info,
12025
12026         .get_lpage_level = vmx_get_lpage_level,
12027
12028         .cpuid_update = vmx_cpuid_update,
12029
12030         .rdtscp_supported = vmx_rdtscp_supported,
12031         .invpcid_supported = vmx_invpcid_supported,
12032
12033         .set_supported_cpuid = vmx_set_supported_cpuid,
12034
12035         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
12036
12037         .write_tsc_offset = vmx_write_tsc_offset,
12038
12039         .set_tdp_cr3 = vmx_set_cr3,
12040
12041         .check_intercept = vmx_check_intercept,
12042         .handle_external_intr = vmx_handle_external_intr,
12043         .mpx_supported = vmx_mpx_supported,
12044         .xsaves_supported = vmx_xsaves_supported,
12045
12046         .check_nested_events = vmx_check_nested_events,
12047
12048         .sched_in = vmx_sched_in,
12049
12050         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
12051         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
12052         .flush_log_dirty = vmx_flush_log_dirty,
12053         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
12054         .write_log_dirty = vmx_write_pml_buffer,
12055
12056         .pre_block = vmx_pre_block,
12057         .post_block = vmx_post_block,
12058
12059         .pmu_ops = &intel_pmu_ops,
12060
12061         .update_pi_irte = vmx_update_pi_irte,
12062
12063 #ifdef CONFIG_X86_64
12064         .set_hv_timer = vmx_set_hv_timer,
12065         .cancel_hv_timer = vmx_cancel_hv_timer,
12066 #endif
12067
12068         .setup_mce = vmx_setup_mce,
12069 };
12070
12071 static int __init vmx_init(void)
12072 {
12073         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
12074                      __alignof__(struct vcpu_vmx), THIS_MODULE);
12075         if (r)
12076                 return r;
12077
12078 #ifdef CONFIG_KEXEC_CORE
12079         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
12080                            crash_vmclear_local_loaded_vmcss);
12081 #endif
12082
12083         return 0;
12084 }
12085
12086 static void __exit vmx_exit(void)
12087 {
12088 #ifdef CONFIG_KEXEC_CORE
12089         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
12090         synchronize_rcu();
12091 #endif
12092
12093         kvm_exit();
12094 }
12095
12096 module_init(vmx_init)
12097 module_exit(vmx_exit)