2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include <linux/nospec.h>
38 #include "kvm_cache_regs.h"
45 #include <asm/virtext.h>
47 #include <asm/fpu/internal.h>
48 #include <asm/perf_event.h>
49 #include <asm/debugreg.h>
50 #include <asm/kexec.h>
52 #include <asm/irq_remapping.h>
53 #include <asm/mmu_context.h>
54 #include <asm/microcode.h>
55 #include <asm/spec-ctrl.h>
60 #define __ex(x) __kvm_handle_fault_on_reboot(x)
61 #define __ex_clear(x, reg) \
62 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
64 MODULE_AUTHOR("Qumranet");
65 MODULE_LICENSE("GPL");
67 static const struct x86_cpu_id vmx_cpu_id[] = {
68 X86_FEATURE_MATCH(X86_FEATURE_VMX),
71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
73 static bool __read_mostly enable_vpid = 1;
74 module_param_named(vpid, enable_vpid, bool, 0444);
76 static bool __read_mostly flexpriority_enabled = 1;
77 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
79 static bool __read_mostly enable_ept = 1;
80 module_param_named(ept, enable_ept, bool, S_IRUGO);
82 static bool __read_mostly enable_unrestricted_guest = 1;
83 module_param_named(unrestricted_guest,
84 enable_unrestricted_guest, bool, S_IRUGO);
86 static bool __read_mostly enable_ept_ad_bits = 1;
87 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
89 static bool __read_mostly emulate_invalid_guest_state = true;
90 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
92 static bool __read_mostly fasteoi = 1;
93 module_param(fasteoi, bool, S_IRUGO);
95 static bool __read_mostly enable_apicv = 1;
96 module_param(enable_apicv, bool, S_IRUGO);
98 static bool __read_mostly enable_shadow_vmcs = 1;
99 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
101 * If nested=1, nested virtualization is supported, i.e., guests may use
102 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
103 * use VMX instructions.
105 static bool __read_mostly nested = 0;
106 module_param(nested, bool, S_IRUGO);
108 static u64 __read_mostly host_xss;
110 static bool __read_mostly enable_pml = 1;
111 module_param_named(pml, enable_pml, bool, S_IRUGO);
115 #define MSR_TYPE_RW 3
117 #define MSR_BITMAP_MODE_X2APIC 1
118 #define MSR_BITMAP_MODE_X2APIC_APICV 2
119 #define MSR_BITMAP_MODE_LM 4
121 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
123 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
124 static int __read_mostly cpu_preemption_timer_multi;
125 static bool __read_mostly enable_preemption_timer = 1;
127 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
130 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
131 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
132 #define KVM_VM_CR0_ALWAYS_ON \
133 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
134 #define KVM_CR4_GUEST_OWNED_BITS \
135 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
136 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
138 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
139 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
141 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
143 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
146 * Hyper-V requires all of these, so mark them as supported even though
147 * they are just treated the same as all-context.
149 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
150 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
151 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
152 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
153 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
156 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
157 * ple_gap: upper bound on the amount of time between two successive
158 * executions of PAUSE in a loop. Also indicate if ple enabled.
159 * According to test, this time is usually smaller than 128 cycles.
160 * ple_window: upper bound on the amount of time a guest is allowed to execute
161 * in a PAUSE loop. Tests indicate that most spinlocks are held for
162 * less than 2^12 cycles
163 * Time is measured based on a counter that runs at the same rate as the TSC,
164 * refer SDM volume 3b section 21.6.13 & 22.1.3.
166 #define KVM_VMX_DEFAULT_PLE_GAP 128
167 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
168 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
169 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
170 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
171 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
173 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
174 module_param(ple_gap, int, S_IRUGO);
176 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
177 module_param(ple_window, int, S_IRUGO);
179 /* Default doubles per-vcpu window every exit. */
180 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
181 module_param(ple_window_grow, int, S_IRUGO);
183 /* Default resets per-vcpu window every exit to ple_window. */
184 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
185 module_param(ple_window_shrink, int, S_IRUGO);
187 /* Default is to compute the maximum so we can never overflow. */
188 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
189 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
190 module_param(ple_window_max, int, S_IRUGO);
192 extern const ulong vmx_return;
194 #define NR_AUTOLOAD_MSRS 8
203 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
204 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
205 * loaded on this CPU (so we can clear them if the CPU goes down).
209 struct vmcs *shadow_vmcs;
212 bool nmi_known_unmasked;
213 unsigned long vmcs_host_cr3; /* May not match real cr3 */
214 unsigned long vmcs_host_cr4; /* May not match real cr4 */
215 /* Support for vnmi-less CPUs */
216 int soft_vnmi_blocked;
218 s64 vnmi_blocked_time;
219 unsigned long *msr_bitmap;
220 struct list_head loaded_vmcss_on_cpu_link;
223 struct shared_msr_entry {
230 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
231 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
232 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
233 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
234 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
235 * More than one of these structures may exist, if L1 runs multiple L2 guests.
236 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
237 * underlying hardware which will be used to run L2.
238 * This structure is packed to ensure that its layout is identical across
239 * machines (necessary for live migration).
240 * If there are changes in this struct, VMCS12_REVISION must be changed.
242 typedef u64 natural_width;
243 struct __packed vmcs12 {
244 /* According to the Intel spec, a VMCS region must start with the
245 * following two fields. Then follow implementation-specific data.
250 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
251 u32 padding[7]; /* room for future expansion */
256 u64 vm_exit_msr_store_addr;
257 u64 vm_exit_msr_load_addr;
258 u64 vm_entry_msr_load_addr;
260 u64 virtual_apic_page_addr;
261 u64 apic_access_addr;
262 u64 posted_intr_desc_addr;
263 u64 vm_function_control;
265 u64 eoi_exit_bitmap0;
266 u64 eoi_exit_bitmap1;
267 u64 eoi_exit_bitmap2;
268 u64 eoi_exit_bitmap3;
269 u64 eptp_list_address;
271 u64 guest_physical_address;
272 u64 vmcs_link_pointer;
274 u64 guest_ia32_debugctl;
277 u64 guest_ia32_perf_global_ctrl;
285 u64 host_ia32_perf_global_ctrl;
286 u64 padding64[8]; /* room for future expansion */
288 * To allow migration of L1 (complete with its L2 guests) between
289 * machines of different natural widths (32 or 64 bit), we cannot have
290 * unsigned long fields with no explict size. We use u64 (aliased
291 * natural_width) instead. Luckily, x86 is little-endian.
293 natural_width cr0_guest_host_mask;
294 natural_width cr4_guest_host_mask;
295 natural_width cr0_read_shadow;
296 natural_width cr4_read_shadow;
297 natural_width cr3_target_value0;
298 natural_width cr3_target_value1;
299 natural_width cr3_target_value2;
300 natural_width cr3_target_value3;
301 natural_width exit_qualification;
302 natural_width guest_linear_address;
303 natural_width guest_cr0;
304 natural_width guest_cr3;
305 natural_width guest_cr4;
306 natural_width guest_es_base;
307 natural_width guest_cs_base;
308 natural_width guest_ss_base;
309 natural_width guest_ds_base;
310 natural_width guest_fs_base;
311 natural_width guest_gs_base;
312 natural_width guest_ldtr_base;
313 natural_width guest_tr_base;
314 natural_width guest_gdtr_base;
315 natural_width guest_idtr_base;
316 natural_width guest_dr7;
317 natural_width guest_rsp;
318 natural_width guest_rip;
319 natural_width guest_rflags;
320 natural_width guest_pending_dbg_exceptions;
321 natural_width guest_sysenter_esp;
322 natural_width guest_sysenter_eip;
323 natural_width host_cr0;
324 natural_width host_cr3;
325 natural_width host_cr4;
326 natural_width host_fs_base;
327 natural_width host_gs_base;
328 natural_width host_tr_base;
329 natural_width host_gdtr_base;
330 natural_width host_idtr_base;
331 natural_width host_ia32_sysenter_esp;
332 natural_width host_ia32_sysenter_eip;
333 natural_width host_rsp;
334 natural_width host_rip;
335 natural_width paddingl[8]; /* room for future expansion */
336 u32 pin_based_vm_exec_control;
337 u32 cpu_based_vm_exec_control;
338 u32 exception_bitmap;
339 u32 page_fault_error_code_mask;
340 u32 page_fault_error_code_match;
341 u32 cr3_target_count;
342 u32 vm_exit_controls;
343 u32 vm_exit_msr_store_count;
344 u32 vm_exit_msr_load_count;
345 u32 vm_entry_controls;
346 u32 vm_entry_msr_load_count;
347 u32 vm_entry_intr_info_field;
348 u32 vm_entry_exception_error_code;
349 u32 vm_entry_instruction_len;
351 u32 secondary_vm_exec_control;
352 u32 vm_instruction_error;
354 u32 vm_exit_intr_info;
355 u32 vm_exit_intr_error_code;
356 u32 idt_vectoring_info_field;
357 u32 idt_vectoring_error_code;
358 u32 vm_exit_instruction_len;
359 u32 vmx_instruction_info;
366 u32 guest_ldtr_limit;
368 u32 guest_gdtr_limit;
369 u32 guest_idtr_limit;
370 u32 guest_es_ar_bytes;
371 u32 guest_cs_ar_bytes;
372 u32 guest_ss_ar_bytes;
373 u32 guest_ds_ar_bytes;
374 u32 guest_fs_ar_bytes;
375 u32 guest_gs_ar_bytes;
376 u32 guest_ldtr_ar_bytes;
377 u32 guest_tr_ar_bytes;
378 u32 guest_interruptibility_info;
379 u32 guest_activity_state;
380 u32 guest_sysenter_cs;
381 u32 host_ia32_sysenter_cs;
382 u32 vmx_preemption_timer_value;
383 u32 padding32[7]; /* room for future expansion */
384 u16 virtual_processor_id;
386 u16 guest_es_selector;
387 u16 guest_cs_selector;
388 u16 guest_ss_selector;
389 u16 guest_ds_selector;
390 u16 guest_fs_selector;
391 u16 guest_gs_selector;
392 u16 guest_ldtr_selector;
393 u16 guest_tr_selector;
394 u16 guest_intr_status;
396 u16 host_es_selector;
397 u16 host_cs_selector;
398 u16 host_ss_selector;
399 u16 host_ds_selector;
400 u16 host_fs_selector;
401 u16 host_gs_selector;
402 u16 host_tr_selector;
406 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
407 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
408 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
410 #define VMCS12_REVISION 0x11e57ed0
413 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
414 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
415 * current implementation, 4K are reserved to avoid future complications.
417 #define VMCS12_SIZE 0x1000
420 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
421 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
424 /* Has the level1 guest done vmxon? */
429 /* The guest-physical address of the current VMCS L1 keeps for L2 */
432 * Cache of the guest's VMCS, existing outside of guest memory.
433 * Loaded from guest memory during VMPTRLD. Flushed to guest
434 * memory during VMCLEAR and VMPTRLD.
436 struct vmcs12 *cached_vmcs12;
438 * Indicates if the shadow vmcs must be updated with the
439 * data hold by vmcs12
441 bool sync_shadow_vmcs;
443 bool change_vmcs01_virtual_x2apic_mode;
444 /* L2 must run next, and mustn't decide to exit to L1. */
445 bool nested_run_pending;
447 struct loaded_vmcs vmcs02;
450 * Guest pages referred to in the vmcs02 with host-physical
451 * pointers, so we must keep them pinned while L2 runs.
453 struct page *apic_access_page;
454 struct page *virtual_apic_page;
455 struct page *pi_desc_page;
456 struct pi_desc *pi_desc;
460 struct hrtimer preemption_timer;
461 bool preemption_timer_expired;
463 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
470 * We only store the "true" versions of the VMX capability MSRs. We
471 * generate the "non-true" versions by setting the must-be-1 bits
472 * according to the SDM.
474 u32 nested_vmx_procbased_ctls_low;
475 u32 nested_vmx_procbased_ctls_high;
476 u32 nested_vmx_secondary_ctls_low;
477 u32 nested_vmx_secondary_ctls_high;
478 u32 nested_vmx_pinbased_ctls_low;
479 u32 nested_vmx_pinbased_ctls_high;
480 u32 nested_vmx_exit_ctls_low;
481 u32 nested_vmx_exit_ctls_high;
482 u32 nested_vmx_entry_ctls_low;
483 u32 nested_vmx_entry_ctls_high;
484 u32 nested_vmx_misc_low;
485 u32 nested_vmx_misc_high;
486 u32 nested_vmx_ept_caps;
487 u32 nested_vmx_vpid_caps;
488 u64 nested_vmx_basic;
489 u64 nested_vmx_cr0_fixed0;
490 u64 nested_vmx_cr0_fixed1;
491 u64 nested_vmx_cr4_fixed0;
492 u64 nested_vmx_cr4_fixed1;
493 u64 nested_vmx_vmcs_enum;
494 u64 nested_vmx_vmfunc_controls;
497 #define POSTED_INTR_ON 0
498 #define POSTED_INTR_SN 1
500 /* Posted-Interrupt Descriptor */
502 u32 pir[8]; /* Posted interrupt requested */
505 /* bit 256 - Outstanding Notification */
507 /* bit 257 - Suppress Notification */
509 /* bit 271:258 - Reserved */
511 /* bit 279:272 - Notification Vector */
513 /* bit 287:280 - Reserved */
515 /* bit 319:288 - Notification Destination */
523 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
525 return test_and_set_bit(POSTED_INTR_ON,
526 (unsigned long *)&pi_desc->control);
529 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
531 return test_and_clear_bit(POSTED_INTR_ON,
532 (unsigned long *)&pi_desc->control);
535 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
537 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
540 static inline void pi_clear_sn(struct pi_desc *pi_desc)
542 return clear_bit(POSTED_INTR_SN,
543 (unsigned long *)&pi_desc->control);
546 static inline void pi_set_sn(struct pi_desc *pi_desc)
548 return set_bit(POSTED_INTR_SN,
549 (unsigned long *)&pi_desc->control);
552 static inline void pi_clear_on(struct pi_desc *pi_desc)
554 clear_bit(POSTED_INTR_ON,
555 (unsigned long *)&pi_desc->control);
558 static inline int pi_test_on(struct pi_desc *pi_desc)
560 return test_bit(POSTED_INTR_ON,
561 (unsigned long *)&pi_desc->control);
564 static inline int pi_test_sn(struct pi_desc *pi_desc)
566 return test_bit(POSTED_INTR_SN,
567 (unsigned long *)&pi_desc->control);
571 struct kvm_vcpu vcpu;
572 unsigned long host_rsp;
576 u32 idt_vectoring_info;
578 struct shared_msr_entry *guest_msrs;
581 unsigned long host_idt_base;
583 u64 msr_host_kernel_gs_base;
584 u64 msr_guest_kernel_gs_base;
587 u64 arch_capabilities;
590 u32 vm_entry_controls_shadow;
591 u32 vm_exit_controls_shadow;
592 u32 secondary_exec_control;
595 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
596 * non-nested (L1) guest, it always points to vmcs01. For a nested
597 * guest (L2), it points to a different VMCS.
599 struct loaded_vmcs vmcs01;
600 struct loaded_vmcs *loaded_vmcs;
601 bool __launched; /* temporary, used in vmx_vcpu_run */
602 struct msr_autoload {
604 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
605 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
609 u16 fs_sel, gs_sel, ldt_sel;
613 int gs_ldt_reload_needed;
614 int fs_reload_needed;
615 u64 msr_host_bndcfgs;
620 struct kvm_segment segs[8];
623 u32 bitmask; /* 4 bits per segment (1 bit per field) */
624 struct kvm_save_segment {
632 bool emulation_required;
636 /* Posted interrupt descriptor */
637 struct pi_desc pi_desc;
639 /* Support for a guest hypervisor (nested VMX) */
640 struct nested_vmx nested;
642 /* Dynamic PLE window. */
644 bool ple_window_dirty;
646 /* Support for PML */
647 #define PML_ENTITY_NUM 512
650 /* apic deadline value in host tsc */
653 u64 current_tsc_ratio;
658 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
659 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
660 * in msr_ia32_feature_control_valid_bits.
662 u64 msr_ia32_feature_control;
663 u64 msr_ia32_feature_control_valid_bits;
666 enum segment_cache_field {
675 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
677 return container_of(vcpu, struct vcpu_vmx, vcpu);
680 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
682 return &(to_vmx(vcpu)->pi_desc);
685 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
686 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
687 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
688 [number##_HIGH] = VMCS12_OFFSET(name)+4
691 static unsigned long shadow_read_only_fields[] = {
693 * We do NOT shadow fields that are modified when L0
694 * traps and emulates any vmx instruction (e.g. VMPTRLD,
695 * VMXON...) executed by L1.
696 * For example, VM_INSTRUCTION_ERROR is read
697 * by L1 if a vmx instruction fails (part of the error path).
698 * Note the code assumes this logic. If for some reason
699 * we start shadowing these fields then we need to
700 * force a shadow sync when L0 emulates vmx instructions
701 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
702 * by nested_vmx_failValid)
706 VM_EXIT_INSTRUCTION_LEN,
707 IDT_VECTORING_INFO_FIELD,
708 IDT_VECTORING_ERROR_CODE,
709 VM_EXIT_INTR_ERROR_CODE,
711 GUEST_LINEAR_ADDRESS,
712 GUEST_PHYSICAL_ADDRESS
714 static int max_shadow_read_only_fields =
715 ARRAY_SIZE(shadow_read_only_fields);
717 static unsigned long shadow_read_write_fields[] = {
724 GUEST_INTERRUPTIBILITY_INFO,
737 CPU_BASED_VM_EXEC_CONTROL,
738 VM_ENTRY_EXCEPTION_ERROR_CODE,
739 VM_ENTRY_INTR_INFO_FIELD,
740 VM_ENTRY_INSTRUCTION_LEN,
741 VM_ENTRY_EXCEPTION_ERROR_CODE,
747 static int max_shadow_read_write_fields =
748 ARRAY_SIZE(shadow_read_write_fields);
750 static const unsigned short vmcs_field_to_offset_table[] = {
751 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
752 FIELD(POSTED_INTR_NV, posted_intr_nv),
753 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
754 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
755 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
756 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
757 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
758 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
759 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
760 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
761 FIELD(GUEST_INTR_STATUS, guest_intr_status),
762 FIELD(GUEST_PML_INDEX, guest_pml_index),
763 FIELD(HOST_ES_SELECTOR, host_es_selector),
764 FIELD(HOST_CS_SELECTOR, host_cs_selector),
765 FIELD(HOST_SS_SELECTOR, host_ss_selector),
766 FIELD(HOST_DS_SELECTOR, host_ds_selector),
767 FIELD(HOST_FS_SELECTOR, host_fs_selector),
768 FIELD(HOST_GS_SELECTOR, host_gs_selector),
769 FIELD(HOST_TR_SELECTOR, host_tr_selector),
770 FIELD64(IO_BITMAP_A, io_bitmap_a),
771 FIELD64(IO_BITMAP_B, io_bitmap_b),
772 FIELD64(MSR_BITMAP, msr_bitmap),
773 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
774 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
775 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
776 FIELD64(TSC_OFFSET, tsc_offset),
777 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
778 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
779 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
780 FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
781 FIELD64(EPT_POINTER, ept_pointer),
782 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
783 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
784 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
785 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
786 FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
787 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
788 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
789 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
790 FIELD64(PML_ADDRESS, pml_address),
791 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
792 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
793 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
794 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
795 FIELD64(GUEST_PDPTR0, guest_pdptr0),
796 FIELD64(GUEST_PDPTR1, guest_pdptr1),
797 FIELD64(GUEST_PDPTR2, guest_pdptr2),
798 FIELD64(GUEST_PDPTR3, guest_pdptr3),
799 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
800 FIELD64(HOST_IA32_PAT, host_ia32_pat),
801 FIELD64(HOST_IA32_EFER, host_ia32_efer),
802 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
803 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
804 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
805 FIELD(EXCEPTION_BITMAP, exception_bitmap),
806 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
807 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
808 FIELD(CR3_TARGET_COUNT, cr3_target_count),
809 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
810 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
811 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
812 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
813 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
814 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
815 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
816 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
817 FIELD(TPR_THRESHOLD, tpr_threshold),
818 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
819 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
820 FIELD(VM_EXIT_REASON, vm_exit_reason),
821 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
822 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
823 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
824 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
825 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
826 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
827 FIELD(GUEST_ES_LIMIT, guest_es_limit),
828 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
829 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
830 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
831 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
832 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
833 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
834 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
835 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
836 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
837 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
838 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
839 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
840 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
841 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
842 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
843 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
844 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
845 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
846 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
847 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
848 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
849 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
850 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
851 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
852 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
853 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
854 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
855 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
856 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
857 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
858 FIELD(EXIT_QUALIFICATION, exit_qualification),
859 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
860 FIELD(GUEST_CR0, guest_cr0),
861 FIELD(GUEST_CR3, guest_cr3),
862 FIELD(GUEST_CR4, guest_cr4),
863 FIELD(GUEST_ES_BASE, guest_es_base),
864 FIELD(GUEST_CS_BASE, guest_cs_base),
865 FIELD(GUEST_SS_BASE, guest_ss_base),
866 FIELD(GUEST_DS_BASE, guest_ds_base),
867 FIELD(GUEST_FS_BASE, guest_fs_base),
868 FIELD(GUEST_GS_BASE, guest_gs_base),
869 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
870 FIELD(GUEST_TR_BASE, guest_tr_base),
871 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
872 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
873 FIELD(GUEST_DR7, guest_dr7),
874 FIELD(GUEST_RSP, guest_rsp),
875 FIELD(GUEST_RIP, guest_rip),
876 FIELD(GUEST_RFLAGS, guest_rflags),
877 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
878 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
879 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
880 FIELD(HOST_CR0, host_cr0),
881 FIELD(HOST_CR3, host_cr3),
882 FIELD(HOST_CR4, host_cr4),
883 FIELD(HOST_FS_BASE, host_fs_base),
884 FIELD(HOST_GS_BASE, host_gs_base),
885 FIELD(HOST_TR_BASE, host_tr_base),
886 FIELD(HOST_GDTR_BASE, host_gdtr_base),
887 FIELD(HOST_IDTR_BASE, host_idtr_base),
888 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
889 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
890 FIELD(HOST_RSP, host_rsp),
891 FIELD(HOST_RIP, host_rip),
894 static inline short vmcs_field_to_offset(unsigned long field)
896 const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
897 unsigned short offset;
899 BUILD_BUG_ON(size > SHRT_MAX);
903 field = array_index_nospec(field, size);
904 offset = vmcs_field_to_offset_table[field];
910 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
912 return to_vmx(vcpu)->nested.cached_vmcs12;
915 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
916 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
917 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
918 static bool vmx_xsaves_supported(void);
919 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
920 static void vmx_set_segment(struct kvm_vcpu *vcpu,
921 struct kvm_segment *var, int seg);
922 static void vmx_get_segment(struct kvm_vcpu *vcpu,
923 struct kvm_segment *var, int seg);
924 static bool guest_state_valid(struct kvm_vcpu *vcpu);
925 static u32 vmx_segment_access_rights(struct kvm_segment *var);
926 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
927 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
928 static int alloc_identity_pagetable(struct kvm *kvm);
929 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
930 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
931 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
933 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
934 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
937 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
938 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
940 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
941 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
943 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
946 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
947 * can find which vCPU should be waken up.
949 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
950 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
960 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
962 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
963 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
964 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
965 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
967 static bool cpu_has_load_ia32_efer;
968 static bool cpu_has_load_perf_global_ctrl;
970 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
971 static DEFINE_SPINLOCK(vmx_vpid_lock);
973 static struct vmcs_config {
978 u32 pin_based_exec_ctrl;
979 u32 cpu_based_exec_ctrl;
980 u32 cpu_based_2nd_exec_ctrl;
985 static struct vmx_capability {
990 #define VMX_SEGMENT_FIELD(seg) \
991 [VCPU_SREG_##seg] = { \
992 .selector = GUEST_##seg##_SELECTOR, \
993 .base = GUEST_##seg##_BASE, \
994 .limit = GUEST_##seg##_LIMIT, \
995 .ar_bytes = GUEST_##seg##_AR_BYTES, \
998 static const struct kvm_vmx_segment_field {
1003 } kvm_vmx_segment_fields[] = {
1004 VMX_SEGMENT_FIELD(CS),
1005 VMX_SEGMENT_FIELD(DS),
1006 VMX_SEGMENT_FIELD(ES),
1007 VMX_SEGMENT_FIELD(FS),
1008 VMX_SEGMENT_FIELD(GS),
1009 VMX_SEGMENT_FIELD(SS),
1010 VMX_SEGMENT_FIELD(TR),
1011 VMX_SEGMENT_FIELD(LDTR),
1014 static u64 host_efer;
1016 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1019 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1020 * away by decrementing the array size.
1022 static const u32 vmx_msr_index[] = {
1023 #ifdef CONFIG_X86_64
1024 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1026 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1029 static inline bool is_exception_n(u32 intr_info, u8 vector)
1031 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1032 INTR_INFO_VALID_MASK)) ==
1033 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1036 static inline bool is_debug(u32 intr_info)
1038 return is_exception_n(intr_info, DB_VECTOR);
1041 static inline bool is_breakpoint(u32 intr_info)
1043 return is_exception_n(intr_info, BP_VECTOR);
1046 static inline bool is_page_fault(u32 intr_info)
1048 return is_exception_n(intr_info, PF_VECTOR);
1051 static inline bool is_no_device(u32 intr_info)
1053 return is_exception_n(intr_info, NM_VECTOR);
1056 static inline bool is_invalid_opcode(u32 intr_info)
1058 return is_exception_n(intr_info, UD_VECTOR);
1061 static inline bool is_external_interrupt(u32 intr_info)
1063 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1064 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1067 static inline bool is_machine_check(u32 intr_info)
1069 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1070 INTR_INFO_VALID_MASK)) ==
1071 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1074 /* Undocumented: icebp/int1 */
1075 static inline bool is_icebp(u32 intr_info)
1077 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1078 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1083 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1088 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1093 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1098 return vmcs_config.cpu_based_exec_ctrl &
1099 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1104 return vmcs_config.cpu_based_2nd_exec_ctrl &
1105 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1110 return vmcs_config.cpu_based_2nd_exec_ctrl &
1111 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1116 return vmcs_config.cpu_based_2nd_exec_ctrl &
1117 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1122 return vmcs_config.cpu_based_2nd_exec_ctrl &
1123 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1127 * Comment's format: document - errata name - stepping - processor name.
1129 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1131 static u32 vmx_preemption_cpu_tfms[] = {
1132 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1134 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1138 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1140 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1143 * 320767.pdf - AAP86 - B1 -
1144 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1153 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1161 u32 eax = cpuid_eax(0x00000001), i;
1163 /* Clear the reserved bits */
1164 eax &= ~(0x3U << 14 | 0xfU << 28);
1165 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1166 if (eax == vmx_preemption_cpu_tfms[i])
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1174 return vmcs_config.pin_based_exec_ctrl &
1175 PIN_BASED_VMX_PREEMPTION_TIMER;
1178 static inline bool cpu_has_vmx_posted_intr(void)
1180 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1181 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1184 static inline bool cpu_has_vmx_apicv(void)
1186 return cpu_has_vmx_apic_register_virt() &&
1187 cpu_has_vmx_virtual_intr_delivery() &&
1188 cpu_has_vmx_posted_intr();
1191 static inline bool cpu_has_vmx_flexpriority(void)
1193 return cpu_has_vmx_tpr_shadow() &&
1194 cpu_has_vmx_virtualize_apic_accesses();
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1199 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1204 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1209 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1214 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1217 static inline bool cpu_has_vmx_ept_mt_wb(void)
1219 return vmx_capability.ept & VMX_EPTP_WB_BIT;
1222 static inline bool cpu_has_vmx_ept_5levels(void)
1224 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1227 static inline bool cpu_has_vmx_ept_ad_bits(void)
1229 return vmx_capability.ept & VMX_EPT_AD_BIT;
1232 static inline bool cpu_has_vmx_invept_context(void)
1234 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1237 static inline bool cpu_has_vmx_invept_global(void)
1239 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1242 static inline bool cpu_has_vmx_invvpid_single(void)
1244 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1247 static inline bool cpu_has_vmx_invvpid_global(void)
1249 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1252 static inline bool cpu_has_vmx_invvpid(void)
1254 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1257 static inline bool cpu_has_vmx_ept(void)
1259 return vmcs_config.cpu_based_2nd_exec_ctrl &
1260 SECONDARY_EXEC_ENABLE_EPT;
1263 static inline bool cpu_has_vmx_unrestricted_guest(void)
1265 return vmcs_config.cpu_based_2nd_exec_ctrl &
1266 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1269 static inline bool cpu_has_vmx_ple(void)
1271 return vmcs_config.cpu_based_2nd_exec_ctrl &
1272 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1275 static inline bool cpu_has_vmx_basic_inout(void)
1277 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1280 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1282 return flexpriority_enabled && lapic_in_kernel(vcpu);
1285 static inline bool cpu_has_vmx_vpid(void)
1287 return vmcs_config.cpu_based_2nd_exec_ctrl &
1288 SECONDARY_EXEC_ENABLE_VPID;
1291 static inline bool cpu_has_vmx_rdtscp(void)
1293 return vmcs_config.cpu_based_2nd_exec_ctrl &
1294 SECONDARY_EXEC_RDTSCP;
1297 static inline bool cpu_has_vmx_invpcid(void)
1299 return vmcs_config.cpu_based_2nd_exec_ctrl &
1300 SECONDARY_EXEC_ENABLE_INVPCID;
1303 static inline bool cpu_has_virtual_nmis(void)
1305 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1308 static inline bool cpu_has_vmx_wbinvd_exit(void)
1310 return vmcs_config.cpu_based_2nd_exec_ctrl &
1311 SECONDARY_EXEC_WBINVD_EXITING;
1314 static inline bool cpu_has_vmx_shadow_vmcs(void)
1317 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1318 /* check if the cpu supports writing r/o exit information fields */
1319 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1322 return vmcs_config.cpu_based_2nd_exec_ctrl &
1323 SECONDARY_EXEC_SHADOW_VMCS;
1326 static inline bool cpu_has_vmx_pml(void)
1328 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1331 static inline bool cpu_has_vmx_tsc_scaling(void)
1333 return vmcs_config.cpu_based_2nd_exec_ctrl &
1334 SECONDARY_EXEC_TSC_SCALING;
1337 static inline bool cpu_has_vmx_vmfunc(void)
1339 return vmcs_config.cpu_based_2nd_exec_ctrl &
1340 SECONDARY_EXEC_ENABLE_VMFUNC;
1343 static inline bool report_flexpriority(void)
1345 return flexpriority_enabled;
1348 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1350 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1353 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1355 return vmcs12->cpu_based_vm_exec_control & bit;
1358 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1360 return (vmcs12->cpu_based_vm_exec_control &
1361 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1362 (vmcs12->secondary_vm_exec_control & bit);
1365 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1367 return vmcs12->pin_based_vm_exec_control &
1368 PIN_BASED_VMX_PREEMPTION_TIMER;
1371 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1373 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1376 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1378 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1381 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1383 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1386 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1388 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1391 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1393 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1396 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1398 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1401 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1403 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1406 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1408 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1411 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1413 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1416 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1418 return nested_cpu_has_vmfunc(vmcs12) &&
1419 (vmcs12->vm_function_control &
1420 VMX_VMFUNC_EPTP_SWITCHING);
1423 static inline bool is_nmi(u32 intr_info)
1425 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1426 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1429 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1431 unsigned long exit_qualification);
1432 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1433 struct vmcs12 *vmcs12,
1434 u32 reason, unsigned long qualification);
1436 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1440 for (i = 0; i < vmx->nmsrs; ++i)
1441 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1446 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1452 } operand = { vpid, 0, gva };
1454 asm volatile (__ex(ASM_VMX_INVVPID)
1455 /* CF==1 or ZF==1 --> rc = -1 */
1456 "; ja 1f ; ud2 ; 1:"
1457 : : "a"(&operand), "c"(ext) : "cc", "memory");
1460 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1464 } operand = {eptp, gpa};
1466 asm volatile (__ex(ASM_VMX_INVEPT)
1467 /* CF==1 or ZF==1 --> rc = -1 */
1468 "; ja 1f ; ud2 ; 1:\n"
1469 : : "a" (&operand), "c" (ext) : "cc", "memory");
1472 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1476 i = __find_msr_index(vmx, msr);
1478 return &vmx->guest_msrs[i];
1482 static void vmcs_clear(struct vmcs *vmcs)
1484 u64 phys_addr = __pa(vmcs);
1487 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1488 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1491 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1495 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1497 vmcs_clear(loaded_vmcs->vmcs);
1498 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1499 vmcs_clear(loaded_vmcs->shadow_vmcs);
1500 loaded_vmcs->cpu = -1;
1501 loaded_vmcs->launched = 0;
1504 static void vmcs_load(struct vmcs *vmcs)
1506 u64 phys_addr = __pa(vmcs);
1509 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1510 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1513 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1517 #ifdef CONFIG_KEXEC_CORE
1519 * This bitmap is used to indicate whether the vmclear
1520 * operation is enabled on all cpus. All disabled by
1523 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1525 static inline void crash_enable_local_vmclear(int cpu)
1527 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1530 static inline void crash_disable_local_vmclear(int cpu)
1532 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1535 static inline int crash_local_vmclear_enabled(int cpu)
1537 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1540 static void crash_vmclear_local_loaded_vmcss(void)
1542 int cpu = raw_smp_processor_id();
1543 struct loaded_vmcs *v;
1545 if (!crash_local_vmclear_enabled(cpu))
1548 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1549 loaded_vmcss_on_cpu_link)
1550 vmcs_clear(v->vmcs);
1553 static inline void crash_enable_local_vmclear(int cpu) { }
1554 static inline void crash_disable_local_vmclear(int cpu) { }
1555 #endif /* CONFIG_KEXEC_CORE */
1557 static void __loaded_vmcs_clear(void *arg)
1559 struct loaded_vmcs *loaded_vmcs = arg;
1560 int cpu = raw_smp_processor_id();
1562 if (loaded_vmcs->cpu != cpu)
1563 return; /* vcpu migration can race with cpu offline */
1564 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1565 per_cpu(current_vmcs, cpu) = NULL;
1566 crash_disable_local_vmclear(cpu);
1567 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1570 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1571 * is before setting loaded_vmcs->vcpu to -1 which is done in
1572 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1573 * then adds the vmcs into percpu list before it is deleted.
1577 loaded_vmcs_init(loaded_vmcs);
1578 crash_enable_local_vmclear(cpu);
1581 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1583 int cpu = loaded_vmcs->cpu;
1586 smp_call_function_single(cpu,
1587 __loaded_vmcs_clear, loaded_vmcs, 1);
1590 static inline void vpid_sync_vcpu_single(int vpid)
1595 if (cpu_has_vmx_invvpid_single())
1596 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1599 static inline void vpid_sync_vcpu_global(void)
1601 if (cpu_has_vmx_invvpid_global())
1602 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1605 static inline void vpid_sync_context(int vpid)
1607 if (cpu_has_vmx_invvpid_single())
1608 vpid_sync_vcpu_single(vpid);
1610 vpid_sync_vcpu_global();
1613 static inline void ept_sync_global(void)
1615 if (cpu_has_vmx_invept_global())
1616 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1619 static inline void ept_sync_context(u64 eptp)
1622 if (cpu_has_vmx_invept_context())
1623 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1629 static __always_inline void vmcs_check16(unsigned long field)
1631 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1632 "16-bit accessor invalid for 64-bit field");
1633 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1634 "16-bit accessor invalid for 64-bit high field");
1635 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1636 "16-bit accessor invalid for 32-bit high field");
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1638 "16-bit accessor invalid for natural width field");
1641 static __always_inline void vmcs_check32(unsigned long field)
1643 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1644 "32-bit accessor invalid for 16-bit field");
1645 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1646 "32-bit accessor invalid for natural width field");
1649 static __always_inline void vmcs_check64(unsigned long field)
1651 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1652 "64-bit accessor invalid for 16-bit field");
1653 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1654 "64-bit accessor invalid for 64-bit high field");
1655 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1656 "64-bit accessor invalid for 32-bit field");
1657 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1658 "64-bit accessor invalid for natural width field");
1661 static __always_inline void vmcs_checkl(unsigned long field)
1663 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1664 "Natural width accessor invalid for 16-bit field");
1665 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1666 "Natural width accessor invalid for 64-bit field");
1667 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1668 "Natural width accessor invalid for 64-bit high field");
1669 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1670 "Natural width accessor invalid for 32-bit field");
1673 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1675 unsigned long value;
1677 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1678 : "=a"(value) : "d"(field) : "cc");
1682 static __always_inline u16 vmcs_read16(unsigned long field)
1684 vmcs_check16(field);
1685 return __vmcs_readl(field);
1688 static __always_inline u32 vmcs_read32(unsigned long field)
1690 vmcs_check32(field);
1691 return __vmcs_readl(field);
1694 static __always_inline u64 vmcs_read64(unsigned long field)
1696 vmcs_check64(field);
1697 #ifdef CONFIG_X86_64
1698 return __vmcs_readl(field);
1700 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1704 static __always_inline unsigned long vmcs_readl(unsigned long field)
1707 return __vmcs_readl(field);
1710 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1712 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1713 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1717 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1721 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1722 : "=q"(error) : "a"(value), "d"(field) : "cc");
1723 if (unlikely(error))
1724 vmwrite_error(field, value);
1727 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1729 vmcs_check16(field);
1730 __vmcs_writel(field, value);
1733 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1735 vmcs_check32(field);
1736 __vmcs_writel(field, value);
1739 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1741 vmcs_check64(field);
1742 __vmcs_writel(field, value);
1743 #ifndef CONFIG_X86_64
1745 __vmcs_writel(field+1, value >> 32);
1749 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1752 __vmcs_writel(field, value);
1755 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1757 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1758 "vmcs_clear_bits does not support 64-bit fields");
1759 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1762 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1764 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1765 "vmcs_set_bits does not support 64-bit fields");
1766 __vmcs_writel(field, __vmcs_readl(field) | mask);
1769 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1771 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1774 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1776 vmcs_write32(VM_ENTRY_CONTROLS, val);
1777 vmx->vm_entry_controls_shadow = val;
1780 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1782 if (vmx->vm_entry_controls_shadow != val)
1783 vm_entry_controls_init(vmx, val);
1786 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1788 return vmx->vm_entry_controls_shadow;
1792 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1794 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1797 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1799 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1802 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1804 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1807 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1809 vmcs_write32(VM_EXIT_CONTROLS, val);
1810 vmx->vm_exit_controls_shadow = val;
1813 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1815 if (vmx->vm_exit_controls_shadow != val)
1816 vm_exit_controls_init(vmx, val);
1819 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1821 return vmx->vm_exit_controls_shadow;
1825 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1827 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1830 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1832 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1835 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1837 vmx->segment_cache.bitmask = 0;
1840 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1844 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1846 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1847 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1848 vmx->segment_cache.bitmask = 0;
1850 ret = vmx->segment_cache.bitmask & mask;
1851 vmx->segment_cache.bitmask |= mask;
1855 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1857 u16 *p = &vmx->segment_cache.seg[seg].selector;
1859 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1860 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1864 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1866 ulong *p = &vmx->segment_cache.seg[seg].base;
1868 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1869 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1873 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1875 u32 *p = &vmx->segment_cache.seg[seg].limit;
1877 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1878 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1882 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1884 u32 *p = &vmx->segment_cache.seg[seg].ar;
1886 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1887 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1891 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1895 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1896 (1u << DB_VECTOR) | (1u << AC_VECTOR);
1897 if ((vcpu->guest_debug &
1898 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1899 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1900 eb |= 1u << BP_VECTOR;
1901 if (to_vmx(vcpu)->rmode.vm86_active)
1904 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1906 /* When we are running a nested L2 guest and L1 specified for it a
1907 * certain exception bitmap, we must trap the same exceptions and pass
1908 * them to L1. When running L2, we will only handle the exceptions
1909 * specified above if L1 did not want them.
1911 if (is_guest_mode(vcpu))
1912 eb |= get_vmcs12(vcpu)->exception_bitmap;
1914 vmcs_write32(EXCEPTION_BITMAP, eb);
1918 * Check if MSR is intercepted for currently loaded MSR bitmap.
1920 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
1922 unsigned long *msr_bitmap;
1923 int f = sizeof(unsigned long);
1925 if (!cpu_has_vmx_msr_bitmap())
1928 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
1930 if (msr <= 0x1fff) {
1931 return !!test_bit(msr, msr_bitmap + 0x800 / f);
1932 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1934 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
1941 * Check if MSR is intercepted for L01 MSR bitmap.
1943 static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
1945 unsigned long *msr_bitmap;
1946 int f = sizeof(unsigned long);
1948 if (!cpu_has_vmx_msr_bitmap())
1951 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
1953 if (msr <= 0x1fff) {
1954 return !!test_bit(msr, msr_bitmap + 0x800 / f);
1955 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1957 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
1963 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1964 unsigned long entry, unsigned long exit)
1966 vm_entry_controls_clearbit(vmx, entry);
1967 vm_exit_controls_clearbit(vmx, exit);
1970 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1973 struct msr_autoload *m = &vmx->msr_autoload;
1977 if (cpu_has_load_ia32_efer) {
1978 clear_atomic_switch_msr_special(vmx,
1979 VM_ENTRY_LOAD_IA32_EFER,
1980 VM_EXIT_LOAD_IA32_EFER);
1984 case MSR_CORE_PERF_GLOBAL_CTRL:
1985 if (cpu_has_load_perf_global_ctrl) {
1986 clear_atomic_switch_msr_special(vmx,
1987 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1988 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1994 for (i = 0; i < m->nr; ++i)
1995 if (m->guest[i].index == msr)
2001 m->guest[i] = m->guest[m->nr];
2002 m->host[i] = m->host[m->nr];
2003 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2004 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2007 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2008 unsigned long entry, unsigned long exit,
2009 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2010 u64 guest_val, u64 host_val)
2012 vmcs_write64(guest_val_vmcs, guest_val);
2013 vmcs_write64(host_val_vmcs, host_val);
2014 vm_entry_controls_setbit(vmx, entry);
2015 vm_exit_controls_setbit(vmx, exit);
2018 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
2019 u64 guest_val, u64 host_val)
2022 struct msr_autoload *m = &vmx->msr_autoload;
2026 if (cpu_has_load_ia32_efer) {
2027 add_atomic_switch_msr_special(vmx,
2028 VM_ENTRY_LOAD_IA32_EFER,
2029 VM_EXIT_LOAD_IA32_EFER,
2032 guest_val, host_val);
2036 case MSR_CORE_PERF_GLOBAL_CTRL:
2037 if (cpu_has_load_perf_global_ctrl) {
2038 add_atomic_switch_msr_special(vmx,
2039 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2040 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2041 GUEST_IA32_PERF_GLOBAL_CTRL,
2042 HOST_IA32_PERF_GLOBAL_CTRL,
2043 guest_val, host_val);
2047 case MSR_IA32_PEBS_ENABLE:
2048 /* PEBS needs a quiescent period after being disabled (to write
2049 * a record). Disabling PEBS through VMX MSR swapping doesn't
2050 * provide that period, so a CPU could write host's record into
2053 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2056 for (i = 0; i < m->nr; ++i)
2057 if (m->guest[i].index == msr)
2060 if (i == NR_AUTOLOAD_MSRS) {
2061 printk_once(KERN_WARNING "Not enough msr switch entries. "
2062 "Can't add msr %x\n", msr);
2064 } else if (i == m->nr) {
2066 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2067 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2070 m->guest[i].index = msr;
2071 m->guest[i].value = guest_val;
2072 m->host[i].index = msr;
2073 m->host[i].value = host_val;
2076 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2078 u64 guest_efer = vmx->vcpu.arch.efer;
2079 u64 ignore_bits = 0;
2083 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2084 * host CPUID is more efficient than testing guest CPUID
2085 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2087 if (boot_cpu_has(X86_FEATURE_SMEP))
2088 guest_efer |= EFER_NX;
2089 else if (!(guest_efer & EFER_NX))
2090 ignore_bits |= EFER_NX;
2094 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2096 ignore_bits |= EFER_SCE;
2097 #ifdef CONFIG_X86_64
2098 ignore_bits |= EFER_LMA | EFER_LME;
2099 /* SCE is meaningful only in long mode on Intel */
2100 if (guest_efer & EFER_LMA)
2101 ignore_bits &= ~(u64)EFER_SCE;
2104 clear_atomic_switch_msr(vmx, MSR_EFER);
2107 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2108 * On CPUs that support "load IA32_EFER", always switch EFER
2109 * atomically, since it's faster than switching it manually.
2111 if (cpu_has_load_ia32_efer ||
2112 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2113 if (!(guest_efer & EFER_LMA))
2114 guest_efer &= ~EFER_LME;
2115 if (guest_efer != host_efer)
2116 add_atomic_switch_msr(vmx, MSR_EFER,
2117 guest_efer, host_efer);
2120 guest_efer &= ~ignore_bits;
2121 guest_efer |= host_efer & ignore_bits;
2123 vmx->guest_msrs[efer_offset].data = guest_efer;
2124 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2130 #ifdef CONFIG_X86_32
2132 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2133 * VMCS rather than the segment table. KVM uses this helper to figure
2134 * out the current bases to poke them into the VMCS before entry.
2136 static unsigned long segment_base(u16 selector)
2138 struct desc_struct *table;
2141 if (!(selector & ~SEGMENT_RPL_MASK))
2144 table = get_current_gdt_ro();
2146 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2147 u16 ldt_selector = kvm_read_ldt();
2149 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2152 table = (struct desc_struct *)segment_base(ldt_selector);
2154 v = get_desc_base(&table[selector >> 3]);
2159 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2161 struct vcpu_vmx *vmx = to_vmx(vcpu);
2164 if (vmx->host_state.loaded)
2167 vmx->host_state.loaded = 1;
2169 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2170 * allow segment selectors with cpl > 0 or ti == 1.
2172 vmx->host_state.ldt_sel = kvm_read_ldt();
2173 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2174 savesegment(fs, vmx->host_state.fs_sel);
2175 if (!(vmx->host_state.fs_sel & 7)) {
2176 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2177 vmx->host_state.fs_reload_needed = 0;
2179 vmcs_write16(HOST_FS_SELECTOR, 0);
2180 vmx->host_state.fs_reload_needed = 1;
2182 savesegment(gs, vmx->host_state.gs_sel);
2183 if (!(vmx->host_state.gs_sel & 7))
2184 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2186 vmcs_write16(HOST_GS_SELECTOR, 0);
2187 vmx->host_state.gs_ldt_reload_needed = 1;
2190 #ifdef CONFIG_X86_64
2191 savesegment(ds, vmx->host_state.ds_sel);
2192 savesegment(es, vmx->host_state.es_sel);
2195 #ifdef CONFIG_X86_64
2196 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2197 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2199 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2200 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2203 #ifdef CONFIG_X86_64
2204 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2205 if (is_long_mode(&vmx->vcpu))
2206 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2208 if (boot_cpu_has(X86_FEATURE_MPX))
2209 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2210 for (i = 0; i < vmx->save_nmsrs; ++i)
2211 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2212 vmx->guest_msrs[i].data,
2213 vmx->guest_msrs[i].mask);
2216 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2218 if (!vmx->host_state.loaded)
2221 ++vmx->vcpu.stat.host_state_reload;
2222 vmx->host_state.loaded = 0;
2223 #ifdef CONFIG_X86_64
2224 if (is_long_mode(&vmx->vcpu))
2225 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2227 if (vmx->host_state.gs_ldt_reload_needed) {
2228 kvm_load_ldt(vmx->host_state.ldt_sel);
2229 #ifdef CONFIG_X86_64
2230 load_gs_index(vmx->host_state.gs_sel);
2232 loadsegment(gs, vmx->host_state.gs_sel);
2235 if (vmx->host_state.fs_reload_needed)
2236 loadsegment(fs, vmx->host_state.fs_sel);
2237 #ifdef CONFIG_X86_64
2238 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2239 loadsegment(ds, vmx->host_state.ds_sel);
2240 loadsegment(es, vmx->host_state.es_sel);
2243 invalidate_tss_limit();
2244 #ifdef CONFIG_X86_64
2245 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2247 if (vmx->host_state.msr_host_bndcfgs)
2248 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2249 load_fixmap_gdt(raw_smp_processor_id());
2252 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2255 __vmx_load_host_state(vmx);
2259 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2261 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2262 struct pi_desc old, new;
2266 * In case of hot-plug or hot-unplug, we may have to undo
2267 * vmx_vcpu_pi_put even if there is no assigned device. And we
2268 * always keep PI.NDST up to date for simplicity: it makes the
2269 * code easier, and CPU migration is not a fast path.
2271 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2275 * First handle the simple case where no cmpxchg is necessary; just
2276 * allow posting non-urgent interrupts.
2278 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2279 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2280 * expects the VCPU to be on the blocked_vcpu_list that matches
2283 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2285 pi_clear_sn(pi_desc);
2289 /* The full case. */
2291 old.control = new.control = pi_desc->control;
2293 dest = cpu_physical_id(cpu);
2295 if (x2apic_enabled())
2298 new.ndst = (dest << 8) & 0xFF00;
2301 } while (cmpxchg64(&pi_desc->control, old.control,
2302 new.control) != old.control);
2305 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2307 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2308 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2312 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2313 * vcpu mutex is already taken.
2315 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2317 struct vcpu_vmx *vmx = to_vmx(vcpu);
2318 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2320 if (!already_loaded) {
2321 loaded_vmcs_clear(vmx->loaded_vmcs);
2322 local_irq_disable();
2323 crash_disable_local_vmclear(cpu);
2326 * Read loaded_vmcs->cpu should be before fetching
2327 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2328 * See the comments in __loaded_vmcs_clear().
2332 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2333 &per_cpu(loaded_vmcss_on_cpu, cpu));
2334 crash_enable_local_vmclear(cpu);
2338 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2339 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2340 vmcs_load(vmx->loaded_vmcs->vmcs);
2341 indirect_branch_prediction_barrier();
2344 if (!already_loaded) {
2345 void *gdt = get_current_gdt_ro();
2346 unsigned long sysenter_esp;
2348 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2351 * Linux uses per-cpu TSS and GDT, so set these when switching
2352 * processors. See 22.2.4.
2354 vmcs_writel(HOST_TR_BASE,
2355 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2356 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
2359 * VM exits change the host TR limit to 0x67 after a VM
2360 * exit. This is okay, since 0x67 covers everything except
2361 * the IO bitmap and have have code to handle the IO bitmap
2362 * being lost after a VM exit.
2364 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2366 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2367 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2369 vmx->loaded_vmcs->cpu = cpu;
2372 /* Setup TSC multiplier */
2373 if (kvm_has_tsc_control &&
2374 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2375 decache_tsc_multiplier(vmx);
2377 vmx_vcpu_pi_load(vcpu, cpu);
2378 vmx->host_pkru = read_pkru();
2381 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2383 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2385 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2386 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2387 !kvm_vcpu_apicv_active(vcpu))
2390 /* Set SN when the vCPU is preempted */
2391 if (vcpu->preempted)
2395 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2397 vmx_vcpu_pi_put(vcpu);
2399 __vmx_load_host_state(to_vmx(vcpu));
2402 static bool emulation_required(struct kvm_vcpu *vcpu)
2404 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2407 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2410 * Return the cr0 value that a nested guest would read. This is a combination
2411 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2412 * its hypervisor (cr0_read_shadow).
2414 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2416 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2417 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2419 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2421 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2422 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2425 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2427 unsigned long rflags, save_rflags;
2429 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2430 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2431 rflags = vmcs_readl(GUEST_RFLAGS);
2432 if (to_vmx(vcpu)->rmode.vm86_active) {
2433 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2434 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2435 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2437 to_vmx(vcpu)->rflags = rflags;
2439 return to_vmx(vcpu)->rflags;
2442 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2444 unsigned long old_rflags = vmx_get_rflags(vcpu);
2446 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2447 to_vmx(vcpu)->rflags = rflags;
2448 if (to_vmx(vcpu)->rmode.vm86_active) {
2449 to_vmx(vcpu)->rmode.save_rflags = rflags;
2450 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2452 vmcs_writel(GUEST_RFLAGS, rflags);
2454 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2455 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2458 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2460 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2463 if (interruptibility & GUEST_INTR_STATE_STI)
2464 ret |= KVM_X86_SHADOW_INT_STI;
2465 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2466 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2471 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2473 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2474 u32 interruptibility = interruptibility_old;
2476 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2478 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2479 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2480 else if (mask & KVM_X86_SHADOW_INT_STI)
2481 interruptibility |= GUEST_INTR_STATE_STI;
2483 if ((interruptibility != interruptibility_old))
2484 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2487 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2491 rip = kvm_rip_read(vcpu);
2492 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2493 kvm_rip_write(vcpu, rip);
2495 /* skipping an emulated instruction also counts */
2496 vmx_set_interrupt_shadow(vcpu, 0);
2499 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2500 unsigned long exit_qual)
2502 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2503 unsigned int nr = vcpu->arch.exception.nr;
2504 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2506 if (vcpu->arch.exception.has_error_code) {
2507 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2508 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2511 if (kvm_exception_is_soft(nr))
2512 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2514 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2516 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2517 vmx_get_nmi_mask(vcpu))
2518 intr_info |= INTR_INFO_UNBLOCK_NMI;
2520 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2524 * KVM wants to inject page-faults which it got to the guest. This function
2525 * checks whether in a nested guest, we need to inject them to L1 or L2.
2527 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2529 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2530 unsigned int nr = vcpu->arch.exception.nr;
2532 if (nr == PF_VECTOR) {
2533 if (vcpu->arch.exception.nested_apf) {
2534 *exit_qual = vcpu->arch.apf.nested_apf_token;
2538 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2539 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2540 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2541 * can be written only when inject_pending_event runs. This should be
2542 * conditional on a new capability---if the capability is disabled,
2543 * kvm_multiple_exception would write the ancillary information to
2544 * CR2 or DR6, for backwards ABI-compatibility.
2546 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2547 vcpu->arch.exception.error_code)) {
2548 *exit_qual = vcpu->arch.cr2;
2552 if (vmcs12->exception_bitmap & (1u << nr)) {
2553 if (nr == DB_VECTOR)
2554 *exit_qual = vcpu->arch.dr6;
2564 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2566 struct vcpu_vmx *vmx = to_vmx(vcpu);
2567 unsigned nr = vcpu->arch.exception.nr;
2568 bool has_error_code = vcpu->arch.exception.has_error_code;
2569 u32 error_code = vcpu->arch.exception.error_code;
2570 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2572 if (has_error_code) {
2573 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2574 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2577 if (vmx->rmode.vm86_active) {
2579 if (kvm_exception_is_soft(nr))
2580 inc_eip = vcpu->arch.event_exit_inst_len;
2581 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2582 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2586 if (kvm_exception_is_soft(nr)) {
2587 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2588 vmx->vcpu.arch.event_exit_inst_len);
2589 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2591 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2593 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2596 static bool vmx_rdtscp_supported(void)
2598 return cpu_has_vmx_rdtscp();
2601 static bool vmx_invpcid_supported(void)
2603 return cpu_has_vmx_invpcid() && enable_ept;
2607 * Swap MSR entry in host/guest MSR entry array.
2609 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2611 struct shared_msr_entry tmp;
2613 tmp = vmx->guest_msrs[to];
2614 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2615 vmx->guest_msrs[from] = tmp;
2619 * Set up the vmcs to automatically save and restore system
2620 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2621 * mode, as fiddling with msrs is very expensive.
2623 static void setup_msrs(struct vcpu_vmx *vmx)
2625 int save_nmsrs, index;
2628 #ifdef CONFIG_X86_64
2629 if (is_long_mode(&vmx->vcpu)) {
2630 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2632 move_msr_up(vmx, index, save_nmsrs++);
2633 index = __find_msr_index(vmx, MSR_LSTAR);
2635 move_msr_up(vmx, index, save_nmsrs++);
2636 index = __find_msr_index(vmx, MSR_CSTAR);
2638 move_msr_up(vmx, index, save_nmsrs++);
2639 index = __find_msr_index(vmx, MSR_TSC_AUX);
2640 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2641 move_msr_up(vmx, index, save_nmsrs++);
2643 * MSR_STAR is only needed on long mode guests, and only
2644 * if efer.sce is enabled.
2646 index = __find_msr_index(vmx, MSR_STAR);
2647 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2648 move_msr_up(vmx, index, save_nmsrs++);
2651 index = __find_msr_index(vmx, MSR_EFER);
2652 if (index >= 0 && update_transition_efer(vmx, index))
2653 move_msr_up(vmx, index, save_nmsrs++);
2655 vmx->save_nmsrs = save_nmsrs;
2657 if (cpu_has_vmx_msr_bitmap())
2658 vmx_update_msr_bitmap(&vmx->vcpu);
2662 * reads and returns guest's timestamp counter "register"
2663 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2664 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2666 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2668 u64 host_tsc, tsc_offset;
2671 tsc_offset = vmcs_read64(TSC_OFFSET);
2672 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2676 * writes 'offset' into guest's timestamp counter offset register
2678 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2680 if (is_guest_mode(vcpu)) {
2682 * We're here if L1 chose not to trap WRMSR to TSC. According
2683 * to the spec, this should set L1's TSC; The offset that L1
2684 * set for L2 remains unchanged, and still needs to be added
2685 * to the newly set TSC to get L2's TSC.
2687 struct vmcs12 *vmcs12;
2688 /* recalculate vmcs02.TSC_OFFSET: */
2689 vmcs12 = get_vmcs12(vcpu);
2690 vmcs_write64(TSC_OFFSET, offset +
2691 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2692 vmcs12->tsc_offset : 0));
2694 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2695 vmcs_read64(TSC_OFFSET), offset);
2696 vmcs_write64(TSC_OFFSET, offset);
2701 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2702 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2703 * all guests if the "nested" module option is off, and can also be disabled
2704 * for a single guest by disabling its VMX cpuid bit.
2706 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2708 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2712 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2713 * returned for the various VMX controls MSRs when nested VMX is enabled.
2714 * The same values should also be used to verify that vmcs12 control fields are
2715 * valid during nested entry from L1 to L2.
2716 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2717 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2718 * bit in the high half is on if the corresponding bit in the control field
2719 * may be on. See also vmx_control_verify().
2721 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2724 * Note that as a general rule, the high half of the MSRs (bits in
2725 * the control fields which may be 1) should be initialized by the
2726 * intersection of the underlying hardware's MSR (i.e., features which
2727 * can be supported) and the list of features we want to expose -
2728 * because they are known to be properly supported in our code.
2729 * Also, usually, the low half of the MSRs (bits which must be 1) can
2730 * be set to 0, meaning that L1 may turn off any of these bits. The
2731 * reason is that if one of these bits is necessary, it will appear
2732 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2733 * fields of vmcs01 and vmcs02, will turn these bits off - and
2734 * nested_vmx_exit_reflected() will not pass related exits to L1.
2735 * These rules have exceptions below.
2738 /* pin-based controls */
2739 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2740 vmx->nested.nested_vmx_pinbased_ctls_low,
2741 vmx->nested.nested_vmx_pinbased_ctls_high);
2742 vmx->nested.nested_vmx_pinbased_ctls_low |=
2743 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2744 vmx->nested.nested_vmx_pinbased_ctls_high &=
2745 PIN_BASED_EXT_INTR_MASK |
2746 PIN_BASED_NMI_EXITING |
2747 PIN_BASED_VIRTUAL_NMIS;
2748 vmx->nested.nested_vmx_pinbased_ctls_high |=
2749 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2750 PIN_BASED_VMX_PREEMPTION_TIMER;
2751 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2752 vmx->nested.nested_vmx_pinbased_ctls_high |=
2753 PIN_BASED_POSTED_INTR;
2756 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2757 vmx->nested.nested_vmx_exit_ctls_low,
2758 vmx->nested.nested_vmx_exit_ctls_high);
2759 vmx->nested.nested_vmx_exit_ctls_low =
2760 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2762 vmx->nested.nested_vmx_exit_ctls_high &=
2763 #ifdef CONFIG_X86_64
2764 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2766 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2767 vmx->nested.nested_vmx_exit_ctls_high |=
2768 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2769 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2770 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2772 if (kvm_mpx_supported())
2773 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2775 /* We support free control of debug control saving. */
2776 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2778 /* entry controls */
2779 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2780 vmx->nested.nested_vmx_entry_ctls_low,
2781 vmx->nested.nested_vmx_entry_ctls_high);
2782 vmx->nested.nested_vmx_entry_ctls_low =
2783 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2784 vmx->nested.nested_vmx_entry_ctls_high &=
2785 #ifdef CONFIG_X86_64
2786 VM_ENTRY_IA32E_MODE |
2788 VM_ENTRY_LOAD_IA32_PAT;
2789 vmx->nested.nested_vmx_entry_ctls_high |=
2790 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2791 if (kvm_mpx_supported())
2792 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2794 /* We support free control of debug control loading. */
2795 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2797 /* cpu-based controls */
2798 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2799 vmx->nested.nested_vmx_procbased_ctls_low,
2800 vmx->nested.nested_vmx_procbased_ctls_high);
2801 vmx->nested.nested_vmx_procbased_ctls_low =
2802 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2803 vmx->nested.nested_vmx_procbased_ctls_high &=
2804 CPU_BASED_VIRTUAL_INTR_PENDING |
2805 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2806 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2807 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2808 CPU_BASED_CR3_STORE_EXITING |
2809 #ifdef CONFIG_X86_64
2810 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2812 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2813 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2814 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2815 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2816 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2818 * We can allow some features even when not supported by the
2819 * hardware. For example, L1 can specify an MSR bitmap - and we
2820 * can use it to avoid exits to L1 - even when L0 runs L2
2821 * without MSR bitmaps.
2823 vmx->nested.nested_vmx_procbased_ctls_high |=
2824 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2825 CPU_BASED_USE_MSR_BITMAPS;
2827 /* We support free control of CR3 access interception. */
2828 vmx->nested.nested_vmx_procbased_ctls_low &=
2829 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2832 * secondary cpu-based controls. Do not include those that
2833 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2835 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2836 vmx->nested.nested_vmx_secondary_ctls_low,
2837 vmx->nested.nested_vmx_secondary_ctls_high);
2838 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2839 vmx->nested.nested_vmx_secondary_ctls_high &=
2840 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2841 SECONDARY_EXEC_DESC |
2842 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2843 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2844 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2845 SECONDARY_EXEC_WBINVD_EXITING;
2848 /* nested EPT: emulate EPT also to L1 */
2849 vmx->nested.nested_vmx_secondary_ctls_high |=
2850 SECONDARY_EXEC_ENABLE_EPT;
2851 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2852 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2853 if (cpu_has_vmx_ept_execute_only())
2854 vmx->nested.nested_vmx_ept_caps |=
2855 VMX_EPT_EXECUTE_ONLY_BIT;
2856 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2857 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2858 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2859 VMX_EPT_1GB_PAGE_BIT;
2860 if (enable_ept_ad_bits) {
2861 vmx->nested.nested_vmx_secondary_ctls_high |=
2862 SECONDARY_EXEC_ENABLE_PML;
2863 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2866 vmx->nested.nested_vmx_ept_caps = 0;
2868 if (cpu_has_vmx_vmfunc()) {
2869 vmx->nested.nested_vmx_secondary_ctls_high |=
2870 SECONDARY_EXEC_ENABLE_VMFUNC;
2872 * Advertise EPTP switching unconditionally
2873 * since we emulate it
2876 vmx->nested.nested_vmx_vmfunc_controls =
2877 VMX_VMFUNC_EPTP_SWITCHING;
2881 * Old versions of KVM use the single-context version without
2882 * checking for support, so declare that it is supported even
2883 * though it is treated as global context. The alternative is
2884 * not failing the single-context invvpid, and it is worse.
2887 vmx->nested.nested_vmx_secondary_ctls_high |=
2888 SECONDARY_EXEC_ENABLE_VPID;
2889 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2890 VMX_VPID_EXTENT_SUPPORTED_MASK;
2892 vmx->nested.nested_vmx_vpid_caps = 0;
2894 if (enable_unrestricted_guest)
2895 vmx->nested.nested_vmx_secondary_ctls_high |=
2896 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2898 /* miscellaneous data */
2899 rdmsr(MSR_IA32_VMX_MISC,
2900 vmx->nested.nested_vmx_misc_low,
2901 vmx->nested.nested_vmx_misc_high);
2902 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2903 vmx->nested.nested_vmx_misc_low |=
2904 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2905 VMX_MISC_ACTIVITY_HLT;
2906 vmx->nested.nested_vmx_misc_high = 0;
2909 * This MSR reports some information about VMX support. We
2910 * should return information about the VMX we emulate for the
2911 * guest, and the VMCS structure we give it - not about the
2912 * VMX support of the underlying hardware.
2914 vmx->nested.nested_vmx_basic =
2916 VMX_BASIC_TRUE_CTLS |
2917 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2918 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2920 if (cpu_has_vmx_basic_inout())
2921 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2924 * These MSRs specify bits which the guest must keep fixed on
2925 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2926 * We picked the standard core2 setting.
2928 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2929 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2930 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2931 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2933 /* These MSRs specify bits which the guest must keep fixed off. */
2934 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2935 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2937 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2938 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2942 * if fixed0[i] == 1: val[i] must be 1
2943 * if fixed1[i] == 0: val[i] must be 0
2945 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2947 return ((val & fixed1) | fixed0) == val;
2950 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2952 return fixed_bits_valid(control, low, high);
2955 static inline u64 vmx_control_msr(u32 low, u32 high)
2957 return low | ((u64)high << 32);
2960 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2965 return (superset | subset) == superset;
2968 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2970 const u64 feature_and_reserved =
2971 /* feature (except bit 48; see below) */
2972 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2974 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2975 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2977 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2981 * KVM does not emulate a version of VMX that constrains physical
2982 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2984 if (data & BIT_ULL(48))
2987 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2988 vmx_basic_vmcs_revision_id(data))
2991 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2994 vmx->nested.nested_vmx_basic = data;
2999 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3004 switch (msr_index) {
3005 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3006 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
3007 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
3009 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3010 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
3011 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
3013 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3014 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
3015 highp = &vmx->nested.nested_vmx_exit_ctls_high;
3017 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3018 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
3019 highp = &vmx->nested.nested_vmx_entry_ctls_high;
3021 case MSR_IA32_VMX_PROCBASED_CTLS2:
3022 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
3023 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
3029 supported = vmx_control_msr(*lowp, *highp);
3031 /* Check must-be-1 bits are still 1. */
3032 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
3035 /* Check must-be-0 bits are still 0. */
3036 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
3040 *highp = data >> 32;
3044 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
3046 const u64 feature_and_reserved_bits =
3048 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3049 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3051 GENMASK_ULL(13, 9) | BIT_ULL(31);
3054 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
3055 vmx->nested.nested_vmx_misc_high);
3057 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3060 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3061 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3062 vmx_misc_preemption_timer_rate(data) !=
3063 vmx_misc_preemption_timer_rate(vmx_misc))
3066 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3069 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3072 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3075 vmx->nested.nested_vmx_misc_low = data;
3076 vmx->nested.nested_vmx_misc_high = data >> 32;
3080 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3082 u64 vmx_ept_vpid_cap;
3084 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3085 vmx->nested.nested_vmx_vpid_caps);
3087 /* Every bit is either reserved or a feature bit. */
3088 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3091 vmx->nested.nested_vmx_ept_caps = data;
3092 vmx->nested.nested_vmx_vpid_caps = data >> 32;
3096 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3100 switch (msr_index) {
3101 case MSR_IA32_VMX_CR0_FIXED0:
3102 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3104 case MSR_IA32_VMX_CR4_FIXED0:
3105 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3112 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3113 * must be 1 in the restored value.
3115 if (!is_bitwise_subset(data, *msr, -1ULL))
3123 * Called when userspace is restoring VMX MSRs.
3125 * Returns 0 on success, non-0 otherwise.
3127 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3129 struct vcpu_vmx *vmx = to_vmx(vcpu);
3131 switch (msr_index) {
3132 case MSR_IA32_VMX_BASIC:
3133 return vmx_restore_vmx_basic(vmx, data);
3134 case MSR_IA32_VMX_PINBASED_CTLS:
3135 case MSR_IA32_VMX_PROCBASED_CTLS:
3136 case MSR_IA32_VMX_EXIT_CTLS:
3137 case MSR_IA32_VMX_ENTRY_CTLS:
3139 * The "non-true" VMX capability MSRs are generated from the
3140 * "true" MSRs, so we do not support restoring them directly.
3142 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3143 * should restore the "true" MSRs with the must-be-1 bits
3144 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3145 * DEFAULT SETTINGS".
3148 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3149 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3150 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3151 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3152 case MSR_IA32_VMX_PROCBASED_CTLS2:
3153 return vmx_restore_control_msr(vmx, msr_index, data);
3154 case MSR_IA32_VMX_MISC:
3155 return vmx_restore_vmx_misc(vmx, data);
3156 case MSR_IA32_VMX_CR0_FIXED0:
3157 case MSR_IA32_VMX_CR4_FIXED0:
3158 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3159 case MSR_IA32_VMX_CR0_FIXED1:
3160 case MSR_IA32_VMX_CR4_FIXED1:
3162 * These MSRs are generated based on the vCPU's CPUID, so we
3163 * do not support restoring them directly.
3166 case MSR_IA32_VMX_EPT_VPID_CAP:
3167 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3168 case MSR_IA32_VMX_VMCS_ENUM:
3169 vmx->nested.nested_vmx_vmcs_enum = data;
3173 * The rest of the VMX capability MSRs do not support restore.
3179 /* Returns 0 on success, non-0 otherwise. */
3180 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3182 struct vcpu_vmx *vmx = to_vmx(vcpu);
3184 switch (msr_index) {
3185 case MSR_IA32_VMX_BASIC:
3186 *pdata = vmx->nested.nested_vmx_basic;
3188 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3189 case MSR_IA32_VMX_PINBASED_CTLS:
3190 *pdata = vmx_control_msr(
3191 vmx->nested.nested_vmx_pinbased_ctls_low,
3192 vmx->nested.nested_vmx_pinbased_ctls_high);
3193 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3194 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3196 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3197 case MSR_IA32_VMX_PROCBASED_CTLS:
3198 *pdata = vmx_control_msr(
3199 vmx->nested.nested_vmx_procbased_ctls_low,
3200 vmx->nested.nested_vmx_procbased_ctls_high);
3201 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3202 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3204 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3205 case MSR_IA32_VMX_EXIT_CTLS:
3206 *pdata = vmx_control_msr(
3207 vmx->nested.nested_vmx_exit_ctls_low,
3208 vmx->nested.nested_vmx_exit_ctls_high);
3209 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3210 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3212 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3213 case MSR_IA32_VMX_ENTRY_CTLS:
3214 *pdata = vmx_control_msr(
3215 vmx->nested.nested_vmx_entry_ctls_low,
3216 vmx->nested.nested_vmx_entry_ctls_high);
3217 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3218 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3220 case MSR_IA32_VMX_MISC:
3221 *pdata = vmx_control_msr(
3222 vmx->nested.nested_vmx_misc_low,
3223 vmx->nested.nested_vmx_misc_high);
3225 case MSR_IA32_VMX_CR0_FIXED0:
3226 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3228 case MSR_IA32_VMX_CR0_FIXED1:
3229 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3231 case MSR_IA32_VMX_CR4_FIXED0:
3232 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3234 case MSR_IA32_VMX_CR4_FIXED1:
3235 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3237 case MSR_IA32_VMX_VMCS_ENUM:
3238 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3240 case MSR_IA32_VMX_PROCBASED_CTLS2:
3241 *pdata = vmx_control_msr(
3242 vmx->nested.nested_vmx_secondary_ctls_low,
3243 vmx->nested.nested_vmx_secondary_ctls_high);
3245 case MSR_IA32_VMX_EPT_VPID_CAP:
3246 *pdata = vmx->nested.nested_vmx_ept_caps |
3247 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3249 case MSR_IA32_VMX_VMFUNC:
3250 *pdata = vmx->nested.nested_vmx_vmfunc_controls;
3259 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3262 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3264 return !(val & ~valid_bits);
3268 * Reads an msr value (of 'msr_index') into 'pdata'.
3269 * Returns 0 on success, non-0 otherwise.
3270 * Assumes vcpu_load() was already called.
3272 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3274 struct shared_msr_entry *msr;
3276 switch (msr_info->index) {
3277 #ifdef CONFIG_X86_64
3279 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3282 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3284 case MSR_KERNEL_GS_BASE:
3285 vmx_load_host_state(to_vmx(vcpu));
3286 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3290 return kvm_get_msr_common(vcpu, msr_info);
3292 msr_info->data = guest_read_tsc(vcpu);
3294 case MSR_IA32_SPEC_CTRL:
3295 if (!msr_info->host_initiated &&
3296 !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
3297 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
3298 !guest_cpuid_has(vcpu, X86_FEATURE_RDS))
3301 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3303 case MSR_IA32_ARCH_CAPABILITIES:
3304 if (!msr_info->host_initiated &&
3305 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3307 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3309 case MSR_IA32_SYSENTER_CS:
3310 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3312 case MSR_IA32_SYSENTER_EIP:
3313 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3315 case MSR_IA32_SYSENTER_ESP:
3316 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3318 case MSR_IA32_BNDCFGS:
3319 if (!kvm_mpx_supported() ||
3320 (!msr_info->host_initiated &&
3321 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3323 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3325 case MSR_IA32_MCG_EXT_CTL:
3326 if (!msr_info->host_initiated &&
3327 !(to_vmx(vcpu)->msr_ia32_feature_control &
3328 FEATURE_CONTROL_LMCE))
3330 msr_info->data = vcpu->arch.mcg_ext_ctl;
3332 case MSR_IA32_FEATURE_CONTROL:
3333 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3335 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3336 if (!nested_vmx_allowed(vcpu))
3338 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3340 if (!vmx_xsaves_supported())
3342 msr_info->data = vcpu->arch.ia32_xss;
3345 if (!msr_info->host_initiated &&
3346 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3348 /* Otherwise falls through */
3350 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3352 msr_info->data = msr->data;
3355 return kvm_get_msr_common(vcpu, msr_info);
3361 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3364 * Writes msr value into into the appropriate "register".
3365 * Returns 0 on success, non-0 otherwise.
3366 * Assumes vcpu_load() was already called.
3368 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3370 struct vcpu_vmx *vmx = to_vmx(vcpu);
3371 struct shared_msr_entry *msr;
3373 u32 msr_index = msr_info->index;
3374 u64 data = msr_info->data;
3376 switch (msr_index) {
3378 ret = kvm_set_msr_common(vcpu, msr_info);
3380 #ifdef CONFIG_X86_64
3382 vmx_segment_cache_clear(vmx);
3383 vmcs_writel(GUEST_FS_BASE, data);
3386 vmx_segment_cache_clear(vmx);
3387 vmcs_writel(GUEST_GS_BASE, data);
3389 case MSR_KERNEL_GS_BASE:
3390 vmx_load_host_state(vmx);
3391 vmx->msr_guest_kernel_gs_base = data;
3394 case MSR_IA32_SYSENTER_CS:
3395 vmcs_write32(GUEST_SYSENTER_CS, data);
3397 case MSR_IA32_SYSENTER_EIP:
3398 vmcs_writel(GUEST_SYSENTER_EIP, data);
3400 case MSR_IA32_SYSENTER_ESP:
3401 vmcs_writel(GUEST_SYSENTER_ESP, data);
3403 case MSR_IA32_BNDCFGS:
3404 if (!kvm_mpx_supported() ||
3405 (!msr_info->host_initiated &&
3406 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3408 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3409 (data & MSR_IA32_BNDCFGS_RSVD))
3411 vmcs_write64(GUEST_BNDCFGS, data);
3414 kvm_write_tsc(vcpu, msr_info);
3416 case MSR_IA32_SPEC_CTRL:
3417 if (!msr_info->host_initiated &&
3418 !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
3419 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
3420 !guest_cpuid_has(vcpu, X86_FEATURE_RDS))
3423 /* The STIBP bit doesn't fault even if it's not advertised */
3424 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_RDS))
3427 vmx->spec_ctrl = data;
3434 * When it's written (to non-zero) for the first time, pass
3438 * The handling of the MSR bitmap for L2 guests is done in
3439 * nested_vmx_merge_msr_bitmap. We should not touch the
3440 * vmcs02.msr_bitmap here since it gets completely overwritten
3441 * in the merging. We update the vmcs01 here for L1 as well
3442 * since it will end up touching the MSR anyway now.
3444 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3448 case MSR_IA32_PRED_CMD:
3449 if (!msr_info->host_initiated &&
3450 !guest_cpuid_has(vcpu, X86_FEATURE_IBPB) &&
3451 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
3454 if (data & ~PRED_CMD_IBPB)
3460 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3464 * When it's written (to non-zero) for the first time, pass
3468 * The handling of the MSR bitmap for L2 guests is done in
3469 * nested_vmx_merge_msr_bitmap. We should not touch the
3470 * vmcs02.msr_bitmap here since it gets completely overwritten
3473 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3476 case MSR_IA32_ARCH_CAPABILITIES:
3477 if (!msr_info->host_initiated)
3479 vmx->arch_capabilities = data;
3481 case MSR_IA32_CR_PAT:
3482 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3483 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3485 vmcs_write64(GUEST_IA32_PAT, data);
3486 vcpu->arch.pat = data;
3489 ret = kvm_set_msr_common(vcpu, msr_info);
3491 case MSR_IA32_TSC_ADJUST:
3492 ret = kvm_set_msr_common(vcpu, msr_info);
3494 case MSR_IA32_MCG_EXT_CTL:
3495 if ((!msr_info->host_initiated &&
3496 !(to_vmx(vcpu)->msr_ia32_feature_control &
3497 FEATURE_CONTROL_LMCE)) ||
3498 (data & ~MCG_EXT_CTL_LMCE_EN))
3500 vcpu->arch.mcg_ext_ctl = data;
3502 case MSR_IA32_FEATURE_CONTROL:
3503 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3504 (to_vmx(vcpu)->msr_ia32_feature_control &
3505 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3507 vmx->msr_ia32_feature_control = data;
3508 if (msr_info->host_initiated && data == 0)
3509 vmx_leave_nested(vcpu);
3511 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3512 if (!msr_info->host_initiated)
3513 return 1; /* they are read-only */
3514 if (!nested_vmx_allowed(vcpu))
3516 return vmx_set_vmx_msr(vcpu, msr_index, data);
3518 if (!vmx_xsaves_supported())
3521 * The only supported bit as of Skylake is bit 8, but
3522 * it is not supported on KVM.
3526 vcpu->arch.ia32_xss = data;
3527 if (vcpu->arch.ia32_xss != host_xss)
3528 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3529 vcpu->arch.ia32_xss, host_xss);
3531 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3534 if (!msr_info->host_initiated &&
3535 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3537 /* Check reserved bit, higher 32 bits should be zero */
3538 if ((data >> 32) != 0)
3540 /* Otherwise falls through */
3542 msr = find_msr_entry(vmx, msr_index);
3544 u64 old_msr_data = msr->data;
3546 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3548 ret = kvm_set_shared_msr(msr->index, msr->data,
3552 msr->data = old_msr_data;
3556 ret = kvm_set_msr_common(vcpu, msr_info);
3562 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3564 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3567 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3570 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3572 case VCPU_EXREG_PDPTR:
3574 ept_save_pdptrs(vcpu);
3581 static __init int cpu_has_kvm_support(void)
3583 return cpu_has_vmx();
3586 static __init int vmx_disabled_by_bios(void)
3590 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3591 if (msr & FEATURE_CONTROL_LOCKED) {
3592 /* launched w/ TXT and VMX disabled */
3593 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3596 /* launched w/o TXT and VMX only enabled w/ TXT */
3597 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3598 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3599 && !tboot_enabled()) {
3600 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3601 "activate TXT before enabling KVM\n");
3604 /* launched w/o TXT and VMX disabled */
3605 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3606 && !tboot_enabled())
3613 static void kvm_cpu_vmxon(u64 addr)
3615 cr4_set_bits(X86_CR4_VMXE);
3616 intel_pt_handle_vmx(1);
3618 asm volatile (ASM_VMX_VMXON_RAX
3619 : : "a"(&addr), "m"(addr)
3623 static int hardware_enable(void)
3625 int cpu = raw_smp_processor_id();
3626 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3629 if (cr4_read_shadow() & X86_CR4_VMXE)
3632 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3633 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3634 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3637 * Now we can enable the vmclear operation in kdump
3638 * since the loaded_vmcss_on_cpu list on this cpu
3639 * has been initialized.
3641 * Though the cpu is not in VMX operation now, there
3642 * is no problem to enable the vmclear operation
3643 * for the loaded_vmcss_on_cpu list is empty!
3645 crash_enable_local_vmclear(cpu);
3647 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3649 test_bits = FEATURE_CONTROL_LOCKED;
3650 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3651 if (tboot_enabled())
3652 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3654 if ((old & test_bits) != test_bits) {
3655 /* enable and lock */
3656 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3658 kvm_cpu_vmxon(phys_addr);
3664 static void vmclear_local_loaded_vmcss(void)
3666 int cpu = raw_smp_processor_id();
3667 struct loaded_vmcs *v, *n;
3669 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3670 loaded_vmcss_on_cpu_link)
3671 __loaded_vmcs_clear(v);
3675 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3678 static void kvm_cpu_vmxoff(void)
3680 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3682 intel_pt_handle_vmx(0);
3683 cr4_clear_bits(X86_CR4_VMXE);
3686 static void hardware_disable(void)
3688 vmclear_local_loaded_vmcss();
3692 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3693 u32 msr, u32 *result)
3695 u32 vmx_msr_low, vmx_msr_high;
3696 u32 ctl = ctl_min | ctl_opt;
3698 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3700 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3701 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3703 /* Ensure minimum (required) set of control bits are supported. */
3711 static __init bool allow_1_setting(u32 msr, u32 ctl)
3713 u32 vmx_msr_low, vmx_msr_high;
3715 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3716 return vmx_msr_high & ctl;
3719 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3721 u32 vmx_msr_low, vmx_msr_high;
3722 u32 min, opt, min2, opt2;
3723 u32 _pin_based_exec_control = 0;
3724 u32 _cpu_based_exec_control = 0;
3725 u32 _cpu_based_2nd_exec_control = 0;
3726 u32 _vmexit_control = 0;
3727 u32 _vmentry_control = 0;
3729 min = CPU_BASED_HLT_EXITING |
3730 #ifdef CONFIG_X86_64
3731 CPU_BASED_CR8_LOAD_EXITING |
3732 CPU_BASED_CR8_STORE_EXITING |
3734 CPU_BASED_CR3_LOAD_EXITING |
3735 CPU_BASED_CR3_STORE_EXITING |
3736 CPU_BASED_USE_IO_BITMAPS |
3737 CPU_BASED_MOV_DR_EXITING |
3738 CPU_BASED_USE_TSC_OFFSETING |
3739 CPU_BASED_INVLPG_EXITING |
3740 CPU_BASED_RDPMC_EXITING;
3742 if (!kvm_mwait_in_guest())
3743 min |= CPU_BASED_MWAIT_EXITING |
3744 CPU_BASED_MONITOR_EXITING;
3746 opt = CPU_BASED_TPR_SHADOW |
3747 CPU_BASED_USE_MSR_BITMAPS |
3748 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3749 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3750 &_cpu_based_exec_control) < 0)
3752 #ifdef CONFIG_X86_64
3753 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3754 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3755 ~CPU_BASED_CR8_STORE_EXITING;
3757 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3759 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3760 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3761 SECONDARY_EXEC_WBINVD_EXITING |
3762 SECONDARY_EXEC_ENABLE_VPID |
3763 SECONDARY_EXEC_ENABLE_EPT |
3764 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3765 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3766 SECONDARY_EXEC_RDTSCP |
3767 SECONDARY_EXEC_ENABLE_INVPCID |
3768 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3769 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3770 SECONDARY_EXEC_SHADOW_VMCS |
3771 SECONDARY_EXEC_XSAVES |
3772 SECONDARY_EXEC_RDSEED |
3773 SECONDARY_EXEC_RDRAND |
3774 SECONDARY_EXEC_ENABLE_PML |
3775 SECONDARY_EXEC_TSC_SCALING |
3776 SECONDARY_EXEC_ENABLE_VMFUNC;
3777 if (adjust_vmx_controls(min2, opt2,
3778 MSR_IA32_VMX_PROCBASED_CTLS2,
3779 &_cpu_based_2nd_exec_control) < 0)
3782 #ifndef CONFIG_X86_64
3783 if (!(_cpu_based_2nd_exec_control &
3784 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3785 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3788 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3789 _cpu_based_2nd_exec_control &= ~(
3790 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3791 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3792 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3794 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3795 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3797 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3798 CPU_BASED_CR3_STORE_EXITING |
3799 CPU_BASED_INVLPG_EXITING);
3800 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3801 vmx_capability.ept, vmx_capability.vpid);
3804 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3805 #ifdef CONFIG_X86_64
3806 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3808 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3809 VM_EXIT_CLEAR_BNDCFGS;
3810 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3811 &_vmexit_control) < 0)
3814 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3815 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3816 PIN_BASED_VMX_PREEMPTION_TIMER;
3817 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3818 &_pin_based_exec_control) < 0)
3821 if (cpu_has_broken_vmx_preemption_timer())
3822 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3823 if (!(_cpu_based_2nd_exec_control &
3824 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3825 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3827 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3828 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3829 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3830 &_vmentry_control) < 0)
3833 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3835 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3836 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3839 #ifdef CONFIG_X86_64
3840 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3841 if (vmx_msr_high & (1u<<16))
3845 /* Require Write-Back (WB) memory type for VMCS accesses. */
3846 if (((vmx_msr_high >> 18) & 15) != 6)
3849 vmcs_conf->size = vmx_msr_high & 0x1fff;
3850 vmcs_conf->order = get_order(vmcs_conf->size);
3851 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3852 vmcs_conf->revision_id = vmx_msr_low;
3854 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3855 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3856 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3857 vmcs_conf->vmexit_ctrl = _vmexit_control;
3858 vmcs_conf->vmentry_ctrl = _vmentry_control;
3860 cpu_has_load_ia32_efer =
3861 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3862 VM_ENTRY_LOAD_IA32_EFER)
3863 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3864 VM_EXIT_LOAD_IA32_EFER);
3866 cpu_has_load_perf_global_ctrl =
3867 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3868 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3869 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3870 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3873 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3874 * but due to errata below it can't be used. Workaround is to use
3875 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3877 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3882 * BC86,AAY89,BD102 (model 44)
3886 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3887 switch (boot_cpu_data.x86_model) {
3893 cpu_has_load_perf_global_ctrl = false;
3894 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3895 "does not work properly. Using workaround\n");
3902 if (boot_cpu_has(X86_FEATURE_XSAVES))
3903 rdmsrl(MSR_IA32_XSS, host_xss);
3908 static struct vmcs *alloc_vmcs_cpu(int cpu)
3910 int node = cpu_to_node(cpu);
3914 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3917 vmcs = page_address(pages);
3918 memset(vmcs, 0, vmcs_config.size);
3919 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3923 static void free_vmcs(struct vmcs *vmcs)
3925 free_pages((unsigned long)vmcs, vmcs_config.order);
3929 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3931 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3933 if (!loaded_vmcs->vmcs)
3935 loaded_vmcs_clear(loaded_vmcs);
3936 free_vmcs(loaded_vmcs->vmcs);
3937 loaded_vmcs->vmcs = NULL;
3938 if (loaded_vmcs->msr_bitmap)
3939 free_page((unsigned long)loaded_vmcs->msr_bitmap);
3940 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3943 static struct vmcs *alloc_vmcs(void)
3945 return alloc_vmcs_cpu(raw_smp_processor_id());
3948 static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3950 loaded_vmcs->vmcs = alloc_vmcs();
3951 if (!loaded_vmcs->vmcs)
3954 loaded_vmcs->shadow_vmcs = NULL;
3955 loaded_vmcs_init(loaded_vmcs);
3957 if (cpu_has_vmx_msr_bitmap()) {
3958 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
3959 if (!loaded_vmcs->msr_bitmap)
3961 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
3966 free_loaded_vmcs(loaded_vmcs);
3970 static void free_kvm_area(void)
3974 for_each_possible_cpu(cpu) {
3975 free_vmcs(per_cpu(vmxarea, cpu));
3976 per_cpu(vmxarea, cpu) = NULL;
3980 enum vmcs_field_type {
3981 VMCS_FIELD_TYPE_U16 = 0,
3982 VMCS_FIELD_TYPE_U64 = 1,
3983 VMCS_FIELD_TYPE_U32 = 2,
3984 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3987 static inline int vmcs_field_type(unsigned long field)
3989 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
3990 return VMCS_FIELD_TYPE_U32;
3991 return (field >> 13) & 0x3 ;
3994 static inline int vmcs_field_readonly(unsigned long field)
3996 return (((field >> 10) & 0x3) == 1);
3999 static void init_vmcs_shadow_fields(void)
4003 /* No checks for read only fields yet */
4005 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
4006 switch (shadow_read_write_fields[i]) {
4008 if (!kvm_mpx_supported())
4016 shadow_read_write_fields[j] =
4017 shadow_read_write_fields[i];
4020 max_shadow_read_write_fields = j;
4022 /* shadowed fields guest access without vmexit */
4023 for (i = 0; i < max_shadow_read_write_fields; i++) {
4024 unsigned long field = shadow_read_write_fields[i];
4026 clear_bit(field, vmx_vmwrite_bitmap);
4027 clear_bit(field, vmx_vmread_bitmap);
4028 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
4029 clear_bit(field + 1, vmx_vmwrite_bitmap);
4030 clear_bit(field + 1, vmx_vmread_bitmap);
4033 for (i = 0; i < max_shadow_read_only_fields; i++) {
4034 unsigned long field = shadow_read_only_fields[i];
4036 clear_bit(field, vmx_vmread_bitmap);
4037 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
4038 clear_bit(field + 1, vmx_vmread_bitmap);
4042 static __init int alloc_kvm_area(void)
4046 for_each_possible_cpu(cpu) {
4049 vmcs = alloc_vmcs_cpu(cpu);
4055 per_cpu(vmxarea, cpu) = vmcs;
4060 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
4061 struct kvm_segment *save)
4063 if (!emulate_invalid_guest_state) {
4065 * CS and SS RPL should be equal during guest entry according
4066 * to VMX spec, but in reality it is not always so. Since vcpu
4067 * is in the middle of the transition from real mode to
4068 * protected mode it is safe to assume that RPL 0 is a good
4071 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4072 save->selector &= ~SEGMENT_RPL_MASK;
4073 save->dpl = save->selector & SEGMENT_RPL_MASK;
4076 vmx_set_segment(vcpu, save, seg);
4079 static void enter_pmode(struct kvm_vcpu *vcpu)
4081 unsigned long flags;
4082 struct vcpu_vmx *vmx = to_vmx(vcpu);
4085 * Update real mode segment cache. It may be not up-to-date if sement
4086 * register was written while vcpu was in a guest mode.
4088 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4089 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4090 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4091 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4092 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4093 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4095 vmx->rmode.vm86_active = 0;
4097 vmx_segment_cache_clear(vmx);
4099 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4101 flags = vmcs_readl(GUEST_RFLAGS);
4102 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
4103 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
4104 vmcs_writel(GUEST_RFLAGS, flags);
4106 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
4107 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
4109 update_exception_bitmap(vcpu);
4111 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4112 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4113 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4114 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4115 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4116 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4119 static void fix_rmode_seg(int seg, struct kvm_segment *save)
4121 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4122 struct kvm_segment var = *save;
4125 if (seg == VCPU_SREG_CS)
4128 if (!emulate_invalid_guest_state) {
4129 var.selector = var.base >> 4;
4130 var.base = var.base & 0xffff0;
4140 if (save->base & 0xf)
4141 printk_once(KERN_WARNING "kvm: segment base is not "
4142 "paragraph aligned when entering "
4143 "protected mode (seg=%d)", seg);
4146 vmcs_write16(sf->selector, var.selector);
4147 vmcs_writel(sf->base, var.base);
4148 vmcs_write32(sf->limit, var.limit);
4149 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
4152 static void enter_rmode(struct kvm_vcpu *vcpu)
4154 unsigned long flags;
4155 struct vcpu_vmx *vmx = to_vmx(vcpu);
4157 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4158 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4159 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4160 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4161 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
4162 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4163 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
4165 vmx->rmode.vm86_active = 1;
4168 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4169 * vcpu. Warn the user that an update is overdue.
4171 if (!vcpu->kvm->arch.tss_addr)
4172 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4173 "called before entering vcpu\n");
4175 vmx_segment_cache_clear(vmx);
4177 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
4178 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
4179 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4181 flags = vmcs_readl(GUEST_RFLAGS);
4182 vmx->rmode.save_rflags = flags;
4184 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
4186 vmcs_writel(GUEST_RFLAGS, flags);
4187 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
4188 update_exception_bitmap(vcpu);
4190 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4191 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4192 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4193 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4194 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4195 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4197 kvm_mmu_reset_context(vcpu);
4200 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4202 struct vcpu_vmx *vmx = to_vmx(vcpu);
4203 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4209 * Force kernel_gs_base reloading before EFER changes, as control
4210 * of this msr depends on is_long_mode().
4212 vmx_load_host_state(to_vmx(vcpu));
4213 vcpu->arch.efer = efer;
4214 if (efer & EFER_LMA) {
4215 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4218 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4220 msr->data = efer & ~EFER_LME;
4225 #ifdef CONFIG_X86_64
4227 static void enter_lmode(struct kvm_vcpu *vcpu)
4231 vmx_segment_cache_clear(to_vmx(vcpu));
4233 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4234 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4235 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4237 vmcs_write32(GUEST_TR_AR_BYTES,
4238 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4239 | VMX_AR_TYPE_BUSY_64_TSS);
4241 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4244 static void exit_lmode(struct kvm_vcpu *vcpu)
4246 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4247 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4252 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4255 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4257 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4259 vpid_sync_context(vpid);
4263 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4265 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4268 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4271 vmx_flush_tlb(vcpu);
4274 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4276 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4278 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4279 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4282 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4284 if (enable_ept && is_paging(vcpu))
4285 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4286 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4289 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4291 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4293 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4294 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4297 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4299 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4301 if (!test_bit(VCPU_EXREG_PDPTR,
4302 (unsigned long *)&vcpu->arch.regs_dirty))
4305 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4306 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4307 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4308 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4309 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4313 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4315 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4317 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4318 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4319 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4320 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4321 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4324 __set_bit(VCPU_EXREG_PDPTR,
4325 (unsigned long *)&vcpu->arch.regs_avail);
4326 __set_bit(VCPU_EXREG_PDPTR,
4327 (unsigned long *)&vcpu->arch.regs_dirty);
4330 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4332 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4333 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4334 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4336 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4337 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4338 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4339 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4341 return fixed_bits_valid(val, fixed0, fixed1);
4344 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4346 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4347 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4349 return fixed_bits_valid(val, fixed0, fixed1);
4352 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4354 u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4355 u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4357 return fixed_bits_valid(val, fixed0, fixed1);
4360 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4361 #define nested_guest_cr4_valid nested_cr4_valid
4362 #define nested_host_cr4_valid nested_cr4_valid
4364 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4366 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4368 struct kvm_vcpu *vcpu)
4370 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4371 vmx_decache_cr3(vcpu);
4372 if (!(cr0 & X86_CR0_PG)) {
4373 /* From paging/starting to nonpaging */
4374 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4375 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4376 (CPU_BASED_CR3_LOAD_EXITING |
4377 CPU_BASED_CR3_STORE_EXITING));
4378 vcpu->arch.cr0 = cr0;
4379 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4380 } else if (!is_paging(vcpu)) {
4381 /* From nonpaging to paging */
4382 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4383 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4384 ~(CPU_BASED_CR3_LOAD_EXITING |
4385 CPU_BASED_CR3_STORE_EXITING));
4386 vcpu->arch.cr0 = cr0;
4387 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4390 if (!(cr0 & X86_CR0_WP))
4391 *hw_cr0 &= ~X86_CR0_WP;
4394 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4396 struct vcpu_vmx *vmx = to_vmx(vcpu);
4397 unsigned long hw_cr0;
4399 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4400 if (enable_unrestricted_guest)
4401 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4403 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4405 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4408 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4412 #ifdef CONFIG_X86_64
4413 if (vcpu->arch.efer & EFER_LME) {
4414 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4416 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4422 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4424 vmcs_writel(CR0_READ_SHADOW, cr0);
4425 vmcs_writel(GUEST_CR0, hw_cr0);
4426 vcpu->arch.cr0 = cr0;
4428 /* depends on vcpu->arch.cr0 to be set to a new value */
4429 vmx->emulation_required = emulation_required(vcpu);
4432 static int get_ept_level(struct kvm_vcpu *vcpu)
4434 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
4439 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4441 u64 eptp = VMX_EPTP_MT_WB;
4443 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
4445 if (enable_ept_ad_bits &&
4446 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4447 eptp |= VMX_EPTP_AD_ENABLE_BIT;
4448 eptp |= (root_hpa & PAGE_MASK);
4453 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4455 unsigned long guest_cr3;
4460 eptp = construct_eptp(vcpu, cr3);
4461 vmcs_write64(EPT_POINTER, eptp);
4462 if (is_paging(vcpu) || is_guest_mode(vcpu))
4463 guest_cr3 = kvm_read_cr3(vcpu);
4465 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4466 ept_load_pdptrs(vcpu);
4469 vmx_flush_tlb(vcpu);
4470 vmcs_writel(GUEST_CR3, guest_cr3);
4473 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4476 * Pass through host's Machine Check Enable value to hw_cr4, which
4477 * is in force while we are in guest mode. Do not let guests control
4478 * this bit, even if host CR4.MCE == 0.
4480 unsigned long hw_cr4 =
4481 (cr4_read_shadow() & X86_CR4_MCE) |
4482 (cr4 & ~X86_CR4_MCE) |
4483 (to_vmx(vcpu)->rmode.vm86_active ?
4484 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4486 if (cr4 & X86_CR4_VMXE) {
4488 * To use VMXON (and later other VMX instructions), a guest
4489 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4490 * So basically the check on whether to allow nested VMX
4493 if (!nested_vmx_allowed(vcpu))
4497 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4500 vcpu->arch.cr4 = cr4;
4502 if (!is_paging(vcpu)) {
4503 hw_cr4 &= ~X86_CR4_PAE;
4504 hw_cr4 |= X86_CR4_PSE;
4505 } else if (!(cr4 & X86_CR4_PAE)) {
4506 hw_cr4 &= ~X86_CR4_PAE;
4510 if (!enable_unrestricted_guest && !is_paging(vcpu))
4512 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4513 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4514 * to be manually disabled when guest switches to non-paging
4517 * If !enable_unrestricted_guest, the CPU is always running
4518 * with CR0.PG=1 and CR4 needs to be modified.
4519 * If enable_unrestricted_guest, the CPU automatically
4520 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4522 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4524 vmcs_writel(CR4_READ_SHADOW, cr4);
4525 vmcs_writel(GUEST_CR4, hw_cr4);
4529 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4530 struct kvm_segment *var, int seg)
4532 struct vcpu_vmx *vmx = to_vmx(vcpu);
4535 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4536 *var = vmx->rmode.segs[seg];
4537 if (seg == VCPU_SREG_TR
4538 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4540 var->base = vmx_read_guest_seg_base(vmx, seg);
4541 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4544 var->base = vmx_read_guest_seg_base(vmx, seg);
4545 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4546 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4547 ar = vmx_read_guest_seg_ar(vmx, seg);
4548 var->unusable = (ar >> 16) & 1;
4549 var->type = ar & 15;
4550 var->s = (ar >> 4) & 1;
4551 var->dpl = (ar >> 5) & 3;
4553 * Some userspaces do not preserve unusable property. Since usable
4554 * segment has to be present according to VMX spec we can use present
4555 * property to amend userspace bug by making unusable segment always
4556 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4557 * segment as unusable.
4559 var->present = !var->unusable;
4560 var->avl = (ar >> 12) & 1;
4561 var->l = (ar >> 13) & 1;
4562 var->db = (ar >> 14) & 1;
4563 var->g = (ar >> 15) & 1;
4566 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4568 struct kvm_segment s;
4570 if (to_vmx(vcpu)->rmode.vm86_active) {
4571 vmx_get_segment(vcpu, &s, seg);
4574 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4577 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4579 struct vcpu_vmx *vmx = to_vmx(vcpu);
4581 if (unlikely(vmx->rmode.vm86_active))
4584 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4585 return VMX_AR_DPL(ar);
4589 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4593 if (var->unusable || !var->present)
4596 ar = var->type & 15;
4597 ar |= (var->s & 1) << 4;
4598 ar |= (var->dpl & 3) << 5;
4599 ar |= (var->present & 1) << 7;
4600 ar |= (var->avl & 1) << 12;
4601 ar |= (var->l & 1) << 13;
4602 ar |= (var->db & 1) << 14;
4603 ar |= (var->g & 1) << 15;
4609 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4610 struct kvm_segment *var, int seg)
4612 struct vcpu_vmx *vmx = to_vmx(vcpu);
4613 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4615 vmx_segment_cache_clear(vmx);
4617 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4618 vmx->rmode.segs[seg] = *var;
4619 if (seg == VCPU_SREG_TR)
4620 vmcs_write16(sf->selector, var->selector);
4622 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4626 vmcs_writel(sf->base, var->base);
4627 vmcs_write32(sf->limit, var->limit);
4628 vmcs_write16(sf->selector, var->selector);
4631 * Fix the "Accessed" bit in AR field of segment registers for older
4633 * IA32 arch specifies that at the time of processor reset the
4634 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4635 * is setting it to 0 in the userland code. This causes invalid guest
4636 * state vmexit when "unrestricted guest" mode is turned on.
4637 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4638 * tree. Newer qemu binaries with that qemu fix would not need this
4641 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4642 var->type |= 0x1; /* Accessed */
4644 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4647 vmx->emulation_required = emulation_required(vcpu);
4650 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4652 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4654 *db = (ar >> 14) & 1;
4655 *l = (ar >> 13) & 1;
4658 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4660 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4661 dt->address = vmcs_readl(GUEST_IDTR_BASE);
4664 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4666 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4667 vmcs_writel(GUEST_IDTR_BASE, dt->address);
4670 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4672 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4673 dt->address = vmcs_readl(GUEST_GDTR_BASE);
4676 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4678 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4679 vmcs_writel(GUEST_GDTR_BASE, dt->address);
4682 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4684 struct kvm_segment var;
4687 vmx_get_segment(vcpu, &var, seg);
4689 if (seg == VCPU_SREG_CS)
4691 ar = vmx_segment_access_rights(&var);
4693 if (var.base != (var.selector << 4))
4695 if (var.limit != 0xffff)
4703 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4705 struct kvm_segment cs;
4706 unsigned int cs_rpl;
4708 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4709 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4713 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4717 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4718 if (cs.dpl > cs_rpl)
4721 if (cs.dpl != cs_rpl)
4727 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4731 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4733 struct kvm_segment ss;
4734 unsigned int ss_rpl;
4736 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4737 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4741 if (ss.type != 3 && ss.type != 7)
4745 if (ss.dpl != ss_rpl) /* DPL != RPL */
4753 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4755 struct kvm_segment var;
4758 vmx_get_segment(vcpu, &var, seg);
4759 rpl = var.selector & SEGMENT_RPL_MASK;
4767 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4768 if (var.dpl < rpl) /* DPL < RPL */
4772 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4778 static bool tr_valid(struct kvm_vcpu *vcpu)
4780 struct kvm_segment tr;
4782 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4786 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4788 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4796 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4798 struct kvm_segment ldtr;
4800 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4804 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4814 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4816 struct kvm_segment cs, ss;
4818 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4819 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4821 return ((cs.selector & SEGMENT_RPL_MASK) ==
4822 (ss.selector & SEGMENT_RPL_MASK));
4826 * Check if guest state is valid. Returns true if valid, false if
4828 * We assume that registers are always usable
4830 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4832 if (enable_unrestricted_guest)
4835 /* real mode guest state checks */
4836 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4837 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4839 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4841 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4843 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4845 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4847 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4850 /* protected mode guest state checks */
4851 if (!cs_ss_rpl_check(vcpu))
4853 if (!code_segment_valid(vcpu))
4855 if (!stack_segment_valid(vcpu))
4857 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4859 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4861 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4863 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4865 if (!tr_valid(vcpu))
4867 if (!ldtr_valid(vcpu))
4871 * - Add checks on RIP
4872 * - Add checks on RFLAGS
4878 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4880 return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4883 static int init_rmode_tss(struct kvm *kvm)
4889 idx = srcu_read_lock(&kvm->srcu);
4890 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4891 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4894 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4895 r = kvm_write_guest_page(kvm, fn++, &data,
4896 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4899 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4902 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4906 r = kvm_write_guest_page(kvm, fn, &data,
4907 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4910 srcu_read_unlock(&kvm->srcu, idx);
4914 static int init_rmode_identity_map(struct kvm *kvm)
4917 kvm_pfn_t identity_map_pfn;
4923 /* Protect kvm->arch.ept_identity_pagetable_done. */
4924 mutex_lock(&kvm->slots_lock);
4926 if (likely(kvm->arch.ept_identity_pagetable_done))
4929 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4931 r = alloc_identity_pagetable(kvm);
4935 idx = srcu_read_lock(&kvm->srcu);
4936 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4939 /* Set up identity-mapping pagetable for EPT in real mode */
4940 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4941 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4942 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4943 r = kvm_write_guest_page(kvm, identity_map_pfn,
4944 &tmp, i * sizeof(tmp), sizeof(tmp));
4948 kvm->arch.ept_identity_pagetable_done = true;
4951 srcu_read_unlock(&kvm->srcu, idx);
4954 mutex_unlock(&kvm->slots_lock);
4958 static void seg_setup(int seg)
4960 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4963 vmcs_write16(sf->selector, 0);
4964 vmcs_writel(sf->base, 0);
4965 vmcs_write32(sf->limit, 0xffff);
4967 if (seg == VCPU_SREG_CS)
4968 ar |= 0x08; /* code segment */
4970 vmcs_write32(sf->ar_bytes, ar);
4973 static int alloc_apic_access_page(struct kvm *kvm)
4978 mutex_lock(&kvm->slots_lock);
4979 if (kvm->arch.apic_access_page_done)
4981 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4982 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4986 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4987 if (is_error_page(page)) {
4993 * Do not pin the page in memory, so that memory hot-unplug
4994 * is able to migrate it.
4997 kvm->arch.apic_access_page_done = true;
4999 mutex_unlock(&kvm->slots_lock);
5003 static int alloc_identity_pagetable(struct kvm *kvm)
5005 /* Called with kvm->slots_lock held. */
5009 BUG_ON(kvm->arch.ept_identity_pagetable_done);
5011 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
5012 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
5017 static int allocate_vpid(void)
5023 spin_lock(&vmx_vpid_lock);
5024 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
5025 if (vpid < VMX_NR_VPIDS)
5026 __set_bit(vpid, vmx_vpid_bitmap);
5029 spin_unlock(&vmx_vpid_lock);
5033 static void free_vpid(int vpid)
5035 if (!enable_vpid || vpid == 0)
5037 spin_lock(&vmx_vpid_lock);
5038 __clear_bit(vpid, vmx_vpid_bitmap);
5039 spin_unlock(&vmx_vpid_lock);
5042 static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
5045 int f = sizeof(unsigned long);
5047 if (!cpu_has_vmx_msr_bitmap())
5051 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5052 * have the write-low and read-high bitmap offsets the wrong way round.
5053 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5055 if (msr <= 0x1fff) {
5056 if (type & MSR_TYPE_R)
5058 __clear_bit(msr, msr_bitmap + 0x000 / f);
5060 if (type & MSR_TYPE_W)
5062 __clear_bit(msr, msr_bitmap + 0x800 / f);
5064 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5066 if (type & MSR_TYPE_R)
5068 __clear_bit(msr, msr_bitmap + 0x400 / f);
5070 if (type & MSR_TYPE_W)
5072 __clear_bit(msr, msr_bitmap + 0xc00 / f);
5077 static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
5080 int f = sizeof(unsigned long);
5082 if (!cpu_has_vmx_msr_bitmap())
5086 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5087 * have the write-low and read-high bitmap offsets the wrong way round.
5088 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5090 if (msr <= 0x1fff) {
5091 if (type & MSR_TYPE_R)
5093 __set_bit(msr, msr_bitmap + 0x000 / f);
5095 if (type & MSR_TYPE_W)
5097 __set_bit(msr, msr_bitmap + 0x800 / f);
5099 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5101 if (type & MSR_TYPE_R)
5103 __set_bit(msr, msr_bitmap + 0x400 / f);
5105 if (type & MSR_TYPE_W)
5107 __set_bit(msr, msr_bitmap + 0xc00 / f);
5112 static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
5113 u32 msr, int type, bool value)
5116 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
5118 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
5122 * If a msr is allowed by L0, we should check whether it is allowed by L1.
5123 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
5125 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
5126 unsigned long *msr_bitmap_nested,
5129 int f = sizeof(unsigned long);
5131 if (!cpu_has_vmx_msr_bitmap()) {
5137 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5138 * have the write-low and read-high bitmap offsets the wrong way round.
5139 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5141 if (msr <= 0x1fff) {
5142 if (type & MSR_TYPE_R &&
5143 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
5145 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
5147 if (type & MSR_TYPE_W &&
5148 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
5150 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
5152 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
5154 if (type & MSR_TYPE_R &&
5155 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
5157 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
5159 if (type & MSR_TYPE_W &&
5160 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
5162 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
5167 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5171 if (cpu_has_secondary_exec_ctrls() &&
5172 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5173 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5174 mode |= MSR_BITMAP_MODE_X2APIC;
5175 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5176 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5179 if (is_long_mode(vcpu))
5180 mode |= MSR_BITMAP_MODE_LM;
5185 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5187 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5192 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5193 unsigned word = msr / BITS_PER_LONG;
5194 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5195 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5198 if (mode & MSR_BITMAP_MODE_X2APIC) {
5200 * TPR reads and writes can be virtualized even if virtual interrupt
5201 * delivery is not in use.
5203 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5204 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5205 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5206 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5207 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5212 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
5214 struct vcpu_vmx *vmx = to_vmx(vcpu);
5215 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5216 u8 mode = vmx_msr_bitmap_mode(vcpu);
5217 u8 changed = mode ^ vmx->msr_bitmap_mode;
5222 vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5223 !(mode & MSR_BITMAP_MODE_LM));
5225 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5226 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5228 vmx->msr_bitmap_mode = mode;
5231 static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
5233 return enable_apicv;
5236 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5238 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5242 * Don't need to mark the APIC access page dirty; it is never
5243 * written to by the CPU during APIC virtualization.
5246 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5247 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5248 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5251 if (nested_cpu_has_posted_intr(vmcs12)) {
5252 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5253 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5258 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
5260 struct vcpu_vmx *vmx = to_vmx(vcpu);
5265 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5268 vmx->nested.pi_pending = false;
5269 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5272 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5273 if (max_irr != 256) {
5274 vapic_page = kmap(vmx->nested.virtual_apic_page);
5275 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
5276 kunmap(vmx->nested.virtual_apic_page);
5278 status = vmcs_read16(GUEST_INTR_STATUS);
5279 if ((u8)max_irr > ((u8)status & 0xff)) {
5281 status |= (u8)max_irr;
5282 vmcs_write16(GUEST_INTR_STATUS, status);
5286 nested_mark_vmcs12_pages_dirty(vcpu);
5289 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
5293 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
5295 if (vcpu->mode == IN_GUEST_MODE) {
5297 * The vector of interrupt to be delivered to vcpu had
5298 * been set in PIR before this function.
5300 * Following cases will be reached in this block, and
5301 * we always send a notification event in all cases as
5304 * Case 1: vcpu keeps in non-root mode. Sending a
5305 * notification event posts the interrupt to vcpu.
5307 * Case 2: vcpu exits to root mode and is still
5308 * runnable. PIR will be synced to vIRR before the
5309 * next vcpu entry. Sending a notification event in
5310 * this case has no effect, as vcpu is not in root
5313 * Case 3: vcpu exits to root mode and is blocked.
5314 * vcpu_block() has already synced PIR to vIRR and
5315 * never blocks vcpu if vIRR is not cleared. Therefore,
5316 * a blocked vcpu here does not wait for any requested
5317 * interrupts in PIR, and sending a notification event
5318 * which has no effect is safe here.
5321 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
5328 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5331 struct vcpu_vmx *vmx = to_vmx(vcpu);
5333 if (is_guest_mode(vcpu) &&
5334 vector == vmx->nested.posted_intr_nv) {
5336 * If a posted intr is not recognized by hardware,
5337 * we will accomplish it in the next vmentry.
5339 vmx->nested.pi_pending = true;
5340 kvm_make_request(KVM_REQ_EVENT, vcpu);
5341 /* the PIR and ON have been set by L1. */
5342 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
5343 kvm_vcpu_kick(vcpu);
5349 * Send interrupt to vcpu via posted interrupt way.
5350 * 1. If target vcpu is running(non-root mode), send posted interrupt
5351 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5352 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5353 * interrupt from PIR in next vmentry.
5355 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5357 struct vcpu_vmx *vmx = to_vmx(vcpu);
5360 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5364 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5367 /* If a previous notification has sent the IPI, nothing to do. */
5368 if (pi_test_and_set_on(&vmx->pi_desc))
5371 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
5372 kvm_vcpu_kick(vcpu);
5376 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5377 * will not change in the lifetime of the guest.
5378 * Note that host-state that does change is set elsewhere. E.g., host-state
5379 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5381 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5386 unsigned long cr0, cr3, cr4;
5389 WARN_ON(cr0 & X86_CR0_TS);
5390 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
5393 * Save the most likely value for this task's CR3 in the VMCS.
5394 * We can't use __get_current_cr3_fast() because we're not atomic.
5397 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
5398 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
5400 /* Save the most likely value for this task's CR4 in the VMCS. */
5401 cr4 = cr4_read_shadow();
5402 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5403 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
5405 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
5406 #ifdef CONFIG_X86_64
5408 * Load null selectors, so we can avoid reloading them in
5409 * __vmx_load_host_state(), in case userspace uses the null selectors
5410 * too (the expected case).
5412 vmcs_write16(HOST_DS_SELECTOR, 0);
5413 vmcs_write16(HOST_ES_SELECTOR, 0);
5415 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5416 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5418 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5419 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5422 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
5423 vmx->host_idt_base = dt.address;
5425 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5427 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5428 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5429 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5430 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5432 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5433 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5434 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5438 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5440 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5442 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5443 if (is_guest_mode(&vmx->vcpu))
5444 vmx->vcpu.arch.cr4_guest_owned_bits &=
5445 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5446 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5449 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5451 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5453 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5454 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5455 /* Enable the preemption timer dynamically */
5456 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5457 return pin_based_exec_ctrl;
5460 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5462 struct vcpu_vmx *vmx = to_vmx(vcpu);
5464 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5465 if (cpu_has_secondary_exec_ctrls()) {
5466 if (kvm_vcpu_apicv_active(vcpu))
5467 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5468 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5469 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5471 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5472 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5473 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5476 if (cpu_has_vmx_msr_bitmap())
5477 vmx_update_msr_bitmap(vcpu);
5480 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5482 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5484 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5485 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5487 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5488 exec_control &= ~CPU_BASED_TPR_SHADOW;
5489 #ifdef CONFIG_X86_64
5490 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5491 CPU_BASED_CR8_LOAD_EXITING;
5495 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5496 CPU_BASED_CR3_LOAD_EXITING |
5497 CPU_BASED_INVLPG_EXITING;
5498 return exec_control;
5501 static bool vmx_rdrand_supported(void)
5503 return vmcs_config.cpu_based_2nd_exec_ctrl &
5504 SECONDARY_EXEC_RDRAND;
5507 static bool vmx_rdseed_supported(void)
5509 return vmcs_config.cpu_based_2nd_exec_ctrl &
5510 SECONDARY_EXEC_RDSEED;
5513 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
5515 struct kvm_vcpu *vcpu = &vmx->vcpu;
5517 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5518 if (!cpu_need_virtualize_apic_accesses(vcpu))
5519 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5521 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5523 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5524 enable_unrestricted_guest = 0;
5525 /* Enable INVPCID for non-ept guests may cause performance regression. */
5526 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5528 if (!enable_unrestricted_guest)
5529 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5531 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5532 if (!kvm_vcpu_apicv_active(vcpu))
5533 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5534 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5535 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5536 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5538 We can NOT enable shadow_vmcs here because we don't have yet
5541 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5544 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5546 if (vmx_xsaves_supported()) {
5547 /* Exposing XSAVES only when XSAVE is exposed */
5548 bool xsaves_enabled =
5549 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
5550 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
5552 if (!xsaves_enabled)
5553 exec_control &= ~SECONDARY_EXEC_XSAVES;
5557 vmx->nested.nested_vmx_secondary_ctls_high |=
5558 SECONDARY_EXEC_XSAVES;
5560 vmx->nested.nested_vmx_secondary_ctls_high &=
5561 ~SECONDARY_EXEC_XSAVES;
5565 if (vmx_rdtscp_supported()) {
5566 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
5567 if (!rdtscp_enabled)
5568 exec_control &= ~SECONDARY_EXEC_RDTSCP;
5572 vmx->nested.nested_vmx_secondary_ctls_high |=
5573 SECONDARY_EXEC_RDTSCP;
5575 vmx->nested.nested_vmx_secondary_ctls_high &=
5576 ~SECONDARY_EXEC_RDTSCP;
5580 if (vmx_invpcid_supported()) {
5581 /* Exposing INVPCID only when PCID is exposed */
5582 bool invpcid_enabled =
5583 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
5584 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
5586 if (!invpcid_enabled) {
5587 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5588 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
5592 if (invpcid_enabled)
5593 vmx->nested.nested_vmx_secondary_ctls_high |=
5594 SECONDARY_EXEC_ENABLE_INVPCID;
5596 vmx->nested.nested_vmx_secondary_ctls_high &=
5597 ~SECONDARY_EXEC_ENABLE_INVPCID;
5601 if (vmx_rdrand_supported()) {
5602 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
5604 exec_control &= ~SECONDARY_EXEC_RDRAND;
5608 vmx->nested.nested_vmx_secondary_ctls_high |=
5609 SECONDARY_EXEC_RDRAND;
5611 vmx->nested.nested_vmx_secondary_ctls_high &=
5612 ~SECONDARY_EXEC_RDRAND;
5616 if (vmx_rdseed_supported()) {
5617 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
5619 exec_control &= ~SECONDARY_EXEC_RDSEED;
5623 vmx->nested.nested_vmx_secondary_ctls_high |=
5624 SECONDARY_EXEC_RDSEED;
5626 vmx->nested.nested_vmx_secondary_ctls_high &=
5627 ~SECONDARY_EXEC_RDSEED;
5631 vmx->secondary_exec_control = exec_control;
5634 static void ept_set_mmio_spte_mask(void)
5637 * EPT Misconfigurations can be generated if the value of bits 2:0
5638 * of an EPT paging-structure entry is 110b (write/execute).
5640 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5641 VMX_EPT_MISCONFIG_WX_VALUE);
5644 #define VMX_XSS_EXIT_BITMAP 0
5646 * Sets up the vmcs for emulated real mode.
5648 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5650 #ifdef CONFIG_X86_64
5656 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5657 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5659 if (enable_shadow_vmcs) {
5660 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5661 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5663 if (cpu_has_vmx_msr_bitmap())
5664 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
5666 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5669 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5670 vmx->hv_deadline_tsc = -1;
5672 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5674 if (cpu_has_secondary_exec_ctrls()) {
5675 vmx_compute_secondary_exec_control(vmx);
5676 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5677 vmx->secondary_exec_control);
5680 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5681 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5682 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5683 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5684 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5686 vmcs_write16(GUEST_INTR_STATUS, 0);
5688 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5689 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5693 vmcs_write32(PLE_GAP, ple_gap);
5694 vmx->ple_window = ple_window;
5695 vmx->ple_window_dirty = true;
5698 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5699 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5700 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5702 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5703 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
5704 vmx_set_constant_host_state(vmx);
5705 #ifdef CONFIG_X86_64
5706 rdmsrl(MSR_FS_BASE, a);
5707 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5708 rdmsrl(MSR_GS_BASE, a);
5709 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5711 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5712 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5715 if (cpu_has_vmx_vmfunc())
5716 vmcs_write64(VM_FUNCTION_CONTROL, 0);
5718 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5719 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5720 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5721 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5722 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5724 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5725 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5727 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5728 u32 index = vmx_msr_index[i];
5729 u32 data_low, data_high;
5732 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5734 if (wrmsr_safe(index, data_low, data_high) < 0)
5736 vmx->guest_msrs[j].index = i;
5737 vmx->guest_msrs[j].data = 0;
5738 vmx->guest_msrs[j].mask = -1ull;
5742 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
5743 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
5745 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5747 /* 22.2.1, 20.8.1 */
5748 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5750 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5751 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5753 set_cr4_guest_host_mask(vmx);
5755 if (vmx_xsaves_supported())
5756 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5759 ASSERT(vmx->pml_pg);
5760 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5761 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5767 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5769 struct vcpu_vmx *vmx = to_vmx(vcpu);
5770 struct msr_data apic_base_msr;
5773 vmx->rmode.vm86_active = 0;
5776 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5777 kvm_set_cr8(vcpu, 0);
5780 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5781 MSR_IA32_APICBASE_ENABLE;
5782 if (kvm_vcpu_is_reset_bsp(vcpu))
5783 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5784 apic_base_msr.host_initiated = true;
5785 kvm_set_apic_base(vcpu, &apic_base_msr);
5788 vmx_segment_cache_clear(vmx);
5790 seg_setup(VCPU_SREG_CS);
5791 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5792 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5794 seg_setup(VCPU_SREG_DS);
5795 seg_setup(VCPU_SREG_ES);
5796 seg_setup(VCPU_SREG_FS);
5797 seg_setup(VCPU_SREG_GS);
5798 seg_setup(VCPU_SREG_SS);
5800 vmcs_write16(GUEST_TR_SELECTOR, 0);
5801 vmcs_writel(GUEST_TR_BASE, 0);
5802 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5803 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5805 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5806 vmcs_writel(GUEST_LDTR_BASE, 0);
5807 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5808 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5811 vmcs_write32(GUEST_SYSENTER_CS, 0);
5812 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5813 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5814 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5817 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
5818 kvm_rip_write(vcpu, 0xfff0);
5820 vmcs_writel(GUEST_GDTR_BASE, 0);
5821 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5823 vmcs_writel(GUEST_IDTR_BASE, 0);
5824 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5826 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5827 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5828 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5832 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5834 if (cpu_has_vmx_tpr_shadow() && !init_event) {
5835 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5836 if (cpu_need_tpr_shadow(vcpu))
5837 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5838 __pa(vcpu->arch.apic->regs));
5839 vmcs_write32(TPR_THRESHOLD, 0);
5842 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5845 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5847 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5848 vmx->vcpu.arch.cr0 = cr0;
5849 vmx_set_cr0(vcpu, cr0); /* enter rmode */
5850 vmx_set_cr4(vcpu, 0);
5851 vmx_set_efer(vcpu, 0);
5853 update_exception_bitmap(vcpu);
5855 vpid_sync_context(vmx->vpid);
5859 * In nested virtualization, check if L1 asked to exit on external interrupts.
5860 * For most existing hypervisors, this will always return true.
5862 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5864 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5865 PIN_BASED_EXT_INTR_MASK;
5869 * In nested virtualization, check if L1 has set
5870 * VM_EXIT_ACK_INTR_ON_EXIT
5872 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5874 return get_vmcs12(vcpu)->vm_exit_controls &
5875 VM_EXIT_ACK_INTR_ON_EXIT;
5878 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5880 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5881 PIN_BASED_NMI_EXITING;
5884 static void enable_irq_window(struct kvm_vcpu *vcpu)
5886 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5887 CPU_BASED_VIRTUAL_INTR_PENDING);
5890 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5892 if (!cpu_has_virtual_nmis() ||
5893 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5894 enable_irq_window(vcpu);
5898 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5899 CPU_BASED_VIRTUAL_NMI_PENDING);
5902 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5904 struct vcpu_vmx *vmx = to_vmx(vcpu);
5906 int irq = vcpu->arch.interrupt.nr;
5908 trace_kvm_inj_virq(irq);
5910 ++vcpu->stat.irq_injections;
5911 if (vmx->rmode.vm86_active) {
5913 if (vcpu->arch.interrupt.soft)
5914 inc_eip = vcpu->arch.event_exit_inst_len;
5915 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5916 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5919 intr = irq | INTR_INFO_VALID_MASK;
5920 if (vcpu->arch.interrupt.soft) {
5921 intr |= INTR_TYPE_SOFT_INTR;
5922 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5923 vmx->vcpu.arch.event_exit_inst_len);
5925 intr |= INTR_TYPE_EXT_INTR;
5926 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5929 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5931 struct vcpu_vmx *vmx = to_vmx(vcpu);
5933 if (!cpu_has_virtual_nmis()) {
5935 * Tracking the NMI-blocked state in software is built upon
5936 * finding the next open IRQ window. This, in turn, depends on
5937 * well-behaving guests: They have to keep IRQs disabled at
5938 * least as long as the NMI handler runs. Otherwise we may
5939 * cause NMI nesting, maybe breaking the guest. But as this is
5940 * highly unlikely, we can live with the residual risk.
5942 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
5943 vmx->loaded_vmcs->vnmi_blocked_time = 0;
5946 ++vcpu->stat.nmi_injections;
5947 vmx->loaded_vmcs->nmi_known_unmasked = false;
5949 if (vmx->rmode.vm86_active) {
5950 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5951 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5955 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5956 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5959 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5961 struct vcpu_vmx *vmx = to_vmx(vcpu);
5964 if (!cpu_has_virtual_nmis())
5965 return vmx->loaded_vmcs->soft_vnmi_blocked;
5966 if (vmx->loaded_vmcs->nmi_known_unmasked)
5968 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5969 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5973 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5975 struct vcpu_vmx *vmx = to_vmx(vcpu);
5977 if (!cpu_has_virtual_nmis()) {
5978 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
5979 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
5980 vmx->loaded_vmcs->vnmi_blocked_time = 0;
5983 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5985 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5986 GUEST_INTR_STATE_NMI);
5988 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5989 GUEST_INTR_STATE_NMI);
5993 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5995 if (to_vmx(vcpu)->nested.nested_run_pending)
5998 if (!cpu_has_virtual_nmis() &&
5999 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
6002 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6003 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
6004 | GUEST_INTR_STATE_NMI));
6007 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
6009 return (!to_vmx(vcpu)->nested.nested_run_pending &&
6010 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
6011 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
6012 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
6015 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
6019 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
6023 kvm->arch.tss_addr = addr;
6024 return init_rmode_tss(kvm);
6027 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6032 * Update instruction length as we may reinject the exception
6033 * from user space while in guest debugging mode.
6035 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
6036 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6037 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
6041 if (vcpu->guest_debug &
6042 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
6059 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
6060 int vec, u32 err_code)
6063 * Instruction with address size override prefix opcode 0x67
6064 * Cause the #SS fault with 0 error code in VM86 mode.
6066 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
6067 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
6068 if (vcpu->arch.halt_request) {
6069 vcpu->arch.halt_request = 0;
6070 return kvm_vcpu_halt(vcpu);
6078 * Forward all other exceptions that are valid in real mode.
6079 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
6080 * the required debugging infrastructure rework.
6082 kvm_queue_exception(vcpu, vec);
6087 * Trigger machine check on the host. We assume all the MSRs are already set up
6088 * by the CPU and that we still run on the same CPU as the MCE occurred on.
6089 * We pass a fake environment to the machine check handler because we want
6090 * the guest to be always treated like user space, no matter what context
6091 * it used internally.
6093 static void kvm_machine_check(void)
6095 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
6096 struct pt_regs regs = {
6097 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
6098 .flags = X86_EFLAGS_IF,
6101 do_machine_check(®s, 0);
6105 static int handle_machine_check(struct kvm_vcpu *vcpu)
6107 /* already handled by vcpu_run */
6111 static int handle_exception(struct kvm_vcpu *vcpu)
6113 struct vcpu_vmx *vmx = to_vmx(vcpu);
6114 struct kvm_run *kvm_run = vcpu->run;
6115 u32 intr_info, ex_no, error_code;
6116 unsigned long cr2, rip, dr6;
6118 enum emulation_result er;
6120 vect_info = vmx->idt_vectoring_info;
6121 intr_info = vmx->exit_intr_info;
6123 if (is_machine_check(intr_info))
6124 return handle_machine_check(vcpu);
6126 if (is_nmi(intr_info))
6127 return 1; /* already handled by vmx_vcpu_run() */
6129 if (is_invalid_opcode(intr_info)) {
6130 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
6131 if (er == EMULATE_USER_EXIT)
6133 if (er != EMULATE_DONE)
6134 kvm_queue_exception(vcpu, UD_VECTOR);
6139 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6140 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6143 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
6144 * MMIO, it is better to report an internal error.
6145 * See the comments in vmx_handle_exit.
6147 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
6148 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
6149 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6150 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
6151 vcpu->run->internal.ndata = 3;
6152 vcpu->run->internal.data[0] = vect_info;
6153 vcpu->run->internal.data[1] = intr_info;
6154 vcpu->run->internal.data[2] = error_code;
6158 if (is_page_fault(intr_info)) {
6159 cr2 = vmcs_readl(EXIT_QUALIFICATION);
6160 /* EPT won't cause page fault directly */
6161 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
6162 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
6166 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
6168 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
6169 return handle_rmode_exception(vcpu, ex_no, error_code);
6173 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
6176 dr6 = vmcs_readl(EXIT_QUALIFICATION);
6177 if (!(vcpu->guest_debug &
6178 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
6179 vcpu->arch.dr6 &= ~15;
6180 vcpu->arch.dr6 |= dr6 | DR6_RTM;
6181 if (is_icebp(intr_info))
6182 skip_emulated_instruction(vcpu);
6184 kvm_queue_exception(vcpu, DB_VECTOR);
6187 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
6188 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
6192 * Update instruction length as we may reinject #BP from
6193 * user space while in guest debugging mode. Reading it for
6194 * #DB as well causes no harm, it is not used in that case.
6196 vmx->vcpu.arch.event_exit_inst_len =
6197 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6198 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6199 rip = kvm_rip_read(vcpu);
6200 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
6201 kvm_run->debug.arch.exception = ex_no;
6204 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
6205 kvm_run->ex.exception = ex_no;
6206 kvm_run->ex.error_code = error_code;
6212 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6214 ++vcpu->stat.irq_exits;
6218 static int handle_triple_fault(struct kvm_vcpu *vcpu)
6220 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6221 vcpu->mmio_needed = 0;
6225 static int handle_io(struct kvm_vcpu *vcpu)
6227 unsigned long exit_qualification;
6228 int size, in, string, ret;
6231 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6232 string = (exit_qualification & 16) != 0;
6233 in = (exit_qualification & 8) != 0;
6235 ++vcpu->stat.io_exits;
6238 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6240 port = exit_qualification >> 16;
6241 size = (exit_qualification & 7) + 1;
6243 ret = kvm_skip_emulated_instruction(vcpu);
6246 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6247 * KVM_EXIT_DEBUG here.
6249 return kvm_fast_pio_out(vcpu, size, port) && ret;
6253 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
6256 * Patch in the VMCALL instruction:
6258 hypercall[0] = 0x0f;
6259 hypercall[1] = 0x01;
6260 hypercall[2] = 0xc1;
6263 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6264 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6266 if (is_guest_mode(vcpu)) {
6267 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6268 unsigned long orig_val = val;
6271 * We get here when L2 changed cr0 in a way that did not change
6272 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6273 * but did change L0 shadowed bits. So we first calculate the
6274 * effective cr0 value that L1 would like to write into the
6275 * hardware. It consists of the L2-owned bits from the new
6276 * value combined with the L1-owned bits from L1's guest_cr0.
6278 val = (val & ~vmcs12->cr0_guest_host_mask) |
6279 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6281 if (!nested_guest_cr0_valid(vcpu, val))
6284 if (kvm_set_cr0(vcpu, val))
6286 vmcs_writel(CR0_READ_SHADOW, orig_val);
6289 if (to_vmx(vcpu)->nested.vmxon &&
6290 !nested_host_cr0_valid(vcpu, val))
6293 return kvm_set_cr0(vcpu, val);
6297 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6299 if (is_guest_mode(vcpu)) {
6300 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6301 unsigned long orig_val = val;
6303 /* analogously to handle_set_cr0 */
6304 val = (val & ~vmcs12->cr4_guest_host_mask) |
6305 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6306 if (kvm_set_cr4(vcpu, val))
6308 vmcs_writel(CR4_READ_SHADOW, orig_val);
6311 return kvm_set_cr4(vcpu, val);
6314 static int handle_cr(struct kvm_vcpu *vcpu)
6316 unsigned long exit_qualification, val;
6322 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6323 cr = exit_qualification & 15;
6324 reg = (exit_qualification >> 8) & 15;
6325 switch ((exit_qualification >> 4) & 3) {
6326 case 0: /* mov to cr */
6327 val = kvm_register_readl(vcpu, reg);
6328 trace_kvm_cr_write(cr, val);
6331 err = handle_set_cr0(vcpu, val);
6332 return kvm_complete_insn_gp(vcpu, err);
6334 err = kvm_set_cr3(vcpu, val);
6335 return kvm_complete_insn_gp(vcpu, err);
6337 err = handle_set_cr4(vcpu, val);
6338 return kvm_complete_insn_gp(vcpu, err);
6340 u8 cr8_prev = kvm_get_cr8(vcpu);
6342 err = kvm_set_cr8(vcpu, cr8);
6343 ret = kvm_complete_insn_gp(vcpu, err);
6344 if (lapic_in_kernel(vcpu))
6346 if (cr8_prev <= cr8)
6349 * TODO: we might be squashing a
6350 * KVM_GUESTDBG_SINGLESTEP-triggered
6351 * KVM_EXIT_DEBUG here.
6353 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
6359 WARN_ONCE(1, "Guest should always own CR0.TS");
6360 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6361 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6362 return kvm_skip_emulated_instruction(vcpu);
6363 case 1: /*mov from cr*/
6366 val = kvm_read_cr3(vcpu);
6367 kvm_register_write(vcpu, reg, val);
6368 trace_kvm_cr_read(cr, val);
6369 return kvm_skip_emulated_instruction(vcpu);
6371 val = kvm_get_cr8(vcpu);
6372 kvm_register_write(vcpu, reg, val);
6373 trace_kvm_cr_read(cr, val);
6374 return kvm_skip_emulated_instruction(vcpu);
6378 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
6379 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
6380 kvm_lmsw(vcpu, val);
6382 return kvm_skip_emulated_instruction(vcpu);
6386 vcpu->run->exit_reason = 0;
6387 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6388 (int)(exit_qualification >> 4) & 3, cr);
6392 static int handle_dr(struct kvm_vcpu *vcpu)
6394 unsigned long exit_qualification;
6397 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6398 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6400 /* First, if DR does not exist, trigger UD */
6401 if (!kvm_require_dr(vcpu, dr))
6404 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6405 if (!kvm_require_cpl(vcpu, 0))
6407 dr7 = vmcs_readl(GUEST_DR7);
6410 * As the vm-exit takes precedence over the debug trap, we
6411 * need to emulate the latter, either for the host or the
6412 * guest debugging itself.
6414 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6415 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
6416 vcpu->run->debug.arch.dr7 = dr7;
6417 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6418 vcpu->run->debug.arch.exception = DB_VECTOR;
6419 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
6422 vcpu->arch.dr6 &= ~15;
6423 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
6424 kvm_queue_exception(vcpu, DB_VECTOR);
6429 if (vcpu->guest_debug == 0) {
6430 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6431 CPU_BASED_MOV_DR_EXITING);
6434 * No more DR vmexits; force a reload of the debug registers
6435 * and reenter on this instruction. The next vmexit will
6436 * retrieve the full state of the debug registers.
6438 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6442 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6443 if (exit_qualification & TYPE_MOV_FROM_DR) {
6446 if (kvm_get_dr(vcpu, dr, &val))
6448 kvm_register_write(vcpu, reg, val);
6450 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6453 return kvm_skip_emulated_instruction(vcpu);
6456 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6458 return vcpu->arch.dr6;
6461 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6465 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6467 get_debugreg(vcpu->arch.db[0], 0);
6468 get_debugreg(vcpu->arch.db[1], 1);
6469 get_debugreg(vcpu->arch.db[2], 2);
6470 get_debugreg(vcpu->arch.db[3], 3);
6471 get_debugreg(vcpu->arch.dr6, 6);
6472 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6474 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6475 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6478 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6480 vmcs_writel(GUEST_DR7, val);
6483 static int handle_cpuid(struct kvm_vcpu *vcpu)
6485 return kvm_emulate_cpuid(vcpu);
6488 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6490 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6491 struct msr_data msr_info;
6493 msr_info.index = ecx;
6494 msr_info.host_initiated = false;
6495 if (vmx_get_msr(vcpu, &msr_info)) {
6496 trace_kvm_msr_read_ex(ecx);
6497 kvm_inject_gp(vcpu, 0);
6501 trace_kvm_msr_read(ecx, msr_info.data);
6503 /* FIXME: handling of bits 32:63 of rax, rdx */
6504 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6505 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6506 return kvm_skip_emulated_instruction(vcpu);
6509 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6511 struct msr_data msr;
6512 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6513 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6514 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6518 msr.host_initiated = false;
6519 if (kvm_set_msr(vcpu, &msr) != 0) {
6520 trace_kvm_msr_write_ex(ecx, data);
6521 kvm_inject_gp(vcpu, 0);
6525 trace_kvm_msr_write(ecx, data);
6526 return kvm_skip_emulated_instruction(vcpu);
6529 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6531 kvm_apic_update_ppr(vcpu);
6535 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6537 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6538 CPU_BASED_VIRTUAL_INTR_PENDING);
6540 kvm_make_request(KVM_REQ_EVENT, vcpu);
6542 ++vcpu->stat.irq_window_exits;
6546 static int handle_halt(struct kvm_vcpu *vcpu)
6548 return kvm_emulate_halt(vcpu);
6551 static int handle_vmcall(struct kvm_vcpu *vcpu)
6553 return kvm_emulate_hypercall(vcpu);
6556 static int handle_invd(struct kvm_vcpu *vcpu)
6558 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6561 static int handle_invlpg(struct kvm_vcpu *vcpu)
6563 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6565 kvm_mmu_invlpg(vcpu, exit_qualification);
6566 return kvm_skip_emulated_instruction(vcpu);
6569 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6573 err = kvm_rdpmc(vcpu);
6574 return kvm_complete_insn_gp(vcpu, err);
6577 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6579 return kvm_emulate_wbinvd(vcpu);
6582 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6584 u64 new_bv = kvm_read_edx_eax(vcpu);
6585 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6587 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6588 return kvm_skip_emulated_instruction(vcpu);
6592 static int handle_xsaves(struct kvm_vcpu *vcpu)
6594 kvm_skip_emulated_instruction(vcpu);
6595 WARN(1, "this should never happen\n");
6599 static int handle_xrstors(struct kvm_vcpu *vcpu)
6601 kvm_skip_emulated_instruction(vcpu);
6602 WARN(1, "this should never happen\n");
6606 static int handle_apic_access(struct kvm_vcpu *vcpu)
6608 if (likely(fasteoi)) {
6609 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6610 int access_type, offset;
6612 access_type = exit_qualification & APIC_ACCESS_TYPE;
6613 offset = exit_qualification & APIC_ACCESS_OFFSET;
6615 * Sane guest uses MOV to write EOI, with written value
6616 * not cared. So make a short-circuit here by avoiding
6617 * heavy instruction emulation.
6619 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6620 (offset == APIC_EOI)) {
6621 kvm_lapic_set_eoi(vcpu);
6622 return kvm_skip_emulated_instruction(vcpu);
6625 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6628 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6630 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6631 int vector = exit_qualification & 0xff;
6633 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6634 kvm_apic_set_eoi_accelerated(vcpu, vector);
6638 static int handle_apic_write(struct kvm_vcpu *vcpu)
6640 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6641 u32 offset = exit_qualification & 0xfff;
6643 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6644 kvm_apic_write_nodecode(vcpu, offset);
6648 static int handle_task_switch(struct kvm_vcpu *vcpu)
6650 struct vcpu_vmx *vmx = to_vmx(vcpu);
6651 unsigned long exit_qualification;
6652 bool has_error_code = false;
6655 int reason, type, idt_v, idt_index;
6657 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6658 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6659 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6661 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6663 reason = (u32)exit_qualification >> 30;
6664 if (reason == TASK_SWITCH_GATE && idt_v) {
6666 case INTR_TYPE_NMI_INTR:
6667 vcpu->arch.nmi_injected = false;
6668 vmx_set_nmi_mask(vcpu, true);
6670 case INTR_TYPE_EXT_INTR:
6671 case INTR_TYPE_SOFT_INTR:
6672 kvm_clear_interrupt_queue(vcpu);
6674 case INTR_TYPE_HARD_EXCEPTION:
6675 if (vmx->idt_vectoring_info &
6676 VECTORING_INFO_DELIVER_CODE_MASK) {
6677 has_error_code = true;
6679 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6682 case INTR_TYPE_SOFT_EXCEPTION:
6683 kvm_clear_exception_queue(vcpu);
6689 tss_selector = exit_qualification;
6691 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6692 type != INTR_TYPE_EXT_INTR &&
6693 type != INTR_TYPE_NMI_INTR))
6694 skip_emulated_instruction(vcpu);
6696 if (kvm_task_switch(vcpu, tss_selector,
6697 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6698 has_error_code, error_code) == EMULATE_FAIL) {
6699 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6700 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6701 vcpu->run->internal.ndata = 0;
6706 * TODO: What about debug traps on tss switch?
6707 * Are we supposed to inject them and update dr6?
6713 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6715 unsigned long exit_qualification;
6719 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6722 * EPT violation happened while executing iret from NMI,
6723 * "blocked by NMI" bit has to be set before next VM entry.
6724 * There are errata that may cause this bit to not be set:
6727 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6728 cpu_has_virtual_nmis() &&
6729 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6730 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6732 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6733 trace_kvm_page_fault(gpa, exit_qualification);
6735 /* Is it a read fault? */
6736 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6737 ? PFERR_USER_MASK : 0;
6738 /* Is it a write fault? */
6739 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6740 ? PFERR_WRITE_MASK : 0;
6741 /* Is it a fetch fault? */
6742 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6743 ? PFERR_FETCH_MASK : 0;
6744 /* ept page table entry is present? */
6745 error_code |= (exit_qualification &
6746 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6747 EPT_VIOLATION_EXECUTABLE))
6748 ? PFERR_PRESENT_MASK : 0;
6750 error_code |= (exit_qualification & 0x100) != 0 ?
6751 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
6753 vcpu->arch.exit_qualification = exit_qualification;
6754 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6757 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6763 * A nested guest cannot optimize MMIO vmexits, because we have an
6764 * nGPA here instead of the required GPA.
6766 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6767 if (!is_guest_mode(vcpu) &&
6768 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6769 trace_kvm_fast_mmio(gpa);
6771 * Doing kvm_skip_emulated_instruction() depends on undefined
6772 * behavior: Intel's manual doesn't mandate
6773 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
6774 * occurs and while on real hardware it was observed to be set,
6775 * other hypervisors (namely Hyper-V) don't set it, we end up
6776 * advancing IP with some random value. Disable fast mmio when
6777 * running nested and keep it for real hardware in hope that
6778 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
6780 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
6781 return kvm_skip_emulated_instruction(vcpu);
6783 return x86_emulate_instruction(vcpu, gpa, EMULTYPE_SKIP,
6784 NULL, 0) == EMULATE_DONE;
6787 ret = kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
6791 /* It is the real ept misconfig */
6794 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6795 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6800 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6802 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6803 CPU_BASED_VIRTUAL_NMI_PENDING);
6804 ++vcpu->stat.nmi_window_exits;
6805 kvm_make_request(KVM_REQ_EVENT, vcpu);
6810 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6812 struct vcpu_vmx *vmx = to_vmx(vcpu);
6813 enum emulation_result err = EMULATE_DONE;
6816 bool intr_window_requested;
6817 unsigned count = 130;
6819 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6820 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6822 while (vmx->emulation_required && count-- != 0) {
6823 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6824 return handle_interrupt_window(&vmx->vcpu);
6826 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6829 err = emulate_instruction(vcpu, 0);
6831 if (err == EMULATE_USER_EXIT) {
6832 ++vcpu->stat.mmio_exits;
6837 if (err != EMULATE_DONE) {
6838 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6839 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6840 vcpu->run->internal.ndata = 0;
6844 if (vcpu->arch.halt_request) {
6845 vcpu->arch.halt_request = 0;
6846 ret = kvm_vcpu_halt(vcpu);
6850 if (signal_pending(current))
6860 static int __grow_ple_window(int val)
6862 if (ple_window_grow < 1)
6865 val = min(val, ple_window_actual_max);
6867 if (ple_window_grow < ple_window)
6868 val *= ple_window_grow;
6870 val += ple_window_grow;
6875 static int __shrink_ple_window(int val, int modifier, int minimum)
6880 if (modifier < ple_window)
6885 return max(val, minimum);
6888 static void grow_ple_window(struct kvm_vcpu *vcpu)
6890 struct vcpu_vmx *vmx = to_vmx(vcpu);
6891 int old = vmx->ple_window;
6893 vmx->ple_window = __grow_ple_window(old);
6895 if (vmx->ple_window != old)
6896 vmx->ple_window_dirty = true;
6898 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6901 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6903 struct vcpu_vmx *vmx = to_vmx(vcpu);
6904 int old = vmx->ple_window;
6906 vmx->ple_window = __shrink_ple_window(old,
6907 ple_window_shrink, ple_window);
6909 if (vmx->ple_window != old)
6910 vmx->ple_window_dirty = true;
6912 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6916 * ple_window_actual_max is computed to be one grow_ple_window() below
6917 * ple_window_max. (See __grow_ple_window for the reason.)
6918 * This prevents overflows, because ple_window_max is int.
6919 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6921 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6923 static void update_ple_window_actual_max(void)
6925 ple_window_actual_max =
6926 __shrink_ple_window(max(ple_window_max, ple_window),
6927 ple_window_grow, INT_MIN);
6931 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6933 static void wakeup_handler(void)
6935 struct kvm_vcpu *vcpu;
6936 int cpu = smp_processor_id();
6938 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6939 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6940 blocked_vcpu_list) {
6941 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6943 if (pi_test_on(pi_desc) == 1)
6944 kvm_vcpu_kick(vcpu);
6946 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6949 void vmx_enable_tdp(void)
6951 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6952 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6953 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6954 0ull, VMX_EPT_EXECUTABLE_MASK,
6955 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6956 VMX_EPT_RWX_MASK, 0ull);
6958 ept_set_mmio_spte_mask();
6962 static __init int hardware_setup(void)
6966 rdmsrl_safe(MSR_EFER, &host_efer);
6968 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6969 kvm_define_shared_msr(i, vmx_msr_index[i]);
6971 for (i = 0; i < VMX_BITMAP_NR; i++) {
6972 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6977 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6978 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6980 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6982 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6984 if (setup_vmcs_config(&vmcs_config) < 0) {
6989 if (boot_cpu_has(X86_FEATURE_NX))
6990 kvm_enable_efer_bits(EFER_NX);
6992 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6993 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6996 if (!cpu_has_vmx_shadow_vmcs())
6997 enable_shadow_vmcs = 0;
6998 if (enable_shadow_vmcs)
6999 init_vmcs_shadow_fields();
7001 if (!cpu_has_vmx_ept() ||
7002 !cpu_has_vmx_ept_4levels() ||
7003 !cpu_has_vmx_ept_mt_wb()) {
7005 enable_unrestricted_guest = 0;
7006 enable_ept_ad_bits = 0;
7009 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7010 enable_ept_ad_bits = 0;
7012 if (!cpu_has_vmx_unrestricted_guest())
7013 enable_unrestricted_guest = 0;
7015 if (!cpu_has_vmx_flexpriority())
7016 flexpriority_enabled = 0;
7019 * set_apic_access_page_addr() is used to reload apic access
7020 * page upon invalidation. No need to do anything if not
7021 * using the APIC_ACCESS_ADDR VMCS field.
7023 if (!flexpriority_enabled)
7024 kvm_x86_ops->set_apic_access_page_addr = NULL;
7026 if (!cpu_has_vmx_tpr_shadow())
7027 kvm_x86_ops->update_cr8_intercept = NULL;
7029 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7030 kvm_disable_largepages();
7032 if (!cpu_has_vmx_ple())
7035 if (!cpu_has_vmx_apicv()) {
7037 kvm_x86_ops->sync_pir_to_irr = NULL;
7040 if (cpu_has_vmx_tsc_scaling()) {
7041 kvm_has_tsc_control = true;
7042 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7043 kvm_tsc_scaling_ratio_frac_bits = 48;
7046 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7053 update_ple_window_actual_max();
7056 * Only enable PML when hardware supports PML feature, and both EPT
7057 * and EPT A/D bit features are enabled -- PML depends on them to work.
7059 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7063 kvm_x86_ops->slot_enable_log_dirty = NULL;
7064 kvm_x86_ops->slot_disable_log_dirty = NULL;
7065 kvm_x86_ops->flush_log_dirty = NULL;
7066 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7069 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7072 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7073 cpu_preemption_timer_multi =
7074 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7076 kvm_x86_ops->set_hv_timer = NULL;
7077 kvm_x86_ops->cancel_hv_timer = NULL;
7080 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
7082 kvm_mce_cap_supported |= MCG_LMCE_P;
7084 return alloc_kvm_area();
7087 for (i = 0; i < VMX_BITMAP_NR; i++)
7088 free_page((unsigned long)vmx_bitmap[i]);
7093 static __exit void hardware_unsetup(void)
7097 for (i = 0; i < VMX_BITMAP_NR; i++)
7098 free_page((unsigned long)vmx_bitmap[i]);
7104 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
7105 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
7107 static int handle_pause(struct kvm_vcpu *vcpu)
7110 grow_ple_window(vcpu);
7113 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
7114 * VM-execution control is ignored if CPL > 0. OTOH, KVM
7115 * never set PAUSE_EXITING and just set PLE if supported,
7116 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
7118 kvm_vcpu_on_spin(vcpu, true);
7119 return kvm_skip_emulated_instruction(vcpu);
7122 static int handle_nop(struct kvm_vcpu *vcpu)
7124 return kvm_skip_emulated_instruction(vcpu);
7127 static int handle_mwait(struct kvm_vcpu *vcpu)
7129 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
7130 return handle_nop(vcpu);
7133 static int handle_invalid_op(struct kvm_vcpu *vcpu)
7135 kvm_queue_exception(vcpu, UD_VECTOR);
7139 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
7144 static int handle_monitor(struct kvm_vcpu *vcpu)
7146 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
7147 return handle_nop(vcpu);
7151 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7152 * set the success or error code of an emulated VMX instruction, as specified
7153 * by Vol 2B, VMX Instruction Reference, "Conventions".
7155 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
7157 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
7158 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7159 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
7162 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
7164 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7165 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
7166 X86_EFLAGS_SF | X86_EFLAGS_OF))
7170 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
7171 u32 vm_instruction_error)
7173 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
7175 * failValid writes the error number to the current VMCS, which
7176 * can't be done there isn't a current VMCS.
7178 nested_vmx_failInvalid(vcpu);
7181 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
7182 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
7183 X86_EFLAGS_SF | X86_EFLAGS_OF))
7185 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
7187 * We don't need to force a shadow sync because
7188 * VM_INSTRUCTION_ERROR is not shadowed
7192 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
7194 /* TODO: not to reset guest simply here. */
7195 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7196 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
7199 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
7201 struct vcpu_vmx *vmx =
7202 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
7204 vmx->nested.preemption_timer_expired = true;
7205 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
7206 kvm_vcpu_kick(&vmx->vcpu);
7208 return HRTIMER_NORESTART;
7212 * Decode the memory-address operand of a vmx instruction, as recorded on an
7213 * exit caused by such an instruction (run by a guest hypervisor).
7214 * On success, returns 0. When the operand is invalid, returns 1 and throws
7217 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7218 unsigned long exit_qualification,
7219 u32 vmx_instruction_info, bool wr, gva_t *ret)
7223 struct kvm_segment s;
7226 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7227 * Execution", on an exit, vmx_instruction_info holds most of the
7228 * addressing components of the operand. Only the displacement part
7229 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7230 * For how an actual address is calculated from all these components,
7231 * refer to Vol. 1, "Operand Addressing".
7233 int scaling = vmx_instruction_info & 3;
7234 int addr_size = (vmx_instruction_info >> 7) & 7;
7235 bool is_reg = vmx_instruction_info & (1u << 10);
7236 int seg_reg = (vmx_instruction_info >> 15) & 7;
7237 int index_reg = (vmx_instruction_info >> 18) & 0xf;
7238 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7239 int base_reg = (vmx_instruction_info >> 23) & 0xf;
7240 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
7243 kvm_queue_exception(vcpu, UD_VECTOR);
7247 /* Addr = segment_base + offset */
7248 /* offset = base + [index * scale] + displacement */
7249 off = exit_qualification; /* holds the displacement */
7251 off += kvm_register_read(vcpu, base_reg);
7253 off += kvm_register_read(vcpu, index_reg)<<scaling;
7254 vmx_get_segment(vcpu, &s, seg_reg);
7255 *ret = s.base + off;
7257 if (addr_size == 1) /* 32 bit */
7260 /* Checks for #GP/#SS exceptions. */
7262 if (is_long_mode(vcpu)) {
7263 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7264 * non-canonical form. This is the only check on the memory
7265 * destination for long mode!
7267 exn = is_noncanonical_address(*ret, vcpu);
7268 } else if (is_protmode(vcpu)) {
7269 /* Protected mode: apply checks for segment validity in the
7271 * - segment type check (#GP(0) may be thrown)
7272 * - usability check (#GP(0)/#SS(0))
7273 * - limit check (#GP(0)/#SS(0))
7276 /* #GP(0) if the destination operand is located in a
7277 * read-only data segment or any code segment.
7279 exn = ((s.type & 0xa) == 0 || (s.type & 8));
7281 /* #GP(0) if the source operand is located in an
7282 * execute-only code segment
7284 exn = ((s.type & 0xa) == 8);
7286 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7289 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7291 exn = (s.unusable != 0);
7292 /* Protected mode: #GP(0)/#SS(0) if the memory
7293 * operand is outside the segment limit.
7295 exn = exn || (off + sizeof(u64) > s.limit);
7298 kvm_queue_exception_e(vcpu,
7299 seg_reg == VCPU_SREG_SS ?
7300 SS_VECTOR : GP_VECTOR,
7308 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
7311 struct x86_exception e;
7313 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7314 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
7317 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
7318 sizeof(*vmpointer), &e)) {
7319 kvm_inject_page_fault(vcpu, &e);
7326 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7328 struct vcpu_vmx *vmx = to_vmx(vcpu);
7329 struct vmcs *shadow_vmcs;
7332 r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7336 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7337 if (!vmx->nested.cached_vmcs12)
7338 goto out_cached_vmcs12;
7340 if (enable_shadow_vmcs) {
7341 shadow_vmcs = alloc_vmcs();
7343 goto out_shadow_vmcs;
7344 /* mark vmcs as shadow */
7345 shadow_vmcs->revision_id |= (1u << 31);
7346 /* init shadow vmcs */
7347 vmcs_clear(shadow_vmcs);
7348 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7351 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7352 HRTIMER_MODE_REL_PINNED);
7353 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7355 vmx->nested.vmxon = true;
7359 kfree(vmx->nested.cached_vmcs12);
7362 free_loaded_vmcs(&vmx->nested.vmcs02);
7369 * Emulate the VMXON instruction.
7370 * Currently, we just remember that VMX is active, and do not save or even
7371 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7372 * do not currently need to store anything in that guest-allocated memory
7373 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7374 * argument is different from the VMXON pointer (which the spec says they do).
7376 static int handle_vmon(struct kvm_vcpu *vcpu)
7381 struct vcpu_vmx *vmx = to_vmx(vcpu);
7382 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7383 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7386 * The Intel VMX Instruction Reference lists a bunch of bits that are
7387 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7388 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7389 * Otherwise, we should fail with #UD. But most faulting conditions
7390 * have already been checked by hardware, prior to the VM-exit for
7391 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7392 * that bit set to 1 in non-root mode.
7394 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7395 kvm_queue_exception(vcpu, UD_VECTOR);
7399 if (vmx->nested.vmxon) {
7400 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7401 return kvm_skip_emulated_instruction(vcpu);
7404 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7405 != VMXON_NEEDED_FEATURES) {
7406 kvm_inject_gp(vcpu, 0);
7410 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7415 * The first 4 bytes of VMXON region contain the supported
7416 * VMCS revision identifier
7418 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7419 * which replaces physical address width with 32
7421 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7422 nested_vmx_failInvalid(vcpu);
7423 return kvm_skip_emulated_instruction(vcpu);
7426 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7427 if (is_error_page(page)) {
7428 nested_vmx_failInvalid(vcpu);
7429 return kvm_skip_emulated_instruction(vcpu);
7431 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7433 kvm_release_page_clean(page);
7434 nested_vmx_failInvalid(vcpu);
7435 return kvm_skip_emulated_instruction(vcpu);
7438 kvm_release_page_clean(page);
7440 vmx->nested.vmxon_ptr = vmptr;
7441 ret = enter_vmx_operation(vcpu);
7445 nested_vmx_succeed(vcpu);
7446 return kvm_skip_emulated_instruction(vcpu);
7450 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7451 * for running VMX instructions (except VMXON, whose prerequisites are
7452 * slightly different). It also specifies what exception to inject otherwise.
7453 * Note that many of these exceptions have priority over VM exits, so they
7454 * don't have to be checked again here.
7456 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7458 if (!to_vmx(vcpu)->nested.vmxon) {
7459 kvm_queue_exception(vcpu, UD_VECTOR);
7465 static void vmx_disable_shadow_vmcs(struct vcpu_vmx *vmx)
7467 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL, SECONDARY_EXEC_SHADOW_VMCS);
7468 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7471 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7473 if (vmx->nested.current_vmptr == -1ull)
7476 if (enable_shadow_vmcs) {
7477 /* copy to memory all shadowed fields in case
7478 they were modified */
7479 copy_shadow_to_vmcs12(vmx);
7480 vmx->nested.sync_shadow_vmcs = false;
7481 vmx_disable_shadow_vmcs(vmx);
7483 vmx->nested.posted_intr_nv = -1;
7485 /* Flush VMCS12 to guest memory */
7486 kvm_vcpu_write_guest_page(&vmx->vcpu,
7487 vmx->nested.current_vmptr >> PAGE_SHIFT,
7488 vmx->nested.cached_vmcs12, 0, VMCS12_SIZE);
7490 vmx->nested.current_vmptr = -1ull;
7494 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7495 * just stops using VMX.
7497 static void free_nested(struct vcpu_vmx *vmx)
7499 if (!vmx->nested.vmxon)
7502 vmx->nested.vmxon = false;
7503 free_vpid(vmx->nested.vpid02);
7504 vmx->nested.posted_intr_nv = -1;
7505 vmx->nested.current_vmptr = -1ull;
7506 if (enable_shadow_vmcs) {
7507 vmx_disable_shadow_vmcs(vmx);
7508 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7509 free_vmcs(vmx->vmcs01.shadow_vmcs);
7510 vmx->vmcs01.shadow_vmcs = NULL;
7512 kfree(vmx->nested.cached_vmcs12);
7513 /* Unpin physical memory we referred to in the vmcs02 */
7514 if (vmx->nested.apic_access_page) {
7515 kvm_release_page_dirty(vmx->nested.apic_access_page);
7516 vmx->nested.apic_access_page = NULL;
7518 if (vmx->nested.virtual_apic_page) {
7519 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
7520 vmx->nested.virtual_apic_page = NULL;
7522 if (vmx->nested.pi_desc_page) {
7523 kunmap(vmx->nested.pi_desc_page);
7524 kvm_release_page_dirty(vmx->nested.pi_desc_page);
7525 vmx->nested.pi_desc_page = NULL;
7526 vmx->nested.pi_desc = NULL;
7529 free_loaded_vmcs(&vmx->nested.vmcs02);
7532 /* Emulate the VMXOFF instruction */
7533 static int handle_vmoff(struct kvm_vcpu *vcpu)
7535 if (!nested_vmx_check_permission(vcpu))
7537 free_nested(to_vmx(vcpu));
7538 nested_vmx_succeed(vcpu);
7539 return kvm_skip_emulated_instruction(vcpu);
7542 /* Emulate the VMCLEAR instruction */
7543 static int handle_vmclear(struct kvm_vcpu *vcpu)
7545 struct vcpu_vmx *vmx = to_vmx(vcpu);
7549 if (!nested_vmx_check_permission(vcpu))
7552 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7555 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7556 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7557 return kvm_skip_emulated_instruction(vcpu);
7560 if (vmptr == vmx->nested.vmxon_ptr) {
7561 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7562 return kvm_skip_emulated_instruction(vcpu);
7565 if (vmptr == vmx->nested.current_vmptr)
7566 nested_release_vmcs12(vmx);
7568 kvm_vcpu_write_guest(vcpu,
7569 vmptr + offsetof(struct vmcs12, launch_state),
7570 &zero, sizeof(zero));
7572 nested_vmx_succeed(vcpu);
7573 return kvm_skip_emulated_instruction(vcpu);
7576 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7578 /* Emulate the VMLAUNCH instruction */
7579 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7581 return nested_vmx_run(vcpu, true);
7584 /* Emulate the VMRESUME instruction */
7585 static int handle_vmresume(struct kvm_vcpu *vcpu)
7588 return nested_vmx_run(vcpu, false);
7592 * Read a vmcs12 field. Since these can have varying lengths and we return
7593 * one type, we chose the biggest type (u64) and zero-extend the return value
7594 * to that size. Note that the caller, handle_vmread, might need to use only
7595 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7596 * 64-bit fields are to be returned).
7598 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7599 unsigned long field, u64 *ret)
7601 short offset = vmcs_field_to_offset(field);
7607 p = ((char *)(get_vmcs12(vcpu))) + offset;
7609 switch (vmcs_field_type(field)) {
7610 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7611 *ret = *((natural_width *)p);
7613 case VMCS_FIELD_TYPE_U16:
7616 case VMCS_FIELD_TYPE_U32:
7619 case VMCS_FIELD_TYPE_U64:
7629 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7630 unsigned long field, u64 field_value){
7631 short offset = vmcs_field_to_offset(field);
7632 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7636 switch (vmcs_field_type(field)) {
7637 case VMCS_FIELD_TYPE_U16:
7638 *(u16 *)p = field_value;
7640 case VMCS_FIELD_TYPE_U32:
7641 *(u32 *)p = field_value;
7643 case VMCS_FIELD_TYPE_U64:
7644 *(u64 *)p = field_value;
7646 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7647 *(natural_width *)p = field_value;
7656 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7659 unsigned long field;
7661 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7662 const unsigned long *fields = shadow_read_write_fields;
7663 const int num_fields = max_shadow_read_write_fields;
7667 vmcs_load(shadow_vmcs);
7669 for (i = 0; i < num_fields; i++) {
7671 switch (vmcs_field_type(field)) {
7672 case VMCS_FIELD_TYPE_U16:
7673 field_value = vmcs_read16(field);
7675 case VMCS_FIELD_TYPE_U32:
7676 field_value = vmcs_read32(field);
7678 case VMCS_FIELD_TYPE_U64:
7679 field_value = vmcs_read64(field);
7681 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7682 field_value = vmcs_readl(field);
7688 vmcs12_write_any(&vmx->vcpu, field, field_value);
7691 vmcs_clear(shadow_vmcs);
7692 vmcs_load(vmx->loaded_vmcs->vmcs);
7697 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7699 const unsigned long *fields[] = {
7700 shadow_read_write_fields,
7701 shadow_read_only_fields
7703 const int max_fields[] = {
7704 max_shadow_read_write_fields,
7705 max_shadow_read_only_fields
7708 unsigned long field;
7709 u64 field_value = 0;
7710 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7712 vmcs_load(shadow_vmcs);
7714 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7715 for (i = 0; i < max_fields[q]; i++) {
7716 field = fields[q][i];
7717 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7719 switch (vmcs_field_type(field)) {
7720 case VMCS_FIELD_TYPE_U16:
7721 vmcs_write16(field, (u16)field_value);
7723 case VMCS_FIELD_TYPE_U32:
7724 vmcs_write32(field, (u32)field_value);
7726 case VMCS_FIELD_TYPE_U64:
7727 vmcs_write64(field, (u64)field_value);
7729 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7730 vmcs_writel(field, (long)field_value);
7739 vmcs_clear(shadow_vmcs);
7740 vmcs_load(vmx->loaded_vmcs->vmcs);
7744 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7745 * used before) all generate the same failure when it is missing.
7747 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7749 struct vcpu_vmx *vmx = to_vmx(vcpu);
7750 if (vmx->nested.current_vmptr == -1ull) {
7751 nested_vmx_failInvalid(vcpu);
7757 static int handle_vmread(struct kvm_vcpu *vcpu)
7759 unsigned long field;
7761 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7762 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7765 if (!nested_vmx_check_permission(vcpu))
7768 if (!nested_vmx_check_vmcs12(vcpu))
7769 return kvm_skip_emulated_instruction(vcpu);
7771 /* Decode instruction info and find the field to read */
7772 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7773 /* Read the field, zero-extended to a u64 field_value */
7774 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7775 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7776 return kvm_skip_emulated_instruction(vcpu);
7779 * Now copy part of this value to register or memory, as requested.
7780 * Note that the number of bits actually copied is 32 or 64 depending
7781 * on the guest's mode (32 or 64 bit), not on the given field's length.
7783 if (vmx_instruction_info & (1u << 10)) {
7784 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7787 if (get_vmx_mem_address(vcpu, exit_qualification,
7788 vmx_instruction_info, true, &gva))
7790 /* _system ok, as hardware has verified cpl=0 */
7791 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7792 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7795 nested_vmx_succeed(vcpu);
7796 return kvm_skip_emulated_instruction(vcpu);
7800 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7802 unsigned long field;
7804 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7805 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7806 /* The value to write might be 32 or 64 bits, depending on L1's long
7807 * mode, and eventually we need to write that into a field of several
7808 * possible lengths. The code below first zero-extends the value to 64
7809 * bit (field_value), and then copies only the appropriate number of
7810 * bits into the vmcs12 field.
7812 u64 field_value = 0;
7813 struct x86_exception e;
7815 if (!nested_vmx_check_permission(vcpu))
7818 if (!nested_vmx_check_vmcs12(vcpu))
7819 return kvm_skip_emulated_instruction(vcpu);
7821 if (vmx_instruction_info & (1u << 10))
7822 field_value = kvm_register_readl(vcpu,
7823 (((vmx_instruction_info) >> 3) & 0xf));
7825 if (get_vmx_mem_address(vcpu, exit_qualification,
7826 vmx_instruction_info, false, &gva))
7828 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7829 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7830 kvm_inject_page_fault(vcpu, &e);
7836 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7837 if (vmcs_field_readonly(field)) {
7838 nested_vmx_failValid(vcpu,
7839 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7840 return kvm_skip_emulated_instruction(vcpu);
7843 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7844 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7845 return kvm_skip_emulated_instruction(vcpu);
7848 nested_vmx_succeed(vcpu);
7849 return kvm_skip_emulated_instruction(vcpu);
7852 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7854 vmx->nested.current_vmptr = vmptr;
7855 if (enable_shadow_vmcs) {
7856 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7857 SECONDARY_EXEC_SHADOW_VMCS);
7858 vmcs_write64(VMCS_LINK_POINTER,
7859 __pa(vmx->vmcs01.shadow_vmcs));
7860 vmx->nested.sync_shadow_vmcs = true;
7864 /* Emulate the VMPTRLD instruction */
7865 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7867 struct vcpu_vmx *vmx = to_vmx(vcpu);
7870 if (!nested_vmx_check_permission(vcpu))
7873 if (nested_vmx_get_vmptr(vcpu, &vmptr))
7876 if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7877 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7878 return kvm_skip_emulated_instruction(vcpu);
7881 if (vmptr == vmx->nested.vmxon_ptr) {
7882 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7883 return kvm_skip_emulated_instruction(vcpu);
7886 if (vmx->nested.current_vmptr != vmptr) {
7887 struct vmcs12 *new_vmcs12;
7889 page = kvm_vcpu_gpa_to_page(vcpu, vmptr);
7890 if (is_error_page(page)) {
7891 nested_vmx_failInvalid(vcpu);
7892 return kvm_skip_emulated_instruction(vcpu);
7894 new_vmcs12 = kmap(page);
7895 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7897 kvm_release_page_clean(page);
7898 nested_vmx_failValid(vcpu,
7899 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7900 return kvm_skip_emulated_instruction(vcpu);
7903 nested_release_vmcs12(vmx);
7905 * Load VMCS12 from guest memory since it is not already
7908 memcpy(vmx->nested.cached_vmcs12, new_vmcs12, VMCS12_SIZE);
7910 kvm_release_page_clean(page);
7912 set_current_vmptr(vmx, vmptr);
7915 nested_vmx_succeed(vcpu);
7916 return kvm_skip_emulated_instruction(vcpu);
7919 /* Emulate the VMPTRST instruction */
7920 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7922 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7923 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7925 struct x86_exception e;
7927 if (!nested_vmx_check_permission(vcpu))
7930 if (get_vmx_mem_address(vcpu, exit_qualification,
7931 vmx_instruction_info, true, &vmcs_gva))
7933 /* ok to use *_system, as hardware has verified cpl=0 */
7934 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7935 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7937 kvm_inject_page_fault(vcpu, &e);
7940 nested_vmx_succeed(vcpu);
7941 return kvm_skip_emulated_instruction(vcpu);
7944 /* Emulate the INVEPT instruction */
7945 static int handle_invept(struct kvm_vcpu *vcpu)
7947 struct vcpu_vmx *vmx = to_vmx(vcpu);
7948 u32 vmx_instruction_info, types;
7951 struct x86_exception e;
7956 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7957 SECONDARY_EXEC_ENABLE_EPT) ||
7958 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7959 kvm_queue_exception(vcpu, UD_VECTOR);
7963 if (!nested_vmx_check_permission(vcpu))
7966 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7967 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7969 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7971 if (type >= 32 || !(types & (1 << type))) {
7972 nested_vmx_failValid(vcpu,
7973 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7974 return kvm_skip_emulated_instruction(vcpu);
7977 /* According to the Intel VMX instruction reference, the memory
7978 * operand is read even if it isn't needed (e.g., for type==global)
7980 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7981 vmx_instruction_info, false, &gva))
7983 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7984 sizeof(operand), &e)) {
7985 kvm_inject_page_fault(vcpu, &e);
7990 case VMX_EPT_EXTENT_GLOBAL:
7992 * TODO: track mappings and invalidate
7993 * single context requests appropriately
7995 case VMX_EPT_EXTENT_CONTEXT:
7996 kvm_mmu_sync_roots(vcpu);
7997 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7998 nested_vmx_succeed(vcpu);
8005 return kvm_skip_emulated_instruction(vcpu);
8008 static int handle_invvpid(struct kvm_vcpu *vcpu)
8010 struct vcpu_vmx *vmx = to_vmx(vcpu);
8011 u32 vmx_instruction_info;
8012 unsigned long type, types;
8014 struct x86_exception e;
8020 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
8021 SECONDARY_EXEC_ENABLE_VPID) ||
8022 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
8023 kvm_queue_exception(vcpu, UD_VECTOR);
8027 if (!nested_vmx_check_permission(vcpu))
8030 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8031 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
8033 types = (vmx->nested.nested_vmx_vpid_caps &
8034 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
8036 if (type >= 32 || !(types & (1 << type))) {
8037 nested_vmx_failValid(vcpu,
8038 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8039 return kvm_skip_emulated_instruction(vcpu);
8042 /* according to the intel vmx instruction reference, the memory
8043 * operand is read even if it isn't needed (e.g., for type==global)
8045 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
8046 vmx_instruction_info, false, &gva))
8048 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
8049 sizeof(operand), &e)) {
8050 kvm_inject_page_fault(vcpu, &e);
8053 if (operand.vpid >> 16) {
8054 nested_vmx_failValid(vcpu,
8055 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8056 return kvm_skip_emulated_instruction(vcpu);
8060 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
8061 if (is_noncanonical_address(operand.gla, vcpu)) {
8062 nested_vmx_failValid(vcpu,
8063 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8064 return kvm_skip_emulated_instruction(vcpu);
8067 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
8068 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
8069 if (!operand.vpid) {
8070 nested_vmx_failValid(vcpu,
8071 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
8072 return kvm_skip_emulated_instruction(vcpu);
8075 case VMX_VPID_EXTENT_ALL_CONTEXT:
8079 return kvm_skip_emulated_instruction(vcpu);
8082 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
8083 nested_vmx_succeed(vcpu);
8085 return kvm_skip_emulated_instruction(vcpu);
8088 static int handle_pml_full(struct kvm_vcpu *vcpu)
8090 unsigned long exit_qualification;
8092 trace_kvm_pml_full(vcpu->vcpu_id);
8094 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8097 * PML buffer FULL happened while executing iret from NMI,
8098 * "blocked by NMI" bit has to be set before next VM entry.
8100 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
8101 cpu_has_virtual_nmis() &&
8102 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
8103 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8104 GUEST_INTR_STATE_NMI);
8107 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8108 * here.., and there's no userspace involvement needed for PML.
8113 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8115 kvm_lapic_expired_hv_timer(vcpu);
8119 static bool valid_ept_address(struct kvm_vcpu *vcpu, u64 address)
8121 struct vcpu_vmx *vmx = to_vmx(vcpu);
8122 int maxphyaddr = cpuid_maxphyaddr(vcpu);
8124 /* Check for memory type validity */
8125 switch (address & VMX_EPTP_MT_MASK) {
8126 case VMX_EPTP_MT_UC:
8127 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_UC_BIT))
8130 case VMX_EPTP_MT_WB:
8131 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPTP_WB_BIT))
8138 /* only 4 levels page-walk length are valid */
8139 if ((address & VMX_EPTP_PWL_MASK) != VMX_EPTP_PWL_4)
8142 /* Reserved bits should not be set */
8143 if (address >> maxphyaddr || ((address >> 7) & 0x1f))
8146 /* AD, if set, should be supported */
8147 if (address & VMX_EPTP_AD_ENABLE_BIT) {
8148 if (!(vmx->nested.nested_vmx_ept_caps & VMX_EPT_AD_BIT))
8155 static int nested_vmx_eptp_switching(struct kvm_vcpu *vcpu,
8156 struct vmcs12 *vmcs12)
8158 u32 index = vcpu->arch.regs[VCPU_REGS_RCX];
8160 bool accessed_dirty;
8161 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
8163 if (!nested_cpu_has_eptp_switching(vmcs12) ||
8164 !nested_cpu_has_ept(vmcs12))
8167 if (index >= VMFUNC_EPTP_ENTRIES)
8171 if (kvm_vcpu_read_guest_page(vcpu, vmcs12->eptp_list_address >> PAGE_SHIFT,
8172 &address, index * 8, 8))
8175 accessed_dirty = !!(address & VMX_EPTP_AD_ENABLE_BIT);
8178 * If the (L2) guest does a vmfunc to the currently
8179 * active ept pointer, we don't have to do anything else
8181 if (vmcs12->ept_pointer != address) {
8182 if (!valid_ept_address(vcpu, address))
8185 kvm_mmu_unload(vcpu);
8186 mmu->ept_ad = accessed_dirty;
8187 mmu->base_role.ad_disabled = !accessed_dirty;
8188 vmcs12->ept_pointer = address;
8190 * TODO: Check what's the correct approach in case
8191 * mmu reload fails. Currently, we just let the next
8192 * reload potentially fail
8194 kvm_mmu_reload(vcpu);
8200 static int handle_vmfunc(struct kvm_vcpu *vcpu)
8202 struct vcpu_vmx *vmx = to_vmx(vcpu);
8203 struct vmcs12 *vmcs12;
8204 u32 function = vcpu->arch.regs[VCPU_REGS_RAX];
8207 * VMFUNC is only supported for nested guests, but we always enable the
8208 * secondary control for simplicity; for non-nested mode, fake that we
8209 * didn't by injecting #UD.
8211 if (!is_guest_mode(vcpu)) {
8212 kvm_queue_exception(vcpu, UD_VECTOR);
8216 vmcs12 = get_vmcs12(vcpu);
8217 if ((vmcs12->vm_function_control & (1 << function)) == 0)
8222 if (nested_vmx_eptp_switching(vcpu, vmcs12))
8228 return kvm_skip_emulated_instruction(vcpu);
8231 nested_vmx_vmexit(vcpu, vmx->exit_reason,
8232 vmcs_read32(VM_EXIT_INTR_INFO),
8233 vmcs_readl(EXIT_QUALIFICATION));
8238 * The exit handlers return 1 if the exit was handled fully and guest execution
8239 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8240 * to be done to userspace and return 0.
8242 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
8243 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
8244 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
8245 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
8246 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
8247 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
8248 [EXIT_REASON_CR_ACCESS] = handle_cr,
8249 [EXIT_REASON_DR_ACCESS] = handle_dr,
8250 [EXIT_REASON_CPUID] = handle_cpuid,
8251 [EXIT_REASON_MSR_READ] = handle_rdmsr,
8252 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
8253 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
8254 [EXIT_REASON_HLT] = handle_halt,
8255 [EXIT_REASON_INVD] = handle_invd,
8256 [EXIT_REASON_INVLPG] = handle_invlpg,
8257 [EXIT_REASON_RDPMC] = handle_rdpmc,
8258 [EXIT_REASON_VMCALL] = handle_vmcall,
8259 [EXIT_REASON_VMCLEAR] = handle_vmclear,
8260 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
8261 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
8262 [EXIT_REASON_VMPTRST] = handle_vmptrst,
8263 [EXIT_REASON_VMREAD] = handle_vmread,
8264 [EXIT_REASON_VMRESUME] = handle_vmresume,
8265 [EXIT_REASON_VMWRITE] = handle_vmwrite,
8266 [EXIT_REASON_VMOFF] = handle_vmoff,
8267 [EXIT_REASON_VMON] = handle_vmon,
8268 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
8269 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
8270 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
8271 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
8272 [EXIT_REASON_WBINVD] = handle_wbinvd,
8273 [EXIT_REASON_XSETBV] = handle_xsetbv,
8274 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
8275 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
8276 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
8277 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
8278 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
8279 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
8280 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
8281 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
8282 [EXIT_REASON_INVEPT] = handle_invept,
8283 [EXIT_REASON_INVVPID] = handle_invvpid,
8284 [EXIT_REASON_RDRAND] = handle_invalid_op,
8285 [EXIT_REASON_RDSEED] = handle_invalid_op,
8286 [EXIT_REASON_XSAVES] = handle_xsaves,
8287 [EXIT_REASON_XRSTORS] = handle_xrstors,
8288 [EXIT_REASON_PML_FULL] = handle_pml_full,
8289 [EXIT_REASON_VMFUNC] = handle_vmfunc,
8290 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
8293 static const int kvm_vmx_max_exit_handlers =
8294 ARRAY_SIZE(kvm_vmx_exit_handlers);
8296 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8297 struct vmcs12 *vmcs12)
8299 unsigned long exit_qualification;
8300 gpa_t bitmap, last_bitmap;
8305 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
8306 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
8308 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8310 port = exit_qualification >> 16;
8311 size = (exit_qualification & 7) + 1;
8313 last_bitmap = (gpa_t)-1;
8318 bitmap = vmcs12->io_bitmap_a;
8319 else if (port < 0x10000)
8320 bitmap = vmcs12->io_bitmap_b;
8323 bitmap += (port & 0x7fff) / 8;
8325 if (last_bitmap != bitmap)
8326 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
8328 if (b & (1 << (port & 7)))
8333 last_bitmap = bitmap;
8340 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8341 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8342 * disinterest in the current event (read or write a specific MSR) by using an
8343 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8345 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8346 struct vmcs12 *vmcs12, u32 exit_reason)
8348 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8351 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8355 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8356 * for the four combinations of read/write and low/high MSR numbers.
8357 * First we need to figure out which of the four to use:
8359 bitmap = vmcs12->msr_bitmap;
8360 if (exit_reason == EXIT_REASON_MSR_WRITE)
8362 if (msr_index >= 0xc0000000) {
8363 msr_index -= 0xc0000000;
8367 /* Then read the msr_index'th bit from this bitmap: */
8368 if (msr_index < 1024*8) {
8370 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
8372 return 1 & (b >> (msr_index & 7));
8374 return true; /* let L1 handle the wrong parameter */
8378 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8379 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8380 * intercept (via guest_host_mask etc.) the current event.
8382 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8383 struct vmcs12 *vmcs12)
8385 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8386 int cr = exit_qualification & 15;
8390 switch ((exit_qualification >> 4) & 3) {
8391 case 0: /* mov to cr */
8392 reg = (exit_qualification >> 8) & 15;
8393 val = kvm_register_readl(vcpu, reg);
8396 if (vmcs12->cr0_guest_host_mask &
8397 (val ^ vmcs12->cr0_read_shadow))
8401 if ((vmcs12->cr3_target_count >= 1 &&
8402 vmcs12->cr3_target_value0 == val) ||
8403 (vmcs12->cr3_target_count >= 2 &&
8404 vmcs12->cr3_target_value1 == val) ||
8405 (vmcs12->cr3_target_count >= 3 &&
8406 vmcs12->cr3_target_value2 == val) ||
8407 (vmcs12->cr3_target_count >= 4 &&
8408 vmcs12->cr3_target_value3 == val))
8410 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8414 if (vmcs12->cr4_guest_host_mask &
8415 (vmcs12->cr4_read_shadow ^ val))
8419 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8425 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8426 (vmcs12->cr0_read_shadow & X86_CR0_TS))
8429 case 1: /* mov from cr */
8432 if (vmcs12->cpu_based_vm_exec_control &
8433 CPU_BASED_CR3_STORE_EXITING)
8437 if (vmcs12->cpu_based_vm_exec_control &
8438 CPU_BASED_CR8_STORE_EXITING)
8445 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8446 * cr0. Other attempted changes are ignored, with no exit.
8448 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8449 if (vmcs12->cr0_guest_host_mask & 0xe &
8450 (val ^ vmcs12->cr0_read_shadow))
8452 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8453 !(vmcs12->cr0_read_shadow & 0x1) &&
8462 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8463 * should handle it ourselves in L0 (and then continue L2). Only call this
8464 * when in is_guest_mode (L2).
8466 static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason)
8468 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8469 struct vcpu_vmx *vmx = to_vmx(vcpu);
8470 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8472 if (vmx->nested.nested_run_pending)
8475 if (unlikely(vmx->fail)) {
8476 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8477 vmcs_read32(VM_INSTRUCTION_ERROR));
8482 * The host physical addresses of some pages of guest memory
8483 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8484 * Page). The CPU may write to these pages via their host
8485 * physical address while L2 is running, bypassing any
8486 * address-translation-based dirty tracking (e.g. EPT write
8489 * Mark them dirty on every exit from L2 to prevent them from
8490 * getting out of sync with dirty tracking.
8492 nested_mark_vmcs12_pages_dirty(vcpu);
8494 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8495 vmcs_readl(EXIT_QUALIFICATION),
8496 vmx->idt_vectoring_info,
8498 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8501 switch (exit_reason) {
8502 case EXIT_REASON_EXCEPTION_NMI:
8503 if (is_nmi(intr_info))
8505 else if (is_page_fault(intr_info))
8506 return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8507 else if (is_no_device(intr_info) &&
8508 !(vmcs12->guest_cr0 & X86_CR0_TS))
8510 else if (is_debug(intr_info) &&
8512 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8514 else if (is_breakpoint(intr_info) &&
8515 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8517 return vmcs12->exception_bitmap &
8518 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8519 case EXIT_REASON_EXTERNAL_INTERRUPT:
8521 case EXIT_REASON_TRIPLE_FAULT:
8523 case EXIT_REASON_PENDING_INTERRUPT:
8524 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8525 case EXIT_REASON_NMI_WINDOW:
8526 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8527 case EXIT_REASON_TASK_SWITCH:
8529 case EXIT_REASON_CPUID:
8531 case EXIT_REASON_HLT:
8532 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8533 case EXIT_REASON_INVD:
8535 case EXIT_REASON_INVLPG:
8536 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8537 case EXIT_REASON_RDPMC:
8538 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8539 case EXIT_REASON_RDRAND:
8540 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8541 case EXIT_REASON_RDSEED:
8542 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8543 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8544 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8545 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8546 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8547 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8548 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8549 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8550 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8552 * VMX instructions trap unconditionally. This allows L1 to
8553 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8556 case EXIT_REASON_CR_ACCESS:
8557 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8558 case EXIT_REASON_DR_ACCESS:
8559 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8560 case EXIT_REASON_IO_INSTRUCTION:
8561 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8562 case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8563 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8564 case EXIT_REASON_MSR_READ:
8565 case EXIT_REASON_MSR_WRITE:
8566 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8567 case EXIT_REASON_INVALID_STATE:
8569 case EXIT_REASON_MWAIT_INSTRUCTION:
8570 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8571 case EXIT_REASON_MONITOR_TRAP_FLAG:
8572 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8573 case EXIT_REASON_MONITOR_INSTRUCTION:
8574 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8575 case EXIT_REASON_PAUSE_INSTRUCTION:
8576 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8577 nested_cpu_has2(vmcs12,
8578 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8579 case EXIT_REASON_MCE_DURING_VMENTRY:
8581 case EXIT_REASON_TPR_BELOW_THRESHOLD:
8582 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8583 case EXIT_REASON_APIC_ACCESS:
8584 return nested_cpu_has2(vmcs12,
8585 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8586 case EXIT_REASON_APIC_WRITE:
8587 case EXIT_REASON_EOI_INDUCED:
8588 /* apic_write and eoi_induced should exit unconditionally. */
8590 case EXIT_REASON_EPT_VIOLATION:
8592 * L0 always deals with the EPT violation. If nested EPT is
8593 * used, and the nested mmu code discovers that the address is
8594 * missing in the guest EPT table (EPT12), the EPT violation
8595 * will be injected with nested_ept_inject_page_fault()
8598 case EXIT_REASON_EPT_MISCONFIG:
8600 * L2 never uses directly L1's EPT, but rather L0's own EPT
8601 * table (shadow on EPT) or a merged EPT table that L0 built
8602 * (EPT on EPT). So any problems with the structure of the
8603 * table is L0's fault.
8606 case EXIT_REASON_INVPCID:
8608 nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_INVPCID) &&
8609 nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8610 case EXIT_REASON_WBINVD:
8611 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8612 case EXIT_REASON_XSETBV:
8614 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8616 * This should never happen, since it is not possible to
8617 * set XSS to a non-zero value---neither in L1 nor in L2.
8618 * If if it were, XSS would have to be checked against
8619 * the XSS exit bitmap in vmcs12.
8621 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8622 case EXIT_REASON_PREEMPTION_TIMER:
8624 case EXIT_REASON_PML_FULL:
8625 /* We emulate PML support to L1. */
8627 case EXIT_REASON_VMFUNC:
8628 /* VM functions are emulated through L2->L0 vmexits. */
8635 static int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason)
8637 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8640 * At this point, the exit interruption info in exit_intr_info
8641 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8642 * we need to query the in-kernel LAPIC.
8644 WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
8645 if ((exit_intr_info &
8646 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8647 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
8648 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8649 vmcs12->vm_exit_intr_error_code =
8650 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8653 nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
8654 vmcs_readl(EXIT_QUALIFICATION));
8658 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8660 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8661 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8664 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8667 __free_page(vmx->pml_pg);
8672 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8674 struct vcpu_vmx *vmx = to_vmx(vcpu);
8678 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8680 /* Do nothing if PML buffer is empty */
8681 if (pml_idx == (PML_ENTITY_NUM - 1))
8684 /* PML index always points to next available PML buffer entity */
8685 if (pml_idx >= PML_ENTITY_NUM)
8690 pml_buf = page_address(vmx->pml_pg);
8691 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8694 gpa = pml_buf[pml_idx];
8695 WARN_ON(gpa & (PAGE_SIZE - 1));
8696 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8699 /* reset PML index */
8700 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8704 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8705 * Called before reporting dirty_bitmap to userspace.
8707 static void kvm_flush_pml_buffers(struct kvm *kvm)
8710 struct kvm_vcpu *vcpu;
8712 * We only need to kick vcpu out of guest mode here, as PML buffer
8713 * is flushed at beginning of all VMEXITs, and it's obvious that only
8714 * vcpus running in guest are possible to have unflushed GPAs in PML
8717 kvm_for_each_vcpu(i, vcpu, kvm)
8718 kvm_vcpu_kick(vcpu);
8721 static void vmx_dump_sel(char *name, uint32_t sel)
8723 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8724 name, vmcs_read16(sel),
8725 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8726 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8727 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8730 static void vmx_dump_dtsel(char *name, uint32_t limit)
8732 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8733 name, vmcs_read32(limit),
8734 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8737 static void dump_vmcs(void)
8739 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8740 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8741 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8742 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8743 u32 secondary_exec_control = 0;
8744 unsigned long cr4 = vmcs_readl(GUEST_CR4);
8745 u64 efer = vmcs_read64(GUEST_IA32_EFER);
8748 if (cpu_has_secondary_exec_ctrls())
8749 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8751 pr_err("*** Guest State ***\n");
8752 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8753 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8754 vmcs_readl(CR0_GUEST_HOST_MASK));
8755 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8756 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8757 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8758 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8759 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8761 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8762 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8763 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8764 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8766 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8767 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8768 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8769 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8770 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8771 vmcs_readl(GUEST_SYSENTER_ESP),
8772 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8773 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8774 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8775 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8776 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8777 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8778 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8779 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8780 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8781 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8782 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8783 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8784 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8785 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8786 efer, vmcs_read64(GUEST_IA32_PAT));
8787 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8788 vmcs_read64(GUEST_IA32_DEBUGCTL),
8789 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8790 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8791 pr_err("PerfGlobCtl = 0x%016llx\n",
8792 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8793 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8794 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8795 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8796 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8797 vmcs_read32(GUEST_ACTIVITY_STATE));
8798 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8799 pr_err("InterruptStatus = %04x\n",
8800 vmcs_read16(GUEST_INTR_STATUS));
8802 pr_err("*** Host State ***\n");
8803 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8804 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8805 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8806 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8807 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8808 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8809 vmcs_read16(HOST_TR_SELECTOR));
8810 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8811 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8812 vmcs_readl(HOST_TR_BASE));
8813 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8814 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8815 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8816 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8817 vmcs_readl(HOST_CR4));
8818 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8819 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8820 vmcs_read32(HOST_IA32_SYSENTER_CS),
8821 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8822 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8823 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8824 vmcs_read64(HOST_IA32_EFER),
8825 vmcs_read64(HOST_IA32_PAT));
8826 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8827 pr_err("PerfGlobCtl = 0x%016llx\n",
8828 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8830 pr_err("*** Control State ***\n");
8831 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8832 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8833 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8834 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8835 vmcs_read32(EXCEPTION_BITMAP),
8836 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8837 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8838 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8839 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8840 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8841 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8842 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8843 vmcs_read32(VM_EXIT_INTR_INFO),
8844 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8845 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8846 pr_err(" reason=%08x qualification=%016lx\n",
8847 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8848 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8849 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8850 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8851 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8852 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8853 pr_err("TSC Multiplier = 0x%016llx\n",
8854 vmcs_read64(TSC_MULTIPLIER));
8855 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8856 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8857 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8858 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8859 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8860 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8861 n = vmcs_read32(CR3_TARGET_COUNT);
8862 for (i = 0; i + 1 < n; i += 4)
8863 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8864 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8865 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8867 pr_err("CR3 target%u=%016lx\n",
8868 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8869 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8870 pr_err("PLE Gap=%08x Window=%08x\n",
8871 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8872 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8873 pr_err("Virtual processor ID = 0x%04x\n",
8874 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8878 * The guest has exited. See if we can fix it or if we need userspace
8881 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8883 struct vcpu_vmx *vmx = to_vmx(vcpu);
8884 u32 exit_reason = vmx->exit_reason;
8885 u32 vectoring_info = vmx->idt_vectoring_info;
8887 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8890 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8891 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8892 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8893 * mode as if vcpus is in root mode, the PML buffer must has been
8897 vmx_flush_pml_buffer(vcpu);
8899 /* If guest state is invalid, start emulating */
8900 if (vmx->emulation_required)
8901 return handle_invalid_guest_state(vcpu);
8903 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
8904 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
8906 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8908 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8909 vcpu->run->fail_entry.hardware_entry_failure_reason
8914 if (unlikely(vmx->fail)) {
8915 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8916 vcpu->run->fail_entry.hardware_entry_failure_reason
8917 = vmcs_read32(VM_INSTRUCTION_ERROR);
8923 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8924 * delivery event since it indicates guest is accessing MMIO.
8925 * The vm-exit can be triggered again after return to guest that
8926 * will cause infinite loop.
8928 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8929 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8930 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8931 exit_reason != EXIT_REASON_PML_FULL &&
8932 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8933 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8934 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8935 vcpu->run->internal.ndata = 3;
8936 vcpu->run->internal.data[0] = vectoring_info;
8937 vcpu->run->internal.data[1] = exit_reason;
8938 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8939 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8940 vcpu->run->internal.ndata++;
8941 vcpu->run->internal.data[3] =
8942 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8947 if (unlikely(!cpu_has_virtual_nmis() &&
8948 vmx->loaded_vmcs->soft_vnmi_blocked)) {
8949 if (vmx_interrupt_allowed(vcpu)) {
8950 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
8951 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
8952 vcpu->arch.nmi_pending) {
8954 * This CPU don't support us in finding the end of an
8955 * NMI-blocked window if the guest runs with IRQs
8956 * disabled. So we pull the trigger after 1 s of
8957 * futile waiting, but inform the user about this.
8959 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8960 "state on VCPU %d after 1 s timeout\n",
8961 __func__, vcpu->vcpu_id);
8962 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
8966 if (exit_reason < kvm_vmx_max_exit_handlers
8967 && kvm_vmx_exit_handlers[exit_reason])
8968 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8970 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8972 kvm_queue_exception(vcpu, UD_VECTOR);
8977 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8979 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8981 if (is_guest_mode(vcpu) &&
8982 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8985 if (irr == -1 || tpr < irr) {
8986 vmcs_write32(TPR_THRESHOLD, 0);
8990 vmcs_write32(TPR_THRESHOLD, irr);
8993 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8995 u32 sec_exec_control;
8997 /* Postpone execution until vmcs01 is the current VMCS. */
8998 if (is_guest_mode(vcpu)) {
8999 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
9003 if (!cpu_has_vmx_virtualize_x2apic_mode())
9006 if (!cpu_need_tpr_shadow(vcpu))
9009 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9012 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9013 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9015 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
9016 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9017 vmx_flush_tlb_ept_only(vcpu);
9019 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
9021 vmx_update_msr_bitmap(vcpu);
9024 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
9026 struct vcpu_vmx *vmx = to_vmx(vcpu);
9029 * Currently we do not handle the nested case where L2 has an
9030 * APIC access page of its own; that page is still pinned.
9031 * Hence, we skip the case where the VCPU is in guest mode _and_
9032 * L1 prepared an APIC access page for L2.
9034 * For the case where L1 and L2 share the same APIC access page
9035 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
9036 * in the vmcs12), this function will only update either the vmcs01
9037 * or the vmcs02. If the former, the vmcs02 will be updated by
9038 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
9039 * the next L2->L1 exit.
9041 if (!is_guest_mode(vcpu) ||
9042 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
9043 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9044 vmcs_write64(APIC_ACCESS_ADDR, hpa);
9045 vmx_flush_tlb_ept_only(vcpu);
9049 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
9057 status = vmcs_read16(GUEST_INTR_STATUS);
9059 if (max_isr != old) {
9061 status |= max_isr << 8;
9062 vmcs_write16(GUEST_INTR_STATUS, status);
9066 static void vmx_set_rvi(int vector)
9074 status = vmcs_read16(GUEST_INTR_STATUS);
9075 old = (u8)status & 0xff;
9076 if ((u8)vector != old) {
9078 status |= (u8)vector;
9079 vmcs_write16(GUEST_INTR_STATUS, status);
9083 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
9085 if (!is_guest_mode(vcpu)) {
9086 vmx_set_rvi(max_irr);
9094 * In guest mode. If a vmexit is needed, vmx_check_nested_events
9097 if (nested_exit_on_intr(vcpu))
9101 * Else, fall back to pre-APICv interrupt injection since L2
9102 * is run without virtual interrupt delivery.
9104 if (!kvm_event_needs_reinjection(vcpu) &&
9105 vmx_interrupt_allowed(vcpu)) {
9106 kvm_queue_interrupt(vcpu, max_irr, false);
9107 vmx_inject_irq(vcpu);
9111 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
9113 struct vcpu_vmx *vmx = to_vmx(vcpu);
9116 WARN_ON(!vcpu->arch.apicv_active);
9117 if (pi_test_on(&vmx->pi_desc)) {
9118 pi_clear_on(&vmx->pi_desc);
9120 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9121 * But on x86 this is just a compiler barrier anyway.
9123 smp_mb__after_atomic();
9124 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
9126 max_irr = kvm_lapic_find_highest_irr(vcpu);
9128 vmx_hwapic_irr_update(vcpu, max_irr);
9132 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
9134 if (!kvm_vcpu_apicv_active(vcpu))
9137 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
9138 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
9139 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
9140 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
9143 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
9145 struct vcpu_vmx *vmx = to_vmx(vcpu);
9147 pi_clear_on(&vmx->pi_desc);
9148 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
9151 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
9153 u32 exit_intr_info = 0;
9154 u16 basic_exit_reason = (u16)vmx->exit_reason;
9156 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
9157 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
9160 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9161 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9162 vmx->exit_intr_info = exit_intr_info;
9164 /* if exit due to PF check for async PF */
9165 if (is_page_fault(exit_intr_info))
9166 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
9168 /* Handle machine checks before interrupts are enabled */
9169 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
9170 is_machine_check(exit_intr_info))
9171 kvm_machine_check();
9173 /* We need to handle NMIs before interrupts are enabled */
9174 if (is_nmi(exit_intr_info)) {
9175 kvm_before_handle_nmi(&vmx->vcpu);
9177 kvm_after_handle_nmi(&vmx->vcpu);
9181 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
9183 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9185 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
9186 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
9187 unsigned int vector;
9188 unsigned long entry;
9190 struct vcpu_vmx *vmx = to_vmx(vcpu);
9191 #ifdef CONFIG_X86_64
9195 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9196 desc = (gate_desc *)vmx->host_idt_base + vector;
9197 entry = gate_offset(desc);
9199 #ifdef CONFIG_X86_64
9200 "mov %%" _ASM_SP ", %[sp]\n\t"
9201 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
9206 __ASM_SIZE(push) " $%c[cs]\n\t"
9209 #ifdef CONFIG_X86_64
9214 THUNK_TARGET(entry),
9215 [ss]"i"(__KERNEL_DS),
9216 [cs]"i"(__KERNEL_CS)
9220 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
9222 static bool vmx_has_high_real_mode_segbase(void)
9224 return enable_unrestricted_guest || emulate_invalid_guest_state;
9227 static bool vmx_mpx_supported(void)
9229 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
9230 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
9233 static bool vmx_xsaves_supported(void)
9235 return vmcs_config.cpu_based_2nd_exec_ctrl &
9236 SECONDARY_EXEC_XSAVES;
9239 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
9244 bool idtv_info_valid;
9246 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9248 if (cpu_has_virtual_nmis()) {
9249 if (vmx->loaded_vmcs->nmi_known_unmasked)
9252 * Can't use vmx->exit_intr_info since we're not sure what
9253 * the exit reason is.
9255 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
9256 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9257 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9259 * SDM 3: 27.7.1.2 (September 2008)
9260 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9261 * a guest IRET fault.
9262 * SDM 3: 23.2.2 (September 2008)
9263 * Bit 12 is undefined in any of the following cases:
9264 * If the VM exit sets the valid bit in the IDT-vectoring
9265 * information field.
9266 * If the VM exit is due to a double fault.
9268 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9269 vector != DF_VECTOR && !idtv_info_valid)
9270 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9271 GUEST_INTR_STATE_NMI);
9273 vmx->loaded_vmcs->nmi_known_unmasked =
9274 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9275 & GUEST_INTR_STATE_NMI);
9276 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
9277 vmx->loaded_vmcs->vnmi_blocked_time +=
9278 ktime_to_ns(ktime_sub(ktime_get(),
9279 vmx->loaded_vmcs->entry_time));
9282 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
9283 u32 idt_vectoring_info,
9284 int instr_len_field,
9285 int error_code_field)
9289 bool idtv_info_valid;
9291 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
9293 vcpu->arch.nmi_injected = false;
9294 kvm_clear_exception_queue(vcpu);
9295 kvm_clear_interrupt_queue(vcpu);
9297 if (!idtv_info_valid)
9300 kvm_make_request(KVM_REQ_EVENT, vcpu);
9302 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9303 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
9306 case INTR_TYPE_NMI_INTR:
9307 vcpu->arch.nmi_injected = true;
9309 * SDM 3: 27.7.1.2 (September 2008)
9310 * Clear bit "block by NMI" before VM entry if a NMI
9313 vmx_set_nmi_mask(vcpu, false);
9315 case INTR_TYPE_SOFT_EXCEPTION:
9316 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9318 case INTR_TYPE_HARD_EXCEPTION:
9319 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
9320 u32 err = vmcs_read32(error_code_field);
9321 kvm_requeue_exception_e(vcpu, vector, err);
9323 kvm_requeue_exception(vcpu, vector);
9325 case INTR_TYPE_SOFT_INTR:
9326 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
9328 case INTR_TYPE_EXT_INTR:
9329 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
9336 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9338 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
9339 VM_EXIT_INSTRUCTION_LEN,
9340 IDT_VECTORING_ERROR_CODE);
9343 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9345 __vmx_complete_interrupts(vcpu,
9346 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9347 VM_ENTRY_INSTRUCTION_LEN,
9348 VM_ENTRY_EXCEPTION_ERROR_CODE);
9350 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9353 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9356 struct perf_guest_switch_msr *msrs;
9358 msrs = perf_guest_get_msrs(&nr_msrs);
9363 for (i = 0; i < nr_msrs; i++)
9364 if (msrs[i].host == msrs[i].guest)
9365 clear_atomic_switch_msr(vmx, msrs[i].msr);
9367 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
9371 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9373 struct vcpu_vmx *vmx = to_vmx(vcpu);
9377 if (vmx->hv_deadline_tsc == -1)
9381 if (vmx->hv_deadline_tsc > tscl)
9382 /* sure to be 32 bit only because checked on set_hv_timer */
9383 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9384 cpu_preemption_timer_multi);
9388 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9391 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
9393 struct vcpu_vmx *vmx = to_vmx(vcpu);
9394 unsigned long debugctlmsr, cr3, cr4;
9396 /* Record the guest's net vcpu time for enforced NMI injections. */
9397 if (unlikely(!cpu_has_virtual_nmis() &&
9398 vmx->loaded_vmcs->soft_vnmi_blocked))
9399 vmx->loaded_vmcs->entry_time = ktime_get();
9401 /* Don't enter VMX if guest state is invalid, let the exit handler
9402 start emulation until we arrive back to a valid state */
9403 if (vmx->emulation_required)
9406 if (vmx->ple_window_dirty) {
9407 vmx->ple_window_dirty = false;
9408 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9411 if (vmx->nested.sync_shadow_vmcs) {
9412 copy_vmcs12_to_shadow(vmx);
9413 vmx->nested.sync_shadow_vmcs = false;
9416 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9417 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9418 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9419 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9421 cr3 = __get_current_cr3_fast();
9422 if (unlikely(cr3 != vmx->loaded_vmcs->vmcs_host_cr3)) {
9423 vmcs_writel(HOST_CR3, cr3);
9424 vmx->loaded_vmcs->vmcs_host_cr3 = cr3;
9427 cr4 = cr4_read_shadow();
9428 if (unlikely(cr4 != vmx->loaded_vmcs->vmcs_host_cr4)) {
9429 vmcs_writel(HOST_CR4, cr4);
9430 vmx->loaded_vmcs->vmcs_host_cr4 = cr4;
9433 /* When single-stepping over STI and MOV SS, we must clear the
9434 * corresponding interruptibility bits in the guest state. Otherwise
9435 * vmentry fails as it then expects bit 14 (BS) in pending debug
9436 * exceptions being set, but that's not correct for the guest debugging
9438 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9439 vmx_set_interrupt_shadow(vcpu, 0);
9441 if (static_cpu_has(X86_FEATURE_PKU) &&
9442 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
9443 vcpu->arch.pkru != vmx->host_pkru)
9444 __write_pkru(vcpu->arch.pkru);
9446 atomic_switch_perf_msrs(vmx);
9447 debugctlmsr = get_debugctlmsr();
9449 vmx_arm_hv_timer(vcpu);
9452 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9453 * it's non-zero. Since vmentry is serialising on affected CPUs, there
9454 * is no need to worry about the conditional branch over the wrmsr
9455 * being speculatively taken.
9457 x86_spec_ctrl_set_guest(vmx->spec_ctrl);
9459 vmx->__launched = vmx->loaded_vmcs->launched;
9461 /* Store host registers */
9462 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9463 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9464 "push %%" _ASM_CX " \n\t"
9465 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9467 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
9468 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
9470 /* Reload cr2 if changed */
9471 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9472 "mov %%cr2, %%" _ASM_DX " \n\t"
9473 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9475 "mov %%" _ASM_AX", %%cr2 \n\t"
9477 /* Check if vmlaunch of vmresume is needed */
9478 "cmpl $0, %c[launched](%0) \n\t"
9479 /* Load guest registers. Don't clobber flags. */
9480 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9481 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9482 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9483 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9484 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9485 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9486 #ifdef CONFIG_X86_64
9487 "mov %c[r8](%0), %%r8 \n\t"
9488 "mov %c[r9](%0), %%r9 \n\t"
9489 "mov %c[r10](%0), %%r10 \n\t"
9490 "mov %c[r11](%0), %%r11 \n\t"
9491 "mov %c[r12](%0), %%r12 \n\t"
9492 "mov %c[r13](%0), %%r13 \n\t"
9493 "mov %c[r14](%0), %%r14 \n\t"
9494 "mov %c[r15](%0), %%r15 \n\t"
9496 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9498 /* Enter guest mode */
9500 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9502 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9504 /* Save guest registers, load host registers, keep flags */
9505 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9507 "setbe %c[fail](%0)\n\t"
9508 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9509 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9510 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9511 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9512 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9513 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9514 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9515 #ifdef CONFIG_X86_64
9516 "mov %%r8, %c[r8](%0) \n\t"
9517 "mov %%r9, %c[r9](%0) \n\t"
9518 "mov %%r10, %c[r10](%0) \n\t"
9519 "mov %%r11, %c[r11](%0) \n\t"
9520 "mov %%r12, %c[r12](%0) \n\t"
9521 "mov %%r13, %c[r13](%0) \n\t"
9522 "mov %%r14, %c[r14](%0) \n\t"
9523 "mov %%r15, %c[r15](%0) \n\t"
9524 "xor %%r8d, %%r8d \n\t"
9525 "xor %%r9d, %%r9d \n\t"
9526 "xor %%r10d, %%r10d \n\t"
9527 "xor %%r11d, %%r11d \n\t"
9528 "xor %%r12d, %%r12d \n\t"
9529 "xor %%r13d, %%r13d \n\t"
9530 "xor %%r14d, %%r14d \n\t"
9531 "xor %%r15d, %%r15d \n\t"
9533 "mov %%cr2, %%" _ASM_AX " \n\t"
9534 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9536 "xor %%eax, %%eax \n\t"
9537 "xor %%ebx, %%ebx \n\t"
9538 "xor %%esi, %%esi \n\t"
9539 "xor %%edi, %%edi \n\t"
9540 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
9541 ".pushsection .rodata \n\t"
9542 ".global vmx_return \n\t"
9543 "vmx_return: " _ASM_PTR " 2b \n\t"
9545 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9546 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9547 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9548 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9549 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9550 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9551 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9552 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9553 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9554 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9555 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9556 #ifdef CONFIG_X86_64
9557 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9558 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9559 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9560 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9561 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9562 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9563 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9564 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9566 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9567 [wordsize]"i"(sizeof(ulong))
9569 #ifdef CONFIG_X86_64
9570 , "rax", "rbx", "rdi", "rsi"
9571 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9573 , "eax", "ebx", "edi", "esi"
9578 * We do not use IBRS in the kernel. If this vCPU has used the
9579 * SPEC_CTRL MSR it may have left it on; save the value and
9580 * turn it off. This is much more efficient than blindly adding
9581 * it to the atomic save/restore list. Especially as the former
9582 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
9584 * For non-nested case:
9585 * If the L01 MSR bitmap does not intercept the MSR, then we need to
9589 * If the L02 MSR bitmap does not intercept the MSR, then we need to
9592 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
9593 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
9595 x86_spec_ctrl_restore_host(vmx->spec_ctrl);
9597 /* Eliminate branch target predictions from guest mode */
9600 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9602 update_debugctlmsr(debugctlmsr);
9604 #ifndef CONFIG_X86_64
9606 * The sysexit path does not restore ds/es, so we must set them to
9607 * a reasonable value ourselves.
9609 * We can't defer this to vmx_load_host_state() since that function
9610 * may be executed in interrupt context, which saves and restore segments
9611 * around it, nullifying its effect.
9613 loadsegment(ds, __USER_DS);
9614 loadsegment(es, __USER_DS);
9617 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9618 | (1 << VCPU_EXREG_RFLAGS)
9619 | (1 << VCPU_EXREG_PDPTR)
9620 | (1 << VCPU_EXREG_SEGMENTS)
9621 | (1 << VCPU_EXREG_CR3));
9622 vcpu->arch.regs_dirty = 0;
9625 * eager fpu is enabled if PKEY is supported and CR4 is switched
9626 * back on host, so it is safe to read guest PKRU from current
9629 if (static_cpu_has(X86_FEATURE_PKU) &&
9630 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
9631 vcpu->arch.pkru = __read_pkru();
9632 if (vcpu->arch.pkru != vmx->host_pkru)
9633 __write_pkru(vmx->host_pkru);
9637 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9638 * we did not inject a still-pending event to L1 now because of
9639 * nested_run_pending, we need to re-enable this bit.
9641 if (vmx->nested.nested_run_pending)
9642 kvm_make_request(KVM_REQ_EVENT, vcpu);
9644 vmx->nested.nested_run_pending = 0;
9645 vmx->idt_vectoring_info = 0;
9647 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
9648 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
9651 vmx->loaded_vmcs->launched = 1;
9652 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9654 vmx_complete_atomic_exit(vmx);
9655 vmx_recover_nmi_blocking(vmx);
9656 vmx_complete_interrupts(vmx);
9658 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9660 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9662 struct vcpu_vmx *vmx = to_vmx(vcpu);
9665 if (vmx->loaded_vmcs == vmcs)
9669 vmx->loaded_vmcs = vmcs;
9671 vmx_vcpu_load(vcpu, cpu);
9677 * Ensure that the current vmcs of the logical processor is the
9678 * vmcs01 of the vcpu before calling free_nested().
9680 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9682 struct vcpu_vmx *vmx = to_vmx(vcpu);
9685 r = vcpu_load(vcpu);
9687 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9692 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9694 struct vcpu_vmx *vmx = to_vmx(vcpu);
9697 vmx_destroy_pml_buffer(vmx);
9698 free_vpid(vmx->vpid);
9699 leave_guest_mode(vcpu);
9700 vmx_free_vcpu_nested(vcpu);
9701 free_loaded_vmcs(vmx->loaded_vmcs);
9702 kfree(vmx->guest_msrs);
9703 kvm_vcpu_uninit(vcpu);
9704 kmem_cache_free(kvm_vcpu_cache, vmx);
9707 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9710 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9711 unsigned long *msr_bitmap;
9715 return ERR_PTR(-ENOMEM);
9717 vmx->vpid = allocate_vpid();
9719 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9726 * If PML is turned on, failure on enabling PML just results in failure
9727 * of creating the vcpu, therefore we can simplify PML logic (by
9728 * avoiding dealing with cases, such as enabling PML partially on vcpus
9729 * for the guest, etc.
9732 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9737 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9738 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9741 if (!vmx->guest_msrs)
9744 err = alloc_loaded_vmcs(&vmx->vmcs01);
9748 msr_bitmap = vmx->vmcs01.msr_bitmap;
9749 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
9750 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
9751 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
9752 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
9753 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
9754 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
9755 vmx->msr_bitmap_mode = 0;
9757 vmx->loaded_vmcs = &vmx->vmcs01;
9759 vmx_vcpu_load(&vmx->vcpu, cpu);
9760 vmx->vcpu.cpu = cpu;
9761 err = vmx_vcpu_setup(vmx);
9762 vmx_vcpu_put(&vmx->vcpu);
9766 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9767 err = alloc_apic_access_page(kvm);
9773 if (!kvm->arch.ept_identity_map_addr)
9774 kvm->arch.ept_identity_map_addr =
9775 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9776 err = init_rmode_identity_map(kvm);
9782 nested_vmx_setup_ctls_msrs(vmx);
9783 vmx->nested.vpid02 = allocate_vpid();
9786 vmx->nested.posted_intr_nv = -1;
9787 vmx->nested.current_vmptr = -1ull;
9789 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9792 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9793 * or POSTED_INTR_WAKEUP_VECTOR.
9795 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
9796 vmx->pi_desc.sn = 1;
9801 free_vpid(vmx->nested.vpid02);
9802 free_loaded_vmcs(vmx->loaded_vmcs);
9804 kfree(vmx->guest_msrs);
9806 vmx_destroy_pml_buffer(vmx);
9808 kvm_vcpu_uninit(&vmx->vcpu);
9810 free_vpid(vmx->vpid);
9811 kmem_cache_free(kvm_vcpu_cache, vmx);
9812 return ERR_PTR(err);
9815 static void __init vmx_check_processor_compat(void *rtn)
9817 struct vmcs_config vmcs_conf;
9820 if (setup_vmcs_config(&vmcs_conf) < 0)
9822 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9823 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9824 smp_processor_id());
9829 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9834 /* For VT-d and EPT combination
9835 * 1. MMIO: always map as UC
9837 * a. VT-d without snooping control feature: can't guarantee the
9838 * result, try to trust guest.
9839 * b. VT-d with snooping control feature: snooping control feature of
9840 * VT-d engine can guarantee the cache correctness. Just set it
9841 * to WB to keep consistent with host. So the same as item 3.
9842 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9843 * consistent with host MTRR
9846 cache = MTRR_TYPE_UNCACHABLE;
9850 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9851 ipat = VMX_EPT_IPAT_BIT;
9852 cache = MTRR_TYPE_WRBACK;
9856 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9857 ipat = VMX_EPT_IPAT_BIT;
9858 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9859 cache = MTRR_TYPE_WRBACK;
9861 cache = MTRR_TYPE_UNCACHABLE;
9865 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9868 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9871 static int vmx_get_lpage_level(void)
9873 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9874 return PT_DIRECTORY_LEVEL;
9876 /* For shadow and EPT supported 1GB page */
9877 return PT_PDPE_LEVEL;
9880 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9883 * These bits in the secondary execution controls field
9884 * are dynamic, the others are mostly based on the hypervisor
9885 * architecture and the guest's CPUID. Do not touch the
9889 SECONDARY_EXEC_SHADOW_VMCS |
9890 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9891 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9893 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9895 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9896 (new_ctl & ~mask) | (cur_ctl & mask));
9900 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9901 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9903 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9905 struct vcpu_vmx *vmx = to_vmx(vcpu);
9906 struct kvm_cpuid_entry2 *entry;
9908 vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9909 vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9911 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9912 if (entry && (entry->_reg & (_cpuid_mask))) \
9913 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9916 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9917 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
9918 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
9919 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
9920 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
9921 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
9922 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
9923 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
9924 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
9925 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
9926 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9927 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
9928 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
9929 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
9930 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
9932 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9933 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
9934 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
9935 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
9936 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
9937 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9938 cr4_fixed1_update(bit(11), ecx, bit(2));
9940 #undef cr4_fixed1_update
9943 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9945 struct vcpu_vmx *vmx = to_vmx(vcpu);
9947 if (cpu_has_secondary_exec_ctrls()) {
9948 vmx_compute_secondary_exec_control(vmx);
9949 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
9952 if (nested_vmx_allowed(vcpu))
9953 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9954 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9956 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9957 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9959 if (nested_vmx_allowed(vcpu))
9960 nested_vmx_cr_fixed1_bits_update(vcpu);
9963 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9965 if (func == 1 && nested)
9966 entry->ecx |= bit(X86_FEATURE_VMX);
9969 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9970 struct x86_exception *fault)
9972 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9973 struct vcpu_vmx *vmx = to_vmx(vcpu);
9975 unsigned long exit_qualification = vcpu->arch.exit_qualification;
9977 if (vmx->nested.pml_full) {
9978 exit_reason = EXIT_REASON_PML_FULL;
9979 vmx->nested.pml_full = false;
9980 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9981 } else if (fault->error_code & PFERR_RSVD_MASK)
9982 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9984 exit_reason = EXIT_REASON_EPT_VIOLATION;
9986 nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9987 vmcs12->guest_physical_address = fault->address;
9990 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9992 return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
9995 /* Callbacks for nested_ept_init_mmu_context: */
9997 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9999 /* return the page table to be shadowed - in our case, EPT12 */
10000 return get_vmcs12(vcpu)->ept_pointer;
10003 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
10005 WARN_ON(mmu_is_nested(vcpu));
10006 if (!valid_ept_address(vcpu, nested_ept_get_cr3(vcpu)))
10009 kvm_mmu_unload(vcpu);
10010 kvm_init_shadow_ept_mmu(vcpu,
10011 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
10012 VMX_EPT_EXECUTE_ONLY_BIT,
10013 nested_ept_ad_enabled(vcpu));
10014 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
10015 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
10016 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
10018 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
10022 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
10024 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
10027 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
10030 bool inequality, bit;
10032 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
10034 (error_code & vmcs12->page_fault_error_code_mask) !=
10035 vmcs12->page_fault_error_code_match;
10036 return inequality ^ bit;
10039 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
10040 struct x86_exception *fault)
10042 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10044 WARN_ON(!is_guest_mode(vcpu));
10046 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code) &&
10047 !to_vmx(vcpu)->nested.nested_run_pending) {
10048 vmcs12->vm_exit_intr_error_code = fault->error_code;
10049 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10050 PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
10051 INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
10054 kvm_inject_page_fault(vcpu, fault);
10058 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
10059 struct vmcs12 *vmcs12);
10061 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
10062 struct vmcs12 *vmcs12)
10064 struct vcpu_vmx *vmx = to_vmx(vcpu);
10068 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10070 * Translate L1 physical address to host physical
10071 * address for vmcs02. Keep the page pinned, so this
10072 * physical address remains valid. We keep a reference
10073 * to it so we can release it later.
10075 if (vmx->nested.apic_access_page) { /* shouldn't happen */
10076 kvm_release_page_dirty(vmx->nested.apic_access_page);
10077 vmx->nested.apic_access_page = NULL;
10079 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->apic_access_addr);
10081 * If translation failed, no matter: This feature asks
10082 * to exit when accessing the given address, and if it
10083 * can never be accessed, this feature won't do
10086 if (!is_error_page(page)) {
10087 vmx->nested.apic_access_page = page;
10088 hpa = page_to_phys(vmx->nested.apic_access_page);
10089 vmcs_write64(APIC_ACCESS_ADDR, hpa);
10091 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
10092 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10094 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
10095 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
10096 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
10097 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
10098 kvm_vcpu_reload_apic_access_page(vcpu);
10101 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
10102 if (vmx->nested.virtual_apic_page) { /* shouldn't happen */
10103 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
10104 vmx->nested.virtual_apic_page = NULL;
10106 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->virtual_apic_page_addr);
10109 * If translation failed, VM entry will fail because
10110 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
10111 * Failing the vm entry is _not_ what the processor
10112 * does but it's basically the only possibility we
10113 * have. We could still enter the guest if CR8 load
10114 * exits are enabled, CR8 store exits are enabled, and
10115 * virtualize APIC access is disabled; in this case
10116 * the processor would never use the TPR shadow and we
10117 * could simply clear the bit from the execution
10118 * control. But such a configuration is useless, so
10119 * let's keep the code simple.
10121 if (!is_error_page(page)) {
10122 vmx->nested.virtual_apic_page = page;
10123 hpa = page_to_phys(vmx->nested.virtual_apic_page);
10124 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
10128 if (nested_cpu_has_posted_intr(vmcs12)) {
10129 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
10130 kunmap(vmx->nested.pi_desc_page);
10131 kvm_release_page_dirty(vmx->nested.pi_desc_page);
10132 vmx->nested.pi_desc_page = NULL;
10134 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->posted_intr_desc_addr);
10135 if (is_error_page(page))
10137 vmx->nested.pi_desc_page = page;
10138 vmx->nested.pi_desc = kmap(vmx->nested.pi_desc_page);
10139 vmx->nested.pi_desc =
10140 (struct pi_desc *)((void *)vmx->nested.pi_desc +
10141 (unsigned long)(vmcs12->posted_intr_desc_addr &
10143 vmcs_write64(POSTED_INTR_DESC_ADDR,
10144 page_to_phys(vmx->nested.pi_desc_page) +
10145 (unsigned long)(vmcs12->posted_intr_desc_addr &
10148 if (cpu_has_vmx_msr_bitmap() &&
10149 nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
10150 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
10151 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
10152 CPU_BASED_USE_MSR_BITMAPS);
10154 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
10155 CPU_BASED_USE_MSR_BITMAPS);
10158 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
10160 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
10161 struct vcpu_vmx *vmx = to_vmx(vcpu);
10163 if (vcpu->arch.virtual_tsc_khz == 0)
10166 /* Make sure short timeouts reliably trigger an immediate vmexit.
10167 * hrtimer_start does not guarantee this. */
10168 if (preemption_timeout <= 1) {
10169 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
10173 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10174 preemption_timeout *= 1000000;
10175 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
10176 hrtimer_start(&vmx->nested.preemption_timer,
10177 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
10180 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
10181 struct vmcs12 *vmcs12)
10183 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
10186 if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
10187 !page_address_valid(vcpu, vmcs12->io_bitmap_b))
10193 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
10194 struct vmcs12 *vmcs12)
10196 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
10199 if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
10205 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu *vcpu,
10206 struct vmcs12 *vmcs12)
10208 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10211 if (!page_address_valid(vcpu, vmcs12->virtual_apic_page_addr))
10218 * Merge L0's and L1's MSR bitmap, return false to indicate that
10219 * we do not use the hardware.
10221 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
10222 struct vmcs12 *vmcs12)
10226 unsigned long *msr_bitmap_l1;
10227 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
10229 * pred_cmd & spec_ctrl are trying to verify two things:
10231 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
10232 * ensures that we do not accidentally generate an L02 MSR bitmap
10233 * from the L12 MSR bitmap that is too permissive.
10234 * 2. That L1 or L2s have actually used the MSR. This avoids
10235 * unnecessarily merging of the bitmap if the MSR is unused. This
10236 * works properly because we only update the L01 MSR bitmap lazily.
10237 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
10238 * updated to reflect this when L1 (or its L2s) actually write to
10241 bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
10242 bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
10244 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10245 !pred_cmd && !spec_ctrl)
10248 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->msr_bitmap);
10249 if (is_error_page(page))
10251 msr_bitmap_l1 = (unsigned long *)kmap(page);
10253 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
10255 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
10256 if (nested_cpu_has_apic_reg_virt(vmcs12))
10257 for (msr = 0x800; msr <= 0x8ff; msr++)
10258 nested_vmx_disable_intercept_for_msr(
10259 msr_bitmap_l1, msr_bitmap_l0,
10262 nested_vmx_disable_intercept_for_msr(
10263 msr_bitmap_l1, msr_bitmap_l0,
10264 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
10265 MSR_TYPE_R | MSR_TYPE_W);
10267 if (nested_cpu_has_vid(vmcs12)) {
10268 nested_vmx_disable_intercept_for_msr(
10269 msr_bitmap_l1, msr_bitmap_l0,
10270 APIC_BASE_MSR + (APIC_EOI >> 4),
10272 nested_vmx_disable_intercept_for_msr(
10273 msr_bitmap_l1, msr_bitmap_l0,
10274 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
10280 nested_vmx_disable_intercept_for_msr(
10281 msr_bitmap_l1, msr_bitmap_l0,
10282 MSR_IA32_SPEC_CTRL,
10283 MSR_TYPE_R | MSR_TYPE_W);
10286 nested_vmx_disable_intercept_for_msr(
10287 msr_bitmap_l1, msr_bitmap_l0,
10292 kvm_release_page_clean(page);
10297 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
10298 struct vmcs12 *vmcs12)
10300 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10301 !nested_cpu_has_apic_reg_virt(vmcs12) &&
10302 !nested_cpu_has_vid(vmcs12) &&
10303 !nested_cpu_has_posted_intr(vmcs12))
10307 * If virtualize x2apic mode is enabled,
10308 * virtualize apic access must be disabled.
10310 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10311 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
10315 * If virtual interrupt delivery is enabled,
10316 * we must exit on external interrupts.
10318 if (nested_cpu_has_vid(vmcs12) &&
10319 !nested_exit_on_intr(vcpu))
10323 * bits 15:8 should be zero in posted_intr_nv,
10324 * the descriptor address has been already checked
10325 * in nested_get_vmcs12_pages.
10327 if (nested_cpu_has_posted_intr(vmcs12) &&
10328 (!nested_cpu_has_vid(vmcs12) ||
10329 !nested_exit_intr_ack_set(vcpu) ||
10330 vmcs12->posted_intr_nv & 0xff00))
10333 /* tpr shadow is needed by all apicv features. */
10334 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10340 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10341 unsigned long count_field,
10342 unsigned long addr_field)
10347 if (vmcs12_read_any(vcpu, count_field, &count) ||
10348 vmcs12_read_any(vcpu, addr_field, &addr)) {
10354 maxphyaddr = cpuid_maxphyaddr(vcpu);
10355 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10356 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
10357 pr_debug_ratelimited(
10358 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10359 addr_field, maxphyaddr, count, addr);
10365 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10366 struct vmcs12 *vmcs12)
10368 if (vmcs12->vm_exit_msr_load_count == 0 &&
10369 vmcs12->vm_exit_msr_store_count == 0 &&
10370 vmcs12->vm_entry_msr_load_count == 0)
10371 return 0; /* Fast path */
10372 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
10373 VM_EXIT_MSR_LOAD_ADDR) ||
10374 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
10375 VM_EXIT_MSR_STORE_ADDR) ||
10376 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
10377 VM_ENTRY_MSR_LOAD_ADDR))
10382 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
10383 struct vmcs12 *vmcs12)
10385 u64 address = vmcs12->pml_address;
10386 int maxphyaddr = cpuid_maxphyaddr(vcpu);
10388 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
10389 if (!nested_cpu_has_ept(vmcs12) ||
10390 !IS_ALIGNED(address, 4096) ||
10391 address >> maxphyaddr)
10398 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10399 struct vmx_msr_entry *e)
10401 /* x2APIC MSR accesses are not allowed */
10402 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
10404 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10405 e->index == MSR_IA32_UCODE_REV)
10407 if (e->reserved != 0)
10412 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10413 struct vmx_msr_entry *e)
10415 if (e->index == MSR_FS_BASE ||
10416 e->index == MSR_GS_BASE ||
10417 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10418 nested_vmx_msr_check_common(vcpu, e))
10423 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10424 struct vmx_msr_entry *e)
10426 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10427 nested_vmx_msr_check_common(vcpu, e))
10433 * Load guest's/host's msr at nested entry/exit.
10434 * return 0 for success, entry index for failure.
10436 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10439 struct vmx_msr_entry e;
10440 struct msr_data msr;
10442 msr.host_initiated = false;
10443 for (i = 0; i < count; i++) {
10444 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10446 pr_debug_ratelimited(
10447 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10448 __func__, i, gpa + i * sizeof(e));
10451 if (nested_vmx_load_msr_check(vcpu, &e)) {
10452 pr_debug_ratelimited(
10453 "%s check failed (%u, 0x%x, 0x%x)\n",
10454 __func__, i, e.index, e.reserved);
10457 msr.index = e.index;
10458 msr.data = e.value;
10459 if (kvm_set_msr(vcpu, &msr)) {
10460 pr_debug_ratelimited(
10461 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10462 __func__, i, e.index, e.value);
10471 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10474 struct vmx_msr_entry e;
10476 for (i = 0; i < count; i++) {
10477 struct msr_data msr_info;
10478 if (kvm_vcpu_read_guest(vcpu,
10479 gpa + i * sizeof(e),
10480 &e, 2 * sizeof(u32))) {
10481 pr_debug_ratelimited(
10482 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10483 __func__, i, gpa + i * sizeof(e));
10486 if (nested_vmx_store_msr_check(vcpu, &e)) {
10487 pr_debug_ratelimited(
10488 "%s check failed (%u, 0x%x, 0x%x)\n",
10489 __func__, i, e.index, e.reserved);
10492 msr_info.host_initiated = false;
10493 msr_info.index = e.index;
10494 if (kvm_get_msr(vcpu, &msr_info)) {
10495 pr_debug_ratelimited(
10496 "%s cannot read MSR (%u, 0x%x)\n",
10497 __func__, i, e.index);
10500 if (kvm_vcpu_write_guest(vcpu,
10501 gpa + i * sizeof(e) +
10502 offsetof(struct vmx_msr_entry, value),
10503 &msr_info.data, sizeof(msr_info.data))) {
10504 pr_debug_ratelimited(
10505 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10506 __func__, i, e.index, msr_info.data);
10513 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
10515 unsigned long invalid_mask;
10517 invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
10518 return (val & invalid_mask) == 0;
10522 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10523 * emulating VM entry into a guest with EPT enabled.
10524 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10525 * is assigned to entry_failure_code on failure.
10527 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
10528 u32 *entry_failure_code)
10530 if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
10531 if (!nested_cr3_valid(vcpu, cr3)) {
10532 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10537 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10538 * must not be dereferenced.
10540 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
10542 if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
10543 *entry_failure_code = ENTRY_FAIL_PDPTE;
10548 vcpu->arch.cr3 = cr3;
10549 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
10552 kvm_mmu_reset_context(vcpu);
10557 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10558 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10559 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10560 * guest in a way that will both be appropriate to L1's requests, and our
10561 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10562 * function also has additional necessary side-effects, like setting various
10563 * vcpu->arch fields.
10564 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10565 * is assigned to entry_failure_code on failure.
10567 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10568 bool from_vmentry, u32 *entry_failure_code)
10570 struct vcpu_vmx *vmx = to_vmx(vcpu);
10571 u32 exec_control, vmcs12_exec_ctrl;
10573 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10574 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10575 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10576 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10577 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10578 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10579 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10580 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10581 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10582 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10583 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10584 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10585 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10586 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10587 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10588 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10589 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10590 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10591 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10592 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10593 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10594 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10595 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10596 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10597 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10598 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10599 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10600 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10601 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10602 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10603 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10604 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10605 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10606 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10607 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10608 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10610 if (from_vmentry &&
10611 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10612 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10613 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10615 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10616 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10618 if (from_vmentry) {
10619 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10620 vmcs12->vm_entry_intr_info_field);
10621 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10622 vmcs12->vm_entry_exception_error_code);
10623 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10624 vmcs12->vm_entry_instruction_len);
10625 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10626 vmcs12->guest_interruptibility_info);
10627 vmx->loaded_vmcs->nmi_known_unmasked =
10628 !(vmcs12->guest_interruptibility_info & GUEST_INTR_STATE_NMI);
10630 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10632 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10633 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10634 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10635 vmcs12->guest_pending_dbg_exceptions);
10636 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10637 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10639 if (nested_cpu_has_xsaves(vmcs12))
10640 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10641 vmcs_write64(VMCS_LINK_POINTER, -1ull);
10643 exec_control = vmcs12->pin_based_vm_exec_control;
10645 /* Preemption timer setting is only taken from vmcs01. */
10646 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10647 exec_control |= vmcs_config.pin_based_exec_ctrl;
10648 if (vmx->hv_deadline_tsc == -1)
10649 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10651 /* Posted interrupts setting is only taken from vmcs12. */
10652 if (nested_cpu_has_posted_intr(vmcs12)) {
10653 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10654 vmx->nested.pi_pending = false;
10655 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_NESTED_VECTOR);
10657 exec_control &= ~PIN_BASED_POSTED_INTR;
10660 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10662 vmx->nested.preemption_timer_expired = false;
10663 if (nested_cpu_has_preemption_timer(vmcs12))
10664 vmx_start_preemption_timer(vcpu);
10667 * Whether page-faults are trapped is determined by a combination of
10668 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10669 * If enable_ept, L0 doesn't care about page faults and we should
10670 * set all of these to L1's desires. However, if !enable_ept, L0 does
10671 * care about (at least some) page faults, and because it is not easy
10672 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10673 * to exit on each and every L2 page fault. This is done by setting
10674 * MASK=MATCH=0 and (see below) EB.PF=1.
10675 * Note that below we don't need special code to set EB.PF beyond the
10676 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10677 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10678 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10680 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10681 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10682 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10683 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10685 if (cpu_has_secondary_exec_ctrls()) {
10686 exec_control = vmx->secondary_exec_control;
10688 /* Take the following fields only from vmcs12 */
10689 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10690 SECONDARY_EXEC_ENABLE_INVPCID |
10691 SECONDARY_EXEC_RDTSCP |
10692 SECONDARY_EXEC_XSAVES |
10693 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10694 SECONDARY_EXEC_APIC_REGISTER_VIRT |
10695 SECONDARY_EXEC_ENABLE_VMFUNC);
10696 if (nested_cpu_has(vmcs12,
10697 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10698 vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10699 ~SECONDARY_EXEC_ENABLE_PML;
10700 exec_control |= vmcs12_exec_ctrl;
10703 /* All VMFUNCs are currently emulated through L0 vmexits. */
10704 if (exec_control & SECONDARY_EXEC_ENABLE_VMFUNC)
10705 vmcs_write64(VM_FUNCTION_CONTROL, 0);
10707 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10708 vmcs_write64(EOI_EXIT_BITMAP0,
10709 vmcs12->eoi_exit_bitmap0);
10710 vmcs_write64(EOI_EXIT_BITMAP1,
10711 vmcs12->eoi_exit_bitmap1);
10712 vmcs_write64(EOI_EXIT_BITMAP2,
10713 vmcs12->eoi_exit_bitmap2);
10714 vmcs_write64(EOI_EXIT_BITMAP3,
10715 vmcs12->eoi_exit_bitmap3);
10716 vmcs_write16(GUEST_INTR_STATUS,
10717 vmcs12->guest_intr_status);
10721 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10722 * nested_get_vmcs12_pages will either fix it up or
10723 * remove the VM execution control.
10725 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10726 vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10728 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10733 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10734 * Some constant fields are set here by vmx_set_constant_host_state().
10735 * Other fields are different per CPU, and will be set later when
10736 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10738 vmx_set_constant_host_state(vmx);
10741 * Set the MSR load/store lists to match L0's settings.
10743 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10744 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10745 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10746 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10747 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10750 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10751 * entry, but only if the current (host) sp changed from the value
10752 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10753 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10754 * here we just force the write to happen on entry.
10758 exec_control = vmx_exec_control(vmx); /* L0's desires */
10759 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10760 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10761 exec_control &= ~CPU_BASED_TPR_SHADOW;
10762 exec_control |= vmcs12->cpu_based_vm_exec_control;
10765 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10766 * nested_get_vmcs12_pages can't fix it up, the illegal value
10767 * will result in a VM entry failure.
10769 if (exec_control & CPU_BASED_TPR_SHADOW) {
10770 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10771 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10773 #ifdef CONFIG_X86_64
10774 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
10775 CPU_BASED_CR8_STORE_EXITING;
10780 * Merging of IO bitmap not currently supported.
10781 * Rather, exit every time.
10783 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10784 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10786 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10788 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10789 * bitwise-or of what L1 wants to trap for L2, and what we want to
10790 * trap. Note that CR0.TS also needs updating - we do this later.
10792 update_exception_bitmap(vcpu);
10793 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10794 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10796 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10797 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10798 * bits are further modified by vmx_set_efer() below.
10800 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10802 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10803 * emulated by vmx_set_efer(), below.
10805 vm_entry_controls_init(vmx,
10806 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10807 ~VM_ENTRY_IA32E_MODE) |
10808 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10810 if (from_vmentry &&
10811 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10812 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10813 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10814 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10815 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10818 set_cr4_guest_host_mask(vmx);
10820 if (from_vmentry &&
10821 vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10822 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10824 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10825 vmcs_write64(TSC_OFFSET,
10826 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10828 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10829 if (kvm_has_tsc_control)
10830 decache_tsc_multiplier(vmx);
10832 if (cpu_has_vmx_msr_bitmap())
10833 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
10837 * There is no direct mapping between vpid02 and vpid12, the
10838 * vpid02 is per-vCPU for L0 and reused while the value of
10839 * vpid12 is changed w/ one invvpid during nested vmentry.
10840 * The vpid12 is allocated by L1 for L2, so it will not
10841 * influence global bitmap(for vpid01 and vpid02 allocation)
10842 * even if spawn a lot of nested vCPUs.
10844 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10845 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10846 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10847 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10848 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10851 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10852 vmx_flush_tlb(vcpu);
10859 * Conceptually we want to copy the PML address and index from
10860 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10861 * since we always flush the log on each vmexit, this happens
10862 * to be equivalent to simply resetting the fields in vmcs02.
10864 ASSERT(vmx->pml_pg);
10865 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10866 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10869 if (nested_cpu_has_ept(vmcs12)) {
10870 if (nested_ept_init_mmu_context(vcpu)) {
10871 *entry_failure_code = ENTRY_FAIL_DEFAULT;
10874 } else if (nested_cpu_has2(vmcs12,
10875 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10876 vmx_flush_tlb_ept_only(vcpu);
10880 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10881 * bits which we consider mandatory enabled.
10882 * The CR0_READ_SHADOW is what L2 should have expected to read given
10883 * the specifications by L1; It's not enough to take
10884 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10885 * have more bits than L1 expected.
10887 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10888 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10890 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10891 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10893 if (from_vmentry &&
10894 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10895 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10896 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10897 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10899 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10900 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10901 vmx_set_efer(vcpu, vcpu->arch.efer);
10903 /* Shadow page tables on either EPT or shadow page tables. */
10904 if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10905 entry_failure_code))
10909 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10912 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10915 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10916 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10917 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10918 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10921 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10922 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10926 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10928 struct vcpu_vmx *vmx = to_vmx(vcpu);
10930 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10931 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10932 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10934 if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10935 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10937 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10938 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10940 if (nested_vmx_check_tpr_shadow_controls(vcpu, vmcs12))
10941 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10943 if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10944 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10946 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10947 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10949 if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10950 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10952 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10953 vmx->nested.nested_vmx_procbased_ctls_low,
10954 vmx->nested.nested_vmx_procbased_ctls_high) ||
10955 (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10956 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10957 vmx->nested.nested_vmx_secondary_ctls_low,
10958 vmx->nested.nested_vmx_secondary_ctls_high)) ||
10959 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10960 vmx->nested.nested_vmx_pinbased_ctls_low,
10961 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10962 !vmx_control_verify(vmcs12->vm_exit_controls,
10963 vmx->nested.nested_vmx_exit_ctls_low,
10964 vmx->nested.nested_vmx_exit_ctls_high) ||
10965 !vmx_control_verify(vmcs12->vm_entry_controls,
10966 vmx->nested.nested_vmx_entry_ctls_low,
10967 vmx->nested.nested_vmx_entry_ctls_high))
10968 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10970 if (nested_cpu_has_vmfunc(vmcs12)) {
10971 if (vmcs12->vm_function_control &
10972 ~vmx->nested.nested_vmx_vmfunc_controls)
10973 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10975 if (nested_cpu_has_eptp_switching(vmcs12)) {
10976 if (!nested_cpu_has_ept(vmcs12) ||
10977 !page_address_valid(vcpu, vmcs12->eptp_list_address))
10978 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10982 if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10983 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10985 if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10986 !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10987 !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10988 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10993 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10998 *exit_qual = ENTRY_FAIL_DEFAULT;
11000 if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
11001 !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
11004 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
11005 vmcs12->vmcs_link_pointer != -1ull) {
11006 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
11011 * If the load IA32_EFER VM-entry control is 1, the following checks
11012 * are performed on the field for the IA32_EFER MSR:
11013 * - Bits reserved in the IA32_EFER MSR must be 0.
11014 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
11015 * the IA-32e mode guest VM-exit control. It must also be identical
11016 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
11019 if (to_vmx(vcpu)->nested.nested_run_pending &&
11020 (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
11021 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
11022 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
11023 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
11024 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
11025 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
11030 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
11031 * IA32_EFER MSR must be 0 in the field for that register. In addition,
11032 * the values of the LMA and LME bits in the field must each be that of
11033 * the host address-space size VM-exit control.
11035 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
11036 ia32e = (vmcs12->vm_exit_controls &
11037 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
11038 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
11039 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
11040 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
11047 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
11049 struct vcpu_vmx *vmx = to_vmx(vcpu);
11050 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11054 enter_guest_mode(vcpu);
11056 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
11057 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11059 vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
11060 vmx_segment_cache_clear(vmx);
11062 if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
11063 leave_guest_mode(vcpu);
11064 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11065 nested_vmx_entry_failure(vcpu, vmcs12,
11066 EXIT_REASON_INVALID_STATE, exit_qual);
11070 nested_get_vmcs12_pages(vcpu, vmcs12);
11072 msr_entry_idx = nested_vmx_load_msr(vcpu,
11073 vmcs12->vm_entry_msr_load_addr,
11074 vmcs12->vm_entry_msr_load_count);
11075 if (msr_entry_idx) {
11076 leave_guest_mode(vcpu);
11077 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11078 nested_vmx_entry_failure(vcpu, vmcs12,
11079 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
11084 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
11085 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
11086 * returned as far as L1 is concerned. It will only return (and set
11087 * the success flag) when L2 exits (see nested_vmx_vmexit()).
11093 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
11094 * for running an L2 nested guest.
11096 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
11098 struct vmcs12 *vmcs12;
11099 struct vcpu_vmx *vmx = to_vmx(vcpu);
11100 u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
11104 if (!nested_vmx_check_permission(vcpu))
11107 if (!nested_vmx_check_vmcs12(vcpu))
11110 vmcs12 = get_vmcs12(vcpu);
11112 if (enable_shadow_vmcs)
11113 copy_shadow_to_vmcs12(vmx);
11116 * The nested entry process starts with enforcing various prerequisites
11117 * on vmcs12 as required by the Intel SDM, and act appropriately when
11118 * they fail: As the SDM explains, some conditions should cause the
11119 * instruction to fail, while others will cause the instruction to seem
11120 * to succeed, but return an EXIT_REASON_INVALID_STATE.
11121 * To speed up the normal (success) code path, we should avoid checking
11122 * for misconfigurations which will anyway be caught by the processor
11123 * when using the merged vmcs02.
11125 if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
11126 nested_vmx_failValid(vcpu,
11127 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
11131 if (vmcs12->launch_state == launch) {
11132 nested_vmx_failValid(vcpu,
11133 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
11134 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
11138 ret = check_vmentry_prereqs(vcpu, vmcs12);
11140 nested_vmx_failValid(vcpu, ret);
11145 * After this point, the trap flag no longer triggers a singlestep trap
11146 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11147 * This is not 100% correct; for performance reasons, we delegate most
11148 * of the checks on host state to the processor. If those fail,
11149 * the singlestep trap is missed.
11151 skip_emulated_instruction(vcpu);
11153 ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
11155 nested_vmx_entry_failure(vcpu, vmcs12,
11156 EXIT_REASON_INVALID_STATE, exit_qual);
11161 * We're finally done with prerequisite checking, and can start with
11162 * the nested entry.
11165 ret = enter_vmx_non_root_mode(vcpu, true);
11169 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
11170 return kvm_vcpu_halt(vcpu);
11172 vmx->nested.nested_run_pending = 1;
11177 return kvm_skip_emulated_instruction(vcpu);
11181 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11182 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11183 * This function returns the new value we should put in vmcs12.guest_cr0.
11184 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11185 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11186 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11187 * didn't trap the bit, because if L1 did, so would L0).
11188 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11189 * been modified by L2, and L1 knows it. So just leave the old value of
11190 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11191 * isn't relevant, because if L0 traps this bit it can set it to anything.
11192 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11193 * changed these bits, and therefore they need to be updated, but L0
11194 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11195 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11197 static inline unsigned long
11198 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11201 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
11202 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
11203 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
11204 vcpu->arch.cr0_guest_owned_bits));
11207 static inline unsigned long
11208 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11211 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
11212 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
11213 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
11214 vcpu->arch.cr4_guest_owned_bits));
11217 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
11218 struct vmcs12 *vmcs12)
11223 if (vcpu->arch.exception.injected) {
11224 nr = vcpu->arch.exception.nr;
11225 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11227 if (kvm_exception_is_soft(nr)) {
11228 vmcs12->vm_exit_instruction_len =
11229 vcpu->arch.event_exit_inst_len;
11230 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
11232 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
11234 if (vcpu->arch.exception.has_error_code) {
11235 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
11236 vmcs12->idt_vectoring_error_code =
11237 vcpu->arch.exception.error_code;
11240 vmcs12->idt_vectoring_info_field = idt_vectoring;
11241 } else if (vcpu->arch.nmi_injected) {
11242 vmcs12->idt_vectoring_info_field =
11243 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
11244 } else if (vcpu->arch.interrupt.pending) {
11245 nr = vcpu->arch.interrupt.nr;
11246 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
11248 if (vcpu->arch.interrupt.soft) {
11249 idt_vectoring |= INTR_TYPE_SOFT_INTR;
11250 vmcs12->vm_entry_instruction_len =
11251 vcpu->arch.event_exit_inst_len;
11253 idt_vectoring |= INTR_TYPE_EXT_INTR;
11255 vmcs12->idt_vectoring_info_field = idt_vectoring;
11259 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
11261 struct vcpu_vmx *vmx = to_vmx(vcpu);
11262 unsigned long exit_qual;
11263 bool block_nested_events =
11264 vmx->nested.nested_run_pending || kvm_event_needs_reinjection(vcpu);
11266 if (vcpu->arch.exception.pending &&
11267 nested_vmx_check_exception(vcpu, &exit_qual)) {
11268 if (block_nested_events)
11270 nested_vmx_inject_exception_vmexit(vcpu, exit_qual);
11274 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
11275 vmx->nested.preemption_timer_expired) {
11276 if (block_nested_events)
11278 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
11282 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
11283 if (block_nested_events)
11285 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
11286 NMI_VECTOR | INTR_TYPE_NMI_INTR |
11287 INTR_INFO_VALID_MASK, 0);
11289 * The NMI-triggered VM exit counts as injection:
11290 * clear this one and block further NMIs.
11292 vcpu->arch.nmi_pending = 0;
11293 vmx_set_nmi_mask(vcpu, true);
11297 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
11298 nested_exit_on_intr(vcpu)) {
11299 if (block_nested_events)
11301 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
11305 vmx_complete_nested_posted_interrupt(vcpu);
11309 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
11311 ktime_t remaining =
11312 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
11315 if (ktime_to_ns(remaining) <= 0)
11318 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
11319 do_div(value, 1000000);
11320 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
11324 * Update the guest state fields of vmcs12 to reflect changes that
11325 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11326 * VM-entry controls is also updated, since this is really a guest
11329 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
11331 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
11332 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
11334 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
11335 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
11336 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
11338 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
11339 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
11340 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
11341 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
11342 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
11343 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
11344 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
11345 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
11346 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
11347 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
11348 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
11349 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
11350 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
11351 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
11352 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
11353 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
11354 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
11355 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
11356 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
11357 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
11358 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
11359 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
11360 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
11361 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
11362 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
11363 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
11364 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
11365 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
11366 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
11367 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
11368 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
11369 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
11370 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
11371 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
11372 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
11373 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
11375 vmcs12->guest_interruptibility_info =
11376 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
11377 vmcs12->guest_pending_dbg_exceptions =
11378 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
11379 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11380 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
11382 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
11384 if (nested_cpu_has_preemption_timer(vmcs12)) {
11385 if (vmcs12->vm_exit_controls &
11386 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
11387 vmcs12->vmx_preemption_timer_value =
11388 vmx_get_preemption_timer_value(vcpu);
11389 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
11393 * In some cases (usually, nested EPT), L2 is allowed to change its
11394 * own CR3 without exiting. If it has changed it, we must keep it.
11395 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11396 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11398 * Additionally, restore L2's PDPTR to vmcs12.
11401 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
11402 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
11403 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
11404 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
11405 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
11408 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
11410 if (nested_cpu_has_vid(vmcs12))
11411 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
11413 vmcs12->vm_entry_controls =
11414 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
11415 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
11417 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
11418 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
11419 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
11422 /* TODO: These cannot have changed unless we have MSR bitmaps and
11423 * the relevant bit asks not to trap the change */
11424 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
11425 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
11426 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11427 vmcs12->guest_ia32_efer = vcpu->arch.efer;
11428 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11429 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11430 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
11431 if (kvm_mpx_supported())
11432 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
11436 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11437 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11438 * and this function updates it to reflect the changes to the guest state while
11439 * L2 was running (and perhaps made some exits which were handled directly by L0
11440 * without going back to L1), and to reflect the exit reason.
11441 * Note that we do not have to copy here all VMCS fields, just those that
11442 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11443 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11444 * which already writes to vmcs12 directly.
11446 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
11447 u32 exit_reason, u32 exit_intr_info,
11448 unsigned long exit_qualification)
11450 /* update guest state fields: */
11451 sync_vmcs12(vcpu, vmcs12);
11453 /* update exit information fields: */
11455 vmcs12->vm_exit_reason = exit_reason;
11456 vmcs12->exit_qualification = exit_qualification;
11457 vmcs12->vm_exit_intr_info = exit_intr_info;
11459 vmcs12->idt_vectoring_info_field = 0;
11460 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11461 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11463 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11464 vmcs12->launch_state = 1;
11466 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11467 * instead of reading the real value. */
11468 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
11471 * Transfer the event that L0 or L1 may wanted to inject into
11472 * L2 to IDT_VECTORING_INFO_FIELD.
11474 vmcs12_save_pending_event(vcpu, vmcs12);
11478 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11479 * preserved above and would only end up incorrectly in L1.
11481 vcpu->arch.nmi_injected = false;
11482 kvm_clear_exception_queue(vcpu);
11483 kvm_clear_interrupt_queue(vcpu);
11486 static void load_vmcs12_mmu_host_state(struct kvm_vcpu *vcpu,
11487 struct vmcs12 *vmcs12)
11489 u32 entry_failure_code;
11491 nested_ept_uninit_mmu_context(vcpu);
11494 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11495 * couldn't have changed.
11497 if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
11498 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
11501 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11505 * A part of what we need to when the nested L2 guest exits and we want to
11506 * run its L1 parent, is to reset L1's guest state to the host state specified
11508 * This function is to be called not only on normal nested exit, but also on
11509 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11510 * Failures During or After Loading Guest State").
11511 * This function should be called when the active VMCS is L1's (vmcs01).
11513 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11514 struct vmcs12 *vmcs12)
11516 struct kvm_segment seg;
11518 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11519 vcpu->arch.efer = vmcs12->host_ia32_efer;
11520 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11521 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11523 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11524 vmx_set_efer(vcpu, vcpu->arch.efer);
11526 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11527 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
11528 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
11530 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11531 * actually changed, because vmx_set_cr0 refers to efer set above.
11533 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11534 * (KVM doesn't change it);
11536 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
11537 vmx_set_cr0(vcpu, vmcs12->host_cr0);
11539 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11540 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
11541 vmx_set_cr4(vcpu, vmcs12->host_cr4);
11543 load_vmcs12_mmu_host_state(vcpu, vmcs12);
11547 * Trivially support vpid by letting L2s share their parent
11548 * L1's vpid. TODO: move to a more elaborate solution, giving
11549 * each L2 its own vpid and exposing the vpid feature to L1.
11551 vmx_flush_tlb(vcpu);
11553 /* Restore posted intr vector. */
11554 if (nested_cpu_has_posted_intr(vmcs12))
11555 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
11557 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11558 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11559 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11560 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11561 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
11562 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
11563 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
11565 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11566 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11567 vmcs_write64(GUEST_BNDCFGS, 0);
11569 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
11570 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
11571 vcpu->arch.pat = vmcs12->host_ia32_pat;
11573 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11574 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11575 vmcs12->host_ia32_perf_global_ctrl);
11577 /* Set L1 segment info according to Intel SDM
11578 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11579 seg = (struct kvm_segment) {
11581 .limit = 0xFFFFFFFF,
11582 .selector = vmcs12->host_cs_selector,
11588 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11592 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11593 seg = (struct kvm_segment) {
11595 .limit = 0xFFFFFFFF,
11602 seg.selector = vmcs12->host_ds_selector;
11603 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11604 seg.selector = vmcs12->host_es_selector;
11605 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11606 seg.selector = vmcs12->host_ss_selector;
11607 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11608 seg.selector = vmcs12->host_fs_selector;
11609 seg.base = vmcs12->host_fs_base;
11610 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11611 seg.selector = vmcs12->host_gs_selector;
11612 seg.base = vmcs12->host_gs_base;
11613 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11614 seg = (struct kvm_segment) {
11615 .base = vmcs12->host_tr_base,
11617 .selector = vmcs12->host_tr_selector,
11621 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11623 kvm_set_dr(vcpu, 7, 0x400);
11624 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11626 if (cpu_has_vmx_msr_bitmap())
11627 vmx_update_msr_bitmap(vcpu);
11629 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11630 vmcs12->vm_exit_msr_load_count))
11631 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11635 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11636 * and modify vmcs12 to make it see what it would expect to see there if
11637 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11639 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11640 u32 exit_intr_info,
11641 unsigned long exit_qualification)
11643 struct vcpu_vmx *vmx = to_vmx(vcpu);
11644 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11646 /* trying to cancel vmlaunch/vmresume is a bug */
11647 WARN_ON_ONCE(vmx->nested.nested_run_pending);
11650 * The only expected VM-instruction error is "VM entry with
11651 * invalid control field(s)." Anything else indicates a
11654 WARN_ON_ONCE(vmx->fail && (vmcs_read32(VM_INSTRUCTION_ERROR) !=
11655 VMXERR_ENTRY_INVALID_CONTROL_FIELD));
11657 leave_guest_mode(vcpu);
11659 if (likely(!vmx->fail)) {
11660 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11661 exit_qualification);
11663 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11664 vmcs12->vm_exit_msr_store_count))
11665 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11668 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11669 vm_entry_controls_reset_shadow(vmx);
11670 vm_exit_controls_reset_shadow(vmx);
11671 vmx_segment_cache_clear(vmx);
11673 /* Update any VMCS fields that might have changed while L2 ran */
11674 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11675 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11676 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11677 if (vmx->hv_deadline_tsc == -1)
11678 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11679 PIN_BASED_VMX_PREEMPTION_TIMER);
11681 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11682 PIN_BASED_VMX_PREEMPTION_TIMER);
11683 if (kvm_has_tsc_control)
11684 decache_tsc_multiplier(vmx);
11686 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11687 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11688 vmx_set_virtual_x2apic_mode(vcpu,
11689 vcpu->arch.apic_base & X2APIC_ENABLE);
11690 } else if (!nested_cpu_has_ept(vmcs12) &&
11691 nested_cpu_has2(vmcs12,
11692 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11693 vmx_flush_tlb_ept_only(vcpu);
11696 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11699 /* Unpin physical memory we referred to in vmcs02 */
11700 if (vmx->nested.apic_access_page) {
11701 kvm_release_page_dirty(vmx->nested.apic_access_page);
11702 vmx->nested.apic_access_page = NULL;
11704 if (vmx->nested.virtual_apic_page) {
11705 kvm_release_page_dirty(vmx->nested.virtual_apic_page);
11706 vmx->nested.virtual_apic_page = NULL;
11708 if (vmx->nested.pi_desc_page) {
11709 kunmap(vmx->nested.pi_desc_page);
11710 kvm_release_page_dirty(vmx->nested.pi_desc_page);
11711 vmx->nested.pi_desc_page = NULL;
11712 vmx->nested.pi_desc = NULL;
11716 * We are now running in L2, mmu_notifier will force to reload the
11717 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11719 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11721 if (enable_shadow_vmcs)
11722 vmx->nested.sync_shadow_vmcs = true;
11724 /* in case we halted in L2 */
11725 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11727 if (likely(!vmx->fail)) {
11729 * TODO: SDM says that with acknowledge interrupt on
11730 * exit, bit 31 of the VM-exit interrupt information
11731 * (valid interrupt) is always set to 1 on
11732 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11733 * need kvm_cpu_has_interrupt(). See the commit
11734 * message for details.
11736 if (nested_exit_intr_ack_set(vcpu) &&
11737 exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT &&
11738 kvm_cpu_has_interrupt(vcpu)) {
11739 int irq = kvm_cpu_get_interrupt(vcpu);
11741 vmcs12->vm_exit_intr_info = irq |
11742 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11745 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11746 vmcs12->exit_qualification,
11747 vmcs12->idt_vectoring_info_field,
11748 vmcs12->vm_exit_intr_info,
11749 vmcs12->vm_exit_intr_error_code,
11752 load_vmcs12_host_state(vcpu, vmcs12);
11758 * After an early L2 VM-entry failure, we're now back
11759 * in L1 which thinks it just finished a VMLAUNCH or
11760 * VMRESUME instruction, so we need to set the failure
11761 * flag and the VM-instruction error field of the VMCS
11764 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
11766 load_vmcs12_mmu_host_state(vcpu, vmcs12);
11769 * The emulated instruction was already skipped in
11770 * nested_vmx_run, but the updated RIP was never
11771 * written back to the vmcs01.
11773 skip_emulated_instruction(vcpu);
11778 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11780 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11782 if (is_guest_mode(vcpu)) {
11783 to_vmx(vcpu)->nested.nested_run_pending = 0;
11784 nested_vmx_vmexit(vcpu, -1, 0, 0);
11786 free_nested(to_vmx(vcpu));
11790 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11791 * 23.7 "VM-entry failures during or after loading guest state" (this also
11792 * lists the acceptable exit-reason and exit-qualification parameters).
11793 * It should only be called before L2 actually succeeded to run, and when
11794 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11796 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11797 struct vmcs12 *vmcs12,
11798 u32 reason, unsigned long qualification)
11800 load_vmcs12_host_state(vcpu, vmcs12);
11801 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11802 vmcs12->exit_qualification = qualification;
11803 nested_vmx_succeed(vcpu);
11804 if (enable_shadow_vmcs)
11805 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11808 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11809 struct x86_instruction_info *info,
11810 enum x86_intercept_stage stage)
11812 return X86EMUL_CONTINUE;
11815 #ifdef CONFIG_X86_64
11816 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11817 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11818 u64 divisor, u64 *result)
11820 u64 low = a << shift, high = a >> (64 - shift);
11822 /* To avoid the overflow on divq */
11823 if (high >= divisor)
11826 /* Low hold the result, high hold rem which is discarded */
11827 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11828 "rm" (divisor), "0" (low), "1" (high));
11834 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11836 struct vcpu_vmx *vmx = to_vmx(vcpu);
11837 u64 tscl = rdtsc();
11838 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11839 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11841 /* Convert to host delta tsc if tsc scaling is enabled */
11842 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11843 u64_shl_div_u64(delta_tsc,
11844 kvm_tsc_scaling_ratio_frac_bits,
11845 vcpu->arch.tsc_scaling_ratio,
11850 * If the delta tsc can't fit in the 32 bit after the multi shift,
11851 * we can't use the preemption timer.
11852 * It's possible that it fits on later vmentries, but checking
11853 * on every vmentry is costly so we just use an hrtimer.
11855 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11858 vmx->hv_deadline_tsc = tscl + delta_tsc;
11859 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11860 PIN_BASED_VMX_PREEMPTION_TIMER);
11862 return delta_tsc == 0;
11865 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11867 struct vcpu_vmx *vmx = to_vmx(vcpu);
11868 vmx->hv_deadline_tsc = -1;
11869 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11870 PIN_BASED_VMX_PREEMPTION_TIMER);
11874 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11877 shrink_ple_window(vcpu);
11880 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11881 struct kvm_memory_slot *slot)
11883 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11884 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11887 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11888 struct kvm_memory_slot *slot)
11890 kvm_mmu_slot_set_dirty(kvm, slot);
11893 static void vmx_flush_log_dirty(struct kvm *kvm)
11895 kvm_flush_pml_buffers(kvm);
11898 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11900 struct vmcs12 *vmcs12;
11901 struct vcpu_vmx *vmx = to_vmx(vcpu);
11903 struct page *page = NULL;
11906 if (is_guest_mode(vcpu)) {
11907 WARN_ON_ONCE(vmx->nested.pml_full);
11910 * Check if PML is enabled for the nested guest.
11911 * Whether eptp bit 6 is set is already checked
11912 * as part of A/D emulation.
11914 vmcs12 = get_vmcs12(vcpu);
11915 if (!nested_cpu_has_pml(vmcs12))
11918 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11919 vmx->nested.pml_full = true;
11923 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11925 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
11926 if (is_error_page(page))
11929 pml_address = kmap(page);
11930 pml_address[vmcs12->guest_pml_index--] = gpa;
11932 kvm_release_page_clean(page);
11938 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11939 struct kvm_memory_slot *memslot,
11940 gfn_t offset, unsigned long mask)
11942 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11945 static void __pi_post_block(struct kvm_vcpu *vcpu)
11947 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11948 struct pi_desc old, new;
11952 old.control = new.control = pi_desc->control;
11953 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
11954 "Wakeup handler not enabled while the VCPU is blocked\n");
11956 dest = cpu_physical_id(vcpu->cpu);
11958 if (x2apic_enabled())
11961 new.ndst = (dest << 8) & 0xFF00;
11963 /* set 'NV' to 'notification vector' */
11964 new.nv = POSTED_INTR_VECTOR;
11965 } while (cmpxchg64(&pi_desc->control, old.control,
11966 new.control) != old.control);
11968 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
11969 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11970 list_del(&vcpu->blocked_vcpu_list);
11971 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11972 vcpu->pre_pcpu = -1;
11977 * This routine does the following things for vCPU which is going
11978 * to be blocked if VT-d PI is enabled.
11979 * - Store the vCPU to the wakeup list, so when interrupts happen
11980 * we can find the right vCPU to wake up.
11981 * - Change the Posted-interrupt descriptor as below:
11982 * 'NDST' <-- vcpu->pre_pcpu
11983 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11984 * - If 'ON' is set during this process, which means at least one
11985 * interrupt is posted for this vCPU, we cannot block it, in
11986 * this case, return 1, otherwise, return 0.
11989 static int pi_pre_block(struct kvm_vcpu *vcpu)
11992 struct pi_desc old, new;
11993 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11995 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11996 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11997 !kvm_vcpu_apicv_active(vcpu))
12000 WARN_ON(irqs_disabled());
12001 local_irq_disable();
12002 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
12003 vcpu->pre_pcpu = vcpu->cpu;
12004 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12005 list_add_tail(&vcpu->blocked_vcpu_list,
12006 &per_cpu(blocked_vcpu_on_cpu,
12008 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
12012 old.control = new.control = pi_desc->control;
12014 WARN((pi_desc->sn == 1),
12015 "Warning: SN field of posted-interrupts "
12016 "is set before blocking\n");
12019 * Since vCPU can be preempted during this process,
12020 * vcpu->cpu could be different with pre_pcpu, we
12021 * need to set pre_pcpu as the destination of wakeup
12022 * notification event, then we can find the right vCPU
12023 * to wakeup in wakeup handler if interrupts happen
12024 * when the vCPU is in blocked state.
12026 dest = cpu_physical_id(vcpu->pre_pcpu);
12028 if (x2apic_enabled())
12031 new.ndst = (dest << 8) & 0xFF00;
12033 /* set 'NV' to 'wakeup vector' */
12034 new.nv = POSTED_INTR_WAKEUP_VECTOR;
12035 } while (cmpxchg64(&pi_desc->control, old.control,
12036 new.control) != old.control);
12038 /* We should not block the vCPU if an interrupt is posted for it. */
12039 if (pi_test_on(pi_desc) == 1)
12040 __pi_post_block(vcpu);
12042 local_irq_enable();
12043 return (vcpu->pre_pcpu == -1);
12046 static int vmx_pre_block(struct kvm_vcpu *vcpu)
12048 if (pi_pre_block(vcpu))
12051 if (kvm_lapic_hv_timer_in_use(vcpu))
12052 kvm_lapic_switch_to_sw_timer(vcpu);
12057 static void pi_post_block(struct kvm_vcpu *vcpu)
12059 if (vcpu->pre_pcpu == -1)
12062 WARN_ON(irqs_disabled());
12063 local_irq_disable();
12064 __pi_post_block(vcpu);
12065 local_irq_enable();
12068 static void vmx_post_block(struct kvm_vcpu *vcpu)
12070 if (kvm_x86_ops->set_hv_timer)
12071 kvm_lapic_switch_to_hv_timer(vcpu);
12073 pi_post_block(vcpu);
12077 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
12080 * @host_irq: host irq of the interrupt
12081 * @guest_irq: gsi of the interrupt
12082 * @set: set or unset PI
12083 * returns 0 on success, < 0 on failure
12085 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
12086 uint32_t guest_irq, bool set)
12088 struct kvm_kernel_irq_routing_entry *e;
12089 struct kvm_irq_routing_table *irq_rt;
12090 struct kvm_lapic_irq irq;
12091 struct kvm_vcpu *vcpu;
12092 struct vcpu_data vcpu_info;
12095 if (!kvm_arch_has_assigned_device(kvm) ||
12096 !irq_remapping_cap(IRQ_POSTING_CAP) ||
12097 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
12100 idx = srcu_read_lock(&kvm->irq_srcu);
12101 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
12102 if (guest_irq >= irq_rt->nr_rt_entries ||
12103 hlist_empty(&irq_rt->map[guest_irq])) {
12104 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
12105 guest_irq, irq_rt->nr_rt_entries);
12109 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
12110 if (e->type != KVM_IRQ_ROUTING_MSI)
12113 * VT-d PI cannot support posting multicast/broadcast
12114 * interrupts to a vCPU, we still use interrupt remapping
12115 * for these kind of interrupts.
12117 * For lowest-priority interrupts, we only support
12118 * those with single CPU as the destination, e.g. user
12119 * configures the interrupts via /proc/irq or uses
12120 * irqbalance to make the interrupts single-CPU.
12122 * We will support full lowest-priority interrupt later.
12125 kvm_set_msi_irq(kvm, e, &irq);
12126 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
12128 * Make sure the IRTE is in remapped mode if
12129 * we don't handle it in posted mode.
12131 ret = irq_set_vcpu_affinity(host_irq, NULL);
12134 "failed to back to remapped mode, irq: %u\n",
12142 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
12143 vcpu_info.vector = irq.vector;
12145 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
12146 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
12149 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
12151 ret = irq_set_vcpu_affinity(host_irq, NULL);
12154 printk(KERN_INFO "%s: failed to update PI IRTE\n",
12162 srcu_read_unlock(&kvm->irq_srcu, idx);
12166 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
12168 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
12169 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
12170 FEATURE_CONTROL_LMCE;
12172 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
12173 ~FEATURE_CONTROL_LMCE;
12176 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
12177 .cpu_has_kvm_support = cpu_has_kvm_support,
12178 .disabled_by_bios = vmx_disabled_by_bios,
12179 .hardware_setup = hardware_setup,
12180 .hardware_unsetup = hardware_unsetup,
12181 .check_processor_compatibility = vmx_check_processor_compat,
12182 .hardware_enable = hardware_enable,
12183 .hardware_disable = hardware_disable,
12184 .cpu_has_accelerated_tpr = report_flexpriority,
12185 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
12187 .vcpu_create = vmx_create_vcpu,
12188 .vcpu_free = vmx_free_vcpu,
12189 .vcpu_reset = vmx_vcpu_reset,
12191 .prepare_guest_switch = vmx_save_host_state,
12192 .vcpu_load = vmx_vcpu_load,
12193 .vcpu_put = vmx_vcpu_put,
12195 .update_bp_intercept = update_exception_bitmap,
12196 .get_msr = vmx_get_msr,
12197 .set_msr = vmx_set_msr,
12198 .get_segment_base = vmx_get_segment_base,
12199 .get_segment = vmx_get_segment,
12200 .set_segment = vmx_set_segment,
12201 .get_cpl = vmx_get_cpl,
12202 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
12203 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
12204 .decache_cr3 = vmx_decache_cr3,
12205 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
12206 .set_cr0 = vmx_set_cr0,
12207 .set_cr3 = vmx_set_cr3,
12208 .set_cr4 = vmx_set_cr4,
12209 .set_efer = vmx_set_efer,
12210 .get_idt = vmx_get_idt,
12211 .set_idt = vmx_set_idt,
12212 .get_gdt = vmx_get_gdt,
12213 .set_gdt = vmx_set_gdt,
12214 .get_dr6 = vmx_get_dr6,
12215 .set_dr6 = vmx_set_dr6,
12216 .set_dr7 = vmx_set_dr7,
12217 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
12218 .cache_reg = vmx_cache_reg,
12219 .get_rflags = vmx_get_rflags,
12220 .set_rflags = vmx_set_rflags,
12222 .tlb_flush = vmx_flush_tlb,
12224 .run = vmx_vcpu_run,
12225 .handle_exit = vmx_handle_exit,
12226 .skip_emulated_instruction = skip_emulated_instruction,
12227 .set_interrupt_shadow = vmx_set_interrupt_shadow,
12228 .get_interrupt_shadow = vmx_get_interrupt_shadow,
12229 .patch_hypercall = vmx_patch_hypercall,
12230 .set_irq = vmx_inject_irq,
12231 .set_nmi = vmx_inject_nmi,
12232 .queue_exception = vmx_queue_exception,
12233 .cancel_injection = vmx_cancel_injection,
12234 .interrupt_allowed = vmx_interrupt_allowed,
12235 .nmi_allowed = vmx_nmi_allowed,
12236 .get_nmi_mask = vmx_get_nmi_mask,
12237 .set_nmi_mask = vmx_set_nmi_mask,
12238 .enable_nmi_window = enable_nmi_window,
12239 .enable_irq_window = enable_irq_window,
12240 .update_cr8_intercept = update_cr8_intercept,
12241 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
12242 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
12243 .get_enable_apicv = vmx_get_enable_apicv,
12244 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
12245 .load_eoi_exitmap = vmx_load_eoi_exitmap,
12246 .apicv_post_state_restore = vmx_apicv_post_state_restore,
12247 .hwapic_irr_update = vmx_hwapic_irr_update,
12248 .hwapic_isr_update = vmx_hwapic_isr_update,
12249 .sync_pir_to_irr = vmx_sync_pir_to_irr,
12250 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
12252 .set_tss_addr = vmx_set_tss_addr,
12253 .get_tdp_level = get_ept_level,
12254 .get_mt_mask = vmx_get_mt_mask,
12256 .get_exit_info = vmx_get_exit_info,
12258 .get_lpage_level = vmx_get_lpage_level,
12260 .cpuid_update = vmx_cpuid_update,
12262 .rdtscp_supported = vmx_rdtscp_supported,
12263 .invpcid_supported = vmx_invpcid_supported,
12265 .set_supported_cpuid = vmx_set_supported_cpuid,
12267 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
12269 .write_tsc_offset = vmx_write_tsc_offset,
12271 .set_tdp_cr3 = vmx_set_cr3,
12273 .check_intercept = vmx_check_intercept,
12274 .handle_external_intr = vmx_handle_external_intr,
12275 .mpx_supported = vmx_mpx_supported,
12276 .xsaves_supported = vmx_xsaves_supported,
12278 .check_nested_events = vmx_check_nested_events,
12280 .sched_in = vmx_sched_in,
12282 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
12283 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
12284 .flush_log_dirty = vmx_flush_log_dirty,
12285 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
12286 .write_log_dirty = vmx_write_pml_buffer,
12288 .pre_block = vmx_pre_block,
12289 .post_block = vmx_post_block,
12291 .pmu_ops = &intel_pmu_ops,
12293 .update_pi_irte = vmx_update_pi_irte,
12295 #ifdef CONFIG_X86_64
12296 .set_hv_timer = vmx_set_hv_timer,
12297 .cancel_hv_timer = vmx_cancel_hv_timer,
12300 .setup_mce = vmx_setup_mce,
12303 static int __init vmx_init(void)
12305 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
12306 __alignof__(struct vcpu_vmx), THIS_MODULE);
12310 #ifdef CONFIG_KEXEC_CORE
12311 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
12312 crash_vmclear_local_loaded_vmcss);
12318 static void __exit vmx_exit(void)
12320 #ifdef CONFIG_KEXEC_CORE
12321 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
12328 module_init(vmx_init)
12329 module_exit(vmx_exit)