2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/ftrace_event.h>
31 #include <linux/slab.h>
32 #include <linux/tboot.h>
33 #include "kvm_cache_regs.h"
39 #include <asm/virtext.h>
43 #include <asm/perf_event.h>
47 #define __ex(x) __kvm_handle_fault_on_reboot(x)
48 #define __ex_clear(x, reg) \
49 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
51 MODULE_AUTHOR("Qumranet");
52 MODULE_LICENSE("GPL");
54 static bool __read_mostly enable_vpid = 1;
55 module_param_named(vpid, enable_vpid, bool, 0444);
57 static bool __read_mostly flexpriority_enabled = 1;
58 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
60 static bool __read_mostly enable_ept = 1;
61 module_param_named(ept, enable_ept, bool, S_IRUGO);
63 static bool __read_mostly enable_unrestricted_guest = 1;
64 module_param_named(unrestricted_guest,
65 enable_unrestricted_guest, bool, S_IRUGO);
67 static bool __read_mostly emulate_invalid_guest_state = 0;
68 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
70 static bool __read_mostly vmm_exclusive = 1;
71 module_param(vmm_exclusive, bool, S_IRUGO);
73 static bool __read_mostly fasteoi = 1;
74 module_param(fasteoi, bool, S_IRUGO);
77 * If nested=1, nested virtualization is supported, i.e., guests may use
78 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
79 * use VMX instructions.
81 static bool __read_mostly nested = 0;
82 module_param(nested, bool, S_IRUGO);
84 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
85 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
86 #define KVM_GUEST_CR0_MASK \
87 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
88 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
89 (X86_CR0_WP | X86_CR0_NE)
90 #define KVM_VM_CR0_ALWAYS_ON \
91 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
92 #define KVM_CR4_GUEST_OWNED_BITS \
93 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
96 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
97 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
99 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
102 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
103 * ple_gap: upper bound on the amount of time between two successive
104 * executions of PAUSE in a loop. Also indicate if ple enabled.
105 * According to test, this time is usually smaller than 128 cycles.
106 * ple_window: upper bound on the amount of time a guest is allowed to execute
107 * in a PAUSE loop. Tests indicate that most spinlocks are held for
108 * less than 2^12 cycles
109 * Time is measured based on a counter that runs at the same rate as the TSC,
110 * refer SDM volume 3b section 21.6.13 & 22.1.3.
112 #define KVM_VMX_DEFAULT_PLE_GAP 128
113 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
114 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
115 module_param(ple_gap, int, S_IRUGO);
117 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
118 module_param(ple_window, int, S_IRUGO);
120 #define NR_AUTOLOAD_MSRS 8
121 #define VMCS02_POOL_SIZE 1
130 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
131 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
132 * loaded on this CPU (so we can clear them if the CPU goes down).
138 struct list_head loaded_vmcss_on_cpu_link;
141 struct shared_msr_entry {
148 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
149 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
150 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
151 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
152 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
153 * More than one of these structures may exist, if L1 runs multiple L2 guests.
154 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
155 * underlying hardware which will be used to run L2.
156 * This structure is packed to ensure that its layout is identical across
157 * machines (necessary for live migration).
158 * If there are changes in this struct, VMCS12_REVISION must be changed.
160 typedef u64 natural_width;
161 struct __packed vmcs12 {
162 /* According to the Intel spec, a VMCS region must start with the
163 * following two fields. Then follow implementation-specific data.
168 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
169 u32 padding[7]; /* room for future expansion */
174 u64 vm_exit_msr_store_addr;
175 u64 vm_exit_msr_load_addr;
176 u64 vm_entry_msr_load_addr;
178 u64 virtual_apic_page_addr;
179 u64 apic_access_addr;
181 u64 guest_physical_address;
182 u64 vmcs_link_pointer;
183 u64 guest_ia32_debugctl;
186 u64 guest_ia32_perf_global_ctrl;
193 u64 host_ia32_perf_global_ctrl;
194 u64 padding64[8]; /* room for future expansion */
196 * To allow migration of L1 (complete with its L2 guests) between
197 * machines of different natural widths (32 or 64 bit), we cannot have
198 * unsigned long fields with no explict size. We use u64 (aliased
199 * natural_width) instead. Luckily, x86 is little-endian.
201 natural_width cr0_guest_host_mask;
202 natural_width cr4_guest_host_mask;
203 natural_width cr0_read_shadow;
204 natural_width cr4_read_shadow;
205 natural_width cr3_target_value0;
206 natural_width cr3_target_value1;
207 natural_width cr3_target_value2;
208 natural_width cr3_target_value3;
209 natural_width exit_qualification;
210 natural_width guest_linear_address;
211 natural_width guest_cr0;
212 natural_width guest_cr3;
213 natural_width guest_cr4;
214 natural_width guest_es_base;
215 natural_width guest_cs_base;
216 natural_width guest_ss_base;
217 natural_width guest_ds_base;
218 natural_width guest_fs_base;
219 natural_width guest_gs_base;
220 natural_width guest_ldtr_base;
221 natural_width guest_tr_base;
222 natural_width guest_gdtr_base;
223 natural_width guest_idtr_base;
224 natural_width guest_dr7;
225 natural_width guest_rsp;
226 natural_width guest_rip;
227 natural_width guest_rflags;
228 natural_width guest_pending_dbg_exceptions;
229 natural_width guest_sysenter_esp;
230 natural_width guest_sysenter_eip;
231 natural_width host_cr0;
232 natural_width host_cr3;
233 natural_width host_cr4;
234 natural_width host_fs_base;
235 natural_width host_gs_base;
236 natural_width host_tr_base;
237 natural_width host_gdtr_base;
238 natural_width host_idtr_base;
239 natural_width host_ia32_sysenter_esp;
240 natural_width host_ia32_sysenter_eip;
241 natural_width host_rsp;
242 natural_width host_rip;
243 natural_width paddingl[8]; /* room for future expansion */
244 u32 pin_based_vm_exec_control;
245 u32 cpu_based_vm_exec_control;
246 u32 exception_bitmap;
247 u32 page_fault_error_code_mask;
248 u32 page_fault_error_code_match;
249 u32 cr3_target_count;
250 u32 vm_exit_controls;
251 u32 vm_exit_msr_store_count;
252 u32 vm_exit_msr_load_count;
253 u32 vm_entry_controls;
254 u32 vm_entry_msr_load_count;
255 u32 vm_entry_intr_info_field;
256 u32 vm_entry_exception_error_code;
257 u32 vm_entry_instruction_len;
259 u32 secondary_vm_exec_control;
260 u32 vm_instruction_error;
262 u32 vm_exit_intr_info;
263 u32 vm_exit_intr_error_code;
264 u32 idt_vectoring_info_field;
265 u32 idt_vectoring_error_code;
266 u32 vm_exit_instruction_len;
267 u32 vmx_instruction_info;
274 u32 guest_ldtr_limit;
276 u32 guest_gdtr_limit;
277 u32 guest_idtr_limit;
278 u32 guest_es_ar_bytes;
279 u32 guest_cs_ar_bytes;
280 u32 guest_ss_ar_bytes;
281 u32 guest_ds_ar_bytes;
282 u32 guest_fs_ar_bytes;
283 u32 guest_gs_ar_bytes;
284 u32 guest_ldtr_ar_bytes;
285 u32 guest_tr_ar_bytes;
286 u32 guest_interruptibility_info;
287 u32 guest_activity_state;
288 u32 guest_sysenter_cs;
289 u32 host_ia32_sysenter_cs;
290 u32 padding32[8]; /* room for future expansion */
291 u16 virtual_processor_id;
292 u16 guest_es_selector;
293 u16 guest_cs_selector;
294 u16 guest_ss_selector;
295 u16 guest_ds_selector;
296 u16 guest_fs_selector;
297 u16 guest_gs_selector;
298 u16 guest_ldtr_selector;
299 u16 guest_tr_selector;
300 u16 host_es_selector;
301 u16 host_cs_selector;
302 u16 host_ss_selector;
303 u16 host_ds_selector;
304 u16 host_fs_selector;
305 u16 host_gs_selector;
306 u16 host_tr_selector;
310 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
311 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
312 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
314 #define VMCS12_REVISION 0x11e57ed0
317 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
318 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
319 * current implementation, 4K are reserved to avoid future complications.
321 #define VMCS12_SIZE 0x1000
323 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
325 struct list_head list;
327 struct loaded_vmcs vmcs02;
331 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
332 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
335 /* Has the level1 guest done vmxon? */
338 /* The guest-physical address of the current VMCS L1 keeps for L2 */
340 /* The host-usable pointer to the above */
341 struct page *current_vmcs12_page;
342 struct vmcs12 *current_vmcs12;
344 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
345 struct list_head vmcs02_pool;
347 u64 vmcs01_tsc_offset;
348 /* L2 must run next, and mustn't decide to exit to L1. */
349 bool nested_run_pending;
351 * Guest pages referred to in vmcs02 with host-physical pointers, so
352 * we must keep them pinned while L2 runs.
354 struct page *apic_access_page;
358 struct kvm_vcpu vcpu;
359 unsigned long host_rsp;
362 bool nmi_known_unmasked;
364 u32 idt_vectoring_info;
366 struct shared_msr_entry *guest_msrs;
370 u64 msr_host_kernel_gs_base;
371 u64 msr_guest_kernel_gs_base;
374 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
375 * non-nested (L1) guest, it always points to vmcs01. For a nested
376 * guest (L2), it points to a different VMCS.
378 struct loaded_vmcs vmcs01;
379 struct loaded_vmcs *loaded_vmcs;
380 bool __launched; /* temporary, used in vmx_vcpu_run */
381 struct msr_autoload {
383 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
384 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
388 u16 fs_sel, gs_sel, ldt_sel;
389 int gs_ldt_reload_needed;
390 int fs_reload_needed;
395 struct kvm_save_segment {
400 } tr, es, ds, fs, gs;
403 u32 bitmask; /* 4 bits per segment (1 bit per field) */
404 struct kvm_save_segment seg[8];
407 bool emulation_required;
409 /* Support for vnmi-less CPUs */
410 int soft_vnmi_blocked;
412 s64 vnmi_blocked_time;
417 /* Support for a guest hypervisor (nested VMX) */
418 struct nested_vmx nested;
421 enum segment_cache_field {
430 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
432 return container_of(vcpu, struct vcpu_vmx, vcpu);
435 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
436 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
437 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
438 [number##_HIGH] = VMCS12_OFFSET(name)+4
440 static unsigned short vmcs_field_to_offset_table[] = {
441 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
442 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
443 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
444 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
445 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
446 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
447 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
448 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
449 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
450 FIELD(HOST_ES_SELECTOR, host_es_selector),
451 FIELD(HOST_CS_SELECTOR, host_cs_selector),
452 FIELD(HOST_SS_SELECTOR, host_ss_selector),
453 FIELD(HOST_DS_SELECTOR, host_ds_selector),
454 FIELD(HOST_FS_SELECTOR, host_fs_selector),
455 FIELD(HOST_GS_SELECTOR, host_gs_selector),
456 FIELD(HOST_TR_SELECTOR, host_tr_selector),
457 FIELD64(IO_BITMAP_A, io_bitmap_a),
458 FIELD64(IO_BITMAP_B, io_bitmap_b),
459 FIELD64(MSR_BITMAP, msr_bitmap),
460 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
461 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
462 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
463 FIELD64(TSC_OFFSET, tsc_offset),
464 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
465 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
466 FIELD64(EPT_POINTER, ept_pointer),
467 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
468 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
469 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
470 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
471 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
472 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
473 FIELD64(GUEST_PDPTR0, guest_pdptr0),
474 FIELD64(GUEST_PDPTR1, guest_pdptr1),
475 FIELD64(GUEST_PDPTR2, guest_pdptr2),
476 FIELD64(GUEST_PDPTR3, guest_pdptr3),
477 FIELD64(HOST_IA32_PAT, host_ia32_pat),
478 FIELD64(HOST_IA32_EFER, host_ia32_efer),
479 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
480 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
481 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
482 FIELD(EXCEPTION_BITMAP, exception_bitmap),
483 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
484 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
485 FIELD(CR3_TARGET_COUNT, cr3_target_count),
486 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
487 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
488 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
489 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
490 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
491 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
492 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
493 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
494 FIELD(TPR_THRESHOLD, tpr_threshold),
495 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
496 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
497 FIELD(VM_EXIT_REASON, vm_exit_reason),
498 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
499 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
500 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
501 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
502 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
503 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
504 FIELD(GUEST_ES_LIMIT, guest_es_limit),
505 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
506 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
507 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
508 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
509 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
510 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
511 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
512 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
513 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
514 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
515 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
516 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
517 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
518 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
519 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
520 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
521 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
522 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
523 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
524 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
525 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
526 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
527 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
528 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
529 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
530 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
531 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
532 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
533 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
534 FIELD(EXIT_QUALIFICATION, exit_qualification),
535 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
536 FIELD(GUEST_CR0, guest_cr0),
537 FIELD(GUEST_CR3, guest_cr3),
538 FIELD(GUEST_CR4, guest_cr4),
539 FIELD(GUEST_ES_BASE, guest_es_base),
540 FIELD(GUEST_CS_BASE, guest_cs_base),
541 FIELD(GUEST_SS_BASE, guest_ss_base),
542 FIELD(GUEST_DS_BASE, guest_ds_base),
543 FIELD(GUEST_FS_BASE, guest_fs_base),
544 FIELD(GUEST_GS_BASE, guest_gs_base),
545 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
546 FIELD(GUEST_TR_BASE, guest_tr_base),
547 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
548 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
549 FIELD(GUEST_DR7, guest_dr7),
550 FIELD(GUEST_RSP, guest_rsp),
551 FIELD(GUEST_RIP, guest_rip),
552 FIELD(GUEST_RFLAGS, guest_rflags),
553 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
554 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
555 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
556 FIELD(HOST_CR0, host_cr0),
557 FIELD(HOST_CR3, host_cr3),
558 FIELD(HOST_CR4, host_cr4),
559 FIELD(HOST_FS_BASE, host_fs_base),
560 FIELD(HOST_GS_BASE, host_gs_base),
561 FIELD(HOST_TR_BASE, host_tr_base),
562 FIELD(HOST_GDTR_BASE, host_gdtr_base),
563 FIELD(HOST_IDTR_BASE, host_idtr_base),
564 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
565 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
566 FIELD(HOST_RSP, host_rsp),
567 FIELD(HOST_RIP, host_rip),
569 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
571 static inline short vmcs_field_to_offset(unsigned long field)
573 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
575 return vmcs_field_to_offset_table[field];
578 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
580 return to_vmx(vcpu)->nested.current_vmcs12;
583 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
585 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
586 if (is_error_page(page)) {
587 kvm_release_page_clean(page);
593 static void nested_release_page(struct page *page)
595 kvm_release_page_dirty(page);
598 static void nested_release_page_clean(struct page *page)
600 kvm_release_page_clean(page);
603 static u64 construct_eptp(unsigned long root_hpa);
604 static void kvm_cpu_vmxon(u64 addr);
605 static void kvm_cpu_vmxoff(void);
606 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
607 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
609 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
610 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
612 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
613 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
615 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
616 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
618 static unsigned long *vmx_io_bitmap_a;
619 static unsigned long *vmx_io_bitmap_b;
620 static unsigned long *vmx_msr_bitmap_legacy;
621 static unsigned long *vmx_msr_bitmap_longmode;
623 static bool cpu_has_load_ia32_efer;
624 static bool cpu_has_load_perf_global_ctrl;
626 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
627 static DEFINE_SPINLOCK(vmx_vpid_lock);
629 static struct vmcs_config {
633 u32 pin_based_exec_ctrl;
634 u32 cpu_based_exec_ctrl;
635 u32 cpu_based_2nd_exec_ctrl;
640 static struct vmx_capability {
645 #define VMX_SEGMENT_FIELD(seg) \
646 [VCPU_SREG_##seg] = { \
647 .selector = GUEST_##seg##_SELECTOR, \
648 .base = GUEST_##seg##_BASE, \
649 .limit = GUEST_##seg##_LIMIT, \
650 .ar_bytes = GUEST_##seg##_AR_BYTES, \
653 static struct kvm_vmx_segment_field {
658 } kvm_vmx_segment_fields[] = {
659 VMX_SEGMENT_FIELD(CS),
660 VMX_SEGMENT_FIELD(DS),
661 VMX_SEGMENT_FIELD(ES),
662 VMX_SEGMENT_FIELD(FS),
663 VMX_SEGMENT_FIELD(GS),
664 VMX_SEGMENT_FIELD(SS),
665 VMX_SEGMENT_FIELD(TR),
666 VMX_SEGMENT_FIELD(LDTR),
669 static u64 host_efer;
671 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
674 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
675 * away by decrementing the array size.
677 static const u32 vmx_msr_index[] = {
679 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
681 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
683 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
685 static inline bool is_page_fault(u32 intr_info)
687 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
688 INTR_INFO_VALID_MASK)) ==
689 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
692 static inline bool is_no_device(u32 intr_info)
694 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
695 INTR_INFO_VALID_MASK)) ==
696 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
699 static inline bool is_invalid_opcode(u32 intr_info)
701 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
702 INTR_INFO_VALID_MASK)) ==
703 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
706 static inline bool is_external_interrupt(u32 intr_info)
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
709 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
712 static inline bool is_machine_check(u32 intr_info)
714 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
715 INTR_INFO_VALID_MASK)) ==
716 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
719 static inline bool cpu_has_vmx_msr_bitmap(void)
721 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
724 static inline bool cpu_has_vmx_tpr_shadow(void)
726 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
729 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
731 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
734 static inline bool cpu_has_secondary_exec_ctrls(void)
736 return vmcs_config.cpu_based_exec_ctrl &
737 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
740 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
742 return vmcs_config.cpu_based_2nd_exec_ctrl &
743 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
746 static inline bool cpu_has_vmx_flexpriority(void)
748 return cpu_has_vmx_tpr_shadow() &&
749 cpu_has_vmx_virtualize_apic_accesses();
752 static inline bool cpu_has_vmx_ept_execute_only(void)
754 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
757 static inline bool cpu_has_vmx_eptp_uncacheable(void)
759 return vmx_capability.ept & VMX_EPTP_UC_BIT;
762 static inline bool cpu_has_vmx_eptp_writeback(void)
764 return vmx_capability.ept & VMX_EPTP_WB_BIT;
767 static inline bool cpu_has_vmx_ept_2m_page(void)
769 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
772 static inline bool cpu_has_vmx_ept_1g_page(void)
774 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
777 static inline bool cpu_has_vmx_ept_4levels(void)
779 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
782 static inline bool cpu_has_vmx_invept_individual_addr(void)
784 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
787 static inline bool cpu_has_vmx_invept_context(void)
789 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
792 static inline bool cpu_has_vmx_invept_global(void)
794 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
797 static inline bool cpu_has_vmx_invvpid_single(void)
799 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
802 static inline bool cpu_has_vmx_invvpid_global(void)
804 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
807 static inline bool cpu_has_vmx_ept(void)
809 return vmcs_config.cpu_based_2nd_exec_ctrl &
810 SECONDARY_EXEC_ENABLE_EPT;
813 static inline bool cpu_has_vmx_unrestricted_guest(void)
815 return vmcs_config.cpu_based_2nd_exec_ctrl &
816 SECONDARY_EXEC_UNRESTRICTED_GUEST;
819 static inline bool cpu_has_vmx_ple(void)
821 return vmcs_config.cpu_based_2nd_exec_ctrl &
822 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
825 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
827 return flexpriority_enabled && irqchip_in_kernel(kvm);
830 static inline bool cpu_has_vmx_vpid(void)
832 return vmcs_config.cpu_based_2nd_exec_ctrl &
833 SECONDARY_EXEC_ENABLE_VPID;
836 static inline bool cpu_has_vmx_rdtscp(void)
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_RDTSCP;
842 static inline bool cpu_has_virtual_nmis(void)
844 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
847 static inline bool cpu_has_vmx_wbinvd_exit(void)
849 return vmcs_config.cpu_based_2nd_exec_ctrl &
850 SECONDARY_EXEC_WBINVD_EXITING;
853 static inline bool report_flexpriority(void)
855 return flexpriority_enabled;
858 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
860 return vmcs12->cpu_based_vm_exec_control & bit;
863 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
865 return (vmcs12->cpu_based_vm_exec_control &
866 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
867 (vmcs12->secondary_vm_exec_control & bit);
870 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
871 struct kvm_vcpu *vcpu)
873 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
876 static inline bool is_exception(u32 intr_info)
878 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
879 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
882 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
883 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
884 struct vmcs12 *vmcs12,
885 u32 reason, unsigned long qualification);
887 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
891 for (i = 0; i < vmx->nmsrs; ++i)
892 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
897 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
903 } operand = { vpid, 0, gva };
905 asm volatile (__ex(ASM_VMX_INVVPID)
906 /* CF==1 or ZF==1 --> rc = -1 */
908 : : "a"(&operand), "c"(ext) : "cc", "memory");
911 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
915 } operand = {eptp, gpa};
917 asm volatile (__ex(ASM_VMX_INVEPT)
918 /* CF==1 or ZF==1 --> rc = -1 */
919 "; ja 1f ; ud2 ; 1:\n"
920 : : "a" (&operand), "c" (ext) : "cc", "memory");
923 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
927 i = __find_msr_index(vmx, msr);
929 return &vmx->guest_msrs[i];
933 static void vmcs_clear(struct vmcs *vmcs)
935 u64 phys_addr = __pa(vmcs);
938 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
939 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
942 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
946 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
948 vmcs_clear(loaded_vmcs->vmcs);
949 loaded_vmcs->cpu = -1;
950 loaded_vmcs->launched = 0;
953 static void vmcs_load(struct vmcs *vmcs)
955 u64 phys_addr = __pa(vmcs);
958 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
959 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
962 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
966 static void __loaded_vmcs_clear(void *arg)
968 struct loaded_vmcs *loaded_vmcs = arg;
969 int cpu = raw_smp_processor_id();
971 if (loaded_vmcs->cpu != cpu)
972 return; /* vcpu migration can race with cpu offline */
973 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
974 per_cpu(current_vmcs, cpu) = NULL;
975 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
976 loaded_vmcs_init(loaded_vmcs);
979 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
981 if (loaded_vmcs->cpu != -1)
982 smp_call_function_single(
983 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
986 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
991 if (cpu_has_vmx_invvpid_single())
992 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
995 static inline void vpid_sync_vcpu_global(void)
997 if (cpu_has_vmx_invvpid_global())
998 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1001 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1003 if (cpu_has_vmx_invvpid_single())
1004 vpid_sync_vcpu_single(vmx);
1006 vpid_sync_vcpu_global();
1009 static inline void ept_sync_global(void)
1011 if (cpu_has_vmx_invept_global())
1012 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1015 static inline void ept_sync_context(u64 eptp)
1018 if (cpu_has_vmx_invept_context())
1019 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1025 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1028 if (cpu_has_vmx_invept_individual_addr())
1029 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1032 ept_sync_context(eptp);
1036 static __always_inline unsigned long vmcs_readl(unsigned long field)
1038 unsigned long value;
1040 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041 : "=a"(value) : "d"(field) : "cc");
1045 static __always_inline u16 vmcs_read16(unsigned long field)
1047 return vmcs_readl(field);
1050 static __always_inline u32 vmcs_read32(unsigned long field)
1052 return vmcs_readl(field);
1055 static __always_inline u64 vmcs_read64(unsigned long field)
1057 #ifdef CONFIG_X86_64
1058 return vmcs_readl(field);
1060 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1064 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1066 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1071 static void vmcs_writel(unsigned long field, unsigned long value)
1075 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1076 : "=q"(error) : "a"(value), "d"(field) : "cc");
1077 if (unlikely(error))
1078 vmwrite_error(field, value);
1081 static void vmcs_write16(unsigned long field, u16 value)
1083 vmcs_writel(field, value);
1086 static void vmcs_write32(unsigned long field, u32 value)
1088 vmcs_writel(field, value);
1091 static void vmcs_write64(unsigned long field, u64 value)
1093 vmcs_writel(field, value);
1094 #ifndef CONFIG_X86_64
1096 vmcs_writel(field+1, value >> 32);
1100 static void vmcs_clear_bits(unsigned long field, u32 mask)
1102 vmcs_writel(field, vmcs_readl(field) & ~mask);
1105 static void vmcs_set_bits(unsigned long field, u32 mask)
1107 vmcs_writel(field, vmcs_readl(field) | mask);
1110 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1112 vmx->segment_cache.bitmask = 0;
1115 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1119 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1121 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123 vmx->segment_cache.bitmask = 0;
1125 ret = vmx->segment_cache.bitmask & mask;
1126 vmx->segment_cache.bitmask |= mask;
1130 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1132 u16 *p = &vmx->segment_cache.seg[seg].selector;
1134 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1139 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1141 ulong *p = &vmx->segment_cache.seg[seg].base;
1143 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1148 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1150 u32 *p = &vmx->segment_cache.seg[seg].limit;
1152 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1157 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1159 u32 *p = &vmx->segment_cache.seg[seg].ar;
1161 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1166 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1170 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172 if ((vcpu->guest_debug &
1173 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175 eb |= 1u << BP_VECTOR;
1176 if (to_vmx(vcpu)->rmode.vm86_active)
1179 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1180 if (vcpu->fpu_active)
1181 eb &= ~(1u << NM_VECTOR);
1183 /* When we are running a nested L2 guest and L1 specified for it a
1184 * certain exception bitmap, we must trap the same exceptions and pass
1185 * them to L1. When running L2, we will only handle the exceptions
1186 * specified above if L1 did not want them.
1188 if (is_guest_mode(vcpu))
1189 eb |= get_vmcs12(vcpu)->exception_bitmap;
1191 vmcs_write32(EXCEPTION_BITMAP, eb);
1194 static void clear_atomic_switch_msr_special(unsigned long entry,
1197 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1198 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1201 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1204 struct msr_autoload *m = &vmx->msr_autoload;
1208 if (cpu_has_load_ia32_efer) {
1209 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1210 VM_EXIT_LOAD_IA32_EFER);
1214 case MSR_CORE_PERF_GLOBAL_CTRL:
1215 if (cpu_has_load_perf_global_ctrl) {
1216 clear_atomic_switch_msr_special(
1217 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1218 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1224 for (i = 0; i < m->nr; ++i)
1225 if (m->guest[i].index == msr)
1231 m->guest[i] = m->guest[m->nr];
1232 m->host[i] = m->host[m->nr];
1233 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1234 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1237 static void add_atomic_switch_msr_special(unsigned long entry,
1238 unsigned long exit, unsigned long guest_val_vmcs,
1239 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1241 vmcs_write64(guest_val_vmcs, guest_val);
1242 vmcs_write64(host_val_vmcs, host_val);
1243 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1244 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1247 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1248 u64 guest_val, u64 host_val)
1251 struct msr_autoload *m = &vmx->msr_autoload;
1255 if (cpu_has_load_ia32_efer) {
1256 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1257 VM_EXIT_LOAD_IA32_EFER,
1260 guest_val, host_val);
1264 case MSR_CORE_PERF_GLOBAL_CTRL:
1265 if (cpu_has_load_perf_global_ctrl) {
1266 add_atomic_switch_msr_special(
1267 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1268 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1269 GUEST_IA32_PERF_GLOBAL_CTRL,
1270 HOST_IA32_PERF_GLOBAL_CTRL,
1271 guest_val, host_val);
1277 for (i = 0; i < m->nr; ++i)
1278 if (m->guest[i].index == msr)
1281 if (i == NR_AUTOLOAD_MSRS) {
1282 printk_once(KERN_WARNING"Not enough mst switch entries. "
1283 "Can't add msr %x\n", msr);
1285 } else if (i == m->nr) {
1287 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1288 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1291 m->guest[i].index = msr;
1292 m->guest[i].value = guest_val;
1293 m->host[i].index = msr;
1294 m->host[i].value = host_val;
1297 static void reload_tss(void)
1300 * VT restores TR but not its size. Useless.
1302 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1303 struct desc_struct *descs;
1305 descs = (void *)gdt->address;
1306 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1310 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1315 guest_efer = vmx->vcpu.arch.efer;
1318 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1321 ignore_bits = EFER_NX | EFER_SCE;
1322 #ifdef CONFIG_X86_64
1323 ignore_bits |= EFER_LMA | EFER_LME;
1324 /* SCE is meaningful only in long mode on Intel */
1325 if (guest_efer & EFER_LMA)
1326 ignore_bits &= ~(u64)EFER_SCE;
1328 guest_efer &= ~ignore_bits;
1329 guest_efer |= host_efer & ignore_bits;
1330 vmx->guest_msrs[efer_offset].data = guest_efer;
1331 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1333 clear_atomic_switch_msr(vmx, MSR_EFER);
1334 /* On ept, can't emulate nx, and must switch nx atomically */
1335 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1336 guest_efer = vmx->vcpu.arch.efer;
1337 if (!(guest_efer & EFER_LMA))
1338 guest_efer &= ~EFER_LME;
1339 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1346 static unsigned long segment_base(u16 selector)
1348 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1349 struct desc_struct *d;
1350 unsigned long table_base;
1353 if (!(selector & ~3))
1356 table_base = gdt->address;
1358 if (selector & 4) { /* from ldt */
1359 u16 ldt_selector = kvm_read_ldt();
1361 if (!(ldt_selector & ~3))
1364 table_base = segment_base(ldt_selector);
1366 d = (struct desc_struct *)(table_base + (selector & ~7));
1367 v = get_desc_base(d);
1368 #ifdef CONFIG_X86_64
1369 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1370 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1375 static inline unsigned long kvm_read_tr_base(void)
1378 asm("str %0" : "=g"(tr));
1379 return segment_base(tr);
1382 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1384 struct vcpu_vmx *vmx = to_vmx(vcpu);
1387 if (vmx->host_state.loaded)
1390 vmx->host_state.loaded = 1;
1392 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1393 * allow segment selectors with cpl > 0 or ti == 1.
1395 vmx->host_state.ldt_sel = kvm_read_ldt();
1396 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1397 savesegment(fs, vmx->host_state.fs_sel);
1398 if (!(vmx->host_state.fs_sel & 7)) {
1399 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1400 vmx->host_state.fs_reload_needed = 0;
1402 vmcs_write16(HOST_FS_SELECTOR, 0);
1403 vmx->host_state.fs_reload_needed = 1;
1405 savesegment(gs, vmx->host_state.gs_sel);
1406 if (!(vmx->host_state.gs_sel & 7))
1407 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1409 vmcs_write16(HOST_GS_SELECTOR, 0);
1410 vmx->host_state.gs_ldt_reload_needed = 1;
1413 #ifdef CONFIG_X86_64
1414 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1415 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1417 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1418 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1421 #ifdef CONFIG_X86_64
1422 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1423 if (is_long_mode(&vmx->vcpu))
1424 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1426 for (i = 0; i < vmx->save_nmsrs; ++i)
1427 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1428 vmx->guest_msrs[i].data,
1429 vmx->guest_msrs[i].mask);
1432 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1434 if (!vmx->host_state.loaded)
1437 ++vmx->vcpu.stat.host_state_reload;
1438 vmx->host_state.loaded = 0;
1439 #ifdef CONFIG_X86_64
1440 if (is_long_mode(&vmx->vcpu))
1441 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1443 if (vmx->host_state.gs_ldt_reload_needed) {
1444 kvm_load_ldt(vmx->host_state.ldt_sel);
1445 #ifdef CONFIG_X86_64
1446 load_gs_index(vmx->host_state.gs_sel);
1448 loadsegment(gs, vmx->host_state.gs_sel);
1451 if (vmx->host_state.fs_reload_needed)
1452 loadsegment(fs, vmx->host_state.fs_sel);
1454 #ifdef CONFIG_X86_64
1455 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1459 load_gdt(&__get_cpu_var(host_gdt));
1462 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1465 __vmx_load_host_state(vmx);
1470 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1471 * vcpu mutex is already taken.
1473 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1475 struct vcpu_vmx *vmx = to_vmx(vcpu);
1476 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1479 kvm_cpu_vmxon(phys_addr);
1480 else if (vmx->loaded_vmcs->cpu != cpu)
1481 loaded_vmcs_clear(vmx->loaded_vmcs);
1483 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1484 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1485 vmcs_load(vmx->loaded_vmcs->vmcs);
1488 if (vmx->loaded_vmcs->cpu != cpu) {
1489 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1490 unsigned long sysenter_esp;
1492 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1493 local_irq_disable();
1494 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1495 &per_cpu(loaded_vmcss_on_cpu, cpu));
1499 * Linux uses per-cpu TSS and GDT, so set these when switching
1502 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1503 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1505 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1506 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1507 vmx->loaded_vmcs->cpu = cpu;
1511 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1513 __vmx_load_host_state(to_vmx(vcpu));
1514 if (!vmm_exclusive) {
1515 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1521 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1525 if (vcpu->fpu_active)
1527 vcpu->fpu_active = 1;
1528 cr0 = vmcs_readl(GUEST_CR0);
1529 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1530 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1531 vmcs_writel(GUEST_CR0, cr0);
1532 update_exception_bitmap(vcpu);
1533 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1534 if (is_guest_mode(vcpu))
1535 vcpu->arch.cr0_guest_owned_bits &=
1536 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1537 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1540 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1543 * Return the cr0 value that a nested guest would read. This is a combination
1544 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1545 * its hypervisor (cr0_read_shadow).
1547 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1549 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1550 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1552 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1554 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1555 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1558 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1560 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1561 * set this *before* calling this function.
1563 vmx_decache_cr0_guest_bits(vcpu);
1564 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1565 update_exception_bitmap(vcpu);
1566 vcpu->arch.cr0_guest_owned_bits = 0;
1567 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1568 if (is_guest_mode(vcpu)) {
1570 * L1's specified read shadow might not contain the TS bit,
1571 * so now that we turned on shadowing of this bit, we need to
1572 * set this bit of the shadow. Like in nested_vmx_run we need
1573 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1574 * up-to-date here because we just decached cr0.TS (and we'll
1575 * only update vmcs12->guest_cr0 on nested exit).
1577 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1578 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1579 (vcpu->arch.cr0 & X86_CR0_TS);
1580 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1582 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1585 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1587 unsigned long rflags, save_rflags;
1589 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1590 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1591 rflags = vmcs_readl(GUEST_RFLAGS);
1592 if (to_vmx(vcpu)->rmode.vm86_active) {
1593 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1594 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1595 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1597 to_vmx(vcpu)->rflags = rflags;
1599 return to_vmx(vcpu)->rflags;
1602 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1604 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1605 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1606 to_vmx(vcpu)->rflags = rflags;
1607 if (to_vmx(vcpu)->rmode.vm86_active) {
1608 to_vmx(vcpu)->rmode.save_rflags = rflags;
1609 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1611 vmcs_writel(GUEST_RFLAGS, rflags);
1614 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1616 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1619 if (interruptibility & GUEST_INTR_STATE_STI)
1620 ret |= KVM_X86_SHADOW_INT_STI;
1621 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1622 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1627 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1629 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1630 u32 interruptibility = interruptibility_old;
1632 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1634 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1635 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1636 else if (mask & KVM_X86_SHADOW_INT_STI)
1637 interruptibility |= GUEST_INTR_STATE_STI;
1639 if ((interruptibility != interruptibility_old))
1640 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1643 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1647 rip = kvm_rip_read(vcpu);
1648 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1649 kvm_rip_write(vcpu, rip);
1651 /* skipping an emulated instruction also counts */
1652 vmx_set_interrupt_shadow(vcpu, 0);
1656 * KVM wants to inject page-faults which it got to the guest. This function
1657 * checks whether in a nested guest, we need to inject them to L1 or L2.
1658 * This function assumes it is called with the exit reason in vmcs02 being
1659 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1662 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1664 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1666 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1667 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1670 nested_vmx_vmexit(vcpu);
1674 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1675 bool has_error_code, u32 error_code,
1678 struct vcpu_vmx *vmx = to_vmx(vcpu);
1679 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1681 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1682 nested_pf_handled(vcpu))
1685 if (has_error_code) {
1686 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1687 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1690 if (vmx->rmode.vm86_active) {
1692 if (kvm_exception_is_soft(nr))
1693 inc_eip = vcpu->arch.event_exit_inst_len;
1694 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1695 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1699 if (kvm_exception_is_soft(nr)) {
1700 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1701 vmx->vcpu.arch.event_exit_inst_len);
1702 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1704 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1706 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1709 static bool vmx_rdtscp_supported(void)
1711 return cpu_has_vmx_rdtscp();
1715 * Swap MSR entry in host/guest MSR entry array.
1717 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1719 struct shared_msr_entry tmp;
1721 tmp = vmx->guest_msrs[to];
1722 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1723 vmx->guest_msrs[from] = tmp;
1727 * Set up the vmcs to automatically save and restore system
1728 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1729 * mode, as fiddling with msrs is very expensive.
1731 static void setup_msrs(struct vcpu_vmx *vmx)
1733 int save_nmsrs, index;
1734 unsigned long *msr_bitmap;
1737 #ifdef CONFIG_X86_64
1738 if (is_long_mode(&vmx->vcpu)) {
1739 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1741 move_msr_up(vmx, index, save_nmsrs++);
1742 index = __find_msr_index(vmx, MSR_LSTAR);
1744 move_msr_up(vmx, index, save_nmsrs++);
1745 index = __find_msr_index(vmx, MSR_CSTAR);
1747 move_msr_up(vmx, index, save_nmsrs++);
1748 index = __find_msr_index(vmx, MSR_TSC_AUX);
1749 if (index >= 0 && vmx->rdtscp_enabled)
1750 move_msr_up(vmx, index, save_nmsrs++);
1752 * MSR_STAR is only needed on long mode guests, and only
1753 * if efer.sce is enabled.
1755 index = __find_msr_index(vmx, MSR_STAR);
1756 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1757 move_msr_up(vmx, index, save_nmsrs++);
1760 index = __find_msr_index(vmx, MSR_EFER);
1761 if (index >= 0 && update_transition_efer(vmx, index))
1762 move_msr_up(vmx, index, save_nmsrs++);
1764 vmx->save_nmsrs = save_nmsrs;
1766 if (cpu_has_vmx_msr_bitmap()) {
1767 if (is_long_mode(&vmx->vcpu))
1768 msr_bitmap = vmx_msr_bitmap_longmode;
1770 msr_bitmap = vmx_msr_bitmap_legacy;
1772 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1777 * reads and returns guest's timestamp counter "register"
1778 * guest_tsc = host_tsc + tsc_offset -- 21.3
1780 static u64 guest_read_tsc(void)
1782 u64 host_tsc, tsc_offset;
1785 tsc_offset = vmcs_read64(TSC_OFFSET);
1786 return host_tsc + tsc_offset;
1790 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1791 * counter, even if a nested guest (L2) is currently running.
1793 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1795 u64 host_tsc, tsc_offset;
1798 tsc_offset = is_guest_mode(vcpu) ?
1799 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1800 vmcs_read64(TSC_OFFSET);
1801 return host_tsc + tsc_offset;
1805 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1806 * software catchup for faster rates on slower CPUs.
1808 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1813 if (user_tsc_khz > tsc_khz) {
1814 vcpu->arch.tsc_catchup = 1;
1815 vcpu->arch.tsc_always_catchup = 1;
1817 WARN(1, "user requested TSC rate below hardware speed\n");
1821 * writes 'offset' into guest's timestamp counter offset register
1823 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1825 if (is_guest_mode(vcpu)) {
1827 * We're here if L1 chose not to trap WRMSR to TSC. According
1828 * to the spec, this should set L1's TSC; The offset that L1
1829 * set for L2 remains unchanged, and still needs to be added
1830 * to the newly set TSC to get L2's TSC.
1832 struct vmcs12 *vmcs12;
1833 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1834 /* recalculate vmcs02.TSC_OFFSET: */
1835 vmcs12 = get_vmcs12(vcpu);
1836 vmcs_write64(TSC_OFFSET, offset +
1837 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1838 vmcs12->tsc_offset : 0));
1840 vmcs_write64(TSC_OFFSET, offset);
1844 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1846 u64 offset = vmcs_read64(TSC_OFFSET);
1847 vmcs_write64(TSC_OFFSET, offset + adjustment);
1848 if (is_guest_mode(vcpu)) {
1849 /* Even when running L2, the adjustment needs to apply to L1 */
1850 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1854 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1856 return target_tsc - native_read_tsc();
1859 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1861 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1862 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1866 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1867 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1868 * all guests if the "nested" module option is off, and can also be disabled
1869 * for a single guest by disabling its VMX cpuid bit.
1871 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1873 return nested && guest_cpuid_has_vmx(vcpu);
1877 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1878 * returned for the various VMX controls MSRs when nested VMX is enabled.
1879 * The same values should also be used to verify that vmcs12 control fields are
1880 * valid during nested entry from L1 to L2.
1881 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1882 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1883 * bit in the high half is on if the corresponding bit in the control field
1884 * may be on. See also vmx_control_verify().
1885 * TODO: allow these variables to be modified (downgraded) by module options
1888 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1889 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1890 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1891 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1892 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1893 static __init void nested_vmx_setup_ctls_msrs(void)
1896 * Note that as a general rule, the high half of the MSRs (bits in
1897 * the control fields which may be 1) should be initialized by the
1898 * intersection of the underlying hardware's MSR (i.e., features which
1899 * can be supported) and the list of features we want to expose -
1900 * because they are known to be properly supported in our code.
1901 * Also, usually, the low half of the MSRs (bits which must be 1) can
1902 * be set to 0, meaning that L1 may turn off any of these bits. The
1903 * reason is that if one of these bits is necessary, it will appear
1904 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1905 * fields of vmcs01 and vmcs02, will turn these bits off - and
1906 * nested_vmx_exit_handled() will not pass related exits to L1.
1907 * These rules have exceptions below.
1910 /* pin-based controls */
1912 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1913 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1915 nested_vmx_pinbased_ctls_low = 0x16 ;
1916 nested_vmx_pinbased_ctls_high = 0x16 |
1917 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1918 PIN_BASED_VIRTUAL_NMIS;
1921 nested_vmx_exit_ctls_low = 0;
1922 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1923 #ifdef CONFIG_X86_64
1924 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1926 nested_vmx_exit_ctls_high = 0;
1929 /* entry controls */
1930 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1931 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1932 nested_vmx_entry_ctls_low = 0;
1933 nested_vmx_entry_ctls_high &=
1934 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1936 /* cpu-based controls */
1937 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1938 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1939 nested_vmx_procbased_ctls_low = 0;
1940 nested_vmx_procbased_ctls_high &=
1941 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1942 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1943 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1944 CPU_BASED_CR3_STORE_EXITING |
1945 #ifdef CONFIG_X86_64
1946 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1948 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1949 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1950 CPU_BASED_RDPMC_EXITING |
1951 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1953 * We can allow some features even when not supported by the
1954 * hardware. For example, L1 can specify an MSR bitmap - and we
1955 * can use it to avoid exits to L1 - even when L0 runs L2
1956 * without MSR bitmaps.
1958 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1960 /* secondary cpu-based controls */
1961 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1962 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1963 nested_vmx_secondary_ctls_low = 0;
1964 nested_vmx_secondary_ctls_high &=
1965 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1968 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1971 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1973 return ((control & high) | low) == control;
1976 static inline u64 vmx_control_msr(u32 low, u32 high)
1978 return low | ((u64)high << 32);
1982 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1983 * also let it use VMX-specific MSRs.
1984 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1985 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1986 * like all other MSRs).
1988 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1990 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1991 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1993 * According to the spec, processors which do not support VMX
1994 * should throw a #GP(0) when VMX capability MSRs are read.
1996 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2000 switch (msr_index) {
2001 case MSR_IA32_FEATURE_CONTROL:
2004 case MSR_IA32_VMX_BASIC:
2006 * This MSR reports some information about VMX support. We
2007 * should return information about the VMX we emulate for the
2008 * guest, and the VMCS structure we give it - not about the
2009 * VMX support of the underlying hardware.
2011 *pdata = VMCS12_REVISION |
2012 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2013 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2015 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2016 case MSR_IA32_VMX_PINBASED_CTLS:
2017 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2018 nested_vmx_pinbased_ctls_high);
2020 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2021 case MSR_IA32_VMX_PROCBASED_CTLS:
2022 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2023 nested_vmx_procbased_ctls_high);
2025 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2026 case MSR_IA32_VMX_EXIT_CTLS:
2027 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2028 nested_vmx_exit_ctls_high);
2030 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2031 case MSR_IA32_VMX_ENTRY_CTLS:
2032 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2033 nested_vmx_entry_ctls_high);
2035 case MSR_IA32_VMX_MISC:
2039 * These MSRs specify bits which the guest must keep fixed (on or off)
2040 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2041 * We picked the standard core2 setting.
2043 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2044 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2045 case MSR_IA32_VMX_CR0_FIXED0:
2046 *pdata = VMXON_CR0_ALWAYSON;
2048 case MSR_IA32_VMX_CR0_FIXED1:
2051 case MSR_IA32_VMX_CR4_FIXED0:
2052 *pdata = VMXON_CR4_ALWAYSON;
2054 case MSR_IA32_VMX_CR4_FIXED1:
2057 case MSR_IA32_VMX_VMCS_ENUM:
2060 case MSR_IA32_VMX_PROCBASED_CTLS2:
2061 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2062 nested_vmx_secondary_ctls_high);
2064 case MSR_IA32_VMX_EPT_VPID_CAP:
2065 /* Currently, no nested ept or nested vpid */
2075 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2077 if (!nested_vmx_allowed(vcpu))
2080 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2081 /* TODO: the right thing. */
2084 * No need to treat VMX capability MSRs specially: If we don't handle
2085 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2091 * Reads an msr value (of 'msr_index') into 'pdata'.
2092 * Returns 0 on success, non-0 otherwise.
2093 * Assumes vcpu_load() was already called.
2095 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2098 struct shared_msr_entry *msr;
2101 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2105 switch (msr_index) {
2106 #ifdef CONFIG_X86_64
2108 data = vmcs_readl(GUEST_FS_BASE);
2111 data = vmcs_readl(GUEST_GS_BASE);
2113 case MSR_KERNEL_GS_BASE:
2114 vmx_load_host_state(to_vmx(vcpu));
2115 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2119 return kvm_get_msr_common(vcpu, msr_index, pdata);
2121 data = guest_read_tsc();
2123 case MSR_IA32_SYSENTER_CS:
2124 data = vmcs_read32(GUEST_SYSENTER_CS);
2126 case MSR_IA32_SYSENTER_EIP:
2127 data = vmcs_readl(GUEST_SYSENTER_EIP);
2129 case MSR_IA32_SYSENTER_ESP:
2130 data = vmcs_readl(GUEST_SYSENTER_ESP);
2133 if (!to_vmx(vcpu)->rdtscp_enabled)
2135 /* Otherwise falls through */
2137 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2139 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2144 return kvm_get_msr_common(vcpu, msr_index, pdata);
2152 * Writes msr value into into the appropriate "register".
2153 * Returns 0 on success, non-0 otherwise.
2154 * Assumes vcpu_load() was already called.
2156 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2158 struct vcpu_vmx *vmx = to_vmx(vcpu);
2159 struct shared_msr_entry *msr;
2162 switch (msr_index) {
2164 ret = kvm_set_msr_common(vcpu, msr_index, data);
2166 #ifdef CONFIG_X86_64
2168 vmx_segment_cache_clear(vmx);
2169 vmcs_writel(GUEST_FS_BASE, data);
2172 vmx_segment_cache_clear(vmx);
2173 vmcs_writel(GUEST_GS_BASE, data);
2175 case MSR_KERNEL_GS_BASE:
2176 vmx_load_host_state(vmx);
2177 vmx->msr_guest_kernel_gs_base = data;
2180 case MSR_IA32_SYSENTER_CS:
2181 vmcs_write32(GUEST_SYSENTER_CS, data);
2183 case MSR_IA32_SYSENTER_EIP:
2184 vmcs_writel(GUEST_SYSENTER_EIP, data);
2186 case MSR_IA32_SYSENTER_ESP:
2187 vmcs_writel(GUEST_SYSENTER_ESP, data);
2190 kvm_write_tsc(vcpu, data);
2192 case MSR_IA32_CR_PAT:
2193 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2194 vmcs_write64(GUEST_IA32_PAT, data);
2195 vcpu->arch.pat = data;
2198 ret = kvm_set_msr_common(vcpu, msr_index, data);
2201 if (!vmx->rdtscp_enabled)
2203 /* Check reserved bit, higher 32 bits should be zero */
2204 if ((data >> 32) != 0)
2206 /* Otherwise falls through */
2208 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2210 msr = find_msr_entry(vmx, msr_index);
2213 if (msr - vmx->guest_msrs < vmx->save_nmsrs)
2214 kvm_set_shared_msr(msr->index, msr->data,
2218 ret = kvm_set_msr_common(vcpu, msr_index, data);
2224 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2226 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2229 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2232 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2234 case VCPU_EXREG_PDPTR:
2236 ept_save_pdptrs(vcpu);
2243 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2245 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2246 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2248 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2250 update_exception_bitmap(vcpu);
2253 static __init int cpu_has_kvm_support(void)
2255 return cpu_has_vmx();
2258 static __init int vmx_disabled_by_bios(void)
2262 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2263 if (msr & FEATURE_CONTROL_LOCKED) {
2264 /* launched w/ TXT and VMX disabled */
2265 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2268 /* launched w/o TXT and VMX only enabled w/ TXT */
2269 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2270 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2271 && !tboot_enabled()) {
2272 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2273 "activate TXT before enabling KVM\n");
2276 /* launched w/o TXT and VMX disabled */
2277 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2278 && !tboot_enabled())
2285 static void kvm_cpu_vmxon(u64 addr)
2287 asm volatile (ASM_VMX_VMXON_RAX
2288 : : "a"(&addr), "m"(addr)
2292 static int hardware_enable(void *garbage)
2294 int cpu = raw_smp_processor_id();
2295 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2298 if (read_cr4() & X86_CR4_VMXE)
2301 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2302 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2304 test_bits = FEATURE_CONTROL_LOCKED;
2305 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2306 if (tboot_enabled())
2307 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2309 if ((old & test_bits) != test_bits) {
2310 /* enable and lock */
2311 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2313 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2315 if (vmm_exclusive) {
2316 kvm_cpu_vmxon(phys_addr);
2320 store_gdt(&__get_cpu_var(host_gdt));
2325 static void vmclear_local_loaded_vmcss(void)
2327 int cpu = raw_smp_processor_id();
2328 struct loaded_vmcs *v, *n;
2330 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2331 loaded_vmcss_on_cpu_link)
2332 __loaded_vmcs_clear(v);
2336 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2339 static void kvm_cpu_vmxoff(void)
2341 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2344 static void hardware_disable(void *garbage)
2346 if (vmm_exclusive) {
2347 vmclear_local_loaded_vmcss();
2350 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2353 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2354 u32 msr, u32 *result)
2356 u32 vmx_msr_low, vmx_msr_high;
2357 u32 ctl = ctl_min | ctl_opt;
2359 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2361 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2362 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2364 /* Ensure minimum (required) set of control bits are supported. */
2372 static __init bool allow_1_setting(u32 msr, u32 ctl)
2374 u32 vmx_msr_low, vmx_msr_high;
2376 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2377 return vmx_msr_high & ctl;
2380 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2382 u32 vmx_msr_low, vmx_msr_high;
2383 u32 min, opt, min2, opt2;
2384 u32 _pin_based_exec_control = 0;
2385 u32 _cpu_based_exec_control = 0;
2386 u32 _cpu_based_2nd_exec_control = 0;
2387 u32 _vmexit_control = 0;
2388 u32 _vmentry_control = 0;
2390 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2391 opt = PIN_BASED_VIRTUAL_NMIS;
2392 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2393 &_pin_based_exec_control) < 0)
2396 min = CPU_BASED_HLT_EXITING |
2397 #ifdef CONFIG_X86_64
2398 CPU_BASED_CR8_LOAD_EXITING |
2399 CPU_BASED_CR8_STORE_EXITING |
2401 CPU_BASED_CR3_LOAD_EXITING |
2402 CPU_BASED_CR3_STORE_EXITING |
2403 CPU_BASED_USE_IO_BITMAPS |
2404 CPU_BASED_MOV_DR_EXITING |
2405 CPU_BASED_USE_TSC_OFFSETING |
2406 CPU_BASED_MWAIT_EXITING |
2407 CPU_BASED_MONITOR_EXITING |
2408 CPU_BASED_INVLPG_EXITING |
2409 CPU_BASED_RDPMC_EXITING;
2411 opt = CPU_BASED_TPR_SHADOW |
2412 CPU_BASED_USE_MSR_BITMAPS |
2413 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2414 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2415 &_cpu_based_exec_control) < 0)
2417 #ifdef CONFIG_X86_64
2418 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2419 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2420 ~CPU_BASED_CR8_STORE_EXITING;
2422 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2424 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2425 SECONDARY_EXEC_WBINVD_EXITING |
2426 SECONDARY_EXEC_ENABLE_VPID |
2427 SECONDARY_EXEC_ENABLE_EPT |
2428 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2429 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2430 SECONDARY_EXEC_RDTSCP;
2431 if (adjust_vmx_controls(min2, opt2,
2432 MSR_IA32_VMX_PROCBASED_CTLS2,
2433 &_cpu_based_2nd_exec_control) < 0)
2436 #ifndef CONFIG_X86_64
2437 if (!(_cpu_based_2nd_exec_control &
2438 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2439 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2441 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2442 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2444 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2445 CPU_BASED_CR3_STORE_EXITING |
2446 CPU_BASED_INVLPG_EXITING);
2447 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2448 vmx_capability.ept, vmx_capability.vpid);
2452 #ifdef CONFIG_X86_64
2453 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2455 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2456 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2457 &_vmexit_control) < 0)
2461 opt = VM_ENTRY_LOAD_IA32_PAT;
2462 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2463 &_vmentry_control) < 0)
2466 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2468 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2469 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2472 #ifdef CONFIG_X86_64
2473 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2474 if (vmx_msr_high & (1u<<16))
2478 /* Require Write-Back (WB) memory type for VMCS accesses. */
2479 if (((vmx_msr_high >> 18) & 15) != 6)
2482 vmcs_conf->size = vmx_msr_high & 0x1fff;
2483 vmcs_conf->order = get_order(vmcs_config.size);
2484 vmcs_conf->revision_id = vmx_msr_low;
2486 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2487 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2488 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2489 vmcs_conf->vmexit_ctrl = _vmexit_control;
2490 vmcs_conf->vmentry_ctrl = _vmentry_control;
2492 cpu_has_load_ia32_efer =
2493 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2494 VM_ENTRY_LOAD_IA32_EFER)
2495 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2496 VM_EXIT_LOAD_IA32_EFER);
2498 cpu_has_load_perf_global_ctrl =
2499 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2500 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2501 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2502 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2505 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2506 * but due to arrata below it can't be used. Workaround is to use
2507 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2509 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2514 * BC86,AAY89,BD102 (model 44)
2518 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2519 switch (boot_cpu_data.x86_model) {
2525 cpu_has_load_perf_global_ctrl = false;
2526 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2527 "does not work properly. Using workaround\n");
2537 static struct vmcs *alloc_vmcs_cpu(int cpu)
2539 int node = cpu_to_node(cpu);
2543 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2546 vmcs = page_address(pages);
2547 memset(vmcs, 0, vmcs_config.size);
2548 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2552 static struct vmcs *alloc_vmcs(void)
2554 return alloc_vmcs_cpu(raw_smp_processor_id());
2557 static void free_vmcs(struct vmcs *vmcs)
2559 free_pages((unsigned long)vmcs, vmcs_config.order);
2563 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2565 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2567 if (!loaded_vmcs->vmcs)
2569 loaded_vmcs_clear(loaded_vmcs);
2570 free_vmcs(loaded_vmcs->vmcs);
2571 loaded_vmcs->vmcs = NULL;
2574 static void free_kvm_area(void)
2578 for_each_possible_cpu(cpu) {
2579 free_vmcs(per_cpu(vmxarea, cpu));
2580 per_cpu(vmxarea, cpu) = NULL;
2584 static __init int alloc_kvm_area(void)
2588 for_each_possible_cpu(cpu) {
2591 vmcs = alloc_vmcs_cpu(cpu);
2597 per_cpu(vmxarea, cpu) = vmcs;
2602 static __init int hardware_setup(void)
2604 if (setup_vmcs_config(&vmcs_config) < 0)
2607 if (boot_cpu_has(X86_FEATURE_NX))
2608 kvm_enable_efer_bits(EFER_NX);
2610 if (!cpu_has_vmx_vpid())
2613 if (!cpu_has_vmx_ept() ||
2614 !cpu_has_vmx_ept_4levels()) {
2616 enable_unrestricted_guest = 0;
2619 if (!cpu_has_vmx_unrestricted_guest())
2620 enable_unrestricted_guest = 0;
2622 if (!cpu_has_vmx_flexpriority())
2623 flexpriority_enabled = 0;
2625 if (!cpu_has_vmx_tpr_shadow())
2626 kvm_x86_ops->update_cr8_intercept = NULL;
2628 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2629 kvm_disable_largepages();
2631 if (!cpu_has_vmx_ple())
2635 nested_vmx_setup_ctls_msrs();
2637 return alloc_kvm_area();
2640 static __exit void hardware_unsetup(void)
2645 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2647 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2649 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2650 vmcs_write16(sf->selector, save->selector);
2651 vmcs_writel(sf->base, save->base);
2652 vmcs_write32(sf->limit, save->limit);
2653 vmcs_write32(sf->ar_bytes, save->ar);
2655 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2657 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2661 static void enter_pmode(struct kvm_vcpu *vcpu)
2663 unsigned long flags;
2664 struct vcpu_vmx *vmx = to_vmx(vcpu);
2666 vmx->emulation_required = 1;
2667 vmx->rmode.vm86_active = 0;
2669 vmx_segment_cache_clear(vmx);
2671 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2672 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2673 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2674 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2676 flags = vmcs_readl(GUEST_RFLAGS);
2677 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2678 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2679 vmcs_writel(GUEST_RFLAGS, flags);
2681 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2682 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2684 update_exception_bitmap(vcpu);
2686 if (emulate_invalid_guest_state)
2689 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2690 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2691 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2692 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2694 vmx_segment_cache_clear(vmx);
2696 vmcs_write16(GUEST_SS_SELECTOR, 0);
2697 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2699 vmcs_write16(GUEST_CS_SELECTOR,
2700 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2701 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2704 static gva_t rmode_tss_base(struct kvm *kvm)
2706 if (!kvm->arch.tss_addr) {
2707 struct kvm_memslots *slots;
2708 struct kvm_memory_slot *slot;
2711 slots = kvm_memslots(kvm);
2712 slot = id_to_memslot(slots, 0);
2713 base_gfn = slot->base_gfn + slot->npages - 3;
2715 return base_gfn << PAGE_SHIFT;
2717 return kvm->arch.tss_addr;
2720 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2722 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2724 save->selector = vmcs_read16(sf->selector);
2725 save->base = vmcs_readl(sf->base);
2726 save->limit = vmcs_read32(sf->limit);
2727 save->ar = vmcs_read32(sf->ar_bytes);
2728 vmcs_write16(sf->selector, save->base >> 4);
2729 vmcs_write32(sf->base, save->base & 0xffff0);
2730 vmcs_write32(sf->limit, 0xffff);
2731 vmcs_write32(sf->ar_bytes, 0xf3);
2732 if (save->base & 0xf)
2733 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2734 " aligned when entering protected mode (seg=%d)",
2738 static void enter_rmode(struct kvm_vcpu *vcpu)
2740 unsigned long flags;
2741 struct vcpu_vmx *vmx = to_vmx(vcpu);
2743 if (enable_unrestricted_guest)
2746 vmx->emulation_required = 1;
2747 vmx->rmode.vm86_active = 1;
2750 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2751 * vcpu. Call it here with phys address pointing 16M below 4G.
2753 if (!vcpu->kvm->arch.tss_addr) {
2754 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2755 "called before entering vcpu\n");
2756 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2757 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2758 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2761 vmx_segment_cache_clear(vmx);
2763 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2764 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2765 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2767 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2768 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2770 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2771 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2773 flags = vmcs_readl(GUEST_RFLAGS);
2774 vmx->rmode.save_rflags = flags;
2776 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2778 vmcs_writel(GUEST_RFLAGS, flags);
2779 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2780 update_exception_bitmap(vcpu);
2782 if (emulate_invalid_guest_state)
2783 goto continue_rmode;
2785 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2786 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2787 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2789 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2790 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2791 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2792 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2793 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2795 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2796 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2797 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2798 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2801 kvm_mmu_reset_context(vcpu);
2804 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2806 struct vcpu_vmx *vmx = to_vmx(vcpu);
2807 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2813 * Force kernel_gs_base reloading before EFER changes, as control
2814 * of this msr depends on is_long_mode().
2816 vmx_load_host_state(to_vmx(vcpu));
2817 vcpu->arch.efer = efer;
2818 if (efer & EFER_LMA) {
2819 vmcs_write32(VM_ENTRY_CONTROLS,
2820 vmcs_read32(VM_ENTRY_CONTROLS) |
2821 VM_ENTRY_IA32E_MODE);
2824 vmcs_write32(VM_ENTRY_CONTROLS,
2825 vmcs_read32(VM_ENTRY_CONTROLS) &
2826 ~VM_ENTRY_IA32E_MODE);
2828 msr->data = efer & ~EFER_LME;
2833 #ifdef CONFIG_X86_64
2835 static void enter_lmode(struct kvm_vcpu *vcpu)
2839 vmx_segment_cache_clear(to_vmx(vcpu));
2841 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2842 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2843 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2845 vmcs_write32(GUEST_TR_AR_BYTES,
2846 (guest_tr_ar & ~AR_TYPE_MASK)
2847 | AR_TYPE_BUSY_64_TSS);
2849 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2852 static void exit_lmode(struct kvm_vcpu *vcpu)
2854 vmcs_write32(VM_ENTRY_CONTROLS,
2855 vmcs_read32(VM_ENTRY_CONTROLS)
2856 & ~VM_ENTRY_IA32E_MODE);
2857 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2862 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2864 vpid_sync_context(to_vmx(vcpu));
2866 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2868 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2872 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2874 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2876 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2877 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2880 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2882 if (enable_ept && is_paging(vcpu))
2883 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2884 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2887 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2889 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2891 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2892 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2895 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2897 if (!test_bit(VCPU_EXREG_PDPTR,
2898 (unsigned long *)&vcpu->arch.regs_dirty))
2901 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2902 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2903 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2904 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2905 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2909 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2911 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2912 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2913 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2914 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2915 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2918 __set_bit(VCPU_EXREG_PDPTR,
2919 (unsigned long *)&vcpu->arch.regs_avail);
2920 __set_bit(VCPU_EXREG_PDPTR,
2921 (unsigned long *)&vcpu->arch.regs_dirty);
2924 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2926 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2928 struct kvm_vcpu *vcpu)
2930 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2931 vmx_decache_cr3(vcpu);
2932 if (!(cr0 & X86_CR0_PG)) {
2933 /* From paging/starting to nonpaging */
2934 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2935 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2936 (CPU_BASED_CR3_LOAD_EXITING |
2937 CPU_BASED_CR3_STORE_EXITING));
2938 vcpu->arch.cr0 = cr0;
2939 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2940 } else if (!is_paging(vcpu)) {
2941 /* From nonpaging to paging */
2942 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2943 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2944 ~(CPU_BASED_CR3_LOAD_EXITING |
2945 CPU_BASED_CR3_STORE_EXITING));
2946 vcpu->arch.cr0 = cr0;
2947 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2950 if (!(cr0 & X86_CR0_WP))
2951 *hw_cr0 &= ~X86_CR0_WP;
2954 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2956 struct vcpu_vmx *vmx = to_vmx(vcpu);
2957 unsigned long hw_cr0;
2959 if (enable_unrestricted_guest)
2960 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2961 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2963 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2965 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2968 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2971 #ifdef CONFIG_X86_64
2972 if (vcpu->arch.efer & EFER_LME) {
2973 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2975 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2981 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2983 if (!vcpu->fpu_active)
2984 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2986 vmcs_writel(CR0_READ_SHADOW, cr0);
2987 vmcs_writel(GUEST_CR0, hw_cr0);
2988 vcpu->arch.cr0 = cr0;
2989 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2992 static u64 construct_eptp(unsigned long root_hpa)
2996 /* TODO write the value reading from MSR */
2997 eptp = VMX_EPT_DEFAULT_MT |
2998 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2999 eptp |= (root_hpa & PAGE_MASK);
3004 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3006 unsigned long guest_cr3;
3011 eptp = construct_eptp(cr3);
3012 vmcs_write64(EPT_POINTER, eptp);
3013 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3014 vcpu->kvm->arch.ept_identity_map_addr;
3015 ept_load_pdptrs(vcpu);
3018 vmx_flush_tlb(vcpu);
3019 vmcs_writel(GUEST_CR3, guest_cr3);
3022 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3024 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3025 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3027 if (cr4 & X86_CR4_VMXE) {
3029 * To use VMXON (and later other VMX instructions), a guest
3030 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3031 * So basically the check on whether to allow nested VMX
3034 if (!nested_vmx_allowed(vcpu))
3036 } else if (to_vmx(vcpu)->nested.vmxon)
3039 vcpu->arch.cr4 = cr4;
3041 if (!is_paging(vcpu)) {
3042 hw_cr4 &= ~X86_CR4_PAE;
3043 hw_cr4 |= X86_CR4_PSE;
3044 } else if (!(cr4 & X86_CR4_PAE)) {
3045 hw_cr4 &= ~X86_CR4_PAE;
3049 vmcs_writel(CR4_READ_SHADOW, cr4);
3050 vmcs_writel(GUEST_CR4, hw_cr4);
3054 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3055 struct kvm_segment *var, int seg)
3057 struct vcpu_vmx *vmx = to_vmx(vcpu);
3058 struct kvm_save_segment *save;
3061 if (vmx->rmode.vm86_active
3062 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3063 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3064 || seg == VCPU_SREG_GS)
3065 && !emulate_invalid_guest_state) {
3067 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3068 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3069 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3070 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3071 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3074 var->selector = save->selector;
3075 var->base = save->base;
3076 var->limit = save->limit;
3078 if (seg == VCPU_SREG_TR
3079 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3080 goto use_saved_rmode_seg;
3082 var->base = vmx_read_guest_seg_base(vmx, seg);
3083 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3084 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3085 ar = vmx_read_guest_seg_ar(vmx, seg);
3086 use_saved_rmode_seg:
3087 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3089 var->type = ar & 15;
3090 var->s = (ar >> 4) & 1;
3091 var->dpl = (ar >> 5) & 3;
3092 var->present = (ar >> 7) & 1;
3093 var->avl = (ar >> 12) & 1;
3094 var->l = (ar >> 13) & 1;
3095 var->db = (ar >> 14) & 1;
3096 var->g = (ar >> 15) & 1;
3097 var->unusable = (ar >> 16) & 1;
3100 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3102 struct kvm_segment s;
3104 if (to_vmx(vcpu)->rmode.vm86_active) {
3105 vmx_get_segment(vcpu, &s, seg);
3108 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3111 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3113 if (!is_protmode(vcpu))
3116 if (!is_long_mode(vcpu)
3117 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3120 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3123 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3125 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3126 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3127 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3129 return to_vmx(vcpu)->cpl;
3133 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3140 ar = var->type & 15;
3141 ar |= (var->s & 1) << 4;
3142 ar |= (var->dpl & 3) << 5;
3143 ar |= (var->present & 1) << 7;
3144 ar |= (var->avl & 1) << 12;
3145 ar |= (var->l & 1) << 13;
3146 ar |= (var->db & 1) << 14;
3147 ar |= (var->g & 1) << 15;
3149 if (ar == 0) /* a 0 value means unusable */
3150 ar = AR_UNUSABLE_MASK;
3155 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3156 struct kvm_segment *var, int seg)
3158 struct vcpu_vmx *vmx = to_vmx(vcpu);
3159 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3162 vmx_segment_cache_clear(vmx);
3164 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3165 vmcs_write16(sf->selector, var->selector);
3166 vmx->rmode.tr.selector = var->selector;
3167 vmx->rmode.tr.base = var->base;
3168 vmx->rmode.tr.limit = var->limit;
3169 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3172 vmcs_writel(sf->base, var->base);
3173 vmcs_write32(sf->limit, var->limit);
3174 vmcs_write16(sf->selector, var->selector);
3175 if (vmx->rmode.vm86_active && var->s) {
3177 * Hack real-mode segments into vm86 compatibility.
3179 if (var->base == 0xffff0000 && var->selector == 0xf000)
3180 vmcs_writel(sf->base, 0xf0000);
3183 ar = vmx_segment_access_rights(var);
3186 * Fix the "Accessed" bit in AR field of segment registers for older
3188 * IA32 arch specifies that at the time of processor reset the
3189 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3190 * is setting it to 0 in the usedland code. This causes invalid guest
3191 * state vmexit when "unrestricted guest" mode is turned on.
3192 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3193 * tree. Newer qemu binaries with that qemu fix would not need this
3196 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3197 ar |= 0x1; /* Accessed */
3199 vmcs_write32(sf->ar_bytes, ar);
3200 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3203 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3205 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3207 *db = (ar >> 14) & 1;
3208 *l = (ar >> 13) & 1;
3211 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3213 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3214 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3217 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3219 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3220 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3223 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3225 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3226 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3229 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3231 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3232 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3235 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3237 struct kvm_segment var;
3240 vmx_get_segment(vcpu, &var, seg);
3241 ar = vmx_segment_access_rights(&var);
3243 if (var.base != (var.selector << 4))
3245 if (var.limit != 0xffff)
3253 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3255 struct kvm_segment cs;
3256 unsigned int cs_rpl;
3258 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3259 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3263 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3267 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3268 if (cs.dpl > cs_rpl)
3271 if (cs.dpl != cs_rpl)
3277 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3281 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3283 struct kvm_segment ss;
3284 unsigned int ss_rpl;
3286 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3287 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3291 if (ss.type != 3 && ss.type != 7)
3295 if (ss.dpl != ss_rpl) /* DPL != RPL */
3303 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3305 struct kvm_segment var;
3308 vmx_get_segment(vcpu, &var, seg);
3309 rpl = var.selector & SELECTOR_RPL_MASK;
3317 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3318 if (var.dpl < rpl) /* DPL < RPL */
3322 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3328 static bool tr_valid(struct kvm_vcpu *vcpu)
3330 struct kvm_segment tr;
3332 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3336 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3338 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3346 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3348 struct kvm_segment ldtr;
3350 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3354 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3364 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3366 struct kvm_segment cs, ss;
3368 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3369 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3371 return ((cs.selector & SELECTOR_RPL_MASK) ==
3372 (ss.selector & SELECTOR_RPL_MASK));
3376 * Check if guest state is valid. Returns true if valid, false if
3378 * We assume that registers are always usable
3380 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3382 /* real mode guest state checks */
3383 if (!is_protmode(vcpu)) {
3384 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3386 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3388 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3390 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3392 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3394 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3397 /* protected mode guest state checks */
3398 if (!cs_ss_rpl_check(vcpu))
3400 if (!code_segment_valid(vcpu))
3402 if (!stack_segment_valid(vcpu))
3404 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3406 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3408 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3410 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3412 if (!tr_valid(vcpu))
3414 if (!ldtr_valid(vcpu))
3418 * - Add checks on RIP
3419 * - Add checks on RFLAGS
3425 static int init_rmode_tss(struct kvm *kvm)
3429 int r, idx, ret = 0;
3431 idx = srcu_read_lock(&kvm->srcu);
3432 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3433 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3436 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3437 r = kvm_write_guest_page(kvm, fn++, &data,
3438 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3441 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3444 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3448 r = kvm_write_guest_page(kvm, fn, &data,
3449 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3456 srcu_read_unlock(&kvm->srcu, idx);
3460 static int init_rmode_identity_map(struct kvm *kvm)
3463 pfn_t identity_map_pfn;
3468 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3469 printk(KERN_ERR "EPT: identity-mapping pagetable "
3470 "haven't been allocated!\n");
3473 if (likely(kvm->arch.ept_identity_pagetable_done))
3476 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3477 idx = srcu_read_lock(&kvm->srcu);
3478 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3481 /* Set up identity-mapping pagetable for EPT in real mode */
3482 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3483 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3484 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3485 r = kvm_write_guest_page(kvm, identity_map_pfn,
3486 &tmp, i * sizeof(tmp), sizeof(tmp));
3490 kvm->arch.ept_identity_pagetable_done = true;
3493 srcu_read_unlock(&kvm->srcu, idx);
3497 static void seg_setup(int seg)
3499 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3502 vmcs_write16(sf->selector, 0);
3503 vmcs_writel(sf->base, 0);
3504 vmcs_write32(sf->limit, 0xffff);
3505 if (enable_unrestricted_guest) {
3507 if (seg == VCPU_SREG_CS)
3508 ar |= 0x08; /* code segment */
3512 vmcs_write32(sf->ar_bytes, ar);
3515 static int alloc_apic_access_page(struct kvm *kvm)
3517 struct kvm_userspace_memory_region kvm_userspace_mem;
3520 mutex_lock(&kvm->slots_lock);
3521 if (kvm->arch.apic_access_page)
3523 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3524 kvm_userspace_mem.flags = 0;
3525 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3526 kvm_userspace_mem.memory_size = PAGE_SIZE;
3527 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3531 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3533 mutex_unlock(&kvm->slots_lock);
3537 static int alloc_identity_pagetable(struct kvm *kvm)
3539 struct kvm_userspace_memory_region kvm_userspace_mem;
3542 mutex_lock(&kvm->slots_lock);
3543 if (kvm->arch.ept_identity_pagetable)
3545 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3546 kvm_userspace_mem.flags = 0;
3547 kvm_userspace_mem.guest_phys_addr =
3548 kvm->arch.ept_identity_map_addr;
3549 kvm_userspace_mem.memory_size = PAGE_SIZE;
3550 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3554 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3555 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3557 mutex_unlock(&kvm->slots_lock);
3561 static void allocate_vpid(struct vcpu_vmx *vmx)
3568 spin_lock(&vmx_vpid_lock);
3569 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3570 if (vpid < VMX_NR_VPIDS) {
3572 __set_bit(vpid, vmx_vpid_bitmap);
3574 spin_unlock(&vmx_vpid_lock);
3577 static void free_vpid(struct vcpu_vmx *vmx)
3581 spin_lock(&vmx_vpid_lock);
3583 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3584 spin_unlock(&vmx_vpid_lock);
3587 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3589 int f = sizeof(unsigned long);
3591 if (!cpu_has_vmx_msr_bitmap())
3595 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3596 * have the write-low and read-high bitmap offsets the wrong way round.
3597 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3599 if (msr <= 0x1fff) {
3600 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3601 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3602 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3604 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3605 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3609 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3612 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3613 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3617 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3618 * will not change in the lifetime of the guest.
3619 * Note that host-state that does change is set elsewhere. E.g., host-state
3620 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3622 static void vmx_set_constant_host_state(void)
3628 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3629 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3630 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3632 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3633 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3634 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3635 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3636 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3638 native_store_idt(&dt);
3639 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3641 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3642 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3644 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3645 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3646 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3647 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3649 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3650 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3651 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3655 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3657 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3659 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3660 if (is_guest_mode(&vmx->vcpu))
3661 vmx->vcpu.arch.cr4_guest_owned_bits &=
3662 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3663 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3666 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3668 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3669 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3670 exec_control &= ~CPU_BASED_TPR_SHADOW;
3671 #ifdef CONFIG_X86_64
3672 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3673 CPU_BASED_CR8_LOAD_EXITING;
3677 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3678 CPU_BASED_CR3_LOAD_EXITING |
3679 CPU_BASED_INVLPG_EXITING;
3680 return exec_control;
3683 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3685 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3686 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3687 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3689 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3691 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3692 enable_unrestricted_guest = 0;
3694 if (!enable_unrestricted_guest)
3695 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3697 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3698 return exec_control;
3701 static void ept_set_mmio_spte_mask(void)
3704 * EPT Misconfigurations can be generated if the value of bits 2:0
3705 * of an EPT paging-structure entry is 110b (write/execute).
3706 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3709 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3713 * Sets up the vmcs for emulated real mode.
3715 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3717 #ifdef CONFIG_X86_64
3723 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3724 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3726 if (cpu_has_vmx_msr_bitmap())
3727 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3729 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3732 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3733 vmcs_config.pin_based_exec_ctrl);
3735 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3737 if (cpu_has_secondary_exec_ctrls()) {
3738 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3739 vmx_secondary_exec_control(vmx));
3743 vmcs_write32(PLE_GAP, ple_gap);
3744 vmcs_write32(PLE_WINDOW, ple_window);
3747 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3748 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3749 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3751 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3752 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
3753 vmx_set_constant_host_state();
3754 #ifdef CONFIG_X86_64
3755 rdmsrl(MSR_FS_BASE, a);
3756 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3757 rdmsrl(MSR_GS_BASE, a);
3758 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3760 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3761 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3764 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3765 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3766 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3767 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3768 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3770 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3771 u32 msr_low, msr_high;
3773 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3774 host_pat = msr_low | ((u64) msr_high << 32);
3775 /* Write the default value follow host pat */
3776 vmcs_write64(GUEST_IA32_PAT, host_pat);
3777 /* Keep arch.pat sync with GUEST_IA32_PAT */
3778 vmx->vcpu.arch.pat = host_pat;
3781 for (i = 0; i < NR_VMX_MSR; ++i) {
3782 u32 index = vmx_msr_index[i];
3783 u32 data_low, data_high;
3786 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3788 if (wrmsr_safe(index, data_low, data_high) < 0)
3790 vmx->guest_msrs[j].index = i;
3791 vmx->guest_msrs[j].data = 0;
3792 vmx->guest_msrs[j].mask = -1ull;
3796 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3798 /* 22.2.1, 20.8.1 */
3799 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3801 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3802 set_cr4_guest_host_mask(vmx);
3804 kvm_write_tsc(&vmx->vcpu, 0);
3809 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3811 struct vcpu_vmx *vmx = to_vmx(vcpu);
3815 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3817 vmx->rmode.vm86_active = 0;
3819 vmx->soft_vnmi_blocked = 0;
3821 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3822 kvm_set_cr8(&vmx->vcpu, 0);
3823 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3824 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3825 msr |= MSR_IA32_APICBASE_BSP;
3826 kvm_set_apic_base(&vmx->vcpu, msr);
3828 ret = fx_init(&vmx->vcpu);
3832 vmx_segment_cache_clear(vmx);
3834 seg_setup(VCPU_SREG_CS);
3836 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3837 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3839 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3840 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3841 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3843 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3844 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3847 seg_setup(VCPU_SREG_DS);
3848 seg_setup(VCPU_SREG_ES);
3849 seg_setup(VCPU_SREG_FS);
3850 seg_setup(VCPU_SREG_GS);
3851 seg_setup(VCPU_SREG_SS);
3853 vmcs_write16(GUEST_TR_SELECTOR, 0);
3854 vmcs_writel(GUEST_TR_BASE, 0);
3855 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3856 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3858 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3859 vmcs_writel(GUEST_LDTR_BASE, 0);
3860 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3861 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3863 vmcs_write32(GUEST_SYSENTER_CS, 0);
3864 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3865 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3867 vmcs_writel(GUEST_RFLAGS, 0x02);
3868 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3869 kvm_rip_write(vcpu, 0xfff0);
3871 kvm_rip_write(vcpu, 0);
3872 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3874 vmcs_writel(GUEST_DR7, 0x400);
3876 vmcs_writel(GUEST_GDTR_BASE, 0);
3877 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3879 vmcs_writel(GUEST_IDTR_BASE, 0);
3880 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3882 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3883 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3884 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3886 /* Special registers */
3887 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3891 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3893 if (cpu_has_vmx_tpr_shadow()) {
3894 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3895 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3896 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3897 __pa(vmx->vcpu.arch.apic->regs));
3898 vmcs_write32(TPR_THRESHOLD, 0);
3901 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3902 vmcs_write64(APIC_ACCESS_ADDR,
3903 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3906 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3908 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3909 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3910 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3911 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3912 vmx_set_cr4(&vmx->vcpu, 0);
3913 vmx_set_efer(&vmx->vcpu, 0);
3914 vmx_fpu_activate(&vmx->vcpu);
3915 update_exception_bitmap(&vmx->vcpu);
3917 vpid_sync_context(vmx);
3921 /* HACK: Don't enable emulation on guest boot/reset */
3922 vmx->emulation_required = 0;
3929 * In nested virtualization, check if L1 asked to exit on external interrupts.
3930 * For most existing hypervisors, this will always return true.
3932 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3934 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3935 PIN_BASED_EXT_INTR_MASK;
3938 static void enable_irq_window(struct kvm_vcpu *vcpu)
3940 u32 cpu_based_vm_exec_control;
3941 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3943 * We get here if vmx_interrupt_allowed() said we can't
3944 * inject to L1 now because L2 must run. Ask L2 to exit
3945 * right after entry, so we can inject to L1 more promptly.
3947 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
3951 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3952 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3953 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3956 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3958 u32 cpu_based_vm_exec_control;
3960 if (!cpu_has_virtual_nmis()) {
3961 enable_irq_window(vcpu);
3965 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3966 enable_irq_window(vcpu);
3969 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3970 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3971 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3974 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3976 struct vcpu_vmx *vmx = to_vmx(vcpu);
3978 int irq = vcpu->arch.interrupt.nr;
3980 trace_kvm_inj_virq(irq);
3982 ++vcpu->stat.irq_injections;
3983 if (vmx->rmode.vm86_active) {
3985 if (vcpu->arch.interrupt.soft)
3986 inc_eip = vcpu->arch.event_exit_inst_len;
3987 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3988 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3991 intr = irq | INTR_INFO_VALID_MASK;
3992 if (vcpu->arch.interrupt.soft) {
3993 intr |= INTR_TYPE_SOFT_INTR;
3994 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3995 vmx->vcpu.arch.event_exit_inst_len);
3997 intr |= INTR_TYPE_EXT_INTR;
3998 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4001 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4003 struct vcpu_vmx *vmx = to_vmx(vcpu);
4005 if (is_guest_mode(vcpu))
4008 if (!cpu_has_virtual_nmis()) {
4010 * Tracking the NMI-blocked state in software is built upon
4011 * finding the next open IRQ window. This, in turn, depends on
4012 * well-behaving guests: They have to keep IRQs disabled at
4013 * least as long as the NMI handler runs. Otherwise we may
4014 * cause NMI nesting, maybe breaking the guest. But as this is
4015 * highly unlikely, we can live with the residual risk.
4017 vmx->soft_vnmi_blocked = 1;
4018 vmx->vnmi_blocked_time = 0;
4021 ++vcpu->stat.nmi_injections;
4022 vmx->nmi_known_unmasked = false;
4023 if (vmx->rmode.vm86_active) {
4024 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4025 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4028 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4029 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4032 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4034 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4037 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4038 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4039 | GUEST_INTR_STATE_NMI));
4042 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4044 if (!cpu_has_virtual_nmis())
4045 return to_vmx(vcpu)->soft_vnmi_blocked;
4046 if (to_vmx(vcpu)->nmi_known_unmasked)
4048 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4051 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4053 struct vcpu_vmx *vmx = to_vmx(vcpu);
4055 if (!cpu_has_virtual_nmis()) {
4056 if (vmx->soft_vnmi_blocked != masked) {
4057 vmx->soft_vnmi_blocked = masked;
4058 vmx->vnmi_blocked_time = 0;
4061 vmx->nmi_known_unmasked = !masked;
4063 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4064 GUEST_INTR_STATE_NMI);
4066 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4067 GUEST_INTR_STATE_NMI);
4071 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4073 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4074 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4075 if (to_vmx(vcpu)->nested.nested_run_pending ||
4076 (vmcs12->idt_vectoring_info_field &
4077 VECTORING_INFO_VALID_MASK))
4079 nested_vmx_vmexit(vcpu);
4080 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4081 vmcs12->vm_exit_intr_info = 0;
4082 /* fall through to normal code, but now in L1, not L2 */
4085 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4086 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4087 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4090 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4093 struct kvm_userspace_memory_region tss_mem = {
4094 .slot = TSS_PRIVATE_MEMSLOT,
4095 .guest_phys_addr = addr,
4096 .memory_size = PAGE_SIZE * 3,
4100 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4103 kvm->arch.tss_addr = addr;
4104 if (!init_rmode_tss(kvm))
4110 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4111 int vec, u32 err_code)
4114 * Instruction with address size override prefix opcode 0x67
4115 * Cause the #SS fault with 0 error code in VM86 mode.
4117 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4118 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4121 * Forward all other exceptions that are valid in real mode.
4122 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4123 * the required debugging infrastructure rework.
4127 if (vcpu->guest_debug &
4128 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4130 kvm_queue_exception(vcpu, vec);
4134 * Update instruction length as we may reinject the exception
4135 * from user space while in guest debugging mode.
4137 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4138 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4139 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4150 kvm_queue_exception(vcpu, vec);
4157 * Trigger machine check on the host. We assume all the MSRs are already set up
4158 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4159 * We pass a fake environment to the machine check handler because we want
4160 * the guest to be always treated like user space, no matter what context
4161 * it used internally.
4163 static void kvm_machine_check(void)
4165 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4166 struct pt_regs regs = {
4167 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4168 .flags = X86_EFLAGS_IF,
4171 do_machine_check(®s, 0);
4175 static int handle_machine_check(struct kvm_vcpu *vcpu)
4177 /* already handled by vcpu_run */
4181 static int handle_exception(struct kvm_vcpu *vcpu)
4183 struct vcpu_vmx *vmx = to_vmx(vcpu);
4184 struct kvm_run *kvm_run = vcpu->run;
4185 u32 intr_info, ex_no, error_code;
4186 unsigned long cr2, rip, dr6;
4188 enum emulation_result er;
4190 vect_info = vmx->idt_vectoring_info;
4191 intr_info = vmx->exit_intr_info;
4193 if (is_machine_check(intr_info))
4194 return handle_machine_check(vcpu);
4196 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4197 !is_page_fault(intr_info)) {
4198 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4199 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4200 vcpu->run->internal.ndata = 2;
4201 vcpu->run->internal.data[0] = vect_info;
4202 vcpu->run->internal.data[1] = intr_info;
4206 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4207 return 1; /* already handled by vmx_vcpu_run() */
4209 if (is_no_device(intr_info)) {
4210 vmx_fpu_activate(vcpu);
4214 if (is_invalid_opcode(intr_info)) {
4215 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4216 if (er != EMULATE_DONE)
4217 kvm_queue_exception(vcpu, UD_VECTOR);
4222 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4223 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4224 if (is_page_fault(intr_info)) {
4225 /* EPT won't cause page fault directly */
4227 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4228 trace_kvm_page_fault(cr2, error_code);
4230 if (kvm_event_needs_reinjection(vcpu))
4231 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4232 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4235 if (vmx->rmode.vm86_active &&
4236 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4238 if (vcpu->arch.halt_request) {
4239 vcpu->arch.halt_request = 0;
4240 return kvm_emulate_halt(vcpu);
4245 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4248 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4249 if (!(vcpu->guest_debug &
4250 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4251 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4252 kvm_queue_exception(vcpu, DB_VECTOR);
4255 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4256 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4260 * Update instruction length as we may reinject #BP from
4261 * user space while in guest debugging mode. Reading it for
4262 * #DB as well causes no harm, it is not used in that case.
4264 vmx->vcpu.arch.event_exit_inst_len =
4265 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4266 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4267 rip = kvm_rip_read(vcpu);
4268 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4269 kvm_run->debug.arch.exception = ex_no;
4272 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4273 kvm_run->ex.exception = ex_no;
4274 kvm_run->ex.error_code = error_code;
4280 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4282 ++vcpu->stat.irq_exits;
4286 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4288 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4292 static int handle_io(struct kvm_vcpu *vcpu)
4294 unsigned long exit_qualification;
4295 int size, in, string;
4298 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4299 string = (exit_qualification & 16) != 0;
4300 in = (exit_qualification & 8) != 0;
4302 ++vcpu->stat.io_exits;
4305 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4307 port = exit_qualification >> 16;
4308 size = (exit_qualification & 7) + 1;
4309 skip_emulated_instruction(vcpu);
4311 return kvm_fast_pio_out(vcpu, size, port);
4315 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4318 * Patch in the VMCALL instruction:
4320 hypercall[0] = 0x0f;
4321 hypercall[1] = 0x01;
4322 hypercall[2] = 0xc1;
4325 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4326 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4328 if (to_vmx(vcpu)->nested.vmxon &&
4329 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4332 if (is_guest_mode(vcpu)) {
4334 * We get here when L2 changed cr0 in a way that did not change
4335 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4336 * but did change L0 shadowed bits. This can currently happen
4337 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4338 * loading) while pretending to allow the guest to change it.
4340 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4341 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4343 vmcs_writel(CR0_READ_SHADOW, val);
4346 return kvm_set_cr0(vcpu, val);
4349 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4351 if (is_guest_mode(vcpu)) {
4352 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4353 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4355 vmcs_writel(CR4_READ_SHADOW, val);
4358 return kvm_set_cr4(vcpu, val);
4361 /* called to set cr0 as approriate for clts instruction exit. */
4362 static void handle_clts(struct kvm_vcpu *vcpu)
4364 if (is_guest_mode(vcpu)) {
4366 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4367 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4368 * just pretend it's off (also in arch.cr0 for fpu_activate).
4370 vmcs_writel(CR0_READ_SHADOW,
4371 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4372 vcpu->arch.cr0 &= ~X86_CR0_TS;
4374 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4377 static int handle_cr(struct kvm_vcpu *vcpu)
4379 unsigned long exit_qualification, val;
4384 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4385 cr = exit_qualification & 15;
4386 reg = (exit_qualification >> 8) & 15;
4387 switch ((exit_qualification >> 4) & 3) {
4388 case 0: /* mov to cr */
4389 val = kvm_register_read(vcpu, reg);
4390 trace_kvm_cr_write(cr, val);
4393 err = handle_set_cr0(vcpu, val);
4394 kvm_complete_insn_gp(vcpu, err);
4397 err = kvm_set_cr3(vcpu, val);
4398 kvm_complete_insn_gp(vcpu, err);
4401 err = handle_set_cr4(vcpu, val);
4402 kvm_complete_insn_gp(vcpu, err);
4405 u8 cr8_prev = kvm_get_cr8(vcpu);
4406 u8 cr8 = kvm_register_read(vcpu, reg);
4407 err = kvm_set_cr8(vcpu, cr8);
4408 kvm_complete_insn_gp(vcpu, err);
4409 if (irqchip_in_kernel(vcpu->kvm))
4411 if (cr8_prev <= cr8)
4413 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4420 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4421 skip_emulated_instruction(vcpu);
4422 vmx_fpu_activate(vcpu);
4424 case 1: /*mov from cr*/
4427 val = kvm_read_cr3(vcpu);
4428 kvm_register_write(vcpu, reg, val);
4429 trace_kvm_cr_read(cr, val);
4430 skip_emulated_instruction(vcpu);
4433 val = kvm_get_cr8(vcpu);
4434 kvm_register_write(vcpu, reg, val);
4435 trace_kvm_cr_read(cr, val);
4436 skip_emulated_instruction(vcpu);
4441 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4442 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4443 kvm_lmsw(vcpu, val);
4445 skip_emulated_instruction(vcpu);
4450 vcpu->run->exit_reason = 0;
4451 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4452 (int)(exit_qualification >> 4) & 3, cr);
4456 static int handle_dr(struct kvm_vcpu *vcpu)
4458 unsigned long exit_qualification;
4461 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4462 if (!kvm_require_cpl(vcpu, 0))
4464 dr = vmcs_readl(GUEST_DR7);
4467 * As the vm-exit takes precedence over the debug trap, we
4468 * need to emulate the latter, either for the host or the
4469 * guest debugging itself.
4471 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4472 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4473 vcpu->run->debug.arch.dr7 = dr;
4474 vcpu->run->debug.arch.pc =
4475 vmcs_readl(GUEST_CS_BASE) +
4476 vmcs_readl(GUEST_RIP);
4477 vcpu->run->debug.arch.exception = DB_VECTOR;
4478 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4481 vcpu->arch.dr7 &= ~DR7_GD;
4482 vcpu->arch.dr6 |= DR6_BD;
4483 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4484 kvm_queue_exception(vcpu, DB_VECTOR);
4489 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4490 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4491 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4492 if (exit_qualification & TYPE_MOV_FROM_DR) {
4494 if (!kvm_get_dr(vcpu, dr, &val))
4495 kvm_register_write(vcpu, reg, val);
4497 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4498 skip_emulated_instruction(vcpu);
4502 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4504 vmcs_writel(GUEST_DR7, val);
4507 static int handle_cpuid(struct kvm_vcpu *vcpu)
4509 kvm_emulate_cpuid(vcpu);
4513 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4515 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4518 if (vmx_get_msr(vcpu, ecx, &data)) {
4519 trace_kvm_msr_read_ex(ecx);
4520 kvm_inject_gp(vcpu, 0);
4524 trace_kvm_msr_read(ecx, data);
4526 /* FIXME: handling of bits 32:63 of rax, rdx */
4527 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4528 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4529 skip_emulated_instruction(vcpu);
4533 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4535 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4536 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4537 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4539 if (vmx_set_msr(vcpu, ecx, data) != 0) {
4540 trace_kvm_msr_write_ex(ecx, data);
4541 kvm_inject_gp(vcpu, 0);
4545 trace_kvm_msr_write(ecx, data);
4546 skip_emulated_instruction(vcpu);
4550 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4552 kvm_make_request(KVM_REQ_EVENT, vcpu);
4556 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4558 u32 cpu_based_vm_exec_control;
4560 /* clear pending irq */
4561 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4562 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4563 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4565 kvm_make_request(KVM_REQ_EVENT, vcpu);
4567 ++vcpu->stat.irq_window_exits;
4570 * If the user space waits to inject interrupts, exit as soon as
4573 if (!irqchip_in_kernel(vcpu->kvm) &&
4574 vcpu->run->request_interrupt_window &&
4575 !kvm_cpu_has_interrupt(vcpu)) {
4576 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4582 static int handle_halt(struct kvm_vcpu *vcpu)
4584 skip_emulated_instruction(vcpu);
4585 return kvm_emulate_halt(vcpu);
4588 static int handle_vmcall(struct kvm_vcpu *vcpu)
4590 skip_emulated_instruction(vcpu);
4591 kvm_emulate_hypercall(vcpu);
4595 static int handle_invd(struct kvm_vcpu *vcpu)
4597 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4600 static int handle_invlpg(struct kvm_vcpu *vcpu)
4602 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4604 kvm_mmu_invlpg(vcpu, exit_qualification);
4605 skip_emulated_instruction(vcpu);
4609 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4613 err = kvm_rdpmc(vcpu);
4614 kvm_complete_insn_gp(vcpu, err);
4619 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4621 skip_emulated_instruction(vcpu);
4622 kvm_emulate_wbinvd(vcpu);
4626 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4628 u64 new_bv = kvm_read_edx_eax(vcpu);
4629 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4631 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4632 skip_emulated_instruction(vcpu);
4636 static int handle_apic_access(struct kvm_vcpu *vcpu)
4638 if (likely(fasteoi)) {
4639 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4640 int access_type, offset;
4642 access_type = exit_qualification & APIC_ACCESS_TYPE;
4643 offset = exit_qualification & APIC_ACCESS_OFFSET;
4645 * Sane guest uses MOV to write EOI, with written value
4646 * not cared. So make a short-circuit here by avoiding
4647 * heavy instruction emulation.
4649 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4650 (offset == APIC_EOI)) {
4651 kvm_lapic_set_eoi(vcpu);
4652 skip_emulated_instruction(vcpu);
4656 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4659 static int handle_task_switch(struct kvm_vcpu *vcpu)
4661 struct vcpu_vmx *vmx = to_vmx(vcpu);
4662 unsigned long exit_qualification;
4663 bool has_error_code = false;
4666 int reason, type, idt_v, idt_index;
4668 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4669 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4670 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4672 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4674 reason = (u32)exit_qualification >> 30;
4675 if (reason == TASK_SWITCH_GATE && idt_v) {
4677 case INTR_TYPE_NMI_INTR:
4678 vcpu->arch.nmi_injected = false;
4679 vmx_set_nmi_mask(vcpu, true);
4681 case INTR_TYPE_EXT_INTR:
4682 case INTR_TYPE_SOFT_INTR:
4683 kvm_clear_interrupt_queue(vcpu);
4685 case INTR_TYPE_HARD_EXCEPTION:
4686 if (vmx->idt_vectoring_info &
4687 VECTORING_INFO_DELIVER_CODE_MASK) {
4688 has_error_code = true;
4690 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4693 case INTR_TYPE_SOFT_EXCEPTION:
4694 kvm_clear_exception_queue(vcpu);
4700 tss_selector = exit_qualification;
4702 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4703 type != INTR_TYPE_EXT_INTR &&
4704 type != INTR_TYPE_NMI_INTR))
4705 skip_emulated_instruction(vcpu);
4707 if (kvm_task_switch(vcpu, tss_selector,
4708 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4709 has_error_code, error_code) == EMULATE_FAIL) {
4710 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4711 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4712 vcpu->run->internal.ndata = 0;
4716 /* clear all local breakpoint enable flags */
4717 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4720 * TODO: What about debug traps on tss switch?
4721 * Are we supposed to inject them and update dr6?
4727 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4729 unsigned long exit_qualification;
4733 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4735 if (exit_qualification & (1 << 6)) {
4736 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4740 gla_validity = (exit_qualification >> 7) & 0x3;
4741 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4742 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4743 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4744 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4745 vmcs_readl(GUEST_LINEAR_ADDRESS));
4746 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4747 (long unsigned int)exit_qualification);
4748 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4749 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4753 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4754 trace_kvm_page_fault(gpa, exit_qualification);
4755 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4758 static u64 ept_rsvd_mask(u64 spte, int level)
4763 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4764 mask |= (1ULL << i);
4767 /* bits 7:3 reserved */
4769 else if (level == 2) {
4770 if (spte & (1ULL << 7))
4771 /* 2MB ref, bits 20:12 reserved */
4774 /* bits 6:3 reserved */
4781 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4784 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4786 /* 010b (write-only) */
4787 WARN_ON((spte & 0x7) == 0x2);
4789 /* 110b (write/execute) */
4790 WARN_ON((spte & 0x7) == 0x6);
4792 /* 100b (execute-only) and value not supported by logical processor */
4793 if (!cpu_has_vmx_ept_execute_only())
4794 WARN_ON((spte & 0x7) == 0x4);
4798 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4800 if (rsvd_bits != 0) {
4801 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4802 __func__, rsvd_bits);
4806 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4807 u64 ept_mem_type = (spte & 0x38) >> 3;
4809 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4810 ept_mem_type == 7) {
4811 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4812 __func__, ept_mem_type);
4819 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4822 int nr_sptes, i, ret;
4825 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4827 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4828 if (likely(ret == 1))
4829 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4834 /* It is the real ept misconfig */
4835 printk(KERN_ERR "EPT: Misconfiguration.\n");
4836 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4838 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4840 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4841 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4843 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4844 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4849 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4851 u32 cpu_based_vm_exec_control;
4853 /* clear pending NMI */
4854 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4855 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4856 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4857 ++vcpu->stat.nmi_window_exits;
4858 kvm_make_request(KVM_REQ_EVENT, vcpu);
4863 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4865 struct vcpu_vmx *vmx = to_vmx(vcpu);
4866 enum emulation_result err = EMULATE_DONE;
4869 bool intr_window_requested;
4871 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4872 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4874 while (!guest_state_valid(vcpu)) {
4875 if (intr_window_requested
4876 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4877 return handle_interrupt_window(&vmx->vcpu);
4879 err = emulate_instruction(vcpu, 0);
4881 if (err == EMULATE_DO_MMIO) {
4886 if (err != EMULATE_DONE)
4889 if (signal_pending(current))
4895 vmx->emulation_required = 0;
4901 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4902 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4904 static int handle_pause(struct kvm_vcpu *vcpu)
4906 skip_emulated_instruction(vcpu);
4907 kvm_vcpu_on_spin(vcpu);
4912 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4914 kvm_queue_exception(vcpu, UD_VECTOR);
4919 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4920 * We could reuse a single VMCS for all the L2 guests, but we also want the
4921 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4922 * allows keeping them loaded on the processor, and in the future will allow
4923 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4924 * every entry if they never change.
4925 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4926 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4928 * The following functions allocate and free a vmcs02 in this pool.
4931 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4932 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4934 struct vmcs02_list *item;
4935 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4936 if (item->vmptr == vmx->nested.current_vmptr) {
4937 list_move(&item->list, &vmx->nested.vmcs02_pool);
4938 return &item->vmcs02;
4941 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4942 /* Recycle the least recently used VMCS. */
4943 item = list_entry(vmx->nested.vmcs02_pool.prev,
4944 struct vmcs02_list, list);
4945 item->vmptr = vmx->nested.current_vmptr;
4946 list_move(&item->list, &vmx->nested.vmcs02_pool);
4947 return &item->vmcs02;
4950 /* Create a new VMCS */
4951 item = (struct vmcs02_list *)
4952 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4955 item->vmcs02.vmcs = alloc_vmcs();
4956 if (!item->vmcs02.vmcs) {
4960 loaded_vmcs_init(&item->vmcs02);
4961 item->vmptr = vmx->nested.current_vmptr;
4962 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4963 vmx->nested.vmcs02_num++;
4964 return &item->vmcs02;
4967 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4968 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4970 struct vmcs02_list *item;
4971 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4972 if (item->vmptr == vmptr) {
4973 free_loaded_vmcs(&item->vmcs02);
4974 list_del(&item->list);
4976 vmx->nested.vmcs02_num--;
4982 * Free all VMCSs saved for this vcpu, except the one pointed by
4983 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4984 * currently used, if running L2), and vmcs01 when running L2.
4986 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4988 struct vmcs02_list *item, *n;
4989 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4990 if (vmx->loaded_vmcs != &item->vmcs02)
4991 free_loaded_vmcs(&item->vmcs02);
4992 list_del(&item->list);
4995 vmx->nested.vmcs02_num = 0;
4997 if (vmx->loaded_vmcs != &vmx->vmcs01)
4998 free_loaded_vmcs(&vmx->vmcs01);
5002 * Emulate the VMXON instruction.
5003 * Currently, we just remember that VMX is active, and do not save or even
5004 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5005 * do not currently need to store anything in that guest-allocated memory
5006 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5007 * argument is different from the VMXON pointer (which the spec says they do).
5009 static int handle_vmon(struct kvm_vcpu *vcpu)
5011 struct kvm_segment cs;
5012 struct vcpu_vmx *vmx = to_vmx(vcpu);
5014 /* The Intel VMX Instruction Reference lists a bunch of bits that
5015 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5016 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5017 * Otherwise, we should fail with #UD. We test these now:
5019 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5020 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5021 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5022 kvm_queue_exception(vcpu, UD_VECTOR);
5026 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5027 if (is_long_mode(vcpu) && !cs.l) {
5028 kvm_queue_exception(vcpu, UD_VECTOR);
5032 if (vmx_get_cpl(vcpu)) {
5033 kvm_inject_gp(vcpu, 0);
5037 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5038 vmx->nested.vmcs02_num = 0;
5040 vmx->nested.vmxon = true;
5042 skip_emulated_instruction(vcpu);
5047 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5048 * for running VMX instructions (except VMXON, whose prerequisites are
5049 * slightly different). It also specifies what exception to inject otherwise.
5051 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5053 struct kvm_segment cs;
5054 struct vcpu_vmx *vmx = to_vmx(vcpu);
5056 if (!vmx->nested.vmxon) {
5057 kvm_queue_exception(vcpu, UD_VECTOR);
5061 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5062 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5063 (is_long_mode(vcpu) && !cs.l)) {
5064 kvm_queue_exception(vcpu, UD_VECTOR);
5068 if (vmx_get_cpl(vcpu)) {
5069 kvm_inject_gp(vcpu, 0);
5077 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5078 * just stops using VMX.
5080 static void free_nested(struct vcpu_vmx *vmx)
5082 if (!vmx->nested.vmxon)
5084 vmx->nested.vmxon = false;
5085 if (vmx->nested.current_vmptr != -1ull) {
5086 kunmap(vmx->nested.current_vmcs12_page);
5087 nested_release_page(vmx->nested.current_vmcs12_page);
5088 vmx->nested.current_vmptr = -1ull;
5089 vmx->nested.current_vmcs12 = NULL;
5091 /* Unpin physical memory we referred to in current vmcs02 */
5092 if (vmx->nested.apic_access_page) {
5093 nested_release_page(vmx->nested.apic_access_page);
5094 vmx->nested.apic_access_page = 0;
5097 nested_free_all_saved_vmcss(vmx);
5100 /* Emulate the VMXOFF instruction */
5101 static int handle_vmoff(struct kvm_vcpu *vcpu)
5103 if (!nested_vmx_check_permission(vcpu))
5105 free_nested(to_vmx(vcpu));
5106 skip_emulated_instruction(vcpu);
5111 * Decode the memory-address operand of a vmx instruction, as recorded on an
5112 * exit caused by such an instruction (run by a guest hypervisor).
5113 * On success, returns 0. When the operand is invalid, returns 1 and throws
5116 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5117 unsigned long exit_qualification,
5118 u32 vmx_instruction_info, gva_t *ret)
5121 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5122 * Execution", on an exit, vmx_instruction_info holds most of the
5123 * addressing components of the operand. Only the displacement part
5124 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5125 * For how an actual address is calculated from all these components,
5126 * refer to Vol. 1, "Operand Addressing".
5128 int scaling = vmx_instruction_info & 3;
5129 int addr_size = (vmx_instruction_info >> 7) & 7;
5130 bool is_reg = vmx_instruction_info & (1u << 10);
5131 int seg_reg = (vmx_instruction_info >> 15) & 7;
5132 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5133 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5134 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5135 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5138 kvm_queue_exception(vcpu, UD_VECTOR);
5142 /* Addr = segment_base + offset */
5143 /* offset = base + [index * scale] + displacement */
5144 *ret = vmx_get_segment_base(vcpu, seg_reg);
5146 *ret += kvm_register_read(vcpu, base_reg);
5148 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5149 *ret += exit_qualification; /* holds the displacement */
5151 if (addr_size == 1) /* 32 bit */
5155 * TODO: throw #GP (and return 1) in various cases that the VM*
5156 * instructions require it - e.g., offset beyond segment limit,
5157 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5158 * address, and so on. Currently these are not checked.
5164 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5165 * set the success or error code of an emulated VMX instruction, as specified
5166 * by Vol 2B, VMX Instruction Reference, "Conventions".
5168 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5170 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5171 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5172 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5175 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5177 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5178 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5179 X86_EFLAGS_SF | X86_EFLAGS_OF))
5183 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5184 u32 vm_instruction_error)
5186 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5188 * failValid writes the error number to the current VMCS, which
5189 * can't be done there isn't a current VMCS.
5191 nested_vmx_failInvalid(vcpu);
5194 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5195 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5196 X86_EFLAGS_SF | X86_EFLAGS_OF))
5198 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5201 /* Emulate the VMCLEAR instruction */
5202 static int handle_vmclear(struct kvm_vcpu *vcpu)
5204 struct vcpu_vmx *vmx = to_vmx(vcpu);
5207 struct vmcs12 *vmcs12;
5209 struct x86_exception e;
5211 if (!nested_vmx_check_permission(vcpu))
5214 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5215 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5218 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5219 sizeof(vmptr), &e)) {
5220 kvm_inject_page_fault(vcpu, &e);
5224 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5225 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5226 skip_emulated_instruction(vcpu);
5230 if (vmptr == vmx->nested.current_vmptr) {
5231 kunmap(vmx->nested.current_vmcs12_page);
5232 nested_release_page(vmx->nested.current_vmcs12_page);
5233 vmx->nested.current_vmptr = -1ull;
5234 vmx->nested.current_vmcs12 = NULL;
5237 page = nested_get_page(vcpu, vmptr);
5240 * For accurate processor emulation, VMCLEAR beyond available
5241 * physical memory should do nothing at all. However, it is
5242 * possible that a nested vmx bug, not a guest hypervisor bug,
5243 * resulted in this case, so let's shut down before doing any
5246 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5249 vmcs12 = kmap(page);
5250 vmcs12->launch_state = 0;
5252 nested_release_page(page);
5254 nested_free_vmcs02(vmx, vmptr);
5256 skip_emulated_instruction(vcpu);
5257 nested_vmx_succeed(vcpu);
5261 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5263 /* Emulate the VMLAUNCH instruction */
5264 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5266 return nested_vmx_run(vcpu, true);
5269 /* Emulate the VMRESUME instruction */
5270 static int handle_vmresume(struct kvm_vcpu *vcpu)
5273 return nested_vmx_run(vcpu, false);
5276 enum vmcs_field_type {
5277 VMCS_FIELD_TYPE_U16 = 0,
5278 VMCS_FIELD_TYPE_U64 = 1,
5279 VMCS_FIELD_TYPE_U32 = 2,
5280 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5283 static inline int vmcs_field_type(unsigned long field)
5285 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5286 return VMCS_FIELD_TYPE_U32;
5287 return (field >> 13) & 0x3 ;
5290 static inline int vmcs_field_readonly(unsigned long field)
5292 return (((field >> 10) & 0x3) == 1);
5296 * Read a vmcs12 field. Since these can have varying lengths and we return
5297 * one type, we chose the biggest type (u64) and zero-extend the return value
5298 * to that size. Note that the caller, handle_vmread, might need to use only
5299 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5300 * 64-bit fields are to be returned).
5302 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5303 unsigned long field, u64 *ret)
5305 short offset = vmcs_field_to_offset(field);
5311 p = ((char *)(get_vmcs12(vcpu))) + offset;
5313 switch (vmcs_field_type(field)) {
5314 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5315 *ret = *((natural_width *)p);
5317 case VMCS_FIELD_TYPE_U16:
5320 case VMCS_FIELD_TYPE_U32:
5323 case VMCS_FIELD_TYPE_U64:
5327 return 0; /* can never happen. */
5332 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5333 * used before) all generate the same failure when it is missing.
5335 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5337 struct vcpu_vmx *vmx = to_vmx(vcpu);
5338 if (vmx->nested.current_vmptr == -1ull) {
5339 nested_vmx_failInvalid(vcpu);
5340 skip_emulated_instruction(vcpu);
5346 static int handle_vmread(struct kvm_vcpu *vcpu)
5348 unsigned long field;
5350 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5351 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5354 if (!nested_vmx_check_permission(vcpu) ||
5355 !nested_vmx_check_vmcs12(vcpu))
5358 /* Decode instruction info and find the field to read */
5359 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5360 /* Read the field, zero-extended to a u64 field_value */
5361 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5362 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5363 skip_emulated_instruction(vcpu);
5367 * Now copy part of this value to register or memory, as requested.
5368 * Note that the number of bits actually copied is 32 or 64 depending
5369 * on the guest's mode (32 or 64 bit), not on the given field's length.
5371 if (vmx_instruction_info & (1u << 10)) {
5372 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5375 if (get_vmx_mem_address(vcpu, exit_qualification,
5376 vmx_instruction_info, &gva))
5378 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5379 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5380 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5383 nested_vmx_succeed(vcpu);
5384 skip_emulated_instruction(vcpu);
5389 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5391 unsigned long field;
5393 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5394 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5397 /* The value to write might be 32 or 64 bits, depending on L1's long
5398 * mode, and eventually we need to write that into a field of several
5399 * possible lengths. The code below first zero-extends the value to 64
5400 * bit (field_value), and then copies only the approriate number of
5401 * bits into the vmcs12 field.
5403 u64 field_value = 0;
5404 struct x86_exception e;
5406 if (!nested_vmx_check_permission(vcpu) ||
5407 !nested_vmx_check_vmcs12(vcpu))
5410 if (vmx_instruction_info & (1u << 10))
5411 field_value = kvm_register_read(vcpu,
5412 (((vmx_instruction_info) >> 3) & 0xf));
5414 if (get_vmx_mem_address(vcpu, exit_qualification,
5415 vmx_instruction_info, &gva))
5417 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5418 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5419 kvm_inject_page_fault(vcpu, &e);
5425 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5426 if (vmcs_field_readonly(field)) {
5427 nested_vmx_failValid(vcpu,
5428 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5429 skip_emulated_instruction(vcpu);
5433 offset = vmcs_field_to_offset(field);
5435 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5436 skip_emulated_instruction(vcpu);
5439 p = ((char *) get_vmcs12(vcpu)) + offset;
5441 switch (vmcs_field_type(field)) {
5442 case VMCS_FIELD_TYPE_U16:
5443 *(u16 *)p = field_value;
5445 case VMCS_FIELD_TYPE_U32:
5446 *(u32 *)p = field_value;
5448 case VMCS_FIELD_TYPE_U64:
5449 *(u64 *)p = field_value;
5451 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5452 *(natural_width *)p = field_value;
5455 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5456 skip_emulated_instruction(vcpu);
5460 nested_vmx_succeed(vcpu);
5461 skip_emulated_instruction(vcpu);
5465 /* Emulate the VMPTRLD instruction */
5466 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5468 struct vcpu_vmx *vmx = to_vmx(vcpu);
5471 struct x86_exception e;
5473 if (!nested_vmx_check_permission(vcpu))
5476 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5477 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5480 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5481 sizeof(vmptr), &e)) {
5482 kvm_inject_page_fault(vcpu, &e);
5486 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5487 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5488 skip_emulated_instruction(vcpu);
5492 if (vmx->nested.current_vmptr != vmptr) {
5493 struct vmcs12 *new_vmcs12;
5495 page = nested_get_page(vcpu, vmptr);
5497 nested_vmx_failInvalid(vcpu);
5498 skip_emulated_instruction(vcpu);
5501 new_vmcs12 = kmap(page);
5502 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5504 nested_release_page_clean(page);
5505 nested_vmx_failValid(vcpu,
5506 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5507 skip_emulated_instruction(vcpu);
5510 if (vmx->nested.current_vmptr != -1ull) {
5511 kunmap(vmx->nested.current_vmcs12_page);
5512 nested_release_page(vmx->nested.current_vmcs12_page);
5515 vmx->nested.current_vmptr = vmptr;
5516 vmx->nested.current_vmcs12 = new_vmcs12;
5517 vmx->nested.current_vmcs12_page = page;
5520 nested_vmx_succeed(vcpu);
5521 skip_emulated_instruction(vcpu);
5525 /* Emulate the VMPTRST instruction */
5526 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5528 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5529 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5531 struct x86_exception e;
5533 if (!nested_vmx_check_permission(vcpu))
5536 if (get_vmx_mem_address(vcpu, exit_qualification,
5537 vmx_instruction_info, &vmcs_gva))
5539 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5540 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5541 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5543 kvm_inject_page_fault(vcpu, &e);
5546 nested_vmx_succeed(vcpu);
5547 skip_emulated_instruction(vcpu);
5552 * The exit handlers return 1 if the exit was handled fully and guest execution
5553 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5554 * to be done to userspace and return 0.
5556 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5557 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5558 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5559 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5560 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5561 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5562 [EXIT_REASON_CR_ACCESS] = handle_cr,
5563 [EXIT_REASON_DR_ACCESS] = handle_dr,
5564 [EXIT_REASON_CPUID] = handle_cpuid,
5565 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5566 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5567 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5568 [EXIT_REASON_HLT] = handle_halt,
5569 [EXIT_REASON_INVD] = handle_invd,
5570 [EXIT_REASON_INVLPG] = handle_invlpg,
5571 [EXIT_REASON_RDPMC] = handle_rdpmc,
5572 [EXIT_REASON_VMCALL] = handle_vmcall,
5573 [EXIT_REASON_VMCLEAR] = handle_vmclear,
5574 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
5575 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
5576 [EXIT_REASON_VMPTRST] = handle_vmptrst,
5577 [EXIT_REASON_VMREAD] = handle_vmread,
5578 [EXIT_REASON_VMRESUME] = handle_vmresume,
5579 [EXIT_REASON_VMWRITE] = handle_vmwrite,
5580 [EXIT_REASON_VMOFF] = handle_vmoff,
5581 [EXIT_REASON_VMON] = handle_vmon,
5582 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5583 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5584 [EXIT_REASON_WBINVD] = handle_wbinvd,
5585 [EXIT_REASON_XSETBV] = handle_xsetbv,
5586 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5587 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5588 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5589 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5590 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5591 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5592 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
5595 static const int kvm_vmx_max_exit_handlers =
5596 ARRAY_SIZE(kvm_vmx_exit_handlers);
5599 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5600 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5601 * disinterest in the current event (read or write a specific MSR) by using an
5602 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5604 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5605 struct vmcs12 *vmcs12, u32 exit_reason)
5607 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5610 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5614 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5615 * for the four combinations of read/write and low/high MSR numbers.
5616 * First we need to figure out which of the four to use:
5618 bitmap = vmcs12->msr_bitmap;
5619 if (exit_reason == EXIT_REASON_MSR_WRITE)
5621 if (msr_index >= 0xc0000000) {
5622 msr_index -= 0xc0000000;
5626 /* Then read the msr_index'th bit from this bitmap: */
5627 if (msr_index < 1024*8) {
5629 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5630 return 1 & (b >> (msr_index & 7));
5632 return 1; /* let L1 handle the wrong parameter */
5636 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5637 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5638 * intercept (via guest_host_mask etc.) the current event.
5640 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5641 struct vmcs12 *vmcs12)
5643 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5644 int cr = exit_qualification & 15;
5645 int reg = (exit_qualification >> 8) & 15;
5646 unsigned long val = kvm_register_read(vcpu, reg);
5648 switch ((exit_qualification >> 4) & 3) {
5649 case 0: /* mov to cr */
5652 if (vmcs12->cr0_guest_host_mask &
5653 (val ^ vmcs12->cr0_read_shadow))
5657 if ((vmcs12->cr3_target_count >= 1 &&
5658 vmcs12->cr3_target_value0 == val) ||
5659 (vmcs12->cr3_target_count >= 2 &&
5660 vmcs12->cr3_target_value1 == val) ||
5661 (vmcs12->cr3_target_count >= 3 &&
5662 vmcs12->cr3_target_value2 == val) ||
5663 (vmcs12->cr3_target_count >= 4 &&
5664 vmcs12->cr3_target_value3 == val))
5666 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5670 if (vmcs12->cr4_guest_host_mask &
5671 (vmcs12->cr4_read_shadow ^ val))
5675 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5681 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5682 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5685 case 1: /* mov from cr */
5688 if (vmcs12->cpu_based_vm_exec_control &
5689 CPU_BASED_CR3_STORE_EXITING)
5693 if (vmcs12->cpu_based_vm_exec_control &
5694 CPU_BASED_CR8_STORE_EXITING)
5701 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5702 * cr0. Other attempted changes are ignored, with no exit.
5704 if (vmcs12->cr0_guest_host_mask & 0xe &
5705 (val ^ vmcs12->cr0_read_shadow))
5707 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5708 !(vmcs12->cr0_read_shadow & 0x1) &&
5717 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5718 * should handle it ourselves in L0 (and then continue L2). Only call this
5719 * when in is_guest_mode (L2).
5721 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5723 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5724 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5725 struct vcpu_vmx *vmx = to_vmx(vcpu);
5726 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5728 if (vmx->nested.nested_run_pending)
5731 if (unlikely(vmx->fail)) {
5732 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5733 vmcs_read32(VM_INSTRUCTION_ERROR));
5737 switch (exit_reason) {
5738 case EXIT_REASON_EXCEPTION_NMI:
5739 if (!is_exception(intr_info))
5741 else if (is_page_fault(intr_info))
5743 return vmcs12->exception_bitmap &
5744 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5745 case EXIT_REASON_EXTERNAL_INTERRUPT:
5747 case EXIT_REASON_TRIPLE_FAULT:
5749 case EXIT_REASON_PENDING_INTERRUPT:
5750 case EXIT_REASON_NMI_WINDOW:
5752 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5753 * (aka Interrupt Window Exiting) only when L1 turned it on,
5754 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5755 * Same for NMI Window Exiting.
5758 case EXIT_REASON_TASK_SWITCH:
5760 case EXIT_REASON_CPUID:
5762 case EXIT_REASON_HLT:
5763 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5764 case EXIT_REASON_INVD:
5766 case EXIT_REASON_INVLPG:
5767 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5768 case EXIT_REASON_RDPMC:
5769 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5770 case EXIT_REASON_RDTSC:
5771 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5772 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5773 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5774 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5775 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5776 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5778 * VMX instructions trap unconditionally. This allows L1 to
5779 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5782 case EXIT_REASON_CR_ACCESS:
5783 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5784 case EXIT_REASON_DR_ACCESS:
5785 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5786 case EXIT_REASON_IO_INSTRUCTION:
5787 /* TODO: support IO bitmaps */
5789 case EXIT_REASON_MSR_READ:
5790 case EXIT_REASON_MSR_WRITE:
5791 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5792 case EXIT_REASON_INVALID_STATE:
5794 case EXIT_REASON_MWAIT_INSTRUCTION:
5795 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5796 case EXIT_REASON_MONITOR_INSTRUCTION:
5797 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5798 case EXIT_REASON_PAUSE_INSTRUCTION:
5799 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5800 nested_cpu_has2(vmcs12,
5801 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5802 case EXIT_REASON_MCE_DURING_VMENTRY:
5804 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5806 case EXIT_REASON_APIC_ACCESS:
5807 return nested_cpu_has2(vmcs12,
5808 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5809 case EXIT_REASON_EPT_VIOLATION:
5810 case EXIT_REASON_EPT_MISCONFIG:
5812 case EXIT_REASON_WBINVD:
5813 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5814 case EXIT_REASON_XSETBV:
5821 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5823 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5824 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5828 * The guest has exited. See if we can fix it or if we need userspace
5831 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5833 struct vcpu_vmx *vmx = to_vmx(vcpu);
5834 u32 exit_reason = vmx->exit_reason;
5835 u32 vectoring_info = vmx->idt_vectoring_info;
5837 /* If guest state is invalid, start emulating */
5838 if (vmx->emulation_required && emulate_invalid_guest_state)
5839 return handle_invalid_guest_state(vcpu);
5842 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5843 * we did not inject a still-pending event to L1 now because of
5844 * nested_run_pending, we need to re-enable this bit.
5846 if (vmx->nested.nested_run_pending)
5847 kvm_make_request(KVM_REQ_EVENT, vcpu);
5849 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5850 exit_reason == EXIT_REASON_VMRESUME))
5851 vmx->nested.nested_run_pending = 1;
5853 vmx->nested.nested_run_pending = 0;
5855 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5856 nested_vmx_vmexit(vcpu);
5860 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5861 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5862 vcpu->run->fail_entry.hardware_entry_failure_reason
5867 if (unlikely(vmx->fail)) {
5868 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5869 vcpu->run->fail_entry.hardware_entry_failure_reason
5870 = vmcs_read32(VM_INSTRUCTION_ERROR);
5874 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5875 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5876 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5877 exit_reason != EXIT_REASON_TASK_SWITCH))
5878 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5879 "(0x%x) and exit reason is 0x%x\n",
5880 __func__, vectoring_info, exit_reason);
5882 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5883 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5884 get_vmcs12(vcpu), vcpu)))) {
5885 if (vmx_interrupt_allowed(vcpu)) {
5886 vmx->soft_vnmi_blocked = 0;
5887 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5888 vcpu->arch.nmi_pending) {
5890 * This CPU don't support us in finding the end of an
5891 * NMI-blocked window if the guest runs with IRQs
5892 * disabled. So we pull the trigger after 1 s of
5893 * futile waiting, but inform the user about this.
5895 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5896 "state on VCPU %d after 1 s timeout\n",
5897 __func__, vcpu->vcpu_id);
5898 vmx->soft_vnmi_blocked = 0;
5902 if (exit_reason < kvm_vmx_max_exit_handlers
5903 && kvm_vmx_exit_handlers[exit_reason])
5904 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5906 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5907 vcpu->run->hw.hardware_exit_reason = exit_reason;
5912 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5914 if (irr == -1 || tpr < irr) {
5915 vmcs_write32(TPR_THRESHOLD, 0);
5919 vmcs_write32(TPR_THRESHOLD, irr);
5922 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5926 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5927 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5930 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5931 exit_intr_info = vmx->exit_intr_info;
5933 /* Handle machine checks before interrupts are enabled */
5934 if (is_machine_check(exit_intr_info))
5935 kvm_machine_check();
5937 /* We need to handle NMIs before interrupts are enabled */
5938 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5939 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5940 kvm_before_handle_nmi(&vmx->vcpu);
5942 kvm_after_handle_nmi(&vmx->vcpu);
5946 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5951 bool idtv_info_valid;
5953 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5955 if (cpu_has_virtual_nmis()) {
5956 if (vmx->nmi_known_unmasked)
5959 * Can't use vmx->exit_intr_info since we're not sure what
5960 * the exit reason is.
5962 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5963 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5964 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5966 * SDM 3: 27.7.1.2 (September 2008)
5967 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5968 * a guest IRET fault.
5969 * SDM 3: 23.2.2 (September 2008)
5970 * Bit 12 is undefined in any of the following cases:
5971 * If the VM exit sets the valid bit in the IDT-vectoring
5972 * information field.
5973 * If the VM exit is due to a double fault.
5975 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5976 vector != DF_VECTOR && !idtv_info_valid)
5977 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5978 GUEST_INTR_STATE_NMI);
5980 vmx->nmi_known_unmasked =
5981 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5982 & GUEST_INTR_STATE_NMI);
5983 } else if (unlikely(vmx->soft_vnmi_blocked))
5984 vmx->vnmi_blocked_time +=
5985 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5988 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5989 u32 idt_vectoring_info,
5990 int instr_len_field,
5991 int error_code_field)
5995 bool idtv_info_valid;
5997 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5999 vmx->vcpu.arch.nmi_injected = false;
6000 kvm_clear_exception_queue(&vmx->vcpu);
6001 kvm_clear_interrupt_queue(&vmx->vcpu);
6003 if (!idtv_info_valid)
6006 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6008 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6009 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6012 case INTR_TYPE_NMI_INTR:
6013 vmx->vcpu.arch.nmi_injected = true;
6015 * SDM 3: 27.7.1.2 (September 2008)
6016 * Clear bit "block by NMI" before VM entry if a NMI
6019 vmx_set_nmi_mask(&vmx->vcpu, false);
6021 case INTR_TYPE_SOFT_EXCEPTION:
6022 vmx->vcpu.arch.event_exit_inst_len =
6023 vmcs_read32(instr_len_field);
6025 case INTR_TYPE_HARD_EXCEPTION:
6026 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6027 u32 err = vmcs_read32(error_code_field);
6028 kvm_queue_exception_e(&vmx->vcpu, vector, err);
6030 kvm_queue_exception(&vmx->vcpu, vector);
6032 case INTR_TYPE_SOFT_INTR:
6033 vmx->vcpu.arch.event_exit_inst_len =
6034 vmcs_read32(instr_len_field);
6036 case INTR_TYPE_EXT_INTR:
6037 kvm_queue_interrupt(&vmx->vcpu, vector,
6038 type == INTR_TYPE_SOFT_INTR);
6045 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6047 if (is_guest_mode(&vmx->vcpu))
6049 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6050 VM_EXIT_INSTRUCTION_LEN,
6051 IDT_VECTORING_ERROR_CODE);
6054 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6056 if (is_guest_mode(vcpu))
6058 __vmx_complete_interrupts(to_vmx(vcpu),
6059 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6060 VM_ENTRY_INSTRUCTION_LEN,
6061 VM_ENTRY_EXCEPTION_ERROR_CODE);
6063 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6066 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6069 struct perf_guest_switch_msr *msrs;
6071 msrs = perf_guest_get_msrs(&nr_msrs);
6076 for (i = 0; i < nr_msrs; i++)
6077 if (msrs[i].host == msrs[i].guest)
6078 clear_atomic_switch_msr(vmx, msrs[i].msr);
6080 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6084 #ifdef CONFIG_X86_64
6092 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6094 struct vcpu_vmx *vmx = to_vmx(vcpu);
6096 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6097 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6098 if (vmcs12->idt_vectoring_info_field &
6099 VECTORING_INFO_VALID_MASK) {
6100 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6101 vmcs12->idt_vectoring_info_field);
6102 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6103 vmcs12->vm_exit_instruction_len);
6104 if (vmcs12->idt_vectoring_info_field &
6105 VECTORING_INFO_DELIVER_CODE_MASK)
6106 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6107 vmcs12->idt_vectoring_error_code);
6111 /* Record the guest's net vcpu time for enforced NMI injections. */
6112 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6113 vmx->entry_time = ktime_get();
6115 /* Don't enter VMX if guest state is invalid, let the exit handler
6116 start emulation until we arrive back to a valid state */
6117 if (vmx->emulation_required && emulate_invalid_guest_state)
6120 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6121 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6122 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6123 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6125 /* When single-stepping over STI and MOV SS, we must clear the
6126 * corresponding interruptibility bits in the guest state. Otherwise
6127 * vmentry fails as it then expects bit 14 (BS) in pending debug
6128 * exceptions being set, but that's not correct for the guest debugging
6130 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6131 vmx_set_interrupt_shadow(vcpu, 0);
6133 atomic_switch_perf_msrs(vmx);
6135 vmx->__launched = vmx->loaded_vmcs->launched;
6137 /* Store host registers */
6138 "push %%"R"dx; push %%"R"bp;"
6139 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6141 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6143 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6144 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6146 /* Reload cr2 if changed */
6147 "mov %c[cr2](%0), %%"R"ax \n\t"
6148 "mov %%cr2, %%"R"dx \n\t"
6149 "cmp %%"R"ax, %%"R"dx \n\t"
6151 "mov %%"R"ax, %%cr2 \n\t"
6153 /* Check if vmlaunch of vmresume is needed */
6154 "cmpl $0, %c[launched](%0) \n\t"
6155 /* Load guest registers. Don't clobber flags. */
6156 "mov %c[rax](%0), %%"R"ax \n\t"
6157 "mov %c[rbx](%0), %%"R"bx \n\t"
6158 "mov %c[rdx](%0), %%"R"dx \n\t"
6159 "mov %c[rsi](%0), %%"R"si \n\t"
6160 "mov %c[rdi](%0), %%"R"di \n\t"
6161 "mov %c[rbp](%0), %%"R"bp \n\t"
6162 #ifdef CONFIG_X86_64
6163 "mov %c[r8](%0), %%r8 \n\t"
6164 "mov %c[r9](%0), %%r9 \n\t"
6165 "mov %c[r10](%0), %%r10 \n\t"
6166 "mov %c[r11](%0), %%r11 \n\t"
6167 "mov %c[r12](%0), %%r12 \n\t"
6168 "mov %c[r13](%0), %%r13 \n\t"
6169 "mov %c[r14](%0), %%r14 \n\t"
6170 "mov %c[r15](%0), %%r15 \n\t"
6172 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6174 /* Enter guest mode */
6175 "jne .Llaunched \n\t"
6176 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6177 "jmp .Lkvm_vmx_return \n\t"
6178 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6179 ".Lkvm_vmx_return: "
6180 /* Save guest registers, load host registers, keep flags */
6181 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6183 "mov %%"R"ax, %c[rax](%0) \n\t"
6184 "mov %%"R"bx, %c[rbx](%0) \n\t"
6185 "pop"Q" %c[rcx](%0) \n\t"
6186 "mov %%"R"dx, %c[rdx](%0) \n\t"
6187 "mov %%"R"si, %c[rsi](%0) \n\t"
6188 "mov %%"R"di, %c[rdi](%0) \n\t"
6189 "mov %%"R"bp, %c[rbp](%0) \n\t"
6190 #ifdef CONFIG_X86_64
6191 "mov %%r8, %c[r8](%0) \n\t"
6192 "mov %%r9, %c[r9](%0) \n\t"
6193 "mov %%r10, %c[r10](%0) \n\t"
6194 "mov %%r11, %c[r11](%0) \n\t"
6195 "mov %%r12, %c[r12](%0) \n\t"
6196 "mov %%r13, %c[r13](%0) \n\t"
6197 "mov %%r14, %c[r14](%0) \n\t"
6198 "mov %%r15, %c[r15](%0) \n\t"
6200 "mov %%cr2, %%"R"ax \n\t"
6201 "mov %%"R"ax, %c[cr2](%0) \n\t"
6203 "pop %%"R"bp; pop %%"R"dx \n\t"
6204 "setbe %c[fail](%0) \n\t"
6205 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6206 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6207 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6208 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6209 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6210 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6211 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6212 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6213 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6214 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6215 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6216 #ifdef CONFIG_X86_64
6217 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6218 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6219 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6220 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6221 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6222 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6223 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6224 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6226 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6227 [wordsize]"i"(sizeof(ulong))
6229 , R"ax", R"bx", R"di", R"si"
6230 #ifdef CONFIG_X86_64
6231 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6235 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6236 | (1 << VCPU_EXREG_RFLAGS)
6237 | (1 << VCPU_EXREG_CPL)
6238 | (1 << VCPU_EXREG_PDPTR)
6239 | (1 << VCPU_EXREG_SEGMENTS)
6240 | (1 << VCPU_EXREG_CR3));
6241 vcpu->arch.regs_dirty = 0;
6243 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6245 if (is_guest_mode(vcpu)) {
6246 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6247 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6248 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6249 vmcs12->idt_vectoring_error_code =
6250 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6251 vmcs12->vm_exit_instruction_len =
6252 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6256 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6257 vmx->loaded_vmcs->launched = 1;
6259 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6260 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6262 vmx_complete_atomic_exit(vmx);
6263 vmx_recover_nmi_blocking(vmx);
6264 vmx_complete_interrupts(vmx);
6270 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6272 struct vcpu_vmx *vmx = to_vmx(vcpu);
6276 free_loaded_vmcs(vmx->loaded_vmcs);
6277 kfree(vmx->guest_msrs);
6278 kvm_vcpu_uninit(vcpu);
6279 kmem_cache_free(kvm_vcpu_cache, vmx);
6282 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6285 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6289 return ERR_PTR(-ENOMEM);
6293 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6297 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6299 if (!vmx->guest_msrs) {
6303 vmx->loaded_vmcs = &vmx->vmcs01;
6304 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6305 if (!vmx->loaded_vmcs->vmcs)
6308 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6309 loaded_vmcs_init(vmx->loaded_vmcs);
6314 vmx_vcpu_load(&vmx->vcpu, cpu);
6315 vmx->vcpu.cpu = cpu;
6316 err = vmx_vcpu_setup(vmx);
6317 vmx_vcpu_put(&vmx->vcpu);
6321 if (vm_need_virtualize_apic_accesses(kvm))
6322 err = alloc_apic_access_page(kvm);
6327 if (!kvm->arch.ept_identity_map_addr)
6328 kvm->arch.ept_identity_map_addr =
6329 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6331 if (alloc_identity_pagetable(kvm) != 0)
6333 if (!init_rmode_identity_map(kvm))
6337 vmx->nested.current_vmptr = -1ull;
6338 vmx->nested.current_vmcs12 = NULL;
6343 free_vmcs(vmx->loaded_vmcs->vmcs);
6345 kfree(vmx->guest_msrs);
6347 kvm_vcpu_uninit(&vmx->vcpu);
6350 kmem_cache_free(kvm_vcpu_cache, vmx);
6351 return ERR_PTR(err);
6354 static void __init vmx_check_processor_compat(void *rtn)
6356 struct vmcs_config vmcs_conf;
6359 if (setup_vmcs_config(&vmcs_conf) < 0)
6361 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6362 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6363 smp_processor_id());
6368 static int get_ept_level(void)
6370 return VMX_EPT_DEFAULT_GAW + 1;
6373 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6377 /* For VT-d and EPT combination
6378 * 1. MMIO: always map as UC
6380 * a. VT-d without snooping control feature: can't guarantee the
6381 * result, try to trust guest.
6382 * b. VT-d with snooping control feature: snooping control feature of
6383 * VT-d engine can guarantee the cache correctness. Just set it
6384 * to WB to keep consistent with host. So the same as item 3.
6385 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6386 * consistent with host MTRR
6389 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6390 else if (vcpu->kvm->arch.iommu_domain &&
6391 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6392 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6393 VMX_EPT_MT_EPTE_SHIFT;
6395 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6401 static int vmx_get_lpage_level(void)
6403 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6404 return PT_DIRECTORY_LEVEL;
6406 /* For shadow and EPT supported 1GB page */
6407 return PT_PDPE_LEVEL;
6410 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6412 struct kvm_cpuid_entry2 *best;
6413 struct vcpu_vmx *vmx = to_vmx(vcpu);
6416 vmx->rdtscp_enabled = false;
6417 if (vmx_rdtscp_supported()) {
6418 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6419 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6420 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6421 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6422 vmx->rdtscp_enabled = true;
6424 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6425 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6432 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6434 if (func == 1 && nested)
6435 entry->ecx |= bit(X86_FEATURE_VMX);
6439 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6440 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6441 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6442 * guest in a way that will both be appropriate to L1's requests, and our
6443 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6444 * function also has additional necessary side-effects, like setting various
6445 * vcpu->arch fields.
6447 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6449 struct vcpu_vmx *vmx = to_vmx(vcpu);
6452 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6453 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6454 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6455 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6456 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6457 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6458 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6459 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6460 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6461 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6462 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6463 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6464 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6465 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6466 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6467 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6468 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6469 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6470 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6471 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6472 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6473 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6474 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6475 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6476 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6477 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6478 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6479 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6480 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6481 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6482 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6483 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6484 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6485 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6486 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6487 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6489 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6490 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6491 vmcs12->vm_entry_intr_info_field);
6492 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6493 vmcs12->vm_entry_exception_error_code);
6494 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6495 vmcs12->vm_entry_instruction_len);
6496 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6497 vmcs12->guest_interruptibility_info);
6498 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6499 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6500 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6501 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6502 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6503 vmcs12->guest_pending_dbg_exceptions);
6504 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6505 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6507 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6509 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6510 (vmcs_config.pin_based_exec_ctrl |
6511 vmcs12->pin_based_vm_exec_control));
6514 * Whether page-faults are trapped is determined by a combination of
6515 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6516 * If enable_ept, L0 doesn't care about page faults and we should
6517 * set all of these to L1's desires. However, if !enable_ept, L0 does
6518 * care about (at least some) page faults, and because it is not easy
6519 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6520 * to exit on each and every L2 page fault. This is done by setting
6521 * MASK=MATCH=0 and (see below) EB.PF=1.
6522 * Note that below we don't need special code to set EB.PF beyond the
6523 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6524 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6525 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6527 * A problem with this approach (when !enable_ept) is that L1 may be
6528 * injected with more page faults than it asked for. This could have
6529 * caused problems, but in practice existing hypervisors don't care.
6530 * To fix this, we will need to emulate the PFEC checking (on the L1
6531 * page tables), using walk_addr(), when injecting PFs to L1.
6533 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6534 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6535 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6536 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6538 if (cpu_has_secondary_exec_ctrls()) {
6539 u32 exec_control = vmx_secondary_exec_control(vmx);
6540 if (!vmx->rdtscp_enabled)
6541 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6542 /* Take the following fields only from vmcs12 */
6543 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6544 if (nested_cpu_has(vmcs12,
6545 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6546 exec_control |= vmcs12->secondary_vm_exec_control;
6548 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6550 * Translate L1 physical address to host physical
6551 * address for vmcs02. Keep the page pinned, so this
6552 * physical address remains valid. We keep a reference
6553 * to it so we can release it later.
6555 if (vmx->nested.apic_access_page) /* shouldn't happen */
6556 nested_release_page(vmx->nested.apic_access_page);
6557 vmx->nested.apic_access_page =
6558 nested_get_page(vcpu, vmcs12->apic_access_addr);
6560 * If translation failed, no matter: This feature asks
6561 * to exit when accessing the given address, and if it
6562 * can never be accessed, this feature won't do
6565 if (!vmx->nested.apic_access_page)
6567 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6569 vmcs_write64(APIC_ACCESS_ADDR,
6570 page_to_phys(vmx->nested.apic_access_page));
6573 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6578 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6579 * Some constant fields are set here by vmx_set_constant_host_state().
6580 * Other fields are different per CPU, and will be set later when
6581 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6583 vmx_set_constant_host_state();
6586 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6587 * entry, but only if the current (host) sp changed from the value
6588 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6589 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6590 * here we just force the write to happen on entry.
6594 exec_control = vmx_exec_control(vmx); /* L0's desires */
6595 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6596 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6597 exec_control &= ~CPU_BASED_TPR_SHADOW;
6598 exec_control |= vmcs12->cpu_based_vm_exec_control;
6600 * Merging of IO and MSR bitmaps not currently supported.
6601 * Rather, exit every time.
6603 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6604 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6605 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6607 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6609 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6610 * bitwise-or of what L1 wants to trap for L2, and what we want to
6611 * trap. Note that CR0.TS also needs updating - we do this later.
6613 update_exception_bitmap(vcpu);
6614 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6615 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6617 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6618 vmcs_write32(VM_EXIT_CONTROLS,
6619 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6620 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6621 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6623 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6624 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6625 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6626 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6629 set_cr4_guest_host_mask(vmx);
6631 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6632 vmcs_write64(TSC_OFFSET,
6633 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6635 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6639 * Trivially support vpid by letting L2s share their parent
6640 * L1's vpid. TODO: move to a more elaborate solution, giving
6641 * each L2 its own vpid and exposing the vpid feature to L1.
6643 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6644 vmx_flush_tlb(vcpu);
6647 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6648 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6649 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6650 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6652 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6653 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6654 vmx_set_efer(vcpu, vcpu->arch.efer);
6657 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6658 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6659 * The CR0_READ_SHADOW is what L2 should have expected to read given
6660 * the specifications by L1; It's not enough to take
6661 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6662 * have more bits than L1 expected.
6664 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6665 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6667 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6668 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6670 /* shadow page tables on either EPT or shadow page tables */
6671 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6672 kvm_mmu_reset_context(vcpu);
6674 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6675 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6679 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6680 * for running an L2 nested guest.
6682 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6684 struct vmcs12 *vmcs12;
6685 struct vcpu_vmx *vmx = to_vmx(vcpu);
6687 struct loaded_vmcs *vmcs02;
6689 if (!nested_vmx_check_permission(vcpu) ||
6690 !nested_vmx_check_vmcs12(vcpu))
6693 skip_emulated_instruction(vcpu);
6694 vmcs12 = get_vmcs12(vcpu);
6697 * The nested entry process starts with enforcing various prerequisites
6698 * on vmcs12 as required by the Intel SDM, and act appropriately when
6699 * they fail: As the SDM explains, some conditions should cause the
6700 * instruction to fail, while others will cause the instruction to seem
6701 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6702 * To speed up the normal (success) code path, we should avoid checking
6703 * for misconfigurations which will anyway be caught by the processor
6704 * when using the merged vmcs02.
6706 if (vmcs12->launch_state == launch) {
6707 nested_vmx_failValid(vcpu,
6708 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6709 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6713 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6714 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6715 /*TODO: Also verify bits beyond physical address width are 0*/
6716 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6720 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6721 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6722 /*TODO: Also verify bits beyond physical address width are 0*/
6723 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6727 if (vmcs12->vm_entry_msr_load_count > 0 ||
6728 vmcs12->vm_exit_msr_load_count > 0 ||
6729 vmcs12->vm_exit_msr_store_count > 0) {
6730 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6732 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6736 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6737 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6738 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6739 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6740 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6741 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6742 !vmx_control_verify(vmcs12->vm_exit_controls,
6743 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6744 !vmx_control_verify(vmcs12->vm_entry_controls,
6745 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6747 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6751 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6752 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6753 nested_vmx_failValid(vcpu,
6754 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6758 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6759 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6760 nested_vmx_entry_failure(vcpu, vmcs12,
6761 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6764 if (vmcs12->vmcs_link_pointer != -1ull) {
6765 nested_vmx_entry_failure(vcpu, vmcs12,
6766 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6771 * We're finally done with prerequisite checking, and can start with
6775 vmcs02 = nested_get_current_vmcs02(vmx);
6779 enter_guest_mode(vcpu);
6781 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6784 vmx->loaded_vmcs = vmcs02;
6786 vmx_vcpu_load(vcpu, cpu);
6790 vmcs12->launch_state = 1;
6792 prepare_vmcs02(vcpu, vmcs12);
6795 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6796 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6797 * returned as far as L1 is concerned. It will only return (and set
6798 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6804 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6805 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6806 * This function returns the new value we should put in vmcs12.guest_cr0.
6807 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6808 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6809 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6810 * didn't trap the bit, because if L1 did, so would L0).
6811 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6812 * been modified by L2, and L1 knows it. So just leave the old value of
6813 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6814 * isn't relevant, because if L0 traps this bit it can set it to anything.
6815 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6816 * changed these bits, and therefore they need to be updated, but L0
6817 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6818 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6820 static inline unsigned long
6821 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6824 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6825 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6826 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6827 vcpu->arch.cr0_guest_owned_bits));
6830 static inline unsigned long
6831 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6834 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6835 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6836 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6837 vcpu->arch.cr4_guest_owned_bits));
6841 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6842 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6843 * and this function updates it to reflect the changes to the guest state while
6844 * L2 was running (and perhaps made some exits which were handled directly by L0
6845 * without going back to L1), and to reflect the exit reason.
6846 * Note that we do not have to copy here all VMCS fields, just those that
6847 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6848 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6849 * which already writes to vmcs12 directly.
6851 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6853 /* update guest state fields: */
6854 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6855 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6857 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6858 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6859 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6860 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6862 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6863 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6864 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6865 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6866 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6867 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6868 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6869 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6870 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6871 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6872 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6873 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6874 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6875 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6876 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6877 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6878 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6879 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6880 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6881 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6882 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6883 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6884 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6885 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6886 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6887 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6888 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6889 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6890 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6891 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6892 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6893 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6894 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6895 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6896 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6897 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6899 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6900 vmcs12->guest_interruptibility_info =
6901 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6902 vmcs12->guest_pending_dbg_exceptions =
6903 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6905 /* TODO: These cannot have changed unless we have MSR bitmaps and
6906 * the relevant bit asks not to trap the change */
6907 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6908 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6909 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6910 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6911 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6912 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6914 /* update exit information fields: */
6916 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6917 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6919 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6920 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6921 vmcs12->idt_vectoring_info_field =
6922 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6923 vmcs12->idt_vectoring_error_code =
6924 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6925 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6926 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6928 /* clear vm-entry fields which are to be cleared on exit */
6929 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6930 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6934 * A part of what we need to when the nested L2 guest exits and we want to
6935 * run its L1 parent, is to reset L1's guest state to the host state specified
6937 * This function is to be called not only on normal nested exit, but also on
6938 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6939 * Failures During or After Loading Guest State").
6940 * This function should be called when the active VMCS is L1's (vmcs01).
6942 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6944 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6945 vcpu->arch.efer = vmcs12->host_ia32_efer;
6946 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6947 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6949 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6950 vmx_set_efer(vcpu, vcpu->arch.efer);
6952 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6953 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6955 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6956 * actually changed, because it depends on the current state of
6957 * fpu_active (which may have changed).
6958 * Note that vmx_set_cr0 refers to efer set above.
6960 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6962 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6963 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6964 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6966 update_exception_bitmap(vcpu);
6967 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6968 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6971 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6972 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6974 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6975 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6977 /* shadow page tables on either EPT or shadow page tables */
6978 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6979 kvm_mmu_reset_context(vcpu);
6983 * Trivially support vpid by letting L2s share their parent
6984 * L1's vpid. TODO: move to a more elaborate solution, giving
6985 * each L2 its own vpid and exposing the vpid feature to L1.
6987 vmx_flush_tlb(vcpu);
6991 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6992 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6993 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6994 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6995 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6996 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6997 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6998 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6999 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7000 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7001 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7002 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7003 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7004 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7005 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7007 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7008 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7009 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7010 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7011 vmcs12->host_ia32_perf_global_ctrl);
7015 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7016 * and modify vmcs12 to make it see what it would expect to see there if
7017 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7019 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7021 struct vcpu_vmx *vmx = to_vmx(vcpu);
7023 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7025 leave_guest_mode(vcpu);
7026 prepare_vmcs12(vcpu, vmcs12);
7029 vmx->loaded_vmcs = &vmx->vmcs01;
7031 vmx_vcpu_load(vcpu, cpu);
7035 /* if no vmcs02 cache requested, remove the one we used */
7036 if (VMCS02_POOL_SIZE == 0)
7037 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7039 load_vmcs12_host_state(vcpu, vmcs12);
7041 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7042 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7044 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7047 /* Unpin physical memory we referred to in vmcs02 */
7048 if (vmx->nested.apic_access_page) {
7049 nested_release_page(vmx->nested.apic_access_page);
7050 vmx->nested.apic_access_page = 0;
7054 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7055 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7056 * success or failure flag accordingly.
7058 if (unlikely(vmx->fail)) {
7060 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7062 nested_vmx_succeed(vcpu);
7066 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7067 * 23.7 "VM-entry failures during or after loading guest state" (this also
7068 * lists the acceptable exit-reason and exit-qualification parameters).
7069 * It should only be called before L2 actually succeeded to run, and when
7070 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7072 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7073 struct vmcs12 *vmcs12,
7074 u32 reason, unsigned long qualification)
7076 load_vmcs12_host_state(vcpu, vmcs12);
7077 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7078 vmcs12->exit_qualification = qualification;
7079 nested_vmx_succeed(vcpu);
7082 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7083 struct x86_instruction_info *info,
7084 enum x86_intercept_stage stage)
7086 return X86EMUL_CONTINUE;
7089 static struct kvm_x86_ops vmx_x86_ops = {
7090 .cpu_has_kvm_support = cpu_has_kvm_support,
7091 .disabled_by_bios = vmx_disabled_by_bios,
7092 .hardware_setup = hardware_setup,
7093 .hardware_unsetup = hardware_unsetup,
7094 .check_processor_compatibility = vmx_check_processor_compat,
7095 .hardware_enable = hardware_enable,
7096 .hardware_disable = hardware_disable,
7097 .cpu_has_accelerated_tpr = report_flexpriority,
7099 .vcpu_create = vmx_create_vcpu,
7100 .vcpu_free = vmx_free_vcpu,
7101 .vcpu_reset = vmx_vcpu_reset,
7103 .prepare_guest_switch = vmx_save_host_state,
7104 .vcpu_load = vmx_vcpu_load,
7105 .vcpu_put = vmx_vcpu_put,
7107 .set_guest_debug = set_guest_debug,
7108 .get_msr = vmx_get_msr,
7109 .set_msr = vmx_set_msr,
7110 .get_segment_base = vmx_get_segment_base,
7111 .get_segment = vmx_get_segment,
7112 .set_segment = vmx_set_segment,
7113 .get_cpl = vmx_get_cpl,
7114 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7115 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7116 .decache_cr3 = vmx_decache_cr3,
7117 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7118 .set_cr0 = vmx_set_cr0,
7119 .set_cr3 = vmx_set_cr3,
7120 .set_cr4 = vmx_set_cr4,
7121 .set_efer = vmx_set_efer,
7122 .get_idt = vmx_get_idt,
7123 .set_idt = vmx_set_idt,
7124 .get_gdt = vmx_get_gdt,
7125 .set_gdt = vmx_set_gdt,
7126 .set_dr7 = vmx_set_dr7,
7127 .cache_reg = vmx_cache_reg,
7128 .get_rflags = vmx_get_rflags,
7129 .set_rflags = vmx_set_rflags,
7130 .fpu_activate = vmx_fpu_activate,
7131 .fpu_deactivate = vmx_fpu_deactivate,
7133 .tlb_flush = vmx_flush_tlb,
7135 .run = vmx_vcpu_run,
7136 .handle_exit = vmx_handle_exit,
7137 .skip_emulated_instruction = skip_emulated_instruction,
7138 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7139 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7140 .patch_hypercall = vmx_patch_hypercall,
7141 .set_irq = vmx_inject_irq,
7142 .set_nmi = vmx_inject_nmi,
7143 .queue_exception = vmx_queue_exception,
7144 .cancel_injection = vmx_cancel_injection,
7145 .interrupt_allowed = vmx_interrupt_allowed,
7146 .nmi_allowed = vmx_nmi_allowed,
7147 .get_nmi_mask = vmx_get_nmi_mask,
7148 .set_nmi_mask = vmx_set_nmi_mask,
7149 .enable_nmi_window = enable_nmi_window,
7150 .enable_irq_window = enable_irq_window,
7151 .update_cr8_intercept = update_cr8_intercept,
7153 .set_tss_addr = vmx_set_tss_addr,
7154 .get_tdp_level = get_ept_level,
7155 .get_mt_mask = vmx_get_mt_mask,
7157 .get_exit_info = vmx_get_exit_info,
7159 .get_lpage_level = vmx_get_lpage_level,
7161 .cpuid_update = vmx_cpuid_update,
7163 .rdtscp_supported = vmx_rdtscp_supported,
7165 .set_supported_cpuid = vmx_set_supported_cpuid,
7167 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7169 .set_tsc_khz = vmx_set_tsc_khz,
7170 .write_tsc_offset = vmx_write_tsc_offset,
7171 .adjust_tsc_offset = vmx_adjust_tsc_offset,
7172 .compute_tsc_offset = vmx_compute_tsc_offset,
7173 .read_l1_tsc = vmx_read_l1_tsc,
7175 .set_tdp_cr3 = vmx_set_cr3,
7177 .check_intercept = vmx_check_intercept,
7180 static int __init vmx_init(void)
7184 rdmsrl_safe(MSR_EFER, &host_efer);
7186 for (i = 0; i < NR_VMX_MSR; ++i)
7187 kvm_define_shared_msr(i, vmx_msr_index[i]);
7189 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7190 if (!vmx_io_bitmap_a)
7193 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7194 if (!vmx_io_bitmap_b) {
7199 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7200 if (!vmx_msr_bitmap_legacy) {
7205 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7206 if (!vmx_msr_bitmap_longmode) {
7212 * Allow direct access to the PC debug port (it is often used for I/O
7213 * delays, but the vmexits simply slow things down).
7215 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7216 clear_bit(0x80, vmx_io_bitmap_a);
7218 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7220 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7221 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7223 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7225 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7226 __alignof__(struct vcpu_vmx), THIS_MODULE);
7230 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7231 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7232 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7233 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7234 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7235 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7238 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7239 VMX_EPT_EXECUTABLE_MASK);
7240 ept_set_mmio_spte_mask();
7248 free_page((unsigned long)vmx_msr_bitmap_longmode);
7250 free_page((unsigned long)vmx_msr_bitmap_legacy);
7252 free_page((unsigned long)vmx_io_bitmap_b);
7254 free_page((unsigned long)vmx_io_bitmap_a);
7258 static void __exit vmx_exit(void)
7260 free_page((unsigned long)vmx_msr_bitmap_legacy);
7261 free_page((unsigned long)vmx_msr_bitmap_longmode);
7262 free_page((unsigned long)vmx_io_bitmap_b);
7263 free_page((unsigned long)vmx_io_bitmap_a);
7268 module_init(vmx_init)
7269 module_exit(vmx_exit)