arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/ftrace_event.h>
  31 #include <linux/slab.h>
  32 #include <linux/tboot.h>
  33 #include "kvm_cache_regs.h"
  34 #include "x86.h"
  35
  36 #include <asm/io.h>
  37 #include <asm/desc.h>
  38 #include <asm/vmx.h>
  39 #include <asm/virtext.h>
  40 #include <asm/mce.h>
  41 #include <asm/i387.h>
  42 #include <asm/xcr.h>
  43 #include <asm/perf_event.h>
  44
  45 #include "trace.h"
  46
  47 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  48 #define __ex_clear(x, reg) \
  49         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  50
  51 MODULE_AUTHOR("Qumranet");
  52 MODULE_LICENSE("GPL");
  53
  54 static bool __read_mostly enable_vpid = 1;
  55 module_param_named(vpid, enable_vpid, bool, 0444);
  56
  57 static bool __read_mostly flexpriority_enabled = 1;
  58 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  59
  60 static bool __read_mostly enable_ept = 1;
  61 module_param_named(ept, enable_ept, bool, S_IRUGO);
  62
  63 static bool __read_mostly enable_unrestricted_guest = 1;
  64 module_param_named(unrestricted_guest,
  65                         enable_unrestricted_guest, bool, S_IRUGO);
  66
  67 static bool __read_mostly emulate_invalid_guest_state = 0;
  68 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  69
  70 static bool __read_mostly vmm_exclusive = 1;
  71 module_param(vmm_exclusive, bool, S_IRUGO);
  72
  73 static bool __read_mostly fasteoi = 1;
  74 module_param(fasteoi, bool, S_IRUGO);
  75
  76 /*
  77  * If nested=1, nested virtualization is supported, i.e., guests may use
  78  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  79  * use VMX instructions.
  80  */
  81 static bool __read_mostly nested = 0;
  82 module_param(nested, bool, S_IRUGO);
  83
  84 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  85         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  86 #define KVM_GUEST_CR0_MASK                                              \
  87         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  88 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  89         (X86_CR0_WP | X86_CR0_NE)
  90 #define KVM_VM_CR0_ALWAYS_ON                                            \
  91         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  92 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  93         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  94          | X86_CR4_OSXMMEXCPT)
  95
  96 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  97 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  98
  99 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 100
 101 /*
 102  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 103  * ple_gap:    upper bound on the amount of time between two successive
 104  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 105  *             According to test, this time is usually smaller than 128 cycles.
 106  * ple_window: upper bound on the amount of time a guest is allowed to execute
 107  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 108  *             less than 2^12 cycles
 109  * Time is measured based on a counter that runs at the same rate as the TSC,
 110  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 111  */
 112 #define KVM_VMX_DEFAULT_PLE_GAP    128
 113 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 114 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 115 module_param(ple_gap, int, S_IRUGO);
 116
 117 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 118 module_param(ple_window, int, S_IRUGO);
 119
 120 #define NR_AUTOLOAD_MSRS 8
 121 #define VMCS02_POOL_SIZE 1
 122
 123 struct vmcs {
 124         u32 revision_id;
 125         u32 abort;
 126         char data[0];
 127 };
 128
 129 /*
 130  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 131  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 132  * loaded on this CPU (so we can clear them if the CPU goes down).
 133  */
 134 struct loaded_vmcs {
 135         struct vmcs *vmcs;
 136         int cpu;
 137         int launched;
 138         struct list_head loaded_vmcss_on_cpu_link;
 139 };
 140
 141 struct shared_msr_entry {
 142         unsigned index;
 143         u64 data;
 144         u64 mask;
 145 };
 146
 147 /*
 148  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 149  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 150  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 151  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 152  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 153  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 154  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 155  * underlying hardware which will be used to run L2.
 156  * This structure is packed to ensure that its layout is identical across
 157  * machines (necessary for live migration).
 158  * If there are changes in this struct, VMCS12_REVISION must be changed.
 159  */
 160 typedef u64 natural_width;
 161 struct __packed vmcs12 {
 162         /* According to the Intel spec, a VMCS region must start with the
 163          * following two fields. Then follow implementation-specific data.
 164          */
 165         u32 revision_id;
 166         u32 abort;
 167
 168         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 169         u32 padding[7]; /* room for future expansion */
 170
 171         u64 io_bitmap_a;
 172         u64 io_bitmap_b;
 173         u64 msr_bitmap;
 174         u64 vm_exit_msr_store_addr;
 175         u64 vm_exit_msr_load_addr;
 176         u64 vm_entry_msr_load_addr;
 177         u64 tsc_offset;
 178         u64 virtual_apic_page_addr;
 179         u64 apic_access_addr;
 180         u64 ept_pointer;
 181         u64 guest_physical_address;
 182         u64 vmcs_link_pointer;
 183         u64 guest_ia32_debugctl;
 184         u64 guest_ia32_pat;
 185         u64 guest_ia32_efer;
 186         u64 guest_ia32_perf_global_ctrl;
 187         u64 guest_pdptr0;
 188         u64 guest_pdptr1;
 189         u64 guest_pdptr2;
 190         u64 guest_pdptr3;
 191         u64 host_ia32_pat;
 192         u64 host_ia32_efer;
 193         u64 host_ia32_perf_global_ctrl;
 194         u64 padding64[8]; /* room for future expansion */
 195         /*
 196          * To allow migration of L1 (complete with its L2 guests) between
 197          * machines of different natural widths (32 or 64 bit), we cannot have
 198          * unsigned long fields with no explict size. We use u64 (aliased
 199          * natural_width) instead. Luckily, x86 is little-endian.
 200          */
 201         natural_width cr0_guest_host_mask;
 202         natural_width cr4_guest_host_mask;
 203         natural_width cr0_read_shadow;
 204         natural_width cr4_read_shadow;
 205         natural_width cr3_target_value0;
 206         natural_width cr3_target_value1;
 207         natural_width cr3_target_value2;
 208         natural_width cr3_target_value3;
 209         natural_width exit_qualification;
 210         natural_width guest_linear_address;
 211         natural_width guest_cr0;
 212         natural_width guest_cr3;
 213         natural_width guest_cr4;
 214         natural_width guest_es_base;
 215         natural_width guest_cs_base;
 216         natural_width guest_ss_base;
 217         natural_width guest_ds_base;
 218         natural_width guest_fs_base;
 219         natural_width guest_gs_base;
 220         natural_width guest_ldtr_base;
 221         natural_width guest_tr_base;
 222         natural_width guest_gdtr_base;
 223         natural_width guest_idtr_base;
 224         natural_width guest_dr7;
 225         natural_width guest_rsp;
 226         natural_width guest_rip;
 227         natural_width guest_rflags;
 228         natural_width guest_pending_dbg_exceptions;
 229         natural_width guest_sysenter_esp;
 230         natural_width guest_sysenter_eip;
 231         natural_width host_cr0;
 232         natural_width host_cr3;
 233         natural_width host_cr4;
 234         natural_width host_fs_base;
 235         natural_width host_gs_base;
 236         natural_width host_tr_base;
 237         natural_width host_gdtr_base;
 238         natural_width host_idtr_base;
 239         natural_width host_ia32_sysenter_esp;
 240         natural_width host_ia32_sysenter_eip;
 241         natural_width host_rsp;
 242         natural_width host_rip;
 243         natural_width paddingl[8]; /* room for future expansion */
 244         u32 pin_based_vm_exec_control;
 245         u32 cpu_based_vm_exec_control;
 246         u32 exception_bitmap;
 247         u32 page_fault_error_code_mask;
 248         u32 page_fault_error_code_match;
 249         u32 cr3_target_count;
 250         u32 vm_exit_controls;
 251         u32 vm_exit_msr_store_count;
 252         u32 vm_exit_msr_load_count;
 253         u32 vm_entry_controls;
 254         u32 vm_entry_msr_load_count;
 255         u32 vm_entry_intr_info_field;
 256         u32 vm_entry_exception_error_code;
 257         u32 vm_entry_instruction_len;
 258         u32 tpr_threshold;
 259         u32 secondary_vm_exec_control;
 260         u32 vm_instruction_error;
 261         u32 vm_exit_reason;
 262         u32 vm_exit_intr_info;
 263         u32 vm_exit_intr_error_code;
 264         u32 idt_vectoring_info_field;
 265         u32 idt_vectoring_error_code;
 266         u32 vm_exit_instruction_len;
 267         u32 vmx_instruction_info;
 268         u32 guest_es_limit;
 269         u32 guest_cs_limit;
 270         u32 guest_ss_limit;
 271         u32 guest_ds_limit;
 272         u32 guest_fs_limit;
 273         u32 guest_gs_limit;
 274         u32 guest_ldtr_limit;
 275         u32 guest_tr_limit;
 276         u32 guest_gdtr_limit;
 277         u32 guest_idtr_limit;
 278         u32 guest_es_ar_bytes;
 279         u32 guest_cs_ar_bytes;
 280         u32 guest_ss_ar_bytes;
 281         u32 guest_ds_ar_bytes;
 282         u32 guest_fs_ar_bytes;
 283         u32 guest_gs_ar_bytes;
 284         u32 guest_ldtr_ar_bytes;
 285         u32 guest_tr_ar_bytes;
 286         u32 guest_interruptibility_info;
 287         u32 guest_activity_state;
 288         u32 guest_sysenter_cs;
 289         u32 host_ia32_sysenter_cs;
 290         u32 padding32[8]; /* room for future expansion */
 291         u16 virtual_processor_id;
 292         u16 guest_es_selector;
 293         u16 guest_cs_selector;
 294         u16 guest_ss_selector;
 295         u16 guest_ds_selector;
 296         u16 guest_fs_selector;
 297         u16 guest_gs_selector;
 298         u16 guest_ldtr_selector;
 299         u16 guest_tr_selector;
 300         u16 host_es_selector;
 301         u16 host_cs_selector;
 302         u16 host_ss_selector;
 303         u16 host_ds_selector;
 304         u16 host_fs_selector;
 305         u16 host_gs_selector;
 306         u16 host_tr_selector;
 307 };
 308
 309 /*
 310  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 311  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 312  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 313  */
 314 #define VMCS12_REVISION 0x11e57ed0
 315
 316 /*
 317  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 318  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 319  * current implementation, 4K are reserved to avoid future complications.
 320  */
 321 #define VMCS12_SIZE 0x1000
 322
 323 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 324 struct vmcs02_list {
 325         struct list_head list;
 326         gpa_t vmptr;
 327         struct loaded_vmcs vmcs02;
 328 };
 329
 330 /*
 331  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 332  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 333  */
 334 struct nested_vmx {
 335         /* Has the level1 guest done vmxon? */
 336         bool vmxon;
 337
 338         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 339         gpa_t current_vmptr;
 340         /* The host-usable pointer to the above */
 341         struct page *current_vmcs12_page;
 342         struct vmcs12 *current_vmcs12;
 343
 344         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 345         struct list_head vmcs02_pool;
 346         int vmcs02_num;
 347         u64 vmcs01_tsc_offset;
 348         /* L2 must run next, and mustn't decide to exit to L1. */
 349         bool nested_run_pending;
 350         /*
 351          * Guest pages referred to in vmcs02 with host-physical pointers, so
 352          * we must keep them pinned while L2 runs.
 353          */
 354         struct page *apic_access_page;
 355 };
 356
 357 struct vcpu_vmx {
 358         struct kvm_vcpu       vcpu;
 359         unsigned long         host_rsp;
 360         u8                    fail;
 361         u8                    cpl;
 362         bool                  nmi_known_unmasked;
 363         u32                   exit_intr_info;
 364         u32                   idt_vectoring_info;
 365         ulong                 rflags;
 366         struct shared_msr_entry *guest_msrs;
 367         int                   nmsrs;
 368         int                   save_nmsrs;
 369 #ifdef CONFIG_X86_64
 370         u64                   msr_host_kernel_gs_base;
 371         u64                   msr_guest_kernel_gs_base;
 372 #endif
 373         /*
 374          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 375          * non-nested (L1) guest, it always points to vmcs01. For a nested
 376          * guest (L2), it points to a different VMCS.
 377          */
 378         struct loaded_vmcs    vmcs01;
 379         struct loaded_vmcs   *loaded_vmcs;
 380         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 381         struct msr_autoload {
 382                 unsigned nr;
 383                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 384                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 385         } msr_autoload;
 386         struct {
 387                 int           loaded;
 388                 u16           fs_sel, gs_sel, ldt_sel;
 389                 int           gs_ldt_reload_needed;
 390                 int           fs_reload_needed;
 391         } host_state;
 392         struct {
 393                 int vm86_active;
 394                 ulong save_rflags;
 395                 struct kvm_save_segment {
 396                         u16 selector;
 397                         unsigned long base;
 398                         u32 limit;
 399                         u32 ar;
 400                 } tr, es, ds, fs, gs;
 401         } rmode;
 402         struct {
 403                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 404                 struct kvm_save_segment seg[8];
 405         } segment_cache;
 406         int vpid;
 407         bool emulation_required;
 408
 409         /* Support for vnmi-less CPUs */
 410         int soft_vnmi_blocked;
 411         ktime_t entry_time;
 412         s64 vnmi_blocked_time;
 413         u32 exit_reason;
 414
 415         bool rdtscp_enabled;
 416
 417         /* Support for a guest hypervisor (nested VMX) */
 418         struct nested_vmx nested;
 419 };
 420
 421 enum segment_cache_field {
 422         SEG_FIELD_SEL = 0,
 423         SEG_FIELD_BASE = 1,
 424         SEG_FIELD_LIMIT = 2,
 425         SEG_FIELD_AR = 3,
 426
 427         SEG_FIELD_NR = 4
 428 };
 429
 430 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 431 {
 432         return container_of(vcpu, struct vcpu_vmx, vcpu);
 433 }
 434
 435 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 436 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 437 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 438                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 439
 440 static unsigned short vmcs_field_to_offset_table[] = {
 441         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 442         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 443         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 444         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 445         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 446         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 447         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 448         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 449         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 450         FIELD(HOST_ES_SELECTOR, host_es_selector),
 451         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 452         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 453         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 454         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 455         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 456         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 457         FIELD64(IO_BITMAP_A, io_bitmap_a),
 458         FIELD64(IO_BITMAP_B, io_bitmap_b),
 459         FIELD64(MSR_BITMAP, msr_bitmap),
 460         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 461         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 462         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 463         FIELD64(TSC_OFFSET, tsc_offset),
 464         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 465         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 466         FIELD64(EPT_POINTER, ept_pointer),
 467         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 468         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 469         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 470         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 471         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 472         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 473         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 474         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 475         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 476         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 477         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 478         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 479         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 480         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 481         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 482         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 483         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 484         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 485         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 486         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 487         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 488         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 489         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 490         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 491         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 492         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 493         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 494         FIELD(TPR_THRESHOLD, tpr_threshold),
 495         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 496         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 497         FIELD(VM_EXIT_REASON, vm_exit_reason),
 498         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 499         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 500         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 501         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 502         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 503         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 504         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 505         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 506         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 507         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 508         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 509         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 510         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 511         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 512         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 513         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 514         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 515         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 516         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 517         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 518         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 519         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 520         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 521         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 522         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 523         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 524         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 525         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 526         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 527         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 528         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 529         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 530         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 531         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 532         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 533         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 534         FIELD(EXIT_QUALIFICATION, exit_qualification),
 535         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 536         FIELD(GUEST_CR0, guest_cr0),
 537         FIELD(GUEST_CR3, guest_cr3),
 538         FIELD(GUEST_CR4, guest_cr4),
 539         FIELD(GUEST_ES_BASE, guest_es_base),
 540         FIELD(GUEST_CS_BASE, guest_cs_base),
 541         FIELD(GUEST_SS_BASE, guest_ss_base),
 542         FIELD(GUEST_DS_BASE, guest_ds_base),
 543         FIELD(GUEST_FS_BASE, guest_fs_base),
 544         FIELD(GUEST_GS_BASE, guest_gs_base),
 545         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 546         FIELD(GUEST_TR_BASE, guest_tr_base),
 547         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 548         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 549         FIELD(GUEST_DR7, guest_dr7),
 550         FIELD(GUEST_RSP, guest_rsp),
 551         FIELD(GUEST_RIP, guest_rip),
 552         FIELD(GUEST_RFLAGS, guest_rflags),
 553         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 554         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 555         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 556         FIELD(HOST_CR0, host_cr0),
 557         FIELD(HOST_CR3, host_cr3),
 558         FIELD(HOST_CR4, host_cr4),
 559         FIELD(HOST_FS_BASE, host_fs_base),
 560         FIELD(HOST_GS_BASE, host_gs_base),
 561         FIELD(HOST_TR_BASE, host_tr_base),
 562         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 563         FIELD(HOST_IDTR_BASE, host_idtr_base),
 564         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 565         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 566         FIELD(HOST_RSP, host_rsp),
 567         FIELD(HOST_RIP, host_rip),
 568 };
 569 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 570
 571 static inline short vmcs_field_to_offset(unsigned long field)
 572 {
 573         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 574                 return -1;
 575         return vmcs_field_to_offset_table[field];
 576 }
 577
 578 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 579 {
 580         return to_vmx(vcpu)->nested.current_vmcs12;
 581 }
 582
 583 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 584 {
 585         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 586         if (is_error_page(page)) {
 587                 kvm_release_page_clean(page);
 588                 return NULL;
 589         }
 590         return page;
 591 }
 592
 593 static void nested_release_page(struct page *page)
 594 {
 595         kvm_release_page_dirty(page);
 596 }
 597
 598 static void nested_release_page_clean(struct page *page)
 599 {
 600         kvm_release_page_clean(page);
 601 }
 602
 603 static u64 construct_eptp(unsigned long root_hpa);
 604 static void kvm_cpu_vmxon(u64 addr);
 605 static void kvm_cpu_vmxoff(void);
 606 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 607 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 608
 609 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 610 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 611 /*
 612  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 613  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 614  */
 615 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 616 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 617
 618 static unsigned long *vmx_io_bitmap_a;
 619 static unsigned long *vmx_io_bitmap_b;
 620 static unsigned long *vmx_msr_bitmap_legacy;
 621 static unsigned long *vmx_msr_bitmap_longmode;
 622
 623 static bool cpu_has_load_ia32_efer;
 624 static bool cpu_has_load_perf_global_ctrl;
 625
 626 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 627 static DEFINE_SPINLOCK(vmx_vpid_lock);
 628
 629 static struct vmcs_config {
 630         int size;
 631         int order;
 632         u32 revision_id;
 633         u32 pin_based_exec_ctrl;
 634         u32 cpu_based_exec_ctrl;
 635         u32 cpu_based_2nd_exec_ctrl;
 636         u32 vmexit_ctrl;
 637         u32 vmentry_ctrl;
 638 } vmcs_config;
 639
 640 static struct vmx_capability {
 641         u32 ept;
 642         u32 vpid;
 643 } vmx_capability;
 644
 645 #define VMX_SEGMENT_FIELD(seg)                                  \
 646         [VCPU_SREG_##seg] = {                                   \
 647                 .selector = GUEST_##seg##_SELECTOR,             \
 648                 .base = GUEST_##seg##_BASE,                     \
 649                 .limit = GUEST_##seg##_LIMIT,                   \
 650                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 651         }
 652
 653 static struct kvm_vmx_segment_field {
 654         unsigned selector;
 655         unsigned base;
 656         unsigned limit;
 657         unsigned ar_bytes;
 658 } kvm_vmx_segment_fields[] = {
 659         VMX_SEGMENT_FIELD(CS),
 660         VMX_SEGMENT_FIELD(DS),
 661         VMX_SEGMENT_FIELD(ES),
 662         VMX_SEGMENT_FIELD(FS),
 663         VMX_SEGMENT_FIELD(GS),
 664         VMX_SEGMENT_FIELD(SS),
 665         VMX_SEGMENT_FIELD(TR),
 666         VMX_SEGMENT_FIELD(LDTR),
 667 };
 668
 669 static u64 host_efer;
 670
 671 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 672
 673 /*
 674  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 675  * away by decrementing the array size.
 676  */
 677 static const u32 vmx_msr_index[] = {
 678 #ifdef CONFIG_X86_64
 679         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 680 #endif
 681         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 682 };
 683 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 684
 685 static inline bool is_page_fault(u32 intr_info)
 686 {
 687         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 688                              INTR_INFO_VALID_MASK)) ==
 689                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 690 }
 691
 692 static inline bool is_no_device(u32 intr_info)
 693 {
 694         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 695                              INTR_INFO_VALID_MASK)) ==
 696                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 697 }
 698
 699 static inline bool is_invalid_opcode(u32 intr_info)
 700 {
 701         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 702                              INTR_INFO_VALID_MASK)) ==
 703                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 704 }
 705
 706 static inline bool is_external_interrupt(u32 intr_info)
 707 {
 708         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 709                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 710 }
 711
 712 static inline bool is_machine_check(u32 intr_info)
 713 {
 714         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 715                              INTR_INFO_VALID_MASK)) ==
 716                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 717 }
 718
 719 static inline bool cpu_has_vmx_msr_bitmap(void)
 720 {
 721         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 722 }
 723
 724 static inline bool cpu_has_vmx_tpr_shadow(void)
 725 {
 726         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 727 }
 728
 729 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 730 {
 731         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 732 }
 733
 734 static inline bool cpu_has_secondary_exec_ctrls(void)
 735 {
 736         return vmcs_config.cpu_based_exec_ctrl &
 737                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 738 }
 739
 740 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 741 {
 742         return vmcs_config.cpu_based_2nd_exec_ctrl &
 743                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 744 }
 745
 746 static inline bool cpu_has_vmx_flexpriority(void)
 747 {
 748         return cpu_has_vmx_tpr_shadow() &&
 749                 cpu_has_vmx_virtualize_apic_accesses();
 750 }
 751
 752 static inline bool cpu_has_vmx_ept_execute_only(void)
 753 {
 754         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 755 }
 756
 757 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 758 {
 759         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 760 }
 761
 762 static inline bool cpu_has_vmx_eptp_writeback(void)
 763 {
 764         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 765 }
 766
 767 static inline bool cpu_has_vmx_ept_2m_page(void)
 768 {
 769         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 770 }
 771
 772 static inline bool cpu_has_vmx_ept_1g_page(void)
 773 {
 774         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 775 }
 776
 777 static inline bool cpu_has_vmx_ept_4levels(void)
 778 {
 779         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 780 }
 781
 782 static inline bool cpu_has_vmx_invept_individual_addr(void)
 783 {
 784         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 785 }
 786
 787 static inline bool cpu_has_vmx_invept_context(void)
 788 {
 789         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 790 }
 791
 792 static inline bool cpu_has_vmx_invept_global(void)
 793 {
 794         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 795 }
 796
 797 static inline bool cpu_has_vmx_invvpid_single(void)
 798 {
 799         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 800 }
 801
 802 static inline bool cpu_has_vmx_invvpid_global(void)
 803 {
 804         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 805 }
 806
 807 static inline bool cpu_has_vmx_ept(void)
 808 {
 809         return vmcs_config.cpu_based_2nd_exec_ctrl &
 810                 SECONDARY_EXEC_ENABLE_EPT;
 811 }
 812
 813 static inline bool cpu_has_vmx_unrestricted_guest(void)
 814 {
 815         return vmcs_config.cpu_based_2nd_exec_ctrl &
 816                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 817 }
 818
 819 static inline bool cpu_has_vmx_ple(void)
 820 {
 821         return vmcs_config.cpu_based_2nd_exec_ctrl &
 822                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 823 }
 824
 825 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 826 {
 827         return flexpriority_enabled && irqchip_in_kernel(kvm);
 828 }
 829
 830 static inline bool cpu_has_vmx_vpid(void)
 831 {
 832         return vmcs_config.cpu_based_2nd_exec_ctrl &
 833                 SECONDARY_EXEC_ENABLE_VPID;
 834 }
 835
 836 static inline bool cpu_has_vmx_rdtscp(void)
 837 {
 838         return vmcs_config.cpu_based_2nd_exec_ctrl &
 839                 SECONDARY_EXEC_RDTSCP;
 840 }
 841
 842 static inline bool cpu_has_virtual_nmis(void)
 843 {
 844         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 845 }
 846
 847 static inline bool cpu_has_vmx_wbinvd_exit(void)
 848 {
 849         return vmcs_config.cpu_based_2nd_exec_ctrl &
 850                 SECONDARY_EXEC_WBINVD_EXITING;
 851 }
 852
 853 static inline bool report_flexpriority(void)
 854 {
 855         return flexpriority_enabled;
 856 }
 857
 858 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 859 {
 860         return vmcs12->cpu_based_vm_exec_control & bit;
 861 }
 862
 863 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 864 {
 865         return (vmcs12->cpu_based_vm_exec_control &
 866                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 867                 (vmcs12->secondary_vm_exec_control & bit);
 868 }
 869
 870 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 871         struct kvm_vcpu *vcpu)
 872 {
 873         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 874 }
 875
 876 static inline bool is_exception(u32 intr_info)
 877 {
 878         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 879                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 880 }
 881
 882 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 883 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 884                         struct vmcs12 *vmcs12,
 885                         u32 reason, unsigned long qualification);
 886
 887 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 888 {
 889         int i;
 890
 891         for (i = 0; i < vmx->nmsrs; ++i)
 892                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 893                         return i;
 894         return -1;
 895 }
 896
 897 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 898 {
 899     struct {
 900         u64 vpid : 16;
 901         u64 rsvd : 48;
 902         u64 gva;
 903     } operand = { vpid, 0, gva };
 904
 905     asm volatile (__ex(ASM_VMX_INVVPID)
 906                   /* CF==1 or ZF==1 --> rc = -1 */
 907                   "; ja 1f ; ud2 ; 1:"
 908                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 909 }
 910
 911 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 912 {
 913         struct {
 914                 u64 eptp, gpa;
 915         } operand = {eptp, gpa};
 916
 917         asm volatile (__ex(ASM_VMX_INVEPT)
 918                         /* CF==1 or ZF==1 --> rc = -1 */
 919                         "; ja 1f ; ud2 ; 1:\n"
 920                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 921 }
 922
 923 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 924 {
 925         int i;
 926
 927         i = __find_msr_index(vmx, msr);
 928         if (i >= 0)
 929                 return &vmx->guest_msrs[i];
 930         return NULL;
 931 }
 932
 933 static void vmcs_clear(struct vmcs *vmcs)
 934 {
 935         u64 phys_addr = __pa(vmcs);
 936         u8 error;
 937
 938         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 939                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 940                       : "cc", "memory");
 941         if (error)
 942                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 943                        vmcs, phys_addr);
 944 }
 945
 946 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 947 {
 948         vmcs_clear(loaded_vmcs->vmcs);
 949         loaded_vmcs->cpu = -1;
 950         loaded_vmcs->launched = 0;
 951 }
 952
 953 static void vmcs_load(struct vmcs *vmcs)
 954 {
 955         u64 phys_addr = __pa(vmcs);
 956         u8 error;
 957
 958         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 959                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 960                         : "cc", "memory");
 961         if (error)
 962                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 963                        vmcs, phys_addr);
 964 }
 965
 966 static void __loaded_vmcs_clear(void *arg)
 967 {
 968         struct loaded_vmcs *loaded_vmcs = arg;
 969         int cpu = raw_smp_processor_id();
 970
 971         if (loaded_vmcs->cpu != cpu)
 972                 return; /* vcpu migration can race with cpu offline */
 973         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 974                 per_cpu(current_vmcs, cpu) = NULL;
 975         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 976         loaded_vmcs_init(loaded_vmcs);
 977 }
 978
 979 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 980 {
 981         if (loaded_vmcs->cpu != -1)
 982                 smp_call_function_single(
 983                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 984 }
 985
 986 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 987 {
 988         if (vmx->vpid == 0)
 989                 return;
 990
 991         if (cpu_has_vmx_invvpid_single())
 992                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 993 }
 994
 995 static inline void vpid_sync_vcpu_global(void)
 996 {
 997         if (cpu_has_vmx_invvpid_global())
 998                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 999 }
1000
1001 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1002 {
1003         if (cpu_has_vmx_invvpid_single())
1004                 vpid_sync_vcpu_single(vmx);
1005         else
1006                 vpid_sync_vcpu_global();
1007 }
1008
1009 static inline void ept_sync_global(void)
1010 {
1011         if (cpu_has_vmx_invept_global())
1012                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1013 }
1014
1015 static inline void ept_sync_context(u64 eptp)
1016 {
1017         if (enable_ept) {
1018                 if (cpu_has_vmx_invept_context())
1019                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1020                 else
1021                         ept_sync_global();
1022         }
1023 }
1024
1025 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1026 {
1027         if (enable_ept) {
1028                 if (cpu_has_vmx_invept_individual_addr())
1029                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1030                                         eptp, gpa);
1031                 else
1032                         ept_sync_context(eptp);
1033         }
1034 }
1035
1036 static __always_inline unsigned long vmcs_readl(unsigned long field)
1037 {
1038         unsigned long value;
1039
1040         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041                       : "=a"(value) : "d"(field) : "cc");
1042         return value;
1043 }
1044
1045 static __always_inline u16 vmcs_read16(unsigned long field)
1046 {
1047         return vmcs_readl(field);
1048 }
1049
1050 static __always_inline u32 vmcs_read32(unsigned long field)
1051 {
1052         return vmcs_readl(field);
1053 }
1054
1055 static __always_inline u64 vmcs_read64(unsigned long field)
1056 {
1057 #ifdef CONFIG_X86_64
1058         return vmcs_readl(field);
1059 #else
1060         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1061 #endif
1062 }
1063
1064 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1065 {
1066         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1068         dump_stack();
1069 }
1070
1071 static void vmcs_writel(unsigned long field, unsigned long value)
1072 {
1073         u8 error;
1074
1075         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1076                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1077         if (unlikely(error))
1078                 vmwrite_error(field, value);
1079 }
1080
1081 static void vmcs_write16(unsigned long field, u16 value)
1082 {
1083         vmcs_writel(field, value);
1084 }
1085
1086 static void vmcs_write32(unsigned long field, u32 value)
1087 {
1088         vmcs_writel(field, value);
1089 }
1090
1091 static void vmcs_write64(unsigned long field, u64 value)
1092 {
1093         vmcs_writel(field, value);
1094 #ifndef CONFIG_X86_64
1095         asm volatile ("");
1096         vmcs_writel(field+1, value >> 32);
1097 #endif
1098 }
1099
1100 static void vmcs_clear_bits(unsigned long field, u32 mask)
1101 {
1102         vmcs_writel(field, vmcs_readl(field) & ~mask);
1103 }
1104
1105 static void vmcs_set_bits(unsigned long field, u32 mask)
1106 {
1107         vmcs_writel(field, vmcs_readl(field) | mask);
1108 }
1109
1110 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1111 {
1112         vmx->segment_cache.bitmask = 0;
1113 }
1114
1115 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1116                                        unsigned field)
1117 {
1118         bool ret;
1119         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1120
1121         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123                 vmx->segment_cache.bitmask = 0;
1124         }
1125         ret = vmx->segment_cache.bitmask & mask;
1126         vmx->segment_cache.bitmask |= mask;
1127         return ret;
1128 }
1129
1130 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1131 {
1132         u16 *p = &vmx->segment_cache.seg[seg].selector;
1133
1134         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1136         return *p;
1137 }
1138
1139 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1140 {
1141         ulong *p = &vmx->segment_cache.seg[seg].base;
1142
1143         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1145         return *p;
1146 }
1147
1148 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1149 {
1150         u32 *p = &vmx->segment_cache.seg[seg].limit;
1151
1152         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1154         return *p;
1155 }
1156
1157 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1158 {
1159         u32 *p = &vmx->segment_cache.seg[seg].ar;
1160
1161         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1163         return *p;
1164 }
1165
1166 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1167 {
1168         u32 eb;
1169
1170         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172         if ((vcpu->guest_debug &
1173              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175                 eb |= 1u << BP_VECTOR;
1176         if (to_vmx(vcpu)->rmode.vm86_active)
1177                 eb = ~0;
1178         if (enable_ept)
1179                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1180         if (vcpu->fpu_active)
1181                 eb &= ~(1u << NM_VECTOR);
1182
1183         /* When we are running a nested L2 guest and L1 specified for it a
1184          * certain exception bitmap, we must trap the same exceptions and pass
1185          * them to L1. When running L2, we will only handle the exceptions
1186          * specified above if L1 did not want them.
1187          */
1188         if (is_guest_mode(vcpu))
1189                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1190
1191         vmcs_write32(EXCEPTION_BITMAP, eb);
1192 }
1193
1194 static void clear_atomic_switch_msr_special(unsigned long entry,
1195                 unsigned long exit)
1196 {
1197         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1198         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1199 }
1200
1201 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1202 {
1203         unsigned i;
1204         struct msr_autoload *m = &vmx->msr_autoload;
1205
1206         switch (msr) {
1207         case MSR_EFER:
1208                 if (cpu_has_load_ia32_efer) {
1209                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1210                                         VM_EXIT_LOAD_IA32_EFER);
1211                         return;
1212                 }
1213                 break;
1214         case MSR_CORE_PERF_GLOBAL_CTRL:
1215                 if (cpu_has_load_perf_global_ctrl) {
1216                         clear_atomic_switch_msr_special(
1217                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1218                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1219                         return;
1220                 }
1221                 break;
1222         }
1223
1224         for (i = 0; i < m->nr; ++i)
1225                 if (m->guest[i].index == msr)
1226                         break;
1227
1228         if (i == m->nr)
1229                 return;
1230         --m->nr;
1231         m->guest[i] = m->guest[m->nr];
1232         m->host[i] = m->host[m->nr];
1233         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1234         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1235 }
1236
1237 static void add_atomic_switch_msr_special(unsigned long entry,
1238                 unsigned long exit, unsigned long guest_val_vmcs,
1239                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1240 {
1241         vmcs_write64(guest_val_vmcs, guest_val);
1242         vmcs_write64(host_val_vmcs, host_val);
1243         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1244         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1245 }
1246
1247 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1248                                   u64 guest_val, u64 host_val)
1249 {
1250         unsigned i;
1251         struct msr_autoload *m = &vmx->msr_autoload;
1252
1253         switch (msr) {
1254         case MSR_EFER:
1255                 if (cpu_has_load_ia32_efer) {
1256                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1257                                         VM_EXIT_LOAD_IA32_EFER,
1258                                         GUEST_IA32_EFER,
1259                                         HOST_IA32_EFER,
1260                                         guest_val, host_val);
1261                         return;
1262                 }
1263                 break;
1264         case MSR_CORE_PERF_GLOBAL_CTRL:
1265                 if (cpu_has_load_perf_global_ctrl) {
1266                         add_atomic_switch_msr_special(
1267                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1268                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1269                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1270                                         HOST_IA32_PERF_GLOBAL_CTRL,
1271                                         guest_val, host_val);
1272                         return;
1273                 }
1274                 break;
1275         }
1276
1277         for (i = 0; i < m->nr; ++i)
1278                 if (m->guest[i].index == msr)
1279                         break;
1280
1281         if (i == NR_AUTOLOAD_MSRS) {
1282                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1283                                 "Can't add msr %x\n", msr);
1284                 return;
1285         } else if (i == m->nr) {
1286                 ++m->nr;
1287                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1288                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1289         }
1290
1291         m->guest[i].index = msr;
1292         m->guest[i].value = guest_val;
1293         m->host[i].index = msr;
1294         m->host[i].value = host_val;
1295 }
1296
1297 static void reload_tss(void)
1298 {
1299         /*
1300          * VT restores TR but not its size.  Useless.
1301          */
1302         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1303         struct desc_struct *descs;
1304
1305         descs = (void *)gdt->address;
1306         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1307         load_TR_desc();
1308 }
1309
1310 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1311 {
1312         u64 guest_efer;
1313         u64 ignore_bits;
1314
1315         guest_efer = vmx->vcpu.arch.efer;
1316
1317         /*
1318          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1319          * outside long mode
1320          */
1321         ignore_bits = EFER_NX | EFER_SCE;
1322 #ifdef CONFIG_X86_64
1323         ignore_bits |= EFER_LMA | EFER_LME;
1324         /* SCE is meaningful only in long mode on Intel */
1325         if (guest_efer & EFER_LMA)
1326                 ignore_bits &= ~(u64)EFER_SCE;
1327 #endif
1328         guest_efer &= ~ignore_bits;
1329         guest_efer |= host_efer & ignore_bits;
1330         vmx->guest_msrs[efer_offset].data = guest_efer;
1331         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1332
1333         clear_atomic_switch_msr(vmx, MSR_EFER);
1334         /* On ept, can't emulate nx, and must switch nx atomically */
1335         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1336                 guest_efer = vmx->vcpu.arch.efer;
1337                 if (!(guest_efer & EFER_LMA))
1338                         guest_efer &= ~EFER_LME;
1339                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1340                 return false;
1341         }
1342
1343         return true;
1344 }
1345
1346 static unsigned long segment_base(u16 selector)
1347 {
1348         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1349         struct desc_struct *d;
1350         unsigned long table_base;
1351         unsigned long v;
1352
1353         if (!(selector & ~3))
1354                 return 0;
1355
1356         table_base = gdt->address;
1357
1358         if (selector & 4) {           /* from ldt */
1359                 u16 ldt_selector = kvm_read_ldt();
1360
1361                 if (!(ldt_selector & ~3))
1362                         return 0;
1363
1364                 table_base = segment_base(ldt_selector);
1365         }
1366         d = (struct desc_struct *)(table_base + (selector & ~7));
1367         v = get_desc_base(d);
1368 #ifdef CONFIG_X86_64
1369        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1370                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1371 #endif
1372         return v;
1373 }
1374
1375 static inline unsigned long kvm_read_tr_base(void)
1376 {
1377         u16 tr;
1378         asm("str %0" : "=g"(tr));
1379         return segment_base(tr);
1380 }
1381
1382 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1383 {
1384         struct vcpu_vmx *vmx = to_vmx(vcpu);
1385         int i;
1386
1387         if (vmx->host_state.loaded)
1388                 return;
1389
1390         vmx->host_state.loaded = 1;
1391         /*
1392          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1393          * allow segment selectors with cpl > 0 or ti == 1.
1394          */
1395         vmx->host_state.ldt_sel = kvm_read_ldt();
1396         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1397         savesegment(fs, vmx->host_state.fs_sel);
1398         if (!(vmx->host_state.fs_sel & 7)) {
1399                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1400                 vmx->host_state.fs_reload_needed = 0;
1401         } else {
1402                 vmcs_write16(HOST_FS_SELECTOR, 0);
1403                 vmx->host_state.fs_reload_needed = 1;
1404         }
1405         savesegment(gs, vmx->host_state.gs_sel);
1406         if (!(vmx->host_state.gs_sel & 7))
1407                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1408         else {
1409                 vmcs_write16(HOST_GS_SELECTOR, 0);
1410                 vmx->host_state.gs_ldt_reload_needed = 1;
1411         }
1412
1413 #ifdef CONFIG_X86_64
1414         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1415         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1416 #else
1417         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1418         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1419 #endif
1420
1421 #ifdef CONFIG_X86_64
1422         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1423         if (is_long_mode(&vmx->vcpu))
1424                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1425 #endif
1426         for (i = 0; i < vmx->save_nmsrs; ++i)
1427                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1428                                    vmx->guest_msrs[i].data,
1429                                    vmx->guest_msrs[i].mask);
1430 }
1431
1432 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1433 {
1434         if (!vmx->host_state.loaded)
1435                 return;
1436
1437         ++vmx->vcpu.stat.host_state_reload;
1438         vmx->host_state.loaded = 0;
1439 #ifdef CONFIG_X86_64
1440         if (is_long_mode(&vmx->vcpu))
1441                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1442 #endif
1443         if (vmx->host_state.gs_ldt_reload_needed) {
1444                 kvm_load_ldt(vmx->host_state.ldt_sel);
1445 #ifdef CONFIG_X86_64
1446                 load_gs_index(vmx->host_state.gs_sel);
1447 #else
1448                 loadsegment(gs, vmx->host_state.gs_sel);
1449 #endif
1450         }
1451         if (vmx->host_state.fs_reload_needed)
1452                 loadsegment(fs, vmx->host_state.fs_sel);
1453         reload_tss();
1454 #ifdef CONFIG_X86_64
1455         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1456 #endif
1457         if (user_has_fpu())
1458                 clts();
1459         load_gdt(&__get_cpu_var(host_gdt));
1460 }
1461
1462 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1463 {
1464         preempt_disable();
1465         __vmx_load_host_state(vmx);
1466         preempt_enable();
1467 }
1468
1469 /*
1470  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1471  * vcpu mutex is already taken.
1472  */
1473 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1474 {
1475         struct vcpu_vmx *vmx = to_vmx(vcpu);
1476         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1477
1478         if (!vmm_exclusive)
1479                 kvm_cpu_vmxon(phys_addr);
1480         else if (vmx->loaded_vmcs->cpu != cpu)
1481                 loaded_vmcs_clear(vmx->loaded_vmcs);
1482
1483         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1484                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1485                 vmcs_load(vmx->loaded_vmcs->vmcs);
1486         }
1487
1488         if (vmx->loaded_vmcs->cpu != cpu) {
1489                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1490                 unsigned long sysenter_esp;
1491
1492                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1493                 local_irq_disable();
1494                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1495                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1496                 local_irq_enable();
1497
1498                 /*
1499                  * Linux uses per-cpu TSS and GDT, so set these when switching
1500                  * processors.
1501                  */
1502                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1503                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1504
1505                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1506                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1507                 vmx->loaded_vmcs->cpu = cpu;
1508         }
1509 }
1510
1511 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1512 {
1513         __vmx_load_host_state(to_vmx(vcpu));
1514         if (!vmm_exclusive) {
1515                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1516                 vcpu->cpu = -1;
1517                 kvm_cpu_vmxoff();
1518         }
1519 }
1520
1521 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1522 {
1523         ulong cr0;
1524
1525         if (vcpu->fpu_active)
1526                 return;
1527         vcpu->fpu_active = 1;
1528         cr0 = vmcs_readl(GUEST_CR0);
1529         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1530         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1531         vmcs_writel(GUEST_CR0, cr0);
1532         update_exception_bitmap(vcpu);
1533         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1534         if (is_guest_mode(vcpu))
1535                 vcpu->arch.cr0_guest_owned_bits &=
1536                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1537         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1538 }
1539
1540 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1541
1542 /*
1543  * Return the cr0 value that a nested guest would read. This is a combination
1544  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1545  * its hypervisor (cr0_read_shadow).
1546  */
1547 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1548 {
1549         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1550                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1551 }
1552 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1553 {
1554         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1555                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1556 }
1557
1558 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1559 {
1560         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1561          * set this *before* calling this function.
1562          */
1563         vmx_decache_cr0_guest_bits(vcpu);
1564         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1565         update_exception_bitmap(vcpu);
1566         vcpu->arch.cr0_guest_owned_bits = 0;
1567         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1568         if (is_guest_mode(vcpu)) {
1569                 /*
1570                  * L1's specified read shadow might not contain the TS bit,
1571                  * so now that we turned on shadowing of this bit, we need to
1572                  * set this bit of the shadow. Like in nested_vmx_run we need
1573                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1574                  * up-to-date here because we just decached cr0.TS (and we'll
1575                  * only update vmcs12->guest_cr0 on nested exit).
1576                  */
1577                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1578                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1579                         (vcpu->arch.cr0 & X86_CR0_TS);
1580                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1581         } else
1582                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1583 }
1584
1585 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1586 {
1587         unsigned long rflags, save_rflags;
1588
1589         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1590                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1591                 rflags = vmcs_readl(GUEST_RFLAGS);
1592                 if (to_vmx(vcpu)->rmode.vm86_active) {
1593                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1594                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1595                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1596                 }
1597                 to_vmx(vcpu)->rflags = rflags;
1598         }
1599         return to_vmx(vcpu)->rflags;
1600 }
1601
1602 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1603 {
1604         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1605         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1606         to_vmx(vcpu)->rflags = rflags;
1607         if (to_vmx(vcpu)->rmode.vm86_active) {
1608                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1609                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1610         }
1611         vmcs_writel(GUEST_RFLAGS, rflags);
1612 }
1613
1614 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1615 {
1616         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1617         int ret = 0;
1618
1619         if (interruptibility & GUEST_INTR_STATE_STI)
1620                 ret |= KVM_X86_SHADOW_INT_STI;
1621         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1622                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1623
1624         return ret & mask;
1625 }
1626
1627 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1628 {
1629         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1630         u32 interruptibility = interruptibility_old;
1631
1632         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1633
1634         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1635                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1636         else if (mask & KVM_X86_SHADOW_INT_STI)
1637                 interruptibility |= GUEST_INTR_STATE_STI;
1638
1639         if ((interruptibility != interruptibility_old))
1640                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1641 }
1642
1643 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1644 {
1645         unsigned long rip;
1646
1647         rip = kvm_rip_read(vcpu);
1648         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1649         kvm_rip_write(vcpu, rip);
1650
1651         /* skipping an emulated instruction also counts */
1652         vmx_set_interrupt_shadow(vcpu, 0);
1653 }
1654
1655 /*
1656  * KVM wants to inject page-faults which it got to the guest. This function
1657  * checks whether in a nested guest, we need to inject them to L1 or L2.
1658  * This function assumes it is called with the exit reason in vmcs02 being
1659  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1660  * is running).
1661  */
1662 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1663 {
1664         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1665
1666         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1667         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1668                 return 0;
1669
1670         nested_vmx_vmexit(vcpu);
1671         return 1;
1672 }
1673
1674 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1675                                 bool has_error_code, u32 error_code,
1676                                 bool reinject)
1677 {
1678         struct vcpu_vmx *vmx = to_vmx(vcpu);
1679         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1680
1681         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1682                 nested_pf_handled(vcpu))
1683                 return;
1684
1685         if (has_error_code) {
1686                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1687                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1688         }
1689
1690         if (vmx->rmode.vm86_active) {
1691                 int inc_eip = 0;
1692                 if (kvm_exception_is_soft(nr))
1693                         inc_eip = vcpu->arch.event_exit_inst_len;
1694                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1695                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1696                 return;
1697         }
1698
1699         if (kvm_exception_is_soft(nr)) {
1700                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1701                              vmx->vcpu.arch.event_exit_inst_len);
1702                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1703         } else
1704                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1705
1706         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1707 }
1708
1709 static bool vmx_rdtscp_supported(void)
1710 {
1711         return cpu_has_vmx_rdtscp();
1712 }
1713
1714 /*
1715  * Swap MSR entry in host/guest MSR entry array.
1716  */
1717 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1718 {
1719         struct shared_msr_entry tmp;
1720
1721         tmp = vmx->guest_msrs[to];
1722         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1723         vmx->guest_msrs[from] = tmp;
1724 }
1725
1726 /*
1727  * Set up the vmcs to automatically save and restore system
1728  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1729  * mode, as fiddling with msrs is very expensive.
1730  */
1731 static void setup_msrs(struct vcpu_vmx *vmx)
1732 {
1733         int save_nmsrs, index;
1734         unsigned long *msr_bitmap;
1735
1736         save_nmsrs = 0;
1737 #ifdef CONFIG_X86_64
1738         if (is_long_mode(&vmx->vcpu)) {
1739                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1740                 if (index >= 0)
1741                         move_msr_up(vmx, index, save_nmsrs++);
1742                 index = __find_msr_index(vmx, MSR_LSTAR);
1743                 if (index >= 0)
1744                         move_msr_up(vmx, index, save_nmsrs++);
1745                 index = __find_msr_index(vmx, MSR_CSTAR);
1746                 if (index >= 0)
1747                         move_msr_up(vmx, index, save_nmsrs++);
1748                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1749                 if (index >= 0 && vmx->rdtscp_enabled)
1750                         move_msr_up(vmx, index, save_nmsrs++);
1751                 /*
1752                  * MSR_STAR is only needed on long mode guests, and only
1753                  * if efer.sce is enabled.
1754                  */
1755                 index = __find_msr_index(vmx, MSR_STAR);
1756                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1757                         move_msr_up(vmx, index, save_nmsrs++);
1758         }
1759 #endif
1760         index = __find_msr_index(vmx, MSR_EFER);
1761         if (index >= 0 && update_transition_efer(vmx, index))
1762                 move_msr_up(vmx, index, save_nmsrs++);
1763
1764         vmx->save_nmsrs = save_nmsrs;
1765
1766         if (cpu_has_vmx_msr_bitmap()) {
1767                 if (is_long_mode(&vmx->vcpu))
1768                         msr_bitmap = vmx_msr_bitmap_longmode;
1769                 else
1770                         msr_bitmap = vmx_msr_bitmap_legacy;
1771
1772                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1773         }
1774 }
1775
1776 /*
1777  * reads and returns guest's timestamp counter "register"
1778  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1779  */
1780 static u64 guest_read_tsc(void)
1781 {
1782         u64 host_tsc, tsc_offset;
1783
1784         rdtscll(host_tsc);
1785         tsc_offset = vmcs_read64(TSC_OFFSET);
1786         return host_tsc + tsc_offset;
1787 }
1788
1789 /*
1790  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1791  * counter, even if a nested guest (L2) is currently running.
1792  */
1793 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1794 {
1795         u64 host_tsc, tsc_offset;
1796
1797         rdtscll(host_tsc);
1798         tsc_offset = is_guest_mode(vcpu) ?
1799                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1800                 vmcs_read64(TSC_OFFSET);
1801         return host_tsc + tsc_offset;
1802 }
1803
1804 /*
1805  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1806  * software catchup for faster rates on slower CPUs.
1807  */
1808 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1809 {
1810         if (!scale)
1811                 return;
1812
1813         if (user_tsc_khz > tsc_khz) {
1814                 vcpu->arch.tsc_catchup = 1;
1815                 vcpu->arch.tsc_always_catchup = 1;
1816         } else
1817                 WARN(1, "user requested TSC rate below hardware speed\n");
1818 }
1819
1820 /*
1821  * writes 'offset' into guest's timestamp counter offset register
1822  */
1823 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1824 {
1825         if (is_guest_mode(vcpu)) {
1826                 /*
1827                  * We're here if L1 chose not to trap WRMSR to TSC. According
1828                  * to the spec, this should set L1's TSC; The offset that L1
1829                  * set for L2 remains unchanged, and still needs to be added
1830                  * to the newly set TSC to get L2's TSC.
1831                  */
1832                 struct vmcs12 *vmcs12;
1833                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1834                 /* recalculate vmcs02.TSC_OFFSET: */
1835                 vmcs12 = get_vmcs12(vcpu);
1836                 vmcs_write64(TSC_OFFSET, offset +
1837                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1838                          vmcs12->tsc_offset : 0));
1839         } else {
1840                 vmcs_write64(TSC_OFFSET, offset);
1841         }
1842 }
1843
1844 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1845 {
1846         u64 offset = vmcs_read64(TSC_OFFSET);
1847         vmcs_write64(TSC_OFFSET, offset + adjustment);
1848         if (is_guest_mode(vcpu)) {
1849                 /* Even when running L2, the adjustment needs to apply to L1 */
1850                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1851         }
1852 }
1853
1854 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1855 {
1856         return target_tsc - native_read_tsc();
1857 }
1858
1859 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1860 {
1861         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1862         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1863 }
1864
1865 /*
1866  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1867  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1868  * all guests if the "nested" module option is off, and can also be disabled
1869  * for a single guest by disabling its VMX cpuid bit.
1870  */
1871 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1872 {
1873         return nested && guest_cpuid_has_vmx(vcpu);
1874 }
1875
1876 /*
1877  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1878  * returned for the various VMX controls MSRs when nested VMX is enabled.
1879  * The same values should also be used to verify that vmcs12 control fields are
1880  * valid during nested entry from L1 to L2.
1881  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1882  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1883  * bit in the high half is on if the corresponding bit in the control field
1884  * may be on. See also vmx_control_verify().
1885  * TODO: allow these variables to be modified (downgraded) by module options
1886  * or other means.
1887  */
1888 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1889 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1890 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1891 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1892 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1893 static __init void nested_vmx_setup_ctls_msrs(void)
1894 {
1895         /*
1896          * Note that as a general rule, the high half of the MSRs (bits in
1897          * the control fields which may be 1) should be initialized by the
1898          * intersection of the underlying hardware's MSR (i.e., features which
1899          * can be supported) and the list of features we want to expose -
1900          * because they are known to be properly supported in our code.
1901          * Also, usually, the low half of the MSRs (bits which must be 1) can
1902          * be set to 0, meaning that L1 may turn off any of these bits. The
1903          * reason is that if one of these bits is necessary, it will appear
1904          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1905          * fields of vmcs01 and vmcs02, will turn these bits off - and
1906          * nested_vmx_exit_handled() will not pass related exits to L1.
1907          * These rules have exceptions below.
1908          */
1909
1910         /* pin-based controls */
1911         /*
1912          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1913          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1914          */
1915         nested_vmx_pinbased_ctls_low = 0x16 ;
1916         nested_vmx_pinbased_ctls_high = 0x16 |
1917                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1918                 PIN_BASED_VIRTUAL_NMIS;
1919
1920         /* exit controls */
1921         nested_vmx_exit_ctls_low = 0;
1922         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1923 #ifdef CONFIG_X86_64
1924         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1925 #else
1926         nested_vmx_exit_ctls_high = 0;
1927 #endif
1928
1929         /* entry controls */
1930         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1931                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1932         nested_vmx_entry_ctls_low = 0;
1933         nested_vmx_entry_ctls_high &=
1934                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1935
1936         /* cpu-based controls */
1937         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1938                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1939         nested_vmx_procbased_ctls_low = 0;
1940         nested_vmx_procbased_ctls_high &=
1941                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1942                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1943                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1944                 CPU_BASED_CR3_STORE_EXITING |
1945 #ifdef CONFIG_X86_64
1946                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1947 #endif
1948                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1949                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1950                 CPU_BASED_RDPMC_EXITING |
1951                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1952         /*
1953          * We can allow some features even when not supported by the
1954          * hardware. For example, L1 can specify an MSR bitmap - and we
1955          * can use it to avoid exits to L1 - even when L0 runs L2
1956          * without MSR bitmaps.
1957          */
1958         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1959
1960         /* secondary cpu-based controls */
1961         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1962                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1963         nested_vmx_secondary_ctls_low = 0;
1964         nested_vmx_secondary_ctls_high &=
1965                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1966 }
1967
1968 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1969 {
1970         /*
1971          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1972          */
1973         return ((control & high) | low) == control;
1974 }
1975
1976 static inline u64 vmx_control_msr(u32 low, u32 high)
1977 {
1978         return low | ((u64)high << 32);
1979 }
1980
1981 /*
1982  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1983  * also let it use VMX-specific MSRs.
1984  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1985  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1986  * like all other MSRs).
1987  */
1988 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1989 {
1990         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1991                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1992                 /*
1993                  * According to the spec, processors which do not support VMX
1994                  * should throw a #GP(0) when VMX capability MSRs are read.
1995                  */
1996                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1997                 return 1;
1998         }
1999
2000         switch (msr_index) {
2001         case MSR_IA32_FEATURE_CONTROL:
2002                 *pdata = 0;
2003                 break;
2004         case MSR_IA32_VMX_BASIC:
2005                 /*
2006                  * This MSR reports some information about VMX support. We
2007                  * should return information about the VMX we emulate for the
2008                  * guest, and the VMCS structure we give it - not about the
2009                  * VMX support of the underlying hardware.
2010                  */
2011                 *pdata = VMCS12_REVISION |
2012                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2013                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2014                 break;
2015         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2016         case MSR_IA32_VMX_PINBASED_CTLS:
2017                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2018                                         nested_vmx_pinbased_ctls_high);
2019                 break;
2020         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2021         case MSR_IA32_VMX_PROCBASED_CTLS:
2022                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2023                                         nested_vmx_procbased_ctls_high);
2024                 break;
2025         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2026         case MSR_IA32_VMX_EXIT_CTLS:
2027                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2028                                         nested_vmx_exit_ctls_high);
2029                 break;
2030         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2031         case MSR_IA32_VMX_ENTRY_CTLS:
2032                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2033                                         nested_vmx_entry_ctls_high);
2034                 break;
2035         case MSR_IA32_VMX_MISC:
2036                 *pdata = 0;
2037                 break;
2038         /*
2039          * These MSRs specify bits which the guest must keep fixed (on or off)
2040          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2041          * We picked the standard core2 setting.
2042          */
2043 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2044 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2045         case MSR_IA32_VMX_CR0_FIXED0:
2046                 *pdata = VMXON_CR0_ALWAYSON;
2047                 break;
2048         case MSR_IA32_VMX_CR0_FIXED1:
2049                 *pdata = -1ULL;
2050                 break;
2051         case MSR_IA32_VMX_CR4_FIXED0:
2052                 *pdata = VMXON_CR4_ALWAYSON;
2053                 break;
2054         case MSR_IA32_VMX_CR4_FIXED1:
2055                 *pdata = -1ULL;
2056                 break;
2057         case MSR_IA32_VMX_VMCS_ENUM:
2058                 *pdata = 0x1f;
2059                 break;
2060         case MSR_IA32_VMX_PROCBASED_CTLS2:
2061                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2062                                         nested_vmx_secondary_ctls_high);
2063                 break;
2064         case MSR_IA32_VMX_EPT_VPID_CAP:
2065                 /* Currently, no nested ept or nested vpid */
2066                 *pdata = 0;
2067                 break;
2068         default:
2069                 return 0;
2070         }
2071
2072         return 1;
2073 }
2074
2075 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2076 {
2077         if (!nested_vmx_allowed(vcpu))
2078                 return 0;
2079
2080         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2081                 /* TODO: the right thing. */
2082                 return 1;
2083         /*
2084          * No need to treat VMX capability MSRs specially: If we don't handle
2085          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2086          */
2087         return 0;
2088 }
2089
2090 /*
2091  * Reads an msr value (of 'msr_index') into 'pdata'.
2092  * Returns 0 on success, non-0 otherwise.
2093  * Assumes vcpu_load() was already called.
2094  */
2095 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2096 {
2097         u64 data;
2098         struct shared_msr_entry *msr;
2099
2100         if (!pdata) {
2101                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2102                 return -EINVAL;
2103         }
2104
2105         switch (msr_index) {
2106 #ifdef CONFIG_X86_64
2107         case MSR_FS_BASE:
2108                 data = vmcs_readl(GUEST_FS_BASE);
2109                 break;
2110         case MSR_GS_BASE:
2111                 data = vmcs_readl(GUEST_GS_BASE);
2112                 break;
2113         case MSR_KERNEL_GS_BASE:
2114                 vmx_load_host_state(to_vmx(vcpu));
2115                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2116                 break;
2117 #endif
2118         case MSR_EFER:
2119                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2120         case MSR_IA32_TSC:
2121                 data = guest_read_tsc();
2122                 break;
2123         case MSR_IA32_SYSENTER_CS:
2124                 data = vmcs_read32(GUEST_SYSENTER_CS);
2125                 break;
2126         case MSR_IA32_SYSENTER_EIP:
2127                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2128                 break;
2129         case MSR_IA32_SYSENTER_ESP:
2130                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2131                 break;
2132         case MSR_TSC_AUX:
2133                 if (!to_vmx(vcpu)->rdtscp_enabled)
2134                         return 1;
2135                 /* Otherwise falls through */
2136         default:
2137                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2138                         return 0;
2139                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2140                 if (msr) {
2141                         data = msr->data;
2142                         break;
2143                 }
2144                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2145         }
2146
2147         *pdata = data;
2148         return 0;
2149 }
2150
2151 /*
2152  * Writes msr value into into the appropriate "register".
2153  * Returns 0 on success, non-0 otherwise.
2154  * Assumes vcpu_load() was already called.
2155  */
2156 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2157 {
2158         struct vcpu_vmx *vmx = to_vmx(vcpu);
2159         struct shared_msr_entry *msr;
2160         int ret = 0;
2161
2162         switch (msr_index) {
2163         case MSR_EFER:
2164                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2165                 break;
2166 #ifdef CONFIG_X86_64
2167         case MSR_FS_BASE:
2168                 vmx_segment_cache_clear(vmx);
2169                 vmcs_writel(GUEST_FS_BASE, data);
2170                 break;
2171         case MSR_GS_BASE:
2172                 vmx_segment_cache_clear(vmx);
2173                 vmcs_writel(GUEST_GS_BASE, data);
2174                 break;
2175         case MSR_KERNEL_GS_BASE:
2176                 vmx_load_host_state(vmx);
2177                 vmx->msr_guest_kernel_gs_base = data;
2178                 break;
2179 #endif
2180         case MSR_IA32_SYSENTER_CS:
2181                 vmcs_write32(GUEST_SYSENTER_CS, data);
2182                 break;
2183         case MSR_IA32_SYSENTER_EIP:
2184                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2185                 break;
2186         case MSR_IA32_SYSENTER_ESP:
2187                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2188                 break;
2189         case MSR_IA32_TSC:
2190                 kvm_write_tsc(vcpu, data);
2191                 break;
2192         case MSR_IA32_CR_PAT:
2193                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2194                         vmcs_write64(GUEST_IA32_PAT, data);
2195                         vcpu->arch.pat = data;
2196                         break;
2197                 }
2198                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2199                 break;
2200         case MSR_TSC_AUX:
2201                 if (!vmx->rdtscp_enabled)
2202                         return 1;
2203                 /* Check reserved bit, higher 32 bits should be zero */
2204                 if ((data >> 32) != 0)
2205                         return 1;
2206                 /* Otherwise falls through */
2207         default:
2208                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2209                         break;
2210                 msr = find_msr_entry(vmx, msr_index);
2211                 if (msr) {
2212                         msr->data = data;
2213                         if (msr - vmx->guest_msrs < vmx->save_nmsrs)
2214                                 kvm_set_shared_msr(msr->index, msr->data,
2215                                                    msr->mask);
2216                         break;
2217                 }
2218                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2219         }
2220
2221         return ret;
2222 }
2223
2224 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2225 {
2226         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2227         switch (reg) {
2228         case VCPU_REGS_RSP:
2229                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2230                 break;
2231         case VCPU_REGS_RIP:
2232                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2233                 break;
2234         case VCPU_EXREG_PDPTR:
2235                 if (enable_ept)
2236                         ept_save_pdptrs(vcpu);
2237                 break;
2238         default:
2239                 break;
2240         }
2241 }
2242
2243 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2244 {
2245         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2246                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2247         else
2248                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2249
2250         update_exception_bitmap(vcpu);
2251 }
2252
2253 static __init int cpu_has_kvm_support(void)
2254 {
2255         return cpu_has_vmx();
2256 }
2257
2258 static __init int vmx_disabled_by_bios(void)
2259 {
2260         u64 msr;
2261
2262         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2263         if (msr & FEATURE_CONTROL_LOCKED) {
2264                 /* launched w/ TXT and VMX disabled */
2265                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2266                         && tboot_enabled())
2267                         return 1;
2268                 /* launched w/o TXT and VMX only enabled w/ TXT */
2269                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2270                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2271                         && !tboot_enabled()) {
2272                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2273                                 "activate TXT before enabling KVM\n");
2274                         return 1;
2275                 }
2276                 /* launched w/o TXT and VMX disabled */
2277                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2278                         && !tboot_enabled())
2279                         return 1;
2280         }
2281
2282         return 0;
2283 }
2284
2285 static void kvm_cpu_vmxon(u64 addr)
2286 {
2287         asm volatile (ASM_VMX_VMXON_RAX
2288                         : : "a"(&addr), "m"(addr)
2289                         : "memory", "cc");
2290 }
2291
2292 static int hardware_enable(void *garbage)
2293 {
2294         int cpu = raw_smp_processor_id();
2295         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2296         u64 old, test_bits;
2297
2298         if (read_cr4() & X86_CR4_VMXE)
2299                 return -EBUSY;
2300
2301         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2302         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2303
2304         test_bits = FEATURE_CONTROL_LOCKED;
2305         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2306         if (tboot_enabled())
2307                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2308
2309         if ((old & test_bits) != test_bits) {
2310                 /* enable and lock */
2311                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2312         }
2313         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2314
2315         if (vmm_exclusive) {
2316                 kvm_cpu_vmxon(phys_addr);
2317                 ept_sync_global();
2318         }
2319
2320         store_gdt(&__get_cpu_var(host_gdt));
2321
2322         return 0;
2323 }
2324
2325 static void vmclear_local_loaded_vmcss(void)
2326 {
2327         int cpu = raw_smp_processor_id();
2328         struct loaded_vmcs *v, *n;
2329
2330         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2331                                  loaded_vmcss_on_cpu_link)
2332                 __loaded_vmcs_clear(v);
2333 }
2334
2335
2336 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2337  * tricks.
2338  */
2339 static void kvm_cpu_vmxoff(void)
2340 {
2341         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2342 }
2343
2344 static void hardware_disable(void *garbage)
2345 {
2346         if (vmm_exclusive) {
2347                 vmclear_local_loaded_vmcss();
2348                 kvm_cpu_vmxoff();
2349         }
2350         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2351 }
2352
2353 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2354                                       u32 msr, u32 *result)
2355 {
2356         u32 vmx_msr_low, vmx_msr_high;
2357         u32 ctl = ctl_min | ctl_opt;
2358
2359         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2360
2361         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2362         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2363
2364         /* Ensure minimum (required) set of control bits are supported. */
2365         if (ctl_min & ~ctl)
2366                 return -EIO;
2367
2368         *result = ctl;
2369         return 0;
2370 }
2371
2372 static __init bool allow_1_setting(u32 msr, u32 ctl)
2373 {
2374         u32 vmx_msr_low, vmx_msr_high;
2375
2376         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2377         return vmx_msr_high & ctl;
2378 }
2379
2380 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2381 {
2382         u32 vmx_msr_low, vmx_msr_high;
2383         u32 min, opt, min2, opt2;
2384         u32 _pin_based_exec_control = 0;
2385         u32 _cpu_based_exec_control = 0;
2386         u32 _cpu_based_2nd_exec_control = 0;
2387         u32 _vmexit_control = 0;
2388         u32 _vmentry_control = 0;
2389
2390         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2391         opt = PIN_BASED_VIRTUAL_NMIS;
2392         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2393                                 &_pin_based_exec_control) < 0)
2394                 return -EIO;
2395
2396         min = CPU_BASED_HLT_EXITING |
2397 #ifdef CONFIG_X86_64
2398               CPU_BASED_CR8_LOAD_EXITING |
2399               CPU_BASED_CR8_STORE_EXITING |
2400 #endif
2401               CPU_BASED_CR3_LOAD_EXITING |
2402               CPU_BASED_CR3_STORE_EXITING |
2403               CPU_BASED_USE_IO_BITMAPS |
2404               CPU_BASED_MOV_DR_EXITING |
2405               CPU_BASED_USE_TSC_OFFSETING |
2406               CPU_BASED_MWAIT_EXITING |
2407               CPU_BASED_MONITOR_EXITING |
2408               CPU_BASED_INVLPG_EXITING |
2409               CPU_BASED_RDPMC_EXITING;
2410
2411         opt = CPU_BASED_TPR_SHADOW |
2412               CPU_BASED_USE_MSR_BITMAPS |
2413               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2414         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2415                                 &_cpu_based_exec_control) < 0)
2416                 return -EIO;
2417 #ifdef CONFIG_X86_64
2418         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2419                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2420                                            ~CPU_BASED_CR8_STORE_EXITING;
2421 #endif
2422         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2423                 min2 = 0;
2424                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2425                         SECONDARY_EXEC_WBINVD_EXITING |
2426                         SECONDARY_EXEC_ENABLE_VPID |
2427                         SECONDARY_EXEC_ENABLE_EPT |
2428                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2429                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2430                         SECONDARY_EXEC_RDTSCP;
2431                 if (adjust_vmx_controls(min2, opt2,
2432                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2433                                         &_cpu_based_2nd_exec_control) < 0)
2434                         return -EIO;
2435         }
2436 #ifndef CONFIG_X86_64
2437         if (!(_cpu_based_2nd_exec_control &
2438                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2439                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2440 #endif
2441         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2442                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2443                    enabled */
2444                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2445                                              CPU_BASED_CR3_STORE_EXITING |
2446                                              CPU_BASED_INVLPG_EXITING);
2447                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2448                       vmx_capability.ept, vmx_capability.vpid);
2449         }
2450
2451         min = 0;
2452 #ifdef CONFIG_X86_64
2453         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2454 #endif
2455         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2456         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2457                                 &_vmexit_control) < 0)
2458                 return -EIO;
2459
2460         min = 0;
2461         opt = VM_ENTRY_LOAD_IA32_PAT;
2462         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2463                                 &_vmentry_control) < 0)
2464                 return -EIO;
2465
2466         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2467
2468         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2469         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2470                 return -EIO;
2471
2472 #ifdef CONFIG_X86_64
2473         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2474         if (vmx_msr_high & (1u<<16))
2475                 return -EIO;
2476 #endif
2477
2478         /* Require Write-Back (WB) memory type for VMCS accesses. */
2479         if (((vmx_msr_high >> 18) & 15) != 6)
2480                 return -EIO;
2481
2482         vmcs_conf->size = vmx_msr_high & 0x1fff;
2483         vmcs_conf->order = get_order(vmcs_config.size);
2484         vmcs_conf->revision_id = vmx_msr_low;
2485
2486         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2487         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2488         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2489         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2490         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2491
2492         cpu_has_load_ia32_efer =
2493                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2494                                 VM_ENTRY_LOAD_IA32_EFER)
2495                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2496                                    VM_EXIT_LOAD_IA32_EFER);
2497
2498         cpu_has_load_perf_global_ctrl =
2499                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2500                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2501                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2502                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2503
2504         /*
2505          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2506          * but due to arrata below it can't be used. Workaround is to use
2507          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2508          *
2509          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2510          *
2511          * AAK155             (model 26)
2512          * AAP115             (model 30)
2513          * AAT100             (model 37)
2514          * BC86,AAY89,BD102   (model 44)
2515          * BA97               (model 46)
2516          *
2517          */
2518         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2519                 switch (boot_cpu_data.x86_model) {
2520                 case 26:
2521                 case 30:
2522                 case 37:
2523                 case 44:
2524                 case 46:
2525                         cpu_has_load_perf_global_ctrl = false;
2526                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2527                                         "does not work properly. Using workaround\n");
2528                         break;
2529                 default:
2530                         break;
2531                 }
2532         }
2533
2534         return 0;
2535 }
2536
2537 static struct vmcs *alloc_vmcs_cpu(int cpu)
2538 {
2539         int node = cpu_to_node(cpu);
2540         struct page *pages;
2541         struct vmcs *vmcs;
2542
2543         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2544         if (!pages)
2545                 return NULL;
2546         vmcs = page_address(pages);
2547         memset(vmcs, 0, vmcs_config.size);
2548         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2549         return vmcs;
2550 }
2551
2552 static struct vmcs *alloc_vmcs(void)
2553 {
2554         return alloc_vmcs_cpu(raw_smp_processor_id());
2555 }
2556
2557 static void free_vmcs(struct vmcs *vmcs)
2558 {
2559         free_pages((unsigned long)vmcs, vmcs_config.order);
2560 }
2561
2562 /*
2563  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2564  */
2565 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2566 {
2567         if (!loaded_vmcs->vmcs)
2568                 return;
2569         loaded_vmcs_clear(loaded_vmcs);
2570         free_vmcs(loaded_vmcs->vmcs);
2571         loaded_vmcs->vmcs = NULL;
2572 }
2573
2574 static void free_kvm_area(void)
2575 {
2576         int cpu;
2577
2578         for_each_possible_cpu(cpu) {
2579                 free_vmcs(per_cpu(vmxarea, cpu));
2580                 per_cpu(vmxarea, cpu) = NULL;
2581         }
2582 }
2583
2584 static __init int alloc_kvm_area(void)
2585 {
2586         int cpu;
2587
2588         for_each_possible_cpu(cpu) {
2589                 struct vmcs *vmcs;
2590
2591                 vmcs = alloc_vmcs_cpu(cpu);
2592                 if (!vmcs) {
2593                         free_kvm_area();
2594                         return -ENOMEM;
2595                 }
2596
2597                 per_cpu(vmxarea, cpu) = vmcs;
2598         }
2599         return 0;
2600 }
2601
2602 static __init int hardware_setup(void)
2603 {
2604         if (setup_vmcs_config(&vmcs_config) < 0)
2605                 return -EIO;
2606
2607         if (boot_cpu_has(X86_FEATURE_NX))
2608                 kvm_enable_efer_bits(EFER_NX);
2609
2610         if (!cpu_has_vmx_vpid())
2611                 enable_vpid = 0;
2612
2613         if (!cpu_has_vmx_ept() ||
2614             !cpu_has_vmx_ept_4levels()) {
2615                 enable_ept = 0;
2616                 enable_unrestricted_guest = 0;
2617         }
2618
2619         if (!cpu_has_vmx_unrestricted_guest())
2620                 enable_unrestricted_guest = 0;
2621
2622         if (!cpu_has_vmx_flexpriority())
2623                 flexpriority_enabled = 0;
2624
2625         if (!cpu_has_vmx_tpr_shadow())
2626                 kvm_x86_ops->update_cr8_intercept = NULL;
2627
2628         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2629                 kvm_disable_largepages();
2630
2631         if (!cpu_has_vmx_ple())
2632                 ple_gap = 0;
2633
2634         if (nested)
2635                 nested_vmx_setup_ctls_msrs();
2636
2637         return alloc_kvm_area();
2638 }
2639
2640 static __exit void hardware_unsetup(void)
2641 {
2642         free_kvm_area();
2643 }
2644
2645 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2646 {
2647         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2648
2649         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2650                 vmcs_write16(sf->selector, save->selector);
2651                 vmcs_writel(sf->base, save->base);
2652                 vmcs_write32(sf->limit, save->limit);
2653                 vmcs_write32(sf->ar_bytes, save->ar);
2654         } else {
2655                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2656                         << AR_DPL_SHIFT;
2657                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2658         }
2659 }
2660
2661 static void enter_pmode(struct kvm_vcpu *vcpu)
2662 {
2663         unsigned long flags;
2664         struct vcpu_vmx *vmx = to_vmx(vcpu);
2665
2666         vmx->emulation_required = 1;
2667         vmx->rmode.vm86_active = 0;
2668
2669         vmx_segment_cache_clear(vmx);
2670
2671         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2672         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2673         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2674         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2675
2676         flags = vmcs_readl(GUEST_RFLAGS);
2677         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2678         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2679         vmcs_writel(GUEST_RFLAGS, flags);
2680
2681         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2682                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2683
2684         update_exception_bitmap(vcpu);
2685
2686         if (emulate_invalid_guest_state)
2687                 return;
2688
2689         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2690         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2691         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2692         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2693
2694         vmx_segment_cache_clear(vmx);
2695
2696         vmcs_write16(GUEST_SS_SELECTOR, 0);
2697         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2698
2699         vmcs_write16(GUEST_CS_SELECTOR,
2700                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2701         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2702 }
2703
2704 static gva_t rmode_tss_base(struct kvm *kvm)
2705 {
2706         if (!kvm->arch.tss_addr) {
2707                 struct kvm_memslots *slots;
2708                 struct kvm_memory_slot *slot;
2709                 gfn_t base_gfn;
2710
2711                 slots = kvm_memslots(kvm);
2712                 slot = id_to_memslot(slots, 0);
2713                 base_gfn = slot->base_gfn + slot->npages - 3;
2714
2715                 return base_gfn << PAGE_SHIFT;
2716         }
2717         return kvm->arch.tss_addr;
2718 }
2719
2720 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2721 {
2722         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2723
2724         save->selector = vmcs_read16(sf->selector);
2725         save->base = vmcs_readl(sf->base);
2726         save->limit = vmcs_read32(sf->limit);
2727         save->ar = vmcs_read32(sf->ar_bytes);
2728         vmcs_write16(sf->selector, save->base >> 4);
2729         vmcs_write32(sf->base, save->base & 0xffff0);
2730         vmcs_write32(sf->limit, 0xffff);
2731         vmcs_write32(sf->ar_bytes, 0xf3);
2732         if (save->base & 0xf)
2733                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2734                             " aligned when entering protected mode (seg=%d)",
2735                             seg);
2736 }
2737
2738 static void enter_rmode(struct kvm_vcpu *vcpu)
2739 {
2740         unsigned long flags;
2741         struct vcpu_vmx *vmx = to_vmx(vcpu);
2742
2743         if (enable_unrestricted_guest)
2744                 return;
2745
2746         vmx->emulation_required = 1;
2747         vmx->rmode.vm86_active = 1;
2748
2749         /*
2750          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2751          * vcpu. Call it here with phys address pointing 16M below 4G.
2752          */
2753         if (!vcpu->kvm->arch.tss_addr) {
2754                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2755                              "called before entering vcpu\n");
2756                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2757                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2758                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2759         }
2760
2761         vmx_segment_cache_clear(vmx);
2762
2763         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2764         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2765         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2766
2767         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2768         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2769
2770         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2771         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2772
2773         flags = vmcs_readl(GUEST_RFLAGS);
2774         vmx->rmode.save_rflags = flags;
2775
2776         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2777
2778         vmcs_writel(GUEST_RFLAGS, flags);
2779         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2780         update_exception_bitmap(vcpu);
2781
2782         if (emulate_invalid_guest_state)
2783                 goto continue_rmode;
2784
2785         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2786         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2787         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2788
2789         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2790         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2791         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2792                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2793         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2794
2795         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2796         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2797         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2798         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2799
2800 continue_rmode:
2801         kvm_mmu_reset_context(vcpu);
2802 }
2803
2804 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2805 {
2806         struct vcpu_vmx *vmx = to_vmx(vcpu);
2807         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2808
2809         if (!msr)
2810                 return;
2811
2812         /*
2813          * Force kernel_gs_base reloading before EFER changes, as control
2814          * of this msr depends on is_long_mode().
2815          */
2816         vmx_load_host_state(to_vmx(vcpu));
2817         vcpu->arch.efer = efer;
2818         if (efer & EFER_LMA) {
2819                 vmcs_write32(VM_ENTRY_CONTROLS,
2820                              vmcs_read32(VM_ENTRY_CONTROLS) |
2821                              VM_ENTRY_IA32E_MODE);
2822                 msr->data = efer;
2823         } else {
2824                 vmcs_write32(VM_ENTRY_CONTROLS,
2825                              vmcs_read32(VM_ENTRY_CONTROLS) &
2826                              ~VM_ENTRY_IA32E_MODE);
2827
2828                 msr->data = efer & ~EFER_LME;
2829         }
2830         setup_msrs(vmx);
2831 }
2832
2833 #ifdef CONFIG_X86_64
2834
2835 static void enter_lmode(struct kvm_vcpu *vcpu)
2836 {
2837         u32 guest_tr_ar;
2838
2839         vmx_segment_cache_clear(to_vmx(vcpu));
2840
2841         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2842         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2843                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2844                                      __func__);
2845                 vmcs_write32(GUEST_TR_AR_BYTES,
2846                              (guest_tr_ar & ~AR_TYPE_MASK)
2847                              | AR_TYPE_BUSY_64_TSS);
2848         }
2849         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2850 }
2851
2852 static void exit_lmode(struct kvm_vcpu *vcpu)
2853 {
2854         vmcs_write32(VM_ENTRY_CONTROLS,
2855                      vmcs_read32(VM_ENTRY_CONTROLS)
2856                      & ~VM_ENTRY_IA32E_MODE);
2857         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2858 }
2859
2860 #endif
2861
2862 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2863 {
2864         vpid_sync_context(to_vmx(vcpu));
2865         if (enable_ept) {
2866                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2867                         return;
2868                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2869         }
2870 }
2871
2872 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2873 {
2874         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2875
2876         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2877         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2878 }
2879
2880 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2881 {
2882         if (enable_ept && is_paging(vcpu))
2883                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2884         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2885 }
2886
2887 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2888 {
2889         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2890
2891         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2892         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2893 }
2894
2895 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2896 {
2897         if (!test_bit(VCPU_EXREG_PDPTR,
2898                       (unsigned long *)&vcpu->arch.regs_dirty))
2899                 return;
2900
2901         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2902                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2903                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2904                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2905                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2906         }
2907 }
2908
2909 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2910 {
2911         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2912                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2913                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2914                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2915                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2916         }
2917
2918         __set_bit(VCPU_EXREG_PDPTR,
2919                   (unsigned long *)&vcpu->arch.regs_avail);
2920         __set_bit(VCPU_EXREG_PDPTR,
2921                   (unsigned long *)&vcpu->arch.regs_dirty);
2922 }
2923
2924 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2925
2926 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2927                                         unsigned long cr0,
2928                                         struct kvm_vcpu *vcpu)
2929 {
2930         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2931                 vmx_decache_cr3(vcpu);
2932         if (!(cr0 & X86_CR0_PG)) {
2933                 /* From paging/starting to nonpaging */
2934                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2935                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2936                              (CPU_BASED_CR3_LOAD_EXITING |
2937                               CPU_BASED_CR3_STORE_EXITING));
2938                 vcpu->arch.cr0 = cr0;
2939                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2940         } else if (!is_paging(vcpu)) {
2941                 /* From nonpaging to paging */
2942                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2943                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2944                              ~(CPU_BASED_CR3_LOAD_EXITING |
2945                                CPU_BASED_CR3_STORE_EXITING));
2946                 vcpu->arch.cr0 = cr0;
2947                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2948         }
2949
2950         if (!(cr0 & X86_CR0_WP))
2951                 *hw_cr0 &= ~X86_CR0_WP;
2952 }
2953
2954 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2955 {
2956         struct vcpu_vmx *vmx = to_vmx(vcpu);
2957         unsigned long hw_cr0;
2958
2959         if (enable_unrestricted_guest)
2960                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2961                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2962         else
2963                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2964
2965         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2966                 enter_pmode(vcpu);
2967
2968         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2969                 enter_rmode(vcpu);
2970
2971 #ifdef CONFIG_X86_64
2972         if (vcpu->arch.efer & EFER_LME) {
2973                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2974                         enter_lmode(vcpu);
2975                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2976                         exit_lmode(vcpu);
2977         }
2978 #endif
2979
2980         if (enable_ept)
2981                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2982
2983         if (!vcpu->fpu_active)
2984                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2985
2986         vmcs_writel(CR0_READ_SHADOW, cr0);
2987         vmcs_writel(GUEST_CR0, hw_cr0);
2988         vcpu->arch.cr0 = cr0;
2989         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2990 }
2991
2992 static u64 construct_eptp(unsigned long root_hpa)
2993 {
2994         u64 eptp;
2995
2996         /* TODO write the value reading from MSR */
2997         eptp = VMX_EPT_DEFAULT_MT |
2998                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2999         eptp |= (root_hpa & PAGE_MASK);
3000
3001         return eptp;
3002 }
3003
3004 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3005 {
3006         unsigned long guest_cr3;
3007         u64 eptp;
3008
3009         guest_cr3 = cr3;
3010         if (enable_ept) {
3011                 eptp = construct_eptp(cr3);
3012                 vmcs_write64(EPT_POINTER, eptp);
3013                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3014                         vcpu->kvm->arch.ept_identity_map_addr;
3015                 ept_load_pdptrs(vcpu);
3016         }
3017
3018         vmx_flush_tlb(vcpu);
3019         vmcs_writel(GUEST_CR3, guest_cr3);
3020 }
3021
3022 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3023 {
3024         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3025                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3026
3027         if (cr4 & X86_CR4_VMXE) {
3028                 /*
3029                  * To use VMXON (and later other VMX instructions), a guest
3030                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3031                  * So basically the check on whether to allow nested VMX
3032                  * is here.
3033                  */
3034                 if (!nested_vmx_allowed(vcpu))
3035                         return 1;
3036         } else if (to_vmx(vcpu)->nested.vmxon)
3037                 return 1;
3038
3039         vcpu->arch.cr4 = cr4;
3040         if (enable_ept) {
3041                 if (!is_paging(vcpu)) {
3042                         hw_cr4 &= ~X86_CR4_PAE;
3043                         hw_cr4 |= X86_CR4_PSE;
3044                 } else if (!(cr4 & X86_CR4_PAE)) {
3045                         hw_cr4 &= ~X86_CR4_PAE;
3046                 }
3047         }
3048
3049         vmcs_writel(CR4_READ_SHADOW, cr4);
3050         vmcs_writel(GUEST_CR4, hw_cr4);
3051         return 0;
3052 }
3053
3054 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3055                             struct kvm_segment *var, int seg)
3056 {
3057         struct vcpu_vmx *vmx = to_vmx(vcpu);
3058         struct kvm_save_segment *save;
3059         u32 ar;
3060
3061         if (vmx->rmode.vm86_active
3062             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3063                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3064                 || seg == VCPU_SREG_GS)
3065             && !emulate_invalid_guest_state) {
3066                 switch (seg) {
3067                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3068                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3069                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3070                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3071                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3072                 default: BUG();
3073                 }
3074                 var->selector = save->selector;
3075                 var->base = save->base;
3076                 var->limit = save->limit;
3077                 ar = save->ar;
3078                 if (seg == VCPU_SREG_TR
3079                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3080                         goto use_saved_rmode_seg;
3081         }
3082         var->base = vmx_read_guest_seg_base(vmx, seg);
3083         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3084         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3085         ar = vmx_read_guest_seg_ar(vmx, seg);
3086 use_saved_rmode_seg:
3087         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3088                 ar = 0;
3089         var->type = ar & 15;
3090         var->s = (ar >> 4) & 1;
3091         var->dpl = (ar >> 5) & 3;
3092         var->present = (ar >> 7) & 1;
3093         var->avl = (ar >> 12) & 1;
3094         var->l = (ar >> 13) & 1;
3095         var->db = (ar >> 14) & 1;
3096         var->g = (ar >> 15) & 1;
3097         var->unusable = (ar >> 16) & 1;
3098 }
3099
3100 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3101 {
3102         struct kvm_segment s;
3103
3104         if (to_vmx(vcpu)->rmode.vm86_active) {
3105                 vmx_get_segment(vcpu, &s, seg);
3106                 return s.base;
3107         }
3108         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3109 }
3110
3111 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3112 {
3113         if (!is_protmode(vcpu))
3114                 return 0;
3115
3116         if (!is_long_mode(vcpu)
3117             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3118                 return 3;
3119
3120         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3121 }
3122
3123 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3124 {
3125         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3126                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3127                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3128         }
3129         return to_vmx(vcpu)->cpl;
3130 }
3131
3132
3133 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3134 {
3135         u32 ar;
3136
3137         if (var->unusable)
3138                 ar = 1 << 16;
3139         else {
3140                 ar = var->type & 15;
3141                 ar |= (var->s & 1) << 4;
3142                 ar |= (var->dpl & 3) << 5;
3143                 ar |= (var->present & 1) << 7;
3144                 ar |= (var->avl & 1) << 12;
3145                 ar |= (var->l & 1) << 13;
3146                 ar |= (var->db & 1) << 14;
3147                 ar |= (var->g & 1) << 15;
3148         }
3149         if (ar == 0) /* a 0 value means unusable */
3150                 ar = AR_UNUSABLE_MASK;
3151
3152         return ar;
3153 }
3154
3155 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3156                             struct kvm_segment *var, int seg)
3157 {
3158         struct vcpu_vmx *vmx = to_vmx(vcpu);
3159         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3160         u32 ar;
3161
3162         vmx_segment_cache_clear(vmx);
3163
3164         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3165                 vmcs_write16(sf->selector, var->selector);
3166                 vmx->rmode.tr.selector = var->selector;
3167                 vmx->rmode.tr.base = var->base;
3168                 vmx->rmode.tr.limit = var->limit;
3169                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3170                 return;
3171         }
3172         vmcs_writel(sf->base, var->base);
3173         vmcs_write32(sf->limit, var->limit);
3174         vmcs_write16(sf->selector, var->selector);
3175         if (vmx->rmode.vm86_active && var->s) {
3176                 /*
3177                  * Hack real-mode segments into vm86 compatibility.
3178                  */
3179                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3180                         vmcs_writel(sf->base, 0xf0000);
3181                 ar = 0xf3;
3182         } else
3183                 ar = vmx_segment_access_rights(var);
3184
3185         /*
3186          *   Fix the "Accessed" bit in AR field of segment registers for older
3187          * qemu binaries.
3188          *   IA32 arch specifies that at the time of processor reset the
3189          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3190          * is setting it to 0 in the usedland code. This causes invalid guest
3191          * state vmexit when "unrestricted guest" mode is turned on.
3192          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3193          * tree. Newer qemu binaries with that qemu fix would not need this
3194          * kvm hack.
3195          */
3196         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3197                 ar |= 0x1; /* Accessed */
3198
3199         vmcs_write32(sf->ar_bytes, ar);
3200         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3201 }
3202
3203 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3204 {
3205         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3206
3207         *db = (ar >> 14) & 1;
3208         *l = (ar >> 13) & 1;
3209 }
3210
3211 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3212 {
3213         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3214         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3215 }
3216
3217 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3218 {
3219         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3220         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3221 }
3222
3223 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3224 {
3225         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3226         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3227 }
3228
3229 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3230 {
3231         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3232         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3233 }
3234
3235 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3236 {
3237         struct kvm_segment var;
3238         u32 ar;
3239
3240         vmx_get_segment(vcpu, &var, seg);
3241         ar = vmx_segment_access_rights(&var);
3242
3243         if (var.base != (var.selector << 4))
3244                 return false;
3245         if (var.limit != 0xffff)
3246                 return false;
3247         if (ar != 0xf3)
3248                 return false;
3249
3250         return true;
3251 }
3252
3253 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3254 {
3255         struct kvm_segment cs;
3256         unsigned int cs_rpl;
3257
3258         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3259         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3260
3261         if (cs.unusable)
3262                 return false;
3263         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3264                 return false;
3265         if (!cs.s)
3266                 return false;
3267         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3268                 if (cs.dpl > cs_rpl)
3269                         return false;
3270         } else {
3271                 if (cs.dpl != cs_rpl)
3272                         return false;
3273         }
3274         if (!cs.present)
3275                 return false;
3276
3277         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3278         return true;
3279 }
3280
3281 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3282 {
3283         struct kvm_segment ss;
3284         unsigned int ss_rpl;
3285
3286         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3287         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3288
3289         if (ss.unusable)
3290                 return true;
3291         if (ss.type != 3 && ss.type != 7)
3292                 return false;
3293         if (!ss.s)
3294                 return false;
3295         if (ss.dpl != ss_rpl) /* DPL != RPL */
3296                 return false;
3297         if (!ss.present)
3298                 return false;
3299
3300         return true;
3301 }
3302
3303 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3304 {
3305         struct kvm_segment var;
3306         unsigned int rpl;
3307
3308         vmx_get_segment(vcpu, &var, seg);
3309         rpl = var.selector & SELECTOR_RPL_MASK;
3310
3311         if (var.unusable)
3312                 return true;
3313         if (!var.s)
3314                 return false;
3315         if (!var.present)
3316                 return false;
3317         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3318                 if (var.dpl < rpl) /* DPL < RPL */
3319                         return false;
3320         }
3321
3322         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3323          * rights flags
3324          */
3325         return true;
3326 }
3327
3328 static bool tr_valid(struct kvm_vcpu *vcpu)
3329 {
3330         struct kvm_segment tr;
3331
3332         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3333
3334         if (tr.unusable)
3335                 return false;
3336         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3337                 return false;
3338         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3339                 return false;
3340         if (!tr.present)
3341                 return false;
3342
3343         return true;
3344 }
3345
3346 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3347 {
3348         struct kvm_segment ldtr;
3349
3350         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3351
3352         if (ldtr.unusable)
3353                 return true;
3354         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3355                 return false;
3356         if (ldtr.type != 2)
3357                 return false;
3358         if (!ldtr.present)
3359                 return false;
3360
3361         return true;
3362 }
3363
3364 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3365 {
3366         struct kvm_segment cs, ss;
3367
3368         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3369         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3370
3371         return ((cs.selector & SELECTOR_RPL_MASK) ==
3372                  (ss.selector & SELECTOR_RPL_MASK));
3373 }
3374
3375 /*
3376  * Check if guest state is valid. Returns true if valid, false if
3377  * not.
3378  * We assume that registers are always usable
3379  */
3380 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3381 {
3382         /* real mode guest state checks */
3383         if (!is_protmode(vcpu)) {
3384                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3385                         return false;
3386                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3387                         return false;
3388                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3389                         return false;
3390                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3391                         return false;
3392                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3393                         return false;
3394                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3395                         return false;
3396         } else {
3397         /* protected mode guest state checks */
3398                 if (!cs_ss_rpl_check(vcpu))
3399                         return false;
3400                 if (!code_segment_valid(vcpu))
3401                         return false;
3402                 if (!stack_segment_valid(vcpu))
3403                         return false;
3404                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3405                         return false;
3406                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3407                         return false;
3408                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3409                         return false;
3410                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3411                         return false;
3412                 if (!tr_valid(vcpu))
3413                         return false;
3414                 if (!ldtr_valid(vcpu))
3415                         return false;
3416         }
3417         /* TODO:
3418          * - Add checks on RIP
3419          * - Add checks on RFLAGS
3420          */
3421
3422         return true;
3423 }
3424
3425 static int init_rmode_tss(struct kvm *kvm)
3426 {
3427         gfn_t fn;
3428         u16 data = 0;
3429         int r, idx, ret = 0;
3430
3431         idx = srcu_read_lock(&kvm->srcu);
3432         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3433         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3434         if (r < 0)
3435                 goto out;
3436         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3437         r = kvm_write_guest_page(kvm, fn++, &data,
3438                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3439         if (r < 0)
3440                 goto out;
3441         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3442         if (r < 0)
3443                 goto out;
3444         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3445         if (r < 0)
3446                 goto out;
3447         data = ~0;
3448         r = kvm_write_guest_page(kvm, fn, &data,
3449                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3450                                  sizeof(u8));
3451         if (r < 0)
3452                 goto out;
3453
3454         ret = 1;
3455 out:
3456         srcu_read_unlock(&kvm->srcu, idx);
3457         return ret;
3458 }
3459
3460 static int init_rmode_identity_map(struct kvm *kvm)
3461 {
3462         int i, idx, r, ret;
3463         pfn_t identity_map_pfn;
3464         u32 tmp;
3465
3466         if (!enable_ept)
3467                 return 1;
3468         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3469                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3470                         "haven't been allocated!\n");
3471                 return 0;
3472         }
3473         if (likely(kvm->arch.ept_identity_pagetable_done))
3474                 return 1;
3475         ret = 0;
3476         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3477         idx = srcu_read_lock(&kvm->srcu);
3478         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3479         if (r < 0)
3480                 goto out;
3481         /* Set up identity-mapping pagetable for EPT in real mode */
3482         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3483                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3484                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3485                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3486                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3487                 if (r < 0)
3488                         goto out;
3489         }
3490         kvm->arch.ept_identity_pagetable_done = true;
3491         ret = 1;
3492 out:
3493         srcu_read_unlock(&kvm->srcu, idx);
3494         return ret;
3495 }
3496
3497 static void seg_setup(int seg)
3498 {
3499         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3500         unsigned int ar;
3501
3502         vmcs_write16(sf->selector, 0);
3503         vmcs_writel(sf->base, 0);
3504         vmcs_write32(sf->limit, 0xffff);
3505         if (enable_unrestricted_guest) {
3506                 ar = 0x93;
3507                 if (seg == VCPU_SREG_CS)
3508                         ar |= 0x08; /* code segment */
3509         } else
3510                 ar = 0xf3;
3511
3512         vmcs_write32(sf->ar_bytes, ar);
3513 }
3514
3515 static int alloc_apic_access_page(struct kvm *kvm)
3516 {
3517         struct kvm_userspace_memory_region kvm_userspace_mem;
3518         int r = 0;
3519
3520         mutex_lock(&kvm->slots_lock);
3521         if (kvm->arch.apic_access_page)
3522                 goto out;
3523         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3524         kvm_userspace_mem.flags = 0;
3525         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3526         kvm_userspace_mem.memory_size = PAGE_SIZE;
3527         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3528         if (r)
3529                 goto out;
3530
3531         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3532 out:
3533         mutex_unlock(&kvm->slots_lock);
3534         return r;
3535 }
3536
3537 static int alloc_identity_pagetable(struct kvm *kvm)
3538 {
3539         struct kvm_userspace_memory_region kvm_userspace_mem;
3540         int r = 0;
3541
3542         mutex_lock(&kvm->slots_lock);
3543         if (kvm->arch.ept_identity_pagetable)
3544                 goto out;
3545         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3546         kvm_userspace_mem.flags = 0;
3547         kvm_userspace_mem.guest_phys_addr =
3548                 kvm->arch.ept_identity_map_addr;
3549         kvm_userspace_mem.memory_size = PAGE_SIZE;
3550         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3551         if (r)
3552                 goto out;
3553
3554         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3555                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3556 out:
3557         mutex_unlock(&kvm->slots_lock);
3558         return r;
3559 }
3560
3561 static void allocate_vpid(struct vcpu_vmx *vmx)
3562 {
3563         int vpid;
3564
3565         vmx->vpid = 0;
3566         if (!enable_vpid)
3567                 return;
3568         spin_lock(&vmx_vpid_lock);
3569         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3570         if (vpid < VMX_NR_VPIDS) {
3571                 vmx->vpid = vpid;
3572                 __set_bit(vpid, vmx_vpid_bitmap);
3573         }
3574         spin_unlock(&vmx_vpid_lock);
3575 }
3576
3577 static void free_vpid(struct vcpu_vmx *vmx)
3578 {
3579         if (!enable_vpid)
3580                 return;
3581         spin_lock(&vmx_vpid_lock);
3582         if (vmx->vpid != 0)
3583                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3584         spin_unlock(&vmx_vpid_lock);
3585 }
3586
3587 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3588 {
3589         int f = sizeof(unsigned long);
3590
3591         if (!cpu_has_vmx_msr_bitmap())
3592                 return;
3593
3594         /*
3595          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3596          * have the write-low and read-high bitmap offsets the wrong way round.
3597          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3598          */
3599         if (msr <= 0x1fff) {
3600                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3601                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3602         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3603                 msr &= 0x1fff;
3604                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3605                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3606         }
3607 }
3608
3609 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3610 {
3611         if (!longmode_only)
3612                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3613         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3614 }
3615
3616 /*
3617  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3618  * will not change in the lifetime of the guest.
3619  * Note that host-state that does change is set elsewhere. E.g., host-state
3620  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3621  */
3622 static void vmx_set_constant_host_state(void)
3623 {
3624         u32 low32, high32;
3625         unsigned long tmpl;
3626         struct desc_ptr dt;
3627
3628         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3629         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3630         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3631
3632         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3633         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3634         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3635         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3636         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3637
3638         native_store_idt(&dt);
3639         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3640
3641         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3642         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3643
3644         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3645         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3646         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3647         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3648
3649         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3650                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3651                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3652         }
3653 }
3654
3655 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3656 {
3657         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3658         if (enable_ept)
3659                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3660         if (is_guest_mode(&vmx->vcpu))
3661                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3662                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3663         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3664 }
3665
3666 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3667 {
3668         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3669         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3670                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3671 #ifdef CONFIG_X86_64
3672                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3673                                 CPU_BASED_CR8_LOAD_EXITING;
3674 #endif
3675         }
3676         if (!enable_ept)
3677                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3678                                 CPU_BASED_CR3_LOAD_EXITING  |
3679                                 CPU_BASED_INVLPG_EXITING;
3680         return exec_control;
3681 }
3682
3683 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3684 {
3685         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3686         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3687                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3688         if (vmx->vpid == 0)
3689                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3690         if (!enable_ept) {
3691                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3692                 enable_unrestricted_guest = 0;
3693         }
3694         if (!enable_unrestricted_guest)
3695                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3696         if (!ple_gap)
3697                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3698         return exec_control;
3699 }
3700
3701 static void ept_set_mmio_spte_mask(void)
3702 {
3703         /*
3704          * EPT Misconfigurations can be generated if the value of bits 2:0
3705          * of an EPT paging-structure entry is 110b (write/execute).
3706          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3707          * spte.
3708          */
3709         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3710 }
3711
3712 /*
3713  * Sets up the vmcs for emulated real mode.
3714  */
3715 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3716 {
3717 #ifdef CONFIG_X86_64
3718         unsigned long a;
3719 #endif
3720         int i;
3721
3722         /* I/O */
3723         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3724         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3725
3726         if (cpu_has_vmx_msr_bitmap())
3727                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3728
3729         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3730
3731         /* Control */
3732         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3733                 vmcs_config.pin_based_exec_ctrl);
3734
3735         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3736
3737         if (cpu_has_secondary_exec_ctrls()) {
3738                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3739                                 vmx_secondary_exec_control(vmx));
3740         }
3741
3742         if (ple_gap) {
3743                 vmcs_write32(PLE_GAP, ple_gap);
3744                 vmcs_write32(PLE_WINDOW, ple_window);
3745         }
3746
3747         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3748         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3749         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3750
3751         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3752         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3753         vmx_set_constant_host_state();
3754 #ifdef CONFIG_X86_64
3755         rdmsrl(MSR_FS_BASE, a);
3756         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3757         rdmsrl(MSR_GS_BASE, a);
3758         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3759 #else
3760         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3761         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3762 #endif
3763
3764         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3765         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3766         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3767         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3768         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3769
3770         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3771                 u32 msr_low, msr_high;
3772                 u64 host_pat;
3773                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3774                 host_pat = msr_low | ((u64) msr_high << 32);
3775                 /* Write the default value follow host pat */
3776                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3777                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3778                 vmx->vcpu.arch.pat = host_pat;
3779         }
3780
3781         for (i = 0; i < NR_VMX_MSR; ++i) {
3782                 u32 index = vmx_msr_index[i];
3783                 u32 data_low, data_high;
3784                 int j = vmx->nmsrs;
3785
3786                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3787                         continue;
3788                 if (wrmsr_safe(index, data_low, data_high) < 0)
3789                         continue;
3790                 vmx->guest_msrs[j].index = i;
3791                 vmx->guest_msrs[j].data = 0;
3792                 vmx->guest_msrs[j].mask = -1ull;
3793                 ++vmx->nmsrs;
3794         }
3795
3796         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3797
3798         /* 22.2.1, 20.8.1 */
3799         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3800
3801         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3802         set_cr4_guest_host_mask(vmx);
3803
3804         kvm_write_tsc(&vmx->vcpu, 0);
3805
3806         return 0;
3807 }
3808
3809 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3810 {
3811         struct vcpu_vmx *vmx = to_vmx(vcpu);
3812         u64 msr;
3813         int ret;
3814
3815         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3816
3817         vmx->rmode.vm86_active = 0;
3818
3819         vmx->soft_vnmi_blocked = 0;
3820
3821         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3822         kvm_set_cr8(&vmx->vcpu, 0);
3823         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3824         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3825                 msr |= MSR_IA32_APICBASE_BSP;
3826         kvm_set_apic_base(&vmx->vcpu, msr);
3827
3828         ret = fx_init(&vmx->vcpu);
3829         if (ret != 0)
3830                 goto out;
3831
3832         vmx_segment_cache_clear(vmx);
3833
3834         seg_setup(VCPU_SREG_CS);
3835         /*
3836          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3837          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3838          */
3839         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3840                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3841                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3842         } else {
3843                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3844                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3845         }
3846
3847         seg_setup(VCPU_SREG_DS);
3848         seg_setup(VCPU_SREG_ES);
3849         seg_setup(VCPU_SREG_FS);
3850         seg_setup(VCPU_SREG_GS);
3851         seg_setup(VCPU_SREG_SS);
3852
3853         vmcs_write16(GUEST_TR_SELECTOR, 0);
3854         vmcs_writel(GUEST_TR_BASE, 0);
3855         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3856         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3857
3858         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3859         vmcs_writel(GUEST_LDTR_BASE, 0);
3860         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3861         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3862
3863         vmcs_write32(GUEST_SYSENTER_CS, 0);
3864         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3865         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3866
3867         vmcs_writel(GUEST_RFLAGS, 0x02);
3868         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3869                 kvm_rip_write(vcpu, 0xfff0);
3870         else
3871                 kvm_rip_write(vcpu, 0);
3872         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3873
3874         vmcs_writel(GUEST_DR7, 0x400);
3875
3876         vmcs_writel(GUEST_GDTR_BASE, 0);
3877         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3878
3879         vmcs_writel(GUEST_IDTR_BASE, 0);
3880         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3881
3882         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3883         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3884         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3885
3886         /* Special registers */
3887         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3888
3889         setup_msrs(vmx);
3890
3891         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3892
3893         if (cpu_has_vmx_tpr_shadow()) {
3894                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3895                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3896                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3897                                      __pa(vmx->vcpu.arch.apic->regs));
3898                 vmcs_write32(TPR_THRESHOLD, 0);
3899         }
3900
3901         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3902                 vmcs_write64(APIC_ACCESS_ADDR,
3903                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3904
3905         if (vmx->vpid != 0)
3906                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3907
3908         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3909         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3910         vmx_set_cr4(&vmx->vcpu, 0);
3911         vmx_set_efer(&vmx->vcpu, 0);
3912         vmx_fpu_activate(&vmx->vcpu);
3913         update_exception_bitmap(&vmx->vcpu);
3914
3915         vpid_sync_context(vmx);
3916
3917         ret = 0;
3918
3919         /* HACK: Don't enable emulation on guest boot/reset */
3920         vmx->emulation_required = 0;
3921
3922 out:
3923         return ret;
3924 }
3925
3926 /*
3927  * In nested virtualization, check if L1 asked to exit on external interrupts.
3928  * For most existing hypervisors, this will always return true.
3929  */
3930 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3931 {
3932         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3933                 PIN_BASED_EXT_INTR_MASK;
3934 }
3935
3936 static void enable_irq_window(struct kvm_vcpu *vcpu)
3937 {
3938         u32 cpu_based_vm_exec_control;
3939         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3940                 /*
3941                  * We get here if vmx_interrupt_allowed() said we can't
3942                  * inject to L1 now because L2 must run. Ask L2 to exit
3943                  * right after entry, so we can inject to L1 more promptly.
3944                  */
3945                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
3946                 return;
3947         }
3948
3949         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3950         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3951         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3952 }
3953
3954 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3955 {
3956         u32 cpu_based_vm_exec_control;
3957
3958         if (!cpu_has_virtual_nmis()) {
3959                 enable_irq_window(vcpu);
3960                 return;
3961         }
3962
3963         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3964                 enable_irq_window(vcpu);
3965                 return;
3966         }
3967         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3968         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3969         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3970 }
3971
3972 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3973 {
3974         struct vcpu_vmx *vmx = to_vmx(vcpu);
3975         uint32_t intr;
3976         int irq = vcpu->arch.interrupt.nr;
3977
3978         trace_kvm_inj_virq(irq);
3979
3980         ++vcpu->stat.irq_injections;
3981         if (vmx->rmode.vm86_active) {
3982                 int inc_eip = 0;
3983                 if (vcpu->arch.interrupt.soft)
3984                         inc_eip = vcpu->arch.event_exit_inst_len;
3985                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3986                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3987                 return;
3988         }
3989         intr = irq | INTR_INFO_VALID_MASK;
3990         if (vcpu->arch.interrupt.soft) {
3991                 intr |= INTR_TYPE_SOFT_INTR;
3992                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3993                              vmx->vcpu.arch.event_exit_inst_len);
3994         } else
3995                 intr |= INTR_TYPE_EXT_INTR;
3996         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3997 }
3998
3999 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4000 {
4001         struct vcpu_vmx *vmx = to_vmx(vcpu);
4002
4003         if (is_guest_mode(vcpu))
4004                 return;
4005
4006         if (!cpu_has_virtual_nmis()) {
4007                 /*
4008                  * Tracking the NMI-blocked state in software is built upon
4009                  * finding the next open IRQ window. This, in turn, depends on
4010                  * well-behaving guests: They have to keep IRQs disabled at
4011                  * least as long as the NMI handler runs. Otherwise we may
4012                  * cause NMI nesting, maybe breaking the guest. But as this is
4013                  * highly unlikely, we can live with the residual risk.
4014                  */
4015                 vmx->soft_vnmi_blocked = 1;
4016                 vmx->vnmi_blocked_time = 0;
4017         }
4018
4019         ++vcpu->stat.nmi_injections;
4020         vmx->nmi_known_unmasked = false;
4021         if (vmx->rmode.vm86_active) {
4022                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4023                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4024                 return;
4025         }
4026         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4027                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4028 }
4029
4030 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4031 {
4032         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4033                 return 0;
4034
4035         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4036                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4037                    | GUEST_INTR_STATE_NMI));
4038 }
4039
4040 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4041 {
4042         if (!cpu_has_virtual_nmis())
4043                 return to_vmx(vcpu)->soft_vnmi_blocked;
4044         if (to_vmx(vcpu)->nmi_known_unmasked)
4045                 return false;
4046         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4047 }
4048
4049 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4050 {
4051         struct vcpu_vmx *vmx = to_vmx(vcpu);
4052
4053         if (!cpu_has_virtual_nmis()) {
4054                 if (vmx->soft_vnmi_blocked != masked) {
4055                         vmx->soft_vnmi_blocked = masked;
4056                         vmx->vnmi_blocked_time = 0;
4057                 }
4058         } else {
4059                 vmx->nmi_known_unmasked = !masked;
4060                 if (masked)
4061                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4062                                       GUEST_INTR_STATE_NMI);
4063                 else
4064                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4065                                         GUEST_INTR_STATE_NMI);
4066         }
4067 }
4068
4069 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4070 {
4071         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4072                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4073                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4074                     (vmcs12->idt_vectoring_info_field &
4075                      VECTORING_INFO_VALID_MASK))
4076                         return 0;
4077                 nested_vmx_vmexit(vcpu);
4078                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4079                 vmcs12->vm_exit_intr_info = 0;
4080                 /* fall through to normal code, but now in L1, not L2 */
4081         }
4082
4083         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4084                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4085                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4086 }
4087
4088 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4089 {
4090         int ret;
4091         struct kvm_userspace_memory_region tss_mem = {
4092                 .slot = TSS_PRIVATE_MEMSLOT,
4093                 .guest_phys_addr = addr,
4094                 .memory_size = PAGE_SIZE * 3,
4095                 .flags = 0,
4096         };
4097
4098         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4099         if (ret)
4100                 return ret;
4101         kvm->arch.tss_addr = addr;
4102         if (!init_rmode_tss(kvm))
4103                 return  -ENOMEM;
4104
4105         return 0;
4106 }
4107
4108 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4109                                   int vec, u32 err_code)
4110 {
4111         /*
4112          * Instruction with address size override prefix opcode 0x67
4113          * Cause the #SS fault with 0 error code in VM86 mode.
4114          */
4115         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4116                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4117                         return 1;
4118         /*
4119          * Forward all other exceptions that are valid in real mode.
4120          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4121          *        the required debugging infrastructure rework.
4122          */
4123         switch (vec) {
4124         case DB_VECTOR:
4125                 if (vcpu->guest_debug &
4126                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4127                         return 0;
4128                 kvm_queue_exception(vcpu, vec);
4129                 return 1;
4130         case BP_VECTOR:
4131                 /*
4132                  * Update instruction length as we may reinject the exception
4133                  * from user space while in guest debugging mode.
4134                  */
4135                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4136                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4137                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4138                         return 0;
4139                 /* fall through */
4140         case DE_VECTOR:
4141         case OF_VECTOR:
4142         case BR_VECTOR:
4143         case UD_VECTOR:
4144         case DF_VECTOR:
4145         case SS_VECTOR:
4146         case GP_VECTOR:
4147         case MF_VECTOR:
4148                 kvm_queue_exception(vcpu, vec);
4149                 return 1;
4150         }
4151         return 0;
4152 }
4153
4154 /*
4155  * Trigger machine check on the host. We assume all the MSRs are already set up
4156  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4157  * We pass a fake environment to the machine check handler because we want
4158  * the guest to be always treated like user space, no matter what context
4159  * it used internally.
4160  */
4161 static void kvm_machine_check(void)
4162 {
4163 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4164         struct pt_regs regs = {
4165                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4166                 .flags = X86_EFLAGS_IF,
4167         };
4168
4169         do_machine_check(&regs, 0);
4170 #endif
4171 }
4172
4173 static int handle_machine_check(struct kvm_vcpu *vcpu)
4174 {
4175         /* already handled by vcpu_run */
4176         return 1;
4177 }
4178
4179 static int handle_exception(struct kvm_vcpu *vcpu)
4180 {
4181         struct vcpu_vmx *vmx = to_vmx(vcpu);
4182         struct kvm_run *kvm_run = vcpu->run;
4183         u32 intr_info, ex_no, error_code;
4184         unsigned long cr2, rip, dr6;
4185         u32 vect_info;
4186         enum emulation_result er;
4187
4188         vect_info = vmx->idt_vectoring_info;
4189         intr_info = vmx->exit_intr_info;
4190
4191         if (is_machine_check(intr_info))
4192                 return handle_machine_check(vcpu);
4193
4194         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4195             !is_page_fault(intr_info)) {
4196                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4197                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4198                 vcpu->run->internal.ndata = 2;
4199                 vcpu->run->internal.data[0] = vect_info;
4200                 vcpu->run->internal.data[1] = intr_info;
4201                 return 0;
4202         }
4203
4204         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4205                 return 1;  /* already handled by vmx_vcpu_run() */
4206
4207         if (is_no_device(intr_info)) {
4208                 vmx_fpu_activate(vcpu);
4209                 return 1;
4210         }
4211
4212         if (is_invalid_opcode(intr_info)) {
4213                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4214                 if (er != EMULATE_DONE)
4215                         kvm_queue_exception(vcpu, UD_VECTOR);
4216                 return 1;
4217         }
4218
4219         error_code = 0;
4220         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4221                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4222         if (is_page_fault(intr_info)) {
4223                 /* EPT won't cause page fault directly */
4224                 BUG_ON(enable_ept);
4225                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4226                 trace_kvm_page_fault(cr2, error_code);
4227
4228                 if (kvm_event_needs_reinjection(vcpu))
4229                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4230                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4231         }
4232
4233         if (vmx->rmode.vm86_active &&
4234             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4235                                                                 error_code)) {
4236                 if (vcpu->arch.halt_request) {
4237                         vcpu->arch.halt_request = 0;
4238                         return kvm_emulate_halt(vcpu);
4239                 }
4240                 return 1;
4241         }
4242
4243         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4244         switch (ex_no) {
4245         case DB_VECTOR:
4246                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4247                 if (!(vcpu->guest_debug &
4248                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4249                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4250                         kvm_queue_exception(vcpu, DB_VECTOR);
4251                         return 1;
4252                 }
4253                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4254                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4255                 /* fall through */
4256         case BP_VECTOR:
4257                 /*
4258                  * Update instruction length as we may reinject #BP from
4259                  * user space while in guest debugging mode. Reading it for
4260                  * #DB as well causes no harm, it is not used in that case.
4261                  */
4262                 vmx->vcpu.arch.event_exit_inst_len =
4263                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4264                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4265                 rip = kvm_rip_read(vcpu);
4266                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4267                 kvm_run->debug.arch.exception = ex_no;
4268                 break;
4269         default:
4270                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4271                 kvm_run->ex.exception = ex_no;
4272                 kvm_run->ex.error_code = error_code;
4273                 break;
4274         }
4275         return 0;
4276 }
4277
4278 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4279 {
4280         ++vcpu->stat.irq_exits;
4281         return 1;
4282 }
4283
4284 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4285 {
4286         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4287         return 0;
4288 }
4289
4290 static int handle_io(struct kvm_vcpu *vcpu)
4291 {
4292         unsigned long exit_qualification;
4293         int size, in, string;
4294         unsigned port;
4295
4296         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4297         string = (exit_qualification & 16) != 0;
4298         in = (exit_qualification & 8) != 0;
4299
4300         ++vcpu->stat.io_exits;
4301
4302         if (string || in)
4303                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4304
4305         port = exit_qualification >> 16;
4306         size = (exit_qualification & 7) + 1;
4307         skip_emulated_instruction(vcpu);
4308
4309         return kvm_fast_pio_out(vcpu, size, port);
4310 }
4311
4312 static void
4313 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4314 {
4315         /*
4316          * Patch in the VMCALL instruction:
4317          */
4318         hypercall[0] = 0x0f;
4319         hypercall[1] = 0x01;
4320         hypercall[2] = 0xc1;
4321 }
4322
4323 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4324 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4325 {
4326         if (to_vmx(vcpu)->nested.vmxon &&
4327             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4328                 return 1;
4329
4330         if (is_guest_mode(vcpu)) {
4331                 /*
4332                  * We get here when L2 changed cr0 in a way that did not change
4333                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4334                  * but did change L0 shadowed bits. This can currently happen
4335                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4336                  * loading) while pretending to allow the guest to change it.
4337                  */
4338                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4339                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4340                         return 1;
4341                 vmcs_writel(CR0_READ_SHADOW, val);
4342                 return 0;
4343         } else
4344                 return kvm_set_cr0(vcpu, val);
4345 }
4346
4347 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4348 {
4349         if (is_guest_mode(vcpu)) {
4350                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4351                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4352                         return 1;
4353                 vmcs_writel(CR4_READ_SHADOW, val);
4354                 return 0;
4355         } else
4356                 return kvm_set_cr4(vcpu, val);
4357 }
4358
4359 /* called to set cr0 as approriate for clts instruction exit. */
4360 static void handle_clts(struct kvm_vcpu *vcpu)
4361 {
4362         if (is_guest_mode(vcpu)) {
4363                 /*
4364                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4365                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4366                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4367                  */
4368                 vmcs_writel(CR0_READ_SHADOW,
4369                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4370                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4371         } else
4372                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4373 }
4374
4375 static int handle_cr(struct kvm_vcpu *vcpu)
4376 {
4377         unsigned long exit_qualification, val;
4378         int cr;
4379         int reg;
4380         int err;
4381
4382         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4383         cr = exit_qualification & 15;
4384         reg = (exit_qualification >> 8) & 15;
4385         switch ((exit_qualification >> 4) & 3) {
4386         case 0: /* mov to cr */
4387                 val = kvm_register_read(vcpu, reg);
4388                 trace_kvm_cr_write(cr, val);
4389                 switch (cr) {
4390                 case 0:
4391                         err = handle_set_cr0(vcpu, val);
4392                         kvm_complete_insn_gp(vcpu, err);
4393                         return 1;
4394                 case 3:
4395                         err = kvm_set_cr3(vcpu, val);
4396                         kvm_complete_insn_gp(vcpu, err);
4397                         return 1;
4398                 case 4:
4399                         err = handle_set_cr4(vcpu, val);
4400                         kvm_complete_insn_gp(vcpu, err);
4401                         return 1;
4402                 case 8: {
4403                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4404                                 u8 cr8 = kvm_register_read(vcpu, reg);
4405                                 err = kvm_set_cr8(vcpu, cr8);
4406                                 kvm_complete_insn_gp(vcpu, err);
4407                                 if (irqchip_in_kernel(vcpu->kvm))
4408                                         return 1;
4409                                 if (cr8_prev <= cr8)
4410                                         return 1;
4411                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4412                                 return 0;
4413                         }
4414                 };
4415                 break;
4416         case 2: /* clts */
4417                 handle_clts(vcpu);
4418                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4419                 skip_emulated_instruction(vcpu);
4420                 vmx_fpu_activate(vcpu);
4421                 return 1;
4422         case 1: /*mov from cr*/
4423                 switch (cr) {
4424                 case 3:
4425                         val = kvm_read_cr3(vcpu);
4426                         kvm_register_write(vcpu, reg, val);
4427                         trace_kvm_cr_read(cr, val);
4428                         skip_emulated_instruction(vcpu);
4429                         return 1;
4430                 case 8:
4431                         val = kvm_get_cr8(vcpu);
4432                         kvm_register_write(vcpu, reg, val);
4433                         trace_kvm_cr_read(cr, val);
4434                         skip_emulated_instruction(vcpu);
4435                         return 1;
4436                 }
4437                 break;
4438         case 3: /* lmsw */
4439                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4440                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4441                 kvm_lmsw(vcpu, val);
4442
4443                 skip_emulated_instruction(vcpu);
4444                 return 1;
4445         default:
4446                 break;
4447         }
4448         vcpu->run->exit_reason = 0;
4449         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4450                (int)(exit_qualification >> 4) & 3, cr);
4451         return 0;
4452 }
4453
4454 static int handle_dr(struct kvm_vcpu *vcpu)
4455 {
4456         unsigned long exit_qualification;
4457         int dr, reg;
4458
4459         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4460         if (!kvm_require_cpl(vcpu, 0))
4461                 return 1;
4462         dr = vmcs_readl(GUEST_DR7);
4463         if (dr & DR7_GD) {
4464                 /*
4465                  * As the vm-exit takes precedence over the debug trap, we
4466                  * need to emulate the latter, either for the host or the
4467                  * guest debugging itself.
4468                  */
4469                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4470                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4471                         vcpu->run->debug.arch.dr7 = dr;
4472                         vcpu->run->debug.arch.pc =
4473                                 vmcs_readl(GUEST_CS_BASE) +
4474                                 vmcs_readl(GUEST_RIP);
4475                         vcpu->run->debug.arch.exception = DB_VECTOR;
4476                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4477                         return 0;
4478                 } else {
4479                         vcpu->arch.dr7 &= ~DR7_GD;
4480                         vcpu->arch.dr6 |= DR6_BD;
4481                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4482                         kvm_queue_exception(vcpu, DB_VECTOR);
4483                         return 1;
4484                 }
4485         }
4486
4487         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4488         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4489         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4490         if (exit_qualification & TYPE_MOV_FROM_DR) {
4491                 unsigned long val;
4492                 if (!kvm_get_dr(vcpu, dr, &val))
4493                         kvm_register_write(vcpu, reg, val);
4494         } else
4495                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4496         skip_emulated_instruction(vcpu);
4497         return 1;
4498 }
4499
4500 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4501 {
4502         vmcs_writel(GUEST_DR7, val);
4503 }
4504
4505 static int handle_cpuid(struct kvm_vcpu *vcpu)
4506 {
4507         kvm_emulate_cpuid(vcpu);
4508         return 1;
4509 }
4510
4511 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4512 {
4513         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4514         u64 data;
4515
4516         if (vmx_get_msr(vcpu, ecx, &data)) {
4517                 trace_kvm_msr_read_ex(ecx);
4518                 kvm_inject_gp(vcpu, 0);
4519                 return 1;
4520         }
4521
4522         trace_kvm_msr_read(ecx, data);
4523
4524         /* FIXME: handling of bits 32:63 of rax, rdx */
4525         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4526         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4527         skip_emulated_instruction(vcpu);
4528         return 1;
4529 }
4530
4531 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4532 {
4533         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4534         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4535                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4536
4537         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4538                 trace_kvm_msr_write_ex(ecx, data);
4539                 kvm_inject_gp(vcpu, 0);
4540                 return 1;
4541         }
4542
4543         trace_kvm_msr_write(ecx, data);
4544         skip_emulated_instruction(vcpu);
4545         return 1;
4546 }
4547
4548 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4549 {
4550         kvm_make_request(KVM_REQ_EVENT, vcpu);
4551         return 1;
4552 }
4553
4554 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4555 {
4556         u32 cpu_based_vm_exec_control;
4557
4558         /* clear pending irq */
4559         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4560         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4561         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4562
4563         kvm_make_request(KVM_REQ_EVENT, vcpu);
4564
4565         ++vcpu->stat.irq_window_exits;
4566
4567         /*
4568          * If the user space waits to inject interrupts, exit as soon as
4569          * possible
4570          */
4571         if (!irqchip_in_kernel(vcpu->kvm) &&
4572             vcpu->run->request_interrupt_window &&
4573             !kvm_cpu_has_interrupt(vcpu)) {
4574                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4575                 return 0;
4576         }
4577         return 1;
4578 }
4579
4580 static int handle_halt(struct kvm_vcpu *vcpu)
4581 {
4582         skip_emulated_instruction(vcpu);
4583         return kvm_emulate_halt(vcpu);
4584 }
4585
4586 static int handle_vmcall(struct kvm_vcpu *vcpu)
4587 {
4588         skip_emulated_instruction(vcpu);
4589         kvm_emulate_hypercall(vcpu);
4590         return 1;
4591 }
4592
4593 static int handle_invd(struct kvm_vcpu *vcpu)
4594 {
4595         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4596 }
4597
4598 static int handle_invlpg(struct kvm_vcpu *vcpu)
4599 {
4600         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4601
4602         kvm_mmu_invlpg(vcpu, exit_qualification);
4603         skip_emulated_instruction(vcpu);
4604         return 1;
4605 }
4606
4607 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4608 {
4609         int err;
4610
4611         err = kvm_rdpmc(vcpu);
4612         kvm_complete_insn_gp(vcpu, err);
4613
4614         return 1;
4615 }
4616
4617 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4618 {
4619         skip_emulated_instruction(vcpu);
4620         kvm_emulate_wbinvd(vcpu);
4621         return 1;
4622 }
4623
4624 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4625 {
4626         u64 new_bv = kvm_read_edx_eax(vcpu);
4627         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4628
4629         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4630                 skip_emulated_instruction(vcpu);
4631         return 1;
4632 }
4633
4634 static int handle_apic_access(struct kvm_vcpu *vcpu)
4635 {
4636         if (likely(fasteoi)) {
4637                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4638                 int access_type, offset;
4639
4640                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4641                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4642                 /*
4643                  * Sane guest uses MOV to write EOI, with written value
4644                  * not cared. So make a short-circuit here by avoiding
4645                  * heavy instruction emulation.
4646                  */
4647                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4648                     (offset == APIC_EOI)) {
4649                         kvm_lapic_set_eoi(vcpu);
4650                         skip_emulated_instruction(vcpu);
4651                         return 1;
4652                 }
4653         }
4654         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4655 }
4656
4657 static int handle_task_switch(struct kvm_vcpu *vcpu)
4658 {
4659         struct vcpu_vmx *vmx = to_vmx(vcpu);
4660         unsigned long exit_qualification;
4661         bool has_error_code = false;
4662         u32 error_code = 0;
4663         u16 tss_selector;
4664         int reason, type, idt_v, idt_index;
4665
4666         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4667         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4668         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4669
4670         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4671
4672         reason = (u32)exit_qualification >> 30;
4673         if (reason == TASK_SWITCH_GATE && idt_v) {
4674                 switch (type) {
4675                 case INTR_TYPE_NMI_INTR:
4676                         vcpu->arch.nmi_injected = false;
4677                         vmx_set_nmi_mask(vcpu, true);
4678                         break;
4679                 case INTR_TYPE_EXT_INTR:
4680                 case INTR_TYPE_SOFT_INTR:
4681                         kvm_clear_interrupt_queue(vcpu);
4682                         break;
4683                 case INTR_TYPE_HARD_EXCEPTION:
4684                         if (vmx->idt_vectoring_info &
4685                             VECTORING_INFO_DELIVER_CODE_MASK) {
4686                                 has_error_code = true;
4687                                 error_code =
4688                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4689                         }
4690                         /* fall through */
4691                 case INTR_TYPE_SOFT_EXCEPTION:
4692                         kvm_clear_exception_queue(vcpu);
4693                         break;
4694                 default:
4695                         break;
4696                 }
4697         }
4698         tss_selector = exit_qualification;
4699
4700         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4701                        type != INTR_TYPE_EXT_INTR &&
4702                        type != INTR_TYPE_NMI_INTR))
4703                 skip_emulated_instruction(vcpu);
4704
4705         if (kvm_task_switch(vcpu, tss_selector,
4706                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4707                             has_error_code, error_code) == EMULATE_FAIL) {
4708                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4709                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4710                 vcpu->run->internal.ndata = 0;
4711                 return 0;
4712         }
4713
4714         /* clear all local breakpoint enable flags */
4715         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4716
4717         /*
4718          * TODO: What about debug traps on tss switch?
4719          *       Are we supposed to inject them and update dr6?
4720          */
4721
4722         return 1;
4723 }
4724
4725 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4726 {
4727         unsigned long exit_qualification;
4728         gpa_t gpa;
4729         int gla_validity;
4730
4731         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4732
4733         if (exit_qualification & (1 << 6)) {
4734                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4735                 return -EINVAL;
4736         }
4737
4738         gla_validity = (exit_qualification >> 7) & 0x3;
4739         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4740                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4741                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4742                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4743                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4744                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4745                         (long unsigned int)exit_qualification);
4746                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4747                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4748                 return 0;
4749         }
4750
4751         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4752         trace_kvm_page_fault(gpa, exit_qualification);
4753         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4754 }
4755
4756 static u64 ept_rsvd_mask(u64 spte, int level)
4757 {
4758         int i;
4759         u64 mask = 0;
4760
4761         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4762                 mask |= (1ULL << i);
4763
4764         if (level > 2)
4765                 /* bits 7:3 reserved */
4766                 mask |= 0xf8;
4767         else if (level == 2) {
4768                 if (spte & (1ULL << 7))
4769                         /* 2MB ref, bits 20:12 reserved */
4770                         mask |= 0x1ff000;
4771                 else
4772                         /* bits 6:3 reserved */
4773                         mask |= 0x78;
4774         }
4775
4776         return mask;
4777 }
4778
4779 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4780                                        int level)
4781 {
4782         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4783
4784         /* 010b (write-only) */
4785         WARN_ON((spte & 0x7) == 0x2);
4786
4787         /* 110b (write/execute) */
4788         WARN_ON((spte & 0x7) == 0x6);
4789
4790         /* 100b (execute-only) and value not supported by logical processor */
4791         if (!cpu_has_vmx_ept_execute_only())
4792                 WARN_ON((spte & 0x7) == 0x4);
4793
4794         /* not 000b */
4795         if ((spte & 0x7)) {
4796                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4797
4798                 if (rsvd_bits != 0) {
4799                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4800                                          __func__, rsvd_bits);
4801                         WARN_ON(1);
4802                 }
4803
4804                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4805                         u64 ept_mem_type = (spte & 0x38) >> 3;
4806
4807                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4808                             ept_mem_type == 7) {
4809                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4810                                                 __func__, ept_mem_type);
4811                                 WARN_ON(1);
4812                         }
4813                 }
4814         }
4815 }
4816
4817 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4818 {
4819         u64 sptes[4];
4820         int nr_sptes, i, ret;
4821         gpa_t gpa;
4822
4823         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4824
4825         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4826         if (likely(ret == 1))
4827                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4828                                               EMULATE_DONE;
4829         if (unlikely(!ret))
4830                 return 1;
4831
4832         /* It is the real ept misconfig */
4833         printk(KERN_ERR "EPT: Misconfiguration.\n");
4834         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4835
4836         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4837
4838         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4839                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4840
4841         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4842         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4843
4844         return 0;
4845 }
4846
4847 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4848 {
4849         u32 cpu_based_vm_exec_control;
4850
4851         /* clear pending NMI */
4852         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4853         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4854         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4855         ++vcpu->stat.nmi_window_exits;
4856         kvm_make_request(KVM_REQ_EVENT, vcpu);
4857
4858         return 1;
4859 }
4860
4861 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4862 {
4863         struct vcpu_vmx *vmx = to_vmx(vcpu);
4864         enum emulation_result err = EMULATE_DONE;
4865         int ret = 1;
4866         u32 cpu_exec_ctrl;
4867         bool intr_window_requested;
4868
4869         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4870         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4871
4872         while (!guest_state_valid(vcpu)) {
4873                 if (intr_window_requested
4874                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4875                         return handle_interrupt_window(&vmx->vcpu);
4876
4877                 err = emulate_instruction(vcpu, 0);
4878
4879                 if (err == EMULATE_DO_MMIO) {
4880                         ret = 0;
4881                         goto out;
4882                 }
4883
4884                 if (err != EMULATE_DONE)
4885                         return 0;
4886
4887                 if (signal_pending(current))
4888                         goto out;
4889                 if (need_resched())
4890                         schedule();
4891         }
4892
4893         vmx->emulation_required = 0;
4894 out:
4895         return ret;
4896 }
4897
4898 /*
4899  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4900  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4901  */
4902 static int handle_pause(struct kvm_vcpu *vcpu)
4903 {
4904         skip_emulated_instruction(vcpu);
4905         kvm_vcpu_on_spin(vcpu);
4906
4907         return 1;
4908 }
4909
4910 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4911 {
4912         kvm_queue_exception(vcpu, UD_VECTOR);
4913         return 1;
4914 }
4915
4916 /*
4917  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4918  * We could reuse a single VMCS for all the L2 guests, but we also want the
4919  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4920  * allows keeping them loaded on the processor, and in the future will allow
4921  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4922  * every entry if they never change.
4923  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4924  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4925  *
4926  * The following functions allocate and free a vmcs02 in this pool.
4927  */
4928
4929 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4930 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4931 {
4932         struct vmcs02_list *item;
4933         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4934                 if (item->vmptr == vmx->nested.current_vmptr) {
4935                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4936                         return &item->vmcs02;
4937                 }
4938
4939         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4940                 /* Recycle the least recently used VMCS. */
4941                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4942                         struct vmcs02_list, list);
4943                 item->vmptr = vmx->nested.current_vmptr;
4944                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4945                 return &item->vmcs02;
4946         }
4947
4948         /* Create a new VMCS */
4949         item = (struct vmcs02_list *)
4950                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4951         if (!item)
4952                 return NULL;
4953         item->vmcs02.vmcs = alloc_vmcs();
4954         if (!item->vmcs02.vmcs) {
4955                 kfree(item);
4956                 return NULL;
4957         }
4958         loaded_vmcs_init(&item->vmcs02);
4959         item->vmptr = vmx->nested.current_vmptr;
4960         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4961         vmx->nested.vmcs02_num++;
4962         return &item->vmcs02;
4963 }
4964
4965 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4966 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4967 {
4968         struct vmcs02_list *item;
4969         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4970                 if (item->vmptr == vmptr) {
4971                         free_loaded_vmcs(&item->vmcs02);
4972                         list_del(&item->list);
4973                         kfree(item);
4974                         vmx->nested.vmcs02_num--;
4975                         return;
4976                 }
4977 }
4978
4979 /*
4980  * Free all VMCSs saved for this vcpu, except the one pointed by
4981  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4982  * currently used, if running L2), and vmcs01 when running L2.
4983  */
4984 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4985 {
4986         struct vmcs02_list *item, *n;
4987         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4988                 if (vmx->loaded_vmcs != &item->vmcs02)
4989                         free_loaded_vmcs(&item->vmcs02);
4990                 list_del(&item->list);
4991                 kfree(item);
4992         }
4993         vmx->nested.vmcs02_num = 0;
4994
4995         if (vmx->loaded_vmcs != &vmx->vmcs01)
4996                 free_loaded_vmcs(&vmx->vmcs01);
4997 }
4998
4999 /*
5000  * Emulate the VMXON instruction.
5001  * Currently, we just remember that VMX is active, and do not save or even
5002  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5003  * do not currently need to store anything in that guest-allocated memory
5004  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5005  * argument is different from the VMXON pointer (which the spec says they do).
5006  */
5007 static int handle_vmon(struct kvm_vcpu *vcpu)
5008 {
5009         struct kvm_segment cs;
5010         struct vcpu_vmx *vmx = to_vmx(vcpu);
5011
5012         /* The Intel VMX Instruction Reference lists a bunch of bits that
5013          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5014          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5015          * Otherwise, we should fail with #UD. We test these now:
5016          */
5017         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5018             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5019             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5020                 kvm_queue_exception(vcpu, UD_VECTOR);
5021                 return 1;
5022         }
5023
5024         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5025         if (is_long_mode(vcpu) && !cs.l) {
5026                 kvm_queue_exception(vcpu, UD_VECTOR);
5027                 return 1;
5028         }
5029
5030         if (vmx_get_cpl(vcpu)) {
5031                 kvm_inject_gp(vcpu, 0);
5032                 return 1;
5033         }
5034
5035         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5036         vmx->nested.vmcs02_num = 0;
5037
5038         vmx->nested.vmxon = true;
5039
5040         skip_emulated_instruction(vcpu);
5041         return 1;
5042 }
5043
5044 /*
5045  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5046  * for running VMX instructions (except VMXON, whose prerequisites are
5047  * slightly different). It also specifies what exception to inject otherwise.
5048  */
5049 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5050 {
5051         struct kvm_segment cs;
5052         struct vcpu_vmx *vmx = to_vmx(vcpu);
5053
5054         if (!vmx->nested.vmxon) {
5055                 kvm_queue_exception(vcpu, UD_VECTOR);
5056                 return 0;
5057         }
5058
5059         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5060         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5061             (is_long_mode(vcpu) && !cs.l)) {
5062                 kvm_queue_exception(vcpu, UD_VECTOR);
5063                 return 0;
5064         }
5065
5066         if (vmx_get_cpl(vcpu)) {
5067                 kvm_inject_gp(vcpu, 0);
5068                 return 0;
5069         }
5070
5071         return 1;
5072 }
5073
5074 /*
5075  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5076  * just stops using VMX.
5077  */
5078 static void free_nested(struct vcpu_vmx *vmx)
5079 {
5080         if (!vmx->nested.vmxon)
5081                 return;
5082         vmx->nested.vmxon = false;
5083         if (vmx->nested.current_vmptr != -1ull) {
5084                 kunmap(vmx->nested.current_vmcs12_page);
5085                 nested_release_page(vmx->nested.current_vmcs12_page);
5086                 vmx->nested.current_vmptr = -1ull;
5087                 vmx->nested.current_vmcs12 = NULL;
5088         }
5089         /* Unpin physical memory we referred to in current vmcs02 */
5090         if (vmx->nested.apic_access_page) {
5091                 nested_release_page(vmx->nested.apic_access_page);
5092                 vmx->nested.apic_access_page = 0;
5093         }
5094
5095         nested_free_all_saved_vmcss(vmx);
5096 }
5097
5098 /* Emulate the VMXOFF instruction */
5099 static int handle_vmoff(struct kvm_vcpu *vcpu)
5100 {
5101         if (!nested_vmx_check_permission(vcpu))
5102                 return 1;
5103         free_nested(to_vmx(vcpu));
5104         skip_emulated_instruction(vcpu);
5105         return 1;
5106 }
5107
5108 /*
5109  * Decode the memory-address operand of a vmx instruction, as recorded on an
5110  * exit caused by such an instruction (run by a guest hypervisor).
5111  * On success, returns 0. When the operand is invalid, returns 1 and throws
5112  * #UD or #GP.
5113  */
5114 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5115                                  unsigned long exit_qualification,
5116                                  u32 vmx_instruction_info, gva_t *ret)
5117 {
5118         /*
5119          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5120          * Execution", on an exit, vmx_instruction_info holds most of the
5121          * addressing components of the operand. Only the displacement part
5122          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5123          * For how an actual address is calculated from all these components,
5124          * refer to Vol. 1, "Operand Addressing".
5125          */
5126         int  scaling = vmx_instruction_info & 3;
5127         int  addr_size = (vmx_instruction_info >> 7) & 7;
5128         bool is_reg = vmx_instruction_info & (1u << 10);
5129         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5130         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5131         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5132         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5133         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5134
5135         if (is_reg) {
5136                 kvm_queue_exception(vcpu, UD_VECTOR);
5137                 return 1;
5138         }
5139
5140         /* Addr = segment_base + offset */
5141         /* offset = base + [index * scale] + displacement */
5142         *ret = vmx_get_segment_base(vcpu, seg_reg);
5143         if (base_is_valid)
5144                 *ret += kvm_register_read(vcpu, base_reg);
5145         if (index_is_valid)
5146                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5147         *ret += exit_qualification; /* holds the displacement */
5148
5149         if (addr_size == 1) /* 32 bit */
5150                 *ret &= 0xffffffff;
5151
5152         /*
5153          * TODO: throw #GP (and return 1) in various cases that the VM*
5154          * instructions require it - e.g., offset beyond segment limit,
5155          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5156          * address, and so on. Currently these are not checked.
5157          */
5158         return 0;
5159 }
5160
5161 /*
5162  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5163  * set the success or error code of an emulated VMX instruction, as specified
5164  * by Vol 2B, VMX Instruction Reference, "Conventions".
5165  */
5166 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5167 {
5168         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5169                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5170                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5171 }
5172
5173 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5174 {
5175         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5176                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5177                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5178                         | X86_EFLAGS_CF);
5179 }
5180
5181 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5182                                         u32 vm_instruction_error)
5183 {
5184         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5185                 /*
5186                  * failValid writes the error number to the current VMCS, which
5187                  * can't be done there isn't a current VMCS.
5188                  */
5189                 nested_vmx_failInvalid(vcpu);
5190                 return;
5191         }
5192         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5193                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5194                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5195                         | X86_EFLAGS_ZF);
5196         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5197 }
5198
5199 /* Emulate the VMCLEAR instruction */
5200 static int handle_vmclear(struct kvm_vcpu *vcpu)
5201 {
5202         struct vcpu_vmx *vmx = to_vmx(vcpu);
5203         gva_t gva;
5204         gpa_t vmptr;
5205         struct vmcs12 *vmcs12;
5206         struct page *page;
5207         struct x86_exception e;
5208
5209         if (!nested_vmx_check_permission(vcpu))
5210                 return 1;
5211
5212         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5213                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5214                 return 1;
5215
5216         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5217                                 sizeof(vmptr), &e)) {
5218                 kvm_inject_page_fault(vcpu, &e);
5219                 return 1;
5220         }
5221
5222         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5223                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5224                 skip_emulated_instruction(vcpu);
5225                 return 1;
5226         }
5227
5228         if (vmptr == vmx->nested.current_vmptr) {
5229                 kunmap(vmx->nested.current_vmcs12_page);
5230                 nested_release_page(vmx->nested.current_vmcs12_page);
5231                 vmx->nested.current_vmptr = -1ull;
5232                 vmx->nested.current_vmcs12 = NULL;
5233         }
5234
5235         page = nested_get_page(vcpu, vmptr);
5236         if (page == NULL) {
5237                 /*
5238                  * For accurate processor emulation, VMCLEAR beyond available
5239                  * physical memory should do nothing at all. However, it is
5240                  * possible that a nested vmx bug, not a guest hypervisor bug,
5241                  * resulted in this case, so let's shut down before doing any
5242                  * more damage:
5243                  */
5244                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5245                 return 1;
5246         }
5247         vmcs12 = kmap(page);
5248         vmcs12->launch_state = 0;
5249         kunmap(page);
5250         nested_release_page(page);
5251
5252         nested_free_vmcs02(vmx, vmptr);
5253
5254         skip_emulated_instruction(vcpu);
5255         nested_vmx_succeed(vcpu);
5256         return 1;
5257 }
5258
5259 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5260
5261 /* Emulate the VMLAUNCH instruction */
5262 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5263 {
5264         return nested_vmx_run(vcpu, true);
5265 }
5266
5267 /* Emulate the VMRESUME instruction */
5268 static int handle_vmresume(struct kvm_vcpu *vcpu)
5269 {
5270
5271         return nested_vmx_run(vcpu, false);
5272 }
5273
5274 enum vmcs_field_type {
5275         VMCS_FIELD_TYPE_U16 = 0,
5276         VMCS_FIELD_TYPE_U64 = 1,
5277         VMCS_FIELD_TYPE_U32 = 2,
5278         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5279 };
5280
5281 static inline int vmcs_field_type(unsigned long field)
5282 {
5283         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5284                 return VMCS_FIELD_TYPE_U32;
5285         return (field >> 13) & 0x3 ;
5286 }
5287
5288 static inline int vmcs_field_readonly(unsigned long field)
5289 {
5290         return (((field >> 10) & 0x3) == 1);
5291 }
5292
5293 /*
5294  * Read a vmcs12 field. Since these can have varying lengths and we return
5295  * one type, we chose the biggest type (u64) and zero-extend the return value
5296  * to that size. Note that the caller, handle_vmread, might need to use only
5297  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5298  * 64-bit fields are to be returned).
5299  */
5300 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5301                                         unsigned long field, u64 *ret)
5302 {
5303         short offset = vmcs_field_to_offset(field);
5304         char *p;
5305
5306         if (offset < 0)
5307                 return 0;
5308
5309         p = ((char *)(get_vmcs12(vcpu))) + offset;
5310
5311         switch (vmcs_field_type(field)) {
5312         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5313                 *ret = *((natural_width *)p);
5314                 return 1;
5315         case VMCS_FIELD_TYPE_U16:
5316                 *ret = *((u16 *)p);
5317                 return 1;
5318         case VMCS_FIELD_TYPE_U32:
5319                 *ret = *((u32 *)p);
5320                 return 1;
5321         case VMCS_FIELD_TYPE_U64:
5322                 *ret = *((u64 *)p);
5323                 return 1;
5324         default:
5325                 return 0; /* can never happen. */
5326         }
5327 }
5328
5329 /*
5330  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5331  * used before) all generate the same failure when it is missing.
5332  */
5333 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5334 {
5335         struct vcpu_vmx *vmx = to_vmx(vcpu);
5336         if (vmx->nested.current_vmptr == -1ull) {
5337                 nested_vmx_failInvalid(vcpu);
5338                 skip_emulated_instruction(vcpu);
5339                 return 0;
5340         }
5341         return 1;
5342 }
5343
5344 static int handle_vmread(struct kvm_vcpu *vcpu)
5345 {
5346         unsigned long field;
5347         u64 field_value;
5348         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5349         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5350         gva_t gva = 0;
5351
5352         if (!nested_vmx_check_permission(vcpu) ||
5353             !nested_vmx_check_vmcs12(vcpu))
5354                 return 1;
5355
5356         /* Decode instruction info and find the field to read */
5357         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5358         /* Read the field, zero-extended to a u64 field_value */
5359         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5360                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5361                 skip_emulated_instruction(vcpu);
5362                 return 1;
5363         }
5364         /*
5365          * Now copy part of this value to register or memory, as requested.
5366          * Note that the number of bits actually copied is 32 or 64 depending
5367          * on the guest's mode (32 or 64 bit), not on the given field's length.
5368          */
5369         if (vmx_instruction_info & (1u << 10)) {
5370                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5371                         field_value);
5372         } else {
5373                 if (get_vmx_mem_address(vcpu, exit_qualification,
5374                                 vmx_instruction_info, &gva))
5375                         return 1;
5376                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5377                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5378                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5379         }
5380
5381         nested_vmx_succeed(vcpu);
5382         skip_emulated_instruction(vcpu);
5383         return 1;
5384 }
5385
5386
5387 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5388 {
5389         unsigned long field;
5390         gva_t gva;
5391         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5392         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5393         char *p;
5394         short offset;
5395         /* The value to write might be 32 or 64 bits, depending on L1's long
5396          * mode, and eventually we need to write that into a field of several
5397          * possible lengths. The code below first zero-extends the value to 64
5398          * bit (field_value), and then copies only the approriate number of
5399          * bits into the vmcs12 field.
5400          */
5401         u64 field_value = 0;
5402         struct x86_exception e;
5403
5404         if (!nested_vmx_check_permission(vcpu) ||
5405             !nested_vmx_check_vmcs12(vcpu))
5406                 return 1;
5407
5408         if (vmx_instruction_info & (1u << 10))
5409                 field_value = kvm_register_read(vcpu,
5410                         (((vmx_instruction_info) >> 3) & 0xf));
5411         else {
5412                 if (get_vmx_mem_address(vcpu, exit_qualification,
5413                                 vmx_instruction_info, &gva))
5414                         return 1;
5415                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5416                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5417                         kvm_inject_page_fault(vcpu, &e);
5418                         return 1;
5419                 }
5420         }
5421
5422
5423         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5424         if (vmcs_field_readonly(field)) {
5425                 nested_vmx_failValid(vcpu,
5426                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5427                 skip_emulated_instruction(vcpu);
5428                 return 1;
5429         }
5430
5431         offset = vmcs_field_to_offset(field);
5432         if (offset < 0) {
5433                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5434                 skip_emulated_instruction(vcpu);
5435                 return 1;
5436         }
5437         p = ((char *) get_vmcs12(vcpu)) + offset;
5438
5439         switch (vmcs_field_type(field)) {
5440         case VMCS_FIELD_TYPE_U16:
5441                 *(u16 *)p = field_value;
5442                 break;
5443         case VMCS_FIELD_TYPE_U32:
5444                 *(u32 *)p = field_value;
5445                 break;
5446         case VMCS_FIELD_TYPE_U64:
5447                 *(u64 *)p = field_value;
5448                 break;
5449         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5450                 *(natural_width *)p = field_value;
5451                 break;
5452         default:
5453                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5454                 skip_emulated_instruction(vcpu);
5455                 return 1;
5456         }
5457
5458         nested_vmx_succeed(vcpu);
5459         skip_emulated_instruction(vcpu);
5460         return 1;
5461 }
5462
5463 /* Emulate the VMPTRLD instruction */
5464 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5465 {
5466         struct vcpu_vmx *vmx = to_vmx(vcpu);
5467         gva_t gva;
5468         gpa_t vmptr;
5469         struct x86_exception e;
5470
5471         if (!nested_vmx_check_permission(vcpu))
5472                 return 1;
5473
5474         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5475                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5476                 return 1;
5477
5478         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5479                                 sizeof(vmptr), &e)) {
5480                 kvm_inject_page_fault(vcpu, &e);
5481                 return 1;
5482         }
5483
5484         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5485                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5486                 skip_emulated_instruction(vcpu);
5487                 return 1;
5488         }
5489
5490         if (vmx->nested.current_vmptr != vmptr) {
5491                 struct vmcs12 *new_vmcs12;
5492                 struct page *page;
5493                 page = nested_get_page(vcpu, vmptr);
5494                 if (page == NULL) {
5495                         nested_vmx_failInvalid(vcpu);
5496                         skip_emulated_instruction(vcpu);
5497                         return 1;
5498                 }
5499                 new_vmcs12 = kmap(page);
5500                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5501                         kunmap(page);
5502                         nested_release_page_clean(page);
5503                         nested_vmx_failValid(vcpu,
5504                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5505                         skip_emulated_instruction(vcpu);
5506                         return 1;
5507                 }
5508                 if (vmx->nested.current_vmptr != -1ull) {
5509                         kunmap(vmx->nested.current_vmcs12_page);
5510                         nested_release_page(vmx->nested.current_vmcs12_page);
5511                 }
5512
5513                 vmx->nested.current_vmptr = vmptr;
5514                 vmx->nested.current_vmcs12 = new_vmcs12;
5515                 vmx->nested.current_vmcs12_page = page;
5516         }
5517
5518         nested_vmx_succeed(vcpu);
5519         skip_emulated_instruction(vcpu);
5520         return 1;
5521 }
5522
5523 /* Emulate the VMPTRST instruction */
5524 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5525 {
5526         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5527         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5528         gva_t vmcs_gva;
5529         struct x86_exception e;
5530
5531         if (!nested_vmx_check_permission(vcpu))
5532                 return 1;
5533
5534         if (get_vmx_mem_address(vcpu, exit_qualification,
5535                         vmx_instruction_info, &vmcs_gva))
5536                 return 1;
5537         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5538         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5539                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5540                                  sizeof(u64), &e)) {
5541                 kvm_inject_page_fault(vcpu, &e);
5542                 return 1;
5543         }
5544         nested_vmx_succeed(vcpu);
5545         skip_emulated_instruction(vcpu);
5546         return 1;
5547 }
5548
5549 /*
5550  * The exit handlers return 1 if the exit was handled fully and guest execution
5551  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5552  * to be done to userspace and return 0.
5553  */
5554 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5555         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5556         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5557         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5558         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5559         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5560         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5561         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5562         [EXIT_REASON_CPUID]                   = handle_cpuid,
5563         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5564         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5565         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5566         [EXIT_REASON_HLT]                     = handle_halt,
5567         [EXIT_REASON_INVD]                    = handle_invd,
5568         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5569         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5570         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5571         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5572         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5573         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5574         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5575         [EXIT_REASON_VMREAD]                  = handle_vmread,
5576         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5577         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5578         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5579         [EXIT_REASON_VMON]                    = handle_vmon,
5580         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5581         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5582         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5583         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5584         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5585         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5586         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5587         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5588         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5589         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5590         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5591 };
5592
5593 static const int kvm_vmx_max_exit_handlers =
5594         ARRAY_SIZE(kvm_vmx_exit_handlers);
5595
5596 /*
5597  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5598  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5599  * disinterest in the current event (read or write a specific MSR) by using an
5600  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5601  */
5602 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5603         struct vmcs12 *vmcs12, u32 exit_reason)
5604 {
5605         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5606         gpa_t bitmap;
5607
5608         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5609                 return 1;
5610
5611         /*
5612          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5613          * for the four combinations of read/write and low/high MSR numbers.
5614          * First we need to figure out which of the four to use:
5615          */
5616         bitmap = vmcs12->msr_bitmap;
5617         if (exit_reason == EXIT_REASON_MSR_WRITE)
5618                 bitmap += 2048;
5619         if (msr_index >= 0xc0000000) {
5620                 msr_index -= 0xc0000000;
5621                 bitmap += 1024;
5622         }
5623
5624         /* Then read the msr_index'th bit from this bitmap: */
5625         if (msr_index < 1024*8) {
5626                 unsigned char b;
5627                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5628                 return 1 & (b >> (msr_index & 7));
5629         } else
5630                 return 1; /* let L1 handle the wrong parameter */
5631 }
5632
5633 /*
5634  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5635  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5636  * intercept (via guest_host_mask etc.) the current event.
5637  */
5638 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5639         struct vmcs12 *vmcs12)
5640 {
5641         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5642         int cr = exit_qualification & 15;
5643         int reg = (exit_qualification >> 8) & 15;
5644         unsigned long val = kvm_register_read(vcpu, reg);
5645
5646         switch ((exit_qualification >> 4) & 3) {
5647         case 0: /* mov to cr */
5648                 switch (cr) {
5649                 case 0:
5650                         if (vmcs12->cr0_guest_host_mask &
5651                             (val ^ vmcs12->cr0_read_shadow))
5652                                 return 1;
5653                         break;
5654                 case 3:
5655                         if ((vmcs12->cr3_target_count >= 1 &&
5656                                         vmcs12->cr3_target_value0 == val) ||
5657                                 (vmcs12->cr3_target_count >= 2 &&
5658                                         vmcs12->cr3_target_value1 == val) ||
5659                                 (vmcs12->cr3_target_count >= 3 &&
5660                                         vmcs12->cr3_target_value2 == val) ||
5661                                 (vmcs12->cr3_target_count >= 4 &&
5662                                         vmcs12->cr3_target_value3 == val))
5663                                 return 0;
5664                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5665                                 return 1;
5666                         break;
5667                 case 4:
5668                         if (vmcs12->cr4_guest_host_mask &
5669                             (vmcs12->cr4_read_shadow ^ val))
5670                                 return 1;
5671                         break;
5672                 case 8:
5673                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5674                                 return 1;
5675                         break;
5676                 }
5677                 break;
5678         case 2: /* clts */
5679                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5680                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5681                         return 1;
5682                 break;
5683         case 1: /* mov from cr */
5684                 switch (cr) {
5685                 case 3:
5686                         if (vmcs12->cpu_based_vm_exec_control &
5687                             CPU_BASED_CR3_STORE_EXITING)
5688                                 return 1;
5689                         break;
5690                 case 8:
5691                         if (vmcs12->cpu_based_vm_exec_control &
5692                             CPU_BASED_CR8_STORE_EXITING)
5693                                 return 1;
5694                         break;
5695                 }
5696                 break;
5697         case 3: /* lmsw */
5698                 /*
5699                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5700                  * cr0. Other attempted changes are ignored, with no exit.
5701                  */
5702                 if (vmcs12->cr0_guest_host_mask & 0xe &
5703                     (val ^ vmcs12->cr0_read_shadow))
5704                         return 1;
5705                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5706                     !(vmcs12->cr0_read_shadow & 0x1) &&
5707                     (val & 0x1))
5708                         return 1;
5709                 break;
5710         }
5711         return 0;
5712 }
5713
5714 /*
5715  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5716  * should handle it ourselves in L0 (and then continue L2). Only call this
5717  * when in is_guest_mode (L2).
5718  */
5719 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5720 {
5721         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5722         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5723         struct vcpu_vmx *vmx = to_vmx(vcpu);
5724         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5725
5726         if (vmx->nested.nested_run_pending)
5727                 return 0;
5728
5729         if (unlikely(vmx->fail)) {
5730                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5731                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5732                 return 1;
5733         }
5734
5735         switch (exit_reason) {
5736         case EXIT_REASON_EXCEPTION_NMI:
5737                 if (!is_exception(intr_info))
5738                         return 0;
5739                 else if (is_page_fault(intr_info))
5740                         return enable_ept;
5741                 return vmcs12->exception_bitmap &
5742                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5743         case EXIT_REASON_EXTERNAL_INTERRUPT:
5744                 return 0;
5745         case EXIT_REASON_TRIPLE_FAULT:
5746                 return 1;
5747         case EXIT_REASON_PENDING_INTERRUPT:
5748         case EXIT_REASON_NMI_WINDOW:
5749                 /*
5750                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5751                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5752                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5753                  * Same for NMI Window Exiting.
5754                  */
5755                 return 1;
5756         case EXIT_REASON_TASK_SWITCH:
5757                 return 1;
5758         case EXIT_REASON_CPUID:
5759                 return 1;
5760         case EXIT_REASON_HLT:
5761                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5762         case EXIT_REASON_INVD:
5763                 return 1;
5764         case EXIT_REASON_INVLPG:
5765                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5766         case EXIT_REASON_RDPMC:
5767                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5768         case EXIT_REASON_RDTSC:
5769                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5770         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5771         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5772         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5773         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5774         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5775                 /*
5776                  * VMX instructions trap unconditionally. This allows L1 to
5777                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5778                  */
5779                 return 1;
5780         case EXIT_REASON_CR_ACCESS:
5781                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5782         case EXIT_REASON_DR_ACCESS:
5783                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5784         case EXIT_REASON_IO_INSTRUCTION:
5785                 /* TODO: support IO bitmaps */
5786                 return 1;
5787         case EXIT_REASON_MSR_READ:
5788         case EXIT_REASON_MSR_WRITE:
5789                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5790         case EXIT_REASON_INVALID_STATE:
5791                 return 1;
5792         case EXIT_REASON_MWAIT_INSTRUCTION:
5793                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5794         case EXIT_REASON_MONITOR_INSTRUCTION:
5795                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5796         case EXIT_REASON_PAUSE_INSTRUCTION:
5797                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5798                         nested_cpu_has2(vmcs12,
5799                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5800         case EXIT_REASON_MCE_DURING_VMENTRY:
5801                 return 0;
5802         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5803                 return 1;
5804         case EXIT_REASON_APIC_ACCESS:
5805                 return nested_cpu_has2(vmcs12,
5806                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5807         case EXIT_REASON_EPT_VIOLATION:
5808         case EXIT_REASON_EPT_MISCONFIG:
5809                 return 0;
5810         case EXIT_REASON_WBINVD:
5811                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5812         case EXIT_REASON_XSETBV:
5813                 return 1;
5814         default:
5815                 return 1;
5816         }
5817 }
5818
5819 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5820 {
5821         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5822         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5823 }
5824
5825 /*
5826  * The guest has exited.  See if we can fix it or if we need userspace
5827  * assistance.
5828  */
5829 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5830 {
5831         struct vcpu_vmx *vmx = to_vmx(vcpu);
5832         u32 exit_reason = vmx->exit_reason;
5833         u32 vectoring_info = vmx->idt_vectoring_info;
5834
5835         /* If guest state is invalid, start emulating */
5836         if (vmx->emulation_required && emulate_invalid_guest_state)
5837                 return handle_invalid_guest_state(vcpu);
5838
5839         /*
5840          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5841          * we did not inject a still-pending event to L1 now because of
5842          * nested_run_pending, we need to re-enable this bit.
5843          */
5844         if (vmx->nested.nested_run_pending)
5845                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5846
5847         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5848             exit_reason == EXIT_REASON_VMRESUME))
5849                 vmx->nested.nested_run_pending = 1;
5850         else
5851                 vmx->nested.nested_run_pending = 0;
5852
5853         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5854                 nested_vmx_vmexit(vcpu);
5855                 return 1;
5856         }
5857
5858         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5859                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5860                 vcpu->run->fail_entry.hardware_entry_failure_reason
5861                         = exit_reason;
5862                 return 0;
5863         }
5864
5865         if (unlikely(vmx->fail)) {
5866                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5867                 vcpu->run->fail_entry.hardware_entry_failure_reason
5868                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5869                 return 0;
5870         }
5871
5872         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5873                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5874                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5875                         exit_reason != EXIT_REASON_TASK_SWITCH))
5876                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5877                        "(0x%x) and exit reason is 0x%x\n",
5878                        __func__, vectoring_info, exit_reason);
5879
5880         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5881             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5882                                         get_vmcs12(vcpu), vcpu)))) {
5883                 if (vmx_interrupt_allowed(vcpu)) {
5884                         vmx->soft_vnmi_blocked = 0;
5885                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5886                            vcpu->arch.nmi_pending) {
5887                         /*
5888                          * This CPU don't support us in finding the end of an
5889                          * NMI-blocked window if the guest runs with IRQs
5890                          * disabled. So we pull the trigger after 1 s of
5891                          * futile waiting, but inform the user about this.
5892                          */
5893                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5894                                "state on VCPU %d after 1 s timeout\n",
5895                                __func__, vcpu->vcpu_id);
5896                         vmx->soft_vnmi_blocked = 0;
5897                 }
5898         }
5899
5900         if (exit_reason < kvm_vmx_max_exit_handlers
5901             && kvm_vmx_exit_handlers[exit_reason])
5902                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5903         else {
5904                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5905                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5906         }
5907         return 0;
5908 }
5909
5910 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5911 {
5912         if (irr == -1 || tpr < irr) {
5913                 vmcs_write32(TPR_THRESHOLD, 0);
5914                 return;
5915         }
5916
5917         vmcs_write32(TPR_THRESHOLD, irr);
5918 }
5919
5920 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5921 {
5922         u32 exit_intr_info;
5923
5924         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5925               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5926                 return;
5927
5928         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5929         exit_intr_info = vmx->exit_intr_info;
5930
5931         /* Handle machine checks before interrupts are enabled */
5932         if (is_machine_check(exit_intr_info))
5933                 kvm_machine_check();
5934
5935         /* We need to handle NMIs before interrupts are enabled */
5936         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5937             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5938                 kvm_before_handle_nmi(&vmx->vcpu);
5939                 asm("int $2");
5940                 kvm_after_handle_nmi(&vmx->vcpu);
5941         }
5942 }
5943
5944 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5945 {
5946         u32 exit_intr_info;
5947         bool unblock_nmi;
5948         u8 vector;
5949         bool idtv_info_valid;
5950
5951         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5952
5953         if (cpu_has_virtual_nmis()) {
5954                 if (vmx->nmi_known_unmasked)
5955                         return;
5956                 /*
5957                  * Can't use vmx->exit_intr_info since we're not sure what
5958                  * the exit reason is.
5959                  */
5960                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5961                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5962                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5963                 /*
5964                  * SDM 3: 27.7.1.2 (September 2008)
5965                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5966                  * a guest IRET fault.
5967                  * SDM 3: 23.2.2 (September 2008)
5968                  * Bit 12 is undefined in any of the following cases:
5969                  *  If the VM exit sets the valid bit in the IDT-vectoring
5970                  *   information field.
5971                  *  If the VM exit is due to a double fault.
5972                  */
5973                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5974                     vector != DF_VECTOR && !idtv_info_valid)
5975                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5976                                       GUEST_INTR_STATE_NMI);
5977                 else
5978                         vmx->nmi_known_unmasked =
5979                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5980                                   & GUEST_INTR_STATE_NMI);
5981         } else if (unlikely(vmx->soft_vnmi_blocked))
5982                 vmx->vnmi_blocked_time +=
5983                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5984 }
5985
5986 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5987                                       u32 idt_vectoring_info,
5988                                       int instr_len_field,
5989                                       int error_code_field)
5990 {
5991         u8 vector;
5992         int type;
5993         bool idtv_info_valid;
5994
5995         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5996
5997         vmx->vcpu.arch.nmi_injected = false;
5998         kvm_clear_exception_queue(&vmx->vcpu);
5999         kvm_clear_interrupt_queue(&vmx->vcpu);
6000
6001         if (!idtv_info_valid)
6002                 return;
6003
6004         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6005
6006         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6007         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6008
6009         switch (type) {
6010         case INTR_TYPE_NMI_INTR:
6011                 vmx->vcpu.arch.nmi_injected = true;
6012                 /*
6013                  * SDM 3: 27.7.1.2 (September 2008)
6014                  * Clear bit "block by NMI" before VM entry if a NMI
6015                  * delivery faulted.
6016                  */
6017                 vmx_set_nmi_mask(&vmx->vcpu, false);
6018                 break;
6019         case INTR_TYPE_SOFT_EXCEPTION:
6020                 vmx->vcpu.arch.event_exit_inst_len =
6021                         vmcs_read32(instr_len_field);
6022                 /* fall through */
6023         case INTR_TYPE_HARD_EXCEPTION:
6024                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6025                         u32 err = vmcs_read32(error_code_field);
6026                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6027                 } else
6028                         kvm_queue_exception(&vmx->vcpu, vector);
6029                 break;
6030         case INTR_TYPE_SOFT_INTR:
6031                 vmx->vcpu.arch.event_exit_inst_len =
6032                         vmcs_read32(instr_len_field);
6033                 /* fall through */
6034         case INTR_TYPE_EXT_INTR:
6035                 kvm_queue_interrupt(&vmx->vcpu, vector,
6036                         type == INTR_TYPE_SOFT_INTR);
6037                 break;
6038         default:
6039                 break;
6040         }
6041 }
6042
6043 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6044 {
6045         if (is_guest_mode(&vmx->vcpu))
6046                 return;
6047         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6048                                   VM_EXIT_INSTRUCTION_LEN,
6049                                   IDT_VECTORING_ERROR_CODE);
6050 }
6051
6052 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6053 {
6054         if (is_guest_mode(vcpu))
6055                 return;
6056         __vmx_complete_interrupts(to_vmx(vcpu),
6057                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6058                                   VM_ENTRY_INSTRUCTION_LEN,
6059                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6060
6061         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6062 }
6063
6064 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6065 {
6066         int i, nr_msrs;
6067         struct perf_guest_switch_msr *msrs;
6068
6069         msrs = perf_guest_get_msrs(&nr_msrs);
6070
6071         if (!msrs)
6072                 return;
6073
6074         for (i = 0; i < nr_msrs; i++)
6075                 if (msrs[i].host == msrs[i].guest)
6076                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6077                 else
6078                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6079                                         msrs[i].host);
6080 }
6081
6082 #ifdef CONFIG_X86_64
6083 #define R "r"
6084 #define Q "q"
6085 #else
6086 #define R "e"
6087 #define Q "l"
6088 #endif
6089
6090 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6091 {
6092         struct vcpu_vmx *vmx = to_vmx(vcpu);
6093
6094         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6095                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6096                 if (vmcs12->idt_vectoring_info_field &
6097                                 VECTORING_INFO_VALID_MASK) {
6098                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6099                                 vmcs12->idt_vectoring_info_field);
6100                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6101                                 vmcs12->vm_exit_instruction_len);
6102                         if (vmcs12->idt_vectoring_info_field &
6103                                         VECTORING_INFO_DELIVER_CODE_MASK)
6104                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6105                                         vmcs12->idt_vectoring_error_code);
6106                 }
6107         }
6108
6109         /* Record the guest's net vcpu time for enforced NMI injections. */
6110         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6111                 vmx->entry_time = ktime_get();
6112
6113         /* Don't enter VMX if guest state is invalid, let the exit handler
6114            start emulation until we arrive back to a valid state */
6115         if (vmx->emulation_required && emulate_invalid_guest_state)
6116                 return;
6117
6118         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6119                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6120         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6121                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6122
6123         /* When single-stepping over STI and MOV SS, we must clear the
6124          * corresponding interruptibility bits in the guest state. Otherwise
6125          * vmentry fails as it then expects bit 14 (BS) in pending debug
6126          * exceptions being set, but that's not correct for the guest debugging
6127          * case. */
6128         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6129                 vmx_set_interrupt_shadow(vcpu, 0);
6130
6131         atomic_switch_perf_msrs(vmx);
6132
6133         vmx->__launched = vmx->loaded_vmcs->launched;
6134         asm(
6135                 /* Store host registers */
6136                 "push %%"R"dx; push %%"R"bp;"
6137                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6138                 "push %%"R"cx \n\t"
6139                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6140                 "je 1f \n\t"
6141                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6142                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6143                 "1: \n\t"
6144                 /* Reload cr2 if changed */
6145                 "mov %c[cr2](%0), %%"R"ax \n\t"
6146                 "mov %%cr2, %%"R"dx \n\t"
6147                 "cmp %%"R"ax, %%"R"dx \n\t"
6148                 "je 2f \n\t"
6149                 "mov %%"R"ax, %%cr2 \n\t"
6150                 "2: \n\t"
6151                 /* Check if vmlaunch of vmresume is needed */
6152                 "cmpl $0, %c[launched](%0) \n\t"
6153                 /* Load guest registers.  Don't clobber flags. */
6154                 "mov %c[rax](%0), %%"R"ax \n\t"
6155                 "mov %c[rbx](%0), %%"R"bx \n\t"
6156                 "mov %c[rdx](%0), %%"R"dx \n\t"
6157                 "mov %c[rsi](%0), %%"R"si \n\t"
6158                 "mov %c[rdi](%0), %%"R"di \n\t"
6159                 "mov %c[rbp](%0), %%"R"bp \n\t"
6160 #ifdef CONFIG_X86_64
6161                 "mov %c[r8](%0),  %%r8  \n\t"
6162                 "mov %c[r9](%0),  %%r9  \n\t"
6163                 "mov %c[r10](%0), %%r10 \n\t"
6164                 "mov %c[r11](%0), %%r11 \n\t"
6165                 "mov %c[r12](%0), %%r12 \n\t"
6166                 "mov %c[r13](%0), %%r13 \n\t"
6167                 "mov %c[r14](%0), %%r14 \n\t"
6168                 "mov %c[r15](%0), %%r15 \n\t"
6169 #endif
6170                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6171
6172                 /* Enter guest mode */
6173                 "jne .Llaunched \n\t"
6174                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6175                 "jmp .Lkvm_vmx_return \n\t"
6176                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6177                 ".Lkvm_vmx_return: "
6178                 /* Save guest registers, load host registers, keep flags */
6179                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6180                 "pop %0 \n\t"
6181                 "mov %%"R"ax, %c[rax](%0) \n\t"
6182                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6183                 "pop"Q" %c[rcx](%0) \n\t"
6184                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6185                 "mov %%"R"si, %c[rsi](%0) \n\t"
6186                 "mov %%"R"di, %c[rdi](%0) \n\t"
6187                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6188 #ifdef CONFIG_X86_64
6189                 "mov %%r8,  %c[r8](%0) \n\t"
6190                 "mov %%r9,  %c[r9](%0) \n\t"
6191                 "mov %%r10, %c[r10](%0) \n\t"
6192                 "mov %%r11, %c[r11](%0) \n\t"
6193                 "mov %%r12, %c[r12](%0) \n\t"
6194                 "mov %%r13, %c[r13](%0) \n\t"
6195                 "mov %%r14, %c[r14](%0) \n\t"
6196                 "mov %%r15, %c[r15](%0) \n\t"
6197 #endif
6198                 "mov %%cr2, %%"R"ax   \n\t"
6199                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6200
6201                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6202                 "setbe %c[fail](%0) \n\t"
6203               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6204                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6205                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6206                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6207                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6208                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6209                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6210                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6211                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6212                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6213                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6214 #ifdef CONFIG_X86_64
6215                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6216                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6217                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6218                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6219                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6220                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6221                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6222                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6223 #endif
6224                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6225                 [wordsize]"i"(sizeof(ulong))
6226               : "cc", "memory"
6227                 , R"ax", R"bx", R"di", R"si"
6228 #ifdef CONFIG_X86_64
6229                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6230 #endif
6231               );
6232
6233         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6234                                   | (1 << VCPU_EXREG_RFLAGS)
6235                                   | (1 << VCPU_EXREG_CPL)
6236                                   | (1 << VCPU_EXREG_PDPTR)
6237                                   | (1 << VCPU_EXREG_SEGMENTS)
6238                                   | (1 << VCPU_EXREG_CR3));
6239         vcpu->arch.regs_dirty = 0;
6240
6241         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6242
6243         if (is_guest_mode(vcpu)) {
6244                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6245                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6246                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6247                         vmcs12->idt_vectoring_error_code =
6248                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6249                         vmcs12->vm_exit_instruction_len =
6250                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6251                 }
6252         }
6253
6254         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6255         vmx->loaded_vmcs->launched = 1;
6256
6257         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6258         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6259
6260         vmx_complete_atomic_exit(vmx);
6261         vmx_recover_nmi_blocking(vmx);
6262         vmx_complete_interrupts(vmx);
6263 }
6264
6265 #undef R
6266 #undef Q
6267
6268 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6269 {
6270         struct vcpu_vmx *vmx = to_vmx(vcpu);
6271
6272         free_vpid(vmx);
6273         free_nested(vmx);
6274         free_loaded_vmcs(vmx->loaded_vmcs);
6275         kfree(vmx->guest_msrs);
6276         kvm_vcpu_uninit(vcpu);
6277         kmem_cache_free(kvm_vcpu_cache, vmx);
6278 }
6279
6280 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6281 {
6282         int err;
6283         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6284         int cpu;
6285
6286         if (!vmx)
6287                 return ERR_PTR(-ENOMEM);
6288
6289         allocate_vpid(vmx);
6290
6291         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6292         if (err)
6293                 goto free_vcpu;
6294
6295         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6296         err = -ENOMEM;
6297         if (!vmx->guest_msrs) {
6298                 goto uninit_vcpu;
6299         }
6300
6301         vmx->loaded_vmcs = &vmx->vmcs01;
6302         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6303         if (!vmx->loaded_vmcs->vmcs)
6304                 goto free_msrs;
6305         if (!vmm_exclusive)
6306                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6307         loaded_vmcs_init(vmx->loaded_vmcs);
6308         if (!vmm_exclusive)
6309                 kvm_cpu_vmxoff();
6310
6311         cpu = get_cpu();
6312         vmx_vcpu_load(&vmx->vcpu, cpu);
6313         vmx->vcpu.cpu = cpu;
6314         err = vmx_vcpu_setup(vmx);
6315         vmx_vcpu_put(&vmx->vcpu);
6316         put_cpu();
6317         if (err)
6318                 goto free_vmcs;
6319         if (vm_need_virtualize_apic_accesses(kvm))
6320                 err = alloc_apic_access_page(kvm);
6321                 if (err)
6322                         goto free_vmcs;
6323
6324         if (enable_ept) {
6325                 if (!kvm->arch.ept_identity_map_addr)
6326                         kvm->arch.ept_identity_map_addr =
6327                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6328                 err = -ENOMEM;
6329                 if (alloc_identity_pagetable(kvm) != 0)
6330                         goto free_vmcs;
6331                 if (!init_rmode_identity_map(kvm))
6332                         goto free_vmcs;
6333         }
6334
6335         vmx->nested.current_vmptr = -1ull;
6336         vmx->nested.current_vmcs12 = NULL;
6337
6338         return &vmx->vcpu;
6339
6340 free_vmcs:
6341         free_vmcs(vmx->loaded_vmcs->vmcs);
6342 free_msrs:
6343         kfree(vmx->guest_msrs);
6344 uninit_vcpu:
6345         kvm_vcpu_uninit(&vmx->vcpu);
6346 free_vcpu:
6347         free_vpid(vmx);
6348         kmem_cache_free(kvm_vcpu_cache, vmx);
6349         return ERR_PTR(err);
6350 }
6351
6352 static void __init vmx_check_processor_compat(void *rtn)
6353 {
6354         struct vmcs_config vmcs_conf;
6355
6356         *(int *)rtn = 0;
6357         if (setup_vmcs_config(&vmcs_conf) < 0)
6358                 *(int *)rtn = -EIO;
6359         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6360                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6361                                 smp_processor_id());
6362                 *(int *)rtn = -EIO;
6363         }
6364 }
6365
6366 static int get_ept_level(void)
6367 {
6368         return VMX_EPT_DEFAULT_GAW + 1;
6369 }
6370
6371 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6372 {
6373         u64 ret;
6374
6375         /* For VT-d and EPT combination
6376          * 1. MMIO: always map as UC
6377          * 2. EPT with VT-d:
6378          *   a. VT-d without snooping control feature: can't guarantee the
6379          *      result, try to trust guest.
6380          *   b. VT-d with snooping control feature: snooping control feature of
6381          *      VT-d engine can guarantee the cache correctness. Just set it
6382          *      to WB to keep consistent with host. So the same as item 3.
6383          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6384          *    consistent with host MTRR
6385          */
6386         if (is_mmio)
6387                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6388         else if (vcpu->kvm->arch.iommu_domain &&
6389                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6390                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6391                       VMX_EPT_MT_EPTE_SHIFT;
6392         else
6393                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6394                         | VMX_EPT_IPAT_BIT;
6395
6396         return ret;
6397 }
6398
6399 static int vmx_get_lpage_level(void)
6400 {
6401         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6402                 return PT_DIRECTORY_LEVEL;
6403         else
6404                 /* For shadow and EPT supported 1GB page */
6405                 return PT_PDPE_LEVEL;
6406 }
6407
6408 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6409 {
6410         struct kvm_cpuid_entry2 *best;
6411         struct vcpu_vmx *vmx = to_vmx(vcpu);
6412         u32 exec_control;
6413
6414         vmx->rdtscp_enabled = false;
6415         if (vmx_rdtscp_supported()) {
6416                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6417                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6418                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6419                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6420                                 vmx->rdtscp_enabled = true;
6421                         else {
6422                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6423                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6424                                                 exec_control);
6425                         }
6426                 }
6427         }
6428 }
6429
6430 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6431 {
6432         if (func == 1 && nested)
6433                 entry->ecx |= bit(X86_FEATURE_VMX);
6434 }
6435
6436 /*
6437  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6438  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6439  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6440  * guest in a way that will both be appropriate to L1's requests, and our
6441  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6442  * function also has additional necessary side-effects, like setting various
6443  * vcpu->arch fields.
6444  */
6445 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6446 {
6447         struct vcpu_vmx *vmx = to_vmx(vcpu);
6448         u32 exec_control;
6449
6450         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6451         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6452         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6453         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6454         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6455         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6456         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6457         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6458         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6459         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6460         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6461         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6462         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6463         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6464         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6465         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6466         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6467         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6468         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6469         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6470         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6471         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6472         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6473         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6474         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6475         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6476         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6477         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6478         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6479         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6480         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6481         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6482         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6483         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6484         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6485         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6486
6487         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6488         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6489                 vmcs12->vm_entry_intr_info_field);
6490         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6491                 vmcs12->vm_entry_exception_error_code);
6492         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6493                 vmcs12->vm_entry_instruction_len);
6494         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6495                 vmcs12->guest_interruptibility_info);
6496         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6497         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6498         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6499         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6500         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6501                 vmcs12->guest_pending_dbg_exceptions);
6502         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6503         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6504
6505         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6506
6507         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6508                 (vmcs_config.pin_based_exec_ctrl |
6509                  vmcs12->pin_based_vm_exec_control));
6510
6511         /*
6512          * Whether page-faults are trapped is determined by a combination of
6513          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6514          * If enable_ept, L0 doesn't care about page faults and we should
6515          * set all of these to L1's desires. However, if !enable_ept, L0 does
6516          * care about (at least some) page faults, and because it is not easy
6517          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6518          * to exit on each and every L2 page fault. This is done by setting
6519          * MASK=MATCH=0 and (see below) EB.PF=1.
6520          * Note that below we don't need special code to set EB.PF beyond the
6521          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6522          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6523          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6524          *
6525          * A problem with this approach (when !enable_ept) is that L1 may be
6526          * injected with more page faults than it asked for. This could have
6527          * caused problems, but in practice existing hypervisors don't care.
6528          * To fix this, we will need to emulate the PFEC checking (on the L1
6529          * page tables), using walk_addr(), when injecting PFs to L1.
6530          */
6531         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6532                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6533         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6534                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6535
6536         if (cpu_has_secondary_exec_ctrls()) {
6537                 u32 exec_control = vmx_secondary_exec_control(vmx);
6538                 if (!vmx->rdtscp_enabled)
6539                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6540                 /* Take the following fields only from vmcs12 */
6541                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6542                 if (nested_cpu_has(vmcs12,
6543                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6544                         exec_control |= vmcs12->secondary_vm_exec_control;
6545
6546                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6547                         /*
6548                          * Translate L1 physical address to host physical
6549                          * address for vmcs02. Keep the page pinned, so this
6550                          * physical address remains valid. We keep a reference
6551                          * to it so we can release it later.
6552                          */
6553                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6554                                 nested_release_page(vmx->nested.apic_access_page);
6555                         vmx->nested.apic_access_page =
6556                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6557                         /*
6558                          * If translation failed, no matter: This feature asks
6559                          * to exit when accessing the given address, and if it
6560                          * can never be accessed, this feature won't do
6561                          * anything anyway.
6562                          */
6563                         if (!vmx->nested.apic_access_page)
6564                                 exec_control &=
6565                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6566                         else
6567                                 vmcs_write64(APIC_ACCESS_ADDR,
6568                                   page_to_phys(vmx->nested.apic_access_page));
6569                 }
6570
6571                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6572         }
6573
6574
6575         /*
6576          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6577          * Some constant fields are set here by vmx_set_constant_host_state().
6578          * Other fields are different per CPU, and will be set later when
6579          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6580          */
6581         vmx_set_constant_host_state();
6582
6583         /*
6584          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6585          * entry, but only if the current (host) sp changed from the value
6586          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6587          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6588          * here we just force the write to happen on entry.
6589          */
6590         vmx->host_rsp = 0;
6591
6592         exec_control = vmx_exec_control(vmx); /* L0's desires */
6593         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6594         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6595         exec_control &= ~CPU_BASED_TPR_SHADOW;
6596         exec_control |= vmcs12->cpu_based_vm_exec_control;
6597         /*
6598          * Merging of IO and MSR bitmaps not currently supported.
6599          * Rather, exit every time.
6600          */
6601         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6602         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6603         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6604
6605         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6606
6607         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6608          * bitwise-or of what L1 wants to trap for L2, and what we want to
6609          * trap. Note that CR0.TS also needs updating - we do this later.
6610          */
6611         update_exception_bitmap(vcpu);
6612         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6613         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6614
6615         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6616         vmcs_write32(VM_EXIT_CONTROLS,
6617                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6618         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6619                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6620
6621         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6622                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6623         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6624                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6625
6626
6627         set_cr4_guest_host_mask(vmx);
6628
6629         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6630                 vmcs_write64(TSC_OFFSET,
6631                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6632         else
6633                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6634
6635         if (enable_vpid) {
6636                 /*
6637                  * Trivially support vpid by letting L2s share their parent
6638                  * L1's vpid. TODO: move to a more elaborate solution, giving
6639                  * each L2 its own vpid and exposing the vpid feature to L1.
6640                  */
6641                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6642                 vmx_flush_tlb(vcpu);
6643         }
6644
6645         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6646                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6647         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6648                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6649         else
6650                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6651         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6652         vmx_set_efer(vcpu, vcpu->arch.efer);
6653
6654         /*
6655          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6656          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6657          * The CR0_READ_SHADOW is what L2 should have expected to read given
6658          * the specifications by L1; It's not enough to take
6659          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6660          * have more bits than L1 expected.
6661          */
6662         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6663         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6664
6665         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6666         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6667
6668         /* shadow page tables on either EPT or shadow page tables */
6669         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6670         kvm_mmu_reset_context(vcpu);
6671
6672         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6673         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6674 }
6675
6676 /*
6677  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6678  * for running an L2 nested guest.
6679  */
6680 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6681 {
6682         struct vmcs12 *vmcs12;
6683         struct vcpu_vmx *vmx = to_vmx(vcpu);
6684         int cpu;
6685         struct loaded_vmcs *vmcs02;
6686
6687         if (!nested_vmx_check_permission(vcpu) ||
6688             !nested_vmx_check_vmcs12(vcpu))
6689                 return 1;
6690
6691         skip_emulated_instruction(vcpu);
6692         vmcs12 = get_vmcs12(vcpu);
6693
6694         /*
6695          * The nested entry process starts with enforcing various prerequisites
6696          * on vmcs12 as required by the Intel SDM, and act appropriately when
6697          * they fail: As the SDM explains, some conditions should cause the
6698          * instruction to fail, while others will cause the instruction to seem
6699          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6700          * To speed up the normal (success) code path, we should avoid checking
6701          * for misconfigurations which will anyway be caught by the processor
6702          * when using the merged vmcs02.
6703          */
6704         if (vmcs12->launch_state == launch) {
6705                 nested_vmx_failValid(vcpu,
6706                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6707                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6708                 return 1;
6709         }
6710
6711         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6712                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6713                 /*TODO: Also verify bits beyond physical address width are 0*/
6714                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6715                 return 1;
6716         }
6717
6718         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6719                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6720                 /*TODO: Also verify bits beyond physical address width are 0*/
6721                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6722                 return 1;
6723         }
6724
6725         if (vmcs12->vm_entry_msr_load_count > 0 ||
6726             vmcs12->vm_exit_msr_load_count > 0 ||
6727             vmcs12->vm_exit_msr_store_count > 0) {
6728                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6729                                     __func__);
6730                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6731                 return 1;
6732         }
6733
6734         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6735               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6736             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6737               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6738             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6739               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6740             !vmx_control_verify(vmcs12->vm_exit_controls,
6741               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6742             !vmx_control_verify(vmcs12->vm_entry_controls,
6743               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6744         {
6745                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6746                 return 1;
6747         }
6748
6749         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6750             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6751                 nested_vmx_failValid(vcpu,
6752                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6753                 return 1;
6754         }
6755
6756         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6757             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6758                 nested_vmx_entry_failure(vcpu, vmcs12,
6759                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6760                 return 1;
6761         }
6762         if (vmcs12->vmcs_link_pointer != -1ull) {
6763                 nested_vmx_entry_failure(vcpu, vmcs12,
6764                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6765                 return 1;
6766         }
6767
6768         /*
6769          * We're finally done with prerequisite checking, and can start with
6770          * the nested entry.
6771          */
6772
6773         vmcs02 = nested_get_current_vmcs02(vmx);
6774         if (!vmcs02)
6775                 return -ENOMEM;
6776
6777         enter_guest_mode(vcpu);
6778
6779         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6780
6781         cpu = get_cpu();
6782         vmx->loaded_vmcs = vmcs02;
6783         vmx_vcpu_put(vcpu);
6784         vmx_vcpu_load(vcpu, cpu);
6785         vcpu->cpu = cpu;
6786         put_cpu();
6787
6788         vmcs12->launch_state = 1;
6789
6790         prepare_vmcs02(vcpu, vmcs12);
6791
6792         /*
6793          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6794          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6795          * returned as far as L1 is concerned. It will only return (and set
6796          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6797          */
6798         return 1;
6799 }
6800
6801 /*
6802  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6803  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6804  * This function returns the new value we should put in vmcs12.guest_cr0.
6805  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6806  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6807  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6808  *     didn't trap the bit, because if L1 did, so would L0).
6809  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6810  *     been modified by L2, and L1 knows it. So just leave the old value of
6811  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6812  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6813  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6814  *     changed these bits, and therefore they need to be updated, but L0
6815  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6816  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6817  */
6818 static inline unsigned long
6819 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6820 {
6821         return
6822         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6823         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6824         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6825                         vcpu->arch.cr0_guest_owned_bits));
6826 }
6827
6828 static inline unsigned long
6829 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6830 {
6831         return
6832         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6833         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6834         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6835                         vcpu->arch.cr4_guest_owned_bits));
6836 }
6837
6838 /*
6839  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6840  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6841  * and this function updates it to reflect the changes to the guest state while
6842  * L2 was running (and perhaps made some exits which were handled directly by L0
6843  * without going back to L1), and to reflect the exit reason.
6844  * Note that we do not have to copy here all VMCS fields, just those that
6845  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6846  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6847  * which already writes to vmcs12 directly.
6848  */
6849 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6850 {
6851         /* update guest state fields: */
6852         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6853         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6854
6855         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6856         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6857         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6858         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6859
6860         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6861         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6862         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6863         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6864         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6865         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6866         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6867         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6868         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6869         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6870         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6871         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6872         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6873         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6874         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6875         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6876         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6877         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6878         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6879         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6880         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6881         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6882         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6883         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6884         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6885         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6886         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6887         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6888         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6889         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6890         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6891         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6892         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6893         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6894         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6895         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6896
6897         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6898         vmcs12->guest_interruptibility_info =
6899                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6900         vmcs12->guest_pending_dbg_exceptions =
6901                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6902
6903         /* TODO: These cannot have changed unless we have MSR bitmaps and
6904          * the relevant bit asks not to trap the change */
6905         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6906         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6907                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6908         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6909         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6910         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6911
6912         /* update exit information fields: */
6913
6914         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
6915         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6916
6917         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6918         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6919         vmcs12->idt_vectoring_info_field =
6920                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6921         vmcs12->idt_vectoring_error_code =
6922                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6923         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6924         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6925
6926         /* clear vm-entry fields which are to be cleared on exit */
6927         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6928                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6929 }
6930
6931 /*
6932  * A part of what we need to when the nested L2 guest exits and we want to
6933  * run its L1 parent, is to reset L1's guest state to the host state specified
6934  * in vmcs12.
6935  * This function is to be called not only on normal nested exit, but also on
6936  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6937  * Failures During or After Loading Guest State").
6938  * This function should be called when the active VMCS is L1's (vmcs01).
6939  */
6940 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6941 {
6942         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6943                 vcpu->arch.efer = vmcs12->host_ia32_efer;
6944         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6945                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6946         else
6947                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6948         vmx_set_efer(vcpu, vcpu->arch.efer);
6949
6950         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6951         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6952         /*
6953          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6954          * actually changed, because it depends on the current state of
6955          * fpu_active (which may have changed).
6956          * Note that vmx_set_cr0 refers to efer set above.
6957          */
6958         kvm_set_cr0(vcpu, vmcs12->host_cr0);
6959         /*
6960          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6961          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6962          * but we also need to update cr0_guest_host_mask and exception_bitmap.
6963          */
6964         update_exception_bitmap(vcpu);
6965         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6966         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6967
6968         /*
6969          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6970          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6971          */
6972         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6973         kvm_set_cr4(vcpu, vmcs12->host_cr4);
6974
6975         /* shadow page tables on either EPT or shadow page tables */
6976         kvm_set_cr3(vcpu, vmcs12->host_cr3);
6977         kvm_mmu_reset_context(vcpu);
6978
6979         if (enable_vpid) {
6980                 /*
6981                  * Trivially support vpid by letting L2s share their parent
6982                  * L1's vpid. TODO: move to a more elaborate solution, giving
6983                  * each L2 its own vpid and exposing the vpid feature to L1.
6984                  */
6985                 vmx_flush_tlb(vcpu);
6986         }
6987
6988
6989         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6990         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6991         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6992         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6993         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6994         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6995         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6996         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6997         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6998         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6999         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7000         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7001         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7002         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7003         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7004
7005         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7006                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7007         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7008                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7009                         vmcs12->host_ia32_perf_global_ctrl);
7010 }
7011
7012 /*
7013  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7014  * and modify vmcs12 to make it see what it would expect to see there if
7015  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7016  */
7017 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7018 {
7019         struct vcpu_vmx *vmx = to_vmx(vcpu);
7020         int cpu;
7021         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7022
7023         leave_guest_mode(vcpu);
7024         prepare_vmcs12(vcpu, vmcs12);
7025
7026         cpu = get_cpu();
7027         vmx->loaded_vmcs = &vmx->vmcs01;
7028         vmx_vcpu_put(vcpu);
7029         vmx_vcpu_load(vcpu, cpu);
7030         vcpu->cpu = cpu;
7031         put_cpu();
7032
7033         /* if no vmcs02 cache requested, remove the one we used */
7034         if (VMCS02_POOL_SIZE == 0)
7035                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7036
7037         load_vmcs12_host_state(vcpu, vmcs12);
7038
7039         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7040         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7041
7042         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7043         vmx->host_rsp = 0;
7044
7045         /* Unpin physical memory we referred to in vmcs02 */
7046         if (vmx->nested.apic_access_page) {
7047                 nested_release_page(vmx->nested.apic_access_page);
7048                 vmx->nested.apic_access_page = 0;
7049         }
7050
7051         /*
7052          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7053          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7054          * success or failure flag accordingly.
7055          */
7056         if (unlikely(vmx->fail)) {
7057                 vmx->fail = 0;
7058                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7059         } else
7060                 nested_vmx_succeed(vcpu);
7061 }
7062
7063 /*
7064  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7065  * 23.7 "VM-entry failures during or after loading guest state" (this also
7066  * lists the acceptable exit-reason and exit-qualification parameters).
7067  * It should only be called before L2 actually succeeded to run, and when
7068  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7069  */
7070 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7071                         struct vmcs12 *vmcs12,
7072                         u32 reason, unsigned long qualification)
7073 {
7074         load_vmcs12_host_state(vcpu, vmcs12);
7075         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7076         vmcs12->exit_qualification = qualification;
7077         nested_vmx_succeed(vcpu);
7078 }
7079
7080 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7081                                struct x86_instruction_info *info,
7082                                enum x86_intercept_stage stage)
7083 {
7084         return X86EMUL_CONTINUE;
7085 }
7086
7087 static struct kvm_x86_ops vmx_x86_ops = {
7088         .cpu_has_kvm_support = cpu_has_kvm_support,
7089         .disabled_by_bios = vmx_disabled_by_bios,
7090         .hardware_setup = hardware_setup,
7091         .hardware_unsetup = hardware_unsetup,
7092         .check_processor_compatibility = vmx_check_processor_compat,
7093         .hardware_enable = hardware_enable,
7094         .hardware_disable = hardware_disable,
7095         .cpu_has_accelerated_tpr = report_flexpriority,
7096
7097         .vcpu_create = vmx_create_vcpu,
7098         .vcpu_free = vmx_free_vcpu,
7099         .vcpu_reset = vmx_vcpu_reset,
7100
7101         .prepare_guest_switch = vmx_save_host_state,
7102         .vcpu_load = vmx_vcpu_load,
7103         .vcpu_put = vmx_vcpu_put,
7104
7105         .set_guest_debug = set_guest_debug,
7106         .get_msr = vmx_get_msr,
7107         .set_msr = vmx_set_msr,
7108         .get_segment_base = vmx_get_segment_base,
7109         .get_segment = vmx_get_segment,
7110         .set_segment = vmx_set_segment,
7111         .get_cpl = vmx_get_cpl,
7112         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7113         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7114         .decache_cr3 = vmx_decache_cr3,
7115         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7116         .set_cr0 = vmx_set_cr0,
7117         .set_cr3 = vmx_set_cr3,
7118         .set_cr4 = vmx_set_cr4,
7119         .set_efer = vmx_set_efer,
7120         .get_idt = vmx_get_idt,
7121         .set_idt = vmx_set_idt,
7122         .get_gdt = vmx_get_gdt,
7123         .set_gdt = vmx_set_gdt,
7124         .set_dr7 = vmx_set_dr7,
7125         .cache_reg = vmx_cache_reg,
7126         .get_rflags = vmx_get_rflags,
7127         .set_rflags = vmx_set_rflags,
7128         .fpu_activate = vmx_fpu_activate,
7129         .fpu_deactivate = vmx_fpu_deactivate,
7130
7131         .tlb_flush = vmx_flush_tlb,
7132
7133         .run = vmx_vcpu_run,
7134         .handle_exit = vmx_handle_exit,
7135         .skip_emulated_instruction = skip_emulated_instruction,
7136         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7137         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7138         .patch_hypercall = vmx_patch_hypercall,
7139         .set_irq = vmx_inject_irq,
7140         .set_nmi = vmx_inject_nmi,
7141         .queue_exception = vmx_queue_exception,
7142         .cancel_injection = vmx_cancel_injection,
7143         .interrupt_allowed = vmx_interrupt_allowed,
7144         .nmi_allowed = vmx_nmi_allowed,
7145         .get_nmi_mask = vmx_get_nmi_mask,
7146         .set_nmi_mask = vmx_set_nmi_mask,
7147         .enable_nmi_window = enable_nmi_window,
7148         .enable_irq_window = enable_irq_window,
7149         .update_cr8_intercept = update_cr8_intercept,
7150
7151         .set_tss_addr = vmx_set_tss_addr,
7152         .get_tdp_level = get_ept_level,
7153         .get_mt_mask = vmx_get_mt_mask,
7154
7155         .get_exit_info = vmx_get_exit_info,
7156
7157         .get_lpage_level = vmx_get_lpage_level,
7158
7159         .cpuid_update = vmx_cpuid_update,
7160
7161         .rdtscp_supported = vmx_rdtscp_supported,
7162
7163         .set_supported_cpuid = vmx_set_supported_cpuid,
7164
7165         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7166
7167         .set_tsc_khz = vmx_set_tsc_khz,
7168         .write_tsc_offset = vmx_write_tsc_offset,
7169         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7170         .compute_tsc_offset = vmx_compute_tsc_offset,
7171         .read_l1_tsc = vmx_read_l1_tsc,
7172
7173         .set_tdp_cr3 = vmx_set_cr3,
7174
7175         .check_intercept = vmx_check_intercept,
7176 };
7177
7178 static int __init vmx_init(void)
7179 {
7180         int r, i;
7181
7182         rdmsrl_safe(MSR_EFER, &host_efer);
7183
7184         for (i = 0; i < NR_VMX_MSR; ++i)
7185                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7186
7187         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7188         if (!vmx_io_bitmap_a)
7189                 return -ENOMEM;
7190
7191         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7192         if (!vmx_io_bitmap_b) {
7193                 r = -ENOMEM;
7194                 goto out;
7195         }
7196
7197         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7198         if (!vmx_msr_bitmap_legacy) {
7199                 r = -ENOMEM;
7200                 goto out1;
7201         }
7202
7203         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7204         if (!vmx_msr_bitmap_longmode) {
7205                 r = -ENOMEM;
7206                 goto out2;
7207         }
7208
7209         /*
7210          * Allow direct access to the PC debug port (it is often used for I/O
7211          * delays, but the vmexits simply slow things down).
7212          */
7213         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7214         clear_bit(0x80, vmx_io_bitmap_a);
7215
7216         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7217
7218         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7219         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7220
7221         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7222
7223         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7224                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7225         if (r)
7226                 goto out3;
7227
7228         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7229         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7230         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7231         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7232         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7233         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7234
7235         if (enable_ept) {
7236                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7237                                 VMX_EPT_EXECUTABLE_MASK);
7238                 ept_set_mmio_spte_mask();
7239                 kvm_enable_tdp();
7240         } else
7241                 kvm_disable_tdp();
7242
7243         return 0;
7244
7245 out3:
7246         free_page((unsigned long)vmx_msr_bitmap_longmode);
7247 out2:
7248         free_page((unsigned long)vmx_msr_bitmap_legacy);
7249 out1:
7250         free_page((unsigned long)vmx_io_bitmap_b);
7251 out:
7252         free_page((unsigned long)vmx_io_bitmap_a);
7253         return r;
7254 }
7255
7256 static void __exit vmx_exit(void)
7257 {
7258         free_page((unsigned long)vmx_msr_bitmap_legacy);
7259         free_page((unsigned long)vmx_msr_bitmap_longmode);
7260         free_page((unsigned long)vmx_io_bitmap_b);
7261         free_page((unsigned long)vmx_io_bitmap_a);
7262
7263         kvm_exit();
7264 }
7265
7266 module_init(vmx_init)
7267 module_exit(vmx_exit)